Electronics Manufacturing with Lead-Free Halogen-Free and Conductive-Adhesive

ELECTRONICS MANUFACTURING WITH LEAD-FREE, HALOGEN-FREE, AND CONDUCTIVE-ADHESIVE MATERIALS

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ELECTRONICS MANUFACTURING WITH LEAD-FREE, HALOGEN-FREE, AND CONDUCTIVE-ADHESIVE MATERIALS

John H. Lau Agilent Technologies, Inc.

C. P. Wong Georgia Institute of Technology

Ning-Cheng Lee Indium Corporation of America

S. W. Ricky Lee Hong Kong University of Science and Technology

Copyright © 2003 by The McGraw-Hill Companies, Inc. All rights reserved. Manufactured in the United States of America. Except as permitted under the United States Copyright Act of 1976, no part of this publication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system, without the prior written permission of the publisher. 0-07-150087-1 The material in this eBook also appears in the print version of this title: 0-07-138624-6. All trademarks are trademarks of their respective owners. Rather than put a trademark symbol after every occurrence of a trademarked name, we use names in an editorial fashion only, and to the benefit of the trademark owner, with no intention of infringement of the trademark. Where such designations appear in this book, they have been printed with initial caps. McGraw-Hill eBooks are available at special quantity discounts to use as premiums and sales promotions, or for use in corporate training programs. For more information, please contact George Hoare, Special Sales, at [email protected] or (212) 904-4069. TERMS OF USE This is a copyrighted work and The McGraw-Hill Companies, Inc. (“McGraw-Hill”) and its licensors reserve all rights in and to the work. Use of this work is subject to these terms. Except as permitted under the Copyright Act of 1976 and the right to store and retrieve one copy of the work, you may not decompile, disassemble, reverse engineer, reproduce, modify, create derivative works based upon, transmit, distribute, disseminate, sell, publish or sublicense the work or any part of it without McGraw-Hill’s prior consent. You may use the work for your own noncommercial and personal use; any other use of the work is strictly prohibited. Your right to use the work may be terminated if you fail to comply with these terms. THE WORK IS PROVIDED “AS IS.” McGRAW-HILL AND ITS LICENSORS MAKE NO GUARANTEES OR WARRANTIES AS TO THE ACCURACY, ADEQUACY OR COMPLETENESS OF OR RESULTS TO BE OBTAINED FROM USING THE WORK, INCLUDING ANY INFORMATION THAT CAN BE ACCESSED THROUGH THE WORK VIA HYPERLINK OR OTHERWISE, AND EXPRESSLY DISCLAIM ANY WARRANTY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. McGraw-Hill and its licensors do not warrant or guarantee that the functions contained in the work will meet your requirements or that its operation will be uninterrupted or error free. Neither McGraw-Hill nor its licensors shall be liable to you or anyone else for any inaccuracy, error or omission, regardless of cause, in the work or for any damages resulting therefrom. McGraw-Hill has no responsibility for the content of any information accessed through the work. Under no circumstances shall McGraw-Hill and/or its licensors be liable for any indirect, incidental, special, punitive, consequential or similar damages that result from the use of or inability to use the work, even if any of them has been advised of the possibility of such damages. This limitation of liability shall apply to any claim or cause whatsoever whether such claim or cause arises in contract, tort or otherwise. DOI: 10.1036/0071386246

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CONTENTS

Chapter 1. Introduction to Environmentally Benign Electronics Manufacturing 1.1

Trends in Industry

1.1.1 1.1.2 1.2

1.3

1.1

Automobile Industry Electronics Industry

1.1 1.2

Trends in Worldwide Environmentally Benign Manufacturing

1.2.1 1.2.2 1.2.3 1.2.4 1.2.5

Government Activity Industry Activity R&D Activity Education Activity Worldwide Efforts on Environmentally Benign Electronics Manufacturing

Trends in Environmentally Benign Electronics Manufacturing

1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7

IC Fabrication IC Packaging PCBs Lead-Free Solders Halogen-Free Flame Retardants Conductive Adhesives End-Of-Life Management

Acknowledgments References

Introduction UBM

2.2.1 2.2.2 2.3

2.4 2.5

Electroless Ni-P-Immersion Au UBM Al-NiV-Cu UBM Overview of Microball Wafer Bumping Microball Preparation Microball Management Microball Wafer Bumping

Sn-Ag-Cu Solder Ball Mounting on Wafers

2.4.1 2.4.2

WLCSP WLCSP with Stress-Relaxation Layer

Stencil Printing on Sn-Ag Solder on Wafers with Ni-Au UBM

2.5.1 2.5.2 2.5.3

1.4 1.4 1.5 1.5 1.6 1.6

1.9 1.9 1.9 1.10 1.11 1.12 1.13

2.1

2.1 2.1

Microball Wafer Bumping with Lead-Free Solders

2.3.1 2.3.2 2.3.3 2.3.4

1.3

1.14 1.14

Chapter 2. Chip (Wafer)-Level Interconnects with Lead-Free Solder Bumps 2.1 2.2

1.1

The Interface Between Electroless Ni and Solders Growth of the IMC and P-Rich Ni Layer Bump Shear Fracture Surface

v

2.1 2.6 2.6

2.6 2.6 2.9 2.12 2.12

2.12 2.15 2.20

2.20 2.22 2.24

vi

CONTENTS

2.6

Stencil Printing of Sn-Cu, Sn-Ag-Bi, and Sn-Ag-Cu Solders on Wafers with Ni-Au UBM

2.6.1 2.6.2 2.6.3 2.7

Stencil Printing of Sn-Cu, Sn-Ag-Bi, and Sn-Ag-Cu Solders on Wafers with Ti-Cu UBM

2.7.1 2.7.2 2.8

Interface of Reflowed Solder Bumps Interface of Annealed Solder Bumps Shear Strength of Solder Bumps Interface of Reflowed Solder Bumps Interface of Annealed Solder Bumps

Paste Printing of Solders on Wafers with Al-NiV-Cu UBM Acknowledgments References

Chapter 3. WLCSP with Lead-Free Solder Bumps on PCB/Substrate 3.1 3.2

Introduction Solder Joint Reliability of SnAgCu WLCSP with a Stress-Relaxation Layer

3.2.1 3.2.2 3.2.3 3.3

Solder Joint Reliability of SnAg and SnAgCu WLCSPs with TiCu and NiAu UBMs

3.3.1 3.3.2 3.4

Finite Element Results Thermal Cycling Results Effects of the Stress-Relaxation Layer on Capacitance Isothermal Fatigue Test Results Thermal Cycling Fatigue Test Results

Solder Joint Reliability of SnAg, SnAgCu, SnAgCuSb, and SnAgInCu WLCSPs with AlNiVCu UBM

3.4.1 3.4.2 3.4.3 3.4.4

Thermal Fatigue of SnAg, SnAgCu, SnAgCuSb and SnAgInCu WLCSPs on Ceramic Substrate Thermal Fatigue of SnAgCu WLCSP on PCB High-Temperature Storage of SnAgCu WLCSP on PCB Shear Strength of SnAgCu WLCSP on PCB

Acknowledgments References

Chapter 4. Chip (Wafer)-Level Interconnects with Solderless Bumps 4.1 4.2 4.3

Introduction Wafers for Electroless Ni-Au, Electroplated Au, and Electroplated Cu Bumps Electroless Ni-P-Immersion Au Bumps

4.3.1 4.3.2 4.4

Electroplated Au Bumps

4.4.1 4.4.2 4.5

Materials and Process Passivation Cracking Materials and Process Bump Specifications and Measurement Methods

Electroplated Cu Bumps

4.5.1 4.5.2

Materials and Process Special Considerations

2.27

2.27 2.29 2.30 2.31

2.31 2.31 2.34 2.34 2.35

3.1

3.1 3.1

3.1 3.2 3.4 3.5

3.5 3.8 3.15

3.15 3.15 3.15 3.17 3.20 3.20

4.1

4.1 4.1 4.1

4.2 4.2 4.6

4.6 4.6 4.8

4.8 4.8

CONTENTS

4.6

Electroplated Copper Wires

4.6.1 4.6.2 4.7

Wire-Bonding Microsprings

4.7.1 4.7.2 4.8

4.12

Materials and Process Equipment

4.12 4.14

Wire-Bonding Cu Stud Bumps

4.17

Materials and Process Shear Strength

Chapter 5. WLCSP with Solderless Bumps on PCB/Substrate Introduction Design, Materials, Process, and Reliability of WLCSPs with Au Bumps, Cu Bumps, and Ni-Au Bumps on PCB with ACF

5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6

4.23 4.24

5.1

5.1 5.1

5.1 5.1 5.4 5.9 5.10 5.10 5.11 5.12 5.12

5.13 5.14 5.14

5.16 5.19

Au-Stud-Bumped WLCSP with ACP/ACF on PCB

5.22

ACF/ACP with Nonconductive Fillers DSC Measurement Results DMA Measurement Results TMA Measurement Results TGA Measurement Results 85°C/85% RH Test and Results Thermal Cycling Test and Results

Au-Stud-Bumped WLCSP Diffused on Au-Plated PCB with NCA

5.8.1 5.8.2 5.9

4.21 4.23

Materials and Process Qualification Tests and Results

5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 5.7.6 5.7.7 5.8

Materials and Process Flow Equipment for SBB Technology

Au-Stud-Bumped WLCSP with ICA on Flex

5.6.1 5.6.2 5.7

PCB ACF FCOB Assemblies with ACF Thermal Cycling Test of FCOB Assemblies with ACF SIR Test Results of ACF FCOB Assemblies Summary

Copper Wired WLCSP with Solders or Adhesives on Substrates Microspring WLCSP with Solders or Adhesives on PCB/Substrate Au-Stud-Bumped WLCSP with ICA on PCB

5.5.1 5.5.2 5.6

4.10

Wire-Bonding Au Stud Bumps

Acknowledgments References

5.3 5.4 5.5

4.9 4.10 4.11 4.11

4.9.1 4.9.2

5.1 5.2

4.9

Materials and Process Special Considerations

4.8.1 4.8.2 4.9

Structure Fabrication Materials and Process

vii

Materials and Process Reliability

Au-Stud-Bumped WLCSP Diffused on Au-Plated Flex with NCA

5.9.1 5.9.2

Materials and Process Reliability

5.10 Cur-Stud-Bumped WLCSP with Lead-Free Solders on PCB

5.10.1 Materials and Process 5.10.2 Reliability Acknowledgments References

5.22 5.23 5.23 5.23 5.26 5.26 5.27 5.29

5.32 5.35 5.37

5.37 5.38 5.42

5.42 5.43 5.45 5.45

viii

CONTENTS

Chapter 6. Environmentally Benign Molding Compounds for IC Packages 6.1 6.2

Introduction Environmentally Benign Molding Compounds for PQFP Packages

6.2.1 6.2.2 6.2.3 6.2.4 6.3

Flame Resistance Systems: Addition-Type Retardants Flame Resistance Systems: Novel Resin Systems Effects of Raised Reflow Temperature on Molding Compounds Halogen-Free Molding Compounds for Lead-Free Soldering

Environmentally Benign Molding Compounds for PBGA Packages

6.3.1 Halogen-Free Flame-Retardant Agents 6.3.2 PBGA Package Warpage Controlled by Tg Dispersion 6.3.3 PBGA Package Warpage Controlled by Stress-Absorbing Agents 6.4

Environmentally Benign Molding Compounds for MAP-PBGA Packages

6.4.1 6.4.2 6.4.3 6.4.4

Halogen-Free Flame-Retardant Resins Sample Preparation Effects of Tg , Shrinkage, and Viscosity on Package Coplanarity Moisture Sensitivity Tests

Acknowledgments References

Chapter 7. Environmentally Benign Die Attach Films for IC Packaging 7.1 7.2

Introduction Environmentally Benign Die Attach Films

7.2.1 7.2.2 7.3

Silver-Filled Film DF-335-7 for Leadframe PQFP Packages Insulating Film DF-400 for BT-Substrate PBGA Packages

Environmentally Benign In-Sn Die Attach Bonding Technique

7.3.1 7.3.2 7.3.3

In-Sn Phase Diagram Design and Process of In-Sn Solder Joints Characterization of In-Sn Solder Joints

Acknowledgments References

Chapter 8. Environmental Issues for Conventional PCBs 8.1 8.2

Introduction Influence of Electronic Products

8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.3

Major Environmental Concerns Energy Issues Chemical Issues Disposal and Recycling Design for Environment

Environmental Research for the PCB Industry

8.3.1 8.3.2 8.3.3

Energy and Solvent Reduction Renewable Resins for PCB Reworkable Encapsulants for Disassembly

6.1

6.1 6.1

6.2 6.4 6.4 6.8 6.10

6.12 6.16 6.19 6.22

6.22 6.22 6.25 6.27 6.29 6.29

7.1

7.1 7.1

7.1 7.6 7.10

7.11 7.12 7.14 7.18 7.18

8.1

8.1 8.2

8.2 8.5 8.7 8.14 8.16 8.18

8.19 8.21 8.22

CONTENTS

8.4

International Driving Forces for Halogen-free Alternatives

8.4.1 8.4.2 8.4.3 8.4.4

Background and Challenge Driving Forces Material Availability Design Measures and Performance

References

Chapter 9. Halogenated and Halogen-Free Materials for Flame Retardation 9.1 9.2

Introduction Brominated Flame Retardants

9.2.1 9.2.2 9.2.3 9.3

Toxicological Aspects of Halogen-Free Flame Retardants

9.3.1 9.3.2 9.3.3 9.4

Production Aspects Classification Risk Assessment Fundamentals Denitrification Bioassay Procedures

Environmentally Conscious Flame-Retarding Plastics

9.4.1

Flame-Retardant Polycarbonate Resin

References

Chapter 10. Fabrication of Environmentally Friendly PCB 10.1 10.2

Introduction PCB DfE

10.2.1 10.2.2 10.2.3 10.2.4 10.3

Process Modeling Health Hazard Assessment Board Optimization Life Cycle Analysis (LCA)

Implementing Green PCB Manufacturing

10.3.1 Basic Processes 10.3.2 Process Modifications 10.3.3 Environmental Impact 10.4

Conformal Coating with Environmental Safety

10.4.1 10.4.2 10.4.3 10.4.4 10.4.5

Fundamentals Coating Selection Curing Methods Dispensing Methods Process Issues

References

Chapter 11. Global Status of Lead-Free Soldering 11.1 11.2 11.3 11.4 11.5 11.6

Introduction Initial Activities Recent Activities Impact of Japanese Activities U.S. Reaction What Are Lead-Free Interconnects?

ix

8.23

8.23 8.24 8.25 8.25 8.25

9.1

9.1 9.2

9.2 9.4 9.5 9.7

9.7 9.9 9.10 9.11

9.12 9.19

10.1

10.1 10.1

10.1 10.2 10.7 10.11 10.11

10.12 10.13 10.16 10.17

10.17 10.17 10.18 10.19 10.20 10.22

11.1

11.1 11.1 11.2 11.5 11.5 11.7

x

CONTENTS

11.7 11.8

Criteria for Lead-Free Solder Viable Lead-Free Alloys

11.8.1 11.8.2 11.8.3 11.8.4 11.8.5 11.8.6 11.8.7 11.8.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 11.16 11.17 11.18 11.19 11.20

Sn96.5/Ag3.5 Sn99.3/Cu0.7 SnAgCu SnAgCuX SnAgBiX SnSb SnZnX SnBi

Cost PCB Finishes Components Thermal Damage Other Concerns Consortium Activity Opinions of Consortia What Are the Selections of Pioneers? Possible Path Is Pb-Free Safe? Summary Information Resources

11.20.1 Legislation 11.20.2 Initiatives from Independent Corporations and Electronics Industry Organizations 11.20.3 Viable Alloys under Consideration References

Chapter 12. Development of Lead-Free Solder Alloys 12.1 12.2 12.3 12.4

Criteria Toxicity Cost and Availability Development of Lead-Free Alloys

12.4.1 Existing Alloys 12.4.2 Modification 12.5 12.6

Lead-Free Alloys Investigated Favorite Pb-Free Alloys

12.6.1 12.6.2 12.6.3 12.6.4 12.7 12.8

Japan Europe North America Comparison of Regional Preferences

Patent Issues Conclusion References

Chapter 13. Prevailing Lead-Free Alloys 13.1

Eutectic Sn-Ag

13.1.1 13.1.2 13.1.3 13.1.4

Physical Properties Mechanical Properties Wetting Properties Reliability

11.8 11.8

11.8 11.8 11.9 11.9 11.9 11.10 11.10 11.11 11.11 11.11 11.12 11.12 11.13 11.13 11.13 11.14 11.14 11.15 11.15 11.16

11.16 11.16 11.17 11.17 12.1

12.1 12.1 12.4 12.4

12.4 12.5 12.13 12.13

12.13 12.13 12.33 12.33 12.36 12.37 12.37 13.1

13.1

13.1 13.1 13.6 13.10

CONTENTS

13.2

Eutectic Sn-Cu

13.2.1 13.2.2 13.2.3 13.2.4 13.3

Physical Properties Mechanical Properties Wetting Properties Reliability

Sn-Ag-Bi and Sn-Ag-Bi-In

13.3.1 Physical and Mechanical Properties 13.3.2 Wetting Properties 13.3.3 Reliability 13.4

Sn-Ag-Cu and Sn-Ag-Cu-X

13.4.1 13.4.2 13.4.3 13.4.4 13.5

Sn-Zn and Sn-Zn-Bi

13.5.1 13.5.2 13.5.3 13.5.4 13.6

Physical Properties Mechanical Properties Wetting Properties Reliability Physical Properties Mechanical Properties Wetting Properties Reliability

Summary References

Chapter 14. Lead-Free Surface Finishes 14.1 14.2 14.3

Introduction Options for PCB Lead-Free Surface Finishes OSP

14.3.1 14.3.2 14.3.3 14.3.4 14.4

Benzotriazole Imidazoles Benzimidazoles Preflux

NiAu

14.4.1 Electrolytic Ni-Au 14.4.2 Electroless Ni/Immersion Au 14.4.3 Electroless Ni/Electroless (Autocatalytic) Au 14.5 14.6 14.7

Immersion Ag Immersion Bi Pd

14.7.1 Electrolytic Pd with or Without Immersion Au 14.7.2 Electroless (Autocatalytic) Pd with or Without Immersion Au 14.8 14.9

Electroless NiPd(Au Flash) NiPd(X)

14.9.1 Electrolytic NiPdCoAu Flash 14.9.2 Electroless NiPdNiAu Flash 14.10 Sn

14.10.1 Electrolytic Sn 14.10.2 Immersion Sn 14.11 Electrolytic NiSn 14.12 Sn-Bi

14.12.1 Immersion Sn-Bi Alloy 14.12.2 Electrolytic Sn-Bi Alloy 14.13 Sn-Cu (HASL)

xi

13.14

13.14 13.14 13.14 13.17 13.23

13.23 13.24 13.26 13.31

13.31 13.34 13.42 13.45 13.54

13.54 13.55 13.55 13.56 13.59 13.59

14.1

14.1 14.1 14.1

14.2 14.7 14.8 14.14 14.14

14.15 14.18 14.25 14.26 14.36 14.38

14.38 14.42 14.43 14.45

14.45 14.45 14.46

14.47 14.50 14.55 14.59

14.59 14.59 14.60

xii

CONTENTS

14.14 Electrolytic SnNi 14.15 Solid Solder Deposition (SSD)

14.15.1 14.15.2 14.15.3 14.15.4 14.15.5 14.15.6 14.15.7 14.16 14.17 14.18 14.19 14.20 14.21 14.22 14.23 14.24 14.25 14.26

HASL Optipad Sipad PPT Solder Cladding Solder Jetting Super Solder

Summary for PCB Surface Finishes Options of Component Surface Finishes NiAu (ENIG) Electrolytic Pd Electroless NiPd Electrolytic PdNi Sn Electrolytic Sn-Ag Electrolytic Sn-Bi Sn-Cu Summary of Component Surface Finishes References

Chapter 15. Implementation of Lead-Free Soldering 15.1

Compatibility of Lead-Free Solders with SMT Reflow Process

15.1.1 15.1.2 15.1.3 15.1.4 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9

Experimental Design for Compatibility Evaluation Results of Compatibility Study Additional Factors to Be Considered Compatibility Assessment

Implementing Lead-Free Wave Soldering Effect of Reflow Profile on Lead-Free Soldering Flux Desired For Lead-Free Paste Soldering Flux Desired For Lead-Free Paste Handling Cleaning Performance of Lead-Free Solder Paste Flux Desired For Lead-Free Residue Cleaning Cleaning Chemistry/Process Desired for Lead-Free Residue Cleaning Selection of Lead-Free Solder Paste References

Chapter 16. Challenges for Lead-Free Soldering 16.1

Challenges for Surface Finishes

16.1.1 16.1.2 16.1.3 16.1.4 16.2

Black Pad Extraneous/Skip Plating Tin Whisker Surface Finish Cleaning Resistance

Challenges for Soldering

16.2.1 16.2.2 16.2.3 16.2.4

Intermetallic Compounds Dross Wave Solder Composition Lead Contamination

14.61 14.62

14.62 14.64 14.65 14.66 14.67 14.67 14.67 14.68 14.70 14.70 14.71 14.71 14.72 14.72 14.72 14.74 14.75 14.76 14.76

15.1

15.1

15.1 15.7 15.16 15.19 15.19 15.21 15.26 15.29 15.29 15.31 15.31 15.36 15.36

16.1

16.1

16.1 16.4 16.5 16.10 16.10

16.10 16.11 16.13 16.14

CONTENTS

16.2.5 16.2.6 16.2.7 16.2.8 16.3

Challenges for Reliability

16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.3.6 16.4

Fillet Lifting Poor Wetting Voiding Rough Joint Appearance Tin Pest Intermetallic Compound Platelet Stiff Joint Thermal Damage Flux Residue Cleaning Conductive Anodic Filament

Unanswered Challenges References

Chapter 17. Introduction to Conductive Adhesives 17.1 17.2

Electronics Packaging: A Brief Overview Overview of Conductive Adhesive Technology

17.2.1 ACAs 17.2.2 ICAs 17.3 17.4

Proposed Approaches for Fundamental Understanding of Conductive Adhesive Technology and Developing Conductive Adhesives for Solder Replacement Research Objectives/Goals

17.4.1 Fundamental Study of the Chemical Nature and Behavior of Organic Lubricants on Silver Flakes 17.4.2 Investigation of the Conductivity Mechanism of Conductive Adhesives 17.4.3 Identification of the Main Mechanisms Underlying the Unstable Contact Resistance of ECAs on Non-Noble Metals and Approaches to Stabilization of Contact Resistance 17.4.4 Development of Conductive Adhesives with Satisfactory Conductivity, Stable Contact Resistance and Desirable Impact Strength 17.5

Outline of Research Acknowledgments References

Chapter 18. Conductivity Establishment of Conductive Adhesives 18.1 18.2

Introduction Experiments

18.2.1 18.2.2 18.2.3 18.2.4 18.2.5

Materials Transmission Electron Microscopy (TEM) Study of ECAs Conductivity Establishment During Cure Measurements of Cure Shrinkage Conductivity Development of Ag Particles and ECA Pastes with External Pressures 18.2.6 Conductivity Establishment of a Conductive Adhesive and Lubricant Behavior of the Ag Flake 18.2.7 Measurements of Modulus Change During Cure

xiii

16.20 16.25 16.26 16.28 16.29

16.29 16.30 16.31 16.33 16.34 16.35 16.36 16.39

17.1

17.1 17.4

17.4 17.8 17.15 17.16

17.16 17.17

17.17 17.18 17.19 17.19 17.19

18.1

18.1 18.2

18.2 18.2 18.2 18.2 18.3 18.4 18.4

xiv

CONTENTS

18.2.8 Cure Study of Conductive Adhesives 18.2.9 Measurements of Cross-Linking Density 18.3

Results and Discussion

18.3.1 Observation of Interparticle Contact Between Silver Flakes 18.3.2 Conductivity Establishment of Conductive Adhesives During Cure 18.3.3 Study of the Relationship Between Silver Flake Lubricant Layer and Conductivity in ECAs 18.3.4 Study of the Relationship Between Cure Shrinkage and Conductivity Establishment 18.4

Conclusions References

Chapter 19. Mechanisms Underlying the Unstable Contact Resistance of ECAs 19.1 19.2

Introduction Experiments

19.2.1 19.2.2 19.2.3 19.2.4 19.3

Materials Study of Bulk Resistance Shifts Study of Contact Resistance Shifts Study of Oxide Formation

Results and Discussion

19.3.1 Contact Resistance Shift Phenomenon 19.3.2 Investigation of Mechanisms Underlying the Unstable Contact Resistance Phenomenon 19.3.3 Observation of Metal Oxide Formation 19.4

Conclusions References

Chapter 20. Stabilization of Contact Resistance of Conductive Adhesives 20.1

Introduction

20.1.1 Factors Affecting Galvanic Corrosion 20.1.2 Additives to Prevent Galvanic Corrosion 20.2

Experiments

20.2.1 20.2.2 20.2.3 20.2.4 20.2.5 20.2.6 20.3

Materials Contact Resistance Test Devices Study of Curing Behaviors of ECAs Study of Dynamic Properties of ECAs Measurement of Moisture Absorption Measurement of Adhesion Strength

Results and Discussion

18.4 18.4 18.5

18.5 18.5 18.8 18.11 18.18 18.18

19.1

19.1 19.3

19.3 19.3 19.4 19.5 19.5

19.5 19.7 19.12 19.13 19.15

20.1

20.1

20.1 20.1 20.3

20.3 20.3 20.3 20.4 20.4 20.4 20.5

20.3.1 Effects of Electrolytes on Contact Resistance Shifts 20.5 20.3.2 Effects of Moisture Absorption on Contact Resistance Shifts 20.5 20.3.3 Stabilization of Contact Resistance Using Additives 20.7 20.4 20.5

Conclusions Summary References Index About the Author

20.13 20.13 20.14 I.1 A.1

PREFACE

Why did we want to write this book? Was it because of fear: fear of (potential) legislation, fear of trade barriers, fear of competition? Absolutely not! We wrote this book for ourselves, our children, and their children, so that we will all have a greener environment to live in! Books of this type can be huge and contain many different viewpoints, e.g., political, economic, cultural, and infrastructural. However, emphasis in this book is placed on fundamental principles, engineering data, and manufacturing technologies. There are four major subjects in this book: integrated circuit (IC) packaging (Chaps. 1 through 7), printed circuit board (PCB)/substrates (Chaps. 8 through 10), PCB/substrate assembly of IC packages (Chaps. 11 through 16), and novel conductive adhesive materials (Chaps. 17 through 20). Chapter 1 briefly discusses the trends in worldwide environmentally benign manufacturing, and especially electronics manufacturing. Chapter 2 presents chip (wafer)-level interconnects with lead-free solder bumps. Emphasis is placed on the under-bump metallurgies (UBMs) and wafer bumping with microball mounting and paste-printing methods. Chapter 3 examines the lead-free solder joint reliability of wafer-level chip-scale packages (WLCSPs) on organic and ceramic substrates. Chapter 4 discusses chip (wafer)-level interconnects with solderless bumps constructed from Ni-Au, Au, and Cu, copper wires, gold wires, gold studs, and copper studs. The design, materials, process, and reliability of WLCSPs with these solderless interconnects on PCB/substrate are presented in Chap. 5. Halogen-free molding compounds for plastic quad flat pack (PQFP), plastic ball grid array (PBGA), and mold array (MAP-PBGA) packages are briefly discussed in Chap. 6. Environmentally benign die attach films for PQFP and PBGA packages and lead-free die attach bonding techniques for IC packaging are examined in Chap. 7. The environmental issues regarding conventional PCBs/substrates are discussed in Chap. 8. The influence of electronic products and the relevant environmental research are reviewed and the international driving forces for alternative materials are highlighted. In Chap. 9, halogenated and halogen-free materials are assessed in detail. Some environmentally conscious flame retardants are introduced. The emerging technologies for fabricating environmentally friendly PCBs are described in Chap. 10. The emphasis is placed on design for environment, green PCB manufacturing, and environmental safety. Chapter 11 reviews the global status of lead-free soldering activity, including legislation, consortia programs, and regional preference on lead-free solder alternatives. Chapter 12 discusses the criteria for lead-free solder, the approaches taken for development of lead-free solders, and the varieties of alloys and properties developed by the industry. Chapter 13 compares in detail the physical, mechanical, and soldering properties and the reliability of the prevailing lead-free solder options. Chapter 14 goes over the lead-free surface finishes for both PCBs and component applications. Both manufacturing process and performance are discussed for each type of surface finish. Implementation of lead-free soldering is analyzed in Chap. 15, with more empha-

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xvi

PREFACE

sis on the requirement for reflow process. While lead-free soldering is inevitable, the challenges of executing it definitely have to be addressed first. These are discussed in detail in Chap. 16. Chapter 17 presents an overview of conductive adhesive technology and proposes approaches for a fundamental understanding. Chapter 18 examines the conductivity mechanisms of isotropic conductive adhesives. Emphasis is placed on the relationship between lubricant removal and conductivity in electrically conductive adhesives (ECAs) and the relationship between cure shrinkage and conductivity establishment. Chapter 19 discusses the mechanisms underlying the contact resistance shifts of ECAs. Contact resistance stabilization of ECAs is presented in Chap. 20, with emphasis on determination of the effects of electrolytes and moisture absorption on contact resistance shifts and on the stabilization of contact resistance using various additives. For whom is this book intended? Undoubtedly it will be of interest to three groups of specialists: (1) those who are active or intend to become active in research and development in electronics and photonics manufacturing with lead-free, halogen-free, and conductive adhesive materials; (2) those who have encountered practical lead-free, halogen-free, and conductive adhesive problems and wish to understand and learn more methods for solving such problems; and (3) those who have to choose a reliable, creative, high-performance, robust, and cost-effective packaging technique for their green products.This book also can be used as a text for college and graduate students who have the potential to become our future leaders, scientists, and engineers in the electronics and photonics industry. We hope this book will serve as a valuable reference to all those faced with the challenging problems created by the ever increasing interest in lead-free, halogenfree, and conductive adhesive materials. We also hope it will aid in stimulating further research and development on environmental, electrical, and thermal designs; materials; processes; manufacturing; electrical, thermal, and end-of-life management; testing; reliability; and more sound applications of lead-free, halogen-free, and conductive adhesive technologies in electronic and photonic products. Organizations that learn how to design lead-free, halogen-free, and conductive adhesive technologies in their interconnect systems have the potential to make major advances in the electronics and photonics industry and to gain great benefits in cost, performance, density, quality, size, weight, and market share. It is our hope that the information presented in this book may assist in removing roadblocks; avoiding unnecessary false starts; and accelerating design, materials, and process development of lead-free, halogen-free, and conductive adhesive technologies. It is an exciting time for these technologies! John H. Lau, PhD, PE, ASME Fellow, IEEE Fellow Palo Alto, CA C. P. Wong, PhD, NAE, IEEE Fellow, AIC Fellow Duluth, Georgia Ning-Cheng Lee, PhD New Hartford, NY S.-W. Ricky Lee Kowloon, Hong Kong

ACKNOWLEDGMENTS

Development and preparation of this book was facilitated by the efforts of a number of dedicated people at McGraw-Hill and North Market Street Graphics. We would like to thank them all, with special mention to Stephanie Landis of North Market Street Graphics, and Thomas Kowalczyk and Jessica Hornick of McGrawHill for their unswerving support and advocacy. Special thanks to Steve Chapman, executive editor of electronics and optical engineering, who made our dream of this book come true by effectively sponsoring the project and solving many problems that arose during the book’s preparation. It has been a great pleasure and fruitful experience to work with these people in transforming our messy manuscripts into a very attractive printed book. The material in this book has clearly been derived from many sources, including individuals, companies, and organizations, and we have attempted to acknowledge in the appropriate parts of the book the assistance that we have been given. It would be quite impossible for us to express our thanks to everyone concerned for their cooperation in producing this book, but we would like to extend due gratitude. Also, we want to thank several professional societies and publishers for permitting us to reproduce some of their illustrations and information in this book. For example, the American Society of Mechanical Engineers (ASME) conference proceedings (e.g., International Intersociety Electronic Packaging Conference) and transactions (e.g., Journal of Electronic Packaging), the Institute of Electrical and Electronic Engineers (IEEE) conference proceedings (e.g., Electronic Components and Technology Conference) and transactions (e.g., Advanced Packaging and Manufacturing Technology), the International Microelectronics and Packaging Society (IMAPS) conference proceedings (e.g., International Symposium on Microelectronics) and transactions (e.g., International Journal of Microcircuits and Electronic Packaging), the Surface Mount Technology Association (SMTA) conference proceedings (e.g., Surface Mount International Conference and Exposition) and journals (e.g., Journal of Surface Mount Technology), the IBM Journal of Research and Development, Electronic Packaging and Production, Advanced Packaging, Circuits Assembly, Surface Mount Technology, Connection Technology, Solid State Technology, Circuit World, Microelectronics International, and Soldering and Surface Mount Technology. John Lau would like to thank his former employers, Hewlett-Packard Company and Express Packaging Systems, for providing him excellent working environments that have nurtured him as a human being, provided job satisfaction, and enhanced his professional reputation. He also would like to thank Steve Erasmus and Ted Lancaster for their trust, respect, and support of his work at Agilent Technologies. Furthermore, he would like to thank his eminent colleagues at Hewlett-Packard Company, Express Packaging Systems, Agilent Technologies, and throughout the electronics and optoelectronics industry for their useful help, strong support, and stimulating discussions.Working and socializing with them have been a privilege and an adventure. He learned a lot about life and packaging and interconnection technologies from them.

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xviii

ACKNOWLEDGMENTS

John Lau also thanks his daughter, Judy, and his wife, Teresa, for their love, consideration, and patience in allowing him to work many weekends on this book. Their belief that he is making a small contribution to the electronics and optoelectronics industry was a strong motivation for him. Knowing that Judy is going to Princeton for her graduate studies in physics this fall, and that Teresa and he are in good health, he wants to thank God for His generous blessings. C. P. Wong wants to thank his former colleagues at AT&T Bell Labs and Georgia Tech—in particular, his current colleagues and good friend Rao Tummala at the Packaging Research Center at the Georgia Institute of Technology (GIT)—for all their support. Special thanks to his former PhD student, D. Lu, for his outstanding work on electrical conductive adhesives. C.P. also thanks his wife, Lorraine, and his children, Michelle and David, for their support, love, and understanding all these years at Bell and GIT. Ning-Cheng Lee would like to express gratitude to Indium Corporation of America for providing a highly inspiring work environment. He also thanks his colleagues at Indium for their encouragement and support of his pursuit of solutions for the never ending challenges of this rapidly evolving world. Ning-Cheng Lee wants to thank his mother, Shu-shuen Chang, for her encouragement and blessing, and his wife, Shen-chwen, for her full support and patience— particularly for her tolerance toward his irregular work hours. He would also like to thank his sister Yu-Hsuan for her selfless and dedicated effort in taking care of their aged mother so that he can focus on outside challenges. Ricky Lee wishes to express his gratitude to his colleagues at Hong Kong University of Science and Technology and his industrial partners in the Asia-Pacific region. Without their efforts to establish a pro-electronic packaging environment, he probably would not have begun his endeavor in this discipline. Special thanks are also due to the Industry Department and Research Grant Council (RGC) of Hong Kong for their financial support to part of his research activities in electronic packaging. Ricky Lee is also indebted to his family. During a certain period while working on this book, he averaged only four hours of sleep a night. Without the spiritual support from the family, he could never have struggled through that exhausting time!

CHAPTER 1

INTRODUCTION TO ENVIRONMENTALLY BENIGN ELECTRONICS MANUFACTURING 1.1

TRENDS IN INDUSTRY

Many thousands of industries have arisen during the four great Western transformations—the Renaissance, the Reformation, the Industrial Revolution, and the Computer Age. The automobile and electronics industries are the largest and most important of the current industries.They will be briefly discussed in the following text.

1.1.1

AUTOMOBILE INDUSTRY

Until 1996, the automobile industry was the largest industry in the world. Its early shift from workshop manufacturing to mass production made cars affordable for billions of people. However, emissions of unburned hydrocarbons, nitrogen oxides, and carbon monoxide spread over urban areas and into the countryside, which was increasingly buried under asphalt and concrete roads. And the synthesis of plastics (used in automobiles) grew into a large, highly energy-intensive industry generating a variety of toxic pollutants previously never present in the biosphere and introducing huge numbers of nondecaying wastes into the environment. Post-1945 developments amplified these trends. New environmental risks were introduced as the developed world entered the period of its most impressive economic growth, terminated only by the 1973 to 1974 quintupling of oil prices. In just 25 years, the consumption of primary commercial energy nearly tripled, electricity generation grew about 8-fold, car ownership increased 6-fold, and production of most kinds of synthetic materials grew more than 10-fold. In the summer of 1970, the Massachusetts Institute of Technology first attempted a systematic evaluation of global environmental issues. Their summary of the Study of Critical Environmental Problems indicated the following relative importance as perceived at that time: (1) emissions of carbon dioxide from fossil fuel combustion; (2) particulate matter in the atmosphere, cirrus clouds from jet aircraft, the effects of supersonic planes on stratospheric chemistry, the thermal pollution of waters, and the impact of pesticides; and (3) mercury and other toxic heavy metals, oil on the ocean, and the nutrient enrichment of coastal waters. Just a month later, U.S. president Richard Nixon sent Congress the first report of the President’s Council on Environmental Quality. Soon afterward, the Environmental Protection Agency (EPA) was born and the environment entered big-time politics. It should be emphasized that this was the first time in history that a nation had taken comprehensive stock of the quality of its surroundings. One of the EPA’s 1.1 Copyright © 2003 by The McGraw-Hill Companies, Inc. Click here for terms of use.

1.2

CHAPTER ONE

greatest achievements is banning lead additives in gasoline, thus reducing the concentration of lead in the air by 94 percent from 1980 to 1999.

1.1.2

ELECTRONICS INDUSTRY

Since 1996, the electronics industry has been the largest industry in the world (more than $1 trillion).1–116 It is the most dynamic, fascinating, and important area of manufacturing.There are many categories of electronic products, such as consumer, computer, and communication items. Today, however, computers and their peripheral products account for the greatest percentage of the total revenue for electronic products. In 1992, 11.5 million personal computers (PCs) were shipped in the U.S. According to the data from the National Safety Council (1999), the number is projected to be 55.8 million in 2005, as shown in Fig. 1.1. In the past few years the electronics industry has been facing an impending change in light of upcoming halogen-free and lead-free technology legislations. This is because the electronics industry has relied on halogenated flame retardants and tin-lead solders for its products. In 1998, the European Commission introduced two draft proposals called the Waste Electrical and Electronic Equipment (WEEE) and Reduction of Hazardous Substances (ROHS) directives. The primary objective of these complementary proposals is to minimize the risks and impacts that the production, use, treatment, and disposal of waste electrical and electronic equipment have on human health and the environment. Additionally, the directives are intended to prevent uncontrolled disposal of electrical and electronic equipment and to foster the development of reuse and recycling methods in order to reduce the amount of waste for disposal. In short, they aim for “green” products!

FIGURE 1.1 In 1992, the number of PCs shipped in the U.S. was 11.5 million. According to the National Safety Council, the projected number for 2005 is 55.8 million.

ENVIRONMENTALLY BENIGN ELECTRONICS MANUFACTURING

1.3

It is interesting to point out that green products sell! For example, Matsushita’s market share of its lead-free MiniDisc player jumped from 4.6 to 15 percent in 6 months (1999) in Japan. Toshiba’s bromine-free printed circuit boards (PCBs) help the company to sell its Libretto and Dynabook notebook computers in Europe and has earned Toshiba some romantic names such as Blue Angel (in Germany), White Swan (in Finland), and TCOGY (in Sweden). The European Commission, which revised the original draft in 2000, included January 2, 2008 as the implementation date for the lead ban. In further revisions, the European Parliament and the Council of Ministers proposed that the ban on lead take effect on January 1, 2006 and January 1, 2007, respectively. Also, WEEE and ROHS addressed several concerns about the use of halogened flame retardants, primarily (1) formation of dioxins and furans during incineration or recycling, and (2) persistence and bioaccumulation. Prior to the proposed ban on halogen, lead, and other toxic materials, there are other projected milestones of the WEEE and ROHS directives; for instance, producers are expected to establish systems for recovering electronic waste by the end of 2003. Japan has begun its version of take-back legislation effective in 2001 for a variety of its domestic products. The Electric Household Appliance Recycling Law passed the obligation for collection and recycling of waste appliances to the producers of those appliances. It should be emphasized that worldwide interest in halogen-free flame retardants and lead-free solders continues to grow, if not for environmental or regulatory reasons, then because of market differentiation. Many Japanese manufacturers are ahead of the proposed regulated ban on halogen and lead. Also, most Japanese system manufacturers want their products to be labeled green for market share opportunities, so they drive subassembly, component, and PCB manufacturers to make the change to halogen-free and lead-free materials prior to impending regulations becoming effective.

1.2 TRENDS IN WORLDWIDE ENVIRONMENTALLY BENIGN MANUFACTURING Worldwide trends in environmentally benign manufacturing (EBM), especially in Europe, Japan, and the U.S., have been studied by Murphy62 in four categories: government, industry, research and development (R&D), and education. The government activities include take-back legislation, landfill bans, material bans, life cycle assessment (LCA) tool and database development, recycling infrastructure, economic incentives, regulation by medium, cooperative/joint efforts with industry, and financial and legal liability. The industrial activities include International Standards Organization (ISO) 14000 certification, water conservation, energy conservation/CO2 emissions, decreased releases to air and water, decreased solid waste/postindustrial recycling, postconsumer recycling, material and energy inventories, alternative material development, supply chain involvement, EBM as a business strategy, and life cycle activities. The R&D activities include relevant basic research (>5 years out) and applied R&D (<5 years out) such as polymers, electronics, metals, automotive/transportation, and systems. The educational activities include courses, programs, focused degree programs, industry sponsorship, and government sponsorship.

1.4

CHAPTER ONE

TABLE 1.1 Government Activities in EBM Japan

U.S.

Europe

Take-back legislation

Activity

**

—

****

Landfill bans

**

*

***

Material bans LCA tool and database development

*

*

**

***

**

****

Recycling infrastructure

**

*

***

Economic incentives

**

*

***

Regulation by medium

*

**

*

Cooperative/joint efforts with industry

**

*

****

Financial and legal liability

*

****

*

More asterisks indicate higher scores.

1.2.1

GOVERNMENT ACTIVITY

Governments in both Japan and Europe appear (at least outwardly) to operate at a greater level of interaction and cooperation with the private sector than does government in the U.S. As a result, Japan and Europe tend to have a more proactive approach to problem solving. The U.S., largely in response to financial and legal liabilities associated with a significant amount of regulatory action, tends to solve problems in a more reactive manner (Table 1.1).

1.2.2

INDUSTRY ACTIVITY

U.S. industry is focused on the reduction of liability, decreased consumption of resources (especially water), and pollution prevention. Corporations in Japan are concerned with energy conservation (reduced CO2 emissions), decreased solid waste, and incorporation of environmental issues into business strategies. European Union (EU) industries are very involved in end-of-life issues (Table 1.2). TABLE 1.2 Industrial Activities in EBM Activity ISO 14000 certification Water conservation Energy conservation/CO2 emissions Decreased releases to air and water

Japan

U.S.

Europe

****

*

***

**

***

*

****

**

**

*

***

**

****

**

***

Postconsumer recycling

**

*

****

Material and energy inventories

***

*

**

Alternative material development

**

*

***

Decreased solid waste/postindustrial recycling

Supply chain involvement EBM as a business strategy Life cycle activities More asterisks indicate higher scores.

**

*

**

****

**

***

**

**

**

ENVIRONMENTALLY BENIGN ELECTRONICS MANUFACTURING

1.5

TABLE 1.3 Research and Development Activities in EBM Activity

Japan

U.S.

Europe

**

***

**

Electronics

**

***

*

Metals

***

*

**

Relevant basic research (>5 years out) Polymers

Automotive/transportation

**

*

***

Systems

**

*

*** **

Applied R&D (<5 years out) Polymers

*

***

Electronics

***

**

**

Metals

***

*

**

Automotive/transportation

***

*

***

Systems

**

*

***

More asterisks indicate higher scores.

1.2.3

R&D ACTIVITY

R&D in the U.S. is heavily focused on materials and process technologies. Japan’s efforts are more closely aligned with applications and manufacturing systems. European research is heavily weighted toward systems engineering, particularly in the areas of design for the environment and LCA (Table 1.3).

1.2.4

EDUCATION ACTIVITY

Higher education has begun to address EBM to a much greater degree in the European countries than in either the U.S. or Japan. However, the U.S. places more emphasis on the environmental consciousness of elementary students than Europe or Japan (Table 1.4). Overall, it appears that EBM in the U.S and Japan. is somewhat behind that in the EU.

TABLE 1.4 Educational Activities in EBM Activity

Japan

U.S.

Europe

Courses

**

**

***

Programs

*

*

**

Focused degree programs

—

—

*

Industry sponsorship

*

**

***

Government sponsorship

*

*

**

More asterisks indicate higher scores.

1.6

CHAPTER ONE

1.2.5 WORLDWIDE EFFORTS ON ENVIRONMENTALLY BENIGN ELECTRONICS MANUFACTURING As mentioned in Sec. 1.1.2, alternative material systems for halogen-free flame retardants and lead-free solders are currently of intense interest in the electronics industry.This was initiated in part by the WEEE/ROHS directives and subsequently driven by Japanese electronics system retailers and manufacturers in an attempt to increase European market share in advance of final legislation. European original equipment manufacturers have adopted some of these materials, albeit somewhat reluctantly. U.S. original equipment manufacturers are investigating the materials and are supplying components and PCBs that are halogen-free and lead-free in response to customer demand. At the same time, they are hesitant to adopt technologies that are largely believed to be less reliable and not clearly of environmental benefit.62

1.3 TRENDS IN ENVIRONMENTALLY BENIGN ELECTRONICS MANUFACTURING The semiconductor is the heart of the electronics industry. The total semiconductor market is expected to reach $224 billion in 2002, as shown in Fig. 1.2. It can be seen that 30 percent of the market is for metal-oxide semiconductor (MOS) microcomponents, which includes microprocessors, microcontrollers, and microperipherals; 21 percent is for MOS memory, which includes dynamic random access memory (DRAM), flash/electronically erasable programmable read-only memory (EEPROM), static random access memory (SRAM), read-only memory (ROM), and erasable programmable read-only memory (EPROM); 20 percent is for MOS logic, which includes application-specific integrated circuits (ASICs), SP logic, flat panel liquid

FIGURE 1.2 Total semiconductor market in 2002.

ENVIRONMENTALLY BENIGN ELECTRONICS MANUFACTURING

1.7

TABLE 1.5 Semiconductor Technology Trends and Forecast Technology

1999

2000

2001

2002

2003

2004

2005

≥1.0 µm

595

676

472

555

538

571

574

0.8 µm

1,016

1,077

793

992

1,067

1,209

1,083

0.5 µm

2,226

2,318

1,762

1,907

1,798

2,202

2,015

0.35 µm

2,893

4,101

2,348

2,651

2,649

3,328

3,018

0.25 µm

2,253

3,567

2,621

3,543

3,708

4,303

4,045

0.18 µm

80

998

1,306

2,716

4,575

6,463

6,095

0.13 µm

0

15

172

630

1,622

3,047

4,049

<0.13 µm

0

0

0

0

19

344

1,235

9,108

12,752

9,475

12,993

15,976

21,467

22,112

Total

Values are in thousands of 8″ wafers.

display (FPLD), display driver, and GP logic; 16 percent is for analog devices; 8.4 percent is for discrete devices; 5 percent is for optoelectronics; and 0.36 percent is for bipolar digital devices. The trends in semiconductor technology are shown in Table 1.5 for 8-in wafers. It can be seen that: (1) in 2000, most of the wafers were made using the 0.35-µm technology, with only 15,000 made using 0.13-µm technology; (2) in 2001, most of the wafers were made using 0.25-µm technology; and (3) in 2003, most of the wafers were projected to be made using 0.18-µm technology and more than 1.6 million will be made using 0.13-µm technology. Semiconductor equipment bookings enjoyed the biggest growth between the summer of 1998 and the summer of 2000, as shown in Fig. 1.3. However, the figure drops like a rock after August 2000. The MOS wafer fabrication capacity utilization also reached new lows after the third quarter of 2000, as shown in Fig. 1.4. In Fig. 1.5, which shows the MOS wafer fabrication capacity utilization turning point forecast, it can be seen that things go nowhere but down! As a matter of fact, foundry utilization

FIGURE 1.3 Total semiconductor equipment bookings.

1.8

CHAPTER ONE

FIGURE 1.4 Wafer fabrication utilization reaching new lows.

rates have reached the lowest level ever. Since semiconductors are the best index of the future of the electronics industry, there is no sign of recovery yet. System on a chip (SOC) could be their savior; however, there are many issues to be resolved.1–4 In general, an electronic product consists of semiconductor integrated circuits (IC) devices, IC packages, PCBs, and other components as well as materials such as solder and polymer. In the next section, EBM of these key elements will be briefly discussed.

FIGURE 1.5 Wafer fabrication capacity utilization forecast.

1.8

ENVIRONMENTALLY BENIGN ELECTRONICS MANUFACTURING

1.3.1

1.9

IC FABRICATION

Most ICs are fabricated in a wafer with a diameter that can be as large as 300 mm. Usually IC fabrication facilities are very clean and have few environmental concerns. However, they use too much water, energy, and natural gas as well as produce significant amounts of solid waste, which in turn affect the environment. This is due to IC manufacturing processes such as (1) deposition of very thin layers and etching of patterns at scales down to 0.13 µm (energy-intensive and causes perfluoro compound emission); (2) wafer surface (ultra) cleaning (uses large amounts of water); and (3) chemical mechanical polishing (uses significant amounts of water and creates solid waste). Thus, IC fabrication companies should work very closely with equipment and material companies to qualify new materials and processes as well as to reduce usage of energy and water and emissions of solid waste and perfluoro compounds.

1.3.2

IC PACKAGING

After the wafer is made, it is ready for chip-level interconnects. Solder bumps on the wafer are one form of these interconnects. More than 12 different methods of making the tiny tin-lead solder bumps on wafers have been reported,5 and they will not be repeated here. However, solder bumps with lead-free solders will be discussed in Chaps. 2 and 3. Some companies that provide various types of wafer bumping are Advanced Interconnect Solutions, Amkor Technology Inc., APack Technologies Inc., Aptos Corp., ASE Inc., Carsem, Chipbond Technology Corp., Fujitsu Ltd., IC Interconnect, Kulicke & Soffa Flip Chip Division, Megic Corp., Pac Tech GmbH, SPIL Group, ST Assembly Test Services Ltd., STECO, and Unitive Advanced Semiconductor Packaging. For direct chip attach applications, the solder-bumped chip is placed directly on the PCB.1–11 However, for solder-bumped flip chip in a package (FCIP) applications, the solder-bumped flip chip is surface mounted on the substrate of the FCIP first, and then the FCIP is surface mounted on the PCB with solder. Usually, the melting point of the solder bumps on FCIP is higher than that of the solder joints on the PCB due to packaging hierarchies. However, this is not necessary if the underfill encapsulants are properly made.4–8 It has been proposed that pure tin (with a melting temperature of 232°C) should be used for solder bumps in FCIP. However, for very-fine-pitch pads on the chip, tin whisker growth could short the circuits.117–160 For most FCIPs, the housing (package) is usually made of flame-retardant molding compounds that could cause environmental concerns.This topic will be discussed in Chaps. 6 and 7. It should be noted that there are many different solderless chip-level interconnects4–9 such as Au stud bumps,Au bumps, Cu bumps, Ni-Au bumps, Cu wires, and Au microspring wires. These could be low-cost alternatives to lead-free technology and will be discussed in Chaps. 4 and 5.

1.3.3

PCB

PCBs are used to support and link the components of an electronic product. Unlike the bismaleimide triazine (BT) substrates (with a glass transition temperature >180°C) used in organic FCIP,10 most of the PCB materials have a glass transition

1.10

CHAPTER ONE

temperature ∼125°C. This may not be compatible with the lead-free surface-mount technology assembly process, which requires higher process temperatures as will be discussed in Sec. 1.3.4. Thus, PCB manufacturers should investigate new materials and processes for their PCBs for lead-free applications. Another big challenge for PCB manufacturers is the use of brominated flame retardants (BFRs), because, as mentioned in Sec. 1.1.2, the WEEE/ROHS directives ban the use of many substances, including some BFRs. This topic will be discussed briefly in Sec. 1.3.5 and in more details in Chaps. 8 through 10. Today, most PCB shops use too much water, energy, and chemicals as well as produce significant amounts of solid and trim wastes, which in turn affects the environment. These are due to PCB manufacturing processes such as: (1) drilling (energy-intensive and creates solid waste); (2) plating (uses large amounts of water and complex chemistries including organic and inorganic compounds); and (3) etching (water-, energy-, and chemical-intensive). PCBs with build-up layers connecting through microvias4 could be inherently more environmentally friendly because they have smaller holes, less real estate, and better vision alignment (with higherprecision machines). All of these lead to less solid and trim waste as well as reduced resource consumption for the same functions.

1.3.4

LEAD-FREE SOLDERS

Low-cost tin-lead solders1–16 have been used as joining materials in the electronics industry for many years. The unique physical (well-defined eutectic with a relatively low melting point) and mechanical (reasonably good thermal fatigue reliability) properties of the tin-lead solders have facilitated PCB assembly choices that have fueled creative advanced packaging developments, such as solder-bumped flip chips,1–9 ball grid array packages,1–10 and wafer-level chip-scale packages.1–7 For these packaging technologies, the tin-lead solders are the electrical and mechanical “glue” of the PCB assemblies. If the manufacturing process is well controlled and products are recycled, there is little environmental risk in using tin-lead solder, since it is easily recovered. Since 1992, different bills have been introduced at the U.S. Congress to ban lead from a wide variety of applications, including solders. The reasons are, among others, that lead and its compounds are ranked as one of the top 10 hazardous materials and that lead is the number one environmental threat to children. Also, according to the American Association of Pediatrics, lead can damage the brain and nervous system, and even a low level of lead exposure can cause learning disabilities; hearing loss; speech, language, and behavior problems; and other serious health effects. Of the 5 million tons of lead produced annually, only 0.5 percent is used in electronic solder applications. However, this small amount of lead in solder poses more concern for human health than the lead in storage batteries (almost 100 percent recycled). This is due to the fact that, although solder is only a small percentage by weight of electronic products such as televisions, refrigerators, computers, and phones, these products often end up in landfills after being disposed of, and the lead could be ultimately leached out into the waste stream and the water supply. Most of the lead-free solders,62–101 especially the most promising family (Sn-AgCu-X), have a melting point (∼213°C) higher than that of tin-lead solder (183°C). These higher melting temperatures require higher process temperature profiles. For tin-lead solder the maximum reflow temperature is ∼220°C, and for Sn-Ag-Cu sol-

ENVIRONMENTALLY BENIGN ELECTRONICS MANUFACTURING

1.11

der it is ∼260°C. Thus, in order to use the lead-free solders, all the materials of the PCB and the components on the PCB must be able to withstand the increased thermal exposure. This leads not only to requiring support of the infrastructure (materials, equipment, components, PCB, etc.) but also to increased cost and lower reliability. Furthermore, significantly more energy is needed, which causes environmental concerns. There are many reliability test and modeling data on tin-lead solders.1–16 However, since lead-free solders are so new compared to tin-lead solders, there are not many creditable, reliable data.Thus, there is a big risk in shipping products with leadfree solders, especially those that require very high levels of reliability. Unlike tin-lead solder (with two components and a composition that is very easy to control), most of the potential lead-free solders have at least three components. (For a list of more than 100 lead-free solders, please read Ref. 5.) This could create nonuniformity in compositions, thus making manufacturing process control much more critical and increasing the likelihood of yield loss. Due to the higher melting points of most lead-free solders, component rework is more difficult, if not impossible, which leads to more manufacturing yield loss. Also, disassembly is more difficult, which limits component recovery at the end of life of the product. How should lead-free solders be selected? What are the potential lead-free solders? What are the correct PCB and component surface finishes for lead-free soldering? What are the optimal PCB assembly processes with lead-free soldering? How should low-alpha solders for flip chip applications be selected and used? The answers to these questions can be found in Chaps. 11 through 16.

1.3.5

HALOGEN-FREE FLAME RETARDANTS

Polymers are very important materials for most electronic products.19 They can be used for the housing (molding compounds) and the substrate (epoxy resins) of IC packages. Since most polymers are highly flammable and their presence in electronic products provides a ready source of heat, there is a need for flame retardants of some type to be incorporated into the IC package and PCB (thermosets) used in electronic products. Also, polymers have a poor environmental image, in large part due to their contribution to litter and landfills. Historically, electronic products have used halogenated flame retardants.102–116 A halogen is a chemical compound and is defined as any of a group of five chemically related nonmetallic elements including fluorine, chlorine, bromine, iodine, and astatine. Until recently, halogens have been widely used as fire-extinguishing agents. They may be incorporated into a system, such as the coating on a PCB. Although effective as flame retardants, this group of chemicals can have a negative impact on human and environmental health. Bromine (Br) is a heavy, volatile, corrosive, reddish-brown, nonmetallic liquid element that has a highly irritating vapor. It is used in producing gasoline antiknock mixtures, fumigants, dyes, and photographic chemicals. Chlorine (Cl) is a highly irritating, greenish-yellow gaseous element that is capable of combining with nearly all other elements. It is produced principally by electrolysis of sodium chloride and is used widely to purify water, as a disinfectant and bleaching agent, and in the manufacture of many important compounds including chloroform and carbon tetrachloride.

1.12

CHAPTER ONE

Fluorine (F) is a pale yellow, highly corrosive, poisonous, gaseous element, the most electronegative and most reactive of all the elements. It is used in a wide variety of industrially important compounds. Astatine (At) is a highly unstable radioactive element, the heaviest of the halogen series, which resembles iodine in solution. Its longest-lived isotope has a mass number of 210 and a half-life of 8.3 h. Antimony (Sb) is a metallic element having four allotropic forms, the most common of which is a hard, extremely brittle, lustrous, silver-white, crystalline material. It is used in a wide variety of alloys, especially with lead in battery plates, and in the manufacture of flameproofing compounds, paint, semiconductor devices, and ceramic products. Iodine (I) is a lustrous, grayish-black, corrosive, poisonous element having radioactive isotopes, especially 131I. It is used as a medical tracer and in thyroid disease diagnosis and therapy. Iodine compounds are used as germicides, antiseptics, and dyes. While all these halogenated frame retardants are well know to have detrimental effects on both health and the environment, the BFRs are considered the safest. Currently, the phenolics (one family of BFRs), which include tetrabronmobisphenol A (referred to as TBBPA or TBBA), are used primarily for PCBs. However, due to the WEEE/ROHS directives, there is a significant effort within the electronics industry to find alternatives to BFRs, especially in Japan and Europe. For example, Toshiba, Sony, and Nortel Networks are using halogen-free PCBs (Chaps. 8 through 10). Sumitomo, Nitto Denko, and Kumgang Korea Chemical are making halogen-free molding compounds for IC packages (Chap. 6).

1.3.6

CONDUCTIVE ADHESIVES

Recently, for the sake of a green environment, solderless materials such as adhesives161–180 have been evaluated for assembling flip chips on PCBs and substrates. There are many different kinds of adhesives, including isotropic conductive adhesives (ICAs), anisotropic conductive adhesives (ACAs), and nonconductive adhesives (NCAs). ICAs electrically conduct in all directions. Usually, ICAs are made of epoxy with Ag-Pd filler particles.They can be applied on the pads of PCBs or substrates by stencil printing or screening. But the most commonly used method is dipping the gold, copper, or Ni-Au bumps into the ICA, which will be discussed in Chaps. 4 and 5. Because ACAs electrically conduct only in the vertical direction, they are also called z-axis conductive materials. There are two groups of anisotropic conductive materials, namely, anisotropic conductive films (ACFs) and anisotropic conductive pastes (ACPs). An ACF consists of thermosetting adhesive, conductive particles (solids or plated plastic spheres), and release film, and looks like paper. An ACP consists of thermosetting adhesive and conductive particles and looks like a paste. For both adhesives, the solids often used are Au, Ni, and solder. NCAs are conventional underfills and are not electrically conductive. Their contents are thermosetting adhesive and nonconductive fillers. In general, they are used for diffusion bonding and solder joint reliability in flip chip assemblies. When an NCA cures, it shrinks and brings the bumps and pads into a state of compression, which ensures long-term reliability. The applications of ICAs, ACFs, ACPs, and NCAs will be discussed in Chaps. 4 and 5. Novel developments in ICAs,ACFs,ACPs, and NCAs will be reported in Chaps. 17 through 20.

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FIGURE 1.6 Average lifetime of PCs.

1.3.7

END-OF-LIFE MANAGEMENT

Historically, the precious and base metals such as the gold, palladium, copper, and lead on IC devices and PCBs, the steels of the product housings, and many expensive components on PCBs have been recycled for profitability. However, because of the advance of technologies (much less use of precious and base metals and much more use of plastic instead of steel for the housing) and shorter product lifetimes (cheaper components), recycling is becoming less economically attractive.

FIGURE 1.7 Number of PCs obsoleted in the U.S. was 17.5 million (1997). According to the National Safety Council, the number is projected to reach 61.3 million by 2007.

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CHAPTER ONE

On the other hand, the volume of electronic products being manufactured is growing at an unprecedented rate (see Fig. 1.1 for an example) and their lifetimes are being shortened (see Fig. 1.6), thus accelerating rates of obsolescence (see Fig. 1.7). Consequently, there is more pressure to recycle in Europe and Japan, as discussed in Sec. 1.1.2. The system manufacturers should design their electronic products for recycling and for the environment!

ACKNOWLEDGMENTS The authors would like to thank C. Murphy of the University of Texas, G. Pitts of Ecolibrium, the National Safety Council, and Semiconductor Equipment and Materials International (SEMI) for sharing their useful and important information with the industry.

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69. Glazer, J., “Microstructure and Mechanical Properties of Pb-Free Solder Alloy for LowCost Electronic Assembly: A Review,” Journal of Electronic Materials, 23(8):693–700, 1994. 70. Vianco, P. T., K. L. Erickson, and P. L. Hopkins, Solid State Intermetallic Compound Growth Between Copper and High Temperature, Tin-Rich Solder—Part 1: Experimental Analysis, Sandia National Labs (Contract Number DE-AC04-94AL85000) Report, 1994. 71. Kang, S. K., and A. K. Sarkhel, “Lead (Pb)-Free Solders for Electronic Packaging,” Journal of Electronic Materials, 23(8):701–708, August 1994. 72. Shangguan, D., A. Achari, and W. Green, “Application of Lead-Free Eutectic Sn-Ag Solder in No-Clean Thick Film Electronic Modules,” IEEE Transactions on Components, Packaging and Manufacturing Technology—Part B, 17(4):603–611, 1994. 73. Yang, W., L. E. Felton, and R. W. Messler, “The Effect of Soldering Process Variables on the Microstructure and Mechanical Properties of Eutectic Sn-Ag/Cu Solder Joints,” Journal of Electronic Materials, 24(10):1465–1472, 1995. 74. Hwang, J. S., Modern Solder Technology for Competitive Electronics Manufacturing, McGraw-Hill, New York, 1996. 75. Vianco, P., J. Rejent, I. Artaki, U. Ray, D. Finley, and A. Jackson, “Compatibility of LeadFree Solders with Lead Containing Surface Finishes as a Reliability Issue in Electronic Assemblies,” Proceedings of the IEEE Electronic Components and Technology Conference, pp. 1172–1183, May 1996. 76. Mei, Z., and H. Holder, “A Thermal Fatigue Failure Mechanism of 58Bi-42Sn Solder Joints,” ASME Transactions, Journal of Electronic Packaging, 118:62–66, June 1996. 77. Ren, W., M. Lu, S. Liu, and D. Shangguan, “Thermal Mechanical Property Testing of New Lead-Free Solder Joints,” Soldering and Surface Mount Technology, 9(3):37–40, October 1997. 78. Shangguan, D. A., and G. Gao, “Lead-Free and No-Clean Soldering for Automotive Electronics,” Soldering and Surface Mount Technology, 9(2):5–8, July 1997. 79. NCMS, Lead-Free Solder Project Final Report, NCMS Report 040IRE96, August 1997. 80. Mei, Z., F. Hua, J. Glazer, and C. Key, “Low Temperature Soldering,” Proceedings of IEMTS, pp. 463–476, October 1997. 81. Iida, A., Y. Kizaki, Y. Fukuda, and M. Mori, “The Development of Repairable Au-Al Solid Phase Diffusion Flip-Chip Bonding,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 101–107, May 1997. 82. Hua, F., Z. Mei, and J. Glazer, “Eutectic Sn-Bi as an Alternative to Pb-Free Solder,” Proceedings of Electronic Components and Technology Conference, pp. 277–283, May 1998. 83. Grusd, A., “Lead Free Solders in Electronics,” Proceedings of Surface Mount International Conference, pp. 648–661, August 1998. 84. Biocca, P., “Global Update on Lead-Free Solders,” Proceedings of Surface Mount International Conference, pp. 705–709, August 1998. 85. Wege, S., G. Habenicht, and R. Bergmann, “Manufacture and Reliability of Alternate Solder Alloys,” Proceedings of Surface Mount International Conference, pp. 699–704, August 1998. 86. Trumble, B., “Get the Lead Out,” IEEE Spectrum, 55–60, May 1998. 87. Smith, E. III, and L. Swanger, “Lead Free Solders—A Push in the Wrong Directions?” Proceedings of the IPC Technical Conference, pp. F-10-1–F-10-6, March 1999. 88. Kang, S., J. Horkans, P. Andricacos, R. Carruthers, J. Cotte, M. Datta, P. Gruber, J. Harper, K. Kwietniak, C. Sambucetti, L. Shi, G. Brouillette, and D. Danovitch, “Pb-Free Solder Alloys for Flip Chip Applications,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 283–288, June 1999. 89. Lau, J. H., and C. Chang, “TMA, DMA, DSC, and TGA of Lead Free Solders,” Soldering and Surface Mount Technology, 11(2):17–24, 1999.

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90. Seelig, K., and D. Suraski, “The Status of Lead-Free Solder Alloys,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1405–1409, May 2000. 91. Whitten, G., “Lead-free Solder Implementation for Automotive Electronics,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1410–1415, May 2000. 92. Snowdon, K., C. Tanner, and J. Thompson, “Lead Free Soldering Electronic Interconnect: Current Status and Future Developments,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1416–1419, May 2000. 93. Butterfield, A., V. Visintainer, and V. Goudarzi, “Lead Free Paste Flux Evaluation and Implementation in Personal Communication Devices,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1420–1425, May 2000. 94. Nguty, T., S. Budiman, D. Rajkumar, R. Solomon, and N. Ekere, and M. Currie, “Understanding the Process Window for Printing Lead-Free Solder Pastes,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1426–1435, May 2000. 95. Ezawa, H., M. Miyata, S. Honma, H. Inoue, T. Tokuoka, J. Yoshioka, and M. Tsujimura, “Eutectic Sn-Ag Solder Bump Process for ULSI Flip Chip Technology,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1095–1100, May 2000. 96. Baynham, G., D. Baldwin, K. Boustedt, A. Johansson, C. Wennerholm, D. Patterson, and P. Elenius, “Flip Chip Processing of Lead-Free Solders and Halogen-Free High Density Microvia Substrates,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1101–1105, May 2000. 97. Korhonen, T., P. Su, S. Hong, M. Korhonen, and C. Li, “Under Bump Metallizations for Lead Free Solders,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1106–1110, May 2000. 98. Zama, S., D. Baldwin, T. Hikami, and H. Murata, “Flip Chip Interconnect Systems Using Wire Stud Bumps and Lead Free Solder,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1111–1117, May 2000. 99. Takeda, S., and T. Masuko,“Novel Die Attach Films Having High Reliability Performance for Lead-free Solder and CSP,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1616–1622, May 2000. 100. Lau, J. H., and S. Pan, “Creep Behaviors of Flip Chip on Board with 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints,” Proceedings of IMAPS Microelectronics Conference, pp. 866–873, September 2000. 101. Lau, J. H., S. Pan, and C. Chang, “Creep Analysis of Wafer Level Chip Scale Package (WLCSP) with 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board,” in Packaging of Electronic and Photonic Devices, ASME Book No. HO1217, November 2000. 102. Bauer, M., and E. Schoeffel, “Polycyanurates—Flame Resistant PWBs,” Proceedings of Electronics Goes Green 2000+, pp. 139–140, Berlin, Germany, 2000. 103. Bergendahl, C. G., “Electronics Goes Halogen-Free: International Driving Forces and the Availability and Potential of Halogen-Free Alternatives,” Proceedings of IEEE International Symposium on Electronics and the Environment, pp. 54–58, 2000. 104. Bergendahl, C. G., et al., “Alternatives to Halogenated Flame Retardants in Electronic and Electrical Products: Results from a Conceptual Study,” IVF Research Publication 99824. 105. Feldmann, K., and S. Trautner, “Computer Based Disassembly Planning and Design for Recycling,” Proceedings of Electronics Goes Green 2000+, pp. 231–236, Berlin, Germany, 2000. 106. Fujimoto, J., et al., “Proposal of Service-Oriented Products Based on the Inverse Manufacturing Concept (1st Report)—Concept and Business Model,” Proceedings of Electronics Goes Green 2000+, pp. 115–120, Berlin, Germany, 2000. 107. Hardy, M. L., “Toxicology of Commercial PBDPOs and TBBPA,” presented at IPC Printed Circuits Expo, April 5, 2000.

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1.20

CHAPTER ONE

129. Backes, P. G., “Selected Programs Shorting Failure Investigation Final Report (FASS 1298),” Hughes Technical Internal Correspondence, October 16, 1991. 130. Cunningham, K. M., and M. P. Donahue, “Tin Whiskers: Mechanism of Growth and Prevention,” 4th International SAMPE Electronics Conference, p. 569, June 1990. 131. Haimovich, J., “Hot Air Leveled Tin: Solderability and Some Related Properties,” IEEE Proceedings, 107–112, January 7, 1989. 132. Heutel, K. J., “Problem Notification—Tin Whisker Growth in Electronic Assemblies,” GIDEP Alert F3-A-87-04A, February 19, 1988. 133. Dunn, B. D., “Mechanical and Electrical Characteristics of Tin Whiskers with Special Reference to Spacecraft Systems,” European Space Agency Journal, 12:1–17, January 14, 1988. 134. Dunn, B. D., “A Laboratory Study of Tin Whisker Growth,” European Space Agency (ESA) STR-223, pp. 1–50, September, 1987. 135. Baker, R. G., “Spontaneous Metallic Whisker Growth,” Plating and Surface Finishing, 74(10):10, 74(11):12, 66, 1987. 136. Balmain, K. G., “Arc Propagation, Emission and Damage on Spacecraft Dielectrics,” AGARD CP-406, vol. 16, 1987. 137. Gabe, D. R., “Whisker Growth on Tin Electrodeposits,” Transactions of the IMF, 65:115, 1987. 138. Williams, E. H., “Tin Whiskers on Flat Pack Lead Plating Between Solder Dip and Sealing Glass,” ISTFA Proceedings, 16–21, 1985. 139. Gerbunova, K. M., and V. K. Glazaunova, “Present State of the Problem of Spontaneous Growth of Whisker Crystals on Electrolytic Coatings,” Institute of Physical Chemistry, Academy of Sciences of the USSR, 20(3):342–358, 1984. (in Russian) 140. Lin, M.-C., “Tin Whisker Growth on IC Lead Finish—A Review,” AT&T Bell Laboratories Technical Memorandum: TM52221-840709-01, July 9, 1984. 141. Kawanaka, R., K. Fujiwara, S. Nango, and T. Hasegawa, “Influence of Impurities on the Growth of Tin Whiskers,” Japanese Journal of Applied Physics, 22:917–921, March 19, 1983. 142. Frederickson, A. R., “Electric Discharge Pulses in Irradiated Solid Dielectrics in Space,” IEEE Transactions, EI-18:337–349, 1983. 143. Kakeshita, T., R. Kawanaka, and T. Hasegawa, “Grain Size Effect of Electro-Plated Tin Coatings on Whisker Growth,” Journal of Materials Science, 17:2560–2566, 1982. 144. Dunn, B. D., “The Fusing of Tin-Lead Plating on High Quality Printed-Circuit Boards,” Transactions of the Institute of Metal Finishing, 58:26, 1980. 145. Hada, Y., O. Morikawa, and H. Togami, “Study of Tin Whiskers on Electromagnetic Relay Parts,” 26th Annual National Relay Conference, pp. 9.1–9.15, April 25–26, 1978. 146. Smith, G. A., “How to Avoid Metallic Growth on Electronic Hardware,” Circuits Manufacturing, 66–72, July 1977. 147. Zakraysek, L., D. B. Blackwood, W. Brouillette, W. Leyshon, A. Tardone, C. Byrns, and F. Poe, “Whisker Growth from a Bright Acid Tin Electrodeposit,” Plating and Surface Finishing, 64:38–43, March 1977. 148. Dunn, B. D., “Whisker Formation on Electronic Materials,” ESA Scientific and Technical Review, 2(1):1–22, 1976. 149. Lindborg, U., “A Model for the Spontaneous Growth of Zinc, Cadmium, and Tin Whiskers,” Acta Metallurgica, 24:181, 1976. 150. Sabbagh, N.A.J., and H. J. McQueen, “Tin Whiskers: Causes and Remedies,” Metal Finishing, March 1975. 151. Britton, S. C., “Spontaneous Growth of Whiskers on Tin Coatings: 20 Years of Observation,” Transactions of the Institute of Metal Finishing, 52:95–102, April 3, 1974.

ENVIRONMENTALLY BENIGN ELECTRONICS MANUFACTURING

1.21

152. Kehrer, H. P., and H. G. Kadereit, “Tracer Experiments on the Growth of Tin Whiskers,” Applied Physics Letters, 16(11):411–412, June 1, 1970. 153. Key, P. L., “Surface Morphology of Whisker Crystals of Tin, Zinc and Cadmium,” IEEE Electronic Components Conference, pp. 155–157, May, 1970. 154. Furuta, N., and K. Hamamura, “Growth Mechanism of Proper Tin-Whisker,” Journal of Applied Physics, 8(12):1404–1410, December 1, 1969. 155. Walker, R., “Internal Stress in Electrodeposited Metallic Coatings,” Metal Finishing Monograph, 32, 1968. 156. Arnold, S. M., “Repressing the Growth of Tin Whiskers,” Plating, 53:96–99, 1966. 157. Besancon, R. M., “Electrical Discharges in Gases,” in The Encyclopedia of Physics, Reinhold, pp. 189–193, 1966. 158. Glazunova, V. K., and N. T. Kudryavtsev, “An Investigation of the Conditions of Spontaneous Growth of Filiform Crystals on Electrolytic Coatings,” Translated form Zhurnal Prikladnoi Khimii, 36(3):543–550, March 1963. 159. Arnold, S. M., “Growth of Metal Whiskers on Electrical Components,” Proceedings of Electrical Components Conference, pp. 75–82, 1959. 160. Frank, F. C., “On Tin Whiskers,” Philosophical Magazine, 44:854, 1953. 161. Lau, J. H., “Flip Chip on PCBs with Anisotropic Conductive Film,” Advanced Packaging, 44–48, July/August 1998. 162. Miebner, R., R. Aschenbrenner, and H. Reichl, “Reliability Study of Flip Chip on FR4 Interconnections with ACA,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 595–601, June 1999. 163. Gustafsson, K., S. Mannan, J. Liu, Z. Lai, D. Whalley, and D. Williams, “The Effect of Temperature Ramp Rate on Flip-Chip Joint Quality and Reliability Using Anisotropically Conductive Adhesive on FR-4 Substrate,” IEEE/ECTC Proceedings, pp. 561–566, May 1997. 164. Watanabe, I., K. Takemura, N. Shiozawa, O. Watanabe, K. Kojima, A. Nagai, and T. Tanaka, “Anisotropic Conductive Adhesive Films for Flip-Chip Interconnection,” Proceedings of the 9th International Microelectronics Conference, pp. 328–332, Omiya, Japan, 1996. 165. Watanabe, I., N. Shiozawa, K. Takemura, and T. Ohta, “Flip Chip Interconnection Technology Using Anisotropic Conductive Adhesive Films,” in Flip Chip Technologies, Lau, J. H., ed., McGraw-Hill, New York, pp. 301–315, 1996. 166. Aschenbrenner, R., R. Miebner, and H. Reichl, “Adhesive Flip Chip Bonding on Flexible Substrates,” Proceedings of IEEE Polymeric Electronics Packaging, pp. 86–94, October 1997. 167. Wong, C. P., D. Lu, L. Meyers, S. Vona, and Q. Tong, “Fundamental Study of Electrically Conductive Adhesives (ECAs),” Proceedings of IEEE Polymeric Electronics Packaging, pp. 80–85, October 1997. 168. Lu, D., C. P. Wong, and Q. Tong, “Mechanisms Underlying the Unstable Contact Resistance of Conductive Adhesives,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 342–346, June 1999. 169. Nguyen, G., J. Williams, F. Gibson, and T. Winster, “Electrical Reliability of Conductive Adhesives for Surface Mount Applications,” Proceedings of International Electronic Packaging Conference, pp. 479–486, 1993. 170. Nguyen, G., J. Williams, and F. Gibson, “Conductive Adhesives: Reliable and Economical Alternatives to Solder Paste for Electrical Applications,” Proceedings of ISHM Symposium, pp. 510–517, 1992. 171. Li, L., and J. Morris, “Reliability and Failure Mechanism of Isotropically Conductive Adhesive Joints,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 114–120, May 1995.

1.22

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172. Chung, K., T. Devereaus, C. Monti, and M. Yan, “Z-Axis Conductive Adhesives as Solder Replacement,” Proceedings of International SAMPE Electronic Conference, vol. 7, pp. 473–481, 1994. 173. Yamaguchi, M., F. Asai, F. Eriguchi, and Y. Hotta, “Development of Novel Anitotropic Conductive Film (ACF),” Proceedings of IEEE Electronic Components and Technology Conference, pp. 360–364, June 1999. 174. Hotta, Y., “Development of 0.025 mm Pitch Anisotropic Conductive Film,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1042–1046, June 1998. 175. Dernevik, M., R. Sihlbom, K. Axelsson, Z. Lai, J. Liu, and P. Starski, “Electrically Conductive Adhesives at Microwave Frequencies,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1026–1030, June 1998. 176. Kang, S. K., and S. Purushothaman, “Development of Low Cost, Low Temperature Conductive Adhesives,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1031–1035, June 1998. 177. Yim, M., K. Paik, T. Kim, and Y. Kim, “Anisotropic Conductive Film (ACF) Interconnection for Display Packaging Applications,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1036–1041, June 1998. 178. Wei, Y., and E. Sancaktar, “A Pressure Dependent Conduction Model for Electrically Conductive Adhesives,” Proceedings of International Symposium on Microelectronics, pp. 231–236, 1955. 179. Liu, J., and R. Rorgren, “Joining of Displays Using Thermosetting Anisotropically Conductive Adhesives,” Journal of Electronics Manufacturing, 3:205–214, 1993. 180. Ito, S., M. Mizutani, H. Noro, M. Kuwamura, and A. Prabhu, “A Novel Flip Chip Technology Using Non-Conductive Resin Sheet,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1047–1051, June 1998.

CHAPTER 2

CHIP- (WAFER)- LEVEL INTERCONNECTS WITH LEAD-FREE SOLDER BUMPS 2.1

INTRODUCTION

Alternative material systems for lead-free solders1–71 are currently of intense interest in the electronics industry. This is initiated in part by the Waste Electrical and Electronic Equipment/Reduction of Hazardous Substances (WEEE/ROHS) directives and subsequently driven by Japanese electronics retailers and manufacturers in an attempt to increase European market share in advance of final legislation. In this chapter, chip- (wafer-) level interconnects with lead-free solders are discussed. Wafer bumping is the most important step in using solder-bumped flip chip technologies. The bump sizes60 may vary from 50 µm (for the conventional solderbumped flip chip technology) to as large as 500 µm [for the wafer-level redistribution solder-bumped chip-scale package (CSP)]. There are many different ways to put solder bumps on the wafer/die as reported in Ref. 60. If one accounts for cost, surface-mount technology (SMT) experience, material availability, and processing flexibility, microball mounting and paste printing are the two best methods to bump lead-free solders on the wafer/die. The only limitation is the pad pitch of the chip, which is 125 µm in mass production today. Under-bump metallurgy (UBM) is the heart of solder wafer bumping.60 If it is not properly made, then (1) during or right after reflowing the solder-bumped chip on the printed circuit board (PCB)/substrate, the chip may fall off, and (2) the solder joint quality may not be adequate after multiple reflows. In this chapter, the electroless Ni-P (phosphorus)-immersion Au, Al-NiV-Cu, and the Ti-Cu or TiW-Cu UBMs will be considered. As mentioned earlier, the most likely alternatives to tin-lead solder are the Sn-Ag family of alloys. In this chapter, Sn-Ag, Sn-Ag-Cu, Sn-Cu, Sn-Ag-Bi, and Sn-Pb chip- (wafer-) level interconnects will be considered.

2.2

UBM

There are many different UBMs, as shown in Table 2.1. However, for microball and paste-printing wafer-bumping methods, the Ti-Cu,TiW-Cu, electrolytic Ni, electroless Ni-P-immersion Au, and Al-NiV-Cu are the most commonly used UBMs. The most cost-effective UBMs are the Ni-P-immersion Au (or, in short, Ni-Au) and Al-NiV-Cu.

2.2.1

ELECTROLESS Ni-P-IMMERSION Au UBM

Figures 2.1 and 2.2 show, respectively, the 5- and 12-µm electroless Ni-Au UBMs grown on an Al pad. They are properly done and are ready for solder bumping. In 2.1 Copyright © 2003 by The McGraw-Hill Companies, Inc. Click here for terms of use.

2.2

CHAPTER TWO

TABLE 2.1 Some Well-Known UBMs* for Gold, Copper, Aluminum, Solder, and Nickel Bumps Bump Gold

Copper Aluminum Solder

Nickel

UBM

Bumping process

Cr-Cu/Au

Electroplating

Ti-Pd/Au

Electroplating

Ti-W/Au

Electroplating

Ti-Pt/Au

Electroplating

Cr-Cu

Electroplating

Al-Ni-Cu

Electroplating

Ti

Evaporating

Cr

Evaporating

Cr-Cu-Au

Evaporating/printing/mounting

Ni-Cu

Electroplating/printing/mounting

Ti-Cu

Electroplating/printing/mounting

TiW-Cu

Electroplating/printing/mounting

Ni-Au

Electroless + printing/mounting

Au-Ni-Cu-Ti

Electroplating/printing/mounting

Al-NiV-Cu

Sputtering + printing/mounting

Ni

Electroless Ni/Au

* UBM, under-bump metallurgy.

FIGURE 2.1 SEM photo of electroless Ni-P-immersion Au UBM (∼5 µm thick). (Source: Technical University of Berlin/Fraunhofer Institute IZM.)

CHIP (WAFER)-LEVEL INTERCONNECTS WITH LEAD-FREE SOLDER BUMPS

2.3

FIGURE 2.2 Electroless Ni-P-immersion Au round UBM (∼12 µm thick). (Source: Motorola.)

this section, some useful insights on Ni-Au UBM obtained by the Korea Advanced Institute of Science and Technology (KAIST) are reported.55 Unlike Ni layers prepared by vacuum deposition, the electroless deposited Ni-P is plated by hypophosphite (H2PO2). It is well known that P in the electroless Ni greatly influences the interfacial reactions with SnX solders during reflow. As expected, the intermetallic compound (IMC) formed at the interface is mainly Ni3Sn4. However, a P-rich Ni layer is also formed as a by-product of a Ni-Sn reaction between the Ni-Sn IMC and the electronless Ni layer (i.e., the P that is accumulated at the interface between the electroless Ni and IMC layer). The IMC between the electroless Ni and the 96.5Sn-3.5Ag solder, the shear strength of the lead-free solder bumps, as well as the composition and growth of the P-rich Ni layer, have been investigated in detail.55 Intermetallic compound formation is desired for cross-linking of the solder bump with the UBM metallization, and the process is characterized as self-limiting. However, excessive IMC buildup will eventually result in a loss of contact between the solder bump and the chip metal pad due to UBM consumption into the bulk solder. The process flow of the electroless Ni-P plating developed by KAIST is shown in Table 2.2. It can be seen that before plating, the wafer is cleaned and the doublezincate process is performed to remove the Al2O3 layer and to activate the Al surface on the wafer. The pad sizes are 100 × 100 µm and its pad pitch is 400 µm. The Al pad is 1 µm thick.

2.4

CHAPTER TWO

TABLE 2.2 Electroless Ni-P-Immersion Au Deposition Process on Al Pads Process

Solution

Time

Thickness

Cleaning

HNO3 50%

20 s

N/A*

Zincate pretreatment

ZnO, NaOH

20 s

N/A

Acid dipping

HNO3 50%

5s

N/A

Double zincate

ZnO, NaOH

20 s

N/A

Electroless Ni plating

NiSO4⋅6H2O NaPH2O2⋅6H2O CH3COONa Lactic acid Thiourea

20 min

5 µm

Immersion Au plating

Immersion Au solution

20 min

0.2 µm

* N/A, not applicable. Source: Korea Advanced Institute of Science and Technology (KAIST).

KAIST’s zincate solution is made of NaOH and ZnO, whose ratio has been optimized to create fine and numerous Zn particles on the Al pads. After the doublezincate process, a 5-µm electroless Ni-P UBM is formed in about 20 min. The temperature of the plating bath is controlled at 90 ± 0.5°C. Then, 0.2 µm of Au is immersed on the Ni-P UBM to prevent Ni oxidation and to enhance initial solderability. During the electroless Ni-P fabrication, the two most important parameters are the P content and plating speed. On the one hand, the low-P (≤4 wt %) electroless Ni is a crystalline structure and has many defects (e.g., high stress and hardness, as well as magnetic moment). On the other hand, the high-P (≥10 wt %) electroless Ni acts like an impurity and generates various unexpected effects on the electroless Ni. Thus, an electroless Ni with medium P content (between 4 and 10 wt %) is considered by KAIST. The plating speed affects the surface roughness of the electroless Ni. KAIST has suggested a reasonable plating rate of 0.25 µm/min. The two variables affecting the P content and plating speed are (1) the electroless Ni plating solution and (2) the pH of the plating solution. As shown in Table 2.2, NiSO4 and NaH2PO2 are, respectively, used as a Ni source and a reducing agent. Also, two complexing agents, sodium acetate (CH3COONa) and lactic acid [CH3CH(OH)COOH], are used to affect the properties of the electroless Ni. Furthermore, thiourea (H2NCSNH2) is used to stabilize the electroless Ni process. For example, Fig. 2.3 shows the effects of a complexing agent on P content and plating speed. It can be seen that when the concentration of the lactic acid increases, the P content increases and the plating rate decreases. This is due to the complexing agent, which tends to reduce the concentration of free Ni ions in plating solution.55 Figure 2.4 shows the effects of pH on P content and plating speed. It can be seen that when the pH increases, the plating speed increases and the P content decreases. Also, in order to make the P content fall into the range of between 4 and 10 wt %,

CHIP (WAFER)-LEVEL INTERCONNECTS WITH LEAD-FREE SOLDER BUMPS

FIGURE 2.3 Effects of complexing agent on P content and plating speed.

FIGURE 2.4 Effects of pH on P content and plating speed.

2.5

2.6

CHAPTER TWO

the pH must be 5 or less.Thus, KAIST has found an optimal plating combination: the plating rate is 0.25 µm/min, and the P content is 12.55 ± 0.40 at % (7.05 wt %). In this case, the average surface roughness is 437 ± 174 Å; the resistivity and hardness of the electroless Ni-P are, respectively, 70 ± 10 µΩ-cm and 500 ± 50 HV (Vicker’s hardness).

2.2.2

Al-NiV-Cu UBM

Another popular UBM (Al-NiV-Cu) is given by Flip Chip Technology (FCT). It was originally developed for wafer-level redistribution flip chip packages (Fig. 2.5), but it is applied to ordinary flip chip packages (Fig. 2.6) as well. The manufacturing processes of the wafer-level redistribution flip chip package are (1) deposit the first layer of dielectric [benzocyclobutene (BCB1)] on the wafer; (2) open windows to expose the die bond pads; (3) sputter the wafer with layers of Al, NiV, and Cu for UBM; and (4) pattern the UBM to form traces and bond pads for solder bumps. The Al-NiV-Cu UBM has been shown to be reliable and is suitable for leadfree solders.59

2.3

MICROBALL WAFER BUMPING WITH LEAD-FREE SOLDERS

Just like the solder ball mounting on the substrates of plastic ball grid array (PBGA) packages,65 the microball mounting on the chips54 of the wafer enjoys the same advantages, (e.g., high throughput, uniform bump height, and flexible solder alloy selection). The drawbacks are the tooling that is required and the availability of microball mounters. In this section, we present Nippon Steel’s microball wafer bumping of 93.5Sn-3.5Ag and 96.8Sn-2.6Ag-0.6Cu solders.

2.3.1

OVERVIEW OF MICROBALL WAFER BUMPING

The overall process of forming the UBM and lead-free solder bumps on a wafer by the microball mounting is shown in Fig. 2.7. The UBM is formed by the electroless Ni-Au process with 5 µm of Ni and 0.05 µm of Au. The flux is applied on the UBMs and the micro-solder balls are then transferred to the UBMs, as shown in Fig. 2.7. Reflow the micro-solder balls in a nitrogen atmosphere furnace, and the flux residue is removed by cleaning.

2.3.2

MICROBALL PREPARATION

Figure 2.8 shows the SEM image of the 60-µm (in diameter) 96.6Sn-3.5Ag microsolder balls. They are made from a bulk of Sn-Ag solid by cutting it into many units of specified mass that are heated and melted at a temperature that is much higher than the material’s melting point. Due to the surface tension of liquid metal of the solder, the balls can achieve a high level of sphericity. Figure 2.9 shows the diameter (size) and diameter (x and y directions) measurements of 50 of the Sn-Ag microsolder balls. It can be seen that (1) the size (diameter) variations are less than ±3 µm, and (2) the tolerances of sphericity are controlled within ±3 µm.

FIGURE 2.5 FCT’s ultra-CSP. (a) BCB1 layer after being exposed and developed, (b) thin-film UBM and redistribution layer (RDL) after being etched, (c) BCB2 layer after being exposed and developed, and (d) ultraCSP RDL and solder ball.

2.7

2.8

CHAPTER TWO

FIGURE 2.6 FCT-sputtered UBM and solder paste bumping process. (a) Sputter UBM; (b) apply photoresist, pattern and develop; (c) etch UBM; (d) print solder paste; (e) reflow solder.

FIGURE 2.7 Microball mounting process for UBMs and solder bumps.

CHIP (WAFER)-LEVEL INTERCONNECTS WITH LEAD-FREE SOLDER BUMPS

2.9

FIGURE 2.8 SEM image of 60-µm micro-solder balls (96.5Sn-3.5Ag).

2.3.3

MICROBALL MANAGEMENT

Figure 2.10 shows the process flow of microball bumping with an emphasis on microball management. By vibrating the ball container and bringing the bonding head with the arrangement (management) plate down and closer to the microballs, as shown in Fig. 2.10a, the microballs are retained in the suction holes by suction, as shown in Fig. 2.10b. It should be pointed out that since the diameter of microballs is very small, excess microballs tend to adhere to portions other than the section holes of the manage-

FIGURE 2.9 (a) 60-µm microball (96.5Sn-3.5Ag) size distribution, (b) 60-µm ball (96.5Sn-3.5Ag) diameter measured in x and y directions.

2.10

CHAPTER TWO

FIGURE 2.10 Microball mounting process.

ment plate, as shown in Fig. 2.11a. Also, since the weight of the microballs is very light, a suction leak can occur through an extremely small clearance between a normally attached ball and a suction hole. More than one microball could adhere around one suction hole (Fig. 2.11a). Furthermore, contamination and moisture content on the microball surface may cause excess microballs to adhere to the management plate, as shown in Fig. 2.11a. To remove these excess microballs and keep the normally attached ones in place, ultrasonic vibrations of the bonding head with the management plate are applied, as shown in Fig. 2.10b. The result is shown in Fig. 2.11b. A schematic diagram of the microball mounter developed by Nippon Steel is shown in Fig. 2.12.

CHIP (WAFER)-LEVEL INTERCONNECTS WITH LEAD-FREE SOLDER BUMPS

(a)

2.11

(b)

FIGURE 2.11 Excess microballs (a) adhering to the management plate and (b) perfectly attached. Microball diameter: 100 µm.

FIGURE 2.12 Schematic diagram of the microball mounter.

2.12

2.3.4

CHAPTER TWO

MICROBALL WAFER BUMPING

An 8-in test wafer containing 619 chips, each chip with 625 pads (25 × 25) on a 250µm pitch, as shown in Fig. 2.13, is solder-bumped by the microball mounting method. The wafer bumping yield is 99.995 percent, and the cycle time is 5 min. The bump height is 67.56 ± 3.5 µm, as shown in Fig. 2.14; the bump shear strength is 56.23 ± 7 gf, as shown in Fig. 2.15. Typical cross sections of the chips are shown in Fig. 2.16. It can be seen that voids are not visible. Figure 2.17 shows the top view of the 96.8Sn-2.6Ag0.6Cu and 63Sn-37Pb solder bumps with an 80-µm diameter. They look almost the same. It should be noted, however, that the IMC near the UBM is quite different for these two solders, which will be discussed in detail in the subsequent sections of this chapter. It should be emphasized that most of the wafer bumping methods60 cannot do single-point touch-up. However, just like the solder ball mounting method for the PBGA package, the microball mounting method can. By using single-ball mount equipment, the missing or damaged bumps can be repaired.54

2.4

Sn-Ag-Cu SOLDER BALL MOUNTING ON WAFERS

Hitachi also uses the microball mounting method to put the Sn-Ag-Cu solder bumps on an 8-in wafer, except that: (1) their solder ball diameter is 400 µm and larger; (2) they do wafer-level redistribution (WLR) before solder ball mounting; and (3) they put a stress-relaxation layer on the wafer prior to WLR and mounting.56 Since the bump (ball) sizes are much larger for wafer-level chip-scale packages (WLCSPs), there are many ball mounters available to perform the wafer bumping and reballing. As a matter of fact, most of the solder ball mounters (e.g., Shibuya, Vanguard, KME, Motorola, Fujitsu, Hitachi, and Toray) available today can place 300-µm solder balls.

2.4.1

WLCSP

One of the unique features of most WLCSPs is the use of a metal layer to redistribute the very fine pitch pads on the chip to much larger pitch area-arrayed pads with much bigger solder bumps, so that when the chip is attached on the PCB/substrate, it will have taller solder joints. There are more than 30 different kinds of WLCSPs60,61; however, only Hitachi’s will be considered in this section because they use the ballmounting method to bump the Sn-Ag-Cu solder balls on the wafer. Figure 2.18 shows Hitachi’s 8-in wafer with about 300 chips. The chip size is about 10 × 10 mm, and there are 54 pads. The original pads are along the centerline of the chip. After redistribution, they are in an area-array format with a minimum pitch of 0.8 mm and with 400-µm solder bumps. A schematic cross section of the WLCSP on a PCB is shown in Fig. 2.19, where the original chip pad, the WLR (interconnection) layer, and the new lands (pads) with solder bumps (joints) are visualized. Due to the very large thermal expansion mismatch between the silicon chip and the FR-4 epoxy PCB and the very little compliance of the solder joints, underfill may be needed for solder joint reliability.60–66 However, the underfill encapsulant not only increases the material cost and reduces the manufacturing throughput, it also makes the assembly very difficult to rework and recycle. Thus, alternatives are needed.

CHIP (WAFER)-LEVEL INTERCONNECTS WITH LEAD-FREE SOLDER BUMPS

FIGURE 2.13 100-µm solder bumps (a) on the 8-in wafer (b).

2.13

2.14

CHAPTER TWO

FIGURE 2.14 Height variation of microball bumps on the 8-in wafer.

FIGURE 2.15 Shear-strength variation of microball bumps on the 8-in wafer.

CHIP (WAFER)-LEVEL INTERCONNECTS WITH LEAD-FREE SOLDER BUMPS

2.15

FIGURE 2.16 Cross section of 100-µm solder bumps on Ni-Au UBM.

2.4.2

WLCSP WITH STRESS-RELAXATION LAYER

To eliminate the underfill encapsulant and ensure the solder joint reliability, Hitachi adds a stress-relaxation layer on the wafer before it is redistributed and bumped, as shown in Fig. 2.20. It can be seen that the stress-relaxation layer is between the chip and the solder bumps, and its function is to increase the compliance of the interconnects and to reduce the thermal expansion mismatch between the chip and the PCB. Also, the thick stress-relaxation layer will reduce the capacitance between the chip surface and the interconnections, which is favorable for high-frequency applications.

2.16

CHAPTER TWO

FIGURE 2.17 SEM images of 80-µm Sn-Ag-Cu (a) and Sn-Pb (b) solder bumps.

FIGURE 2.18 Hitachi’s 8-in wafer with the WPP-2 chip.

2.17

2.18

CHAPTER TWO

FIGURE 2.19 Hitachi’s wafer process package (WPP-1) attached on a PCB.

The manufacturing process of Sn-Ag-Cu solder bump mounting on wafers with a stress-relaxation layer is shown in Fig. 2.21. First, the wafer is spin-coated with a photosensitive polyimide (P-PI), and the chip pads and dicing streets are opened up by photolithography. Then, a stress-relaxation layer is formed by printing liquid resin on the wafer through a stencil mask with no openings on the pads and dicing streets. The resin will flow through the open edges and form smooth slopes. To perform wafer redistribution (i.e., to add another layer of metal on the wafer), Hitachi sputters the seed metals (Cr and Cu) on the whole wafer, spin-coats a photoresist layer, and opens up the shapes of interconnections and new pads (in areaarray format) by photolithography.Then, the interconnections and pads are formed by electroplating the Cu and Ni.The photoresist and seed metals are removed by etching. Now, the wafer is spin-coated with the P-PI again and the new chip pads and dicing streets are opened up by photolithography. This time, the P-PI acts like a solder

FIGURE 2.20 WLCSP with a stress-relaxation layer.

CHIP (WAFER)-LEVEL INTERCONNECTS WITH LEAD-FREE SOLDER BUMPS

FIGURE 2.21 Process flow of WLCSP with a stressrelaxation layer.

2.19

2.20

CHAPTER TWO

mask. After fluxing, the Sn-Ag-Cu solder bumps are placed on the new land pads on the wafer through a stencil mask with just about any solder ball mounters that are available today. Finally, the wafer is reflowed, cleaned, and diced. The effects of the stress-relaxation layer of the WLCSP on the solder joint reliability on the PCB will be considered in Chap. 3, Sec. 3.2.

2.5 STENCIL PRINTING OF Sn-Ag SOLDER ON WAFERS WITH Ni-Au UBM By using the stencil-printing method, KAIST bumps the Ni-Au UBM wafer with the 96.5Sn-3.5Ag solder.55 Their findings on the interfacial reactions between the electroless Ni and solders (96.5Sn-3.5Ag and 63Sn-37Pb) are presented here.

2.5.1

THE INTERFACE BETWEEN ELECTROLESS Ni AND SOLDERS

Figure 2.22 shows the cross section of a 96.5Sn-3.5Ag solder bumped by the stencilprinting method. The UBM is Ni-Au. The reflow time is 1 min at 250°C. It can be seen that there are four regions of interest. Region I is the 96.5Sn-3.5Ag bulk solder. Region II is the Ni3Sn4 IMC layer and has irregular shape. [There are three IMCs in the Ni-Sn binary system (i.e., Ni3Sn4, Ni3Sn2, and Ni3Sn, and they all are stable at room temperature. However, only the Ni3Sn4 phase is present in the liquid-Sn–electroless-Ni interaction.] Region III is the P-rich Ni layer and is darker than the rest of the electroless Ni. Region IV is the electroless Ni layer with a composition of 91.3 at % Ni and 8.7 at % P. The P content, which was 12.6 at % before solder reflow, decreases to 8.7 at % after soldering due to the diffusion of P atoms into the interface of the 96.5Sn-3.5Ag bulk solder. The sample is analyzed by backscattered electron image and energy-dispersive x-ray spectroscopy (EDS) and SEM. The effects of reflow time on the interface between the electroless Ni and the 63Sn-37Pb bulk solder is shown in Fig. 2.23. It can be seen that, for a very long (256 min) reflow time, discontinuous dots appear on the dark, thin, and continuous P-rich Ni layer (region III). The composition of this dot phase is 75 at % Ni–25 at % P (Ni3P, exactly 3 Ni to 1 P ratio). Before reflow, the P-rich Ni layer was 73.6 at % Ni–19.1 at % P–7.3 at % Sn. Because of the consumption of Ni with Sn, P is accumulated at the electroless Ni/IMC interface, resulting in a P-rich Ni layer. What about the 7.3 at % Sn atom before reflow? KAIST concludes that the discontinuous dot phase is the Ni3P crystalline phase, and that the thin, continuous dark layer is a metastable Ni-P phase containing Sn. Also, this discontinuous dot Ni3P phase only appears during severe reflow conditions such as a high temperature and a very long reflow time. Additional evidence of Sn diffusion into the P-rich Ni layer is the Kirkendall voids in the Ni3Sn4 IMC layer, which is just above the P-rich Ni layer. It can be seen from Figs. 2.23 and 2.24 that as the reflow time increases, the number and size of the Kirkendall voids increase, especially for the Sn-Ag solder.

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2.21

FIGURE 2.22 A typical interaction between the solder and electroless Ni-Au UBM.

Usually, the Kirkendall voids are considered to be developed in the solder (above the IMC layer) due to the Sn diffusion into the IMC layer. However, the Kirkendall voids in Figs. 2.23 and 2.24 are in the Ni3Sn4 IMC layer, which indicates that the Sn atom is a faster diffusion element than Ni or P during reflow reaction. Sn atoms are detected up to the bottom of the P-rich Ni layer and then disappear at the electroless Ni layer. Thus, the electroless Ni layer can be a good Sn diffusion barrier.

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CHAPTER TWO

FIGURE 2.23 Interfacial reactions at the electroless Ni-Au UBM and 63Sn-37Pb bulk solder at different reflow times. (a) 250°C, 1 min; (b) 250°C, 16 min; (c) 250°C, 256 min.

2.5.2

GROWTH OF THE IMC AND P-RICH Ni LAYER

Again, the 96.5Sn-3.5Ag and 63Sn-37Pb solders on electroless Ni UBM are considered, except that the reflow temperature is 250°C for 96.5Sn-3.5Ag solder and 210°C for 63Sn-37Pb solder. The focus is on the growth of the Ni3Sn4 IMC layer and the P-rich Ni layer for different reflow times. It has been known that the longer the reflow times, the larger the growth rate and that these layers can have an undesirable effect, resulting in a serious degradation of solder joint reliability. Figure 2.25 shows the growth rate of the Ni3Sn4 IMC layer and the P-rich Ni layer for reflow times1/2. It can be seen that (1) for both solders, the thickness of the Ni3Sn4 IMC and P-rich Ni layers increases as the reflow time increases; (2) for both solders, the growth rate of the Ni3Sn4 IMC layer and the P-rich Ni layer is the largest during the first minute; (3) for both solders, the thickness of the Ni3Sn4 IMC is larger than that of the P-rich Ni layers; and (4) for the same reflow time, the thickness of the

FIGURE 2.24 Kirkendall voids. (a) For Sn-Pb solder, reflow at 250°C for 4 min; (b) for Sn-Ag solder, reflow at 250°C for 256 min.

FIGURE 2.25 Growth of Ni3-Sn4 IMC and P-rich Ni layer as a function of reflow time1/2.

2.23

2.24

CHAPTER TWO

TABLE 2.3 Effects of Reflow Time on the IMC* and P-Rich Ni Layer IMC

P-rich Ni layer (µm)

Reflow time (min) Solder

1

8

Reflow time (min) 1

8

63Sn-37Pb

1.02

1.47

0.18

0.238

96.3Sn-3.7Ag

1.38

3.73

0.203

0.501

* IMC, intermetallic compound.

Ni3Sn4 IMC and P-rich Ni layers in the 96.5Sn-3.5Ag solder bump is larger than that in the 63Sn-37Pb solder joint.The last item is expected since 96.5Sn-3.5Ag solder has more Sn content, and above all, it is reflowed at 40°C higher than the 63Sn-37Pb solder.Table 2.3 summarizes the thickness of the Ni3Sn4 IMC and P-rich Ni layers in the 96.5Sn-3.5Ag and 63Sn-37Pb solders at 1 and 8 min.

2.5.3

BUMP SHEAR FRACTURE SURFACE

The solder bumps shown in Fig. 2.26 are subjected to shear tests. The effect of reflow times (1 to 16 min) on the shear strength of the Sn-Ag and Sn-Pb solder

FIGURE 2.26 Screen-printed solder bumps with the electroless Ni-Au UBM.

CHIP (WAFER)-LEVEL INTERCONNECTS WITH LEAD-FREE SOLDER BUMPS

FIGURE 2.27 Backscattered SEM images of a sheared Sn-Pb solder bump, reflowed at 250°C. (a) 1 min, (b) 4 min, (c) 16 min.

2.25

2.26

CHAPTER TWO

bumps is not significant since the fracture surface is in the bulk solder. Also, for the 1-min reflow time (close to the real situation) as well as the reflow temperature (210°C for the 63Sn-37Pb solder bumps and 250°C for 93.5Sn-3.5Ag solder bumps), the shear fracture surfaces are in the bulk solder and nothing special happens. However, for the 63Sn-37Pb solder bumps, reflowed at 250°C for the 16-min reflow time, then the brittle fracture occurs at the Ni3Sn4 IMC region, as shown in Fig. 2.27. Also, the Kirkendall voids are found at the fractured Ni3Sn4 surface, as shown in Fig. 2.28. Thus, the growth of the IMCs, the P-rich Ni layer, and the Kirkendall voids must be controlled in order to prevent the brittle fracture at the electroless Ni/solder bump. But this is not the real reflow condition.

FIGURE 2.28 (a) Magnified image of Fig. 2.27c, (b) top view of Fig. 2.27c.

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2.27

2.6 STENCIL PRINTING OF Sn-Cu, Sn-Ag-Bi, AND Sn-Ag-Cu SOLDERS ON WAFERS WITH Ni-Au UBM Stencil printing of ultrafine mesh (Type 5, −500/+650) lead-free solders (e.g., 99.3Sn0.7Cu, 96.5Sn-3.5Ag, 96Sn-2Ag-2Bi, and 95.5Sn-3.8Ag-0.7Cu) on wafers with electroless Ni-Au and Ti-Cu or TiW-Cu UBM have been studied extensively by Motorola. Some of their useful results are presented in this and the following sections.

2.6.1

INTERFACE OF REFLOWED SOLDER BUMPS

By using their (Motorola’s) own optimized printing process,57, 58 some typical cross sections for the 99.3Sn-0.7Cu, 96.5Sn-3.5Ag, 96Sn-2Ag-2Bi, and 95.5Sn-3.8Ag-0.7Cu lead-free solder bumps are shown in Figs. 2.29 and 2.30. They are obtained after two times of reflow at 260°C. The microstructures are revealed using an etchant of 10 percent HCl and 90 percent methanol for a few seconds. Detailed morphology of the solder-UBM is revealed by using 4 parts glycerol + 1 part acetic acid + 1 part nitric acid at 80°C for a few seconds. This etchant removes the solder and leaves the IMC interface that can be characterized by SEM and EDX. Two types of intermetallics are of interest. One is at the solder-UBM interface and the other is in the bulk of the solder. Blocky-type interfacial intermetallics formed between the solder and the electroless Ni-P UBM. In the bulk solder, larger

FIGURE 2.29 SEM images of various lead-free solder bumps (reflowed twice at 260°C) with electroless Ni-P-immersion Au UBM. (a) Sn-0.7Cu, (b) Sn-3.5Ag, (c) Sn-3.8Ag-0.7Cu, and (d) Sn-2Ag-2Bi.

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CHAPTER TWO

FIGURE 2.30 Magnified SEM images of Fig. 2.29. (a) Sn-0.7Cu, (b) Sn-3.5Ag, (c) Sn-3.8Ag-0.7Cu, and (d) Sn-2Ag-2Bi.

intermetallic particles such as Ag3Sn and Cu6Sn5 are formed. Table 2.4 summarizes the observed IMC. It can be seen that the composition of intermetallics is primarily dependent on the solder alloy composition. There are no large intermetallics observed in the Sn-2Ag-2Bi solder. However, there is a significant difference observed between the Cu-containing solder alloys (Figs. 2.29a and c, and 2.30a and c) and those without Cu (Figs. 2.29b and d, and 2.30b and d). The Cu-containing solders (Sn-0.7Cu and Sn-3.8Ag-0.7Cu) have interfacial IMC with a Ni4Cu7Sn6 ternary composition. The solders without Cu (Sn-3.5Ag and Sn-2Ag-2Bi) have a binary compound of Ni3Sn4, similar to that found in the soldering reaction between Sn-containing solder and electroless Ni UBM. The presence of Cu in the solder also

TABLE 2.4 IMC in Some Lead-Free Solders on Electroless Ni-P-Immersion Au UBM

Solder alloys

Interfacial intermetallics

Large intermetallics inside the solder

99.3Sn-0.7Cu

Sn-Cu-Ni

Cu6Sn5

96.5Sn-3.5Ag

Ni3Sn4

Ag3Sn

95.5Sn-3.8Ag-0.7Cu

Sn-Cu-Ni

Ag3Sn

96Sn-2Ag-2Bi

Ni3Sn4

No large intermetallics

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2.29

affected the adhesion of the interfacial IMC. In the Cu-containing solder alloy bumps, the interfacial IMC (Sn-Cu-Ni) adhered well to the electroless Ni-P UBM, whereas those without Cu (the needle-type Ni3Sn4 compound) lost adhesion and spalled off into solder.

2.6.2

INTERFACE OF ANNEALED SOLDER BUMPS

Figure 2.31 shows the cross-sectional SEM micrographs of the 99.3Sn-0.7Cu, 96.5Sn-3.5Ag, 96Sn-2Ag-2Bi, and 95.5Sn-3.8Ag-0.7Cu lead-free solder bumps obtained by Motorola.57,58 They are obtained after two times of reflow at 260°C and annealed at 150°C for 1000 h. For the Cu-containing solder alloys (Fig. 2.31a and c), the Ni-Cu-Sn IMCs grew to a small extent. The interfacial compound (Ni3Sn4) of the solders without Cu (Fig. 2.31b and d) did not spall into the solder. The large IMCs of Ag3Sn and Cu6Sn5 are unchanged during solid-state annealing. It appears that the interfacial IMCs in the Cu-containing solders are more uniform and stable than those that form in alloys that contain no Cu. Figure 2.32 shows the cross-sectional SEM images of the edge of a 95.5Sn-3.5Ag on a Ni-P bump. The Ni3Sn4 IMC grows extensively near the edge of the UBM, and fracture occurs at this location. The fracture is coincident with the region of excessive IMC growth.

FIGURE 2.31 SEM images of various lead-free solder bumps (reflowed twice at 260°C and annealed at 150°C for 1000 hours) with electroless Ni-P-immersion Au UBM. (a) Sn-0.7Cu, (b) Sn3.5Ag, (c) Sn-3.8Ag-0.7Cu, and (d) Sn-2Ag-2Bi.

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CHAPTER TWO

FIGURE 2.32 SEM images showing the breakage of the edge of electroless Ni-Pimmersion Au UBM. (a) Sn-3.5Ag solder, 10 reflows at 260°C and annealed at 170°C for 1000 h; (b) enlarged image of the circled region in (a).

2.6.3

SHEAR STRENGTH OF SOLDER BUMPS

Shear tests are applied to solder bumps 115 to approximately 135 µm in height and 130 to approximately 150 µm in diameter by Motorola.57,58 The shear blade tip is set to 30 µm above the land pads. Multiple reflows, from 2 to 10, and high-temperature storages at 125°C, 150°C, and 170°C are also performed. The shear tests are performed 7 days after reflow or temperature storage to minimize variation due to room temperature age-softening. Figure 2.33 shows the solder bump shear test results. It can be seen that both Sn-3.5Ag and Sn-3.8Ag-0.7Cu solder bump shear strengths are lower after the second thermal exposure but are not affected by subsequent multiple reflows. The Sn-37Pb and Sn-0.7Cu solder bump shear strengths are basically unchanged after either multiple reflows or high-temperature storage. There does

FIGURE 2.33 Shear test force (strength) after multiple reflows and high-temperature storage.

CHIP (WAFER)-LEVEL INTERCONNECTS WITH LEAD-FREE SOLDER BUMPS

2.31

not appear to be a correlation between multiple reflows and thermal annealing– induced IMCs and microstructural evolution and the solder bump shear strength. The shear fractures are predominantly through the bulk solder for all of the solder alloys.

2.7 STENCIL PRINTING OF Sn-Cu, Sn-Ag-Bi, AND Sn-Ag-Cu SOLDERS ON WAFERS WITH Ti-Cu UBM Today, most of the wafers are with Al conductor lines and land pads. However, semiconductor leaders (e.g., IBM, Motorola, Intel,TSMC, UMC, and TI) are beginning to use Cu conductor lines and land pads.

2.7.1

INTERFACE OF REFLOWED SOLDER BUMPS

Again, some typical cross sections for the 99.3Sn-0.7Cu, 96.5Sn-3.5Ag, 95.5Sn3.8Ag-0.7Cu, and 63Sn-37Pb solder bumps on the Ti-Cu or TiW-Cu (or simply Cu) UBM obtained by Motorola57,58 are shown in Fig. 2.34. They are obtained after two times of reflow at 260°C. The initial Cu UBM is 13 to 15 µm thick. The Cu6Sn5 IMC has good adhesion with the Cu UBM for all solders. However, a slightly different morphology with respect to solder compositions is observed. Table 2.5 summarizes the IMC that is found in these solders on the electroplated Cu UBM. Similar to electroless Ni-P UBM, the IMCs are primarily dependent on the solder composition. The difference is that both Cu6Sn5 and Ag3Sn IMCs are present in Sn-3.8Ag-0.7Cu solder-Cu UBM, whereas there is only Ag3Sn IMC present in the Sn-3.8Ag-0.7Cu solder-Ni-P UBM. This is due to a greater supply of Cu from the Cu UBM during reflow.

2.7.2

INTERFACE OF ANNEALED SOLDER BUMPS

Figure 2.35 shows the cross-sectional SEM micrographs of eutectic Sn-Pb and three lead-free solders on the electroplated Cu UBM after they have been reflowed twice at 260°C and annealed at 150°C for 1000 h. The intermetallics grow extensively compared with the as-reflowed samples shown in Fig. 2.34. The intermetallics change from a blocky morphology to a rather planar type. This suggests that the IMC growth mechanism in the liquid state differs from that in the solid state. The blocky

TABLE 2.5 IMC in Some Lead-Free Solders on Electroplated Cu UBM

Solder alloys

Interfacial intermetallics

Large intermetallics inside the solder

Eutectic SnPb

Cu6Sn5/Cu3Sn

No large compound

99.3Sn0.7Cu

Cu6Sn5/Cu3Sn

Cu6Sn5

96.5Sn3.5Ag

Cu6Sn5/Cu3Sn

Ag3Sn

95.5Sn3.8Ag0.7Cu

Cu6Sn5/Cu3Sn

Ag3Sn & Cu6Sn5

2.32

CHAPTER TWO

FIGURE 2.34 SEM images of various solder bumps (reflowed twice at 260°C) with Cu UBM. (a) Sn-37Pb, (b) Sn-0.7Cu, (c) Sn-3.5Ag, and (d) Sn-3.8Ag-0.7Cu.

FIGURE 2.35 SEM images of various solder bumps (reflowed twice at 260°C and annealed at 150°C for 1000 hours) with Cu UBM. (a) Sn-37Pb, (b) Sn-0.7Cu, (c) Sn-3.5Ag, and (d) Sn3.8Ag-0.7Cu.

FIGURE 2.36 FCT’s 8-mil pitch full-array solder bumps. (a) Wafer, (b) close-up.

2.33

2.34

CHAPTER TWO

FIGURE 2.37 FCT’s ultra-CSP on a laminate substrate.

morphology may indicate that the growth of intermetallics can be achieved by a ripening process as well as an interfacial reaction.57,58 The planar type of intermetallic may be a result of primarily interfacial reaction. This morphology change has been reported in other lead-free solders, such as the Sn-Sb alloy.57,58

2.8 PASTE PRINTING OF SOLDERS ON WAFERS WITH Al-NiV-Cu UBM In Sec. 2.2.2, the first four steps showing how the Al-NiV-Cu UBM is made by the flip chip technology division of K & S have been presented. The next step is to deposit the second layer of dielectric to cover the UBM layer.59 Then, open windows to define the solder bump attachment area. After depositing lead-free solder paste of any kind on the land pads, reflow and clean the solder bumps. Figure 2.36 shows the Sn-Ag-Cu solder bumps, and Fig. 2.37 shows a typical cross section of the leadfree solder-bumped flip chip on a substrate. Their solder joint reliability will be discussed in Chap. 3.

ACKNOWLEDGMENTS The authors would like to thank C. Kallmayer, H. Oppermann, S. Ankock, R. Azadeh, R. Aschenbrenner, and H. Reichl of the Technical University of Berlin and Fraunhofer Institute IZM; J. Lin, A. De Silva, D. Frear, Y. Guo, J. Jang, L. Li, D. Mitchell, B. Yeung, C. Zhang, and Y. Rao of Motorola; Y. Jeon and K. Paik of KAIST; K. Bok, W. Choi, and C. Cho of Samsung; P. Elenius, H. Balkan, D. Patterson, G. Burgess, C. Carlson, M. Johnson, B. Rooney, J. Sanchez, D. Stepniak, and J. Wood of Flip Chip Technology; E. Hashino, K. Shimokawa, Y. Yamamoto, and K. Tatsumi of Nippon Steel; and A. Kazama, T. Satch, Y. Yamaguchi, I. Anjoh, and

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A. Nishimura of Hitachi for sharing their important and useful technology with the industry.

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21. Massiot, M., et al., “Lead-free Solder BGAs and Polymer Stud Grid Arrays,” Proceedings of Electronics Goes Green 2000+, Berlin, pp. 93–98, 2000. 22. Melton, C., et al., “Lead-Free Solder Fine Pitch Stencil Printing,” Proceedings of Surface Mount International, pp. 730–735, 1996. 23. Miric, A. Z., and W. C. Heraeus, “Lead-free Soldering: Legislation, Projects, Alternatives, Outlook,” Proceedings of Electronics Goes Green 2000+, Berlin, pp. 31–36, 2000. 24. Miyazawa, Y., and T. Ariga, “Microstructural Change and Hardness of Lead Free Solder Alloys,” Proceedings of EcoDesign ’99, pp. 616–619, 1999. 25. Napp, D., “NCMS Lead-Free Electronic Interconnect Program,” Proceedings of Surface Mount International, pp. 425–432, 1994. 26. NCMS, “Lead-Free Solder Project Final Report,” NCMS report 0401RE96, Ann Arbor, MI, 1997. 27. Nimmo, K., “Review of Current Issues in Lead-Free Soldering,” Proceedings of Surface Mount International, pp. 467–475, 1997. 28. Nimmo, K., “Environmental Issues in Electronics and the Transition to Lead-free Soldering,” Proceedings of SMTA International, pp. 371–377, 1999. 29. Nimmo, K., “A Review of the Environmental Issues in Electronics and the Challenge of Lead-free Soldering,” Proceedings of Electronics Goes Green 2000+, Berlin, pp. 43–50. 30. Ray, U., “Assessment of Circuit Board Surface Finishes for Electronic Assembly with Lead-Free Solders,” Proceedings of Surface Mount International, pp. 656–668, 1996. 31. Rosser, J. G., “NCMS Lead-Free Solder Project—Executive Summary,” Proceedings of IPC Printed Circuits Expo, pp. (S4) 1–3, 1997. 32. Rubin, H., “Alternate Interconnect Methods Using Conductive Adhesives,” Proceedings of Surface Mount International, pp. 748–752, 1993. 33. Suganuma, K., “Developments in Lead Free Soldering,” J. JIPC, 12(2):83, 1997. 34. Shangguan, D., and A. Achari, “Lead-Free Solder Development for Automotive Electronics Packaging Applications,” Proceedings of Surface Mount International, pp. 423–428, 1995. 35. Smith, E. B., and L. K. Swanger, “Lead Free Solders—A Push in the Wrong Direction?” Proceedings of IPC Printed Circuits Expo, pp. (F-10) 1–6, 1999. 36. Smith, E., and K. Swanger, “Environmental Impact of Lead-free Solders,” Surface Mount Technology, pp. 74–79, July 1999. 37. Socolowsk, N., “Lead-Free Alloys and Limitations for Surface Mount Assembly,” Proceedings of Surface Mount International, pp. 447–480, 1995. 38. Stuart, J. A., et al., “Towards Quantifying the Effect of Lead Legislation on Electronic Product and Process Design,” Proceedings of IPCWorks ’97, pp. (S03-7) 1–4, 1997. 39. Suga, T., “Trend of Lead-free Soldering in Japan—A Report from NEDO Project 1999–2000,” Proceedings of Electronics Goes Green 2000+, Berlin, pp. 149–154, 2000. 40. Suganuma, K., “Interface Phenomena in Lead-Free Soldering,” Proceedings of EcoDesign ’99, pp. 620–625, 1999. 41. Suganuma, K., and C. W. Hwang, “High Temperature Stability of Lead-free Soldering Interfaces,” Proceedings of Electronics Goes Green 2000+, Berlin, pp. 67–72, 2000. 42. Takemoto, T., “Lead-free Solder and Micro-jointing,” Materia, The Japan Institute of Metals, 35(4):320–325, 1996. 43. Takemoto, T., “Toward Defects-free in Lead-Free Micro-Soldering,” Proceedings of EcoDesign ’99, pp. 979–984, 1999. 44. Tsunematsu, T., et al., “Evaluation of Pb-Free Solders for Adaptability to Various Soldering Processes,” Proceedings of EcoDesign ’99, pp. 610–614, 1999. 45. Turbini, L., et al., “Examining the Environmental Impact of Lead-Free Soldering Alternatives,” Proceedings of IEEE, International Symposium on Electronics and the Environment, pp. 46–53, 2000.

CHIP (WAFER)-LEVEL INTERCONNECTS WITH LEAD-FREE SOLDER BUMPS

2.37

46. Turbini, L., et al., “Assessing the Environmental Implications of Lead-Free Soldering,” Proceedings of Electronics Goes Green 2000+, Berlin, pp. 37–42, 2000. 47. Vardaman, J., and P. Spletter, “Lead-free Product Developments in Japan,” Proceedings of Electronics Goes Green 2000+, Berlin, pp. 155–158, 2000. 48. Vianco, P. T., and C. May, “An Evaluation of Prototype Surface Mount Circuit Board Assembled with Three Non-Lead Bearing Solders,” Proceedings of Surface Mount International, pp. 481–494, 1995. 49. Vianco, P. T., et al., “Reliability Studies of Surface Mount Boards Manufactured with LeadFree Solders,” Proceedings of Surface Mount International, pp. 437–448, 1994. 50. Vianco, P. T., “Development of Alternatives to Lead-Free Solder,” Proceedings of Surface Mount International, pp. 725–731, 1993. 51. Warashina, K., et al., “Thermal Fatigue Damage of Quad Flat Pack Leads and Sn-3.5 Ag-X (X = Bi and Cu) Solder Joints,” Proceedings of EcoDesign ’99, pp. 626–631, 1999. 52. Yanada, I., “Electroplating of Lead-Free Solder Alloys Composed of Sn-Bi and Sn-Ag,” Proceedings of IPC Printed Circuits Expo, pp. (S11-2) 1–7, 1998. 53. Zhang, Y., et al., “An Alternative Surface Finish for Tin/Lead Solders: Pure Tin,” Proceedings of Surface Mount International, pp. 641–649, 1996. 54. Hashino, E., K. Shimokawa, Y. Yamamoto, and K. Tatsumi, “Micro-Ball Wafer Bumping for Flip Chip Interconnection,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 957–964, May 2001. 55. Jeon, Y., K. Paik, K. Bok, W. Choi, and C. Cho, “Studies on Ni-Sn Intermetallic Compound and P-Rich Nie Layer at the Electroless Ni UBM—Solder Interface and Their Effects on Flip Chip Solder Joint Reliability,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 69–75, May 2001. 56. Kazama, A., T. Satoh, Y. Yamaguchi, I. Anjoh, and A. Nishimura, “Development of Lowcost and Highly Reliable Wafer Process Package,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 40–46, May 2001. 57. Zhang, C., J. Lin, and Li Li, “Thermal Fatigue Properties of Lead-free Solders on Cu and NiP Under Bump Metallurgies,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 463–470, May 2001. 58. Lin, J., A. De Silva, D. Frear, and Y. Guo, “Characterization of Lead-Free Solders and Under Bump Metallurgies for Flip-Chip Package,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 455–462, May 2001. 59. Balkan, H., D. Patterson, G. Burgess, C. Carlson, P. Elenius, M. Johnson, B. Rooney, J. Sanchez, D. Stepniak, and J. Wood, “Flip-Chip Reliability: Comparative Characterization of Lead Free (Sn/Ag/Cu) and 63Sn/Pb Eutectic Solder,” Proceedings of International Microelectronic Packaging, October 2001. 60. Lau, J. H., Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, McGraw-Hill, New York, 2000. 61. Lau, J. H., and S. W. R. Lee, Chip Scale Package, Design, Materials, Process, Reliability, and Applications, McGraw-Hill, New York, 1999. 62. Lau, J. H., C. Wong, J. L. Prince, and W. Nakayama, Electronic Packaging, Design, Materials, Process, and Reliability, McGraw-Hill, New York, 1998. 63. Lau, J. H., and Y.-H. Pao, Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGraw-Hill, New York, 1997. 64. Lau, J. H., Flip Chip Technologies, McGraw-Hill, New York, 1996. 65. Lau, J. H., Ball Grid Array Technology, McGraw-Hill, New York, 1995. 66. Lau, J. H., Chip On Board Technologies for Multichip Modules, Van Nostrand Reinhold, New York, 1994. 67. Lau, J. H., Handbook of Fine Pitch Surface Mount Technology, Van Nostrand Reinhold, New York, 1994.

2.38

CHAPTER TWO

68. Frear, D., H. Morgan, S. Burchett, and J. Lau, The Mechanics of Solder Alloy, Van Nostrand Reinhold, New York, 1994. 69. Lau, J. H., Thermal Stress and Strain in Microelectronics Packaging, Van Nostrand Reinhold, New York, 1993. 70. Lau, J. H., Handbook of Tape Automated Bonding, Van Nostrand Reinhold, New York, 1992. 71. Lau, J. H., Solder Joint Reliability, Theory and Applications, Van Nostrand Reinhold, New York, 1991.

CHAPTER 3

WLCSP WITH LEAD-FREE SOLDER BUMPS ON PCB/SUBSTRATE 3.1

INTRODUCTION

The solder joint reliability of various wafer-level chip-scale packages (WLCSPs) on organic printed circuit board (PCB)/substrate is the focus of discussion in this chapter,1–117 since the compliance of lead-free solder joints is so small and the thermal expansion mismatch between the silicon chip and epoxy PCB/substrate is so large. Specifically, the useful thermal cycling test and modeling results provided by Hitachi, Motorola, and Flip Chip Technology are presented in this chapter. It should be noted that the surface-mount technology (SMT) assembly of lead-free solderbumped WLCSPs on PCB/substrate will be discussed in Chaps. 11 through 16. In this chapter, the solders on the chip before it is joined to the substrate are called solder bumps. After the solder bumps have been reflowed on the PCB/substrate, they are called solder joints.

3.2 SOLDER JOINT RELIABILITY OF SnAgCu WLCSP WITH A STRESS-RELAXATION LAYER The effects of WLCSP stress-relaxation layer on the SnAgCu solder joint reliability and high-frequency applications have been determined by Hitachi,114 whose useful results are presented in this section.

3.2.1

FINITE ELEMENT RESULTS

The finite element analysis model of Hitachi’s SnAgCu WLCSP with a stressrelaxation layer on a PCB (Fig. 2.20) is shown in Fig. 3.1. Due to double symmetries, only one-fourth of the structure is modeled. The distance from the neutral point (DNP) to a corner solder joint is 4.7 mm, as shown in Table 3.1, where information on chip size, pin layout, and the PCB are also given. The thermal cycling is between −55 and +125°C. Figure 3.2 shows the finite element analysis result in terms of the plastic strain distribution around the corner solder joint.The maximum plastic strain occurs inside the corner solder joint near the interface of the solder joint and the land pad. By choosing the right material for the stress-relaxation layer (as shown in Fig. 3.3) and the correct solder joint geometry (as shown in Fig. 3.4), an optimal structure can be achieved. Table 3.2 shows the material properties of three of the stress-relaxation layers considered by Hitachi. 3.1 Copyright © 2003 by The McGraw-Hill Companies, Inc. Click here for terms of use.

3.2

CHAPTER THREE

FIGURE 3.1 Three-dimensional finite element model of Hitachi’s WLCSP with a stress-relaxation layer.

3.2.2

THERMAL CYCLING RESULTS

In order to determine the performance of these three materials for the stressrelaxation layer under thermal cycling condition, a simpler structure as shown in Fig. 3.5 is constructed. Two different thicknesses of the stress-relaxation layer are considered—75 and 100 µm—as shown in Table 3.3. Figure 3.6 and Table 3.3 show the thermal cycling (−55 and +125°C) test results for samples 1, 2, and 4. It can be seen that sample 4 (resin A at 100 µm thick) gives the best result and sample 2 (resin B at TABLE 3.1 Structural Parameters of Hitachi’s WLCSP Chip Pin layout

Solder Motherboard

Size

10 × 10 mm

Thickness

0.725 mm

Number of bumps

54 (9 × 6)

Bump pitch

0.8 mm (minimum)

DNP

4.7 mm

Material

SnAgCu

Ball diameter

400 µm

Material

FR-4

Thickness

1.27 mm

WLCSP WITH LEAD-FREE SOLDER BUMPS ON PCB/SUBSTRATE

3.3

FIGURE 3.2 Deformation of the corner solder joint.

75 µm thick) yields the worst. Even sample 1 (resin A at 75 µm thick) is not as good as sample 4; however, it is quite close to sample 4 and gives reasonably good results. A typical failure mode at 2250 cycles is shown in Fig. 3.7. It can be seen that the failure location is in the corner solder joint, near the interface between the SnAgCu bulk solder and the stress-relaxation layer.

FIGURE 3.3 Effects of stress-relaxation layer thickness and modulus on the deformation of the corner solder joint.

3.4

CHAPTER THREE

FIGURE 3.4 Effects of stress-relaxation layer thickness and pad geometry on the deformation of the corner solder joint.

Another thermal cycling (−55 and +125°C) test result shows that the solder joints are not reliable if there is no underfill and no stress-relaxation layer, as shown in Fig. 3.8. It can be seen that the joints without the underfill and stress-relaxation layer failed at around 100 cycles. However, those with a 75-µm-thick stress-relaxation layer lasted for more than 2000 cycles. Thus, with the stress-relaxation layer, the solder joints are reliable even without underfill encapsulant. This is because the stressrelaxation layer increases the compliance of the solder joints between the chip and PCB.

3.2.3 EFFECTS OF THE STRESS-RELAXATION LAYER ON CAPACITANCE Figure 3.9 shows a simple geometric model for the calculation of the capacitance of the (longest) interconnection and land pad with a stress-relaxation layer on the wafer. The results are shown in Fig. 3.10 for various thicknesses of the stressrelaxation layer. It can be seen that the capacitance drops from 1.4 pF (without a stress-relaxation layer) to below 0.3 pF (with a 75-µm-thick stress-relaxation layer), which is ideal for high-frequency applications.

TABLE 3.2 Mechanical Properties of Stress-Relaxation Layer Young’s modulus MPa 125°C

CTE (×10−6/°C)

Glass transition temperature (°C)

900

800

92

191

2000

1500

58

221

360

176

195

Resin

−55°C

A

1200

B

2700

C

500

430

25°C

3.5

WLCSP WITH LEAD-FREE SOLDER BUMPS ON PCB/SUBSTRATE

FIGURE 3.5 Cross section of the simplified WLCSP on PCB.

3.3 SOLDER JOINT RELIABILITY OF SnAg AND SnAgCu WLCSPs WITH TiCu AND NiAu UBMs The isothermal fatigue life and thermal cycling fatigue life of SnAg and SnAgCu WLCSPs with Cu and NiAu under-bump metallurgy (UBM) on PCB have been determined by Motorola,115,116 whose useful results are presented in this section.

3.3.1

ISOTHERMAL FATIGUE TEST RESULTS

For isothermal fatigue testing, the test specimen has 28 array solder bumps on a 3.6 × 4.2-mm silicon chip and is flip chip attached to a matching silicon chip. A test system with a displacement resolution of 0.1 µm is used to conduct the test. Fatigue tests are performed at room temperature with fully reversed cyclic loading at different displacements and frequencies ranging, respectively, from 2 to 4 µm and 0.1 to 0.25 Hz. The total shear strain (= D/h) in the solder is determined from the crosshead displacement (D) and the solder joint height (h). The fatigue life (Nf 50%) is determined as the number of cycles to reach 50 percent load drop from peak load. TABLE 3.3 Thermal Fatigue Life with Different Stress-Relaxation Layers Stress-relaxation layer Sample no.

Resin

Young’s modulus at −55°C (MPa)

1

A

1200

2

B

2700

3

C

4

A

* Damaged at interconnection.

Resulting lifetime Thickness (µm)

50% fail cycles

0.1% fail cycles

75

2600

1100

75

1100

450

500

75

1700*

—

1200

100

3200

1500

3.6

CHAPTER THREE

FIGURE 3.6 Solder joint life distributions under thermal cycling (−55/125°C).

(a) Sample 1 (resin A)

(b) Sample 3 (resin C)

FIGURE 3.7 Tested samples at 2250 cycles (−55/125°C). Failure near the pad on the chip.

WLCSP WITH LEAD-FREE SOLDER BUMPS ON PCB/SUBSTRATE

FIGURE 3.8 Solder joint life distributions under thermal cycling (−55/125°C) with and without stressrelaxation layer.

FIGURE 3.9 Simple geometric model for capacitance calculation.

FIGURE 3.10 Effects of the stress-relaxation layer thickness on the capacitance.

3.7

3.8

CHAPTER THREE

The plastic strain range vs. isothermal fatigue life is plotted in Fig. 3.11 for several solder/UBM systems (SnAgCu on electroless Ni-P-immersion Au (for short, NiAu), SnPb on NiAu, SnPb on TiW/Cu (or in short, Cu), SnCu on Cu, SnCu on NiAu, and SnAg on Cu). It can be seen that the Sn0.7Cu on both Cu and NiAu has the best isothermal fatigue life of all the solder/UBM systems evaluated. Also, the data indicate that the isothermal fatigue life for Sn0.7Cu is independent of the two UBMs and the failures are through the bulk of the Sn0.7Cu solder joint as shown in Fig. 3.12. However, the fracture surfaces of both Sn3.8Ag0.7Cu and Sn37Pb solders appear to be related to the UBM, as shown in Figs. 3.13 and 3.14, respectively. Also, Fig. 3.11 shows that Sn3.8Ag0.7Cu on NiAu UBM has the shortest isothermal fatigue life. This is due to the majority of the failures occurring in the UBM intermetallic/solder interface as shown in Fig. 3.13(a). The Sn3.8Ag0.7Cu on Cu UBM shows similar isothermal fatigue life to the Sn0.7Cu solder system and shares a similar failure mode, as shown in Fig. 3.13(b). The Sn37Pb on Cu UBM has better fatigue life than on NiAu UBM but a slightly shorter fatigue life than Sn0.7Cu and Sn3.8Ag0.7Cu on Cu UBM, as shown in Fig. 3.11. Typical isothermal fatigue fracture surfaces of Sn37Pb on NiAu and Cu UBMs are shown in Fig. 3.14.

3.3.2

THERMAL CYCLING FATIGUE TEST RESULTS

Air-to-air thermal cycling testing is used to study the thermal fatigue of several solder/UBM systems by Motorola. The test chip dimensions are 12.6 × 7.46 mm. The chip has 137 pads in a mixed array of 300-µm pitch at the periphery and 225-µm pitch at the area array in the center, and is flip chip bonded to a 1-mm-thick organic substrate made of bismaleimide triazine (BT) resin and solder mask. The metal finish of the substrate is either organic solderability preservative (OSP)/Cu or NiAu/Cu. All three lead-free solders (Sn0.7Cu, Sn3.8Ag0.7Cu, and Sn3.5Ag), as well as the Sn37Pb solder, are prepared with Motorola’s custom-formulated flux (HBA2961 and HB2974)115,116 to achieve “void-free” solder joints. The paste/flux, pad finish, and reflow temperature profile used for the SMT assembly are summarized in Table 3.4. It should be noted that, in order to accelerate failures, there is no underfill or stress-relaxation layer in any of the flip chip assemblies. Figure 3.15 shows the life distribution (Weibull) plots of air-to-air thermal cycling (0 to 100°C) fatigue life for a variety of solder/UBMs. It can be seen that the SnCu0.7 solder joints on both NiAu and Cu UBMs are the most uniform (largest Weibull slope) and have the best thermal fatigue life. Also, the characteristic lives of SnCu0.7 on Cu UBM and SnCu0.7 on NiAu UBM are, respectively, 170 and 209 cycles. This variation of characteristic life is due to the difference in the standoff height (chip-tosubstrate) between these two bump/UBM structures. (The standoff height of SnCu0.7 on NiAu UBM solder joints is taller.) Figure 3.15 also shows that the SnAg3.8Cu0.7 on Cu UBM solder joints have very similar thermal fatigue characteristic lives compared to the eutectic SnPb on NiAu UBM solder joints. The SnAg3.5 on NiAu UBM solder joints have the worst thermal fatigue life. Figure 3.16 summarizes the typical thermal fatigue failure mechanisms of the Sn0.7Cu on NiAu UBM, Sn3.8Ag0.7Cu on Cu UBM, Sn3.5Ag on NiAu UBM, and Sn37Pb on NiAu UBM solder joints. It can be seen that the Sn0.7Cu solder joint fatigue failure mode is through the solder and the Sn37Pb solder joint fatigue cracks and propagates close to the solder-intermetallic interface. For Sn3.8Ag0.7Cu and Sn3.5Ag solder joints, the cracks are at the solder-intermetallic interface, and in some cases, cracks occur through the intermetallics.

WLCSP WITH LEAD-FREE SOLDER BUMPS ON PCB/SUBSTRATE

3.9

FIGURE 3.11 Isothermal fatigue life for various lead-free solders.

(a)

(b)

FIGURE 3.12 Typical isothermal fatigue failures: Sn0.7Cu on (a) Cu UBM and (b) NiPAu UBM.

3.10

CHAPTER THREE

(a)

(b)

FIGURE 3.13 Typical isothermal fatigue failures: Sn3.8Ag0.7Cu on (a) NiPAu UBM and (b) Cu UBM.

(a)

(b)

FIGURE 3.14 Typical isothermal fatigue failures: Sn37Pb on (a) Ni-P-Au UBM and (b) Cu UBM.

WLCSP WITH LEAD-FREE SOLDER BUMPS ON PCB/SUBSTRATE

3.11

TABLE 3.4 Paste/Flux, PCB Finishing, and Reflow Profile for Assembling Samples for Evaluation Lot no.

001201

002107

001202

001203

001012

Solder/UBM

SnCu/ NiP-Au

SnCu/ TiW-Cu

SnCuAg/ TiW-Cu

SnAg/ NiP-Au

SnPb/ NiP-Au

Flux/paste type

HBA296L/ SnCu0.7

HB2974/ SnCu0.7

HBA296L/ SnAg3.8Cu0.7

HBA296L/ SnAg3.5

SMQ92/ SnPb37

Board pad finish

OSP/Cu

OSP/Cu

OSP/Cu

OSP/Cu

NiAu/Cu

Reflow peak temp.

247°C

247°C

245°C

245°C

220°C

Time above liquid temp.

60 s/227°C

60 s/227°C

60 s/217°C

60 s/221°C

60 s/183°C

Figure 3.17 shows the typical thermal fatigue failure mechanisms of the Sn37Pb on Cu UBM, Sn3.5Ag on Cu UBM, and Sn0.7Cu on Cu UBM solder joints. It can be seen that the Sn37Pb on Cu UBM solder joints fail by crack formation and propagation through heterogeneous coarsened bands near the solder/UBM interface. The cracks are observed to form on the outer edge of the solder joint and propagate to the center of the joint. The surface of the solder joint remains smooth after thermal cycling, indicating that the damage is localized to the heterogeneous coarsened band. The Sn0.7Cu on Cu UBM solder joints exhibit a failure mode that differs from those of the other solder alloys studied in this section.The initiation and propagation

FIGURE 3.15 Thermal fatigue life for various lead-free solders (0 to 100°C).

3.12

CHAPTER THREE

FIGURE 3.16 Typical thermal fatigue failures of various solders (0 to 100°C).

of fatigue cracks is through the grain boundaries in the bulk solder, as shown in Fig. 3.17. The fatigue cracks initiate on the highest point of strain at the solder joint, closer to the edge of chip, then propagate across the middle of the joint toward the center of the chip. After thermal cycling testing, the surface of the solder joints is no longer smooth. The Sn0.7Cu solder deforms by grain-boundary sliding and is so compliant in thermal fatigue that it undergoes massive deformation before failing by crack propagation. The thermal fatigue cracks in the Sn3.5Ag on Cu UBM solder joints initiate and propagate through the intermetallics and at the intermetallics-solder interface. The surfaces of the solder joints also exhibit no deformation, with the damage concentrated at the solder-intermetallic interface.The microstructure of the Sn3.5Ag solder joint appears to have more and large Ag3Sn intermetallic compounds (IMCs) present, as shown in Fig. 3.17. Even the large Ag3Sn IMC may strengthen the solder bump, but it may reduce the compliance of the solder joint and thus shorten its thermal fatigue life. The thermal fatigue cracks in the Sn3.5Ag on NiAu UBM solder joints are shown in Figs. 3.18 and 3.19. It can be seen that the thermal fatigue failure mechanism of SnAg3.5 solder joint is similar to that of SnAg0.8Cu0.7. Both solder joints have had very little plastic flow before failure. The thermal fatigue cracks initiate and propa-

WLCSP WITH LEAD-FREE SOLDER BUMPS ON PCB/SUBSTRATE

FIGURE 3.17 Typical thermal fatigue failures of various solders on TiCu UBM (0 to 100°C).

3.13

3.14

CHAPTER THREE

FIGURE 3.18 Typical thermal fatigue failures of Sn3.5Ag on NiPAu UBM (a) before chemical etching and (b) after chemical etching.

gate through the intermetallics and intermetallics/solder interface. Fine colonies and dendrites are seen in the etched sample in Fig. 3.18(b). The SnAg3.5 solder joints have more Ag3Sn intermetallics than the SnAg0.8Cu0.7 solder joints. This increased amount of Ag3Sn intermetallics may have contributed to the shorter thermal fatigue life of SnAg3.5 relative to SnAg0.8Cu0.7, as discussed earlier. Figure 3.19 shows magnified photographs of fatigue crack profiles in the SnAg3.5-NiAu UBM interconnect. Figure 3.19(a) shows that fatigue cracks initiate at the corner of the solder joint and propagate through the interface of the solder and intermetallics. Figure 3.19(b) shows how the interface of solder and Ag3Sn intermetallics can serve as a focal point for crack initiation and propagation. It should be reemphasized that the results and insights presented herein are for the case where there is no underfill or stress-relaxation layer between the chip and the solder joints in the flip chip assembly. In real applications, either or both of these will ensure the WLCSP solder joint reliability.

FIGURE 3.19 Magnified images of Fig. 3.18 (Sn3.5Ag on NiPAu UBM) (a) through intermetallics near UBM and (b) through interface of bulk Ag3Sn intermetallics/solder.

WLCSP WITH LEAD-FREE SOLDER BUMPS ON PCB/SUBSTRATE

3.15

3.4 SOLDER JOINT RELIABILITY OF SnAg, SnAgCu, SnAgCuSb, AND SnAgInCu WLCSPs WITH AlNiVCu UBM The thermal fatigue life, high-temperature storage, and shear strength of various lead-free WLCSPs on ceramic substrates and on organic substrates have been studied by Flip Chip Technology,117 whose useful results are reported in this section.

3.4.1 THERMAL FATIGUE OF SnAg, SnAgCu, SnAgCuSb, AND SnAgInCu WLCSPs ON CERAMIC SUBSTRATE The thermal cycling test results of 96.3Sn3.5Ag, Sn3.5Ag0.7-1Cu, SnAgCuSb, and SnAgInCu WLCSPs with AlNiVCu UBM on ceramic substrate have been obtained by Flip Chip Technology. There is no underfill encapsulant in the assemblies. Figures 3.20 and 3.21 show the life distributions of the 96.3Sn3.5Ag, SnAgInCu, and Sn37Pb WLCSP solder joints. It can be seen that the thermal fatigue life of the Sn37Pb solder joints is better than that of 96.3Sn3.5Ag solder joint. However, the thermal fatigue life of the SnAgInCu solder joints is better than that of the Sn37Pb solder joints. Table 3.5 summarizes all the thermal cycling test results. It can be seen that the WLCSP with the SnAgCuSb lead-free solder yields the best thermal fatigue life on the ceramic substrate.

3.4.2

THERMAL FATIGUE OF SnAgCu WLCSP ON PCB

The PCB for the test specimen is made of the high glass transition temperature FR-4 epoxy with Cu-OSP finish. The chip dimensions are 5.1 × 5.1 mm with 200µm-pitch peripheral pads. The peak reflow temperature for the SnAgCu solder is 257°C with time above 240°C at approximately 30 to 35 s and time above 217°C at approximately 65 to 70 s. The underfill material is Namics 8437-2. The test conditions are shown in Table 3.6. It can be seen that the cycling condition is from −40 to 125°C. After 1000 cycles, there is no failure. The cross section of the tested specimens is shown in Fig. 3.22. It can be seen that there is no visible cracking. In order to see the failure mode sooner, some specimens without underfill were tested. As expected, these specimens failed very early; a typical fracture surface is shown in Fig. 3.23. It can be seen that the fracture plane for the SnAgCu solder joint is through the bulk solder near the UBM interface and is very similar to that of Sn37Pb solder joint.

3.4.3

HIGH-TEMPERATURE STORAGE OF SnAgCu WLCSP ON PCB

The effects of IMC formation and growth on SnAgCu solder joint reliability can be determined by high-temperature storage testing at 150°C for 1000 h as shown in

3.16

CHAPTER THREE

FIGURE 3.20 Life distributions of Sn37Pb and Sn3.5Ag solder joints on ceramic substrate.

FIGURE 3.21 Life distributions of Sn37Pb and SnAgInCu (LF-1) solder joints on ceramic substrate.

3.17

WLCSP WITH LEAD-FREE SOLDER BUMPS ON PCB/SUBSTRATE

TABLE 3.5 Thermal Fatigue Life of Lead-Free Solder Joints on Ceramic Substrate SnAg Weibull life (h)

63 SnPb

166

208

CASTIN®

SnAgCu

550

774

Weibull slope

1.52

4.0

3.3

3.3

Relative reliability

0.8

1.0

2.6

3.7

Table 3.6. After 1000 h of testing, none of the underfilled flip chip assemblies failed. A typical cross section of the tested assembly is shown in Fig. 3.24. It can be seen that while the Sn37Pb solder joints display grain coarsening, the SnAgCu solder joints are nearly unchanged. A number of nonunderfilled flip chip assemblies were also subjected to 1000 h of aging at 150°C. After the test, a pull test was performed. The fracture surface is shown in Fig. 3.25. It can be seen that the shear plane on the nonunderfilled flip chip assemblies is through the bulk solder above the IMC layer for both the SnPb and SnAgCu solder joints.

3.4.4

SHEAR STRENGTH OF SnAgCu WLCSP ON PCB

The solder joint shear force to failure (strength) of SnAgCu WLCSP on PCB can be obtained by the shear testing and is slightly higher than that of the SnPb assembly. The fracture surface, as shown in Fig. 3.26, is mostly through the bulk solder and above the IMC layer on occasion, similar to that of SnPb solder joints. A multiple reflow test was conducted on the wafer by Flip Chip Technology to demonstrate AlNiVCu UBM robustness of the SnAgCu WLCSP. It was found that the effects of multiple reflows is to slightly reduce the shear strength of the SnAgCu solder bumps for the first 6 reflows and level off by 10 reflow operations. The scanning electron microscope images of the Cu6Sn5 IMC at the UBM interface are shown in Fig. 3.27. It can be seen that: (1) the shear mode is ductile and no NiSn interaction is observed through the 10 reflow cycles; (2) The Cu6Sn5 IMC is more columnar in the AnAgCu case; and (3) although Cu6Sn5 IMC is detected following early reflow cycles in the SnPb solder joints, it is absent in the SnAgCu solder joints.

TABLE 3.6 Reliability Test Conditions Reliability Test

Conditions

Standard

−40/125°C, 1000 cycles

JEDEC Std. 22-A104-A

High-temp storage

150°C, 1000 h

JEDEC Std. 22-A103-A

Die shear

2 mm/s, 10 Kg

N/A

Thermal cycle

3.18

CHAPTER THREE

(a)

(b)

FIGURE 3.22 Typical cross section of (a) SnAgCu and (b) SnPb solder joints after 1000 thermal cycles (−40 to 125°C).

(a)

(b)

FIGURE 3.23 Typical fracture surface (through the bulk solder) of both (a) SnAgCu and (b) SnPb solder joints without underfill after thermal cycling (−40 to 125°C).

(a)

(b)

FIGURE 3.24 Typical cross section of (a) SnAgCu and (b) SnPb solder joints after 1000 h of hightemperature storage (150°C).

WLCSP WITH LEAD-FREE SOLDER BUMPS ON PCB/SUBSTRATE

(a)

3.19

(b)

FIGURE 3.25 Typical pull test fracture surface (through bulk solder) of (a) SnAgCu and (b) SnPb solder joints without underfill after 1000 h of high-temperature storage (150°C).

(a)

(b)

FIGURE 3.26 Typical shear test fracture surface (through bulk solder) of (a) SnAgCu and (b) SnPb solder joints without underfill.

(a)

(b)

FIGURE 3.27 Typical IMC (Cu6Sn5) at the interface for the SnAgCu solder bump: (a) no reflows, (b) 10 reflows.

3.20

CHAPTER THREE

ACKNOWLEDGMENTS The authors would like to thank A. Kazama, T. Satch, Y. Yamaguchi, I. Anjoh, and A. Nishimura of Hitachi; J. Lin, A. De Silva, D. Frear, Y. Guo, J. Jang, Li Li, D. Mitchell, B. Yeung, C. Zhang, and Y. Rao of Motorola; and P. Elenius, H. Balkan, D. Patterson, G. Burgess, C. Carlson, M. Johnson, B. Rooney, J. Sanchez, D. Stepniak, and J.Wood of Flip Chip Technology for sharing their important and useful knowledge with the industry.

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27. Naguyen, L., L. Hoang, P. Fine, Q. Tong, B. Ma, R. Humphreys, A. Savoca, C. P. Wong, S. Shi, M. Vincent, and L. Wang, “High Performance Underfills Development—Materials, Processes, and Reliability,” IEEE 1st International Symposium on Polymeric Electronics Packaging, pp. 300–306, Norrkoping, Sweden, October 1997. 28. Erickson, M., and K. Kirsten, “Simplifying the Assembly Process with a Reflow Encapsulant,” Electronic Packaging and Production, 81–86, February 1997. 29. Wong, C. P., M. B. Vincent, and S. Shi, “Fast-Flow Underfill Encapsulant: Flow Rate and Coefficient of Thermal Expansion,” Proceedings of the ASME—Advances in Electronic Packaging, 19-1:301–306, 1997. 30. Wong, C. P., S. H. Shi, and G. Jefferson, “High Performance No Flow Underfills for LowCost Flip-Chip Applications,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 850–858, San Jose, CA, May 1997.

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31. Tummala, R., E. Rymaszewski, and A. Klopfenstein, Microelectronics Packaging Handbook, Chapman & Hall, New York, 1997. 32. Lau, J. H., C. Chang, and R. Chen, “Effects of Underfill Encapsulant on the Mechanical and Electrical Performance of a Functional Flip Chip Device,” Journal of Electronics Manufacturing, 7(4):269–277, December 1997. 33. Lau, J. H., and C. Chang, “How to Select Underfill Materials for Solder Bumped Flip Chip on Low Cost Substrates,” Proceedings of the International Symposium on Microelectronics, 693–700, San Diego, CA, November 1998. 34. Nguyen, L., C. Quentin, P. Fine, B. Cobb, S. Bayyuk, H. Yang, and S. A. Bidstrup-Allen, “Underfill of Flip Chip on Laminates: Simulation and Validation,” Proceedings of the International Symposium on Adhesives in Electronics, pp. 27–30, Binghamton, NY, September 1998. 35. Pascarella, N., and D. Baldwin, “Compression Flow Modeling of Underfill Encapsulants for Low Cost Flip Chip Assembly,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 463–470, Seattle, WA, May 1998. 36. Nguyen, L., P. Fine, B. Cobb, Q. Tong, B. Ma, and A. Savoca, “Reworkable Flip Chip Underfill—Materials and Processes,” Proceedings of the International Symposium on Microelectronics, pp. 707–713, San Diego, CA, November 1998. 37. Capote, M. A., and S. Zhu, “No-Underfill Flip-Chip Encapsulation,” Proceedings of Surface Mount International Conference, pp. 291–293, San Jose, CA, August 1998. 38. Capote, M. A., W. Johnson, S. Zhu, L. Zhou, and B. Gao, “Reflow-Curable Polymer Fluxes for Flip Chip Encapsulation,” Proceedings of the International Conference on Multichip Modules and High Density Packaging, pp. 41–46, Denver, CO, April 1998. 39. Vincent, M. B., and C. P. Wong, “Enhancement of Underfill Encapsulants for Flip-Chip Technology,” Proceedings of Surface Mount International Conference, pp. 303–312, San Jose, CA, August 1998. 40. Vincent, M. B., L. Meyers, and C. P. Wong, “Enhancement of Underfill Performance for Flip-Chip Applications by Use of Silane Additives,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 125–131, Seattle, WA, May 1998. 41. Wang, L., and C. P. Wong, “Novel Thermally Reworkable Underfill Encapsulants for FlipChip Applications,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 92–100, Seattle, WA, May 1998. 42. Shi, S. H., and C. P. Wong, “Study of the Fluxing Agent Effects on the Properties of NoFlow Underfill Materials for Flip-Chip Applications,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 117–124, Seattle, WA, May 1998. 43. Wong, C. P., D. Baldwin, M. B. Vincent, B. Fennell, L. J. Wang, and S. H. Shi, “Characterization of a No-Flow Underfill Encapsulant During the Solder Reflow Process,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1253–1259, Seattle, WA, May 1998. 44. Ito, S., M. Mizutani, H. Noro, M. Kuwamura, and A. Prabhu, “A Novel Flip Chip Technology Using Non-Conductive Resin Sheet,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1047–1051, Seattle, WA, May 1998. 45. Gilleo, K., and D. Blumel, “The Great Underfill Race,” Proceedings of the International Symposium on Microelectronics, pp. 701–706, San Diego, CA, November 1998. 46. Lau, J. H., C. Chang, T. Chen, D. Cheng, and E. Lao, “A Low-Cost Solder-Bumped Chip Scale Package—NuCSP,” Circuit World, 24(3):11–25, April 1998. 47. Elshabini-Riad, A., and F. Barlow III, Thin Film Technology Handbook, McGraw-Hill, New York, 1998. 48. Garrou, P. E., and I. Turlik, Multichip Module Technology Handbook, McGraw-Hill, New York, 1998. 49. Lau, J. H., C. Chang, and O. Chien, “SMT Compatible No-Flow Underfill for Solder Bumped Flip Chip on Low-Cost Substrates,” Journal of Electronics Manufacturing, 8(3 and 4):151–164, December 1998.

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50. Lau, J. H., and C. Chang, “Characterization of Underfill Materials for Functional Solder Bumped Flip Chips on Board Applications,” IEEE Transactions on Components and Packaging Technology, Part A, 22(1):111–119, March 1999. 51. Thorpe, R., and D. F. Baldwin, “High Throughput Flip Chip Processing and Reliability Analysis Using No-Flow Underfills,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 419–425, San Diego, CA, June 1999. 52. Qian, Z., M. Lu, W. Ren, and S. Liu, “Fatigue Life Prediction of Flip-Chips in Terms of Nonlinear Behaviors of Solder and Underfill,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 141–148, San Diego, CA, June 1999. 53. Wang, L., and C. P. Wong, “Epoxy-Additive Interaction Studies of Thermally Reworkable Underfills for Flip-Chip Applications,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 34–42, San Diego, CA, June 1999. 54. Lau, J. H., S.-W. Lee, C. Chang, and O. Chien, “Effects of Underfill Material Properties on the Reliability of Solder Bumped Flip Chip on Board with Imperfect Underfill Encapsulants,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 571–582, San Diego, CA, June 1999. 55. Lau, J. H., C. Chang, and O. Chien, “No-Flow Underfill for Solder Bumped Flip Chip on Low-Cost Substrates,” Proceedings of NEPCON West, pp. 158–181, February 1999. 56. Tong, Q., A. Savoca, L. Nguyen, P. Fine, and B. Cobb, “Novel Fast Cure and Reworkable Underfill Materials,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 43–48, San Diego, CA, June 1999. 57. Benjamin, T. A., A. Chang, D. A. Dubois, M. Fan, D. L. Gelles, S. R. Iyer, S. Mohindra, P. N. Tutunjian, P. K. Wang, and W. J. Wright, “CARIVERSE Resin: A Thermally Reversible Network Polymer for Electronic Applications,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 49–55, San Diego, CA, June 1999. 58. Wada, M., “Development of Underfill Material with High Valued Performance,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 56–60, San Diego, CA, June 1999. 59. Houston, P. N., D. F. Baldwin, M. Deladisma, L. N. Crane, and M. Konarski, “Low Cost Flip Chip Processing and Reliability of Fast-Flow, Snap-Cure Underfills,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 61–70, San Diego, CA, June 1999. 60. Kulojarvi, K., S. Pienimaa, and J. K. Kivilahti, “High Volume Capable Direct Chip Attachment Methods,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 441–445, San Diego, CA, June 1999. 61. Shi, S. H., and C. P. Wong, “Recent Advances in the Development of No-Flow Underfill Encapsulants—A Practical Approach Towards the Actual Manufacturing Application,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 770–776, San Diego, CA, June 1999. 62. Rao, Y., S. H. Shi, and C. P. Wong, “A Simple Evaluation Methodology of Young’s Modulus—Temperature Relationship for the Underfill Encapsulants,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 784–789, San Diego, CA, June 1999. 63. Fine, P., and L. Nguyen, “Flip Chip Underfill Flow Characteristics and Prediction,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 790–796, San Diego, CA, June 1999. 64. Johnson, C. H., and D. F. Baldwin, “Wafer Scale Packaging Based on Underfill Applied at the Wafer Level for Low-Cost Flip Chip Processing,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 950–954, San Diego, CA, June 1999. 65. DeBarros, T., P. Neathway, and Q. Chu, “The No-Flow Fluxing Underfill Adhesive for Low Cost, High Reliability Flip Chip Assembly,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 955–960, San Diego, CA, June 1999. 66. Shi, S. H., T. Yamashita, and C. P. Wong, “Development of the Wafer Level CompressiveFlow Underfill Process and Its Required Materials,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 961–966, San Diego, CA, June 1999.

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67. Chau, M. M., B. Ho, T. Herrington, and J. Bowen, “Novel Flip Chip Underfills,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 967–974, San Diego, CA, June 1999. 68. Feustel, F., and A. Eckebracht,“Influence of Flux Selection and Underfill Selection on the Reliability of Flip Chips on FR-4,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 583–588, San Diego, CA, June 1999. 69. Okura, J. H., K. Drabha, S. Shetty, and A. Dasgupta, “Guidelines to Select Underfills for Flip Chip on Board Assemblies,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 589–594, San Diego, CA, June 1999. 70. Anderson, B., “Development Methodology for a High-Performance, Snap-Cure FlipChip Underfill,” Proceedings of NEPCON WEST, pp. 135–143, February 1999. 71. Wyllie, G., and B. Miquel, “Technical Advancements in Underfill Dispensing,” Proceedings of NEPCON WEST, pp. 152–157, February 1999. 72. Crane, L., A. Torres-Filho, E. Yager, M. Heuel, C. Ober, S. Yang, J. Chen, and R. Johnson, “Development of Reworkable Underfills, Materials, Reliability and Proceeding,” Proceedings of NEPCON WEST, pp. 144–151, February 1999. 73. Gilleo, K., “The Ultimate Flip Chip-Integrated Flux/Underfill,” Proceedings of NEPCON WEST, pp. 1477–1488, February 1999. 74. Miller, M., I. Mohammed, X. Dai, N. Jiang, and P. Ho, “Analysis of Flip-Chip Packages Using High Resolution Moire Interometry,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 979–986, San Diego, CA, June 1999. 75. Hanna, C., S. Michaelides, P. Palaniappan, D. Baldwin, and S. Sitaraman, “Numerical and Experimental Study of the Evolution of Stresses in Flip Chip Assemblies During Assembly and Thermal Cycling,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1001–1009, San Diego, CA, June 1999. 76. Emerson, J., and L. Adkins, “Techniques for Determining the Flow Properties of Underfill Materials,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 777–781, San Diego, CA, June 1999. 77. Guo, Y., G. Lehmann, T. Driscoll, and E. Cotts, “A Model of the Underfill Flow Process: Particle Distribution Effects,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 71–76, San Diego, CA, June 1999. 78. Mercado, L.,V. Sarihan,Y. Guo, and A. Mawer,“Impact of Solder Pad Size on Solder Joint Reliability in Flip Chip PBGA Packages,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 255–259, San Diego, CA, June 1999. 79. Qian, Z., M. Lu, W. Ren, and S. Liu, “Fatigue Life Prediction of Flip-Chips in Terms of Nonlinear Behaviors of Solder and Underfill,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 141–148, San Diego, CA, June 1999. 80. Gektin, V., A. Bar-Cohen, and S. Witzman, “Thermo-Structural Behavior of Underfilled Flip-Chips,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 440–447, Orlando, FL, May 1996. 81. Wu, T. Y., Y. Tsukada, W. T. Chen, “Materials and Mechanics Issues in Flip-Chip Organic Packaging,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 524–534, Orlando, FL, May 1996. 82. Doot, R. K., “Motorola’s First DCA Product: The Gold Line Pen Pager,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 535–539, Orlando, FL, May 1996. 83. Greer, S. T., “An Extended Eutectic Solder Bump for FCOB,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 546–551, Orlando, FL, May 1996. 84. Peterson, D. W., J. S. Sweet, S. N. Burchett, and A. Hsia, “Stresses From Flip-Chip Assembly and Underfill: Measurements with the ATC4.1 Assembly Test Chip and Analysis by Finite Element Method,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 134–143, San Jose, CA, May 1997.

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85. Zhou, T., M. Hundt, C. Villa, R. Bond, and T. Lao, “Thermal Study for Flip Chip on FR-4 Boards,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 879–884, San Jose, CA, May 1997. 86. Ni, G., M. H. Gordon, W. F. Schmidt, and R. P. Selvam, “Flow Properties of Liquid Underfill Encapsulations and Underfill Process Considerations,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 101–108, Seattle, WA, May 1998. 87. Hoang, L., A. Murphy, and K. Desai, “Methodology for Screening High Performance Underfill Materials,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 111–116, Seattle, WA, May 1998. 88. Dai, X., M. V. Brillhart, and P. S. Ho, “Polymer Interfacial Adhesion in Microelectronic Assemblies,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 132–137, Seattle, WA, May 1998. 89. Zhao, J. X. Dai, and P. Ho, “Analysis and Modeling Verification for Thermal-Mechanical Deformation in Flip-Chip Packages,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 336–344, Seattle, WA, May 1998. 90. Matsushima, H., S. Baba, and Y. Tomita, “Thermally Enhanced Flip-Chip BGA with Organic Substrate,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 685–691, Seattle, WA, May 1998. 91. Gurumurthy, C., L. G. Norris, C. Hui, and E. Kramer, “Characterization of Underfill/Passivation Interfacial Adhesion for Direct Chip Attach Assemblies Using Fracture Toughness and Hydro-Thermal Fatigue Measurements,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 721–728, Seattle, WA, May 1998. 92. Palaniappan, P., P. Selman, D. Baldwin, J. Wu, and C. P. Wong, “Correlation of Flip Chip Underfill Process Parameters and Material Properties with In-Process Stress Generation,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 838–847, Seattle, WA, May 1998. 93. Qu, J., and C. P. Wong, “Effective Elastic Modulus of Underfill Material for Flip-Chip Applications,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 848–850, Seattle, WA, May 1998. 94. Sylvester, M., D. Banks, R. Kern, and R. Pofahl, “Thermomechanical Reliability Assessment of Large Organic Flip-Chip Ball Grid Array Packages,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 851–860, Seattle, WA, May 1998. 95. Wiegele, S., P. Thompson, R. Lee, and E. Ramsland, “Reliability and Process Characterization of Electroless Nickel-Gold/Solder Flip Chip Interconnect,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 861–866, Seattle, WA, May 1998. 96. Caers, J., R. Oesterholt, R. Bressers, T. Mouthaan, J. Verweij, “Reliability of Flip Chip on Board, First Order Model for the Effect on Contact Integrity of Moisture Penetration in the Underfill,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 867–871, Seattle, WA, May 1998. 97. Roesner, B., X. Baraton, K. Guttmann, and C. Samin, “Thermal Fatigue of Solder FlipChip Assemblies,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 872–877, Seattle, WA, May 1998. 98. Pang, J., T. Tan, and S. Sitaraman, “Thermo-Mechanical Analysis of Solder Joint Fatigue and Creep in a Flip Chip On Board Package Subjected to Temperature Cycling Loading,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 878–883, Seattle, WA, May 1998. 99. Gopalakrishnan, L., M. Ranjan, Y. Sha, K. Srihari, and C. Woychik, “Encapsulant Materials for Flip-Chip Attach,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1291–1297, Seattle, WA, May 1998. 100. Yang, H., S. Bayyuk, A. Krishnan, A. Przekwas, L. Nguyen, and P. Fine, “Computional Simulation of Underfill Encapsulation of Flip-Chip ICs, Part I: Flow Modeling and SurfaceTension Effects,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1311–1317, Seattle, WA, May 1998.

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101. Liu, S., J. Wang, D. Zou, X. He, Z. Qian, and Y. Guo, “Resolving Displacement Field of Solder Ball in Flip-Chip Package by Both Phase Shifting Moire Interferometry and FEM Modeling,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1345–1353, Seattle, WA, May 1998. 102. Hong, B., and T. Yuan, “Integrated Flow—Thermomechanical and Reliability Analysis of a Low Air Cooled Flip Chip-PBGA Package,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1354–1360, Seattle, WA, May 1998. 103. Wang, J., Z. Qian, D. Zou, and S. Liu, “Creep Behavior of a Flip-Chip Pacakge by Both FEM Modeling and Real Time Moire Interferometry,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1439–1445, Seattle, WA, May 1998. 104. Lau, J., C. Chang, C. Chen, R. Lee, T. Chen, D. Cheng, T. Tseng, and D. Lin, “Via-In-Pad (VIP) Substrates for Solder Bumped Flip Chip Applications,” Proceedings of Surface Mount International Conference, pp. 128–136, September 1999. 105. Lau, J. H., “Critical Issues of WLCSP with Emphasis on Cost Analysis and Solder Joint Reliability,” IEEE Transactions on Electronics Packaging Manufacturing, 25(1):42–50, January 2002. 106. Lau, J. H., T. Chung, R. Lee, C. Chang, and C. Chen, “A Novel and Reliable Wafer-Level Chip Scale Package (WLCSP),” Proceedings of the Chip Scale International Conference, pp. H1–8, September 1999. 107. Lau, J. H., R. Lee, C. Chang, and C. Chen, “Solder Joint Reliability of Wafer Level Chip Scale Packages (WLCSP): A Time-Temperature-Dependent Creep Analysis,” ASME Paper No. 99-IMECE/EEP-5, International Mechanical Engineering Congress and Exposition, November 1999. 108. Lau, J. H., and R. Lee, “Effects of Printed Circuit Board Thickness on Solder Joint Reliability of Flip Chip Assemblies with Imperfect Underfill,” ASME Paper No. 99-IMECE/EEP-4, International Mechanical Engineering Congress and Exposition, November 1999. 109. Lau, J. H., C. Chang, and R. Lee, “Failure Analysis of Solder Bumped Flip Chip on LowCost Substrate,” Proceedings of the International Electronic Manufacturing Technology Symposium, pp. 457–472, October 1999. 110. Lau, J. H., C. Chang, and C. Chen, “Characteristics and Reliability of No-Flow Underfills for Solder Bumped Flip Chips on Low Cost Substrates,” Proceedings of the International Symposium on Microelectronics, pp. 592–598, October 1999. 111. Lau, J. H., and R. Lee, “Modeling and Analysis of 96.5Sn-3.5Ag Lead-Free Solder Joint of WLCSP on Buildup Microvia Printed Circuit Board,” IEEE Transactions on Electronics Packaging Manufacturing, 25(1):51–58, January 2002. 112. Hashino, E., K. Shimokawa, Y. Yamamoto, and K. Tatsumi, “Micro-Ball Wafer Bumping for Flip Chip Interconnection,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 957–964, May 2001. 113. Jeon, Y., K. Paik, K. Bok, W. Choi, and C. Cho, “Studies on Ni-Sn Intermetallic Compound and P-Rich Nie Layer at the Electroless Ni UBM—Solder Interface and Their Effects on Flip Chip Solder Joint Reliability,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 69–75, May 2001. 114. Kazama, A., T. Satoh, Y. Yamaguchi, I. Anjoh, A. Nishimura, “Development of Low-Cost and Highly Reliable Wafer Process Package,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 40–46, May 2001. 115. Zhang, C., J. Lin, and Li Li, “Thermal Fatigue Properties of Lead-free Solders on Cu and NiP Under Bump Metallurgies,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 463–470, May 2001. 116. Lin, J., A. De Silva, D. Frear, and Y. Guo, “Characterization of Lead-Free Solders and Under Bump Metallurgies for Flip-Chip Package,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 455–462, May 2001. 117. Balkan, H., D. Patterson, G. Burgess, C. Carlson, P. Elenius, M. Johnson, B. Rooney, J. Sanchez, D. Stepniak, and J. Wood, “Flip-Chip Reliability: Comparative Characterization of Lead Free (Sn/Ag/Cu) and 63Sn/Pb Eutectic Solder,” IMAPs Flip Chip Workshop, October 2001.

CHAPTER 4

CHIP (WAFER)-LEVEL INTERCONNECTS WITH SOLDERLESS BUMPS 4.1

INTRODUCTION

The lead-free solder bumps discussed in Chaps. 2 and 3 are just one of many different kinds of chip (wafer)-level interconnects.1–19 In this chapter, solderless chip (wafer)-level interconnects such as electroless Ni-P-immersion Au bumps, electroplated gold bumps, electroplated copper bumps, electroplated copper wires, wirebonding gold wires (microsprings), wire-bonding gold stud bumps, and wire-bonding copper stud bumps will be discussed.

4.2 WAFERS FOR ELECTROLESS Ni-Au, ELECTROPLATED Au, AND ELECTROPLATED Cu BUMPS In this section the wafer size for Ni-Au bumps, electroplated Au bumps, and electroplated Cu bumps is 6 in. The chip is 0.5 in (12.7 mm) square and 25 mil (0.64 mm) thick. The street width between all the chips is 6 mil (0.15 mm). The chip has 8-mil (0.2-mm) square pads and 14-mil (0.36-mm) pitch. All of the pads are arranged symmetrically around the perimeter of the chip and are interconnected via traces on the chip in an alternating pattern so as to provide daisy-chained connections when the chip is attached to the FR-4 printed circuit board (PCB). The silicon wafer consists of a patterned aluminum layer on a layer of silicon dioxide that is covered with a patterned silicon nitride passivation layer. The wafer fabrication process flow starts with a 0.25-µm layer of silicon dioxide deposited by plasma enhanced chemical vapor deposition on a <111> silicon substrate. For the metal layer, a 0.85-µm layer of Al-1%Si-0.1%Ti alloy is sputtered over the silicon dioxide. The metal pattern is then defined by coating with positive resist, exposed by projection alignment, developed, and wet–chemical etched. After the photoresist is removed by plasma stripping, the metal pattern is sintered at 450°C to remove film stresses. For the passivation layer, a 0.75-µm layer of silicon nitride is deposited over the entire surface of the wafer by plasma enhanced chemical vapor deposition. The pad opening in the passivation layer is then defined by coating with positive resist, exposed by projection alignment, developed, and plasma-etched. Finally, the resist is removed by plasma stripping, leaving the silicon nitride passivation layer to overlap the perimeter of the Al pads by 10 µm.

4.3

ELECTROLESS Ni-P-IMMERSION Au BUMPS

One of the critical differences between electroless Ni-P-immersion Au (for short, Ni-Au) under-bump metallurgies (UBMs;Chap.2) and Ni-Au bumps is the Ni thickness. 4.1 Copyright © 2003 by The McGraw-Hill Companies, Inc. Click here for terms of use.

4.2

CHAPTER FOUR

Usually, the thickness of Ni-Au UBMs is 5 µm (but can be as high as 12 µm or as low as 3 µm) and that of Ni-Au bumps is 20 µm (but can be as high as 25 µm or as low as 15 µm). The advantages of the electroless Ni-Au UBMs are: (1) its costs are low; (2) it is compatible with eutectic solders; (3) it has high solder wetability; (4) Al-Ni adhesion is more than adequate for surface-mount technology applications; and (5) Ni-Sn intermetallic growth is adequate for most of the solder joint thermal fatigue lives. However, the quality and uniformity of electroless Ni-Au bumps depend on the careful monitoring of each process step and the tight contamination control (every 2 h) of the zincate, Ni, and Au solution tanks. The Al-Ni adhesion and electrical resistance at the interface are strongly affected by the cleaning and activation processes.5 The advantages of electroless Ni-Au bumps are: (1) their costs are low and (2) they are suitable for conductive adhesive material.

4.3.1

MATERIALS AND PROCESS

The materials and process flow of Ni-Au UBMs13 discussed in Chap. 2 can be used to fabricate the Ni-Au bumps except with much longer process time. However, in this section, the process developed by PICOPAK in 1995 is presented as shown in the following list (for a bump with 24-µm height and 80-gf shear force). 1. Visual inspection of wafer 2. Test runs with diced wafer samples to find optimal process conditions 3. Application of photoresist to cover possible ink dots, undesired openings in dicing lanes, etc., using a standard photolithography process 4. Application of photoresist on back side of wafer 5. Plasma cleaning of exposed surfaces (<5 min at very low wafer temperature) 6. First zincate (2 min at room temperature), rinse in deionized water 7. Zinc strip (1 min at room temperature), rinse in deionized water 8. Second zincate (2 min at room temperature), rinse in deionized water 9. Nickel plating (1 h at <100°C), rinse in deionized water 10. Visual inspection of wafer 11. Bump height measurements 12. Immersion in gold (15 min at <100°C), rinse in deionized water 13. Removal of photoresist in hot (100°C) acidic solution 14. Visual inspection of wafer 15. Bump shear test 16. Bump wetting test (not necessary for anisotropic conductive film application) 17. Documentation and shipping of goods Figure 4.1 shows a cross section of the electroless Ni-Au bump on the 6-in Si wafer. It should be noted that for such a large Ni-Au bump (24-µm height), the Ni creates a large amount of stress that could crack the passivation.

4.3.2

PASSIVATION CRACKING

Figures 4.2 through 4.5 show some examples of passivation cracking of Ni-Au bumps. It can be seen that the cracks occur at the corner of the passivation due to

FIGURE 4.1 A 24-µm electroless Ni-P-immersion Au bump.

FIGURE 4.2 Passivation crack in electroless Ni-P-immersion Au bump.

4.3

FIGURE 4.3 Passivation crack in electroless Ni-P-immersion Au bump.

FIGURE 4.4 Passivation crack in electroless Ni-P-immersion Au bump.

4.4

FIGURE 4.5 Passivation crack in electroless Ni-P-immersion Au bump.

FIGURE 4.6 A perfect Ni-Au bump.

4.5

4.6

CHAPTER FOUR

stress concentration of the passivation geometry stemming from the long duration of Ni plating. Thus, great care in monitoring of all process steps and tight contamination control of the Ni, Zn, and Au solution tanks must be taken in order to obtain the Ni-Au bump shown in Figs. 4.1 and 4.6.

4.4

ELECTROPLATED Au BUMPS

Since their invention by Triggs and Byrns12 in 1971, gold bumps have been used extensively for many applications, especially with tape automated bonding technology.14 Gold bumps usually contain two regions: the thin film adhesion layers to aluminum metallization (UBM) and the main body of the Au bump. As shown in Chap. 2, Table 2.1, there are many UBMs for Au bumps. It can be seen that the thin film structure consists of three layers: (1) an adhesion layer of Ti or Cr a few hundred angstroms thick; (2) a diffusion barrier of Cu, Pd, W, or Pt about 10,000 angstroms thick; and (3) the top capping layer, commonly Au, a few thousand angstroms thick. This capping layer provides an easy surface for plating the Au bump. Typical bump heights range from 15 to 25 µm.

4.4.1

MATERIALS AND PROCESS

The 6-in wafer discussed in Sec.4.2 is Au-bumped by the electroplating process as shown in Fig. 4.7. The UBM of the wafers is titanium (Ti) and tungsten (W) sputtered on the entire surface of the wafer: 0.1 to 0.2 µm of Ti first, followed by 0.3 to 0.5 µm of W. A 20-µm layer of resist is then overlaid on the Ti-W and a bump mask is used to define the bump pattern. The openings in the resist are 7 to 10 µm wider than the pad openings in the passivation layer. A 20-µm-thick layer of Au is then plated over the Ti-W. The resist is then removed and the Ti-W is stripped off with a hydrogen peroxide etch. The final process is annealing of the bumps at an elevated temperature (such as 300°C) to obtain the desired hardness. The microhardness of a well-annealed gold bump is in the range of 50 to 60 on the Vickers scale, while that of an as-deposited bump is about 120. Figure 4.8 shows a cross section of the electroplated Au bump on the 6-in Si wafer.

4.4.2

BUMP SPECIFICATIONS AND MEASUREMENT METHODS

For an Au bump with a height of 25 µm, the specification is ±3 µm. The bump height uniformity should be ±1 µm within a chip and ±2 µm within a wafer.The sample sizes should be five bumps per chip, five chips per wafer, and five wafers per lot. The shear force should be 5.5 gf/mil2. Sample sizes for shearing test (6 µm from the chip pads) should be five bumps per chip, five chips per wafer, and three wafers per lot. The hardness should be larger than 90 Knoop prior to annealing and 35 to 75 Knoop after annealing. Sample sizes for hardness test should be five bumps per chip, five chips per wafer, and two wafers per lot.

4.7 FIGURE 4.7 Electroplated Au wafer-bumping process flow.

4.8

CHAPTER FOUR

FIGURE 4.8 A 20-µm Au bump.

4.5

ELECTROPLATED Cu BUMPS

Because gold is very expensive and copper is much cheaper, copper has been considered as an alternative to gold. In this section, the materials, process, and some special considerations about copper bumps are discussed.

4.5.1

MATERIALS AND PROCESS

The wafer-bumping process with Cu is almost the same as that with Au except for the UBM, which is Ti (0.1 to 0.2 µm) and Cu (0.5 to 0.8 µm). On top of the UBM, the plated Cu thickness is 20 µm. The average microhardness of the as-deposited Cu bumps is about 100 on the Vickers scale. Since the copper surface oxidizes and corrodes very easily, the Cu bumps are immersed with a very thin layer of Sn. Figure 4.9 shows a cross section of the electroplated Cu bump on the 6-in Si wafer.

4.5.2

SPECIAL CONSIDERATIONS

In general, Cu bumps are cheaper than Au bumps. However, difficulty in bonding and additional process steps for the protective layer have prevented copper bumps from gaining widespread use in tape automated bonding or chip on board technologies. A high-purity copper bath (preferably copper sulfate solution) is required to

CHIP (WAFER)-LEVEL INTERCONNECTS WITH SOLDERLESS BUMPS

4.9

FIGURE 4.9 A 20-µm Cu bump.

produce soft copper bumps. Furthermore, with the aluminum conductor pads on the silicon chip, the adhesion to the aluminum bond pads is a critical factor in determining the fabrication yield and reliability of copper bumps.11 On the other hand, with the increasing usage of copper conductor pads on the silicon chips nowadays, copper bumps may gain popularity in the near future.

4.6

ELECTROPLATED COPPER WIRES

Wire interconnect technology (WIT), which was invented by FCPT in 1994,15 provides new opportunities for the integrated circuit designer unavailable from any other chip-level interconnect method. In this section, WIT will be briefly discussed.

4.6.1

STRUCTURE

Structurally, WIT consists of a (copper) metal post (wire) approximately 10 µm in diameter and 50 µm long, as shown in Fig. 4.10. The free end of the copper wire can be attached to a 25-µm-diameter copper pad with lead-free solder or conductive adhesive on the substrate. The pad pitch can be as small as 50 µm. The copper wire can be grown on either the silicon chip surface or the substrate. Due to the extremely high compliance of the copper wire interconnect, the solder (or adhesive) joint is very reliable under thermal cycling conditions.

4.10

CHAPTER FOUR

FIGURE 4.10 FCPT’s electroplated copper wires.

4.6.2

FABRICATION MATERIALS AND PROCESS

WIT is electroplated with copper on either the silicon chip or the substrate. Highaspect-ratio vias in a thick photoresist layer are patterned followed by a fine-grain plating process. The resulting copper wire has nearly the same properties as annealed pure copper. To allow multiple replacement of WIT-attached chips, a thin layer of nickel is coated over the copper wires. The nickel acts as a diffusion barrier between the lead-free solder and copper materials, permitting multiple solder attachment and replacement cycles without degradation of the solder joints. Figure 4.10 shows a scanning electron microscope photo of the copper wires grown on pads with 30-µm pitch. It can be seen that these particular copper wires are approximately 47 µm tall, 10 µm in diameter on the base, and 20 µm in diameter on the free end. To ensure proper assembly and high manufacturing yield, WIT must be fabricated to within very tight height tolerances (for example, a 45-µm-tall WIT should be within ±2.5 percent over an area of 20 mm2 and the height uniformity across a 6-in wafer should be ±5 percent.)

4.7

WIRE-BONDING MICROSPRINGS

The microspring developed by FormFactor is another chip (wafer)-level interconnect. Because of its special S shape, microspring could be even more compliant than WIT. In this section, the material and process of FormFactor’s microspring are briefly discussed.16

CHIP (WAFER)-LEVEL INTERCONNECTS WITH SOLDERLESS BUMPS

4.7.1

4.11

MATERIALS AND PROCESS

The microspring contact is made of gold wire plated with nickel alloy and formed into an S shape on a silicon wafer by a wire bonder as shown in Figs. 4.11 and 4.12. FormFactor called the technology microspring contact on silicon technology (MOST). It employs a simple approach using conventional wire-bonding tools to provide the foundation for the microspring contacts. Since there is no leadframe, no die attach, no molding, no UBM, and no bump, microspring technology has a significantly lower cost than the conventional chip (wafer)level interconnect. Themicrosprings can be attached to the PCB or substrate with either lead-free solders or conductive adhesives.

4.7.2

SPECIAL CONSIDERATIONS

It should be emphasized that, due to the compliance of the microspring contacts, unlike the solder-bumped flip chip waferlevel chip-scale package (WLCSP) on PCBs or organic substrates, underfill is not needed with microsprings. Also, with FormFactor’s wafer on wafer (WOW) process, WLCSP with microspring contacts as shown in Fig. 4.12 can be tested at high speed and burned in at elevated temperatures. One concern about this technology could be that there is too much gold for the solder interconnect to lower its ductility. FIGURE 4.11 FormFactor’s S-shaped microspring.

FIGURE 4.12 FormFactor’s WLCSP with microsprings.

4.12

4.8

CHAPTER FOUR

WIRE-BONDING Au STUD BUMPS

Gold stud bump bonding (SBB) technology was developed by Fujitsu, Matsushita, and others in Japan in the early 1990s17–19 and is now used in several variants in Japan and the European Union. It uses an adhesive to (electrically, mechanically, or both) glue the gold stud-bumped chip to the PCB or substrate. Recently, this technology has been attracting a good deal of attention. This is due to: (1) many critical issues such as cost and uncertainty caused by lead-free soldering; (2) the availability of specially made high-throughput (∼15 bumps per second) automatic production wire bonders, e.g., Panasert and Kulicke & Soffa; and (3) the fact that SBB technology is already in production. The chip (wafer)level interconnect of the SBB technology is the Au stud bump, which is discussed in this section.

4.8.1

MATERIALS AND PROCESS

The Au stud bumps are formed on the Al bond pads on the chip or wafer by a modified wire bonder. The wire is made of Au-1wt%Pd. The processes are illustrated in Fig. 4.13. It can be seen that: (1) as in conventional wire bonding, a gold wire is bonded to the chip bond pads by either thermocompression or ultrasonic energy or both, and (2) the capillary tube is withdrawn to form a loop path and breaks the wire on the top of the Au ball bond. After the Au stud bumping, a mechanical leveling (coining) for the coplanarity (within ±5 µm) of stud bumps is performed as shown in Fig. 4.14. The leveling is usually executed by pressing the chip or wafer against an unyielding flat surface at about 50 gf per bump. Figure 4.15 shows a few different stud bumps created by Kulicke & Soffa’s specially made wire bonder.

FIGURE 4.13 Process flow for Au stud bumps.

CHIP (WAFER)-LEVEL INTERCONNECTS WITH SOLDERLESS BUMPS

FIGURE 4.14 Process flow for Au stud bumps on a wafer level.

FIGURE 4.15 Au stud bump samples by Kulicke & Soffa.

4.13

4.14

4.8.2

CHAPTER FOUR

EQUIPMENT

As mentioned earlier, one of the reasons the SBB technology has attracted so much attention recently is because of the availability of fully automatic equipment. Today, at least two companies—Panasert and Kulicke & Soffa—are providing this equipment. Figure 4.16 shows Panasert’s STBS and Fig. 4.17 shows its operation sequence. It can be seen that this machine operates on chips in a waffle tray, and that the leveling and monitoring are optional. If the leveling option is included, then it will occur somewhere near the microscope and the heating stage (Fig. 4.16). Usually, Panasert uses its flip chip bonder (FCBII) to perform leveling, as shown in Chap. 5. Figures 4.18 and 4.19 show Panasert’s STBW(1) and STBW(2), respectively. The operation sequence of these machines is shown in Fig. 4.20. It can be seen that (1) these machines operate on chips on a wafer; (2) STBW(1) is for wafers in a sin-

FIGURE 4.16 Au stud bump bonder (STBS) by Panasert.

4.15 FIGURE 4.17 Operation sequence of STBS.

4.16

CHAPTER FOUR

FIGURE 4.18 Au stud bump bonder STBW(1) by Panasert.

gle magazine; (3) STBW(2) is for wafers in two magazines; and (4) leveling is not an option. Figure 4.21 shows Panasert’s STBW2, and its operation sequence is shown in Fig. 4.22. It can be seen that the biggest difference between STBW2 and STBW(2) is there are three working stages for STBW2: one preheating unit, one bonding unit, and one postheating unit. Figure 4.23 shows a Au stud bump after leveling made by Panasert’s machines.

CHIP (WAFER)-LEVEL INTERCONNECTS WITH SOLDERLESS BUMPS

4.17

FIGURE 4.19 Au stud bump bonder STBW(2) by Panasert.

Figure 4.24 shows Kulicke & Soffa’s dual bonder workcell (stud bump bonders on two sides of the wafer-handling unit). This unit can produce twice the throughput in only 1.6 times the space and saves 16 percent of the cost of their WaferPro stud bump bonder with only one bonder.

4.9

WIRE-BONDING Cu STUD BUMPS

In general, application of Au stud bumps is performed with adhesives and not with solders. This is due to the amount of Au in the stud bump, which will reduce the solder joint’s ductility. However, unlike solders (which self-align during reflow), adhesives require very high placement accuracy. Thus, in order to keep one of the unique

FIGURE 4.20 Operation sequence of STBW.

FIGURE 4.21 Au stud bump bonder STBW2 by Panasert.

4.18

4.19 FIGURE 4.22 Operation sequence of STBW2.

FIGURE 4.23 Leveled Au stud bump by Panasert.

FIGURE 4.24 Kulicke & Soffa dual bonder workcell (two bonders and one wafer-handling unit).

4.20

CHIP (WAFER)-LEVEL INTERCONNECTS WITH SOLDERLESS BUMPS

4.21

FIGURE 4.25 Cu stud bumping.

advantages of solders, Cu stud bumps are introduced. Also, with the increasing interest in copper conductor pads, Cu stud bumps could be very popular in the future. In this section, Furukawa’s Cu stud bumps are briefly discussed.19

4.9.1

MATERIALS AND PROCESS

Furukawa’s Cu wire is 25 µm in diameter and is made of 99.99 percent pure copper. In order to prevent the Cu bump from oxidizing, the Cu wire is liquefied in a reduction atmosphere consisting of 5 percent H2 in N2 forming a ball 65 µm in diameter. The reduction gas is blown over the end of the copper wire at 1 l/min. Figures 4.25 and 4.26 show, respectively, the Cu stud-bumping process flow and the Cu ball. It can be seen that the Cu wire is bumped using ultrasonic power. Unlike Au wires, Cu wires are not very malleable and could contribute to chip pad cracking with rapid ultrasonic power. Thus, ultrasonic ramp control is very important for Cu stud bumping to be successful. Figure 4.27 and Table 4.1 show the Cu studbumping test results with various ultrasonic ramp rates at 250°C and under controlled forces. (The initial ultrasonic voltage is measured by an oscilloscope.) It can be seen that (1) the higher the ramp rates, the more the chip pad cracks; and (2) at 129 V/s, there are no chip pad cracks. Thus, the Cu stud bumps can be made without cracking the chip pads if a proper ultrasonic ramp rate is used. Just as with Au stud bumps, after the Cu stud bumping on chips, the Cu studs are leveled to produce uniform bump heights. Figure 4.28 shows a Au stud bump (a) and a Cu stud bump (b) after leveling. FIGURE 4.26 Cu stud copper ball.

4.22

CHAPTER FOUR

FIGURE 4.27 Initial voltage of ultrasonic power control.

FIGURE 4.28 Scanning electron microscope images of (a) Au stud and (b) Cu stud bumps after leveling.

CHIP (WAFER)-LEVEL INTERCONNECTS WITH SOLDERLESS BUMPS

4.23

TABLE 4.1 Under-Pad Crack Occurrence at Various Ramp Rates Ramp rate

4.9.2

Shear strength

Number of cracks

No ramp

64.0 gf

8

194 V/s

83.4 gf

5

159 V/s

75.9 gf

2

129 V/s

68.3 gf

0

SHEAR STRENGTH

The shear strength (force) of Cu stud bumps, along with that of Au stud bumps, is shown in Fig. 4.29. It can be seen that the average shear strength (69 gf) of the Cu stud bumps is larger than that (58 gf) of the Au stud bumps. However, the fracture surface is quite different for these two stud bumps. For the Au stud bumps, the fracture surface is at the bulk Au bump. However, for the Cu stud bumps, the fracture surface is at the interface between the stud bump and the chip pad.This could be due to the difference in hardness between these two materials; Au is softer than Cu.

FIGURE 4.29 Typical shear test force of Au and Cu stud bumps.

ACKNOWLEDGMENTS The authors would like to thank the friendly people of PICOPAK, Panasonic, and Kulicke & Soffa; L. Moresco, D. Love, W. Chou, D. Horine, C. Wong, S. Beilin, and V. Holalkere of Fujitsu Computer Packaging Technologies; J. Healy of FormFactor; S. Zama, T. Hikami, and H. Murata of Furukawa; and D. Baldwin of the Georgia Institute of Technology for providing very useful information to the industry.

4.24

CHAPTER FOUR

REFERENCES 1. Tummala, R. R., Fundamentals of Microsystems Packaging, McGraw-Hill, New York, 2001. 2. Tummala, R. R., E. Rymaszewski, and A. Klopfenstein, Microelectronics Packaging Handbook, Chapman & Hall, New York, 1997. 3. Tummala, R. R., and E. Rymaszewski, Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York, 1989. 4. Lau, J. H., and S.W.R. Lee, Microvias for Low Cost High Density Interconnects, McGrawHill, New York, 2001. 5. Lau, J. H., Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, McGraw-Hill, New York, 2000. 6. Lau, J. H., and S.W.R. Lee, Chip Scale Package, Design, Materials, Process, Reliability, and Applications, McGraw-Hill, New York, 1999. 7. Lau, J. H., C. Wong, J. L. Prince, and W. Nakayama, Electronic Packaging, Design, Materials, Process, and Reliability, McGraw-Hill, New York, 1998. 8. Lau, J. H., and Y.-H. Pao, Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGraw-Hill, New York, 1997. 9. Lau, J. H., Flip Chip Technologies, McGraw-Hill, New York, 1996. 10. Lau, J. H., Ball Grid Array Technology, McGraw-Hill, New York, 1995. 11. Lau, J. H., Chip On Board Technologies for Multichip Modules, Van Nostrand Reinhold, New York, NY, 1994. 12. Triggs, W., and C. Byrns Jr., U.S. Patent No. 3,599,060, 10 August, 1971. 13. Jeon, Y., K. Paik, K. Bok, W. Choi, and C. Cho, “Studies on Ni-Sn Intermetallic Compound and P-rich Ni Layer at the Electroless Nickel UBM-Solder Interface and Their Effects on Flip Chip Solder Joint Reliability,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 69–75, May 2001. 14. Lau, J. H., Handbook of Tape Automated Bonding, Van Nostrand Reinhold, New York, 1992. 15. Moresco, L., D. Love, W. Chou, and V. Holalkere, “Wire Interconnect Technology: An Ultra-High-Density Flip Chip–Substrate Connection Method,” in Flip Chip Technology, Lau, J. H., ed., McGraw-Hill, New York, pp. 367–386, 1996. 16. Healy, J., “The Impact of Microsprings on Wafer Level Packaging of ICs,” Proceedings of the HDI EXPO, pp. 17–36, August 1999. 17. Tsunoi, K., T. Kusagaya, and H. Kira, “Flip Chip Mounting Using Stud Bumps and Adhesive for Encapsulation,” in Flip Chip Technology, Lau, J. H., ed., McGraw-Hill, New York, pp. 357–366, 1996. 18. Zakel, E., and H. Reichl, “Flip Chip Assembly Using Gold, Gold-Tin, and Nickel-Gold Metallurgy,” in Flip Chip Technology, Lau, J. H., ed., McGraw-Hill, New York, pp. 415–490, 1996. 19. Zama, S., D. Baldwin, T. Hikami, and H. Murata, “Flip Chip Interconnect Systems Using Wire Stud Bumps and Lead Free Solder,” IEEE Proceedings of Electronic Components and Technology Conference, May 2000.

CHAPTER 5

WLCSPs WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE 5.1

INTRODUCTION

Based on a full life-cycle analysis,1, 2 it is unclear whether lead-free solders are actually more environmentally friendly. If materials and component availability, reliability uncertainty, increased processing difficulties, and end-of-life (EOL) issues are accounted for, lead-free solders may not be a better choice. Ultimately, the best solutions may be completely new attachment technologies that do not use solder (i.e., solderless, as discussed in Chap. 4). For example,1–46 flip chips with Cu stud bumps, Au stud bumps,Au bumps, Cu bumps, Ni-Au bumps, Cu wires, or Au wires on printed circuit board (PCB)/substrate with isotropic conductive adhesive (ICA), anisotropic conductive paste (ACP), anisotropic conductive film (ACF), or nonconductive adhesive (NCA). In this chapter, various of these technologies are discussed briefly. The novel development of these materials will be discussed in Chaps. 17 through 20.

5.2 DESIGN, MATERIALS, PROCESS, AND RELIABILITY OF WLCSPs WITH Au BUMPS, Cu BUMPS, AND Ni-Au BUMPS ON PCB WITH ACF In this section, direct chip attach (DCA) with solderless flip chip on board (FCOB) with ACF will be considered.4 The chip is bumped with three different metallugies (Ni-Au, Au, and Cu), as discussed in Chap. 4, Secs. 4.3 through 4.5, respectively. The Cu pads on the FR-4 epoxy PCB are with electroless Ni-immersion Au and are organic-coated. Hitachi’s ACF is used for this study. The design, materials, and assembly process flow are shown in Fig. 5.1. In the following sections, some of the major steps will be discussed. Also, some thermal cycling and surface insulation resistance (SIR) test results are presented.

5.2.1

PCB

A matching PCB is designed along with the chip discussed in Chap. 4, Sec. 4.2. The Cu pads are round (8-mil, or 0.2-mm, diameter) and in a 14-mil (0.36-mm) pitch. In this study, two Cu-pad finishings, electroless Ni-Au and organic-coated, are considered (Fig. 5.2). Most of the pads are interconnected via traces on the PCB in an alternating pattern so as to provide daisy-chained connections with the chip.

5.2.2

ACF

The ACF used for this study is Hitachi Chemical’s double-layer ACF (Fig. 5.3). It consists of nonfilled thermal setting adhesive and Ni- (2 to approximately 5 µm) 5.1 Copyright © 2003 by The McGraw-Hill Companies, Inc. Click here for terms of use.

5.2

CHAPTER FIVE

FIGURE 5.1 Flip chip on board/substrate with ACP/ACF process flow.

conducting particle-filled thermal setting adhesive layers. Each layer is about 30 µm thick. Hitachi Chemical has shown that there are more conductive particles between the chip bumps and the substrate pads if the conducting particle-filled thermal setting adhesive layer in the ACF faces toward the pad of the substrate (Fig. 5.4). For this study, the ACF is sandwiched by two layers of release paper.

FIGURE 5.2 Au-bumped, Cu-bumped, and Ni-Au-bumped flip chip on a PCB with either Cu-Ni-Au or OCC finishes.

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.3

FIGURE 5.3 Hitachi’s double-layer ACP.

It should be pointed out that, unlike the underfills for the conventional solderbumped flip chip on PCBs or substrates applications,28, 34 the thermal setting adhesive of the ACF doesn’t consist of any filler [which leads to very high thermal coefficient of expansion (TCE)] and has many voids in the bonded assembly. Since the compliance between the chip bumps and the pads on the PCB or substrate is very small, thermal fatigue reliability could be an issue, especially for telecommunication products, which require 20 years of life. Thus, to lower the TCE, reduce the voids, and increase the adhesion strength of the thermal setting adhesive of the ACF/ACP, some amount of nonconductive fillers should be incorporated into the ACF/ACP.

FIGURE 5.4 Effect of Hitachi’s ACF arrangements on the number of conductive particles per bump.

5.4

5.2.3

CHAPTER FIVE

FCOB ASSEMBLIES WITH ACF

More than 100 chips have been bonded on the Cu-Ni-Au and organic-coated copper (OCC) FR-4 PCB. These chips have three different kinds of bumps: 1. 20-µm Cu bumps 2. 20-µm Au bumps 3. 24-µm Ni-Au bumps The assembly process of the ACF is very simple and clean (fluxless). First of all, cut the ACF to a little larger than the size of the chip and remove one of the release papers. Place the ACF on the FR-4 PCB with the other release paper facing upward. This is called tacking. The next step is to prepress the ACF under a condition of 80°C and 5 s. This is called lamination. In the next step, a lookup camera is used to read in some of the bumps of the chip. Remove the release paper.Then a lookdown camera is FIGURE 5.5 Top view of a flip chip with an used to read in the corresponding pad ACF on a PCB. locations of the PCB. After the necessary adjustment, the chip is placed on top of the ACF on the PCB. This is called pick and place and is done on Hitachi’s aligning machine. Finally, the chip on board assembly is transported to the Hitachi bonder to do the bonding at a condition of 180°C, 5 kg/mm2, and 20 s. Figure 5.5 shows a typical flip chip on PCB with ACF assembly. A typical cross section of the assembly is shown in Fig. 5.6. There are many voids.

FIGURE 5.6 Typical cross section of a flip chip with ACF on PCB (many voids).

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.5

Figures 5.7 through 5.10 show the scanning electron microscope (SEM) cross section of the ACF-bonded flip chip with Au bumps on a PCB with Cu-Ni-Au pads. It can be seen that there are a few Ni conducting particles. Since the electroplated Au bump on the chip is softer than the electroless Au-Ni on the PCB, these Ni conducting particles penetrated more into the Au bump on the chip. One of the disadvantages of anisotropic conductive materials is to waste conductive particles, such as the one shown in Fig. 5.10. Figure 5.11 shows the SEM cross section of the ACF-bonded flip chip with Cu bumps on a PCB with Cu-Ni-Au pads. It can be seen that most of the Ni conducting particles penetrated into the electroplated Cu (with a flesh of Sn) bump on the chip. Again, this is because the microhardness of the Au-Ni pads on the PCB is harder than that of the Sn-Cu bumps on the chip. Figure 5.12 shows the SEM cross section of the ACF-bonded flip chip with Ni-Au bumps on a PCB with Cu-Ni-Au pads. It can be seen that the penetration of the Ni conducting particles into both the Ni (with a flesh of Au) bump on the chip and the Au-Ni pads on the PCB is small. As a matter of fact, some of the Ni conducting particles have been badly deformed. Figure 5.13 shows the SEM cross section of the ACF-bonded flip chip with Cu bumps on a PCB with OCC pads. It can be seen that the Ni conducting particles penetrated into both the Cu (with a flesh of Sn) bump on the chip and the OCC pad on the PCB. In general, the ACF assembly yield is strongly affected by the kinds of bumps on the chip and the flatness of the PCBs. In our cases, chips with Cu bumps have the highest yield and chips with Ni-Au bumps have the lowest yield. This could be due to the microhardness of the bumps, since the Cu bump is the smallest and the Ni-Au bump is the largest.Also, a PCB with OCC pads leads to a better assembly yield than that with Cu-Ni-Au pads. This could be due to the less-curve surface (more flatness) of the OCC finishing.

FIGURE 5.7 particles.

Au-bumped flip chip on Cu-Ni-Au PCB with Ni conductive

5.6

CHAPTER FIVE

FIGURE 5.8 Magnified image of Au-bumped flip chip on Cu-Ni-Au PCB with Ni conductive particles.

FIGURE 5.9 A closer look at the Au-bumped flip chip on Cu-Ni-Au PCB with Ni conductive particles.

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

FIGURE 5.10 A nickel particle is wasted.

FIGURE 5.11 Cu-bumped flip chip on Cu-Ni-Au PCB with Ni conductive particles.

5.7

5.8

CHAPTER FIVE

FIGURE 5.12 Ni-Au-bumped flip chip on Cu-Ni-Au PCB with Ni conductive particles.

FIGURE 5.13 Cu-bumped flip chip on OCC PCB with Ni conductive particles.

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.9

FIGURE 5.14 Thermal cycling profile (−20 to 110°C, 15-min ramp and 15-min dwell).

5.2.4

THERMAL CYCLING TEST OF FCOB ASSEMBLIES WITH ACF

Forty ACF-bonded flip chips (20 with Au bumps and 20 with Cu bumps) on a Cu-Ni-Au PCB are subjected to thermal cycling. The temperature profile is shown in Fig. 5.14. It is from −20 to 110°C, and the cycle time is 1 h. The test results are shown in Fig. 5.15. It can be seen that after 1000 cycles, for both cases, there is no opening yet. However, the resistance of the FCOB assemblies with Cu bumps increases to about 29 percent.

FIGURE 5.15 Thermal cycling test results (−20 to 110°C, 15-min ramp and 15-min dwell).

5.10

CHAPTER FIVE

FIGURE 5.16 SIR test results.

On the other hand, the increase in resistance of the FCOB assemblies with Au bumps is only 5.3 percent. This could be due to more degradation of the Cu-bumped FCOB than that of the Au-bumped FCOB assemblies after thermal cycling. From the present results, it is expected that the Au-bumped FCOB with ACF assemblies should have a better thermal fatigue life than the Cu-bumped FCOB with ACF assemblies.

5.2.5

SIR TEST RESULTS OF ACF FCOB ASSEMBLIES

Surface insulation resistance (SIR) testing is one of the most widely used techniques to assess the electrical performance reliability in electronic packaging. Leakage currents are monitored as a function of time at predetermined temperature, humidity, and bias voltage conditions. Leakage currents between closely spaced bumps and pads are sensitive indicators and are good signals of potential field risks. The SIR values of 100 MΩ or higher are acceptable for commercial and industrial applications, and 500 MΩ is acceptable for military requirements. Figure 5.16 shows the SIR test (85°C/85% RH at 10-V bias) results for the ACF-bonded FCOB assemblies. It can be seen that ACF is acceptable for all of the cases under consideration.

5.2.6

SUMMARY

The Au-bumped, Cu-bumped, and Ni-Au-bumped flip chips have been assembled on Cu-Ni-Au and OCC PCBs with ACF. Important parameters and process steps such as the wafer; wafer bumping with Au, Cu, and Ni-Au; PCB; ACF; tacking; lamination; pick and place; and bonding have been discussed. Furthermore, the ACFbonded FCOB assemblies have been subjected to thermal cycling and SIR tests. Some important results are summarized as follows: 1. The ACF-bonded FCOB assembly yield is strongly affected by the kinds of bumps (Au, Cu, and Ni-Au) on the chip. A flip chip with Cu bumps has the highest assembly yield, and that with Ni-Au bumps has the lowest.

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.11

2. The ACF-bonded FCOB assembly yield is strongly affected by the flatness of the PCB. Also, in this study, a PCB with OCC pads leads to a better assembly yield than a PCB with Cu-Ni-Au pads. 3. There is no opening in the ACF-bonded flip chip on Cu-Ni-Au PCB assemblies after 1000 temperature cycles (−20 to 110°C). The resistance change due to 1000 temperature cycles of the Au-bumped flip chip assemblies (5.3 percent) is smaller than that of Cu-bumped flip chip assemblies (29 percent). 4. In this study, the ACF-bonded FCOB assemblies meet the SIR test requirements for commercial, industrial, and military applications.

5.3 COPPER-WIRED WLCSP WITH SOLDERS OR ADHESIVES ON SUBSTRATES The electroplated copper-wired WLCSP, developed by Fujitsu Computer Packaging Technologies, has been discussed in Chap. 4, Sec. 4.6.The assembly of this WLCSP on the PCB or substrate has also been reported in Ref. 38. Figure 5.17 shows a typical

FIGURE 5.17 Electroplated copper wire soldered to a substrate.

5.12

CHAPTER FIVE

cross section of the wire interconnect technology (WIT) assembly. In this case, the copper-wired WLCSP is soldered on the substrate. However, the following two points should be emphasized: 1. Adhesives work as well as solders. 2. The solder materials can be lead-free. Usually, the solder or adhesive materials are stencil- or screen-printed on the substrate. The thermal and electrical performance, as well as the solder joint reliability, of this assembly have been demonstrated in Ref. 38.

5.4 MICROSPRING WLCSP WITH SOLDERS OR ADHESIVES ON PCB/SUBSTRATE The wire-bonding gold-wired WLCSP, developed by FormFactor, has been discussed in Chap. 4, Sec. 4.7. The assembly of this WLCSP on the PCB or substrate has also been reported in Ref. 39. Figure 5.18 shows a typical photo of the microspring assembly. It can be seen that the S-shape microsprings connect to the PCB through a solder, which is printed on the PCB with a stencil and reflowed. If an adhesive is used, then it will be printed on the PCB with a screen and cured. The solder joint reliability of this assembly has been demonstrated in Ref. 39.

5.5

Au-STUD-BUMPED WLCSP WITH ICA ON PCB

The materials, process, and equipment of wire-bonding gold-stud-bumped WLCSPs have been discussed in Chap. 4, Sec. 4.8. In this section, the materials, process, and equipment of gold-stud-bumped WLCSP bonding (SBB) on PCB or substrate are briefly discussed.

FIGURE 5.18 Wire-bonding S-shape microsprings soldered to a substrate.

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.5.1

5.13

MATERIALS AND PROCESS FLOW

Figure 5.19 shows the process flow of the SBB technology. The following can be seen: ●

●

●

After leveling the Au-stud bumps on the chip (or on the wafer and after dicing), as discussed in Chap. 4, Sec. 4.8.1, the individual chip is flipped over and placed in a rotating disk containing a shallow bath of ICA, such as the Ag-Pd paste. Once the ICA is transferred to the stud bumps, the chip is mounted on top of the PCB or substrate with a load of 2 gf per bump. This is followed by curing at a temperature ranging from 120 to 180°C.

The height of the ICA is usually controlled by a doctor blade and is about twothirds of the height of the stud bump, including the leveled tail. Figure 5.20 shows a Au-stud bump after dipping in an ICA made by Panasert’s machines. It can be seen that in order to avoid the shorting of the neighboring bumps, the ICA is only applied on the top and the upper sides of the stud bump. The final process step is to apply the underfill on one or two adjacent sides of the chip. Due to the capillary action, the underfill will flow and fill the gap between the chip and the PCB or substrate. After curing the underfill material, it will cement the chip on the PCB or substrate. It should be noted that underfill encapsulants are very difficult, if not impossible, to rework. On the other hand, due to its thermoplastic nature (which offers only a limited adhesion strength), the ICA joint is very easy to rework. Therefore, most of the tests and rework should be done before the underfill process. In this case (and for chips with peripheral pads), a small amount of nonconductive adhesive can be applied to the chip center area on the PCB or substrate before chip placement and

FIGURE 5.19 Stud bump bonding (SBB) technology process flow.

5.14

CHAPTER FIVE

FIGURE 5.20 Leveled Au-stud bump after being dipped in ICA.

bonding. This temporary adhesive is cured with the ICA adhesive at the same time and is used to increase the adhesion strength between the chip and the PCB or substrate before underfilling.

5.5.2

EQUIPMENT FOR SBB TECHNOLOGY

As mentioned in Chap. 4, Sec. 4.8.2, there are at least two well-established companies (Panasert and Kulicke and Soffa) who are providing the SBB equipment. Figures 5.21 and 5.22 show the Panasert FCBII(1) and FCBII(2), respectively. FCBII(1) is the standard flip chip bonding for Panasert, and FCBII(2) is a highthroughput, automatic board handing, and IC flip-over feeding machine. Their operating sequences are shown in Fig. 5.23. It should be noted that these machines can be used for not only SBB technology but all other kinds of flip chip technologies. Kulicke and Soffa’s machines for SBB technology have been shown in Fig. 4.24.

5.6

Au-STUD-BUMPED WLCSP WITH ICA ON FLEX

Chip-on-flex (COF) has been used for a long time.36, 41 There are many different kinds of COF [e.g., wire-bonding COF, tape automated bonding (TAB) COF, and flip COF (FCOF)], and their substrate is not rigid but flexible. In this section, the design, materials, process, and reliability of Matsushita’s Au-stud-bumped FCOF with ICA is discussed.

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.15

FIGURE 5.21 Panasert’s flip chip bonder FCBII(1).

A flexible substrate (or simply a type) is much thinner and lighter than the FR-4 epoxy PCB, BT substrate, ceramic substrate, or other rigid substrates. Also, there is the advantage of being able to fold a flexible substrate in order to pack it into a very small package’s case. Thus, with the flexible substrate, ultimately small and lightweight electronic products are possible.

5.16

CHAPTER FIVE

FIGURE 5.22 Panasert’s flip chip bonder FCBII(2).

5.6.1

MATERIALS AND PROCESS

The materials and process of SBB technology with ICA on PCB have been discussed in Sec. 5.5 of this chapter. Figure 5.24 shows a schematic of Matsushita’s SBB technology with ICA on a tape, and Fig. 5.25 shows the process flow.42 It can be seen that the Au-stud bumping and most of the processes are the same for both cases. The key difference is the substrate (i.e., the PCB is rigid and the tape is flexible). To keep the liquid crystal polymer (LCP) tape flat and fix during assembly, it is flattened on an aluminum plate with an adhesive sheet whose adhesive strength is easily lost beyond 160°C. After the chip placement, the ICA and the temporary

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.17

FIGURE 5.23 Operation sequence of Panasert’s flip chip bonder FCBII.

adhesive are cured at 120°C for 2 h in a convection oven. Then, the underfill resin is cured at 150°C for 2 h in a convection oven. Matsushita’s LCP tape for the Au-stud-bumped WLCSP is shown in Fig. 5.26.The dimensions are 30 × 30 × 0.05 mm. There are 248 periphery pads and their pitch is 0.15 mm. The dielectric constant, TCE, and modulus of the LCP tape are, respectively, 3 (at 1 MHz), 15 × 10−6/°C, and 6.86 GPa. Compared with those (4.8, 16 × 10−6/°C, and 21.4 GPa) of FR-4 epoxy PCB, it can be seen that the LCP is more suitable for high-frequency applications (lower dielectric constant) and that it is more easily bent (lower modulus). The moisture absorption of LCP is 0.04 percent after holding at 23°C for 24 h.

5.18

CHAPTER FIVE

FIGURE 5.24 Au-stud-bumped WLCSP on a flexible substrate with an ICA.

Matsushita’s ICA consists of an organic binder and a conductive filler. The bisphenol-A type with high-molecular-weight epoxy resin, which is flexible over a wide range of temperatures, is used as the organic binder. Flake Ag powder is used as the conductive filler for high conductivity.The viscosity and volume resistivity are, respectively, 30 Pa·s and 1 × 10−4 Ω⭈cm. It should be noted that this ICA is very easy to deform and thus relaxes the thermal stress due to thermal expansion mismatch between the chip and the tape. The material properties of the temporary adhesive are TCE = 29 × 10−6/°C; modulus = 8 GPa; Tg = 119°C; and viscosity = 42 Pa·s. One can see that ● ●

The viscosity is high enough not to form large voids during assembly. The glass transition temperature Tg is low enough to be cured quickly.

FIGURE 5.25 Matsushita’s process flow of Au-stud-bumped WLCSP on a flexible substrate with an ICA.

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.19

FIGURE 5.26 Matsushita’s flexible substrate.

The material properties of the underfill resin are TCE = 26 × 10−6/°C; modulus = 11.4 GPa; Tg = 123°C; and viscosity = 5 Pa·s. It consists of an epoxy resin of acid anhyderide type and 60 wt % of globular SiO2 fillers. Figure 5.27(a) shows a typical crosssection of the Au stud-bumped WLCSP on the LCP substrate with an ICA.

5.6.2

QUALIFICATION TESTS AND RESULTS

Matsushita’s Au-stud-bumped WLCSPs on the LCP substrate with the ICA are subjected to the multiple reflow test, pressure cooker test, and thermal shock test. The test conditions for the reflow soldering are as follows: after 168 h of 85°C/85% RH, three times reflow with 240°C for 5 s (JEDEC level 1). For the pressure cooker, the test conditions are 100 h at 121°C and 2 atms. For thermal shock the test conditions are −55 (5 min) +125 (5 min), liquid to liquid. The connection resistance per bump is measured using the four-point probe method. These test results are shown in Figs. 5.27(b) through 5.30. It can be seen from Fig. 5.27(b) that there is no crack of the Au-stud-ICA interconnect.Also, the chip thickness

5.20

CHAPTER FIVE

(a)

(b)

FIGURE 5.27 Typical cross sections of Au-stud-bumped WLCSP on a flexible substrate with an ICA after tests.

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

FIGURE 5.28 Contact resistance under JEDEC level 1 test.

FIGURE 5.29 Contact resistance under pressure cooker test.

5.21

5.22

CHAPTER FIVE

FIGURE 5.30 +125°C).

Contact resistance under thermal shock (liquid-to-liquid) test (−55 and

is 0.4 mm; the LCP tape thickness is 0.05 mm; the underfill thickness is 0.07 mm; and the ICA thickness is about 0.04 mm. Figures 5.28 through 5.30 show, respectively, that the connection resistance of the Au-stud-ICA joint on the LCP is stable under the multiple reflow test, pressure cooker test, and thermal shock test.

5.7

Au-STUD-BUMPED WLCSP WITH ACP/ACF ON PCB

The material and process flow of Au-stud-bumped WLCSPs with ACF/ACP on the PCB or substrate are almost the same as those of Au-, Cu-, or Ni-Au-bumped WLCSPs with ACF/ACP on PCB, as discussed in Sec. 5.2 of this chapter, except for the bump structure and material. As mentioned earlier, since the thermal setting adhesive in most of the ACP/ACF doesn’t contain nonconductive fillers, its TCE is very large and the bonded assembly consists of many voids. To achieve the same level of reliability as the Au-stud-bumped WLCSP with ICA on the PCB with underfill encapsulant, some amount of nonconductive fillers (in addition to the conductive fillers) are incorporated into the ACF/ACP. In this section, the effects of nonconductive fillers on the ACP/ACF joint reliability are presented.

5.7.1

ACF/ACP WITH NONCONDUCTIVE FILLERS

The Korea Advanced Institute of Science and Technology (KAIST)43 uses the Ni as the conductive filler and silica as the nonconductive filler. They mix the silica (5 to 45 wt %), the Ni, and the liquid epoxy to produce anisotropic conductive adhesives

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.23

(ACAs) of 10, 30, and 50 wt % total (conductive and nonconductive) filler content. Surface modification of fillers is performed to achieve uniform dispersion of filler inside the epoxy matrix of the ACA composite. The ACAs are formulated by mixing fillers, liquid epoxy resin, and a hardener. The mixtures are stirred and degassed under a vacuum for 3 h to eliminate the air that is induced during stirring. A differential scanning calorimeter (DSC), thermomechanical analysis (TMA), dynamic mechanical analysis (DMA), and thermogravitational analysis (TGA) are used to investigate the curing conditions and material properties of the modified ACAs.

5.7.2

DSC MEASUREMENT RESULTS

Figure 5.31a shows the effect of filler contents on the curing profiles, and Fig. 5.31b shows the effect of filler contents on Tg of the ACA composite materials. The following can be seen: ●

●

The increase of filler contents slightly shifts the curing onset temperature and peak temperature to the higher temperature. The addition of Ni and silica fillers slightly modifies the shape of the DSC curves and increases the Tg.

5.7.3

DMA MEASUREMENT RESULTS

Fig. 5.32, a and b, shows the effect of filler contents on the storage modulus and loss modulus, respectively, of the ACA composite materials. One can see the following: ●

●

●

For all the filler contents, the higher the temperature the lower the storage modulus. The higher the filler contents the higher the storage modulus, especially at room temperature. The Tg (characterized by the knee in the loss modulus curve) increases as the filler content increases.

These behaviors could be due to the increasing interactions of polymer/filler in the ACA composites.

5.7.4

TMA MEASUREMENT RESULTS

Figure 5.33 and Table 5.1 (α1 is the TCE below TgTMA, and α2 is the TCE above TgTMA) show the effect of filler contents on the TCE and TgTMA of the ACA composite materials. One can be see the following: ● ● ●

The higher the filler content the higher the TgTMA. The higher the filler content the lower the α1. The filler content doesn’t affect α2 significantly.

5.24

CHAPTER FIVE

(a)

(b)

FIGURE 5.31 DSC curves of ACA specimens with silica and nickel fillers of various contents (10, 30, and 50 wt %). (a) The curing profiles and (b) the glass transition curves.

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.25

(a)

(b)

FIGURE 5.32 DMA curves of ACA specimens with silica and nickel fillers of various contents (10, 30, and 50 wt %). (a) The storage modulus and (b) the loss modulus.

5.26

CHAPTER FIVE

FIGURE 5.33 TMA curves of ACA specimens with silica and nickel fillers of various contents (10, 30, and 50 wt %).

Thus, higher filler contents are not usable for the thermal fatigue reliability of the ACA joints.

5.7.5

TGA MEASUREMENT RESULTS

Figure 5.34 shows the effect of filler contents on the decomposition temperature and weight loss of ACA composites. The following can be seen: ● ●

The higher the filler content the lower the weight loss. The filler content doesn’t affect the decomposition temperature (393°C) of these ACA composites.

5.7.6

85°C/85% RH TEST AND RESULTS

The test flip chip on the PCB (34 × 37 mm) as well as the Au stud bumps after leveling are shown in Fig. 5.35. The dimensions of the chip are 5 × 5 mm. It has 48 pads (60 µm in diameter) on a 130-µm pitch. The PCB is made of FR-4 epoxy with Ni-Au fin-

TABLE 5.1 TgTMA and CTE of ACA Composites Below and Above TgTMA ACA composite

TgTMA (°C)

α1 (ppm/°C)

α2 (ppm/°C)

ACA with 10 wt% filler

87.62

87.9

3960

ACA with 30 wt% filler

93.53

76.1

3630

ACA with 50 wt% filler

98.77

60.7

3920

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.27

FIGURE 5.34 TGA curves of ACA specimens with silica and nickel fillers of various contents (10, 30, and 50 wt %).

ishing. Figure 5.36 shows the cross sections of the Au-stud-bumped WLCSP on a PCB with an ACA containing both conductive and nonconductive fillers. They are very obvious. The contact resistance of a single interconnect is measured using a four-point probe method. Figure 5.37 shows the contact resistance measurement results during the 85°C/85% RH test (Fig. 5.37a) and 85°C/dry test (Fig. 5.37b). It should be noted that no catastrophic failures are observed,43 and the following can be seen: ●

●

●

The contact resistance of the ACAs with 30 and 50 wt % filler contents is very stabilized up to 1000 h of 85°C/85% RH test. The contact resistance of the ACA with 10 wt % filler contents is stabilized up to 500 h of 85°C/85% RH test and then increases. The contact resistance of the ACAs with 10, 30, and 50 wt % filler contents is very stabilized during all the 1000 h of 85°C/dry test.

5.7.7

THERMAL CYCLING TEST AND RESULTS

Figure 5.38 shows the contact resistance measurement results during the thermal cycling (−60 to 150°C, air-to-air). One can see the following: ● ● ●

The ACA with 10 wt % filler contents cannot pass 300 cycles. The ACA with 30 wt % filler contents cannot pass 400 cycles. The ACA with 50 wt % filler contents passed 700 cycles.

5.28

CHAPTER FIVE

(a)

FIGURE 5.35 KAIST’s Au-stud bumps (a) and test assembly (b).

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.29

(b)

FIGURE 5.35 (Continued) KAIST’s Au-stud bumps (a) and test assembly (b).

These results show that filler contents are very important for the ACA joint reliability. Just like the underfill materials, higher filler contents will lead to lower TCE and higher modulus ACAs and, consequently, higher thermal fatigue reliability of the ACA joints.

5.8 Au-STUD-BUMPED WLCSP DIFFUSED ON Au-PLATED PCB WITH NCA The Au-stud bumps without leveling can be bonded on a Au-plated PCB with thermal compression. The interconnect long-term reliability can be assured by the nonconductive adhesive (NCA). In this section, the results obtained by Sharp are presented.44

5.30

CHAPTER FIVE

(a)

(b)

FIGURE 5.36 KAIST’s Au-stud bumps on a PCB with an ACA with both conductive and nonconductive fillers. (a) Optical view of cross section of flip chip assembly using an ACA; (b) enlarged view of the interconnection formed by Au stud bump and Ni particles between chip I/O and substrate pad.

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

(a)

(a)

FIGURE 5.37 dry test.

Contact resistance under (a) 85°C/85% RH test and (b) 85°C/

5.31

5.32

CHAPTER FIVE

FIGURE 5.38 Contact resistance under thermal cycling test (−60 to +150°C for 700 cycles).

5.8.1

MATERIALS AND PROCESS

Figure 5.39 shows a Au-stud-bumped WLCSP on PCB with NCA assembly. Figure 5.40 shows the Au-stud bumps (which can be made with the process discussed in Sec. 5.5) without leveling. The bump diameter is 82 ⫾ 3 µm, bump height is 64 ⫾ 3 µm, and bump pitch is 110 µm. The bump shear strength is 0.44 ⫾ 0.04 N/bump. The specifications of the chip and the PCB are shown in Table 5.2. It can be seen that the chip dimensions are 10 × 10 × 0.2 mm. It has 316 pads on a 110-µm pitch. The PCB is made of FR-5 glass epoxy, and the dimensions are 100 × 50 × 0.2 mm. The pad finishing is Cu-Ni-Au. The NCA is made of silica particles and thermal setting epoxy resin. The material properties are as follows: modulus = 7.8 GPa; TCE = 28 × 10−6/°C; Tg = 150°C; and average silica filler size = 0.4 µm.

FIGURE 5.39 Au-stud-bumped WLCSP on Au-plated PCB with an NCA.

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.33

FIGURE 5.40 Au stud bumps without leveling.

Sharp’s bonding process is very simple. First, dispense the NCA on the PCB. Next, place the Au-stud-bumped WLCSP, as shown in Fig. 5.40 face-down on the PCB. Finally, the NCA between the mounted chip and the PCB is hardened under heat and pressure using a flip chip bonder equipped with a constant-heat tool, which completes the process. Figure 5.41a shows a cross section of the Au-studbumped WLCSP with NCA on the Au-plated PCB assembly. The bonding condi-

TABLE 5.2 Specifications of the Chip and the Substrate

Material Size Thickness

Substrate

Chip

FR-5 glass-epoxy (Tg: 180–190°C)

Si

100mm × 50mm

10mm × 10mm

0.2 mm

0.2 mm

I/Os

316

316

Pitch

110 µm

110 µm

Flash-Au/Ni/Cu

Au bump/Al Pad

Electrode

5.34

CHAPTER FIVE

(a)

(b)

FIGURE 5.41 (a) Au stud bumps without leveling (gold-gold thermocompression) on the Auplated PCB with an NCA. (b) Au-stud-bumped joints showing nonuniformity.

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.35

tions are as follows: bonding temperature = 337°C; bonding force = 300 N/chip; and bonding time = 5 s. It can be seen that the gap between the chip and the PCB is about 20 µm. One of the drawbacks of Au-Au metallic diffusion is joint nonuniformity, as shown in Fig. 5.41b. It can be seen that the left-hand joint is larger than the righthand joint. Among other reasons, this is due to the variation of passivation opening of chip pads, which defines the bump deformation during bonding.

5.8.2

RELIABILITY

The effects of different bonding temperatures, bonding forces, and bonding times on the performance (contact resistance) of the Au-stud-bumped WLCSP with NCA on the Au-plated PCB assemblies subjected to the 85°C/85% RH test condition are shown in Figs. 5.42 through 5.44. To make a good Au-Au metallic diffusion bond: ● ● ●

A bonding force of 300 N/chip is required. The bonding time is not significant. The bonding temperature (337°C) is adequate.

Figure 5.45 shows the thermal cycling test (−40 to 125°C, 10-min dwells) results of the Au-stud-bumped WLCSP with NCA on the Au-plated PCB with a bonding temperature of 337°C, a bonding force of 300 N/chip, and a bonding time of 3.5 s. It can be seen and confirmed that these process parameters will lead to sufficient reliable interconnects for practical use.

FIGURE 5.42 Contact resistance under 85°C/85% RH test (200-N/ chip bonding load and 5-s bonding time).

5.36

CHAPTER FIVE

FIGURE 5.43 Contact resistance under 85°C/85% RH test (300-N/chip bonding load and 5-s bonding time).

FIGURE 5.44 Contact resistance under 85°C/85% RH test (300-N/chip bonding load and 337°C bonding temperature).

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.37

FIGURE 5.45 Contact resistance under thermal cycling test (−40 to +125°C, 10-min dwell). The bonding temperature is 337°C, bonding force is 300 N/chip, and bonding time is 3.5 s.

5.9 Au-STUD-BUMPED WLCSP DIFFUSED ON Au-PLATED FLEX WITH NCA The Au-stud-bumped flip chip on Au-plated flexible substrate with NCA has been studied by NEC.45 Their results are presented in this section.

5.9.1

MATERIALS AND PROCESS

Figure 5.46 shows a schematic of NEC’s tape gold-gold gang bond BGA (T-G2BGA) package. Its assembly process flow is shown in Fig. 5.47. The focus of this section is

FIGURE 5.46 NEC’s T-G2BGA structure.

5.38

CHAPTER FIVE

FIGURE 5.47 Process flow of NEC’s T-G2BGA package.

only on the materials and assembly process of the Au-stud-bumped WLCSP on the Au-plated tape substrate with NCA. The NEC Au-stud bump is shown in Fig. 5.48 (very similar to that shown in Fig. 5.40). The chip dimensions are 7.33 × 14.26 × 0.32 mm.There are 94 peripheral pads and 64 center pads, and they are on a 150-µm pitch. The two-layer tape is made of polyimide (50 µm thick), and the conductor thickness is 18-µm copper + 2 µm of electroplated nickel + 0.5–1.5 µm of electroplated Au. The underfill material properties are shown in Table 5.3. It can be seen that the underfill consists of 62 wt % of filler contents and the resin is epoxy/amine. Before assembly, the gold-plated pads on the tape are cleaned with argon plasma dry cleaner for good interconnection. Then, the flip chip is bonded on the tape substrate using thermocompression gold-gold interconnection technology. After the bonding, just like the conventional flip chip technology, the NCA (underfill) is dispensed on one or two adjacent sides of the chip on the tape substrate and then is cured.

5.9.2

RELIABILITY

The effects of bonding forces, electroplating thickness of Ni and Au on the pads of the tape substrate, and bonding time (the bonding temperature is 270°C) on the shear strength of the Au-stud-bumped assembly are shown in Figs. 5.49 through 5.52, in which the following can be seen:

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.39

FIGURE 5.48 Nonleveled (acute tail) Au stud bump.

●

●

● ●

The shear strength is not affected by the Ni and Au thickness (thus, a 2-µm thickness of Ni and a 0.5-µm thickness of Au are chosen). The deformation of chip pads doesn’t increase significantly for the increase of bonding force. The shear strength increases as the bonding force increases. The bonding of 7.5 s yields the best interconnect.

TABLE 5.3 Underfill Resin Properties Item

Unit

Resin Filler content Tg CTE*

Data Epoxy/Amine

wt %

62

°C

90

ppm
29

>Tg

100

(TMA) Bending modulus

GPa

9.5

Bending strength

MPa

130

Cl

0.5

ppm Na+

<1

Purity (after PCT 20 h)

+

K

<1

5.40

CHAPTER FIVE

FIGURE 5.49 Effects of bonding force and tape plating thickness on shear test force (strength), 94 bumps/chip.

FIGURE 5.50 Effects of bonding force and tape plating time on bonding deformation.

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.41

FIGURE 5.51 Effects of bonding force and bonding time on shear test force (strength), 64 bumps/chip.

Thus, the optimal parameters for Au-Au thermocompression are as follows: bonding temperature = 270°C; bonding stage temperature = 70°C; bonding time = 7.5 s; and bonding force = 100 gf/bump. A closer look at the IMC (after dry-etching) of the Au-Au bonding is shown in Fig. 5.53.There is no crack and no clear boundary between the Au stud bump and the gold-plated tape under the optimum bonding conditions.

FIGURE 5.52 Effects of bonding force and bonding time on bonding deformation.

5.42

CHAPTER FIVE

FIGURE 5.53 Interface between the Au stud bump and the flip chip pad.

5.10 Cu-STUD-BUMPED WLCSP WITH LEAD-FREE SOLDERS ON PCB As mentioned earlier, due to its rigidity (very little compliance), stud-bumped WLCSPs are usually attached to the PCB or substrate with adhesives cured at a temperature ranging from 120 to 180°C. Also, most of the adhesives for SBB technology applications are easy to deform; thus, they relax the thermal stresses due to the thermal expansion mismatch between the silicon chip and the organic substrate during the cooldown and operation of the assembly. However, unlike solders (which have the self-alignment characteristic during reflow), adhesives require very high placement accuracy (which will decrease throughput and increase costs). Thus, stud-bumped WLCSPs on PCBs or substrates with lead-free solder could be an alternative. Since Au stud bumps are too much for the solder joints to remain ductile, Cu stud bumps are chosen by the Georgia Institute of Technology (GIT) for their investigation.46

5.10.1

MATERIALS AND PROCESS

The lead-free solder paste studied by GIT is Sn-3.5Ag-0.5Cu, which consists of type 4 solder particles and no-clean, low-solid flux. It is deposited onto the PCB by a metal stencil having 150-µm square apertures and a 50-µm thickness. The Cu stud bumping developed by Furukawa has already been discussed in Chap. 4, Sec. 4.9. By using a flip chip bonder, the Cu-stud-bumped WLCSP is placed on the pasted PCB. The reflow temperature profile is as follows: ramp rate = 1.7°C/s; soak temperature = 130°C/150°C; soak time = 33 s; peak temperature = 242°C; time above the melting temperature = 43 s. Before dispensing the underfill, the PCB is baked at 100°C for 2 h to reduce moisture contents. The underfill is dispensed at

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.43

FIGURE 5.54 (a) Au-stud- and (b) Cu-stud-bumped WLCSP on a PCB with Sn-3.5 Ag-0.5Cu leadfree solder joints.

90°C and cured at 150°C for 7 min. Figure 5.54, a and b, shows, respectively, the Austud-bumped and Cu-stud-bumped WLCSP on PCB with the lead-free Sn-3.5Ag0.5Cu solder joint.

5.10.2

RELIABILITY

The Au-stud- and Cu-stud-bumped WLCSP on PCB with the lead-free solder are assembled (20 each) and are subjected to a thermal shock (liquid-to-liquid) test. The test condition is −50 to 125°C with 10-min cycles. The test results are shown in Fig. 5.55. It can be seen that 30 percent of both of the Au-stud- and Cu-stud-bumped WLCSP lead-free assemblies failed even before the test started. Also, more than 90 percent of the Cu-stud- and Au-stud-bumped WLCSP lead-free assemblies failed, respectively, before 100 cycles and 500 cycles. Figure 5.56, a and b, shows, respectively, the cross section of the Au-stud- and Cu-stud-bumped WLCSP tested samples. These could be due to the following: ●

●

●

The microhardness of Cu is harder than that of Au; thus, the Cu stud is less compliant. The thermal expansion mismatch between the silicon chip and the organic PCB initiates the crack near the interface between the chip pad and the bump during the cooldown of reflow soldering. The pad area on the PCB is much larger than that on the chip; thus, for the same shear force, there are more shear stresses on the chip side. The following should be reemphasized:

●

●

The compliance of the stud-bumped WLCSP assemblies with solders is much less than that with adhesives. The bonding temperature of the stud-bumped WLCSP assemblies with solders (especially lead-free) is much higher than that with adhesives.

5.44

CHAPTER FIVE

FIGURE 5.55 Thermal shock test results of Au-stud- and Cu-stud-bumped WLCSP on a PCB with Sn-3.5Ag-0.5Cu lead-free solder joints.

FIGURE 5.56 Failure modes of (a) Au-stud- and (b) Cu-stud-bumped WLCSP on a PCB with Sn3.5Ag-0.5Cu lead-free solder joints after thermal shock.

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE ●

5.45

The bonding time of the stud-bumped WLCSP assemblies with solders is much longer than that with adhesives.

Thus, to make SBB with lead-free solder technology work, the following are necessary: ● ● ● ● ● ●

To use less energy to make the Cu stud bumps To make the Cu stud bumps more compliant by annealing To better design the pad configuration on the chip and the PCB To use lower-melting-point lead-free solders To use less stiff (more compliance) lead-free solders To optimize the reflow temperature profile for this specific application

ACKNOWLEDGMENTS The authors would like to thank L. Moresco, D. Love, W. Chou, D. Horine, C. Wong, S. Beilin, and V. Holalkere of Fujitsu Computer Packaging Technologies; J. Healy of FormFactor; K. Tsunoi, T. Kusagaya, and H. Kira of Fujitsu; T. Garvin of Panasonic; P. Lin of K&S; Y. Kumano, Y. Tomura, M. Itagaki, and Y. Bessho of Matsushita; M. Yim and K. Paik of KAIST; Y. Sakamoto, H. Matsubara, K. Yamamura, and T. Nukii of Sharp; S. Isozaki, T. Kimura, T. Shimada, and H. Nakajima of NEC; S. Zama, T. Hikami, and H. Murata of Furukawa; D. Baldwin of Georgia Institute of Technology (GIT); I. Watanabe, K. Takenura, N. Shiozawa, O. Watanabe, K. Kojima, A. Nagai, and T. Tanaka of Hitachi; and the people of PICOPAK for sharing their useful and important information with the industry.

REFERENCES 1. Turbini, L., “Examining the Environmental Impact of Lead-Free Soldering Alternatives,” Proceedings of IEEE, International Symposium on Electronics and the Environment, pp. 46–53, 2000. 2. Turbini, L., “Assessing the Environmental Implications of Lead-Free Soldering,” Proceedings of Electronics Goes Green 2000+, Berlin, pp. 37–42, 2000. 3. Liu, J., Conductive Adhesives for Electronics Packaging, Electrochemical Publications Ltd., Port Erin, Isle of Man, UK, 1999. 4. Lau, J. H., “Flip Chip on PCBs with Anisotropic Conductive Film,” Advanced Packaging, pp. 44–48, July/August 1998. 5. Miebner, R., R. Aschenbrenner, and H. Reichl, “Reliability Study of Flip Chip on FR4 Interconnections with ACA,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 595–601, June 1999. 6. K. Gustafsson, S. Mannan, J. Liu, Z. Lai, D. Whalley, and D. Williams, “The Effect of Temperature Ramp Rate on Flip-Chip Joint Quality and Reliability Using Anisotropically Conductive Adhesive on FR-4 Substrate,” IEEE/ECTC Proceedings, pp. 561–566, May 1997. 7. Watanabe, I., K. Takemura, N. Shiozawa, O. Watanabe, K. Kojima, A. Nagai, and T. Tanaka, “Anisotropic Conductive Adhesive Films for Flip-Chip Interconnection,” Proceedings of the 9th International Microelectronics Conference, Omiya, Japan, pp. 328–332, 1996.

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8. Watanabe, I., N. Shiozawa, K. Takemura, and T. Ohta, “Flip Chip Interconnection Technology Using Anisotropic Conductive Adhesive Films” in Flip Chip Technologies, Lau, J. H., ed., McGraw-Hill, New York, pp. 301–315, 1996. 9. Aschenbrenner, R., R. Miebner, and H. Reichl, “Adhesive Flip Chip Bonding on Flexible Substrates,” Proceedings of the IEEE Polymeric Electronics Packaging, pp. 86–94, October 1997. 10. Wong, C. P., D. Lu, L. Meyers, S. Vona, and Q. Tong, “Fundamental Study of Electrically Conductive Adhesives (ECAs),” Proceedings of the IEEE Polymeric Electronics Packaging, pp. 80–85, October 1997. 11. Lu, D., C. P.Wong, and Q.Tong,“Mechanisma Underlying the Unstable Contact Resistance of Conductive Adhesives,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 342–346, June 1999. 12. Nguyen, G., J. Williams, F. Gibson, and T. Winster, “Electrical Reliability of Conductive Adhesives for Surface Mount Applications,” Proceedings of International Electronic Packaging Conference, pp. 479–486, 1993. 13. Nguyen, G., J. Williams, and F. Gibson, “Conductive Adhesives: Reliable and Economical Alternatives to Solder Paste for Electrical Applications,” Proceedings of ISHM Symposium, pp. 510–517, 1992. 14. Li, L., and J. Morris, “Reliability and Failure Mechanism of Isotropically Conductive Adhesive Joints,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 114–120, May 1995. 15. Chung, K., T. Devereaus, C. Monti, and M. Yan, “Z-Axis Conductive Adhesives as Solder Replacement,” Proceedings of International SAMPE Electronic Conference, vol. 7, pp. 473–481, 1994. 16. Yamaguchi, M., F. Asai, F. Eriguchi, and Y. Hotta, “Development of Novel Anitotropic Conductive Film (ACF),” Proceedings of IEEE Electronic Components and Technology Conference, pp. 360–364, June 1999. 17. Hotta, Y., “Development of 0.025 mm Pitch Anisotropic Conductive Film,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1042–1046, June 1998. 18. Dernevik, M., R. Sihlbom, K. Axelsson, Z. Lai, J. Liu, and P. Starski, “Electrically Conductive Adhesives at Microwave Frequencies,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1026–1030, June 1998. 19. Kang, S. K., and S. Purushothaman, “Development of Low Cost, Low Temperature Conductive Adhesives,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1031–1035, June 1998. 20. Yim, M., K. Paik,T. Kim, and Y. Kim,“Anisotropic Conductive Film (ACF) Interconnection for Display Packaging Applications,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1036–1041, June 1998. 21. Wei, Y., and E. Sancaktar, “A Pressure Dependent Conduction Model for Electrically Conductive Adhesives,” Proceedings of International Symposium on Microelectronics, pp. 231–236, 1955. 22. Liu, J., and R. Rorgren, “Joining of Displays Using Thermosetting Anisotropically Conductive Adhesives,” Journal of Electronics Manufacturing, 3:205–214, 1993. 23. Ito, S., M. Mizutani, H. Noro, M. Kuwamura, and A. Prabhu, “A Novel Flip Chip Technology Using Non-Conductive Resin Sheet,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1047–1051, June 1998. 24. Tummala, R. R., Fundamentals of Microsystems Packaging, McGraw-Hill, New York, 2001. 25. Tummala, R. R., E. Rymaszewski, and A. Klopfenstein, Microelectronics Packaging Handbook, Chapman & Hall, New York, 1997. 26. Tummala, R. R., and E. Rymaszewski, Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York, 1989.

WLCSPS WITH SOLDERLESS BUMPS ON PCB/SUBSTRATE

5.47

27. Lau, J. H., and S. W. R. Lee, Microvias for Low-Cost High-Density Interconnects, McGrawHill, New York, 2001. 28. Lau, J. H., Low-Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, McGraw-Hill, New York, 2000. 29. Lau, J. H., and S. W. R. Lee, Chip Scale Package, Design, Materials, Process, Reliability, and Applications, McGraw-Hill, New York, 1999. 30. Lau, J. H., C. Wong, J. L. Prince, and W. Nakayama, Electronic Packaging, Design, Materials, Process, and Reliability, McGraw-Hill, New York, 1998. 31. Lau, J. H., and Y.-H. Pao, Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine-Pitch SMT Assemblies, McGraw-Hill, New York, 1997. 32. Lau, J. H., Flip Chip Technologies, McGraw-Hill, New York, 1996. 33. Lau, J. H., Ball Grid Array Technology, McGraw-Hill, New York, 1995. 34. Lau, J. H., Chip On Board Technologies for Multichip Modules, Van Nostrand Reinhold, New York, 1994. 35. Jeon, Y., K. Paik, K. Bok, W. Choi, and C. Cho, “Studies on Ni-Sn Intermetallic Compound and P-rich Ni Layer at the Electroless Nickel UBM-Solder Interface and Their Effects on Flip Chip Solder Joint Reliability,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 69–75, May 2001. 36. Lau, J. H., Handbook of Tape Automated Bonding,Van Nostrand Reinhold, New York, 1992. 37. Triggs, W., and C. Byrns, Jr., U.S. Patent No. 3,599,060, August 10, 1971. 38. Moresco, L., D. Love, W. Chou, and V. Holalkere, “Wire Interconnect Technology: An Ultra-High-Density Flip Chip-Substrate Connection Method,” in Flip Chip Technology, Lau, J. H., ed., McGraw-Hill, New York, pp. 367–386, 1996. 39. Healy, J., “The Impact of Microsprings on Wafer Level Packaging of ICs,” Proceedings of the HDI EXPO, pp. 17–36, August 1999. 40. Tsunoi, K., T. Kusagaya, and H. Kira, “Flip Chip Mounting Using Stud Bumps and Adhesive for Encapsulation,” in Flip Chip Technology, Lau, J. H., ed., McGraw-Hill, New York, pp. 357–366, 1996. 41. Zakel, E., and H. Reichl, “Flip Chip Assembly Using Gold, Gold-Tin, and Nickel-Gold Metallurgy,” in Flip Chip Technology, Lau, J. H., ed., McGraw-Hill, New York, pp. 415–490, 1996. 42. Kumano, Y., Y. Tomura, M. Itagaki, and Y. Bessho, “Investigation of Chip-on-Flex Application Using SBB Flip-Chip Technique,” Proceedings of International Symposium on Microelectronics, pp. 137–142, September 1999. 43. Yim, M., and K. Paik, “Effect of Non-Conducting Filler Additions on Anisotropic Conductive Adhesives (ACAs) Properties and the Reliability of ACAs Flip Chip on Organic Substrates,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 899–905, May 2000. 44. Sakamoto, Y., H. Matsubara, K. Yamamura, and T. Nukii, “Flip Chip Bonding Technology Using Resin for Adhesion,” Proceedings of International Symposium on Microelectronics, pp. 143–148, September 1999. 45. Isozaki, S., T. Kimura, T. Shimada, and H. Nakajima, “Development of Low Cost, High Reliability CSP using Gold-Gold Interconnection Technology,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 63–68, May 2001. 46. Zama, S., D. Baldwin, T. Hikami, and H. Murata, “Flip Chip Interconnect Systems Using Wire Stud Bumps and Lead Free Solder,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 1111–1117, May 2000.

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CHAPTER 6

ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR IC PACKAGES 6.1

INTRODUCTION

As discussed in Chap. 1, the Waste Electrical and Electronic Equipment and Reduction of Hazardous Substances directives require electronic products to be halogen-free and lead-free due to increasing awareness of environmental compatibility. Chip (wafer)-level interconnects with lead-free solder bumps have been discussed in Chap. 2. Wafer-level chip-scale packages (WLCSPs) with lead-free solder bumps on printed circuit boards (PCBs) or the substrate of flip chip in a package have been presented in Chap. 3. Chip (wafer)-level interconnects with solderless bumps have been discussed in Chap. 4 and WLCSPs with solderless bumps on PCBs, tapes, or the substrate of flip chip in a package have been reported in Chap. 5. In this chapter the halogen (Br or Sb)-free flame-retardant molding compounds for plastic quad flat pack (PQFP), plastic ball grid array (PBGA), and mold array PBGA (MAP-PBGA) packages are discussed. To obtain halogen-free molding compound, it is necessary to maintain flame resistance, even when brominated (Br) epoxy and antimony (Sb) oxide (traditionally used as flame retardants) are eliminated.1–20 This can be achieved by either (1) adding novel flame retardants to the conventional resin, (2) mixing a compound with high filler content to give flame resistance, (3) changing resin construction to inflammable, or (4) combining any of (1), (2), and (3). Unlike Sn-37Pb solder [melting temperature of 183°C and maximum reflow temperature of 220°C], most of the lead-free solders in the SnAgCuX family have melting temperatures above 213°C. Thus, the maximum reflow temperature of the lead-free solders could be 260°C. With this increase of reflow temperature the dimensional deformation and vapor pressure (which are the driving forces for package cracking, delamination, and popcorning)9–20 in the molding compound increase as shown in Table 6.1 and Fig. 6.1. This is because (1) the thermal expansion mismatch within the package is a function of temperature and (2) the generated vapor pressure from moisture absorption of the molding compound is also temperature dependent. Thus, novel epoxy molding compounds (EMCs) that are halogen free and generate no defective products at 260°C of maximum reflow temperature are desperately needed in the electronics industry.

6.2 ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR PQFP PACKAGES The major components of a conventional molding compound are epoxy resin, phenol resin–type hardener, spherical silica, triphenylphosphine as a catalyst, and other 6.1 Copyright © 2003 by The McGraw-Hill Companies, Inc. Click here for terms of use.

6.2

CHAPTER SIX

TABLE 6.1 Stress Increase Factors 240°C

260°C

Estimated maximum vapor pressure

Reflow temperature MPa Rate

3.2 100

4.5 141

Saturated vapor pressure at reflow temp.

Thermal expansion of molding compound

% Rate

0.30 100

0.41 137

Typical data of EMC for SMD

ingredients such as a coupling agent, wax, and carbon black. In the study of novel addition-type flame retardants by Sumitomo,13,14 flame-retarding agents were used to replace spherical silica. The mixture was melted and kneaded after preliminary mixing at room temperature. The obtained material was formed into tablets after being cooled and crushed, and was used for molding.

6.2.1 FLAME RESISTANCE SYSTEMS: ADDITION-TYPE RETARDANTS The new flame retardants studied by Sumitomo are shown in Table 6.2. It can be seen that three groups of materials are considered: an (inorganic) phosphorus group, an (aluminum or magnesium) metal hydrate group, and a (molybdenum and boric) metal compound group. The materials were considered individually as well as in combination. The test specimens used for flame resistance tests were molded by a low-pressure transfer molding machine with a molding temperature of 175°C, a molding pressure of 7 MPa, and a curing time of 120 s (or 10 MPa for 90 s). The postmold curing time was 8 h. Molded specimens of 125 × 13 × 1.6 mm and 125 × 13 × 3.2 mm were used for the UL-94 flammability test. Measurements were taken by recording burning time of the specimens after the flame was removed following 10 s of ignition. This was repeated, again recording the burning time after removing the flame following 10 s of ignition. Five molded specimens were tested and were judged to be V-0 level when the maximum burning time was within 10 s and the sum of burning time was within 50 s.

FIGURE 6.1 Influence of elevated reflow temperature and failure modes.

ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR IC PACKAGES

6.3

TABLE 6.2 New Flame Retardants in Sumitomo Study Flame retardant

Assumed mechanism

Inorganic phosphorus

Oxygen trap

Aluminum hydrate

Discharge of water

Magnesium hydrate

Discharge of water, buildup of char layer

Molybdenum compound

Hydrogen extract, buildup of char layer

Boric compound

Discharge of water

TABLE 6.3 Evaluation Results for Flame Retardants Flame retardant Inorganic phosphorus

Necessary quantity 1%

Defect None

Aluminum hydrate

>15%

Magnesium hydrate

10%

Molybdenum compound

10%

Curability drop, water absorption increase

7%

Curability drop, water absorption increase

Boric compound

Lack of flame resistance, curability drop Curability drop

Studied formulation: biphenyl epoxy/filler content 87%. Necessary quantity: minimum amount of flame retardant to pass UL-94 V-0/1.6 mmt.

The test results for the single addition of novel addition-type flame retardants are shown in Table 6.3. It can be seen that the best flame resistance is in the inorganic phophorus group. Others are not adequate for single addition due to insufficient flame resistance and insufficient curing properties. The test results for combinations of novel addition-type flame retardants are shown in Fig. 6.2. It can be seen that flame resistance is improved by the synergistic

FIGURE 6.2 Combination effects of two different flame-retardant compounds on UL-94 test.

6.4

CHAPTER SIX

effect when the molybdenum compound and the boric compound are used together, although they are not effective when used individually, especially for small amounts.

6.2.2

FLAME RESISTANCE SYSTEMS: NOVEL RESIN SYSTEMS

Various resins such as nitrogen-containing resins are proposed as flame-retardant resins; however, actual use is difficult due to insufficient moldability and moisture resistance. Since the foaming phenomenon is well known in the area of thermoplastic polymers, it was studied for a set of thermoset polymers as shown in Fig. 6.3. The results are shown in Table 6.4 and Fig. 6.4. It can be seen that the longer the distance between functional groups at cross-linked points in the hardener, the higher the flame resistance. Also, flame resistance is related to modulus at heated state, as seen in Fig. 6.4. An enlarged photo of a sample burned in the UL flammability test is shown in Fig. 6.5. It can be seen that the high-modulus compound shows carbonized layers and cracks, but the low-modulus compound with high flame resistance shows carbonized layers and foamed structure.

6.2.3 EFFECTS OF RAISED REFLOW TEMPERATURES ON MOLDING COMPOUNDS In order to study the lead-free reflow temperature resistance of the new compounds, two kinds of packages, 80-pin PQFP and 208-pin PQFP, were used for the evaluation. The body size, leadframe, and chip dimensions for the 80-pin QFP were, respec-

FIGURE 6.3 Resin structures studied by Sumitomo.

ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR IC PACKAGES

6.5

TABLE 6.4 Evaluation Results for Various Resin Systems Molding compound

EMC-1

EMC-2

Epoxy Formulation

Hardener

Flexural modulus Total flaming time

EMC-3

EMC-4

EMC-5

Biphenyl epoxy A

B

C

D

E

240°C

(MPa)

2000

2100

1200

600

1100

1.6 mmt 3.2 mmt

(s) (s)

Burned up 255

111 310

76 52

47 49

61 84

Studied filler content: 87%.

tively, 14 × 20 × 2.7 mm, 42 alloy, and 7.5 × 7.5 mm (with passivation). The body size, leadframe, and chip dimensions for the 208-pin QFP were, respectively, 28 × 28 × 3.2 mm, copper, and 10 × 10 mm (with passivation). The die attach material for the 42 alloy leadframe was epoxy resin group Ag paste A with a curing condition of 200°C for 60 min; for the copper leadframe it was epoxy resin group Ag paste B with a curing condition of 175°C for 30 mins as shown in Table 6.5. These two PQFP packages were treated by the water-absorbing process of the Joint Electronic Device Engineering Council (JEDEC) Level 1 [85°C/85% relative humidity (RH) for 168 h]. After drying, the packages were reflowed at 240°C and 260°C maximum temperatures as shown in the reflow profiles in Fig. 6.6. Specimens were subjected to three repetitions of reflow. The weight of the packages was measured at the start and after moisture absorption and reflow. Also, the amount of absorption before and after reflow was obtained. Surface appearances were inspected visually and the internal elements of the package were studied by scanning acoustic microscopy. In order to find out the influence of raised reflow temperature on the new molding compounds, tests were preformed as shown in Table 6.6. It can be seen from the objective of these tests that (1) Ag paste mounting without chips and without chip

FIGURE 6.4 Effect of modulus of EMC on flammability.

6.6

CHAPTER SIX

FIGURE 6.5 Failure surfaces after flame test.

islands, and (2) without moisture absorption, other than the normal level of chip mounting by Ag paste. Thus, these tests show the influence not only of reflow temperature but also of mounting materials and moisture absorption. The epoxy molding compound is biphenyl-type epoxy resin (EMC-6), which is a mainstream in surface-mount technology packages in use today. The properties of this resin are shown in Table 6.7. The measured amount of absorption and desorption after reflow is shown in Fig. 6.7. It can be seen that the amount of desorption at a maximum 260°C reflow temperature is 1.4 times larger than that at 240°C. This means that the generated vapor pressure is higher at 260°C reflow due to a larger amount of vaporizing moisture. The 80-pin PQFP package reflow resistance is shown in Table 6.8. It can be seen that defects such as cracks and delamination increase when reflow temperature is raised to 260°C from 240°C. Further, delamination of the lead is found in the sample level without chip islands, as shown in Fig. 6.8. TABLE 6.5 Material Properties of Ag Pastes A and B Ag paste Item

Condition

Unit wt%

70

75

CTE 1 (below Tg)

TMA

10−5/°C

3.0

3.0

CTE 2 (above Tg)

TMA

10−5/°C

8.0

8.0

Tg

TMA

°C

125

110

Die shear strength

200°C, 4 mm2

N

10.8

17.6

Flexural modulus

RT

MPa

6400

4900

Water absorption

85°C/85%, 72 h

%

0.4

0.25

Note

Application

Alloy 42

Cu

Ag content

A

B

6.7

ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR IC PACKAGES

FIGURE 6.6 Two reflow temperature profiles for this study.

In summary, the foaming phenomenon seen in a resin system is an effective way to achieve flame resistance by selecting appropriate resins. A synergistic effect is brought about by the different flame-retarding mechanisms of each; for example, molybdenum shares hydrogen abstraction and char formation and boric compounds share dehydration and heat absorption. In summary, in order to resist the raised reflow temperature due to lead-free soldering, the new molding compound resin should decrease the moisture absorption by 30 percent compared to conventional compounds. Also, improvement of the adhesion in the encapsulation resin seems to be important for resisting the raised reflow temperature.

TABLE 6.6 Objectives and Test Conditions for Evaluating the Effects of Elevated Reflow Temperature Evaluation content

Main objective

No chip mounting

Influence of chip and die mount material

No die pad

Grasp of EMC performance without other composed materials

No water absorption treatment

Influence of moisture content

Reflow temperature

Comparison of 240 and 260°C reflow

TABLE 6.7 Material Properties of Molding Compound EMC-6 Item

Unit

CTE

10−5/°C

Flexural strength

MPa

178

22

20

Flexural modulus

MPa

18,600

690

650

Adhesion strength

RT 1.4

240°C 5.4

260°C 5.4

Alloy 42

MPa

18.4

1.7

1.5

Cu

MPa

19.0

1.6

1.4

6.8

CHAPTER SIX

FIGURE 6.7 Effect of reflow treatment on moisture absorption and discharged moisture.

6.2.4 HALOGEN-FREE MOLDING COMPOUNDS FOR LEAD-FREE SOLDERING Based on the studies in Secs. 6.2.1 through 6.2.3 and the guidelines presented in Fig. 6.9 as well as pre-examination of various resin systems, the two resin systems shown in Fig. 6.10 were found by Sumitomo13,14 to be excellent. Their content and material properties are shown in Table 6.9. The resin system with super low viscosity can improve reactions with high crosslink density and makes high filling possible. The super-flexible resin system has low cross-link density; high flexibility, decreasing generated stress; and low moisture absorption due to many aromatic rings in the resin skeleton.

TABLE 6.8 Test Results for 80-Pin PQFP Test no.

T-1

T-2

T-3

T-4

T-5

Yes

Yes

Yes

No

Yes

No

No

Yes

Yes

Yes

No

260

260

260

10

10

10

10

7

0

0

0

0

10

7

0

0

Delamination on die surface

None

None

—

—

None

Delamination on lead finger tips

Small

Large

Large

Large

None

Delamination below die pad

None

Large

Large

—

None

Package structure

Die pad existence Chip mounting

Yes

Yes

Water absorption

85°C/85%, 168 h

Yes

Yes

Reflow temperature

°C

240

260

Number of tested packages

10

External cracks

0

Internal cracks

ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR IC PACKAGES

6.9

FIGURE 6.8 Scanning acoustic microscopy image of 80-pin PQFP without chip pad and chip after 260°C reflow.

FIGURE 6.9 Sumitomo’s strategy and key technology on environmentally friendly epoxy molding compounds.

The test results for these novel resin 80-pin and 208-pin PQFP systems are shown in Figs. 6.11 and 6.12, respectively. In these figures, the failure point is calculated in accordance with following crack points: 0: none 20: small crack within half of length from die pad to lead finger tips 50: middle-size crack within inner lead tips 100: large crack over inner lead tips

6.10

CHAPTER SIX

FIGURE 6.10 Sumitomo’s resin system for environmentally friendly epoxy molding compounds.

as well as delamination points: 0: 10: 20: 50: 100:

none delamination area <5 percent delamination area 5 to 25 percent delamination area 25 to 50 percent delamination area >50 percent

It can be seen from Figs. 6.11 and 6.12 and Table 6.9 that the resin system with super low viscosity can attain the UL V-0 flammability test results without flame retardants if and only if the filler is mixed to 90 percent formulation. However, the super-flexible resin system shows excellent flame resistance regardless of filler contents. Also, both resin systems show higher solder crack resistance with higher filler contents. Furthermore, they clear 260°C maximum reflow temperature with the filler content of 90 percent for the resin system with super-low viscosity and with 84 percent for the super-flexible resin system (Figs. 6.11 and 6.12).

6.3 ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR PBGA PACKAGES One of critical differences between the PQFP and the PBGA packages is that PQFP uses a leadframe and PBGA uses an organic [usually bismaleimide triazine (BT)] substrate.11 Also, unlike PQFP, PBGA only molds the upper portion of the package. In this section, novel halogen-free molding compounds developed by Nitto Denko are presented. These compounds pass the flammability test and allow minimum PBGA package warpages.

TABLE 6.9 Contents and Properties of New Resin System for Environmentally Friendly Molding Compounds EMC-6 Current

EMC-7 EMC-8 EMC-9 Super Low Viscosity

EMC-10

EMC-11 EMC-12 Super Flexible

Resin system filler content

Unit wt%

CTE 1 (
TMA

10−5/°C

1.4

1.2

0.8

0.7

1.6

1.3

CTE 2 (>Tg)

TMA

10−5/°C

5.9

5.0

3.7

2.9

5.3

4.8

Tg

TMA

°C

150

130

130

130

135

135

135

RT

MPa

168

185

175

184

177

179

185

240°C

MPa

23

9

16

21

15

19

24

RT

MPa

19,900

23,700

24,500

28,800

18,200

23,400

22,800

240°C

MPa

740

420

920

1,210

410

620

1,000

SiN

MPa

5.7

3.8

5.6

6.8

6.5

7.0

Alloy 42

MPa

1.7

1.1

1.2

1.1

1.3

1.4

1.1

Cu

MPa

1.1

3.4

3.4

3.0

1.2

1.8

2.4

Item Spiral flow

6.11

Flexural strength Flexural modulus Adhesion strength at 240°C

cm

80

84

88

90

80

84

88

85

>260

180

114

180

107

82 0.9 3.4

6.5

Ag plating

MPa

0.4

0.8

0.9

1.0

0.5

0.6

0.7

Water absorption

Boil 24 h

wt%

0.28

0.25

0.22

0.19

0.21

0.18

0.15

Flammability test

UL-94

—

Fail

Fail

Fail

V-0

V-0

V-0

V-0

6.12

CHAPTER SIX

FIGURE 6.11 Crack test results for the 90-pin PQFP after 260°C reflow.

6.3.1

HALOGEN-FREE FLAME-RETARDANT AGENTS

Nitto Denko17 selected hydroxides as their halogen-free flame-retardant agents. The materials studied are aluminum hydroxide, magnesium hydroxide, and transition metal magnesium hydroxide complex (TMMHC). Their general material properties are shown in Table 6.10. The scanning electron microscopy images of Magnesium

FIGURE 6.12 Crack test results for the 208-pin PQFP after 260°C reflow.

ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR IC PACKAGES

6.13

TABLE 6.10 General Properties of Hydroxide Flame Retardants Mean of particle size (µm)

Decomposition temperature (°C)

DTG peak temperature (°C)

Weight loss (wt%)

Aluminum hydroxide

15

230

300

34.6

Magnesium hydroxide

0.7

350

420

30.9

3

300–350

420

25–30

TMMHC

Hydroxide and TMMHC are shown in Fig. 6.13(a) and (b), respectively. It can be seen that the particle size of TMMHC is much larger than that of magnesium hydroxide. The thermal properties and the particle sizes of these agents were measured by thermogravity analysis (TGA)/dynamic thermoanalysis and a laser particle distribution analyzer, respectively.The compound flow viscosity was measured by a flow tester as a parameter to evaluate the potential damage due to narrow pad pitch and long internal wires. The flammability performance was measured based on the UL-94 test and the passing level is V-0, and the dimensions of the samples were 127 × 12.7 × 1/16 mm. Figure 6.14 shows the position for measuring PBGA package warpage and the dimensions of key elements (such as the chip, BT substrate, and molding compound) of the PBGA package. The package warpage was measured by the Micro Depth Meter from the top surface of the package in the diagonal direction. Figures 6.15, 6.16, and 6.17 show, respectively, the TGA characteristics of magnesium hydroxide, aluminum hydroxide, and non-flame-retardant material. It can be seen that (1) magnesium hydroxide, which has a higher reaction temperature, is more effective than aluminum hydroxide; and (2) the heat decomposition of the

FIGURE 6.13 Scanning electron microscopy (a) images of magnesium hydroxide (×10,000) and (b) TMMHC (×10,000).

6.14

CHAPTER SIX

FIGURE 6.14 Chip and package dimensions as well as position for measuring package warpage.

molding compound without flame-retardant agent starts from 300°C, and the DTG peak appears at 480°C. To achieve flame-retarding characteristics, the endothermic chemical reaction temperature that generates water must be around the temperature of molding compound heat decomposition. In order to minimize the content of flame-retardant agent, TMMHC is introduced to accelerate the carbonization, which improves flame-retarding performance. The flame-retarding mechanism of TMMHC is shown in Fig. 6.18. It can be seen that the hydroxide complex releases water under endothermic chemical reaction. Also, carbonization of the material is accelerated by the transition metal. These then stop the oxygen supply.

FIGURE 6.15 TGA curves for magnesium hydroxide.

ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR IC PACKAGES

6.15

FIGURE 6.16 TGA curves for aluminum hydroxide.

The flammability test results are summarized in Table 6.11, and the TGA measurement results are shown in Figs. 6.19 and 6.20 for molding compounds containing magnesium hydroxide and TMMHC, respectively. It can be seen that the DTG peak without flame-retardant agent is around 480°C (Fig. 6.17). The compound containing magnesium hydroxide shows a DTG peak at 350°C and the shoulder is observed

FIGURE 6.17 TGA curves for non-flame-retardant material.

6.16

CHAPTER SIX

FIGURE 6.18 Flame-retarding mechanism of TMMHC.

from 400 to 470°C. On the other hand, the compound with the TMMHC shows a DTG peak at 350°C without a shoulder. This means that the TMMHC is most effectively working at a compound heat decomposition temperature and keeping temperatures lower.

6.3.2 PBGA PACKAGE WARPAGE CONTROLLED BY Tg DISPERSION For conventional flame-retardant systems such as brominated epoxy and antimony trioxide, the relationship between the package warpage and the total shrinkage of molding compound (at room temperature) is linear, as shown in Fig. 6.21. The total shrinkage is defined as the sum of (1) curing shrinkage during molding and postmold curing; and (2) thermal shrinkage during cooling from curing temperature of the molding compound to room temperature. The extrapolation point, where the zero warpage is given, is defined as the total shrinkage of molding compound equal to 0.2 percent. (The value of 0.2 percent is equal to thermal shrinkage of BT substrate from 175 to 25°C.) In order to minimize the total shrinkage with the purpose of minimizing roomtemperature warpage, most of the conventional PBGA compounds have a very high filler content (over 90 wt%). These molding compounds have the advantage of improving flame retardancy due to the very low organic material content. However,

TABLE 6.11 Flammability Test Results Flame retardant

Magnesium hydroxide

Content (%)

20

TMMHC 20

V-0 level

No pass

Pass

ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR IC PACKAGES

6.17

FIGURE 6.19 TGA curve of compound containing magnesium hydroxide.

without flame-retardant agents, even with 92 wt% filler content, the molding compound cannot pass the UL-94 V-0 test.17 Other methods of minimizing molding compound total shrinkage include selection of a compound with a high glass transition temperature Tg and small thermal shrinkage (a stress-reducing agent such as silicone modifier is sometimes introduced into the molding compound to reduce the shrinkage); (2) selection of a low-Tg material with low viscosity characteristics (higher filler contents); and (3) controlling the modulus change around the Tg of molding compound (the concept of Tg dispersion). Their effects on PBGA package warpage from room temperature to 200°C are shown in Figs. 6.22 and 6.23. It can be seen that molding compounds with Tg dispersion lead to the smallest PBGA package warpage, because the drastic change of modulus of molding compound around Tg has a great impact on the package warpage.

FIGURE 6.20 TGA curve of compound containing TMMHC.

FIGURE 6.21 Effect of total shrinkage of molding compound on package warpage.

FIGURE 6.22 Effect of temperature as well as high-Tg and low-Tg compounds on package warpage.

6.18

ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR IC PACKAGES

6.19

FIGURE 6.23 Effect of Tg-dispersed compound on package warpage.

Also, it can be seen from Fig. 6.22 that, for PBGA packages, the conventional design concepts of high-Tg and low-Tg compounds are not the perfect solutions to control package warpage. This is because of the modulus difference between the molding compound and the BT substrate. The modulus of the molding compound is on the same order as that of the BT substrate when it is below the Tg of the molding compound. However, the modulus of the molding compound is one or two orders of magnitude lower than that of the BT substrate when it is above the Tg. This drastic change of modulus of the molding compound around the Tg is the driving force for PBGA package warpage and should be controlled. The effect of viscosity (filler contents) on PBGA package warpage at room temperature is shown in Fig. 6.24. It can be seen that as the filler content increases (viscosity increases), the PBGA package warpage decreases.

6.3.3 PBGA PACKAGE WARPAGE CONTROLLED BY STRESS-ABSORBING AGENTS The effects of introducing a stress-absorbing agent on the PBGA package warpage from room temperature to 200°C are shown in Fig. 6.25. (During the cooling process, stress absorption is generated in the molding compound.) It can be seen that the molding compounds with both Tg dispersion and stress-absorbing agent yield significant improvements in controlling the PBGA package warpage. By applying the stress-absorbing agent, a smaller package warpage with the same viscosity and the same package warpage with a lower viscosity can be achieved, as shown in Fig. 6.26.

6.20

CHAPTER SIX

FIGURE 6.24 Effect of viscosity (filler content) of Tg-dispersed compound on package warpage.

FIGURE 6.25 Effect of Tg-dispersed and stress-absorption compound on package warpage.

ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR IC PACKAGES

6.21

FIGURE 6.26 Effect of viscosity (filler content) of Tg-dispersed with stress-absorption compound on package warpage.

The choice of Nitto Denko for their new TMMHC flame-retardant PBGA molding compound system is shown in Fig. 6.27.They apply a halogen-free flame-retardant agent (15 wt%) into the PBGA molding compound which is designed by Tg dispersion and the introduction of stress-absorbing agent. It passed the UL-94 V-0 test and yields reasonable package warpage.

FIGURE 6.27 Nitto Denko’s new TMMHC flame-retardant system PBGA compound.

6.22

CHAPTER SIX

6.4 ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR MAP-PBGA PACKAGES Recently, the low-cost, minimum-space, and high-speed MAP-PBGA packages have begun to play a very important role in mobile phones, notebook personal computers, personal digital assistants, and other wireless products and systems. Among all the MAP-type PBGA packages, Amkor’s ChipArrayBGA (CABGA) is the most popular due to its cost, package size, and design, which provide ideal radio frequency operation (low inductance) for high-speed applications. Since the CABGA package is singulated after overmolding the whole matrix, warpage of the matrix is very severe and has to be well controlled (<6 mil) at the cross-sectional direction of the 55.4 × 54-mm mold window size. Also, since the CABGA is near to the chip-scale package, moisture sensitivity level (MSL) of JEDEC Level 3, 30°C/60% RH/192 h at a maximum reflow temperature of 260°C, is required for lead-free soldering. An environmental friendly molding compound, which does not contain flame retardants with Br/Sb and which fits into the lead-free process, has been developed by Amkor and Kumgang Korea Chemical for the CABGA package with an excellent warpage performance and high reliability.18 Their results are presented in the next section.

6.4.1

HALOGEN-FREE FLAME-RETARDANT RESINS

Four kinds of epoxy resins (biphenyl, naphthol, multifunctional, and orthocresol novolac type) and the novolac hardener as shown in Fig. 6.28 have been applied to molding compound for the CABGA packages. The formulation and the matrix resin systems of molding compounds are shown in Tables 6.12 and 6.13, respectively. It can be seen that all molding compounds under consideration do not contain bromine (Br) or antimony (Sb) components as the flame retardant. Instead, the modified phosphorus compound is used as the flame retardant. All raw materials are meltmixed in a twin-screw kneader at 115 to 120°C. The mixed compound is cooled and crushed into powder, which is pressed to form a pellet. Basic properties of molding compounds such as spiral flow, gelation time, and minimum viscosity are measured at 175°C and their results are summarized in Table 6.14. It can be seen that the highest gelation time and lowest viscosity are observed in sample A due to the nature of its biphenyl-type epoxy, which has the lowest viscosity of resin and lowest reactivity.

6.4.2

SAMPLE PREPARATION

Specimens for measurement of thermal properties such as Tg, coefficient of thermal expansion (CTE), and shrinkage were prepared by transfer molding at 175°C and postmold curing for 6 h at 175°C. Tg and CTE were measured by thermo-mechanical analyzer (TMA). The thermal (Tg, CTE, and shrinkage) and mechanical (flexural strength and modulus) test results of molding compounds are summarized in Table 6.15. The moisture absorption was measured after soaking specimens at 85°C/85% RH for 48 h. Total shrinkage of cured compounds was calculated by 100(%)(R1 − R2)/R1, where R1 is the inside diameter of the mold die at 175°C (disk type) and R2 is the out-

ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR IC PACKAGES

6.23

FIGURE 6.28 Chemical structure of epoxy and hardener for environmentally friendly molding compound.

side diameter of the molded specimen at 25°C. Mechanical properties such as flexural strength and modulus were measured by a three-point bending test based on ASTM D-790. Flammability of cured compounds (1-mm thickness) was tested by the UL-94 method. In order to evaluate their moldability properties such as void, coplanarity, and wire sweep, epoxy-type samples A, B, C, and D were assembled on Amkor’s

6.24

CHAPTER SIX

TABLE 6.12 Formulation of New Molding Compound Raw materials

Parts by weight

Epoxy

100

Hardener

See Fig. 6.28

Accelerator

Phosphonium salt

Filler

Fused silica

52–62* 4 1145

Flame retardant

Modified phosphorus compound

0.7

Coupling agent

γ-glycidoxypropyl trimethoxysilane

6

Releasing agent

Carnauba wax

2.5

Colorant

Carbon black

2.5

* Hardener content is controlled to be the equivalent of epoxy and phenol functionality (E/P = 1).

TABLE 6.13 Matrix Resin Systems to Be Considered System

Epoxy (ratio)

Hardener (ratio)

A

E4 (100)

H1 (100)

B

E4 (20)/E1 (80)

H1 (100)

C

E4 (20)/E2 (80)

H1 (100)

D

E4 (20)/E3 (80)

H1 (100)

TABLE 6.14 Basic Properties of Molding Compounds Unit

A

B

C

D

Spiral flow

Item

in

67

45

39

30

Gelation time

s

26

22

22

21

Minimum viscosity

P

49

98

120

160

CABGA assembly line. Figure 6.29(a) and (b) shows the top and bottom views, respectively, of the molded CABGA packages before singulation. It can be seen that each strip is partitioned into four molded parts. Each mold window size is 55.4 × 54 mm. After singulation, nine singulated CABGA packages 13 × 13 mm in size and having 144 pins were obtained from each molded part. The die size was 200 × 203 × 11.5 mil, the gold wire was 1 mil in diameter, and the maximum wire length was 69 mil. The average values of coplanarity and wire sweep data from Amkor’s assembly line are shown in Table 6.16.

ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR IC PACKAGES

6.25

TABLE 6.15 Physical and Mechanical Properties of Molding Compounds Item

Unit

A

B

Tg

°C

141

171

203

C

165

D

CTE1

ppm/°C

9.1

11.4

11.5

10.3

CTE2

ppm/°C

33.4

33.9

31.4

31.1

Shrinkage

%

0.333

0.288

0.272

0.272

Moisture absorption

%

0.143

0.132

0.217

0.155

Flexural strength

25°C, kg/mm2

16.8

16.4

14.3

15.0

240°C, Flexural modulus

kg/mm2

1.9

1.3

1.9

1.5

25°C, kg/mm2

2641

2845

2623

2695

240°C, Flammability

kg/mm2

223

175

348

274

—

V-0

V-0

V-0

V-0

6.4.3 EFFECTS OF Tg, SHRINKAGE, AND VISCOSITY ON PACKAGE COPLANARITY The effects of molding compound properties such as Tg and shrinkage on the coplanarity are shown in Fig. 6.30. It can be seen that the higher the Tg, the lower the coplanarity. However, the higher the total shrinkage of the compound, the higher

FIGURE 6.29 Amkor’s CABGA, (a) top view and (b) bottom view (before singulation).

6.26

CHAPTER SIX

TABLE 6.16 Moldability Test Results for Molding Compounds Item

Unit

A

B

C

D

Coplanarity

mil

4.02

3.14

2.40

2.89

Wire sweep

%

3.78

3.89

5.21

7.15

the coplanarity. The total shrinkage is composed of thermal shrinkage in the range from room temperature to molding temperature and cure shrinkage at molding temperature. Dimensional change of cured compound from 25 to 175°C is measured by TMA and is used for thermal shrinkage calculation. Cure shrinkage is the difference between the total shrinkage and the thermal shrinkage. The thermal shrinkage and cure shrinkage of all samples are plotted as a function of coplanarity in Fig. 6.31. It can be seen that the coplanarity is linearly related to thermal shrinkage and proportional to the difference of the total shrinkage between the substrate and the molding compound. Thus, when the difference of shrinkage between the substrate and molding compound is minimized, the warpage or coplanarity of the package is minimized. The relationship between the wire sweep of a package and the viscosity of a molding compound is well-known, and it is widely recognized that wire sweep decreases with decreasing viscosity of molding compound.18 The same tendency is also observed for halogen-free molding compound as shown in Fig. 6.32. It can be seen that the wire sweep of CABGA package decreases as the molding compound viscosity decreases.

FIGURE 6.30 Relationship between Tg, shrinkage, and coplanarity.

ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR IC PACKAGES

6.27

FIGURE 6.31 Relationship between coplanarity and thermal and cure shrinkage. Dotted line represents the thermal shrinkage of PCB substrate.

6.4.4

MOISTURE SENSITIVITY TESTS

Results of MSL tests are shown in Table 6.17. It can be seen that all the samples are subjected to the JEDEC Level 3 condition (30°C/60% RH/192 h) with a maximum reflow temperature of 260°C, and the JEDEC Level 2 condition (85°C/60% RH/168 h) at a maximum reflow temperature of 240°C. Also, it can be seen that all the samples passed the test except sample C.

FIGURE 6.32 Effect of spiral flow and viscosity on wire sweep.

6.28

CHAPTER SIX

TABLE 6.17 Reliability Test Results for Molding Compounds

JEDEC level

Maximum reflow temperature

A

B

C

D

3

260°C

Pass

Pass

Fail

Pass

2

240°C

Pass

Pass

Fail

Pass

Under Level 3 conditions, there are external package cracks for all the tested units (n = 22) of sample C.These cracks propagate to the top of the package after the occurrence of the die-top delamination, which is scanned by scanning acoustic microscopy. The typical external crack and delamination are shown in Fig. 6.33. Under Level 2 conditions, the external package crack followed by the die-top delamination are observed in 15 units of sample C. The failure mode is very similar to that under JEDEC Level 3 conditions. There are many material properties of molding compounds, such as moisture absorption, adhesion strength, flexural strength and modulus, and fracture toughness, that affect the package reliability. Among them, total amount of moisture absorbed can be the most important factor in MSL performance at higher reflow temperature (260°C). Hence the worst MSL performance observed in sample C is assumed to be due to the highest amount of moisture absorbed as shown in Table 6.15

FIGURE 6.33 Photos of (a) delamination and (b) external cracking.

ENVIRONMENTALLY BENIGN MOLDING COMPOUNDS FOR IC PACKAGES

6.29

ACKNOWLEDGMENTS The authors would like to thank S. Iwasaki, S. Ueda, T. Yagisawa, and H. Suzuki of Sumitomo; M. Yamaguchi, H. Shigyo, Y. Yamamoto, S. Sudo, and S. Ito of Nitto Denko; B. Kong, H. Yun, and J. Lim of Kumgang Korea Chemical; and Y. Jung, D. Kim, and K. Chung of Amkor for sharing their useful and important knowledge with the industry.

REFERENCES 1. Bergendahl, C. G., et al., “Alternatives to Halogenated Flame Retardants in Electronic and Electrical Products: Results from a Conceptual Study,” IVF Research Publication 99824, 1999. 2. Bergendahl, C. G., “Electronics Goes Halogen-Free: International Driving Forces and the Availability and Potential of Halogen-Free Alternatives,” Proceedings of IEEE International Symposium on Electronics and the Environment, pp. 54–58, 2000. 3. Hardy, M. L., “Toxicology of Commercial PBDPOs and TBBPA,” IPC Printed Circuits Expo, April 5, 2000. 4. Hedemalm, P., et al., “Brominated Flame Retardants—An Overview of Toxicology and Industrial Aspects,” Proceedings of IEEE International Symposium on Electronics and the Environment, pp. 203–208, 2000. 5. Hedemalm, P., et al., “Brominated and Phosphorus Flame Retardants—A Comparison of Health and Environmental Effects,” Proceedings of Electronics Goes Green 2000, pp. 115–120, Berlin, Germany, 2000. 6. Hoffmann, M., et al., “Product Design Methodology,” Proceedings of Electronics Goes Green 2000, pp. 217–222, Berlin, Germany, 2000. 7. Iji, M., et al., “New Environmentally Conscious Flame-Retarding Plastics for Electronic Products,” Proceedings of EcoDesign ’99, pp. 245–249, 1999. 8. Segerberg, T., et al., “Toxicological Aspects of Halogen Free Flame Retardants Based on Denitrification Inhibition Tests,” Proceedings of IEEE International Symposium on Electronics and the Environment, pp. 69–74, 2000. 9. Lau, J. H., Lost Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, McGraw-Hill, New York, 2000. 10. Lau, J. H., C. P. Wong, J. Prince, and M. Nakayama, Electronic Packaging: Design, Materials, Process, and Reliability, McGraw-Hill, New York, 1998. 11. Lau, J. H., Ball Grid Array Technology, McGraw-Hill, New York, 1995. 12. Lau, J. H., Thermal Stress and Strain in Microelectronics Packaging, Van Norstrand Reinhold, New York, 1993. 13. Yagisawa, T., and H. Suzuki, “Development of the Environmentally Friendly Epoxy Molding Compound,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 1737–1746, May 2000. 14. Iwasaki, S., and S. Ueda, “Development of Molding Compound for Non-Antimony and Non-Halogen,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 1283–1288, May 1997. 15. Mogi, N., and H. Yasuda, “Development of High-Reliability Epoxy Molding Compounds for Surface-Mount Devices,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 1023–1029, May 1992. 16. Fujita, H., and N. Mogi, “High-Reliability Epoxy Compound for Surface Mount Devices,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 735–741, May 1993.

6.30

CHAPTER SIX

17. Yamaguchi, M., H. Shigyo, Y. Yamamoto, S. Sudo, and S. Ito, “Non Halogen/Antimony Flame Retardant System for High End IC Package,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 1248–1253, May 1997. 18. Kong, B., H. Yim, J. Lim, Y. Jung, D. Kim, and K. Chung, “Highly Reliable and Environmentally Friendly Molding Compound for CABGA Packages,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 1393–1397, May 2001. 19. Oota, K., “Development of Molding Compounds for BGA,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 78–85, May 1995. 20. Ko, M., M. Kim, and D. Shin, “Investigation on the Effect of Molding Compounds on Package Delamination,” IEEE Proceedings of Electronic Components and Technology Conference, pp. 1242–1247, May 1997.

CHAPTER 7

ENVIRONMENTALLY BENIGN DIE ATTACH FILMS FOR IC PACKAGING 7.1

INTRODUCTION

As discussed in Chaps. 1 and 6, environmentally benign electronics manufacturing, especially in Japan and the European Union, wants to be lead-free. Today, the most likely solder candidate is the Sn-Ag-Cu family, with a melting point temperature higher than 213°C. Thus, the maximum reflow temperature of the lead-free solder tends to rise from 220 to 260°C or even higher. This trend leads to serious problems on current die attach materials for molded-plastic integrated circuit (IC) packages. In this chapter, a couple of new die attach films developed by Hitachi for a lead-free soldering environment are presented. For photonic and fiber-optic devices and packaging, lead-free solders [e.g., indium (In) and tin-indium (Sn-In)] used as joining materials have become ever more popular due to their ductility. Since flux and high-temperature solder reflow are not compatible with the optoelectronics packages, low-temperature, fluxless bonding techniques are therefore very desirable. In this chapter, the lowtemperature fluxless bonding technique using In-Sn lead-free solder, developed by the University of California-Irvine, is discussed.

7.2

ENVIRONMENTALLY BENIGN DIE ATTACH FILMS

Silver pastes have been widely used for die attach materials for more than 40 years. However, due to lead-free soldering, most of the current silver pastes will crack and delaminate the package (as shown in Fig. 7.1) during the higher-temperature reflow profile.1–9 As discussed in Chap. 6, the popcorn phenomenon has been under control through various formulation changes in epoxy molding compounds to reduce the amount of moisture absorption. However, die attach materials for lead-free soldering are still under development. Hitachi’s die attach films (DF-335-7 and DF-400)5 for lead-free soldering are discussed in the following two sections.

7.2.1 SILVER-FILLED FILM DF-335-7 FOR LEADFRAME PQFP PACKAGES Die attach materials for leadframe types of plastic quad flat pack (PQFP) packages usually consist of a polyimide-base resin, a thermosetting adhesive resin, and a silver filler. These materials should be low in cost and low in moisture absorption, as well as high in peeling strength for package reliability.

7.1 Copyright © 2003 by The McGraw-Hill Companies, Inc. Click here for terms of use.

7.2

CHAPTER SEVEN

FIGURE 7.1 Plastic package cracking mechanism during solder reflow.

Usually, polyimides absorb 1.3 wt % of moisture (type A), as shown in Table 7.1. To reduce its moisture absorption, hydrophobic chemical structures are introduced into the polymer backbone (types B and C). It can be seen that because of its hydrophobic structure, the new polyimide type C shows significant low moisture absorption (0.2 wt %). Therefore, it is chosen for a base resin of Hitachi’s new die attach film DF-355-7.5–7 The effect of thermosetting resin contents on the peeling strength at 275°C is shown in Fig. 7.2. It can be seen that one unit of the thermosetting resin content TABLE 7.1 Water Absorption of Polyimides

Polyimide

Water absorption* (wt%)

A

1.3

B

0.7

C

0.2

* Immersed for 24 h at room temperature (Ion exchange water).

ENVIRONMENTALLY BENIGN DIE ATTACH FILMS FOR IC PACKAGING

7.3

FIGURE 7.2 Effect of the thermosetting resin content on peeling strength at 275°C.

leads to the maximum peeling strength, and cohesive failure is the fracture mode. For other thermosetting resin contents, interface failure is the peeling fracture mode. The effects of thermosetting resin content on the modulus of the die attach film and adhesion are shown in Fig. 7.3. The modulus is measured by dynamic mechanical analysis. Adhesion is calculated by the surface energies of a silicon chip, a lead-

FIGURE 7.3 Effect of the thermosetting resin content and adhesion’s work and modulus at 275°C.

7.4

CHAPTER SEVEN

frame, and the die attach film, which are measured by the contact angles of their respective surfaces. Note that the modulus of the die attach film reaches the maximum value with one unit of thermosetting resin content. Also, adhesion’s work in both the silicon chip–film and leadframe-film interfaces decreases with increasing thermosetting resin contents. The effect of the die attach film’s silver filler content on the peeling strength at 275°C is shown in Fig. 7.4. Note that the maximum peeling strength occurs at 40 wt % silver filler content, and that cohesive failure is the fracture mode. For other silver filler contents (e.g., 20, 60, and 80 wt %), interface failure is the fracture mode (either silicon chip–film or leadframe-film interfaces).

FIGURE 7.4 Effect of silver filler content on peeling strength at 275°C.

The effects of moisture absorption of both the die attach film and of adhesion’s work are shown in Fig. 7.5. It can be seen that the moisture absorption decreases with increasing silver filler content because silver fillers do not absorb moisture at all. However, adhesion’s work at the silicon chip–film and leadframe-film interfaces decreases with increasing silver filler contents. Figure 7.6 shows the relationship between peeling strength, moisture absorption, and package cracking resistance, as well as high-reliability (hatched) areas. High peeling strength and low moisture absorption are necessary to achieve Joint Electronic Device Engineering Council (JEDEC) Level 1 test conditions. Through all of the preceding investigations, a new die attach film DF-335-7 has been developed by Hitachi,5–7 and its material properties are shown in Table 7.2. Note that DF-335-7 consists of a modified polyimide-base resin having hydrophobic structure, a thermosetting resin of optimum content, and a silver filler of 40 wt %.

ENVIRONMENTALLY BENIGN DIE ATTACH FILMS FOR IC PACKAGING

FIGURE 7.5 Effect of silver filler content on adhesion’s work and water absorption.

FIGURE 7.6 Effect of water absorption on peeling strength and package cracking resistance.

7.5

7.6

CHAPTER SEVEN

TABLE 7.2 Characteristics of Hitachi’s DF-335-7 and Conventional Silver Paste

Item Composition Base resin

Silver filler content Die attach condition Temperature Pressure Time Cure Package crack resistance (85°C/85% RH) 245°C 265°C 275°C Water absorption Peeling strength 245°C 265°C 275°C

Silver paste

Test condition

Unit

DF-335-7

—

Epoxy resin

—

wt %

Modified polyimide+ thermosetting resin 40

70

—

°C N/chip s °C-min

230 0.5 1.0 180-30

— 1.0 <1 180-60

— — — — QFP: 14 × 20 × 1.4 mm Chip size: 8 × 10 mm Leadframe: Cu EMC: CEL-9200

— — —

504 h OK 168 h OK 168 h OK

24 h OK 24 h NG 24 h NG

vol %

0.2

1.2

RT for 24 h

×105 Pa ×105 Pa ×105 Pa

8.1 8.1 8.3

1.0 1.0 0.8

Chip size: 5 × 5 mm Leadframe: Cu

The moisture absorption of DF-335-7 is only one-sixth that of a currently used silver paste (Table 7.2). The peeling strength of DF-335-7 is eight times larger than that of the paste. To evaluate the package cracking resistance of DF-335-7, the 14- × 20- × 1.4-mm low-profile quad flat pack (LQFP) pack is used. The LQFP consists of a silicon chip (8 × 10 × 0.3 mm), a die attach film DF-335-7 (30 µm thick), a copper leadframe with a flat die stage, and an epoxy molding compound (CEL-9200 by Hitachi). The package is exposed to moisture conditioning at 85°C/85% RH for 24 to 504 h and then is tested at high temperature (265 to 275°C) during reflow soldering. No package cracking is observed in packages using the DF-335-7 after these tests. Consequently, DF-335-7 indicates excellent package cracking resistance at high reflow temperatures (265 to 275°C) since its low-moisture-absoprtion and high-peeling-strength characteristics prevent the popcorn phenomenon.

7.2.2 INSULATING FILM DF-400 FOR BT-SUBSTRATE PBGA CSP PACKAGES The requirements of die attach materials for bismaleimide triazine– (BT-) substrate types of plastic ball grid array (PBGA) and chip-scale packages (CSPs) are higher than for those of leadframe types of PQFP packages.Thus, in addition to lower mois-

ENVIRONMENTALLY BENIGN DIE ATTACH FILMS FOR IC PACKAGING

7.7

ture absorption and higher peeling strength, lower stress (which leads to less chip and substrate warpage) and lower glass transition temperature (Tg) (which leads to lower chip attachment temperature) are needed. The effects of modulus of die attach film and Tg on chip warpage are shown in Figs. 7.7 and 7.8. The chip warpage is measured using a surface roughness meter with a scan distance of 11 mm. The test is performed on a silicon chip (5 × 13 × 0.4 mm), which is attached onto a copper leadframe (0.26 mm thick) using a die attach film (5 × 13 × 0.03 mm) at 230°C. The correlation coefficient between the chip warpage and the film’s modulus is 0.466, whereas that value between the chip warpage and Tg of base resins is 0.969. Figures 7.7 and 7.8 show that the influence of Tg on chip warpage is more remarkable than that of the film’s modulus. The chip warpage decreases considerably with decreasing Tg of a base resin.That is to say, decreasing Tg could effectively lower the stress in the chip, molding compound, and the substrate. The effects of die attach temperatures and Tg on the peeling strength of the die attach materials are shown in Fig. 7.9. In the case of a film using a polyimide with a relatively high Tg (120°C), the peeling strength decreases below 220°C of the die attach temperature. However, the peeling strength of a film using a polyimide with a low Tg (57°C) only decreases slightly, even at 180°C. From the results, it is clear that the low-Tg base resin leads to a lower die attach temperature. Through all of the preceding investigations, a new die attach film DF-400 has been developed by Hitachi5–7 for the BT-types of CSP and PBGA packages, and its material properties are shown in Table 7.3. DF-400 consists of a modified polyimidebase resin with a low Tg, a thermosetting resin of optimum content, and an insulating filler. With these elements, DF-400 yields a relatively low attach temperature, low stress, and low chip warpage. Figure 7.10 shows a dynamic mechanical analysis of DF-400. Note that as Tg of the base resin is relatively low (57°C), DF-400 melts and flows at high temperatures before curing. This is one of the reasons for DF-400’s attachment ability at 180°C. The storage modulus of DF-400 in the rubber region at high temperatures (above

FIGURE 7.7 Effect of film’s modulus on chip warpage.

7.8

CHAPTER SEVEN

FIGURE 7.8 Effect of base resin’s Tg on chip warpage.

FIGURE 7.9 Effect of chip attach temperature on peeling strength.

100°C) increases after curing because curing forms a polymer network. This should result in its heat resistance and its good reliability. Table 7.3 shows that the peeling strength of DF-400 is 4 to 5 times greater than that of the currently used die attach silver paste in the cases of both a polyimide substrate and a glass-epoxy substrate. The moisture absorption of DF-400 is only onequarter that of the paste.

ENVIRONMENTALLY BENIGN DIE ATTACH FILMS FOR IC PACKAGING

7.9

TABLE 7.3 Characteristics of DF-400 and Conventional Insulating Paste Insulating paste

Test condition

Low-Tg modified polyimide+ thermosetting resin

Epoxy resin

—

µm

20.0

40

°C N/chip s

180.0 1.0 1.0

— 1.0 <1.0

×105 Pa

2.35

0.46

Glass epoxy substrate

×105 Pa

7.20

1.95

Water absorption

vol %

0.2

0.85

RT for 24 h

OK/NG

OK

NG

OK/NG

OK

—

Package size: 18 × 18 × 0.8 mm without solder resist Package size: 8 × 11 × 1.4 mm without solder resist

Item

Unit

DF-400

Base resin

—

Warpage of silicon chip Die bonding condition Temperature Pressure Time Peeling strength (250°C) Polyimide substrate

Package cracking resistance (85°C/60% RH, 168 h) F-BGA

Stacked CSP

Chip size: 5 × 13 mm Substrate: Cu

— — —

Chip size: 5 × 5 mm without solder resist Chip size: 5 × 5 mm with solder resist

To evaluate DF-400’s package cracking resistance, the fine-pitch ball grid array (F-BGA) and stacked CSP are used. The F-BGA (18 × 18 × 0.8 mm) consists of a silicon chip, a DF-400 film (40 µm), a polyimide substrate having one electrical layer without a solder resist, and an epoxy molding compound. The stacked CSP (8 × 11 × 1.4 mm) consist of two silicon chips, two DF-400 films (25 µm), a polyimide substrate having one electrical layer without a solder resist, and an epoxy molding compound. These packages are exposed to moisture conditioning at 85°C/60% RH for 168 h and then are tested at 245°C during reflow soldering. No package cracking is observed in either package using DF-400 after the tests. Consequently, DF-400 is qualified for BT types of CSP and PBGA packages.

7.10

CHAPTER SEVEN

FIGURE 7.10 Effect of temperature on the storage modulus.

7.3 ENVIRONMENTALLY BENIGN In-Sn DIE ATTACH BONDING TECHNIQUE Indium has been used as a joining material for photonic devices, and has a relatively low melting temperature of 156°C, which means that subsequent bonding operations need a process with a bonding temperature that is lower than 156°C. Thus, the desirable bonding temperature should be lower than 156°C but higher than the maximum temperature of the solder during device operation. An In-Sn binary system with a eutectic temperature of 118°C is often chosen for this purpose.10–15 As a result of the low solidifying temperature, stresses in the bonded structure due to thermal expansion mismatch are also reduced. It is known that the minimal stress or stress-free point in a conventional soldering process is at the temperature where the solder solidifies. The chip, solder, and substrate contract at different rates during the cooldown process, and thus incur stresses that remain locked in the joint interfaces. If the residual stresses are high, it can cause chip cracking and decrease solder fatigue. Thus, a lower-temperature bonding process can reduce the residual stresses that are generated during chip attachment. In conventional soldering processes, oxidation of the solder produces a solid oxide film on the surface of the molten solder. The solid oxide film has a very high melting temperature and becomes a barrier that prevents molten solder from having contact with the parts to be joined. The base metal also gets oxidized easily and the oxide needs to be removed. As a result, the necessary chemical bonds between the solder and the parts cannot be formed unless the oxide is broken up or removed. The most common method of removing the solder and base metal oxide is to apply acid rosin flux, which reduces the oxide and protects the solder and base metal against further oxidation. In applications where flux cannot be used (e.g., photonic and fiber-optic devices), a fluxless process is required.

ENVIRONMENTALLY BENIGN DIE ATTACH FILMS FOR IC PACKAGING

7.11

A new composite solder made of ternary Au-In-Sn alloy has been developed by Lee et al.10–15 This multilayer composite solder achieves a process temperature of 140°C. Also, a fluxless, oxidation-free bonding technique that prohibits the initial oxidation of solder is reported by Lee et al.10–15 Their results will be reported in this section.

7.3.1

In-Sn PHASE DIAGRAM

To explain the fluxless bonding principle, it is important to briefly review the In-Sn phase diagram as displayed in Fig. 7.11.16 The most important application feature is the 118°C eutectic point at composition of 51.7 at % In and 48.3 at % Sn. The equilibrium phases are terminal In and Sn solid solutions, two intermediate phases β and γ, and the eutectic between the two phases. There are no known intermetallic compounds that form in this system. The terminal In solid solution can contain as much as 12 wt % Sn at room temperature and 11 wt % at 143°C. The two Sn terminal solid solutions, metallic β-Sn and semiconducting α-Sn, can contain up to 7 wt % In. The transition between the two solid solutions occurs at 13°C, which is below the room temperature. The solid solution β-Sn exists all the way up to 224°C near the peritectic formation of γ at 224°C. A eutectic composition of 51.7 at % In and 48.3 at % Sn is a mixture of two phases at room temperature, namely the In-rich β phase and the Sn-rich γ phase. The range of composition of the β phase changes significantly with increasing temperature. At room temperature the extent of Sn content in the β phase ranges from 15 to

FIGURE 7.11 In-Sn phase diagram.

7.12

CHAPTER SEVEN

28 at % only, while at high temperatures near the solidus curve it broadens to between 12 and 44 at % Sn. As the eutectic In-Sn is heated up, the amount of the β phase increases and, consequently, the amount of the γ phase decreases. However, the composition of β changes and becomes less In-rich. At the eutectic temperature of 118°C, the mixture would completely melt and form a liquid phase. A composition that is slightly more In-rich compared with the eutectic composition would result in a mixture of the liquid phase with imbedded solid β grains at 118°C, and the mixture would completely melt at the liquidus temperature that is slightly higher than the eutectic melting point. Similarly, an alloy that is Sn-rich in composition would be a mixture of liquid with imbedded γ grains until it reaches the liquidus temperature, which is significantly higher.

7.3.2

DESIGN AND PROCESS OF In-Sn SOLDER JOINTS

The In-Sn multilayer composite design from UC-Irvine is shown in Fig. 7.12a. Thin layers of Cr and Au are deposited on silicon substrate using E-beam evaporation in a high-vacuum system. On a separate piece of silicon wafer, Cr, Sn, In, and Au layers are deposited sequentially using a high-vacuum thermal evaporator in one vacuum cycle. The initial Cr layer enhances the multilayer adhesion to the silicon wafer. The outer Au deposition leads to the immediate formation of AuIn2 intermetallic compound, which conveniently serves as a protective outer layer against inner In oxidation. AuIn2 initially forms at the In-Au interface almost immediately upon deposition, and continues to form along its grain boundaries. The Au-In phase diagram clearly shows the AuIn2 compound phase.17 It has a diffusion coefficient of 6.05 × 10−4 m2/s and activation energy of 0.97 e V.18 AuIn2 is thus a very stable compound and is known to remain unchanged even after many months at room temperature.18 Figure 7.12b shows the final multilayer composite after metallization and In-Au interaction. During deposition, film thickness is monitored. On the substrate, 0.03 mm of Cr and 0.05 mm of Au are deposited. On the die, 0.03 mm of Cr, 2.0 mm of Sn, 2.5 mm of In, and 0.05 mm of Au are deposited. Assuming that the reaction between Au and In is complete, all of the Au is consumed, using up 0.154 mm of the In layer to form AuIn2. Remaining In is available to interact with Sn during bonding. To fabricate the joint, the silicon substrate with Cr-Au metallization is cleaved into square pieces with dimensions of 6 × 6 mm, and the silicon die with Cr-Sn-In-Au metallization into 4 × 4-mm pieces. The In-Sn joint is achieved by heating up the two pieces held together while applying static pressure of 50 to 85 pounds per square inch (psi).The assembly is placed in a furnace tube, purged with nitrogen, and heated in hydrogen up to 140°C in 15 min and held at 140°C for 5 min. Once the bonding process is complete, the furnace is cooled down to room temperature. Cooling time is approximately 20 min. A total of 54 specimens are bonded and evaluated. The essential mechanism of the joint formation, shown in Fig. 7.13, is elaborated as follows. When the furnace temperature reaches 118°C (the In-Sn eutectic melting temperature), the In would react with the Sn to form a thin liquid phase at the interface. Since a 140°C bonding temperature is lower than either the In melting point (157°C) or the Sn melting point (232°C), it appears that none of the multilayer composite would melt. The fundamental concept is solid-state diffusion below the 118°C eutectic temperature. When the furnace temperature is moving toward 118°C, the In and Sn on the interface interdiffuse in solid state to form a thin solid layer of eutectic alloy. When the temperature reaches 118°C, the solid eutectic layer melts and turns into liquid. As the temperature moves beyond 118°C, the liquid eutectic phase dissolves

ENVIRONMENTALLY BENIGN DIE ATTACH FILMS FOR IC PACKAGING

7.13

(a)

(b)

FIGURE 7.12 (a) In-Sn initial multilayer composite design and (b) In-Sn multilayer composite after AuIn2 formation.

the adjacent In and Sn layers, and eventually turns the In-Sn composite into liquid phase. The molten In-Sn alloy wets and breaks up the thin AuIn2 layer to form a mixture of liquid with imbedded solid grains of AuIn2.The melting temperature of AuIn2 is 540.7°C, so it remains in the form of small solid grains during the entire bonding process. The mixture then comes in contact with the Au layer on the substrate and forms additional AuIn2. Once the bonding process is complete, the furnace is cooled down to room temperature and the joint solidifies. It should be noted that another new In-Sn bonding design and technique, which leads to a wider process temperature window, has also been developed by Lee et al.10–15 The remelting temperature of the new In-Sn solder joints is in the range from 175 to 200°C.

7.14

CHAPTER SEVEN

(a)

(b)

FIGURE 7.13 Principles of the In-Sn fluxless bonding process. (a) Upon deposition, the AuIn2 layer is formed. (b) At 118°C, an In-Sn eutectic liquid phase is produced.

7.3.3

CHARACTERIZATION OF In-Sn SOLDER JOINTS

Scanning acoustic microscopy (SAM) is used to study the quality of the joints and to detect any voids inside the joint.10–15 For the samples studied, the contrast in acoustic images is caused mostly by the mismatch in acoustic impedance between the joint material and the air, which is the void. A good sample would give a bright picture, whereas a void would appear as a dark spot in the acoustic image. The operating frequency is 140 MHz for this system, and the corresponding spatial resolution at this frequency is approximately 25 µm. Therefore, it is able to detect voids inside the joint that are 25 µm or larger with virtually no sample preparation. The SAM images show that excellent bonding is consistently achieved and that voids rarely occur inside the joint. Figure 7.14 displays a typical SAM image of a good bonding. To examine the thickness uniformity of the joint and to study the microstructure of the joint, several specimens are cut and polished. Cross sections are exam-

ENVIRONMENTALLY BENIGN DIE ATTACH FILMS FOR IC PACKAGING

7.15

(c)

(d)

FIGURE 7.13 (Continued) (c) During the 118- to-140°C range, additional liquid as well as AuIn2 are produced. (d) Solidification of the mixture completes the joint formation.

ined under an optical microscope, a scanning electron microscope (SEM), and an energy dispersion x-ray microanalyzer (EDX) system. Figure 7.15 exhibits an SEM image from the polished joint cross section. The thickness of the joint is found to be very uniform throughout the cross section. The typical thickness is 5 µm. It is somewhat difficult to analyze in detail the bonding mechanism and the resulting microstructure of the joint using only the SEM and the EDX. However, it is observed that the joint is composed of grains that are 2 to 5 µm in diameter and a surrounding matrix. The grains appear brighter than the matrix under the secondary electron detector. The results of the EDX on composition at several key locations are given in Table 7.4. Locations 4 and 5 are from the matrix area, while the other three locations are from different grains. It is evident that there is a sharp difference in the composition of the matrix and the grains. The matrix is mainly composed of Sn, while the visible grains contain a large amount of Au and In and very little Sn. It seems that during

7.16

CHAPTER SEVEN

FIGURE 7.14 SAM image of a perfectly bonded sample.

cooling, the alloy is divided into regions that are Sn-rich and regions that are In-rich. The overall composition of the joint calculated from the original multilayer structure is 54.5 at % In, 42.1 at % Sn, and 3.4 at % Au. It appears that the matrix is composed of AuIn2 grains embedded in a solid solution of In in Sn. The most probable phase for this solid solution is β-Sn, which extends from 0 to 7 wt % of In at room temperature. Regarding the grains inside the joint, the exact compounds and phases that may be present are not as obvious. However, one possible explanation may be a mixture of the Au-In γ phase, which exists in a narrow region around 30 at % In at room temperature, and the intermetallic compound AuIn.18 Small amounts of one or more In-Sn alloy phases may also be present. It is interesting to observe that no AuSn, AuSn2, or AuSn4 grain shown in the Au-Sn phase diagram18 is detected in the joint. Since the Au content in the joint is very small, it is logical to assume that the majority of the joint is made up of the In-Sn matrix rather than the grains. At first, the large amount of Au in the grains shown in the EDX results and the SEM image seem inconsistent with the overall composition of the joint. However, one should keep in mind that the two-dimensional SEM image is misleading in the accurate representation of the volume fractions of the materials in the joint. The actual volume fraction of the grains is much smaller than it appears because the grains are spherical in shape, rather than cylindrical running through the entire joint. Thus the total volume fraction of the grains inside the joint is significantly

ENVIRONMENTALLY BENIGN DIE ATTACH FILMS FOR IC PACKAGING

7.17

FIGURE 7.15 SEM image of the cross section of a sample bonded with the fluxless Sn-In technology developed by UC-Irvine.

smaller than what appears in two-dimensional analysis. With this geometric consideration, the EDX results are quite consistent with the overall composition in the joint. A debonding test is performed on several samples. The overall remelting temperature of the joint is between 125 and 150°C. This indicates that, among the samples tested, the In-Sn composition of the matrix in the joint ranges from near eutectic to Sn-rich. This result actually offers a very important advantage in that it increases the maximum temperature that the device package can withstand after the bonding process.

TABLE 7.4 Composition Determined by EDX at Locations Indicated in Fig. 7.15 Location

In at %

Sn at %

Au at %

1

36.34

1.28

62.38

2

36.26

2.28

62.47

3

34.85

8.00

57.15

4

22.99

66.40

10.61

5

24.17

64.52

11.31

7.18

CHAPTER SEVEN

ACKNOWLEDGMENTS The authors would like to thank S. Takeda and T. Masuko of Hitachi, and C. C. Lee, R. Chuang, S. Choe, and W. So of the University of California-Irvine for sharing their important and useful technologies with the industry.

REFERENCES 1. Lau, J. H., Lost-Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, McGraw-Hill, New York, 2000. 2. Lau, J. H., C. P. Wong, J. Prince, and M. Nakayama, Electronic Packaging: Design, Materials, Process, and Reliability, McGraw-Hill, New York, 1998. 3. Lau, J. H., Ball Grid Array Technology, McGraw-Hill, New York, 1995. 4. Lau, J. H., Thermal Stress and Strain in Microelectronics Packaging, Van Nostrand Reinhold, New York, 1993. 5. Takeda, S., and T. Masuko, “Novel Die Attach Films Having High Reliability Performance for Lead-free Solder and CSP,” IEEE Proceedings of Electronic Components and Technology Conferences, pp. 1616–1622, May 2000. 6. Takeda, S., “A Novel Die Attach Films Having High Reliability Performance,” Proceedings of the 9th Micro Electronic Symposium, Osaka, Japan, pp. 249–252, October 1999. 7. Takeda, S., T. Masuko, Y. Miyaders, M. Yamazaki, and I. Mackawa, “A Novel Die Bonding Adhesive-Silver Filled Film,” IEEE Proceedings of Electronic Components and Technology Conferences, pp. 518–524, May 1997. 8. Harads, M., “X-ray Analysis of the Package Cracking During Reflow Soldering,” IEEE Proceedings of International Reliability Physics Symposium, pp. 182–187, 1992. 9. Lau, J. H., R. Chen, and C. Chang, “Real-Time Popcorn Analysis of Plastic Ball Grid Array Package During Solder Reflow,” IEEE Proceedings of International Electronics Manufacturing Technology Symposium, pp. 455–463, October 1998. 10. Choe, S., W. So, and C. Lee, “Low Temperature Fluxless Bonding Technique Using In-Sn Composite,” IEEE Proceedings of Electronic Components and Technology Conferences, pp. 114–118, May 2000. 11. Chung, R., S. Choe, and C. Lee, “A Fluxless Sn-In Bonding Process Achieving High ReMelting Temperatures,” IEEE Proceedings of Electronic Components and Technology Conferences, pp. 671–674, May 2001. 12. Lee, C., C. Wang, and G. Matijasevic, “A New Bonding Technology Using Gold and Tin Multilayer Composite Structures,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 14, pp. 407–412, June 1991. 13. Lee, C. Wang, and G. Matijasevic, “Advances in Bonding Technology for Electronic Packaging,” ASME Transactions, Journal of Electronic Packaging, 115:201–207, June 1993. 14. Chen, Y., W. So, and C. Lee, “A Fluxless Bonding Technology Using Indium-Silver Multilayer Composites,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 20:46–51, March 1997. 15. Matijasevic, G., and C. Lee, “Void-Free Au-Sn Eutectic Bonding of GaAs Dice and Its Characterization Using Scanning Acoustic Microscopy,” Journal of Electronic Materials, 18:327–337, March 1989. 16. Okamoto, H., and T. Massalki, Binary Alloy Phase Diagram, vol. 3, ASM International, Metals Park, OH, pp. 2295–2296, 1990. 17. Okamoto, H., and T. Massalki, Binary Alloy Phase Diagram, vol. 3, ASM International, Metals Park, OH, pp. 381–383, 1990. 18. Moffat, W., The Handbook of Binary Phase Diagrams, Genium Publishing Corporation, Schenectady, NY, 1995.

CHAPTER 8

ENVIRONMENTAL ISSUES FOR CONVENTIONAL PCBs 8.1

INTRODUCTION

Electronics manufacturing and disposal of electronics products are perturbing the equilibrium of the atmosphere-land-ocean system on earth. While microelectronics improves the global standard of living, its environmental impact poses a major threat to the quality and existence of life on earth. In the past century, the major concern was pollution from the automobile industry, the steel industry, and energy production using coal. The harmful effects of combustion engine emission made the problem even worse. This is further aggravated by the present impact from the electronics manufacturing industry. These cumulative effects have brought the environment to such a level that clean water and air can no longer be guaranteed. Regarding environmental concerns about microelectronics, in addition to the use of lead in solder materials, which has been a well-known issue, the other significant aspect is the use of bromine and antimony-containing flame retardants in printed circuit boards (PCBs) and in area-array package substrates. These flame retardants are based on a combination of bromine and antimony oxide. Halogens, including bromine, are only weak fire retardants, and antimony oxide by itself is not a fire retardant; however, when combined, they become very effective. The combination retards flames in two ways. During burning, antimony oxide promotes the formation of char (essentially, carbon), which reduces the formation of volatile gases. At the same time, the heat of initial combustion promotes a cross-linking between the organic compound and the antimony, which results in a more stable thermoset polymer. In addition, at temperatures above 315°C, bromine forms hydrobromic acid, which reacts with the antimony oxide to form antimony trihalides and oxyhalides that trap free radicals, inhibiting ignition and pyrolysis.1 The objection to bromine-antimony flame retardants is what happens at the end of a product’s life. According to the European Union (EU) directive on Waste Electrical and Electronic Equipment (WEEE), when electronics that are treated with bromine flame retardants are recycled, they can generate dioxins and furans. (Dioxins and furans are based on a common chemical skeleton, onto which one to eight chlorine atoms can be attached in a variety of positions. The different combinations yield 75 distinct dioxins and 135 different furans.) In the mid-1980s, studies showed that toxic polybrominated dibenzofurans (PBDFs) and polybrominated dibenzodioxins (PBDDs) were formed during the extruding process, which is part of the plastic recycling process. There is also evidence that polybrominated diphenyl-ethers (PBDEs) might act as endocrine disrupters, and high concentrations of PBDEs have been found in the blood of workers in recycling plants. Moreover, polybrominated biphenyls (PBBs) have been found in Arctic seal samples, which indicate a wide geographical distribution from both PBB manufacturing and waste dumps. Once PBBs have been released into the environment, they can reach the food chain.

8.1 Copyright © 2003 by The McGraw-Hill Companies, Inc. Click here for terms of use.

8.2

CHAPTER EIGHT

On the packaging side, some qualified suppliers may be able to produce substrates that do not contain halides or antimony, so there is no problem meeting the European Community (EC) requirements. In the larger world of complete systems, it is not so clear whether there are easy substitutes for bromine and antimony.A controversy arises because in the United States, the State Fire Marshals Association has indicated that it will not accept consumer electronics that contain fiberglassreinforced circuit boards not protected with brominated flame retardants. In a recent press release distributed to European publications, the association indicated that it will call for a trade embargo on any consumer electronics manufactured without brominated flame retardants. It remains to be seen how this will be resolved.2

8.2

INFLUENCE OF ELECTRONIC PRODUCTS

Until the early 1980s, electronics manufacturing was still considered a clean process in the public eye. Due to increasing environmental awareness, more detailed investigations on electronics manufacturing have led to a belief that the operation is no longer clean. Figure 8.1 illustrates six aspects of the life cycle of an electronic product, which includes the following:3 ● ●

● ● ● ●

Electrical, mechanical, and chemical design Raw materials, production of integrated circuits (ICs) and passive components, and organic board fabrication, involving a variety of chemicals Packaging of components using a variety of harmful materials Transportation of the end products to the customers Usage and consumption of products Disposal and recycling

From an environmental standpoint, the preceding factors fall into several categories, a detailed discussion of which follows.

8.2.1

MAJOR ENVIRONMENTAL CONCERNS4, 5

8.2.1.1 Global Warming. Global warming is, by far, the most important environmental concern today. Global warming is caused by excessive shielding gases such as CO2, CH4, N2O, and Freon, which mostly come from human activities (e.g., energy generation by burning fossil fuels). These gases act as a barrier to prevent the release of ground heat to the universe, resulting in higher temperatures on earth. In fact, the presence of these gases and the ozone is also required to some extent to shield the harmful radiation from the sun. Otherwise, the atmosphere would provide no insulation to heat radiation in and out of the earth, and the earth would turn into a frigid airless moon.The moon absorbs four times more solar heat than the earth. But its surface is, on the average, 63°F colder than the earth’s due to the absence of atmosphere. According to the Intergovernmental Panel on Climate Change (IPCC) report, the concentration of CO2 in 2100 will be twice that of 1990, as shown in Fig. 8.2. This will cause an increase in temperature by 2°C and a rise in the sea level by 50 cm. It is believed that 1 billion people will be submerged and that there will be a grain and food shortage, as well as abnormal weather, because of the increased carbon dioxide level. To prevent this situation, a treaty for lowering the emission of warming gases was proposed in 1994, as illustrated in Table 8.1.

ENVIRONMENTAL ISSUES FOR CONVENTIONAL PCBs

FIGURE 8.1 Life cycle of electronic products and environmental concerns.

FIGURE 8.2 Production of CO2 in developing and advanced nations.

8.3

8.4

CHAPTER EIGHT

TABLE 8.1 Targeted Reduction of Objectionable Gases (from 2008 to 2012 as a Percentage of 1990 Levels) The objectionable gases (CO2, CH4, N2O, HF, PFC, SF6) United States

7%

Japan

6%

European Union

8%

8.2.1.2 Depletion of Natural Resources. Minerals are precious to human beings living in this highly industrialized society. The minerals are available in limited quantities, which were produced during the earth’s creation over 46 billion years ago. Human beings have continually been consuming minerals, especially since the beginning of the industrial revolution. If the population continues to use them at this pace, most of the minerals will be depleted within the next 100 years, as shown in Table 8.2. 8.2.1.3 Ozone Hole, Acid Rain, and Pollution. Decomposition of Freon gas in the stratosphere generates chlorine atoms. These atoms destroy the ozone layer and result in an ozone hole. In the presence of the ozone hole, ultraviolet rays directly reach the ground, having a negative influence on people’s health and the ecosystem. The ozone hole is becoming larger and larger every year. Rain with pH below 5.6 is called acid rain. Sulfur oxides (SO2) and nitrogen oxides (NO2) are gases generated from the use of fossil fuels, which acidify rain. The acidification of soil, rivers, lakes, and marshes badly damages the forests and ecosystem. Pollution is caused by discarding harmful industrial waste into the soil or sea. Typical harmful substances include heavy metals and plastic materials. For instance, the daily waste generated in the United States was around 65 million tons in 2001. On a worldwide scale, the amount of waste going into landfills is gigantic. Pollution also occurs from the toxic gases that are released when harmful industrial waste materials are incinerated. TABLE 8.2 Depletion of Critical Materials Total amount Oil (barrels)

Remaining amount

Remaining duration

2 trillion

900 billion

45 years

Natural gases (m )

200 trillion

100 trillion

56 years

Coal (tons)

10 trillion

1 trillion

300 years

4.36 million

72 years

3

Uranium (tons)

—

Silver (tons)

280,000

15,000

19 years

Gold (tons)

42,000

1,800

23 years

Titanium (tons)

173 million

6.45 million

27 years

Copper (tons)

352 million

9 million

39 years

Nickel (tons)

49 million

0.87 million

36 years

Steel (tons)

66 billion

0.982 billion

67 years

ENVIRONMENTAL ISSUES FOR CONVENTIONAL PCBs

8.5

8.2.1.4 Decrease of Tropical Rain Forests and Increase of Desert Areas. The tropical rain forest area has been continuously reduced by burning forests to gain cultivable land, by cutting trees to produce lumber, and by acid rain. It is estimated that 17 million hectares of rain forests are disappearing from the surface of the earth each year. When the tropical rain forests decrease, the ability to consume CO2 from the atmosphere decreases, thus accelerating the global warming process. On average, the desert area increases by 6 million hectares worldwide every year as a result of drought, overcultivation, and the use of pesticides. This influences the production of food and leads to changes in climate. 8.2.1.5 Transfer of Harmful Industrial Waste. Advanced industrial nations usually have strict regulations and high costs for the disposal of industrial waste. As a consequence, harmful industrial waste is often transferred from countries where disposal costs are high to countries where the disposal costs are low. Some countries are prone to severe environmental damage, because waste is left undisposed due to lenient local laws and economic constraints. To control the border transgression of harmful industrial waste, the Basel Treaty was adopted in 1989. It should be noted that the aforementioned environmental issues do not stand alone; instead, they influence one another, as shown in Fig. 8.3. Furthermore, since the population will increase from 6 billion people in 2000 to 12 billion by 2050, it is evident that environmental issues are the most significant issues facing human beings today.

8.2.2

ENERGY ISSUES6

About 90 percent of the primary energy demand in the world is supplied by fossil fuels (e.g., coal, oil, and gas). Electricity is by far the largest energy source required during electronics manufacturing and operation of end products and systems. Approximately one-half of the world’s electricity production comes from burning fossil fuels, which cost about 20 percent of total fossil energy resources. The other half of electricity comes from nuclear power and hydropower, both of which are considered to have less of an environmental impact than the fossil-based electricity production, although they present their own set of problems. The consumption of fossil energy resources may have several significant environmental effects. One direct impact is the depletion of fossil fuels, and another is the higher concentration of polluting gases such as CO2, nitrogen oxides (NO2), and sulfur oxides (SO2). These gases lead to global warming and acid rain as mentioned before. Nitrogen oxide and different hydrocarbon emissions are also significant sources of ground-level ozone, which damages agricultural production and contributes to health hazards. In general, there are two approaches by which energy consumption can be controlled. First, consumers can choose suppliers that use better energy production methods or better fuel qualities. Second, energy consumption can be lowered through improved system design that consumes the energy in a more effective way. For instance, reduction in standby consumption of electricity in ac/dc devices could be very important for products that are plugged in permanently but are not in real use. During long-term operation, more energy is consumed in the standby mode than in the actual use. By switching off the device when not in use, the actual usephase energy consumption can be improved dramatically. For example, consider the charging of a mobile phone. If the charger is plugged in permanently instead of charging it only when needed, the energy consumption during a year of usage can be

8.6

CHAPTER EIGHT

FIGURE 8.3 Mutual relationship among various environmental concerns.

ENVIRONMENTAL ISSUES FOR CONVENTIONAL PCBs

8.7

20 times higher. To avoid this kind of energy consumption, one option is to design smart charging devices that can shut themselves down. Most of the system operations are controlled by software. Hence, software design can play a very important role in reducing power consumption, thereby helping the environment. The daylighting system has been proven to be able to provide energy savings in numerous cases. A leading aviation company in the United States has retrofitted such a lighting system in its design and manufacturing areas, and was able to cut almost 90 percent of the lighting energy being used. The Eco Store with the daylighting system helped to increase the productivity of employees and also boost sales. Examples like these indicate that there are untapped sources of alternative energy. Conventional alternative energy such as wind power and solar energy can be utilized in many tropical developing countries as a source for household energy. In the United States, California receives 9 percent of its energy from renewable sources other than hydroelectricity. In the energy sector, the world’s fastest-growing technologies are wind power and photovoltaic solar cells.

8.2.3

CHEMICAL ISSUES7

8.2.3.1 Risk Substances in Products. Figure 8.4 illustrates the most common processes for electronics production, starting from an IC to a final product such as a PC or a cellular phone. The relevant materials with environmental concerns and their potential solutions are also given for reference. Lead (Pb). Lead is mainly used in the form of solder alloys for connection of components to the printed circuit boards (PCBs), surface treatment of components, PCB finishes, and lead batteries. Lead-containing solders, particularly tin-lead eutectic solder, have been embraced by the electronics manufacturing industry due to their combined benefits of low cost, good soldering properties (such as wettability, adequate melting temperature range, and high oxidation resistance), and desired physical, mechanical, electrical, and metallurgical properties. Lead causes severe health problems, including irreversible brain damage and injury to blood-forming systems, even at relatively low levels in the body. The fact that modern technologies and living habits are significantly contributing to lead concentrations in humans can be illustrated using the following data: ● ● ●

Prehistoric man: 3 × 10−4 g Pb Current Americans: 1500 × 10−4 g Pb Minimum lead poisoning level: 6000 × 10−4 g

Lead enters the body mostly by ingestion. Even after kidney excretion, it remains in the bones with an average life of 3 to 5 years. Cadmium (Cd). Cd is used in nickel-cadmium batteries, chemicals for surface treatments, pigments for paints, and in plastics. Cadmium is a highly toxic metal, and it tends to accumulate in the body. Halogenated Materials. Fluorine (F), chlorine (Cl), and bromine (Br) are very reactive, and are the key elements in many toxic compounds. In the periodic table, they belong to the highly reactive group of elements called halogens. A halogenated material contains one or more of these elements. Halogenated materials are mainly used as flame retardants in electronic products. Bromine is the most common halogen used as a flame retardant. To appreciate

8.8

CHAPTER EIGHT

FIGURE 8.4 Environmental concerns and potential solutions.

the function of a halogen, the mechanism of polymer combustion has to be understood. The mechanism of polymer combustion has been found to be as follows: ● ● ●

Polymer decomposes by heat, resulting in the generation of a hydrocarbon. Hydrocarbon is converted to a radical (OH radical) by oxidation. The OH radical repeats the exothermic oxidation of CO while releasing a lot of heat.

If a halogenated flame retardant is present in the polymer, the heat generated causes the halogenated materials to decompose and form a halogenate gas (HX), which can trap the OH radical and end the radical reaction (combustion). The requirement for flame retardants in the electronics industry goes back to its inception in the late 1940s and 1950s, when it became apparent that high voltages, current, and heat could cause fires. Brominated flame retardants are largely used in plastic frames, housings, cable sets, and PCBs. The current focus is on the use of bromine in PCB epoxy resin (Fig. 8.5) to meet the Underwriters Laboratories (UL), Inc., 94 V0 specifications, which define the self-extinguishing capability of materials. The acceptance of brominated materials became a concern in the late 1970s when studies in Great Britain and Germany revealed that two-thirds of the deaths from accidental fires were caused by toxic gases rather than by direct fire burns. Further

ENVIRONMENTAL ISSUES FOR CONVENTIONAL PCBs

8.9

FIGURE 8.5 Brominated epoxy resin.

(a)

(b)

FIGURE 8.6 Structure for (a) bromodibenzodioxin and (b) bromodibenzofuran.

research showed that, under special burning conditions (700 to 900°C), brominated plastics can produce dibenzodioxins and dibenzofuranes (Fig. 8.6), which are carcinogenic gases and 10,000 times more harmful than cyanate gas. The preceding concerns resulted in many proposed legislations but were defeated because of the lack of availability of a good, low-cost alternative. The WEEE of the EC drafted the most recent legislation. This proposal would eliminate brominated material by 2004 from consumer electronic products. Other countries, including Germany, have already enforced laws that limit the products that are allowed to contain brominated flame retardants.

8.2.3.2 Risky Substances Used in the Manufacturing Process. Besides the substances described in the previous sections, there are other materials that are used specifically in manufacturing processes, but are not included in the final products. Examples of such materials include the following: ●

● ●

● ●

Solvents used in the PCB manufacturing process [e.g., methyl ethyl ketone (MEK), dimethyl formamide (DMF), etc.] Chemicals used for flux cleaning during solder connection (Freon) Chemicals used in the etching process to print copper lines or circuits on PWBs (e.g., strong acids, oxidizers) Wastewater Volatile organic compounds (VOC) used in flux, solder paste, and so on

Restrictions have been imposed on the use and disposal of chemicals for flux cleaning and etching. Solvents that include VOCs and wastewater are a major concern,

8.10

CHAPTER EIGHT

even in today’s PCB manufacturing. Solvents used in industry are regarded as harmful and as a source of ecological pollution because they can directly, or indirectly, lead to the following problems: ● ● ● ● ●

Poisons to the human body Destruction of the ozone layer in the stratosphere Bad odor Global warming Acidification of rain by generation of photochemical oxidants

Wastewater is another source of ecological pollution. The water from a PCB plant contains metals (Cu, Sn, Pb, Fe, Ni, etc.), anions (cyanides, fluoroborates, nitrates, sulfates, etc.), dissolved solids, and suspended solids. The pH is usually between 6 and 9. Ecological pollution can be controlled by implementing legal restrictions. However, it should be recognized that not everything can be controlled or implemented by laws. A commonsense approach to protect health should prevail in such circumstances. As an example of harmful solvents used in industry, the process and chemicals used in PCB manufacturing will be discussed briefly. A PCB is a composite material consisting of reinforcement, such as glass cloth or mat, and a resin such as epoxy. The majority of the epoxy resins used in the process are room-temperature solids. These resins are diluted with a solvent to make a solution of suitable viscosity for impregnation into the glass cloth. These toxic solvents evaporate into the atmosphere after their use. A significant amount of heat is also wasted in evaporating these solvents. During this drying process, the resin is partially reacted to reach higher molecular weight, resulting in an adequate melt viscosity. These partially cured materials are called prepregs, and the intermediate state of the resin is called B-stage resin. In this stage, molecules are still linear and the resin can be melted by heat. Prepregs are piled on each other to reach the desired thickness. They are generally covered with copper foils on one or both sides and laminated under heat and pressure. During this process, the resin melts, and the piled-up sheets and copper foil adhere to each other to form a laminated structure. The final product results from the subsequent curing by cross-linking reaction. This fully cured state of matrix resin is called C-stage resin. 8.2.3.3 Replacement of Lead-Based Solders. Lead-based solders are used extensively in microsystems assembly. Two types of alternate materials, namely, conductive adhesives and lead-free solders, are being developed to replace lead-based solders. Isotropic Conductive Adhesives. Isotropic conductive adhesives were developed to replace eutectic solder (63% Sn, 37% Pb). The main advantages of using polymeric materials are low die stress and low processing temperatures. Most of the conductive adhesives are silver-filled epoxy with more than 65 wt % filler loading. Silver flakes are used because of their high conductivity. Although these adhesives offer electrical conductivity close to that of solder (<5 mΩ/4 × 4 mil bump), and better stencil yields, their usage has been limited to niche applications such as optical devices that are assembled at low temperatures. The deficiency of these adhesives to replace conventional solders for SMT assembly arises from poor reliability and assembly yields. Silver-filled epoxies are not favorable from an economic point of view. These materials cost between $2.50 to $7.00/cc compared with $0.55/cc for solders. In addition, silver-filled epoxy is susceptible to brittle fracture, due to the high filler loading. Unlike lead solders, they do not have self-alignment capability due to

ENVIRONMENTAL ISSUES FOR CONVENTIONAL PCBs

8.11

their low surface energy. Other disadvantages arise from nonreworkability and silver migration failure between tightly pitched leads. Anisotropic Conductive Adhesives. Anisotropic adhesives also have niche applications where low assembly temperature is required. These are mostly used to attach LCD display drivers, because the high solder reflow temperature may destroy the device. Anistropic conductive adhesives may never replace the volume of solder interconnects because of the high pressure required for their assembly. They also suffer from low yield and reliability. Coplanarity is extremely critical and affects the assembly yield. The cured epoxy is also vulnerable to failure by moisture absorption, cracking, and swelling. Lead-Free Solder Alloys. Replacement of eutectic tin-lead solders is still under development. Process parameters (e.g., reflow temperature, preheat temperature, flux type, oven gas, or product bake-out times and temperatures) may require modifications. Although there are successful products assembled with lead-free solders today, acceptable yield is still the bottleneck for many electronic products. Efforts are still under way to find a suitable replacement. All proposed alternative alloys to tin-lead solders use tin as the major constituent, since tin is readily available at a low cost, has a low melting temperature, a high oxidation resistance, and good soldering characteristics such as wettability. Recent studies have been focused on formulating a suitable element that can be alloyed with tin.The search is limited to about a dozen elements. The acceptance or rejection criteria involve toxicity, cost, performance, and availability. Since 13,500 metric tons of lead are consumed in electronic solders worldwide, the availability of a substitute element at a low cost is important. 8.2.3.4 Elimination of Halogenated Flame Retardants. There is an ongoing debate on the replacement of halogenated materials because of the lack of a suitable alternative. For years, many U.S.-based companies and commissions debated numerous concerns (Table 8.3). These include phosphorus- or nitrogen-modified epoxy resins, hydrated alumina, magnesium hydroxide, and high-density polymers. Each of these, however, presents its own challenges. Phosphorus, for example, is expensive and presents electrical leakage when exposed to humidity. Hydrated alumina and magnesium hydroxide, on the other hand, present rheological problems. In spite of all of the difficulties for halogen replacement, many companies, primarily the Japanese consumer electronic manufacturers, are now producing halogen-free laminates

TABLE 8.3 Nonhalogenated Electronic Resin Products Alternative technology

Concern

Phosphorus- and nitrogen-modified Epoxy resin microencapsulated Phosphorus

Phosphorus is also toxic when burned, is more expensive to process (+30%), and will result in electrical leakage with moisture.

Hydrated alumina Magnesium hydroxide

Need very high filler loading because flame retardability is relatively low. Difficult to process when polymer is loaded with high percentage of weight because of high viscosity; these flame retardants release water at relatively lower temperatures, resulting in lower heat resistance.

High-carbon-ring-density polymers (naturally flame-retardant)

Completely different polymer chemistry that is not easily compatible with existing laminate processing.

8.12

CHAPTER EIGHT

and PCBs. These are incorporated into several consumer products that are targeted for the European market. Japanese companies believe that this initiative will gain favorable attention from the EC, which, in turn, will boost the depressed Japanese export market. In 1998, a Japanese company announced the production of the world’s first PC made with a halogen-free motherboard.The resin contains nitrogen- and phosphorusbased flame retardants. They are seeking additional suppliers for their resins and boards. Other companies in Europe and the United States are also planning to implement halogen-free PCBs for cellular phones. It is estimated that the initial prices will be 10 to 20 percent higher compared with the conventional brominated PCBs. It is expected that the prices for halogen-free boards will fall as higher volumes are manufactured. Other electronic equipment manufacturers also desire to meet the pending environmental laws, which have generated many requests for the nonhalogenated boards and, consequently, has spurred increased development and production of nonhalogenated resins. Halogenated flame retardants are generally replaced by phosphorus, nitrogen, inorganic hydroxide (e.g., hydrated alumina), and magnesium hydroxide. Usually these materials are combined. The combination of phosphorus- and nitrogenmodified epoxy resins is most common.At elevated temperatures, phosphorus in the polymer is converted to phosphoric acid. This strong acid reacts with the polymer and absorb the water molecules inside, thus converting it to a carbonlike structure (char). This process of polymer condensation by removal of hydroxyl groups is referred to as carbonization. The carbonized material offers high thermal resistance and acts as a barrier to the diffusion of O2 into the polymer, thus preventing further combustion of the polymer. Nitrogen in polymers forms inert gases during combustion and dilutes the radicals generated during the combustion. Phosphorus and nitrogen have a synergistic effect on the termination of the combustion. Inorganic hydroxides release the water of crystallization when heated above 200 to 400°C. The incombustible water can also absorb heat, dilute the radicals, and hence prevent the polymer combustion. The combination of phosphorus- and nitrogen-modified epoxy resins has some drawbacks, although it is the most common halogen-free technology known today. It is predicted that there will be widespread phosphorus regulation in the near future because of its toxicity level. Hence, the emerging trend is to eliminate both halogens and phosphorus from electronic materials. Accordingly, new flame-retardant epoxies have been developed from a recent collaboration between a Japanese and a Germanbased company.These materials do not have halogens or phosphorus sources but are inherently flame-retardant. This compound consists of an aromatic epoxy resin and a phenol derivative hardener. Because of the highly aromatic structure, this resin provides high heat resistance. On the contrary, the resin is not very rigid, because it has lower cross-link density after cure. When a polymer that has both high heat resistance and low stiffness is exposed to flames, the combustible gases (hydrocarbons) generated from the thermal degradation convert the surface into a layer of foam. This layer prevents the diffusion of oxygen and heat into the resin and stops the combustion. 8.2.3.5 Reduction of Toxic Solvents. Adopting the new PCB process with no discharge of any solvent to the environment can prevent toxic solvent evaporation. A PCB manufacturer in Japan has developed this process and has already utilized it in their production line. Figure 8.7 shows a schematic diagram of this process. Unlike the conventional process, the solvent in this process acts not only as a diluent, but also as a hardener. It means that 100 percent of the solvent is consumed into the

ENVIRONMENTAL ISSUES FOR CONVENTIONAL PCBs

8.13

(a)

(b)

FIGURE 8.7 Comparison of PCB fabrication processes. (a) Solvent usage in conventional process and (b) new process without emission of solvent. (Courtesy of Matsushita Electric Works.)

resin network structure during curing, thus eliminating the discharge to atmosphere. Furthermore, the resin is directly converted to the C stage without passing through the B stage (Fig. 8.8). This new process can save energy in comparison with the conventional process, by avoiding heating for solvent evaporation. Since the process is continuous, heating and cooling steps are eliminated during lamination. Therefore, this process has a much lower environmental impact in terms of solvent emission and thermal energy efficiency. The other way to prevent toxic solvent evaporation in the PCB manufacturing process is to use a direct melting process with no added solvents. It should be noted that most epoxy resins used for PCBs are solids at room temperature. Epoxies can be formulated with a melting temperature ranging from 80 to 150°C. Therefore, by thermal treatment, epoxies can be melted to attain adequate viscosity for impregnation. In this process, the liquid epoxy resin is directly impregnated into the reinforcement such as glass cloth. When utilizing this process, toxic solvent can be eliminated. Some companies have already demonstrated this process in their production line. Furthermore, collaboration between industry and academia in the United States has resulted in a novel recyclable and solvent-free epoxy resin system for PCBs. This novel resin is a lignin-based epoxy, which can be diluted with water.

8.14

CHAPTER EIGHT

FIGURE 8.8 Schematic diagram for the epoxy reaction.

Lignin is one of the constituents of wood and is produced in pulp mills in large volumes, comparable with the production of paper. It is usually handled as a residual waste material. Thus, in addition to environmental friendliness, PCBs made with lignin offer other advantages (e.g., cost reduction and efficient usage of natural resources).

8.2.4

DISPOSAL AND RECYCLING

8.2.4.1 Current State of Disposal and Recycling. When an electronic product is scrapped at the end of its life, an electronic recycler, who specializes in dismounting the products and processing the parts and components, will start to take action. Risk substances can influence the environment during recycling and disposal. Electronic products can be divided into four different scrap categories: 1. Cable sets 2. Printed board assemblies (PBAs) 3. Components and parts that need to be separated for reuse or special waste treatment 4. Structures or housing used for mechanical protection of the product

ENVIRONMENTAL ISSUES FOR CONVENTIONAL PCBs

8.15

In the following section, the environmental concerns that arise from the treatment of a product during its disposal, and the current state of recycling for each of the scrap categories, will be discussed. Cable Sets. The primary environmental concern with dismantling cables and connector frames is the presence of halogenated plastics. A prominent halogenated material is polyvinyl chloride (PVC) with chlorinated and brominated flame retardants. Chemicals that are dissolved in the product during surface treatment of cables are also of concern during recycling. From the current state of recycling, it is observed that all accessible cables are dismounted by the electronic recycler and sent to a special cable recycling facility. Some cables and connectors may have to follow the PBAs into the PBA recycling process. The end results of these two processes are virtually the same: the copper and precious metals are recycled, and the plastics are incinerated or sent to a landfill. PBAs. Brominated flame retardants and the presence of lead components in the soldering system are of special concern today. More toxic substances like mercury have been eliminated by previous regulations. A significant waste fraction arises from PBAs. The recycling of PBAs is very difficult because it is a combination of a variety of materials. The use of halogenated materials and other environmental risk substances in the PCBs and components makes recycling even more difficult. Furthermore, PBAs are made of thermoset resins in order to provide sufficient heat resistance to sustain the high-temperature assembly process. Efforts are being made to use thermoplastic resins for PCBs and encapsulants. However, these technologies have not yet been established. Many PBAs follow their host products into landfills or are incinerated as a part of a big waste stream. Since PBAs contain costly and precious metals, there is a strong interest in their recovery. Metal recovery from PBAs can lead to emission of pollutants if done without proper waste treatment. Special treatment facilities control emissions through extensive cleaning of the waste. Components and Parts Requiring Special Treatment. A wide variety of electronic components contain one or several environmental risk substances that are not suitable for the normal waste disposal. For example, toxic metals such as cadmium and lead present in batteries have a high environmental impact if they are not recycled. Therefore, such components need special treatment. All types of batteries should be dismounted and sent to special facilities for material recovery. Some components and parts, such as computer memories, should be separated for reuse. It should also be made a common practice to reuse old components as spare parts if they are in short supply. Structures or Housing of Electronic Systems. As discussed previously, halogenated materials within plastics raise environmental concerns. Surface coatings made of chromium(VI) and other mixtures are also considered hazardous. The recycling potential is high for metal structures made of steel and aluminum.The mechanical structures are sent to the producers of raw metals and alloys. Alloys and metallic coatings may not be included in the recycled materials, depending on whether the recovery of individual elements from these mixtures is economical. Some metals that are lost in the recovery process may have to be replaced. The recycling potential for plastics is low, because it comprises a mixture of materials and additives. Energy recovery should be considered during the incineration of plastics. 8.2.4.2 Recycling Potential and Future Trends. In principle, recycling of electronics is limited to copper and other precious metals. The recycling potential of plastics is low compared with metals. Plastics are incinerated or sent to the landfill even though they contain risk substances like halogenated flame retardants or

8.16

CHAPTER EIGHT

leaded alloys. If such plastics are landfilled, the risk substances can leach into the soil and pollute the groundwater, subterranean and sea. Acid rain may accelerate this process. The incineration of plastics also leads to pollution of the environment. When halogenated plastics are incinerated in the temperature range of 700 to 900°C, carcinogenic gases such as dibenzodioxin and dibenzofuran are released. Another concern is the transfer of harmful industrial waste from advanced countries to developing countries. In spite of the significant increase in the variety of products over the past several years, the number of products being handled by an electronic recycler is low. The majority of scrapped electronic parts is dumped in landfills or incinerated.A fraction of these products goes through another harmful scrapping process. The environmental risks increase with the increasing number and volume of products. Improvements are necessary to the electronic waste system. Landfilling, along with prevention of incineration of harmful chemicals, should be made mandatory in the future. It is time to implement suitable electronics recycling systems. Electronics recycling must be geared toward automatic shredding of the products into individual material types. Recycling processes should be standardized in order to further reduce the use of harmful substances. If a recycling system had been established in the past, the use of lead would have already been minimized. High-end product manufacturers should be scrutinized and the practice of recycling should be strictly reinforced. Low-end consumer products should use fewer risk substances, because it is difficult to control the recycling of those products.

8.2.5

DESIGN FOR ENVIRONMENT

To compare materials, systems, and products from an environmental standpoint, total environmental impact (from the components to the system-level manufacturing, use, and disposal of products) should be considered. Similarly, the total cost should be estimated when comparing materials, systems, and products. This should include the cost of purchase, use, and disposal. Life cycle assessment (LCA) is a tool for estimating the impact of a product on the environment during its lifetime, which spans from raw material usage during production to its service until scrapped or recycled. Therefore, an LCA reviews the entire life cycle of a product comprehensively. As a demonstration, an LCA study for the new PCB process is compared with the conventional process. The new process can eliminate the emission of solvents and can increase the energy efficiency, as discussed before (Fig. 8.9). Figure 8.10 indicates the results of inventory analysis for energy consumption and CO2 emission. The analysis was done considering raw materials, production, transfer, use, and disposal. As seen in Fig. 8.10, the new PCB process can reduce energy consumption by 77 percent and CO2 emission by 74 percent during production. Furthermore, the LCA analysis helps in understanding that the environmental impact of raw materials is dominant. As a next step toward improvement, one must focus on the selection of raw materials, and choose raw materials that have lower environmental impact. From the LCA study, the importance of reducing the environmental impact throughout the life cycle of a product can be understood. Accomplishing this reduction, however, requires implementation at the beginning of the life cycle. This is called a design for the environment (DfE). In the twenty-first century, customers demand more information regarding the product, process, and its environmental compatibility. Currently, limited information is available to customers regarding the material content of products, process-related

ENVIRONMENTAL ISSUES FOR CONVENTIONAL PCBs

8.17

FIGURE 8.9 Environmental performance profile.

chemicals, and the energy that is consumed in the process. Hence, the customers cannot assess environmental performance while making a purchasing decision.An environmental measure using just one symbol provides limited information to support these kinds of decisions. More information is needed in order to be able to evaluate the use of energy and environmental risk substances. With this knowledge, customers may be able to influence manufacturers to choose environmentally friendly processes and products.

(a)

(b)

FIGURE 8.10 Energy consumption carbon dioxide emission. (a) Energy consumption in megajoules per sheet of PWB and (b) CO2 emission in kilograms per sheet of PWB. (Courtesy of Matsushita Electric Works.)

8.18

CHAPTER EIGHT

Another DfE requirement is that data regarding the environmental impact of a product should be collected during the design phase itself. The design requirements from an environmental point of view should be quantified, so that the information can be shared among different customers. In the future, manufacturers should be prepared to provide more information and answer more questions pertaining to the environmental impact of their products. The future of “green” electronics seems to be extremely bright. However, as long as human beings do not regard environmental issues as their own concerns, natural resources will keep decreasing, industrial output and pollution will keep increasing, and finally, catastrophe in the middle of the twenty-first century will occur. Even legal enforcements may not provide a good solution in such situations. By developing a consciousness of saying no to industrial waste and other types of pollutions, and investing in nature’s capital, people can significantly help to reduce the depletion of nature’s resources and to balance the ecosystem on this planet. Each person must tackle the current environmental issues head-on and follow the path that leads to a sustainable scenario.8–11

8.3

ENVIRONMENTAL RESEARCH FOR THE PCB INDUSTRY

The global concern over environmental and health issues has resulted in a pull from consumers for green technology and products, and a push from regulatory agencies at both the national and international levels. This results in a shift from end-of-pipe solutions (e.g., waste disposal and remediation) to new emphasis on DfE, where the focus is to reduce energy and consumables in the manufacturing of products, and to design products to minimize environmental impact so that they can be disassembled, reused, and/or recycled. This trend may increasingly affect the manufacturing and design of computer products, their technology development, plant locations, and marketing strategies. As the computer industry proceeds in the twenty-first century, further research efforts are required to provide creative solutions to address those issues that are needed to minimize environmental impact, enhance global competitiveness, and address regulatory issues without an impact on quality, productivity, and cost.12–15 In 1994, IBM Research, in partnership with its manufacturing divisions and supported by funding from SEMATECH, developed a diluted cleaning solution used for silicon wafer processing. This replaced the typical cleaning solution that has been used throughout the industry for the past 25 years, and resulted not only in a lower cost due to a one-third reduction in chemical consumption and a saving of 3 million gallons of water per year, but also an increase in yield. This process has now been implemented worldwide in manufacturing facilities. It is an excellent example demonstrating that examining legacy manufacturing processes to reduce resource consumption can also result in enhanced performance and lower costs, and ultimately competitive advantages.16–21 Recently, technologies are being developed to improve materials and processes for PCB fabrication. In this industry, it is a common practice to use high volumes of solvent to coat epoxy resins on the glass fabric that makes up the bulk of the PCB. In the meanwhile, substantial electrical power is needed to dry and cure the resin on the cloth. Currently the PCBs are not recycled, because the removal of soldered and encapsulated subassemblies is too costly. In general, these boards are incinerated using high-cost scrubbers, and the residual ash (approximately 30 per-

ENVIRONMENTAL ISSUES FOR CONVENTIONAL PCBs

8.19

cent by weight of PCB) must be buried in hazardous-waste landfills due to its lead content. To address these concerns, various efforts from the government, academia, as well as private industries are consolidating to develop green card technologies. Such emerging trends are aimed at the following objectives22: ●

●

● ●

To develop microwave technology to eliminate the solvents and reduce the energy that is required to fabricate PCB prepreg To develop new resin systems such as (1) water-based epoxies to eliminate solvent hazards and (2) resins derived from renewable resources (plants or microorganisms) to reduce the usage of oil-based resins To develop alternatives to lead-based solders To develop new, reworkable encapsulation materials to enable the reclamation of devices and packages, and to address disassembly issues

8.3.1

ENERGY AND SOLVENT REDUCTION

In PCB manufacturing, prepreg fabrication has the greatest impact on environmental emissions, since the resin (usually an epoxy resin) is first dissolved in a lowboiling solvent, such as MEK or acetone to control viscosity and ensure efficient wetting of the resin on the glass for uniform coating. The glass cloth is then dipped through a tank containing the solvent resin and passed up a treater tower, which consists of a number of ovens or hot-air jets heating the web to remove the solvent and partially cure the resin (B stage) in a continuous operation. A schematic diagram of the process is illustrated in Fig. 8.11.After removal from the web, the solvent is then vented to the outside or incinerated, emitting up to 600 lb CO2/h or about 5 million lb/year for a medium-sized facility, depending on the environmental regulations at the location of the treater tower. This accounts for about 20 million lb of solvent per year industry-wide, or about 4 percent of the total U.S. production of MEK. In addition to the environmental hazard, there is also the risk of explosion or fire within the treater facility, as well as the risk of operators being exposed to the solvent. The latter not only drives the cost of new installations, but places a severe limitation on the types of solvents that can be used. The expected, more stringent environmental laws will limit the continued use of solvent coating. Some alternatives include melt, powder, and emulsion coating in which the resin is carried by water. For the manufacture of prepreg, the best alternative is in water-based resin systems, which still permit a liquid phase to carry the resin into the closely woven cross-ply glass bundles. A new FR-4 epoxywater emulsion has been developed for prepregging. Initial tests indicate that after water removal, the prepreg has essentially identical properties as prepreg made from organic solvents. Laminates fabricated from the water-based resin have similar electrical, physical, and mechanical properties as those from solvent-based resins. However, effective processing of water-based resins might require new technology and tooling. The limiting factor in the speed of production of prepreg today lies in the heat transfer rate to the resin and fiber in the tower. With the use of microwave radiation drying and curing, the energy savings for a typical tower operation results in the heat utilization being reduced from 1 MW to 20 to 30 kW, which is a substantial reduction. The use of microwave curing to dry and cure resin-coated

8.20

CHAPTER EIGHT

FIGURE 8.11 Application of microwave prepregging for heat reduction.

glass fabric is particularly attractive because microwaves will transfer their energy directly to the resin and solvent without losing heat to convection losses, which wastefully heats the surrounding air or equipment. While microwave technology is broadly used in the food industry, it has been slow to impact applications that call for uniform and controllable heating. Extending microwave drying and curing to a wide web of epoxy-coated glass fabric requires the coupling of the fundamental understanding of processes and materials, with the design and engineering of new microwave applicators. As microwaves couple very efficiently with water, the development of microwave technology would enable the use of water-based resins. These materials would eliminate the environmental and safety concerns of solvents, and provide low-cost materials. Microwave technology has great potential to eliminate the solvents that are used in PCB manufacturing, reduce energy consumption, and provide lower cost, more compact tooling, and enable the use of water-based resins.23

8.21

ENVIRONMENTAL ISSUES FOR CONVENTIONAL PCBs

8.3.2

RENEWABLE RESINS FOR PCB

Another area of interest is the use of biopolymers (materials that are derived from plants and micro-organisms) to replace the oil-based epoxy resins that are typically used in the industry. Of these materials, lignin is of particular interest. Lignin is essentially the glue that ties the cellulose together in plants and trees. It is produced in large volume (∼100 tons/day) as a by-product of paper manufacturing, and its molecular structure provides the thermal stability and chemical resistance necessary for PCBs. Although research is in the initial stages, results of testing at IBM and Sandia National Laboratories have shown that PCBs fabricated using a formulation of epoxy resins with 50 percent lignin content can provide a PCB with equivalent or better thermal and electrical performance than current high-volume PCBs. In addition, the cost of resin materials can be significantly lowered and the dependence on fossil fuels is substantially reduced. Furthermore, the waste stream in paper mills is minimized.24 Table 8.4 compares the material properties of lignin laminates with typical FR-4 materials. TABLE 8.4 Material Properties of Lignin Resin Laminates

Glass transition, min (°C)

IPC Standards for FR-4

Lignin laminate

FR-4 control

>110

124–136

128

15.4 19.7 27.1

24.2 24.2 60.6

7.11 8.43 342

14.6 11.3 430

314

313

0.80

0.3285 1.7386 1.5553

0.3462 2.1760 1.7233

8

7.3

11.3

Coefficient of thermal expansion (µm/m°C) Below Tg X Y Z Above Tg X Y Z Decomposition temperature (°C) Moisture absorption max. (wt %) 24 h room-temperature water 16 h boiling water 1 h pressure cooker Copper peel strength of 1 oz. Cu, min (lb/in) Permittivity, max (at 1 MHz)

5.4

4.1

4.0

0.035

0.023

0.015

Volume resistivity, min (MΩ-cm)

106

1010*

Surface resistivity, min (MΩ-cm)

4

1010*

Dissipation factor, man (at 1 MHz)

10

Dielectric breakdown, min (kV)

40

>45*

Electrical strength, min (V/mil)

7.50

9.00*

Arc resistance, min (sec)

>60

Flammability

66* UL V-0 (using brominated epoxy)

* Testing performed by Trace Laboratories on laboratory laminate samples.

UL V-0

8.22

8.3.3

CHAPTER EIGHT

REWORKABLE ENCAPSULANTS FOR DISASSEMBLY

Over the past 30 years, epoxy thermosetting polymers have improved to the point where they are the mainstay for electronic packaging, providing high reliability at low cost. They are easily processed prior to curing because of their low viscosity without the addition of solvents. However, after curing, these materials become highly cross-linked and, hence, insoluble and infusible. While they are excellent encapsulants, it is not possible to recover part-good assemblies, or to remove and recycle chips and components. To address these concerns, a new thermosetting epoxy composition has been developed that functions like a typical encapsulant, but can be removed for chip rework and component disassembly.25–27 This new epoxy incorporates a chemically cleavable link into the polymer network, as shown in Fig. 8.12, which allows the material to be completely dissolved in specially designed, water-based, mildly acidic systems. The material meets all of the stringent requirements of a typical epoxy, including curing speed, temperature and

FIGURE 8.12 New formulation allows encapsulation to be dissolved in water.

ENVIRONMENTAL ISSUES FOR CONVENTIONAL PCBs

8.23

humidity stability, ionic purity, and age testing under actual-use conditions. The material is easily synthesized and has been scaled up at a commercial source. Actual assemblies have been fabricated and tested, and the system is undergoing qualification. The development and rapid implementation of the preceding innovative technologies have been effective because of partnerships with industry, academia, and government agencies, as well as a concurrent focus on cost, performance, and productivity. While these new technologies are aimed at the electronics industry, it is believed that they may impact a much broader technology base.

8.4 INTERNATIONAL DRIVING FORCES FOR HALOGEN-FREE ALTERNATIVES The term halogenated refers to the addition of halogenated organic compounds to a polymer in order to achieve a flame retardancy function. Halogenated flame retardants (HFRs) can be used in a number of applications within electronic and electrical products. Halogen additives [such as polyterafluoroethylene (PTFE)] may be added to prevent dripping of a polymer in the case of fire. PVC may be used in enclosures, and Teflon/PTFE (a fluoro-based polymer) substrates may be used to achieve good high-frequency properties. Trace amounts of halogens may also be present in epoxy resins due to limits to the ability to purify chemicals. The electronics manufacturing industries are facing an increasing need to find halogen-free alternatives for flame retardancy in their products due to the legislative actions and market pressure. To support development of corporate actions, the International Project on Flame Retardancy in Electronics-Conceptual Study has been carried out with the collaboration among major electronics manufacturers and materials suppliers from Europe and Japan.28 The idea behind the conceptual approach was to gain a comprehensive view of state-of-the-art halogen-free alternatives and of the mechanism governing the design for flame retardancy.

8.4.1

BACKGROUND AND CHALLENGE

In the past decade, there has been an increasing concern about the potential effects on the environment from the use of HFRs. The demands for reducing the usage of HFRs have turned into legal actions. The major electronics manufacturers perceive nowadays that they will be judged by the market if their products contain HFRs. In the long run, all electronics should be free from HFRs. This is a transformation that requires an extensive technical development and thorough assessments of new solutions in terms of technical, economic, and environmental performance, as well as infield reliability and considerations concerning timing and sourcing.29 The question of flame retardancy (or fire safety) includes at least three major aspects that must be considered: 1. Electrical condition. Electronic products contain energy sources making them a potential source of fire. 2. Origin of fire. The objective of design for fire safety in electronic products is to avoid fire being caused by the product itself (internal fire safety) and to avoid electronic products contributing to and/or enhancing fires originating from sources in the vicinity of the products (external fire safety).

8.24

CHAPTER EIGHT

3. Trade-off condition. To find a balance between flame retardancy (fire safety level), environmental impacts, technical performance, and life cycle economics.

8.4.2

DRIVING FORCES

The trend toward halogen-free alternatives is created by a number of driving forces. Brief descriptions of the major ones are summarized as follows. 8.4.2.1 Legal Actions. In May 1998, the first draft proposal for an EC directive on WEEE was presented, followed by a second draft in July 1998. In July 1999, a draft proposal for a European Parliament and Council Directive on WEEE was presented. This draft calls for a ban of PBB and PBDE from 2004. In March 1999, the Swedish chemical inspectorate (KemI) forwarded a report to the Swedish government concerning a prohibition of flame retardants. KemI proposed that Sweden introduce a prohibition against marketing and use of PBDE and PBB and prohibit the marketing of goods containing these substances. Sweden should also work for a prohibition within the EU and make additional efforts to achieve a change on the international market. It is unclear what the final outcome of these and other legal actions will be. In any case, they highlight the use of HFRs. 8.4.2.2 Environmental Labeling Schemes. Environmental schemes such as TCO’95, TCO’99, Nordic Swan, and Blue Angel do not allow the use of HFRs. It is true that the requirement is restricted to plastic parts with a certain minimum weight (i.e., PCBs and component encapsulants are not included). The schemes have a clear impact on the market. More than 1000 display units (models) have received the TCO label, and it is estimated that more than 100 million display units with the TCO label are in use worldwide. Environmental schemes will probably gain increasing recognition in the future, and the requirements on flame retardants will probably become more severe. 8.4.2.3 Japanese Dioxin Case. Dioxin emissions have become a major environmental issue in Japan in recent years. In March 1997, local authorities in Tokorozawa City detected dioxin from Japanese incineration facilities due to too low process temperatures. A local regulation is now in place and legislative actions are being considered by the Japanese government. This has caused Japanese electronics manufacturers to develop halogen-free solutions and to implement halogen-free materials in products. 8.4.2.4 Customer Requirements and Public Perception. Large companies and institutional buyers increasingly ask for material declarations when buying office equipment. Halogenated flame retardants are one of the major substances that are considered when evaluating quotations. Scientific studies have shown occurrence of HFRs in human blood and breast milk. Halogenated flame retardants are now a recurrent subject in Nordic newspapers and magazines and are increasingly perceived as an environmental problem by the public. 8.4.2.5 Corporate Actions. An increasing number of companies are today evaluating halogen-free PCB laminates and IC encapsulation materials. Several large Japanese electronics manufacturers have implemented halogen-free PCBs in products such as laptop computers.

ENVIRONMENTAL ISSUES FOR CONVENTIONAL PCBs

8.4.3

8.25

MATERIAL AVAILABILITY

To assess the availability of halogen-free materials and components, a large number of polymer, PCB laminate, and cable manufacturers, as well as semiconductor manufacturers, were surveyed. The results are summarized as follows: ● ●

● ●

At least four halogen-free FR-4-grade laminates were commercially available. Substantial work has been done in developing halogen-free encapsulants for semiconductors by a number of companies. From 1999, some of these materials are commercially available. Quite a wide range of halogen-free polymers is available for other applications such as connectors, transformers, relays, and so forth. A wide range of halogen-free polymers are available for enclosure applications. There is a large number of compound suppliers for cables and wires. Most of them are currently developing or producing halogen-free materials.

The International Conference on Halogen-Free Materials for Electronic and Electrical Products, held in September 1999, showed that additional halogen-free PCB laminates are available on the market.30

8.4.4

DESIGN MEASURES AND PERFORMANCE

In addition to the survey of halogen-free materials, design measures reducing or eliminating the need for flame retardants were identified and assessed. The identification of design measures was based on the fundamental conditions for a fire to take place. The outbreak of fire in a piece of electronic equipment is dependent on the supply of fuel, heat, and oxygen. For ignition to occur, all three components are needed. In the case of electronic equipment, the fuel will initially consist of polymers, possibly dust, and other combustible material in the equipment. Keeping in mind the conditions for a fire to take place, the following potential design options are available: ●

●

●

Eliminate or reduce the amount of fuel (e.g., by using materials with a low rate of combustion and a high glass transition temperature). Reduce heat and/or energy levels (e.g., by using fuses, keeping down normal operating temperatures, protecting inputs from transients, and using materials that will conduct heat away from hot spot). Reduce or eliminate oxygen (e.g., by restricting air supply).

The challenge of “Design for Environmentally Conscious Fire Safety” has been addressed in a new project, called FIRESEL, which began in early spring 2000. The aim of this project has been to investigate the science of fire safety in electronic systems to enable reliable, cost-effective, and environmentally sound solutions to fire safety.

REFERENCES 1. Feldman, K.,“Suitability of Thermoplastic Base Materials for PCBs,” Proceedings PCWC7, Basel, Switzerland, pp. 12–18, 1996.

8.26

CHAPTER EIGHT

2. Goldberg, L. H., and W. Middleton, eds., Green Electronics/Green Bottom Line: Environmentally Responsible Engineering, Newnes, Boston, 2000. 3. Tummula, R., Fundamentals of Microsystems Packaging, McGraw-Hill, New York, 2001. 4. Beckel, L., ed., The Atlas of Global Change, Simon & Schuster Macmillan, New York, 1998. 5. Mannion, M., and S. R. Bowlby, eds., Environmental Issues, John Wiley & Sons, New York, 1992. 6. Mendicino, L., and L. Simpson, eds., Proceedings of the Second International Symposium on Environmental Issues in the Electronics and Semiconductor Industries, Electrochemical Society, Seattle, WA, 1999. 7. Murphy, J., The Additive for Plastics Handbook, Elsevier Technology, New York, pp. 324–325, 1996. 8. Shaw, J. M., S. L. Buchwalter, J. C. Hedrick, S. K. Kang, L. L. Kosbar, and J. D. Gelorme, “Big Blue Goes Green,” Printed Circuit Fabrication, 19(11):38–44, 1996. 9. Shirrcl, C. D., W. H. Christiansen, S. R. Lyer, and L. D. Bravence, “Prepregging for the Twenty First Century: A Solventless Prepregging Process,” Proceedings IPC Printed Circuits Expo., 1996. 10. Simmons, G., Earth, Air, Water: Resources and Environment in the Late 20th Century, Edward Arnold, New York, 1991. 11. Simpson, C. R., et al., eds., Environmental Issues in the Electronics/Semiconductor Industries and Electrochemical/Photochemical Methods for Pollution Abatement, Electrochemical Society, NJ, 1998. 12. Balzhiser, R. E., Technology and the Environment, National Academy of Engineering, Washington, DC, 1989. 13. U.S. Congress, Office of Technology Assessment, Green Products by Design Choices for a Cleaner Environment, OTA-E541, U.S. Govt. Printing Office, Washington, DC, October 1992. 14. MCC Task Force, Environmental Consciousness: A Strategic Competitive Issue for the Electronics and Computer Industry, MCC Task Force, March 1993. 15. The National Science and Technology Council, Technology for a Sustainable Future, The National Science and Technology Council, Washington, DC, 1994. 16. Cohen, S., et al.,“Minimizing Chemical Consumption for Semiconductor Wet Wafer Cleaning Processes,” Microcontamination Conference, San Jose, CA, 1993. 17. Lewis, D. A., S. Whitehair, A. Viehbeck, and J. M. Shaw, MRS Proceedings, Spring 1996. 18. Rosbar, L., and J. D. Gelorme, Bio-Based Resins for the Manufacture of PCBs, SPE ANTEC, May 1996. 19. Saraf, R. F., J. M. Roldan, C. J. Sambucetti, M. A. Gaynes, and R. Lewis, “High Performance Isotropic Polymer/Metal Composite for Interconnect Technology,” Japan International Electronic Manufacturing Technology Symposium, IEEE/CPMT, Omiya, Japan, December 1995. 20. Saraf, R. F., J. M. Roldan, R. Jagannathan, C. Sambucetti, J. Marino, and C. Jahnes, “Polymer/Metal Composite for Interconnection Technology,” 45th Annual Electronic Components and Technology Conference, IEEE, Las Vegas, NV, May 1995. 21. Brusic, V., G. S. Frankel, J. Roldan, and R. Saraf, “Corrosion and Protection of a Conductive Silver Paste,” J. Electrochem. Soc., 142:2591, 1995. 22. Gaynes, M.A., R. H. Lewis, R. F. Saraf, and J. M. Roldan,“Evaluation of Contact Resistance for Isotropic Electrically Conductive Adhesives,” IEEE Trans., Comp. Pkg., Mfg. Tech., 18:299, 1995. 23. Gaynes, M.A., R. H. Lewis, R. F. Saraf, and J. M. Roldan,“Evaluation of Contact Resistance for Isotropic Electrically Conductive Adhesives,” 1st Intl. Conf. on Adhesive Joining Tech. in Electronics Mfg., Berlin, Germany, November 1994.

ENVIRONMENTAL ISSUES FOR CONVENTIONAL PCBs

8.27

24. Kang, S., T. Graham, S. Purushothaman, J. Roldan, and R. Saraf, “Lead-Free Conducting Adhesives,” Proc. IEEE International Symposium on Electronics and the Environment, pp. 177–181, Orlando, FL, May 1–3, 1995. 25. Kang, S., R. Rai, and S. Purushothaman, “Development of High Conductivity Lead (Pb)Free Conducting Adhesives,” Proc. 46th Electronic Components and Technology Conf., pp. 568–570, Orlando, FL, May 1996. 26. Buchwalter, S. L., and J. D. Gelorme, “Reworkable Encapsulation,” Proc. IEEE International Symposium on Electronics and the Environment, pp. 81–82, Orlando, FL, May 1–3, 1995. 27. Pompao, F. L., A. J. Call, J. T. Coffin, and S. L. Buchwalter, “Reworkable Encapsulation for Flip-Chip Packaging,” Advances in Electronic Packaging,ASME 1995, EEP, 10(2):781–787, 1995. 28. Bergendahl, C. G., et al., “Alternatives to halogenated flame retardants in electronic and electrical products. Results from a conceptual study,” IVF Research Publication 99824, The Swedish Institute of Production Engineering Research, 1999. 29. Conference documentation from the “International Conference on Halogen-free Materials for Electronic and Electrical Products,” 27–28 September 1999, IVF Research Publication 99828, The Swedish Institute of Production Engineering Research, 1999. 30. Bergendahl, C. G., “Electronics Goes Halogen-Free: International Driving Forces and the Availability and Potential of Halogen-Free Alternatives,” Proc. IEEE International Symposium on Electronics and the Environment, pp. 54–58, Orlando, FL, May 1–3, 1995.

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CHAPTER 9

HALOGENATED AND HALOGEN-FREE MATERIALS FOR FLAME RETARDATION

9.1

INTRODUCTION

In many cases some form of flame retardant is needed if polymeric materials are to be used. In modern society, flame retardants save lives by preventing fire initiation and propagation, which in a wider sense is also good for the environment. In electrical and electronic equipment, flame retardants based on bromine are dominant. Some of the brominated flame retardants, such as polybrominated biphenyls (PBBs), have been shown to have serious long-term health and environmental effects. Others, such as hexabromocyclododecane (HBCD), are suspected of having similar effects. Some brominated flame retardants, especially reactive types, may be more or less harmless. Thus, brominated flame retardants constitute a broad group of substances that have a wide range of properties with regard to toxicity and environmental aspects. The acute toxicity of the majority of the brominated flame retardants is low or very low. This is also the case for many of the breakdown products. The important risks of brominated flame retardants are therefore mainly connected to long-term effects. Long-term effects are only relevant if the substance or its breakdown products may bioaccumulate. A substance that is fat soluble and stable and that has a route of exposure to a specific organism may bioaccumulate. Substances that are water soluble or unstable, or that have no route of exposure, will not bioaccumulate. Other factors, such as molecule size and metabolism, may also affect the rate of bioaccumulation. Among the large group of brominated flame retardants, there are substances and breakdown products that have the potential to bioaccumulate, but also many with low or negligible potential to do so. Breakdown products of specific interest due to their high toxicity and potential for bioaccumulation are polybrominated dibenzodioxins (PBDDs) and dibenzofurans (PBDFs). These may form under certain conditions in combustion of some brominated flame retardants. PBDFs may also form in photolysis (i.e., degradation in sunlight) of polybrominated diphenyl ether (PBDE.) PBBs and PBDE will easily form brominated dibenzodioxins in combustion. Several other flame retardants are likely to have a high or moderate potential of forming these compounds. However, there is also a large group for which the potential of forming brominated dibenzodioxins and dibenzofurans will be low or very low. Not even the high-volume brominated flame retardants are well understood in terms of environmental effects. Much needs to be investigated in order to perform risk assessments based on the whole life cycle of these substances.1 9.1 Copyright © 2003 by The McGraw-Hill Companies, Inc. Click here for terms of use.

9.2

CHAPTER NINE

9.2

BROMINATED FLAME RETARDANTS

9.2.1

PRODUCTION ASPECTS

The total use of brominated flame retardants is increasing, and the world production in 1998 was 250,000 to 300,000 tons.2 At least eight types of brominated flame retardants are produced in volumes exceeding 5,000 tons per year: ● ● ● ● ● ● ● ●

Tetrabromobisphenol A (TBBA) PBDEs HBCD Tetrabromophtalimide Tribromophenol and derivatives TBBA-polycarbonate oligomer TBBA-epoxyoligomer Brominated polystyrene

TBBA is by far the most common of the brominated flame retardants. TBBA and TBBA derivatives are used for epoxy and polycarbonate plastics and can be found in practically every electrical and electronic product.A comprehensive survey shows that more than 60 commercial flame retardants may be produced in a year (Table 9.1).

TABLE 9.1 Commercially Available Brominated Flame Retardants Chemical group

Chemical name

CAS number

PBBs

Decabromobiphenyl (deca-BB)

PBDEs

Decabromodiphenyl ether (deca-BDE)

1163-19-5

Octabromodiphenyl ether (octa-BDE)

32536-52-0

Pentabromodiphenyl ether (penta-BDE)

32534-81-9

Substances similar to PBDEs

TBBA and derivatives

13654-09-6

Poly(2,6-dibromophenylene oxide)

69882-11-7

Tetradecabromodiphenoxybenzene

58965-66-5

1,2-bis(2,4,6-tribromophenoxy) ethane

37853-59-1

3,5,3′,5′-tetrabromobisphenol A (TBBA)

79-94-7

TBBA, unspecified

30496-13-0

TBBA-epichlorhydrin oligomer

40039-93-8

TBBA-TBBA-diglycidylether oligomer

70682-74-5

TBBA carbonate oligomer

28906-13-0

TBBA carbonate oligomer, phenoxy end capped

94334-64-2

TBBA carbonate oligomer, 2,4,6-tribromophenol terminated

71342-77-3

TBBA-bisphenol A-phosgene polymer

32844-27-2

TBBA-bis-(2,3-dibromopropyl ether)

21850-44-2

TBBA-bis-(2-hydroxyethyl ether)

4162-45-2

TBBA-bis-(allyl ether)

25327-89-3

TBBA-dimethyl ether

37853-61-5

HALOGENATED AND HALOGEN-FREE MATERIALS FOR FLAME RETARDATION 9.3

TABLE 9.1 Commercially Available Brominated Flame Retardants (Continued) Tetrabromobisphenol S (TBBS) and derivatives

TBBS

39635-79-5

TBBS-bis-(2,3-dibromopropyl ether)

42757-55-1

Bromophenols and derivatives

2,4-dibromophenol

615-58-7

2,4,6-tribromophenol

118-79-6

Pentabromophenol

608-71-9

2,4,6-tribromophenylallyl ether

3278-89-5

Tribromophenylallyl ether, unspecified

26762-91-4

Cycloaliphatic brominated flame retardants

Tetrabromophthalic acid (TBPA) and derivatives

Phthalimides and related substances

Bromine-containing alcohols and polyols

Brominated polystyrene

Brominated alkanes and alkenes

HBCD, unspecified

25637-99-4

1,2,5,9,10-hexabromocyclododecane (HBCD)

3194-55-6

Tetrabromocyclooctane

31454-48-5

1,2-dibromo-4-(1,2 dibromomethyl)-cyclohexane

3322-93-8

TBPA Na salt

25357-79-3

Tetrabromophthalic anhydride

632-79-1

Bis(methyl) tetrabromophtalate

55481-60-2

Bis(2-ethylhexyl) tetrabromophtalate

26040-51-7

2-hydroxy-propyl-2-(2-hydroxy-ethoxy)-ethyl-TBP

20566-35-2

TBPA, glycol, and propylene oxide esters

75790-69-1

N,N′-ethylene-bis-(tetrabromophthalimide)

32588-76-4

Ethylene-bis(5,6-dibromonorbornane-2, 3-dicarboximide)

52907-07-0

2,3-dibromo-2-butene-1,4-diol

3234-02-4

Dibromoneopentyl glycol

3296-90-0

Dibromopropanol

96-13-9

Tribromoneopentyl alcohol

36483-57-5

Polytribromostyrene

57137-10-7

Tribromostyrene

61368-34-1

Dibromostyrene grafted PP

171091-06-8

Polydibromostyrene

31780-26-4

Bromo/chloro paraffins

68955-41-9

Bromo/chloro alpha olefin

82600-56-4

Vinyl bromide

593-60-2

Brominated cyanurate derivatives

Tris-(2,3-dibromopropyl)-isocyanurate

52434-90-9

Bromine- and phosphate-containing flame retardants

Tris(2,4-dibromophenyl) phosphate

49690-63-3

Tris(tribromoneopentyl) phosphate

19186-97-1

Brominated toluenes

Other brominated flame retardants

Chlorinated and brominated phosphate ester

125997-20-8

Pentabromotoluene

87-83-2

Pentabromobenzyl bromide

38521-51-6

1,3-butadiene homopolymer brominated

68441-46-3

Pentabromobenzyl acrylate, monomer

59447-55-1

Pentabromobenzyl acrylate, polymer

59447-57-3

Decabromodiphenyl ethane

61262-53-1

Tribromobisphenyl maleinimide

59789-51-4

9.4

9.2.2

CHAPTER NINE

CLASSIFICATION

Flame retardants can be divided into reactive, additive, and oligomeric flame categories.3,4 9.2.2.1 Reactive Flame Retardants. This category refers to flame retardants that are chemically reacted into the polymer, effectively becoming a part of a polymer molecule. Reactive flame retardants are mainly used in thermoset plastics and resins, especially in epoxy, polyesters, and polyurethanes. The chemical bond between the flame retardant and the polymer makes it difficult for the flame retardant to escape from the polymer in its original form, e.g., in combustion or a waste deposit. However, it is important to keep in mind that chemical reactions are seldom complete, and traces of the original, unreacted flame retardant will therefore usually be found. Reactive flame retardants will affect the physical and chemical properties of the plastic, and it is therefore more technically demanding and more expensive to use reactive flame retardants than additive flame retardants. Reactive flame retardants have no plasticizing effect, and usually small effects on the thermal stability of the polymer. Reactive flame retardants are designed to be highly reactive in order to bond to the polymer. Therefore, they are often irritating, allergenic, or toxic in their free form. However, properly reacted into the polymer matrix, the reactivity will be lost, and they cannot easily leach or bleed out of the material. Consequently, the final polymer will be without risk to handle and use, and also less toxic than additive flame retardants, at least until a fire decomposes the polymeric structure. If the flame retardants escape, some of the breakdown products may have a certain solubility in water. The most common reactive brominated flame retardant, TBBA, is often used in epoxy and polycarbonate plastics. TBBA derivatives are used in polyesters and polyurethanes. 9.2.2.2 Additive Flame Retardants. This category refers to flame retardants that do not react into the polymer molecule.This means that the additive may escape in its original form from the polymer, e.g., in combustion, in sunlight, or in a waste deposit. Additive flame retardants are usually fat soluble, with a low solubility in water. There is a risk that the additive flame retardant may escape in the use phase via surface evaporation. When the surface layer has been depleted of substances that can evaporate, there may be a risk that additional additive flame retardants may be supplied to the surface through migration of material from the bulk of the polymer. The manufacturing cost of polymers containing additive flame retardants is usually lower than that of polymers containing reactive flame retardants. Additive flame retardants are mainly used in thermoplastics, textiles, and rubber, e.g., polyolefins, polyvinyl chloride, polystyrene, polyurethane, polyesters, and polyamides. If they are compatible with the plastic and soluble in the polymer bulk, they act as plasticizers; otherwise, they are considered fillers. They are sometimes volatile or tend to bleed, so the flame retardation of the plastic may gradually be reduced. If they are compatible, the plastic may be transparent, and the mechanical properties are little affected by the flame retardant. If they are not compatible, the plastic will not be transparent, and the chemical properties will be affected. Additive brominated flame retardants usually consist of relatively small molecules that easily migrate through the material, especially when the material melts during fire. Thus, additive flame retardants are often more efficient as flame retardants than reactive flame retardants. The most common types of additive bromi-

HALOGENATED AND HALOGEN-FREE MATERIALS FOR FLAME RETARDATION 9.5

nated flame retardants, PBDEs and HBCD, are used in polymers such as acrylonitrilebutadine-styrene (ABS). 9.2.2.3 Oligomeric Flame Retardants. This category has properties between those of additive and reactive flame retardants. Oligomers are not chemically bound to the polymer matrix. These molecules are bigger and do not leach out as easily as additive flame retardants. The oligomeric molecules are normally too big to efficiently penetrate animal or human body tissue, though they may decompose to smaller molecules in a fire or other degradation processes, e.g., in human tissue. A common type of oligomeric flame retardants are oligomers of TBBA, with or without terminal groups of brominated paraffins. Other common oligomeric flame retardants are oligomers of 2-6-dibromophenol and oligomers of dibromo- and tribromostyrene.

9.2.3

RISK ASSESSMENT

9.2.3.1 PBBs. PBBs are aromatic brominated flame retardants, and are similar to polychlorinated biphenyls (PCBs), differing only in the type of halogen atoms in the chemical structure. However, the bromine atom is much bigger and heavier than the chlorine atom. Bromine is also more loosely attached to carbon than chlorine. This means that the physical, chemical, and toxicological behaviors of PBBs will differ somewhat from those of PCBs. Both PCBs and PBBs are stable compounds, due to so-called resonance stability (which is due to the fact that electrons can easily move around in the whole molecule). Thus, they break down very slowly in nature. PBBs are slightly less stable than PCBs and thus bioaccumulate slightly less readily than PCBs. PBBs are generally less soluble than PCBs in fat.5,6 Neither PCBs nor PBBs are soluble in water. The only isomer of PBBs in current use is deca-BDE, though commercial mixtures may also contain smaller amounts of nona- and octa-BDE. From the structure of PBBs it can be concluded that brominated dibenzofurans and dibenzodioxins can be formed in combustion. This takes place via a small decomposition that forms radicals, followed by a slight oxidation or a rearrangement. Therefore, PBBs readily form brominated dibenzodioxins and dibenzofurans in uncontrolled combustion. There has also been a report that mixed chlorine- and bromine-containing dibenzodioxins and dibenzofurans can be formed from PBBs and chlorine-containing material.7 Bromine can also be substituted with chlorine. Health and environmental effects of mixed bromine- and chlorine-containing dibenzodioxins are not known. PBBs have been shown to induce chronic toxicity and cancer in animals. The acute toxicity is low, but cancer has been induced at a daily dose of merely 0.5 mg/kg body weight. A number of chronic toxic effects have been observed in experimental animals at long-term exposure doses of around 1 mg/kg body weight per day. The long-term toxicities of PCBs and PBBs are similar, though PCBs are slightly more toxic than PBBs. The obvious risk that the effects of PCBs and PBBs may be additive or even multiplicative cannot be neglected. With few exceptions, the cause of death in laboratory animals exposed to halogenated aromatic compounds cannot usually be attributed to a single organ or system. On exposure, the first signs are body weight loss, followed by weakness, debilitation, and finally death. Some authors use the term metabolic death. Other diseases often complicate the picture, and may make it difficult to attribute the body response to a certain substance.

9.6

CHAPTER NINE

9.2.3.2 PBDEs. PBDEs are a group of aromatic brominated flame retardants. At first glance, it may seem that the only difference between PBBs and PBDEs is the introduction of an oxygen atom between the aromatic rings, and that PBBs and PBDEs may show a similar toxicity pattern. However, this is not the case. Several animal tests show clearly that PBDEs are much less toxic than PBBs. This is mainly due to their totally different three-dimensional structures.8 PBDEs are stable compounds, but their stability is significantly lower than that of PCBs and PBBs. The lower stability of PBDEs is due to the oxygen atom between the phenyl rings. The oxygen atom will restrict the mobility of electrons between the two phenyl rings and thereby give a lower stability to the compound compared to PCBs and PBBs. From the structure of PBDEs it can be concluded that brominated dibenzofurans and dibenzodioxins can be formed in combustion. This will take place via a small decomposition that forms radicals, followed by a slight oxidation or a rearrangement. There have also been reports that polybrominated dibenzofurans may form from lower brominated PBDEs via photolysis (sunlight).9 The acute toxicity of PBDEs is low, and only long-term effects are a concern. An example is the oral lethal dose 50 percent (LD50) of penta-BDE, which is high (5.0 to 7.4 g/kg body weight, comparable to the toxicity of ethanol). The biological activity of PBDEs is significantly lower than that of PBBs. Deca-BDE may give rise to tumors in the liver, and may exert negative effects on reproduction. Deca-BDE is listed by the Environmental Protection Agency as a suspected carcinogen and developmental toxicant. Deca-BDE can easily be debrominated in sunlight to lower brominated congeners. Penta- and tetra-BDE are persistent, bioaccumulating, and toxic to aquatic life. Toxic effects are mainly observed in the liver, but thyroid hormone and neurotoxic effects can also occur. An investigation has shown that neonatal exposure to tetraBDE and penta-BDE can induce neurotoxic effects in the adult animal. Both tetraBDE and penta-BDE induced permanent abberations in spontaneous motor behavior, a disruption that also worsened with age. Neonatal exposure to pentaBDE also affected learning and memory functions in the adult animal. Similar neurotoxic effects have been reported with certain types of PCBs.10 9.2.3.3 TBBA. TBBA is usually used as an aromatic brominated flame retardant, either in a reactive form or as an additive oligomer. Thus, assessment of the properties of the TBBA monomer is only of limited value in predicting the environmental properties of the final polymer. TBBA bound in a polymer matrix is several orders of magnitude less dangerous to health and the environment than PBDEs, which in turn are an order of magnitude less dangerous than PBBs. Degradation products of TBBA fixed in a polymer matrix are several orders of magnitude less dangerous to health and the environment than degradation products from PBDEs or PBBs. The formation of brominated dibenzodioxins and dibenzofurans from TBBA takes place only under highly unusual conditions. When TBBA is reacted into a polymer, the properties of the TBBA monomer are no longer relevant to the finished polymer. However, the study of the degradation processes of the monomer TBBA may give some insight into a subset of the chemicals that may be formed in degradation of the TBBA-containing polymer. The TBBA monomer is photolytically decomposed when exposed to ultraviolet light, both in the absence and the presence of hydroxyl radicals. The main product is 2,4,6-tribromophenol. A number of other decomposition products are also found, and some of these have been tentatively identified:11

HALOGENATED AND HALOGEN-FREE MATERIALS FOR FLAME RETARDATION 9.7 ● ● ● ● ●

Di- and tribromobisphenol A Dibromophenol 2,6-dibromo-4-(bromoisopropylene)phenol 2,6-dibromo-4-(dibromoisopropylene)phenol 2,6-dibromo-1,4-dihydroxybenzene

Lower brominated bromophenols are soluble in water and therefore cannot bioaccumulate, but they are toxic. It can be expected that many of the degradation products of the epoxy-TBBA or polycarbonate-TBBA will also be water soluble, and thus have no long-term effects on the environment. TBBA itself has low solubility in water, but good solubility in other polar solvents. Its solubility in aromatic solvents is moderate to low and its solubility in fat is moderate to low.12 Studies of TBBA in sediments have shown that a dimethylated derivate is also found that is not present in the product itself. It is not completely understood how this methylated TBBA is formed, but one hypothesis is that TBBA is methylated by microorganisms in the sediment.13 TBBA, when reacted into a polymer matrix, will not interact to any appreciable degree with biological matter. However, if TBBA has not been reacted properly into the matrix, several superficial health effects may occur, such as sensitization to allergy or photoallergy, skin irritation, eye irritation, etc. It has also been discussed whether hormonal effects may be caused by TBBA in its free form, but no proofs of this have been presented. It seems reasonable for the industry not to use materials with proven negative effects, such as PBBs. It also seems reasonable to investigate possible long-term effects of any suspected chemicals used in products, including an assessment of possible degradation products. Bromine in itself is not an environmental toxin. However, bromine is included in some synthetic substances that are stable and may bioaccumulate or that have the potential to form toxins in combustion. Nonhalogen flame retardants are not yet proven to be better for the environment than halogenated flame retardants. There is little basis, from an environmental perspective, to phase out or prohibit the use of all halogenated flame retardants.14

9.3 TOXICOLOGICAL ASPECTS OF HALOGEN-FREE FLAME RETARDANTS The change from brominated flame retardants to nonhalogenated alternatives has started in the electronics industry. Information about toxicological aspects concerning the involved chemicals is limited, however. This study shows that one nonhalogenated alternative has lower toxicity than the brominated flame retardant TBBA when tested for inhibition of denitrification. The other nonhalogenated alternative showed higher toxicity, but was more soluble in water than TBBA, indicating less risk for bioaccumulation. Denitrification is a bacterial process that is of great importance in soil and water environments.15

9.3.1

FUNDAMENTALS

9.3.1.1 General Trends. The change from brominated flame retardants to nonhalogenated alternatives has started due to environmental concern. One sig-

9.8

CHAPTER NINE

nificant role is played by the discussion about toxicity of the brominated flame retardants. Brominated flame retardants are one of 15 chemicals listed for priority action by the OSPAR Convention (1992), i.e., the Convention for the Protection of the Marine Environment of the Northeast Atlantic, which entered into effect in 1998. The convention’s statement says that discharges, emissions, and losses of hazardous substances (i.e., toxic, persistent, and liable to bioaccumulate) shall be reduced. The third draft of the European Parliament and Council Directive on Waste Electrical and Electronic Equipment was presented in 1999. It requires that member states phase out the use of PBBs and PBDEs by January 1, 2004. The second draft required all halogenated flame retardants to be phased out. 9.3.1.2 Use of Flame Retardants. PCBs have been used as a flame retardant and softener in plastics—mainly cables and rubber—in electronic products, but this use was limited to the 1950s and 1960s. PBBs are assumed to have been used in protection shields and buttons in electronic products. It is unlikely that they have been used in printed circuit boards. PBDEs are used as an additive flame retardant in thermoplastics or rubber. They exist in TV and personal computer housings but seem to have disappeared starting in the mid 1990s. They are also present in some printed circuit boards. PBDEs have been used in higher quantities than PBBs. Commercially, penta-, octa-, and decaBDE are used. Octa- and deca-BDE are the most usual forms in electronics, although penta-BDE is primarily used in paper phenol printed circuit boards. TBBA is presently used in printed circuit boards of FR-4 type. It was the most used brominated flame retardant in the mid-1990s. 9.3.1.3 Toxicity. A substance may have a toxic (harmful) effect on an organism in the environment. This effect may consist of an inhibition of special enzymes, growth, or reproduction, or it may lead to death of the organism. Toxicity may be reduced by adsorption to dead and inert organic and inorganic matter as well as by chemical binding and chelation. TBBA is expected to become associated with soil and sediment, and is not expected to evaporate. The compound is suspected to be nonbiodegradable, to bioaccumulate in organisms, and to be very toxic to water-living organisms. It has a low toxicity to mammals and is not suspected to be mutagenic. The regional risk characterization ratios (EUSES method) indicate that neither the environment nor human beings in the regional area are at risk from TBBA. Available data indicate that TBBA, when used as a reactive flame retardant, can be expected to be at least 10 times less dangerous to mammals than PBBs and PBDEs. 9.3.1.4 Exposure. PBDEs have been detected in white-beaked dolphins (>7 ppm) and harbor seals (>1 ppm) feeding in the North Sea and the Wadden Sea. It has been found in herring, gray seals, and ringed seals along the Swedish coastline of the Baltic Sea. Studies suggest that PBDEs biomagnify, because lower levels were found in fish than in seals. The level of PBDEs in breast milk of native Swedish mothers living in the Stockholm region has increased from less than 0.2 to 4.0 ng/g lipid between 1972 and 1997. The levels are strongly correlated with the fat content of the milk. However, the level of organochlorine compounds (which were banned in the early 1970s) has decreased. In 1997 the level of PCBs was still approximately 350 ng/g lipid. TBBA has a certain solubility in water and can, due to its chemical structure, bond to sulphate and gluconic acid via the hydroxy groups. It can be secreted via the gallbladder and leave the body with feces.

HALOGENATED AND HALOGEN-FREE MATERIALS FOR FLAME RETARDATION 9.9

9.3.1.5 Bromine Industry Activities. A theory launched by the Bromine Science and Environmental Forum (BSEF) argues that some individual cases resulted in high emissions of PBDEs, which would explain the present findings in biota. The cases are oil industry offshore drilling in the North Sea in the early 1990s and coal mining industry (Germany and Sweden) hydraulic fluids during the 1980s. Higher PBDE congeners (octa- and deca-PBDE) are very stable products and do not degrade in the environment. Commercial penta-PBDE is manufactured and used in very low volumes today. Therefore, the quantities of lower PBDE congeners found recently cannot be explained by brominated flame retardants. TBBA has minimal toxicity on acute and repeated dosing. In aquatic systems, toxicity and bioconcentration are dependent on species. The relatively high bioconcentration factor in some species is balanced by rapid elimination. Therefore, there is little potential for bioaccumulation.

9.3.2

DENITRIFICATION

9.3.2.1 Interest in Denitrification. Interest in denitritication exists for several reasons. First, it is a major mechanism of loss of fertilizer nitrogen resulting in decreased efficiency of fertilizer use. Second, it is of great potential application in the removal of nitrogen from high-nitrogen waste materials such as animal residues. Third, denitrification is an important process, contributing N2O to the atmosphere, where it is involved in stratospheric reactions, which result in the depletion of ozone. Fourth, it is the mechanism by which the global nitrogen cycle is balanced. The Swedish government, for example, introduced requirements for nitrogen reduction in wastewater treatment plants in the early 1990s, aiming to reduce the nitrogen discharges to the Baltic and Kattegatt in order to prevent eutrophication.16 9.3.2.2 Definition of Denitrification. Denitrification refers to the dissimilatory reduction, by essentially aerobic bacteria, of one or both of the nitrogen oxides, nitrate (NO3−) and nitrite (NO2−) to nitrogen gas (N2) via the gaseous oxides [nitric oxide (NO) and nitrous oxide (N2O)] as shown in Fig. 9.1. The nitrogen oxides act as terminal electron acceptors in the absence of oxygen. The reduction is catalyzed by the enzyme systems nitrate reductase, nitrite reductase, nitric oxide reductase, and nitrous oxide reductase. Here the inhibition of nitrite reductase is measured, since it is the key enzyme step in denitrification.17

–

nitrate reductase

NO3

NO2–

nitrite reductase

NO N2

N2O nitrous oxide reductase

FIGURE 9.1 Enzymes for denitrification.

nitric oxide reductase

9.10

9.3.3

CHAPTER NINE

BIOASSAY PROCEDURES

9.3.3.1 Bacterium. The ability to denitrify is a property possessed by a diverse category of bacteria. The present toxicity tests are based on a pure culture of a denitrifying bacterium in order to achieve good reproducibility and comparable results. The bacterium is isolated from wastewater treatment sludge. It has been thoroughly characterized and is a member of the Comamonas group.

(a)

(b)

(c)

FIGURE 9.2 Typical results of denitrification inhibition tests: (a) TBBA, (b) OAP, (c) LMB 6129.

HALOGENATED AND HALOGEN-FREE MATERIALS FOR FLAME RETARDATION 9.11

9.3.3.2 Denitrification Inhibition Test. The Comamonas bacteria were grown on nutrient agar plates and kept at 30°C overnight. A bacterial suspension containing 0.01 g (wet mass) of bacteria and 1 ml of nutrient broth was mixed.The substrate, NO2, was added as a NaNO2 solution, to give a final concentration of 150 mg NO2/l. The experiments were carried out in microtiter plates, where each well contains 250 µl in total. None of the flame retardants were completely soluble in water. Several solvents, with decreasing dielectric constants, were tested. TBBA and OAP were dissolved in methanol, while LMB 6129 was dissolved in acetone. All experiments were done as duplicates, and some typical test results are presented in Fig. 9.2. The nitrite consumption rate was followed over time as samples of 5 µl were taken out at 15-min intervals. The nitrite concentrations were measured colorimetrically using a spectrophotometer at a wavelength of 595 nm. This test is a substrate utilization method, which measures the decrease in a substrate (nitrite). A color complex is formed between the unreacted substrate and the reagent. The color weakens as the substrate level decreases. Inhibition of the bacteria is measured as a decrease in the rate at which the substrate is consumed. If the bacteria are inhibited, the rate is lower than for a reference sample.18 9.3.3.3 Water Solution Test. The fact that the flame retardants have poor water solubility made it interesting to perform a long-term solubility test. The flame retardants were placed in water for 1 month, after which the saturated water solution was tested for toxicity. In all other aspects this test was performed like the preceding experiment. 9.3.3.4 Bacterium Growth Test. The pure culture of the denitrfying bacterium was streaked out on a nutrient agar plate. A small amount of each flame retardant was then added in the middle of the plate. The agar plates were incubated overnight at 30°C and then analyzed by visual inspection for bacterial growth. A circle of no growth around the flame retardant indicates inhibition of growth. The bigger the circle, the more toxic the tested compound.

9.4 ENVIRONMENTALLY CONSCIOUS FLAME-RETARDING PLASTICS In electronic products, thermoplastics, which include polycarbonate, acrylonitrilebutadien-styrene copolymer, and polystyrene, are mainly used in housings. Furthermore, thermosetting plastics—mainly epoxy resin compounds consisting of epoxy resin, hardener, and additives—are used as insulating materials for electronic parts. In order to prevent fire from originating in electronic products, these plastics contain flame-retarding additives, most commonly in the form of organic halogen compounds such as brominated aromatic compounds. There is, however, a serious problem with such halogen compounds: during burning, they generate toxic substances that can injure people and contaminate the environment. In addition to the fire-related dangers, the treatment and recycling of the waste materials is also made extremely difficult. While attempts have begun to replace these halogen compounds with safer phosphorus compounds that generate almost no toxic gas, phosphorus compounds themselves are somewhat toxic and can leak out of waste plastics. Furthermore, most phosphorus compounds have the disadvantage of reducing the moldability and humidity resistance of the plastics. New flame-retardant plastics have been developed for electronic products in order to overcome the environmental hazards originating from current plastics containing toxic flame-retarding additives.19

9.12

9.4.1

CHAPTER NINE

FLAME-RETARDANT POLYCARBONATE RESIN

9.4.1.1 New Silicone Flame-Retarding Additive. Silicone compounds have been studied as candidates for safer flame-retarding additives because of their high heat resistance, nontoxicity, and lack of generation of toxic gases during combustion. Previous attempts mainly include studies to improve the flame resistance of plastics as a whole by adding silicones. That is, in plastics, heat resistance networks formed with polydimethylsiloxans (methyl silicones) containing reactive functional groups were studied. Also, addition of cross-linked methyl silicone powders with high heat resistance to plastics was attempted. However, their flame-retardant properties were not good enough because they did not retard flaming on the plastics’ surfaces, where combustion actually occurs. A new flame-retarding silicone compound, as illustrated in Fig. 9.3, was developed for polycarbonate resin. From the comparison presented in Fig. 9.4, the new silicone shows far higher flame-retardant effectiveness for polycarbonate resin than previous silicones and can perfectly replace the current flame-retarding additives including halogen (bromine) compounds and phosphorus compounds. The new silicone has a special structure, which is a branched chain containing aromatic groups and nonreactive terminals. It FIGURE 9.3 Structure of a new flame-retarding silicone compound for polycarbonate resin. incorporates a new flame-retarding mechanism, as shown in Fig. 9.5: the silicone finely disperses in the polycarbonate resin, moves from inside to the polycarbonate’s surface during combustion, and then forms a flame-resistant barrier on the surface. As shown in Fig. 9.6, in polycarbonate resin, dispersion of the new silicone is extremely fine. This can be mainly credited to its high solubility in the polycarbonate resin, which is due to the aromatic groups in the chain. Methyl silicone (branch type and linear type) showed low solubility in the polycarbonate resin due to the lack of aromatic groups. Branch silicone derivatives with reactive groups in the terminals, whether containing aromatic groups in the chain or not, showed poor dispersion because of their gelation during mixing with the polycarbonate resin.20 Figure 9.7 indicates the concentration (ratio of Si to C) of the new silicone at the surface of the molded polycarbonate resin before and after combustion, and shows movement of the silicone from the inside of the polycarbonate resin to its surface during combustion. This movement can result from differences in solubility and viscosity between the silicone and the polycarbonate resin at high temperatures during burning. Figure 9.8 shows the flame resistance of silicone derivatives themselves. The new silicone showed far higher flame resistance than the polycarbonate resin alone or with methyl silicones. This is mainly due to its aromatic groups, which can form condensed aromatic compounds known as precursors to highly flame-resistant char (carbonaceous substances), and also due to its branch structure, which shows higher heat resistance than a linear structure. Therefore, the new silicone can form a flameresistant barrier after moving to the polycarbonate’s surface during combustion. We

HALOGENATED AND HALOGEN-FREE MATERIALS FOR FLAME RETARDATION 9.13

FIGURE 9.4 Flame-retardant effectiveness of silicones for polycarbonate resin.

believe that during combustion the new silicone and the polycarbonate synergistically form a highly flame-retardant complex substance on the polycarbonate’s surface because the polycarbonate alone can form similar condensed aromatic compounds on the surface during combustion. 9.4.1.2 General Properties of the Polycarbonate Resin with the New Silicone. The polycarbonate resin containing the new silicone achieved far higher safety

FIGURE 9.5 Flame-retarding mechanism of new silicone for polycarbonate resin.

9.14

CHAPTER NINE

FIGURE 9.6 Dispersion of silicones in polycarbonate resin.

FIGURE 9.7 Movement of new silicone to the surface of polycarbonate resin during combustion.

HALOGENATED AND HALOGEN-FREE MATERIALS FOR FLAME RETARDATION 9.15

FIGURE 9.8 Flame resistance of silicones.

TABLE 9.2 Properties of Polycarbonate Resin with Flame Retardants

Properties Impact strength (kgf/cm/cm, 1⁄8 in)

With TBBA

With phenyl phosphorus ester

With new silicone

12

4

45

Flexural strength (kgf/cm2)

980

1080

920

Flexural modulus (kgf/mm2)

230

270

230

134

106

133

22

47

22

V-0

V-0

V-0

Impact strength (kgf/cm/cm)

11

4

38

Flame resistance (UL-94, 1⁄16 in)

V-1

V-0

V-0

HDT (°C) Melt flow (g/10 min) Flame resistance (UL-94, 1⁄16 in) Recycling properties (100%)*

* Reextruding and retabulating.

9.16

CHAPTER NINE

FIGURE 9.9 Self-extinguishing network formed by new epoxy resin compound.

FIGURE 9.10 Flame resistance of epoxy resin compounds.

HALOGENATED AND HALOGEN-FREE MATERIALS FOR FLAME RETARDATION 9.17

when burned and when disposed of than current plastics containing halogen or phosphorus-type flame-retarding additives. The polycarbonate resin meets a high flame-retarding standard (UL 94V-0) and has other good important properties, such as strength, moldability (contamination of mold, melt flow characteristic in mold), surface hardness, and heat resistance (Table 9.2). In particular, the impact strength is better than that of polycarbonate containing a bromine compound and a phosphorus compound and the heat resistance is higher than that with phosphorus compounds. Furthermore, these characteristics are maintained when the product is recycled. NEC Corporation has started to use the new plastic in housings of liquid crystal display monitors and projectors, and also in battery packs for notebook computers.21

FIGURE 9.11 Cross-section of molded epoxy resin compounds.

9.18

9.4.2

CHAPTER NINE

SELF-EXTINGUISHING EPOXY RESIN COMPOUND

A new self-extinguishing epoxy resin compound was developed as a flame retardant for electronic products. It contains no toxic flame-retarding additives and can be used as a high-quality molding resin for electronic parts. As illustrated in Fig. 9.9, the compound contains an aromatic epoxy resin and a phenol derivative hardener, both of which contain multiaromatic groups in their main chains and also additives (silica particle filler, releasing agent, etc). From the comparison presented in Fig. 9.10, the resin compound shows far higher flame retardation than current epoxy resin compounds because of its new flame-retarding mechanism: the formation of a foam layer on the resin surface during combustion (see Fig. 9.11), which can retard oxygen

TABLE 9.3 Characteristics of Newly Developed Molding Resin Newly developed molding resin

Characteristics Composition

Flame-retarding additive

None Silica >80%

Filler Specific gravity Water resistance Strength

Heat resistance Insulation Flow behavior Flame retardance

3

(g/cm ) Water absorption ratio (%) (boiling for 24 h) Flexural strength at room temperature (N/mm2) Flexural modulus at room temperature (N/mm2) Flexural strength at 240°C (N/mm2) Flexural modulus at 240°C (N/mm2) Glass transition temperature (°C) Volume resistance (×1011 Ω/cm) at 150°C Spiral flow length (cm) UL-94 test (1.6 mmt) Humidity treatment time (h) before soldering

Resistance to soldering heat (number of failures in 6 packages)

1.96 0.17 172 21,360 15.9 480 132 104 106 V-0 96

168

Current molding resin* Bromine compound and Sb2O3 Silica >80% 1.91 0.22 167 18,130 19.6 510 145 42 85 V-0 96

168

Delamination between chip and compound 0 S 0 S Package cracking 0 0 0 0 80-pin QFP (package size = 20 × 14 × 2 mm, silicone chip size = 9.0 × 9.0 × 0.35 mm) 85°C, 85% RH, IR at 240°C for 10 s (3 times), S figure: small delamination PCT time (h)

Pressure cooker bias test (number of failures in 15 packages)

Pressure cooker test after IR reflow (number of failures in 6 packages)

120 0 0 160 0 2 200 0 2 240 1 — 16-pin DIP (package size = 19 × 5 × 4 mm, silicone chip size = 3.0 × 3.5 × 0.35 mm) 125°C, 100% RH, applied voltage = 20 V PCT time (h)

204 318 514

0 0 0

0 0 0

80-pin QFP (package size = 20 × 14 × 2 mm, silicone chip size = 3.0 × 3.5 × 0.35 mm) 85°C, 85% RH for 48 h and IR at 240°C for 10 s, → 121°C, 100% RH Thermal cycle test (number of failure in 12 packages)

700 cycles 0 0 80-pin QFP (package size = 20 × 14 × 2 mm, silicone chip size = 9.0 × 9.0 × 0.35 mm) −65 ∼ +150°C for 10 min

* Biphenyl-type epoxy resin and phenol resin hardener. QFP, quad flat pack; IR, infrared; PCT, pressure cooker test; DIP, dual inline package; RH, relative humidity.

HALOGENATED AND HALOGEN-FREE MATERIALS FOR FLAME RETARDATION 9.19

passage and heat transfer. After a curing reaction between the epoxy resin and the hardener, the resin compound forms a special network structure with a low crosslink density and high resistance to thermal decomposition due to the multiaromatic groups in the main chain. Because of the compound’s elasticity at high temperature resulting from this low cross-link density, gaslike substances generated from the inside of the resin compound by thermal degradation during combustion form the surface material into a foam layer. Furthermore, the higher resistance to thermal decomposition plays an important role in the stability of the foam layer during combustion. The epoxy resin compound has good characteristics as a high-quality molding resin as well as high flame resistance (Table 9.3). In fact, its resistance to solder heating and thermal cycles is as high as that for current high-quality molding resins containing bromine-type flame-retarding additives used for LSIs. Its resistance to humidity is even better. Other general properties, such as insulation, heat resistance, strength, and moldability are good enough for practical use.22 Environmentally friendly flame-retardant plastics containing no toxic flameretarding additives such as halogen (bromine) compounds and phosphorus compounds have been developed for electronic products. A polycarbonate resin containing a new silicone flame-retarding additive has been developed for use in housings. Furthermore, a self-extinguishing epoxy resin compound containing no flame-retarding additives was developed as a high-quality molding resin for electronic parts. These plastics show good general properties as well as high flame retardation.

REFERENCES 1. Hedemalm, P., A. Eklund, R. Bloom, and J. Haggstrom, “Brominated Flame Retardants— An Overview of Toxicology and Industrial Aspects,” Proc. IEEE International Symposium on Electronics and the Environment, pp. 203–208, San Francisco, CA, May 8–10, 2000. 2. Troitzsch, J. H., International Plastics Flammability Handbook: Principles, Regulations,Testing and Approval, 2d ed., Munich, Germany: Hanser, 1990. 3. IPCS International Programme on Chemical Safety: Environmental Health Criteria 152: “Polybrominated Biphenyls,” World Health Organization, Geneva, 1994. 4. IPCS International Programme on Chemical Safety: Environmental Health Criteria 140: “Polychlorinated Biphenyls and Terphenyls,” World Health Organization, Geneva, 1993. 5. IPCS International Programme on Chemical Safety: Environmental Health Criteria 162: “Brominated Diphenyl Ethers,” World Health Organization, Geneva, 1994. 6. Watanabe, I., and R. Satsukawa, “Formation of Brominated Dibenzofurans from the Photolysis of Flame Retardant Decabromodiphenyl Ether in Hexane Solution by UV and Sunlight,” Bull. Environ. Cona. Toxicol., 39, 953–959, 1987. 7. Eriksson, P., E. Jakobsson, and A. Fredriksson, Organohalogen Compounds, 35:375–377, 1998. 8. Eriksson, J., and E. Iakobsson, “Decomposition of Tetrabromobisphenol A in Presence of UV Light and Hydroxyl Radicals,” Organohalogen Compounds, 35:419–422, 1998. 9. Flick, E. W., Plastics Additives, an Industrial Guide, 2d ed., Noyes Publications, 1993. 10. Segerberg, T., L. Gumaelius, H. Hessle, and E. Ostensson, “Toxicological Aspects of Halogen-Free Flame Retardants Based on Denitrification Inhibition Tests,” Proc. IEEE International Symposium on Electronics and the Environment, pp. 69–74, San Francisco, CA May 8–10, 2000.

9.20

CHAPTER NINE

11. Grunditz, C., “Bioassays for the Determination of Nitrification Inhibition,” Royal Institute of Technology, Department of Biotechnology, 1999. 12. Gumaelius, L., and G. Dalhammar, “Development of a Biosensor for Denitrification Inhibition,” Royal Institute of Technology, Department of Biotechnology, 1998. [in Swedish] 13. Hardy, M. L., “Tetrabromobisphenol A: Toxicology and Environmental Effects Evaluation by the World Health Organization under the International Programme on Chemical Safety,” CMA BFRIP Brominated Flame Retardants Workshop, 1995. 14. Hessle, H., and E. Ostensson, “Toxicological Characterization of Laminate Flame Retardancy Systems,” Royal Institute of Technology, Engineers School, 1999. 15. Noren, K., and D. Meironyte, “Contaminants in Swedish Human Milk—Decreasing Levels of Organochlorine and Increasing Levels of Organobromine Compounds,” Dioxin ’98, Organohalogen Compounds, 38:1–4, 1998. 16. Camino, G., and L. Costa, Polymer Degradation and Stability, 20:271–294, 1988. 17. Cullis, C. F., Journal of Analytical and Pyrolysis, 11:451–463, 1987. 18. Dumler, R., H. Thoma, and O. Hutzinger, Chemosphere, 19(1–6):305–308, 1989. 19. Luijk, P., H.A.J. Govers, G. B. Eijkel, and J. J. Boon, Journal of Applied Pyrolysis, 20:303–319, 1991. 20. Iji, M., S. Serizawa, and Y. Kiuchi, “New Environmentally Conscious Flame-Retarding Plastics for Electronics Products,” Proceedings of the First International Symposium on Environmentally Conscious Design and Inverse Manufacturing, pp. 245–249, 1999. 21. Iji, M., and S. Serizawa, Polymers for Advanced Technologies, 9:1–8, 1998. 22. Bush, B., Plastics Engineering, 42(2):29–32, 1986.

CHAPTER 10

FABRICATION OF ENVIRONMENTALLY FRIENDLY PCB 10.1

INTRODUCTION

The integration of factors concerning environmental impact during manufacturing, use, and disposition of product is an emerging issue in design of electronics. The drivers for this in electronics include certification standards such as ISO 14000 and British Standard 7750; ecolabeling programs such as Energy Star, Blue Angel, and TCO; increasing internalization of waste mitigation and disposal costs into the product cost; and an increasing need for environmental accountability in global supply networks. One important aspect of product design for the environment (DfE) in electronics is consideration of environmental impact during the manufacturing stage. In particular, the fabrication and assembly stages of printed circuit board (PCB) are significant contributors to life cycle environmental impacts. Process models can be used as an analytical tool to develop environmental performance indicators for products. These process models, while modeling the manufacturing waste streams, also implicitly model the product parameters and can be used conveniently for product design optimization.1 In the following sections, techniques based on process modeling and product optimization will be introduced. These techniques may not only be implemented in PCB assembly design to minimize environmental impact, but also can be easily applied to other product optimization problems. First the process models for PCB fabrication are briefly described. A waste stream weighting scheme, which is very useful for comparing two or more dissimilar waste streams, is then introduced. Subsequently an optimization algorithm will be discussed for seeking a balance between the various board design parameters, such as board area, number of layers, and number of boards on a panel, in order to come up with the physical board design with the minimum manufacturing waste per board. A case study will be presented to demonstrate the implementation of these models and principles. Furthermore, specific issues such as how to incorporate various design constraints and how the analyses fit into the overall life cycle assessment of a product will be reviewed.

10.2 10.2.1

PCB DfE PROCESS MODELING

Manufacturing a PCB assembly consists of three parts: (1) semiconductor fabrication, (2) electronic packaging, and (3) bare-board manufacturing and component assembly. Despite a tremendous flexibility in process selection in semiconductor 10.1 Copyright © 2003 by The McGraw-Hill Companies, Inc. Click here for terms of use.

10.2

CHAPTER TEN

manufacturing, there is somewhat limited room for product optimization to achieve better environmental results. In electronic packaging, one can choose from a wide variety of packages. However, in most cases, the functional requirements very quickly narrow the choice to a few types. For bare-board fabrication, about 7 percent of the materials used actually go into the product and the remaining 93 percent are emitted as process waste.2 Thus, minimizing the process waste is the most logical way to minimize the environmental impact of circuit boards. The process steps include laminate core fabrication, resist coating, exposure, development, copper etching, resist stripping, oxide treatment, lamination, drilling, desmearing, copper plating, and solder masking, as shown in Fig. 10.1. In general, the thermochemical and thermomechanical behaviors of various process steps involved in fabrication may be modeled to predict the waste streams. For instance, the waste streams from the etching operation can be modeled in terms of the board parameters as mCu = ρCu (1 − KCu) Acore tCu

(10.1)

metc = mCu (MCuCl 2 /MCu)

(10.2)

mCu2Cl2 = mCu (MCu 2 Cl 2 /MCu)

(10.3)

where m represents the mass, M represents the molecular weight, A represents the area, t represents the thickness, and K represents the fraction of copper retained on the board after etching for a particular layer. Similar models can be formulated for component assembly operations such as stenciling, component placement, reflow, wave soldering, and board cleaning.3,4 These models must be validated using the actual waste stream data collected at the fabrication site. Figure 10.2 shows the model estimates for the reflow and wave-soldering processes.

10.2.2

HEALTH HAZARD ASSESSMENT

It is crucial to be able to compare the raw mass of waste streams. This can be achieved using some kind of health hazard assessment method such as the health hazard scoring system.5 This system computes a scalar weighting factor called the health hazard score (HHS), which is calculated for a particular waste stream using its health hazard potential data (carcinogenicity, reactivity, flammability, dermal irritability, inhalation toxicity, oral toxicity, and eye irritation), its phase (solid, solid particulate, liquid, vapor, or aerosol), and the safety practices on site. This number essentially brings two dissimilar waste streams to the same level of hazard for the purpose of mutual comparison. The categorical hazard score H is determined based on information from various sources such as the American Conference of Governmental and Industrial Hygienists threshold limit value data and the Registry of Toxic Effects of Chemical Substances database. To introduce phase effects with chemical hazard subscores, a phase matrix P can be constructed to partition the hazard share for each factor among the different physical phases using the Kepner-Tregoe method, where each coefficient is assigned a fractional value from 0 to 1. The final factor to consider is site modeling. Since each site in which manufacturing occurs is different in terms of facilities design, equipment, and work practices, these site-specific factors have a significant influence on waste stream environmental impact. However, these factors are largely qualitative in nature (e.g., wearing pro-

10.3 FIGURE 10.1 Typical process steps in PCB fabrication.

10.4 FIGURE 10.2 Process model estimates for reflow and wave-soldering processes: (a) solder paste waste, (b) dross waste.

FABRICATION OF ENVIRONMENTALLY FRIENDLY PCB

10.5

tective garments, continuous monitoring of the process). A major challenge, therefore, is to reduce qualitative site information to a quantitative form, which can be evaluated along with chemical hazards and phase. One approach is to construct a set of pairwise evaluations comparing toxicity (oral and inhaled), carcinogenesis, irritation (dermal and eye), reactivity, and flammability using the analytic hierarchy process (AHP), a method that ranks pairwise comparisons between various factors. Successive comparisons set up a matrix. Initially, a subjective set of priorities is elicited from the user regarding the different factors (such as toxicity, reactivity, and flammability). These priorities then are placed into an AHP matrix. The schematic of the HHS method is shown in Fig. 10.3.

FIGURE 10.3 HHS method.

Examples of categorical hazard scores are shown in Table 10.1. A sample phase matrix is shown in Table 10.2, and a sample AHP matrix is shown in Table 10.3. Based on this matrix, an l-x-7 fate and transport column vector F can be calculated. A rank value is determined with the following equation: Rl =

k

冢 j冱= l X 冣

l/k

ij

(10.4)

where Xij are the elements of the k-x-k prioritization matrix X. Here, k = 7, the number of effects of interest. The elements of F then are determined by a simple normalization: k

F (i) = Ri /冱 Ri, i=l

i = l,......k

(10.5)

For the matrix in Table 10.3, the F vector is F = [0.01 0.05 0.07 0.43 0.03 0.21 0.20] T

(10.6)

The environmental impact index, or HHS for the ith waste stream and the jth phase (HHSij) can be calculated as HHSij = HiPij ⋅ F

(10.7)

10.6

CHAPTER TEN

where Hi is the l-x-7 vector of the raw score [0, I, E,......, F] for the ith waste stream, Pij is the transposition of the jth column of the phase matrix for the ith waste stream, and HiPij is an l-x-7 vector equal to the element-by-element product of Hi and Pij. Once derived, an overall HHS index can be written for chemical species with multiphase pathways in terms of the mass fractions of the different phases as HHSi = 冱 HHSijMj /冱 Mj j

(10.8)

j

TABLE 10.1 Score Hi for Reactivity Score

Reacts with

9

Metals, oxidizing agents, acids, bases, moist air, water, etc.

8

Metals, moist air

7

Metals

6

Moist air

4–5

Oxidizing agents

1–3

Acids or bases

0

No known substance (inert)

TABLE 10.2 Sample Phase Matrix Phase Solid

Liquid

Aerosol

Vapor

Oral toxicity

Hazard

0.3

0.4

0

0

Solid particles

Inhalation toxicity

0

0

0.5

0.3

0.2

Eye irritation

0

0

0.4

0.4

0.2

0.3

Dermal irritation

0.2

0.5

0

0

0.3

Carcinogenicity

0

0.3

0.3

0.3

0.1

Reactivity

0

0.5

0.2

0.2

0.1

Flammability

0.1

0.6

0.1

0.1

0.1

TABLE 10.3 Sample AHP Matrix for Site-Specific Prioritization

O I E X= D C R F

冤

O I .1 1⁄5 5 1 10 1 30 10 2 1⁄2 20 5 20 5

E ⁄10 1 1 6 1 ⁄2 4 3

1

D C ⁄30 1⁄2 1 ⁄10 2 1 2 ⁄6 1 15 1 1 ⁄15 1 5 ⁄2 1 8 ⁄3 1

R ⁄20 1 ⁄5 1 ⁄4 2 1 ⁄5 1 1

1

F ⁄20 1 ⁄5 1 ⁄3 3 1 ⁄8 1 1

1

冥

FABRICATION OF ENVIRONMENTALLY FRIENDLY PCB

10.2.3

10.7

BOARD OPTIMIZATION

10.2.3.1 Deciding the Variables of the Problem. Once equipped with a set of process models and hazard assessments, we can analyze a particular board design. Keeping the functionality of the board untouched, we can change its physical design and observe the change in the waste stream generation impact. First, we intuitively decide which factors will have the most significant impact on the waste stream. For circuit boards, we observe from the process models that the number of layers, number of boards tiled on a single panel, and board area are the key design parameters. We cannot vary the number of pins or components at this point because that will hamper the functionality of the board and our focus is not on devices on the board. 10.2.3.2 Deriving Interparameter Relationships. Changing certain design parameters affects other design parameters. For example, changing the dimensions of the board requires recomputing the copper fraction for every layer. Thus we need to derive relationships between various parameters. These relationships serve as the equality constraints of the optimization problem. In the following example of board design, there are three major formulas to be derived. Copper Fraction of the Signal Layers. In a previous study,6 the relationship for the average length of copper traces on a board has been derived as 兹A 苶r 2 苶 Lavg = (A + 1) ᎏᎏ s /N苶1) l(As + 苶] 6(n − 1)兹A 苶s [1 + 兹2A

(10.9)

where As is the aspect ratio, Ar is the routable area of the board, Nl is the total number of component pins, and n is the average net size. From this formula, the copper fraction of signal layers can be written as KCu−board = (LavgNintttrace)/Ab

(10.10)

where Nint = Nl (n − 1)/n. Number of Boards per Panel. Boards can be arranged on a rectangular panel in two possible orientations, as shown in Fig. 10.4. If we denote the length and breadth of the board and panel by Lb, Wb, Lp, and Wp, respectively, then the number of boards for the two orientations may be expressed as follows: Orientation 1:

Nb = Int(Lp/Wb) Int(Wp/Lb) + Int(Lp/Lb) Nb = Int(Lp/Wb) Int(Wp/Lb)

(if GL > Wb) (otherwise)

(10.11)

Orientation 2:

Nb = Int(Lp/Lb) Int(Wp/Wb) + Int(Wp/Lb) Nb = Int(Lp/Lb) Int(Wp/Wb)

(if GW > Wb) (otherwise)

(10.12)

We must calculate the number of boards per panel using these formulas and choose the orientation that gives the maximum number of boards per panel. In this way more of the material will go into the product and less into the manufacturing waste. Total Number of Signal Layers. The number of signal layers can be estimated given the routable board area Ar and the number of “reference components” Nref using the density approach.6 The number of reference components is equivalent to the number of components when all components are weighted with reference to a

10.8

CHAPTER TEN

FIGURE 10.4 Layout of two panels: (a) orientation 1, (b) orientation 2.

14-pin DIP component as one unit. The categorical functional dependence is given in Table 10.4. 10.2.3.3 Optimization. Once we derive the process models and the preceding relationships, we can follow a procedure like the one depicted in Fig. 10.5 to optimize the board design parameters. The results of such an optimization are shown in Fig. 10.6. The plot shows the weighted mass of the waste streams on a per-board basis as a function of the board dimensions. From this plot, we can choose the dimensions of the board corresponding to the minimum waste. We also can observe the effect of relaxing a constraint or imposing an additional constraint on the optimization problem. These constraints can easily be imposed or removed during waste stream calculation from process models. Several useful conclusions can be drawn from these plots: ●

●

●

The minimum waste does not necessarily occur for the smallest or thinnest (i.e., fewest layers) board size. A large variation (more than 100 percent in the plots shown) in the amount of waste per board occurs as the dimensions and the number of layers of the board are varied. Thus the scope for waste minimization through design optimization is tremendous. The choice of panels also makes a difference in waste generation. Thus, whenever a variety of panels is available, we must calculate which to choose.

TABLE 10.4 Signal Layer Estimation Ar /Nref (in2/14-pin DIP)

Ns-layers

Above 1.0

2

0.8–1.0

2

0.6–0.8

4

0.42–0.6

6

0.35–0.42

8

0.2–0.35

10

0.0–0.2

10+

10.9 FIGURE 10.5 Board design optimization procedure.

10.10 FIGURE 10.6 Waste mass as a function of board dimensions for two different panel sizes: (a) 18 × 24 in, (b) 21 × 27 in.

FABRICATION OF ENVIRONMENTALLY FRIENDLY PCB

10.2.4

10.11

LIFE CYCLE ASSESSMENT (LCA)

A bare board is only one component of an overall PCB assembly. Thus, it is important to perform a similar optimization analysis on every component of the assembly. Also, design variation in one component sometimes necessitates design variation in another. For example, making the board smaller may allow the use of flip chip ball grid array components, which may not be as environmentally benign as quad flat packages because of the potential worker exposure hazard in the solder-bumping process. Therefore, the optimization procedure eventually can be extended to incorporate selection of component packaging. Electronic packaging presents discrete choices of package types. We can formulate the process models for each package type as a function of a functional parameter, such as the pin count. For semiconductor or die manufacturing, environmental issues are largely a function of waste mitigation in the manufacturing process; currently, limited opportunity is available to effect environmental decisions through design changes. However, a change in technology brings about major changes in process steps, chemicals used, and process mechanics and a resulting significant change in process waste. Therefore, process models for semiconductor manufacturing must predict the waste per die as a function of the yield (which is a function of die size and wafer size) and the technology used. So far, we have examined mainly design optimization of a product for minimum process waste. One aspect neglected in this analysis is the amount of material going into the product itself and its eventual fate. Although manufacturing wastes represent the dominant life cycle impact for PCBs, we cannot neglect the environmental impacts of use and disposition phases of the life cycle for other components of a circuit board or computer. LCA examines a product from the time its raw material is mined to the time the product is disposed back into the environment. It looks at material and energy flows in mining, material refinement, manufacturing, use, consumption, and disposal (which includes recycling, reuse, remanufacturing, incineration, deposit in a landfill, etc.) associated with a particular product. While LCA conceptually is straightforward, to implement such analyses requires a great deal of data that often are unavailable or of low quality. LCA is extremely data intensive, and while results can be found for some comparisons, often the data are so poor that little can be learned from them. Furthermore, few have agreed on how the multiple health and environmental impacts of a product’s life cycle can be compared to those of another product, making comparisons between products difficult. LCA is ultimately an attempt to draw a quantitative connection between the existence of a product (its manufacture, use, and disposition) and environmental impact. DfE is an attempt to incorporate this information (i.e., connections, analyses) to minimize environmental impacts of design decisions. Just as more traditional engineering models help designers predict the performance of their designs in terms of speed, weight, energy consumption, and other more standard measures of performance, LCA is a model that predicts for designers the environmental performance of their designs.

10.3

IMPLEMENTING GREEN PCB MANUFACTURING

The U.S. PCB industry has significantly improved its environmental performance over the past 20 years. This industry, which has the potential to be a major polluter,

10.12

CHAPTER TEN

has consciously altered its processes and practices to minimize its toxic output. While PCB manufacturers once viewed the effects of environmental regulations as a threat to their long-term growth, they have reversed this position. One of the best examples of this remarkable turnaround is how they actively became partners with regulatory agency programs such as the U.S. Environmental Protection Agency (EPA) Design for the Environment program. The industry continues to work with these agencies to assess the performance, cost, and environmental impact of alternatives to traditional PCB manufacturing methods.7 Despite the great advances within the PCB industry, environmentally conscious designers can further reduce the impact of the products they design by being aware of the consequences of design on processes and material. The concept of connecting design decisions to environmental consequences further down the supply chain is referred to as DfE. It means, for example, that requiring a solder surface on finished PCBs to be shipped to an assembler has more environmental consequences than allowing the PCB manufacturer to use an alternative finish such as Sn. The proposed concept and the procedure for making such circuit boards are further reviewed in the subsequent sections.

10.3.1

BASIC PROCESSES

There are several types of PCBs, depending on use, operational environment, and cost constraints. The simplest type of board is single-sided, with no holes for connections to other layers; these typically are made out of inexpensive laminate material and used for consumer products where there is little electronic sophistication and cost is the driver. A copper-clad dielectric is coated with a resist material, which is patterned to protect the areas where circuitry will be formed and the remaining copper etched away. This is referred to as the print and etch process. The chief waste products are etchant, consumed resist, and scrap or excess board material. The dielectric material can be either a rigid plastic (typically paper phenolic or glass/epoxy) or flexible plastic (e.g., certain nylons or polyesters). The second type of board is double sided, with plated through-holes. This board also is in common use. Because of the need to plate the dielectric on the walls of the holes connecting both sides, either electroless copper or, more recently, direct plating chemistries are used to make the surface conductive. Once the surface is conductive, the walls are typically plated using standard electroplating copper baths. This means that the surface of the board also is plated either as a sheet of copper (panel plating) or as resist-defined circuit areas (pattern plating). In either case, the copper between circuit lines must be removed by etching. In pattern plating, of course, the background copper is much thinner than the circuit lines. The dielectric again can be rigid or flexible. The most sophisticated boards, requiring complicated circuit routing to accommodate interconnecting integrated circuit chips, are usually multilayer boards. These boards traditionally have been manufactured by building innerlayers using the print and etch process. These innerlayers then are stacked in register and laminated together with partially polymerized dielectric between the layers along with outer layers of plain copper sheet. The outer layer is then typically drilled with throughholes to connect the various layers. The outer layers are either panel or pattern plated after the hole walls are coated using electroless or direct metallization. Again the dielectric can be rigid, flexible, or a combination of the two. The various processes used to make these types of boards have undergone changes during the past few years, the most significant of which are listed in the next

FABRICATION OF ENVIRONMENTALLY FRIENDLY PCB

10.13

section. All these changes have had a significant effect in reducing the environmental impact of this industry.

10.3.2

PROCESS MODIFICATIONS

10.3.2.1 Switch from Chromic-Based Etchants. Beginning in the late 1970s and continuing through the early 1990s, alternatives were developed to replace chromicbased etchants. This happened because chromic-based etchants were not easy to regenerate, etched at a slow rate, and had a low limit of dissolved copper.8 They were also being regulated by environmental and health and safety agencies due to the hexavalent species, which was considered carcinogenic. The copper chloride and ammoniacal etchants, which have now replaced chromic etchants in the PCB industry, overcame all these disadvantages and were cheaper. The changes also significantly reduced the volume of etchant used by the industry and, therefore, its generation of spent etchant. Unlike chromic-based etchants, spent ammoniacal and cupric chloride etchants can be regenerated, reclaimed, or reused in other manufacturing operations.9 10.3.2.2 Elimination of Chlorinated Solvents. With the invention of solventdevelopable dry film photoresists in the late 1960s, the PCB industry used significant amounts of trichloroethane and methylene chloride to develop and strip them. In the late 1970s and early 1980s, aqueous and semiaqueous processable resists were developed, using either bicarbonate/hydroxide or butyl carbitol/cellosolve as developers or strippers. Trichloroethane continued to be used as a cleaning solvent until 1990, when it was found to contribute to stratospheric ozone depletion. During the ensuing decade, it was virtually eliminated from use when the EPA adopted a phaseout program for all ozone-depleting substances in Title VI of the Clean Air Act amendments.10 Other cleaning solvents categorized as ozone-depleting substances, for example HCFC-141(b), also were eliminated when the industry switched to alternatives, such as citrus-based terpenes and aqueous-based cleaners. 10.3.2.3 Improved Process Control. Some of the industry’s most successful environmental improvements include the widespread adoption of simple housekeeping measures that minimize waste generation and improve process control. Examples of such improvements include taking steps to reduce chemical loss, increase process bath life, and recover materials that otherwise would be disposed.11 These steps often included better bath control through improved use of sensors and control equipment. In addition, total quality management (TQM) systems can produce improved environmental as well as economic results. Adoption of a total quality management program can reduce facility scrap rates and result in process changes that reduce chemical losses or conserve process baths. 10.3.2.4 Reduced Use of Sn-Pb as Etch Resist. For many years, electroplated Sn-Pb was the most common PCB metal etch resist used in pattern plating. Its widespread use also is due to the requirement of many upstream customers to be able to use reflowed Sn or Pb as the PCB surface finish of choice. The industry began to switch to Pb-free etch metal resists due to technical constraints associated with Sn-Pb etch resists. In addition, the industry saw widespread use of hot-air solder leveling (HASL) as the predominant PCB surface finish prior to adding components. Typically, any Sn-Pb plating had to be stripped off prior to the HASL process,

10.14

CHAPTER TEN

thereby generating a Pb-containing hazardous waste. Facilities that switched to HASL began to look for an etch resist that, when stripped, would not be an environmental hazard. Sn was the most logical alternative. As an etch resist, Sn performs just as well as Sn-Pb; however, Sn is not considered a hazardous waste and does not represent the worker safety issues associated with Pb.12 10.3.2.5 Increased Use of an Alternative Metal-Bonding Surface Finish. To be effective, a PCB surface finish must prevent copper oxidization, facilitate solderability, and prevent defects during assembly. For many years, the reflowed Sn-Pb surface finish, which applies Sn-Pb solder to all exposed PCB traces, was the predominant PCB surface finish. Currently, HASL, which applies Sn-Pb solder only to PCB through holes and pads, has significantly reduced the industry’s use of Pb. Despite its advantages, HASL still poses several drawbacks; for instance, unless its waste solder dross is recycled, it must be managed as a hazardous waste. HASL also results in domed solder surfaces, whereas new and more complex packaging designs require flat surfaces.13 Among its other problems, HASL does not effectively cover the electroless nickel/immersion gold process, which has grown in use due to the ease of bonding wire semiconductors to it. Also, it has difficulty in adapting to the increased miniaturization of component attachment points. The Institute for Printed Circuits (IPC) is currently assessing Pb-free alternatives to HASL through the EPA DfE PCB Project. The project will assess the economic, environmental, and performance characteristics of the following HASL alternatives; organic solder protectorates, immersion Sn and Ag, electroless nickel/immersion gold, immersion palladium, and electroless nickel/immersion palladium. 10.3.2.6 Improved End-of-Pipe Pollution Control Practices. In the 1970s, conventional metal precipitation systems were the most common type of wastewater treatment utilized by the industry. Although precipitation remains very common, some facilities are supplementing or replacing such systems with ion exchange and electrowinnowing technologies. For most facilities, copper, Pb, and nickel, all of which are amenable to ion exchange and electrowinnowing, are the only metal ions present in significant concentrations. Furthermore, these techniques result in salable forms of metals, which can produce economic revenue for the company as well as a “cleaner” waste treatment sludge that may not be subject to Resource Conservation and Recovery Act (RCRA) hazardous waste regulations. The use of nonchelated process chemistries also has reduced the generation of wastewater treatment sludge. Reduced sludge generation means cost savings, since the avoided cost of managing this sludge, which the EPA considers a listed hazardous waste (e.g., F006) in most cases, can be significant. 10.3.2.7 Increased Reuse and Recycling of Manufacturing By-Products. The circuit formation processes noted already are subtractive and, in many cases, the most reliable and cost-effective ways to manufacture PCBs. The subtractive method generates large amounts of copper-bearing waste streams. Approximately 60 percent of the copper is removed in the typical etching process, resulting in a significant amount of copper leaving the facility as waste. In general, the industry recycles a majority of its manufacturing by-products (e.g., wastewater treatment sludge, etchant, off-specification boards, frames, and solder dross). Recycling extracts copper for reuse, reducing the need for virgin copper ore to be mined and reducing potential groundwater contamination (which could occur if copper-containing waste or incinerator ash is left in a landfill). PCB manufacturers can use on-site recycling methods, such as electrowinnowing, to remove metallic ions

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10.15

from spent process solutions, ion exchange regenerant, and concentrated rinse waters; or they can send their manufacturing by-products off site to facilities where the valuable constituents are reused or reclaimed. Currently, the following materials are not subject to the RCRA hazardous waste restrictions and rules when they are reclaimed: scrap boards, scrap trim, router dust, solder baths and dumps, and solder dross. In addition, some states have ruled that spent etchant, when shipped to specific facilities that use the etchant as a direct feed stock in manufacturing operations, is not subject to RCRA. 10.3.2.8 Increased Use of Direct Metallization. As noted, the electroless copper process has been used to make drilled through-holes conductive. Electroless copper uses large quantities of water, formaldehyde, and chelators, such as ethylene diaminetetraacetic acid (EDTA). These chelators also chelate metal waste streams, complicating their treatment. The EPA and the IPC, under a DfE project, assessed a number of direct metallization alternatives—carbon, graphite, palladium, and conductive polymers—and found that all of them cost less, perform as well, and have less environmental impact (no formaldehyde or EDTA and less water use) than electroless copper. In addition, facilities that switched to alternatives have found that these alternatives often are less hazardous to use; increase production flow; decrease maintenance requirements; and reduce cycle time, operating costs, and water usage, increasing the facilities’ bottom lines. 10.3.2.9 Increased Water Reuse and Recycling. The PCB industry is dependent on the use of large quantities of high-quality water, which is used primarily to rinse circuit boards between process steps. PCB facilities now increasingly employ water reuse and recycling technologies to extend process bath life and decrease their reliance on municipal water, which may be costly and, in some cases, of poor quality. Facilities located in areas where water supplies are scarce may face flow restrictions from municipal water authorities. The installation of on-site water recycling systems and the use of simple water use reduction methods (e.g., flow restrictors, conductivity controls, flow meters, counterflow rinse tanks, and spray rinse systems) have resulted in large water use reductions for a number of PCB facilities. Fortunately, the adoption of water conservation practices often results in economic gain. 10.3.2.10 Future Opportunities for Pollution Prevention. There are additional opportunities for improved environmental impact. These might include: ● ●

● ●

● ● ● ●

One hundred percent beneficial reuse and recycling of all hazardous by-products Use of raw materials from sustainable sources (e.g., copper foil from recycled copper, laminate from bio-based or recycled plastic sources) Zero-water-discharge manufacturing processes Systematic management of environmental health safety (EHS) compliance and performance [ISO 1400 I and Environmental Management Systems (EMAS)] Development of technically acceptable Pb-free solders Standardization and implementation of design for reuse and disassembly practices Development and implementation of energy-efficient manufacturing operations Integration of environmental cost and activity-based cost accounting tools into traditional accounting methods

10.16

10.3.3

CHAPTER TEN

ENVIRONMENTAL IMPACT

10.3.3.1 Current Technology Trends. Since the industry is being driven to produce lighter, denser, cheaper circuits, designers must take advantage of these technologies. Many of the newer processes utilize less material, produce less waste, and are more energy efficient. For example, the two major approaches to microvias utilize either laser to make vias without drilling or photodielectric materials. While both these approaches produce vias that connect only layer to layer where physically needed, this immediately increases the circuit density and reduces material usage. Photodielectrics can also produce circuit “channels” as well as vias, which in combination with additive metallization would further significantly reduce waste. In addition to being used to make vias, lasers also are being utilized more seriously to create pattern resists used in making the circuit traces. Laser direct imaging allows the circuit design to go directly from the digital output of the design to the board itself without utilizing a phototool. This eliminates the phototool and its waste streams. In the case of a photodielectric, it may even be possible to image the vias and channels directly into the dielectric. 10.3.3.2 Electrical Design Effects. As can be seen from the improvements at both the chemical usage and the technology levels, it is possible to utilize materials and processes to significantly reduce the environmental impact of a circuit board. However, this can happen only if the PCB manufacturer is allowed to pick the best process and materials and not be hampered by outmoded specifications that might call for some specific chemical usage. For example, if electroless copper in the vias or holes is specified, then the manufacturer cannot utilize direct metallization processes to do the same process. Thinner copper and utilization of polymer thick film conductors for via metallization, shielding, and even conductor metallization can save much waste, since either less copper is used or, in the case of polymer thick films, the process is strictly additive. In addition, newer technology should be implemented where possible. For example, microvia technologies can be used to significantly reduce layer count or board size. This freedom to trade off layer count for board size can be significant, especially if the original board dimensions do not fit well into the standard panel sizes used in the industry. Unused panel areas that end up as edge trim scrap typically must go through all the same process steps as the final board. This means that all that processing and material is wasted and accounts for a significant portion of the scrap. Using mixed flex-rigid boards, thinner flexible materials can be used in place of rigid materials to not only carry circuitry but also function as an interboard connector. The key to utilizing the right materials and processes is to work closely with the PCB manufacturers. Decisions can be arrived at that both meet technical specifications and have the least environmental impact. Many people currently are working on methods to incorporate DfE in design algorithms, but direct discussions with suppliers will often serve the same function. Many PCB fabricators also now have inhouse design capabilities and can suggest alternatives to a given design. The PCB industry has made great strides in reducing its environmental impact by stepping up its pollution prevention efforts. Additional improvements may be made by optimizing the utilized processes and materials. Still other ongoing efforts may reduce the environmental burden even further. While the manufacturers themselves can implement much of this, cooperation along the electronic supply chain is critical. Those asking for specific materials and design considerations must be aware of the consequences of those design decisions. Despite the number of efforts to implement

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DfE mechanisms to make this process easier, it is just as important to work directly with suppliers to understand the constraints that design decisions impose and the opportunities for improvement should other choices be made.14

10.4 10.4.1

CONFORMAL COATING WITH ENVIRONMENTAL SAFETY FUNDAMENTALS

A conformal coating is a thin layer of insulating material applied to the surface of a PCB to protect sensitive components from thermal shock, moisture, humidity, corrosion, dust, dirt, and other damaging elements. When properly applied, these coatings provide a high degree of insulative protection and are usually resistant to many types of solvents and harsh environments. Coatings also provide excellent dielectric resistance. Demanding applications where conformal coatings are critical include automotive products, consumer electronics and appliances, industrial controls, military/aerospace systems, and medical devices.15 In the past, because of the cost of conformal coating materials and application processes, only the most expensive boards or those with special reliability requirements were coated. Recent advances in application technology and process ability have improved the economics of conformal coating use. Additionally, as circuit size diminishes and components become more delicate, protective barrier coatings are growing in importance. While many available conformal coatings are still solvent based, the market for solvent-free coatings in North America and other parts of the world is growing rapidly. In 1970, the U.S. government passed the Clean Air Act, which gave the EPA the authority to set national air quality standards to protect against common pollutants, including materials that release volatile organic compounds and ozone-depleting chemicals. EPA and Occupational Health and Safety Administration standards, stringent state and local regulations, and emerging environmental awareness have combined to encourage coatings formulators and electronics manufacturers to use solvent-free and low–ozone-depleting chemical/volatile organic compound coatings wherever possible in their manufacturing operations. Although solvent-free coatings are more expensive on a per-unit basis than solvent-based materials, much less volume is used. Because solvent-free coatings are 100 percent solids, they do not evaporate as part of the curing process. Solvent-based materials are typically 60 to 70 percent solvents, all of which are wasted during evaporation.

10.4.2

COATING SELECTION

Conformal coatings are generally classified according to the molecular structure of their polymer backbone. There are five traditional conformal coating chemistries: acrylic, epoxy, urethane and parylene (commonly grouped together as organics), and silicone (an inorganic). All except parylene were solvent based until a decade ago, when increased environmental concerns and resulting government regulations dictated the reformulation of conformal coatings to solvent-free, low–ozone-depleting chemical/volatile organic compound materials and processes. Many environmentally acceptable coatings are hybrid formulations that combine two or more coating chemistries (e.g., urethane acrylate and acrylic functional silicones) to improve performance properties, wetting, adhesion, and cure requirements.

10.18

CHAPTER TEN

Solvent-free organic coatings are typically tough, abrasion-resistant materials that offer improved moisture and chemical resistance and operate at temperatures ranging from −40 to 125°C. Typical organic coating dielectric strength is 1000 V/mil. Organic coatings in general, and acrylics and urethanes in particular, are resistant to a broad range of solvents. However, acrylics and urethanes may not be the best coating chemistries for environments exposed to wide fluctuations in temperature over short periods of time, as they tend to crack under thermal stress. Rework on acrylics and urethanes can be handled using mechanical abrasion or microsand blasting. Epoxies tend to be the least popular conformal coatings because of rework issues. Because most board substrates are made of epoxy, the manufacturer may destroy the board by removing the coating. Silicone coatings are soft, flexible materials with a high coefficient of thermal expansion, which allows them to absorb expansion and contraction stress without harming protected components and to function well in environments with extreme temperature cycling from −40 to 204°C. Silicones are very forgiving materials in production because they coat and adhere to just about any surface found on a PCB and offer good resistance to polar solvents, an attribute that makes them ideal for automotive electronics applications. Silicone’s dielectric strength is typically 500 V/mil. Parylene coatings are deposited onto PCBs using gas-phase polymerization to provide a very thin uniform coating. Boards coated with parylene must be processed in a batch operation using special high-vacuum equipment. An adhesion promotion process using silane and isopropyl alcohol followed by a rinse and bake-out step is generally required as a pretreatment for most electronic components bound for parylene deposition. Because this coating can find its way into gaps as small as 0.001 in, airtight masking of interconnects is required to prevent leakage. Parylene is applied in the cured state during the chemical vapor deposition process once the raw dimer material is sublimated.

10.4.3

CURING METHODS

There are various methods available to achieve rapid cure or solidification of conformal coatings, including two-component mixing, heat, moisture, and ultraviolet (UV) light exposure. Each of these methods is appropriate for specific coating chemistries and has distinct advantages and disadvantages. Traditional acrylic, urethane, and epoxy coatings can cure or solidify in minutes using heat or two-component technology, which involves a room-temperature chemical reaction. Silicone coatings may be cured by exposure to heat, UV light, or ambient moisture. Hybrid coating formulations, which incorporate multiple coating chemistries, are designed either to be UV curable or to rely upon dual-cure mechanisms such as UV light, heat, or ambient catalyzation to enhance cure efficiency and increase in-line cure speeds. Every cure method has its own set of advantages and disadvantages. Twocomponent mixing offers wide latitude in adjusting a coating’s cure speed and pot life. However, this technology is often considered undesirable because it requires the user to inventory and mix, in the proper ratio, two different materials. Catalyzed coatings use two-component room-temperature cure. Properly formulated, these materials have a 1:1 mix ratio and a pot life of 8 to 10 h (one shift) or up to 5 days depending on the chemistry, which makes them good candidates for robotic applications. These coatings wet and adhere well in the no-clean process, and have a very effective shadow cure. Recent advances in static mixing and meter mix equipment

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make it possible to mate two-component materials with both atomized spray and selective application equipment. While heat cure improves wetting and lowers viscosity, some heat-cure coatings, particularly platinum-catalyzed silicones, are subject to cure inhibition. This occurs when the coating comes into contact with various sulfur, amine, or organometallic compounds that are sometimes found on boards as residual contaminates from the integrated circuit chip demolding or solder flux process. Additionally, achieving very rapid cure (less than 2 min) requires a temperature in excess of 150°C, which may be high enough to damage some components. Moisture-cure coatings solidify rapidly on exposure to ambient or induced moisture. Extremely moisture-sensitive materials may cure inconveniently (e.g., in the feed line, on the surface of the supply reservoir, or at the dispense nozzle). To control a potential rise in viscosity, the coating should be exposed to as little moisture as possible prior to application. UV light cure is an efficient process. UV light cure materials contain a photoinitiator that cures the coating in seconds when exposed to the proper UV light wavelength. One major problem encountered with UV materials is their inability to cure in areas not exposed to UV light. To overcome this problem, UV coatings have been formulated with a secondary cure mechanism to ensure full cure in areas that are not directly exposed to UV energy. Full cure in shadowed areas is extremely important for board performance with all coating chemistries, as elevated operating or test temperatures may cause uncured material to expand, rupturing the coating fillet and cracking solder joints or integrated circuit packages. UV light curing materials also are subject to oxygen inhibition, a process that occurs at the coating-air interface when oxygen reacts competitively with free radicals generated during UV light exposure. Oxygen inhibition can be overcome by increasing UV light intensity or by reducing oxygen concentration with a nitrogen blanket. Prior to selecting a coating chemistry, the end-use environment of the PCB should be reviewed, assessing the potential for exposure to solvents, temperature extremes, dramatic temperature gradients, and physical stress. No one coating is right for all boards and conditions. Working closely with reputable coating material suppliers that team up with equipment suppliers is the best way to ensure the selection of an appropriate material and process.

10.4.4

DISPENSING METHODS

Normally the final manufacturing step on a PCB assembly line, conformal coatings can be applied manually or with semi- or fully automated techniques. Preparation for conformal coating is a four-step process. First, board cleanliness is established and, if necessary, the board is cleaned. Next, connectors on the PCB are masked off as necessary to protect interconnects from the coating process. Coatings are then applied to the board and cured. Finally, any protective masks on the board are removed. Conformal coating dispensing techniques can be selective or nonselective. Nonselective systems apply the coating uniformly at a very fast pace, but add substantial time and cost in material waste and manual masking/demasking operations. Examples of nonselective dispensing techniques are dip, atomized spray, brush, and wave or flow coating. ●

Dip. Boards are immersed into liquid conformal coatings and withdrawn. Because most dipped coatings will not penetrate very narrow gaps, the dipping process is decreasing in popularity.

10.20 ●

●

●

CHAPTER TEN

Atomized spray. Performed with a standard automotive paint spraying gun, atomized spray is the most popular method of manual coating as it provides fast, uniform coverage. Brush. Typically used for small boards or localized repair and touch-up coating application, brushing is the least used application method and is best suited for low-volume production. Uniform thickness and bubbling are the main problems with brush application. Wave or flow coating. Boards are indexed over a wave or pumped tide of coating material that is applied to one side at a time.

Computer-controlled selective coating systems apply coatings to designated areas of the PCB. Because coatings are precisely dispensed in defined areas, masking and demasking operations as well as other off-line batch activities are significantly reduced or eliminated. Selective coating systems offer substantial savings in resin conservation and off-line masking and demasking labor operations. Some popular selective coating systems are as follows: ●

●

●

●

An airless process using a nozzle to dispense a shaped curtain of coating material, designed for use with solvent-based materials. Evaporation helps control cured film thickness and migration of wet material. A Venturi-type air-assisted dispensing head designed to dispense high-viscosity, solvent-free materials.This device produces a wide (≥1 in) coating curtain from the head and stretches it over the board’s surface. Overspray is dependent on the viscosity of the material being applied and the on/off times programmed into the dispensing profile. A dispensing head shaped like a probe. During selective dispensing, an air assist “twists” the coating stream into a bead, corkscrew, or conical mist pattern on the substrate. Though designed to dispense low-viscosity coatings, this head is not as sensitive to viscosity or chemistry as other technologies, and offers three different dispensing patterns that can be programmed for specific board geometries. Selective atomized spray head systems. These have been found to work well with a wide range of coating viscosities. Multiple tools and spray heads can be incorporated to perform varied dispensing tasks.

All selective systems can be configured with indexers, board inverters, and various cure systems to create an automated process that can be added to a conventional assembly line.

10.4.5

PROCESS ISSUES

The degree of solder mask cure is important to conformal coating performance. If not cured completely, ingredients such as glycols, bromides, and ionic compounds can exit the film during subsequent solder excursions, leaving residues that may ultimately affect the wetting characteristics and adhesion of the conformal coating. Some of these residues can also contribute to electrochemical migration and subsequent dendrite formation. Also, if the solder mask materials are not applied to clean, uncontaminated substrates, many problems can occur during conformal coating. While contaminated boards fail less quickly with a conformal coating, they can still fail because of trapped ionic and corrosive species between the substrate and the coating.

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10.21

Not long ago, board substrates were G-10 or FR-4 materials using RMA flux chemistries and CFC-113 solvent-cleaning methods. These limited variables made tracking compatibility problems relatively simple. Today’s wide selection of solder masks, flux chemistries, solder processes, and alternative cleaning processes has greatly complicated compatibility issues. By performing cleanliness and adhesion testing, board manufacturers can assess the baseline contamination of the PCB and determine whether further cleaning is necessary to ensure conformal coating adhesion, integrity, and reliability. Two effective methods of testing boards are ionic cleanliness testing, which determines levels of chloride per square inch, and surface insulation, an electrical test of solder joints. Although conventional ionic cleanliness testing methods are not as accurate as ion chromatography, they are excellent cleanliness monitors for the production environment. If contamination levels are higher than recommended (5.7 µg/NaCl/cm2), board manufacturers have a number of choices for cleaning the assembly. However, there is still no single, easy, environmentally safe answer to board cleaning. When considering replacement cleaning chemistries, manufacturers should note the cleaning capability, evaporation times, residue, and odor of the process. With any of the available cleaning processes, a chemical reaction may take place that could affect board performance and reliability. No-clean/low-solids fluxes are not usually removed by cleaning prior to coating application. The type and level of remaining residue is dependent on the board design and the solder profile. Inadequate preheat temperatures and dwell time duration can affect the success of a no-clean process. If the profile is not done correctly, ionic and corrosive species from the flux can cause a variety of performance problems. The flux application method and soldering environment also have an impact on how much unvolatized flux species will remain on the assembly. Because a conformal coating can retard corrosion but not prevent it, manufacturers using these materials must benchmark and maintain proper processes to prevent corrosion and ensure reliability. Excessive residues can be coated, but entrapment of the ionic and corrosive species will cause a variety of problems over time. Conventional ionic testing is not routinely performed on low solids because evaporation of the isopropyl alcohol in the test solution causes a visible white residue to form around the solder fillets, creating aesthetic concerns. Water-soluble fluxes work well when used in conjunction with conformal coating operations. As these materials are very aggressive, they must be washed off within minutes of soldering operations. As a result, board surfaces are generally well cleaned and few coating problems are encountered. However, water-soluble fluxes can outgas residual absorbed contaminants and water during heat excursion, causing dendrite formation or coating blisters in areas of flux stains. The drying process must be as controlled as the actual cleaning process. Again, proper process controls will greatly reduce potential problems. For effective, long-term conformal coating solutions, board manufacturers should work closely with conformal coating formulators to determine effective board cleaning methods. Although this was once the sole responsibility of board manufacturers, coating suppliers will now assess and test process-ready assemblies for cleanliness and coat them with application-appropriate coatings to determine their effectiveness in the assembly process. Coating companies will also work closely with equipment manufacturers to prequalify adhesives and dispense equipment, ensuring that materials and the application systems will run smoothly on the customer’s production line.

10.22

CHAPTER TEN

REFERENCES 1. Siddhaye, S., and P. Sheng, “Design for Environment: A Printed Circuit Board Assembly Example,” in Green Electronics, Green Bottom Line, Goldberg, L. H., and W. Middleton, eds., Newnes, Boston, pp. 113–122, 2000. 2. Allen, D., “Life Cycle Assessment and Design for the Environment,” Tutorial Notes, IEEE Symposium on Electronics and the Environment, San Francisco, CA, May 1997. 3. Siddhaye, S., and P. Sheng, “Integration of Environmental Factors for Process Modeling of Printed Circuit Board Manufacturing—II. Fabrication,” Proceedings of the IEEE International Symposium on Electronics and the Environment, pp. 226–233, San Francisco, CA, May 1997. 4. Worhach, P., and P. Sheng, “Integration of Environmental Factors for Process Modeling of Printed Circuit Board Manufacturing—I. Assembly,” Proceedings of the IEEE International Symposium on Electronics and the Environment, pp. 218–225, San Francisco, CA, May 1997. 5. Srinivasan, M., T. Wu, and P. Sheng, “Development of a Scoring Index for the Evaluation of Environmental Factors in Machining Processes: Part I, Formulation,” Transactions of NAMR, 23:115–121, 1995. 6. Balakrishnan, S., and M. Pecht, Placement and Routing of Electronic Modules, pp. 59–96, Dekker, New York, 1993. 7. www.epa.gov/opptintr/dfe/pwb/pwb.html. 8. Coombs, C. F., Printed Circuits Handbook, McGraw-Hill, New York, 1996. 9. PWB Project Case Study 2, On-Site Etchant Regeneration, EPA744-F-95005, July 1995. 10. FR 42 USC Section 7671(c). 5. PWB Project Case Study 1, Pollution Prevention Work Practices, EPA 744F-95-004. 11. U.S. EPA, “Printed Wiring Board Industry and Use Cluster Profile,” EPA 744-R-95-005, pp. 2–38, September 1995. 12. IPC Surface Mount Council White Paper, “PWB Surface Finishes,” SMCWP-005, April 1997. 13. U.S. EPA, “Implementing Cleaner Technologies in the Printed Wiring Board Industry: Making Holes Conductive,” EPA 744-R-97-001, February 1997. 14. Evans, H., and J. W. Lott, “Implementing Green Printed Wiring Board Manufacturing,” in Green Electronics, Green Bottom Line, Goldberg, L. H., and W. Middleton, eds., Newnes, Boston, pp. 153–160, 2000. 15. Ritchie, B., and L. Bennington, “New Conformal Coatings Combine Protection with Environmental Safety,” SMT, 14(4):44–48, April 2000.

CHAPTER 11

GLOBAL STATUS OF LEAD-FREE SOLDERING 11.1

INTRODUCTION

Lead (Pb) has been widely used in the industry for a long time. Of the approximately 5 million tons of lead consumed globally every year, 81 percent is used in the storage batteries, with ammunition and lead oxides together accounting for about 10 percent, as shown in Table 11.1.1 However, despite the longtime acceptance of lead by human society, lead poisoning is now well recognized as a health threat. The common clinical types of lead poisoning may be classified according to their clinical picture as (a) alimentary, (b) neuromotor, and (c) encephalic.2 Lead poisoning commonly occurs following prolonged exposure to lead or lead compounds. The damage often is induced slowly, but definitely. Some historians even speculate that the fall of the Roman Empire could be related to the use of lead in the pipelines that carried drinking water to Roman cities. Due to the profound evidence of toxicity, the use of lead chemicals in paint and gasoline has been prohibited for several years. Storage batteries, due to their almost 100 percent recycling levels, do not contribute to pollution or contamination and thus pose no immediate issue. On the other hand, although solder is only a small percentage by weight of electronic products (TVs, refrigerators, PCs, phones, etc.), these devices often end up in landfills after being disposed, and the lead could leach out into the water supply. For instance, in Japan the lead elution environmental standard in landfills is 0.3 mg/l. In the toxic materials detection tests recently performed by the Japanese Environmental Agency, it was confirmed that the amount of lead leaching from the pulverized remains of TV tubes and printed substrates for PCs and pachinko machines far exceeds the environmental standard.3 In the USA, the regulatory limit for lead in drinking water is 0.015 mg/l per EPA40 CFR141. The limit is 5 mg/l if the test is done by Toxicity Characteristics Leaching Procedure per EPA40 CFR261. A recent study4 demonstrates that the lead leached out from solder can be several hundred times higher than the limit. This concern about lead is a natural result of the growing global concern about the environment. This environmental awareness can be demonstrated by the “German Blue Bird” system, which has been widely used in the European community for some time. Consumers in Germany call it the “Blue Eco Angel,” but its official name is Environmental Label. This is a special logo for products with positive environmental features on the German market and has been in use for two decades. As of today, over 4000 products bear the mark.5

11.2

INITIAL ACTIVITIES

The attempt to ban lead from electronic solder was initiated by the U.S. Congress. In 1990, Reid S2638—subsequently modified to S729—proposed banning of all lead11.1 Copyright © 2003 by The McGraw-Hill Companies, Inc. Click here for terms of use.

11.2

CHAPTER ELEVEN

TABLE 11.1 Lead Consumption by Product Product Storage batteries

Consumption (%) 80.81

Other oxides (paint, glass and ceramic products, pigments, and chemicals)

4.78

Ammunition

4.69

Sheet lead

1.79

Cable covering

1.40

Casting metals

1.13

Brass and bronze billets and ingots

0.72

Pipes, traps, and other extruded products

0.72

Solder (excluding electronic solder)

0.70

Electronic solder

0.49

Miscellaneous

2.77

bearing alloys, including electronic solders, and instituting a tax of $1.69 per kg on primary lead and $0.83 per kg on secondary lead used in the industry. However, lead solders were removed from the bills after intense lobbying by the U.S. electronics industry. In 1994, Denmark, Sweden, Norway, Finland and Iceland signed a statement to phase out Pb in long run. On June 16, 1997, a press release from the Swedish Government identified lead as one of the elements to be eliminated from products over the following 10 years.The Sweden Environmental Quality Objectives direct that any new products, including batteries, introduced in Sweden should be largely free from Pb by 2020. Swedish manufacturers are also under a voluntary ban effective in 2000.6 At about the same time frame, recycling laws were proposed in various Asian countries. In October 1996, the Discard Processing/Resource Reclamation Committee of the Industrial Structure Council in the Japanese Ministry of International Trade and Industry (MITI) announced goals for recycling discarded automobiles. Also in 1996, the Japanese Automobile Industrial Association set up a self-managed environmental program. The Pb used in new automobiles is to be cut in half by 2000 (excluding Pb used in batteries) and to one-third of 1996 values by 2005. Most of the Pb usage in Japanese vehicles now is in paint and radiators.

11.3

RECENT ACTIVITIES

There are pending producer responsibility laws for electronic and electrical equipment in a number of European countries. Laws were passed in Holland and Switzerland before 1999 involving producer responsibility. Norway followed in 1999 and Sweden in 2000. In some cases producer responsibility may involve the manufacturer, importer, or reseller taking responsibility for the take-back of products and proper end-of-life treatment. Threshold limits for recycling of specified types of materials may be included also. Denmark has proposed its own Pb ban, but cathode ray tubes and electronics are not included.7 In 1998 the European Union (EU) introduced a draft directive (law) called the Waste from Electrical and Electronic Equipment Directive (WEEE), which calls for

GLOBAL STATUS OF LEAD-FREE SOLDERING

11.3

a ban on lead in all electronics (except automotive) by January 1, 2004. WEEE, which intends to ban the selling and/or importing of electrical/electronic equipment containing lead interconnects, encountered objection from many European electronics trade bodies including EUROBIT (information technology), ECTEL (telecommunications), the Printed Circuit Industry Federation, the Federation of Electronics Industries, etc. On June 13, 2000, the EU Commission officially adopted the WEEE proposals as two separate but associated draft directives for submission to the European Parliament—WEEE and Reduction of Hazardous Substances (ROHS). The ROHS proposals required replacement of lead and various other heavy metals and brominated flame retardants beginning January 1, 2008. On April 24, 2001, the Environmental Committee of the European Parliament adopted a number of amendments to the two pending EU waste directives and advanced their progress through the EU legislative process.8 The Committee agreed to exempt electronic applications where high-temperature melting solder is used, thereby alleviating the pressure in identifying lead-free high-temperature solder alternatives. The deadline for the proposed chemical ban was advanced from 2008 to 2006. Other results from the vote included: (1) an amendment to include servers and storage equipment in the ROHS chemical ban exemption failed; (2) consumables (e.g., printer cartridges) are now covered by WEEE, with producers responsible for collection; (3) collection targets have also been increased from 4 to 6 kg/head/year; (4) recovery targets increased by 5 to 10 percent; (5) the deadline for implementing collection and recycling schemes advanced from 5 years to 30 months after implementation, and (6) the costs of historic waste may be financed collectively by producers through a visible fee. The European Parliament voted on May 15, 2001, to adopt proposals to amend the date for the hazardous material ban in the WEEE/ROHS draft to 2006. Material and components where substitution is “impossible” are exempt from the ban, including lead in server, storage, voice and data transmission, and networking equipment. The Council of Ministers from each European state government discussed the proposals on April 10, 2002. Their opinion aligns with the parliament proposals in setting a target date of January 2006 for a ban on hazardous materials including lead. This opinion of the council will be discussed and voted on by the European Parliament in the next few months in order to allow the directives to be finalized. The list of hazardous materials is due to be reviewed in 2003, with the possibility of extending the ban to, e.g., polyvinyl chloride and other halogenated flame retardants, etc.5 The move toward Pb-free processes raised the attention of some major manufacturers. Nortel Networks is one of the lead-free pioneers in Europe. They initiated a lead-free program in 1991, selected Sn99.3/Cu0.7 in 1994, built 500 lead-free phones in 1998, and targeted meeting the second WEEE in 2001.9 In Korea, Samsung Group declared its commitment to protecting the environment in 1994, and completed development of a “green” semiconductor product that uses no halogen compounds (which contain such toxic substances as lead, chlorine, and bromine). Company officials say that the new-concept device will go into mass production in the second half of 2001. The new concept is initially being applied to Samsung’s 128-Mb synchronous dynamic random access memory package and 256Mbyte module for PC-133 systems. Samsung has replaced the tin-lead compound used to plate the package terminals with a tin-bismuth compound. Conventional tinlead solder paste has also been replaced by a tin-silver-copper solder. Moreover, external packages and printed circuit boards no longer contain halogens such as chlorine, bromine, or antimony. Examples of these green products include conventional packages, ball grid array (BGA) packages, and memory modules.10

11.4

CHAPTER ELEVEN

In Japan, the only legislative activities deal with the reclamation and recycling of electronics. The Home Electronics Recycling Law came into force on April 1, 2001, and applies only to TVs, refrigerators, and similar items. On January 30, 1998, the Japanese Electronic Industry Development Association (JEIDA) and the Japanese Institute of Electronics Packaging (JIEP) presented a report entitled “Challenges and Efforts Toward Commercialization of Lead-Free Solder—Roadmap 2000 for Commercialization of Lead-Free Solder.” This report, which includes a survey of 132 companies, offers the Japanese perspective on leadfree electronics. In this report, JEIDA proposes the following roadmap for lead elimination: ● ● ● ● ● ● ● ●

First adoption of lead-free solders in mass-produced goods: 1999 Adoption of lead-free components: 2000 Adoption of lead-free solders in wave soldering: 2000 Expansion of use of lead-free components: 2001 Expansion of use of lead-free solders in new products: 2001 General use of lead-free solders in new products: 2002 Full use of lead-free solders in all new products: 2003 Lead-containing solders used only exceptionally: 2005

The roadmap presented by JIEP is fairly similar to that of JEIDA, as shown in the following list:1 ● ● ● ● ● ● ●

Mass production using Pb-free solder: 1999 to 2000 Adoption of Pb-free components: 1999 Increased adoption of Pb-free components: 2000 to 2001 Full-scale recycling of assembly boards: 2001 to 2002 Pb-free solder used for new products preferentially: 2003 Pb-containing solder used only exceptionally: 2005 to 2010 Elimination of Pb solders: 2010

Some major Japanese original equipment manufacturers (OEMs) have begun to jointly develop recycling processes for electronic products. A number of major Japanese companies, e.g., Sony, Toshiba, Matsushita, Hitachi, and NEC, have made commitments to go lead free by 2001. This is in advance of Japanese legislation on take-back due to come into force in April 2001. The Pb-free advancement roadmaps of those companies are detailed in the following list: ●

●

Matsushita (Panasonic) has been shipping 40,000 MiniDisc players per month with lead-free solder since October 1, 1998, and plans to eliminate all lead interconnects in four products by April 2001. Matsushita’s market share of its lead-free MiniDisc player jumped from 4.6 percent to 15 percent in 6 months in Japan. This lead-free product was reported to be introduced into Europe in March, 1999. Matsushita is using SnAgBiIn and SnCu.5 Currently only disc players and TVs are using lead-free solder. Matsushita has also indicated it will begin marketing leadfree products in the U.S. in 2000. Each division of Matsushita is charged with using a lead-free solder for at least one electronic product by March 2002. Sony reduced its lead usage in 1999 by half of that used in 1996, and it plans to completely eliminate lead from all products except high-density packaging by

GLOBAL STATUS OF LEAD-FREE SOLDERING

●

●

●

●

●

●

11.5

2001. Sony’s suppliers have been instructed to provide only lead-free materials and parts. Sony uses SnAgBiCu and possibly also Sn93.4/Ag2/Bi4/Cu0.5/Ge0.1 solder for assembly. By 2001, all lead will be eliminated except in high-density electronics packaging. Akikazu Shibata of Sony predicted in 1999 that the company would be 50 percent lead free in 1 to 2 years, and more than 75 percent lead free in 5 years. Sony aims to introduce lead-free solder for all models produced in Japan and overseas by March 2001 and March 2002, respectively. Fujitsu has announced the following lead-free roadmap: ● Complete lineup of lead-free LSI products to be available by October 2000. ● Half of all printed circuit boards used in Fujitsu products to be lead free by December 2001. ● Total elimination of lead from all Fujitsu products by December 2002. This initiative includes not only components internally produced at Fujitsu, but also parts supplied by outside vendors. Toshiba eliminated Pb from refrigerators, TVs, cleaners, PCs, and other major products by December 2000 and plans to eliminate Pb solder in mobile phones by 2003. The company possibly uses SnAgCu.5 Hitachi cut lead usage by 50 percent by March 2000 from 1997 levels. Half of its domestic products were lead free in 2000, with Pb having been eliminated from refrigerators, air conditioners, TVs, VCRs, and PCs since 1999. The company will eliminate inner Pb interconnects by March 2002 and Pb will be completely phased out by March 2004. Hitachi uses SnAgBi and SnAgCu and is currently investing 1.2 billion yen ($11.2 million) to expand production of lead-free solder.5 NEC launched the world’s first three notebook computers with lead-free motherboards, manufactured with SnZn. It plans to install lead-free motherboards in desktop PCs next. NEC will reduce lead use by 50 percent by fiscal 2003 (versus 1998) and is currently using lead-free semiconductors, which began shipping in January 2001. NEC is labeling lead-free products to differentiate them from those that contain lead. The company uses SnAgCu, SnZn, SnCu, and SnZnBi.5 Mitsubishi plans to cut Pb usage to 50 percent by 2004 and to eliminate it entirely by 2005 for four major products.5 NTT has announced it will use no Pb or Cd in newly purchased equipment.11

11.4

IMPACT OF JAPANESE ACTIVITIES

By 2001 the leading Japanese OEMs will have introduced products that contain no Pb in their interconnect systems. This will allow the Japanese to be positioned to exclude products from Japan that do not meet these environmental standards. Furthermore, existence of Japanese products will justify European legislation requiring Pb reduction and highly recyclable electronic products by 2007,12 thereby further increasing the pressure on the rest of the world to convert to Pb-free processes.

11.5

U.S. REACTION

Since the initial attempt in Congress in early 1990s, very little activity has been seen in the U.S. until recently. The automotive segment is probably the only one with sus-

11.6

CHAPTER ELEVEN

tained interest. There is no legislation pending. The Lead Industry Association, Electronic Industries Alliance (EIA), Institute for Printed Circuits (IPC), and National Electrical Manufacturers Association all have been active in lobbying against leadfree legislation. The only activities under way in the U.S. are at the state level and deal primarily with electronics recycling rather than reduction in the use of toxic elements. Obviously, the message from offshore is loud and clear: either work on lead-free soldering now or forget about doing business. Thus the National Electronics Manufacturing Initiative (NEMI) called for a “Lead-Free Initiative Meeting” in February 1999 to review the situation, and since then has rolled out a series of action items to establish a Pb-free direction for the U.S. electronics industry. The second NEMI meeting, held on May 26 to 27, 1999, effectively motivated many manufacturers to get involved in Pb-free development. In April 1999 the IPC board of directors announced the following position statement: The US electronics interconnection industry, represented by the IPC, uses less than 2 percent of the world’s annual lead consumption. Furthermore, all available scientific evidence and US government reports indicate that the lead used in US printed wiring board (PWB) manufacturing and electronic assembly produces no significant environmental or health hazards. Nonetheless, in the opinion of IPC, the pressure to eliminate lead in electronic interconnections will continue in the future from both the legislative and competitive sides. IPC encourages and supports research and development of lead-free materials and technologies. These new technologies should provide product integrity, performance and reliability equivalent to lead-containing products without introducing new environmental risks or health hazards. IPC prefers global rather than regional solutions to this issue, and is encouraging a coordinated approach to the voluntary reduction or elimination of lead by the electronics interconnection industry.

The IPC statement probably fairly truly reflects the opinion of most of U.S. industry: “Pb in electronics is not perceived as a health issue, but government and commercial drivers will push for its adoption anyway. Thus IPC will facilitate activities to enable it to happen.”13 To serve the industry by helping with lead-free initiatives, the IPC developed and maintained the IPC lead-free e-mail forum. In addition, the IPC also organized a conference, IPC Works ’99, held in October 1999, with major emphasis on the Pbfree issue. It was at this conference that the IPC presented the industry with a first draft of the IPC Roadmap for Electronics Assemblies. The impact of this conference is that it was industry talking, including customers, suppliers, and competitors. The HAL User Group, an organization composed of manufacturers of printed circuit boards (PCBs), original equipment manufacturers (OEMs), contract manufacturers (CMs), chemical suppliers, and equipment manufacturers, also met in August, 1999 to address Pb-free surface finishes as a response to the pressure for Pbfree soldering. On January 17, 2001, the Environmental Protection Agency (EPA) lowered the threshold reporting level for lead starting with calendar year 2001 in its Toxic Release Inventory Rule. Therefore, any company that manufactures, processes, or otherwise uses lead or lead-containing products in quantities of 100 lb or more must file a report. This change will require many U.S. manufacturers who had never met the previous requirement of 10,000/25,000 pounds to file reports. The first report for the new requirements will be due on July 1, 2002.14

GLOBAL STATUS OF LEAD-FREE SOLDERING

11.7

To meet this pressing lead-free challenge from offshore, a number of American companies also engaged in lead-free programs, as reported by the IPC:5 ● ●

● ● ●

●

● ●

● ● ● ●

Boeing. Currently evaluating and developing reliability data on Pb-free finishes ChipPAC. Has qualified Pb-free BGAs and is scheduled to go into high-volume production in the fourth quarter of 2000 Delphi Delco. Conducting developmental activities, 2- to 3-year window Lucent Technologies. Aligning with industry through consortium activities Motorola SPS. Currently evaluating and running pilot plant production with leadfree soldering Shipley Co. LLC. Currently offering/developing Pb-free finishes for components and connectors as well as PWB final finish applications Sun Microsystems. Participating in industry consortia and monitoring the situation Texas Instruments. Introduced NiPd finish for components in 1989; believes it is in a leadership position Hadco. Investigating processes to replace SnPb board finishes IBM. Interim strategy developed in 1999; plans to stay ahead of the industry Honeywell. Has formed a team to formulate activities on Pb-free processes Visasystems. Has a patent on an organic solderability preservative (OSP)

However, a second opinion also exists on the aggressive move toward lead-free solder. On April 10, 2001, the IPC and 35 other trade associations sued the EPA.This suit is directed against the EPA ruling that reduces reporting thresholds of lead and challenges the PBT label for metals. As reported by Harvey Miller at InfraFOCUS, “PBT stands for persistent, bioaccumulative, and toxic; that is the combination that characterizes another class of toxins, often confused with metals—persistent organic pollutants, such as polychlorinated biphenyls, DDT, and other synthetic creations of the last 50 years that are truly dangerous to life. These chemicals cause cancer, disrupt metabolism, and hormonal signals. It is very difficult to eliminate them or reverse their damage. Metals, even essential ones, can present toxic effects when excessive amounts are present, but on every other score, they are comparatively benign.” This suit is supported by the numerous scientific reports in the Expert Workshop that was cosponsored by the EPA and was held in January 2000.

11.6

WHAT ARE LEAD-FREE INTERCONNECTS?

Pb may be present in metals, such as tin, as an impurity at a level of <0.1 percent by weight. Obviously this impurity will carry over into Pb-free alloys. In addition, it is difficult to have all components converted to Pb-free finishes in a given amount of time. It was therefore proposed by the High Density Packages User Group (HDPUG), a nonprofit U.S. trade organization, that a target Pb content of 1 percent by weight in the interconnect NOW would be reasonable with a level of <0.1 percent in several years. When considering the presence of Pb per weight of product, the Pb concentration might be around 100 ppm.6 Besides the HDPUG proposal, the top three European semiconductor manufacturers—Infineon Technologies, Philips Semiconductors, and STMicroelectronics— also unveiled on July 12, 2001, their proposal for the world’s first standard for

11.8

CHAPTER ELEVEN

defining and evaluating lead-free semiconductor devices. This proposal contains an upper limit for lead-free components of 0.1 percent related to the individual material, not to the whole package or component. The proposal is a result of an initiative to eliminate lead from semiconductors, aiming at accelerating the use of lead-free technologies. The three companies will be able to introduce their lead-free products far in advance to the legislative deadlines. Fully qualified lead-free components will be available by the end of 2001.15

11.7

CRITERIA FOR LEAD-FREE SOLDER

The criteria used for screening candidate Pb-free alloys can be categorized as follows: ● ● ● ● ● ● ●

Nontoxic Available and affordable Narrow plastic range Acceptable wetting Material manufacturable Acceptable processing temperature Form reliable joints

11.8

VIABLE LEAD-FREE ALLOYS

The following alloys are considered representative of viable candidates for replacing eutectic SnPb systems. Many of the systems are based on adding small quantities of third or fourth elements to binary alloy systems in order to lower the melting point and increase the wetting and reliability. It is reported that with increasing amounts of additive elements, (1) the melting point of the system decreases; (2) the bond strength first rapidly decreases, then almost levels off, then decreases again; and (3) the wettability first increases rapidly, reaching the maximum at a composition corresponding to the midpoint of the plateau of bond strength, then decreases.16

11.8.1

Sn96.5/Ag3.5

Sn96.5/Ag3.5 (221°C) is one of most promising alloys used by the National Center for Manufacturing Sciences (NCMS), Ford, Motorola, and TI Japan. A German study has suggested that it is one of the most suitable alloys. There is long experience with using this alloy. Indium Corp. reported it to have the poorest wetting for reflow soldering among high-Sn alloys.17

11.8.2

Sn99.3/Cu0.7

Sn99.3/Cu0.7 (227°C) is reported by Nortel to have soldering quality equal to that of eutectic SnPb in telephone manufacturing. In air reflow the wettability is reduced

GLOBAL STATUS OF LEAD-FREE SOLDERING

11.9

and fillet exhibits a rough and textured appearance. This alloy is probably the “poorest” in mechanical properties of all Pb-free solders. It is preferably used for wave soldering because of the low cost of materials and of inerting of waves.

11.8.3

SnAgCu

SnAgCu is a ternary eutectic (217°C), although the exact composition needs to be clarified. Cu is added to SnAg in order to slow the Cu dissolution; lower the melting temperature; and improve wettability, creep, and thermal fatigue characteristics. Nokia and Multicore have found yields and reliability comparable to or better than those for eutectic SnPb alloy. The Brite-Euram project reported better reliability and solderability than SnAg and SnCu, and recommended this alloy for generalpurpose use. The following compositions are examples: ●

● ● ● ● ● ●

Sn93.6/Ag4.7/Cu1.7 (216 to 218°C, AMES Labs, patent USP5527628 covers any alloy containing 3.5 to 7.7 percent Ag, 1 to 4 percent Cu, 0 to 10 percent Bi, 0 to 1 percent Zn, balance Sn) Sn95/Ag4.0/Cu1 (217 to 219°C, AMES Labs) 96.5Sn/3.0Ag/0.5Cu (Harris Brazing Co.) Sn95.5/Ag4.0/Cu0.5 (217 to 219°C, published 50 years ago,18 unpatentable) Sn95.5/Ag3.8/Cu0.7 (217 to 219°C) Sn96.3/Ag3.2/Cu0.5 (217 to 218°C) Sn95.75/Ag3.5/Cu0.75 (Senju, patent JP5050286 covers 3 to 5 percent Ag, 0.5 to 3 percent Cu, 0 to 5 percent Sb, balance Sn)

11.8.4

SnAgCuX

Sn96.2/Ag2.5/Cu0.8/Sb0.5 (213 to 218°C, AIM, Castin Alloy) is reported by International Tin Research Institute (ITRI), Lucent, Ford, and Sandia Labs to have greater fatigue performance than eutectic SnPb alloy. The Brite-Euram project reported that addition of 0.5 percent Sb may strengthen the alloy further. Sn97/Cu2/Sb0.8/ Ag0.2 (226 to 228°C, Kester, SAF-A-LLOY) may be considered for wave- and handsoldering applications. SnAgCuIn (Tamura) may also be promising.

11.8.5

SnAgBiX

Addition of ≤5 percent Bi lowers the melting point and improves wettability of SnAg systems. Solderability is the best among a range of Pb-free alloys, as confirmed by Indium Corp.17 and Matsushita. The NCMS observed fillet lifting at through-hole joints as a concern for wave soldering, although other alloys such as Sn96.5/Ag3.5 also suffer fillet lifting to a lesser extent. Fillet lifting is caused by mismatch in thermal coefficient of expansion between solder and PCB materials and is aggravated by solders with a pasty range. It can be altered by addition of other elements. Addition of Cu and/or Ge results in strength improvement and possibly wettability improvement. Adding Pb to SnBi alloys can cause a 96°C ternary eutectic, Bi52/Pb32/Sn16, to form. Calculations predict that at a fixed 6 percent Pb, even alloys with ≤4.8 percent Bi can have this eutectic liquid form, and thus SnPb surface finishes should be avoided. The Japan Electronic Industry Promotion Association recommends both

11.10

CHAPTER ELEVEN

SnAgCu and SnAgBi. Some examples are shown in the following list. There are no unpatented compositions. ●

● ● ● ● ● ● ●

Sn91.8/Ag3.4/Bi4.8 (202 to 215°C, Sandia Labs Patent USP5439639, covers Ag 3 to 4 percent, Bi 3 to 5 percent, Sn balance): considered by the NCMS to be most promising alloys, along with eutectic SnAg and eutectic Sn/Bi Sn93.5/Ag3.5/Bi3 (210 to 217°C, Nihon Handa) Sn90.5/Bi7.5/Ag2 (191 to 210°C, Tamura Kaken) SnAgBi (Matsushita) Sn94/Ag3/Bi3 (213°C) Sn92/Ag3/Bi5 (210°C) Sn92.7/Ag3.2/Bi3/Cu1.1/Ge (Japan Solder) Sn93/Ag3.5/Bi0.5/In3 (Harima, Mitsui Metals)

Addition of a large amount (about 5 to 20 percent) of Bi lowers the melting point to that of eutectic SnPb solders but sacrifices the good properties of eutectic SnAg systems. Moreover, low-temperature eutectic Bi58/Sn42, which has a low partial melting point (138°C), may be created. And there are reliability problems such as interfacial problems with plating containing Pb on the electrodes of electronic components. It is attractive for low-cost manufacturing. Examples are shown in the following list: ● ● ● ● ● ● ●

Sn/Ag2/Bi7.5/Cu0.5 (Alloy H, Alpha Metals, developed at ITRI) Sn/Ag2.0–2.8/Bi13–17/Cu0–1 (Hitachi) Sn/Ag2.8/Bi10/Cu0.6 (Ono) Sn/Ag/Bi3 (210°C, Matsushita) Sn/Ag/Bi6 (220°C, Matsushita) Sn/Ag/Bi10 (205°C, Matsushita) Sn/Ag/Bi15 (209°C, Matsushita)

11.8.6

SnSb

Sn95/Sb5 (232 to 240°C) has poor wetting, although better than Sn96.5/Ag3.5, and the liquidus temperature is too high.

11.8.7

SnZnX

Sn91/Zn9 (eutectic 199°C) is fairly reactive, since Zn causes oxidation and corrosion, and reacts with flux to form a hardened paste. Japanese home electronics manufacturers are interested in Sn89/Zn8/Bi3. Bi replaces Zn to reduce Zn corrosion in humid conditions. SnZnBi alloys can have melting points close to that of eutectic SnPb. These alloys were developed primarily by home electronics manufacturers targeting low-cost products. ● ● ●

Sn90/Zn9/In1 (AT&T) Sn89/Zn8/Bi3 (191 to 195°, Matsushita, Senju) SnZnBiX (Hitachi Harima, Tamura)

GLOBAL STATUS OF LEAD-FREE SOLDERING

11.8.8

11.11

SnBi

Bi58/Sn42 (138°C) is recommended by the NCMS as a promising replacement. Eutectic Bi58/Sn42 is unusually resistant to coarsening. It is reported by HewlettPackard to have properties better than or equivalent to those of eutectic SnPb and is promising for low-temperature applications or some consumer products. Addition of 1 percent Cu dramatically slows coarsening of eutectic SnBi. The concerns are that (1) eutectic Bi52/Pb32/Sn16 (96°C) is formed on Pb surface finishes, (2) Bi is byproduct of Pb mining, and (3) there is difficulty in separating Bi from Cu at recycling.

11.9

COST

The cost of solder bar is dictated by the raw materials cost (see Table 11.2).19 However, for fabricated products such as solder pastes, the processing cost of manufacturing can become a dominant factor, and the difference between SnPb and Pb-free materials becomes very small.

TABLE 11.2 Relative Cost of Lead-Free Solder Materials

Solder alloy

Relative bar cost ($/kg)

Relative paste cost ($/kg)

Sn63/Pb37

1

1

Sn96.5/Ag3.5

2.29

1.07

Sn95/Ag3/Bi2

2.17

1.06

Sn96.1/Ag2.6/Cu0.8/Sb0.5

2.06

1.05

Sn91.8/Ag3.4/Bi4.8

2.26

1.06

Sn95/Ag3.5/Cu0.5/Zn1

2.27

1.06

Sn93.6/Ag4.7/Cu1.7

2.56

1.08

Sn96.1/Ag3.2/Cu0.7

2.21

1.06

Sn95.2/Ag3.5/Cu1.3

2.28

1.06

Relative cost of selected metals: Pb, 1; Zn, 1.7; Cu, 3; Sb, 3.9; Bi, 8.6; Sn, 11; Ag, 260; Au, 15,000.

11.10

PCB FINISHES

Pb-free surface finishes for PCB are readily available. Some, such as NiAu and OSPs, have long use history. Shown below are some more promising options: ●

●

OSPs, such as benzotriazole and benzimidazole. Low-temperature processes may not remove OSPs, and high-temperature processes may remove them and allow oxidation, particularly for multiple passes. Immersion Ag (organic Ag, Alpha Level)

11.12 ● ● ● ● ● ●

CHAPTER ELEVEN

Immersion Au/Electroless Ni Hot-air solder leveling SnCu SnBi Electroless Pd/Electroless Ni Electroless PdCu Sn (pure, whiskerless varieties)

11.11

COMPONENTS

Pb can exist in components in three different forms. Among those, the second and the third categories are related to soldering. 1. Lead used in functional materials in piezoelectric elements, capacitors, glass, fuses, etc. 2. Lead in solder used in internal connections within components 3. Lead in solder-plating surface finishes on the leads of components In general, it is relatively easy to eliminate Pb from surface finishes of the leads of components. Examples of alternatives include Sn, PdNi, Au, Ag, NiPd, NiAu, AgPt, AgPd, PtPdAg, NiAuCu, Pd, and Ni. As one of the pioneers, ASAT installed pure matte tin for plating leadframes.20 Sony chooses NiPdAu or SnBi plating for replacing SnPb surface-mount device (SMD) or through-hole device (THD) surface finishes.21 Among those options, Pd plating is difficult when the leads are made out of iron Alloy 42.4,6 Also, AgPd can cause voids due to Ag diffusion into solder. As to the Pb in solder used in internal connections within the components, such as flip chip in package, the first-level interconnection solder melting temperature (around 300°C) is normally considerably higher than the second-level interconnection solder melting temperature (about 180°C). If the melting temperature for the latter interconnection is set at around 220°C, then the first-level interconnection needs to have a melting point preferred to be above 260 to 270°C in order to avoid remelt during subsequent reflow processes. There are only few alloys that fall into that category, such as Au80/Sn20 (280°C), which is very expensive. 95Sn/5Sb (232 to 240°C) and Sn65/Ag25/Sb10 (233°C) might also be considered. The later, known as J alloy, exhibits very low ductility and unacceptable thermal and mechanical fatigue life for die attach.3 Both alloys are also too close in melting temperature to SnAgCu to be good candidates for internal connections. Technologically it will be even more difficult to substitute for the Pb used in functional materials in components.

11.12

THERMAL DAMAGE

There is more to ponder besides finding solder alloy alternatives to phase out lead. Since most of the promising alloy alternatives require a higher processing temperature, whether the components or substrates used can sustain the process becomes a big question mark.6 For instance, electrolytic capacitors are highly susceptible to high-temperature damage.Wound components, such as relays, are also susceptible to high-temperature damage and are considered likely to experience an increased ten-

GLOBAL STATUS OF LEAD-FREE SOLDERING

11.13

dency toward the popcorn effect from plastic-encapsulated integrated circuits near their expiry date. In addition, a parametric damage to memory integrated circuits processed around 250°C is possible. As mentioned earlier, PCB and BGA polymeric substrates and solder masks may also suffer from higher processing temperatures. The plastic insulation of connectors may also become distorted. All these situations pose a great challenge to material scientists and design engineers as far as finding solutions.

11.13

OTHER CONCERNS

The corrosion and electromigration tendencies of the new alloys need to be measured. Pb-free solder on Pb solder, Pb-free solder on Pb-free solder, pastes, and fluxes need to be evaluated. Since solder without Pb is different in appearance and is more difficult to monitor via x-ray, new standards for visual and x-ray inspection are needed.

11.14

CONSORTIUM ACTIVITY

There are many coordinated efforts addressing the lead-free challenge. In North America, the NCMS has dedicated $10 million over four years, with reports released in August 1997. The National Institute of Standards and Technology is also active in participating in Pb-free programs. Currently, NEMI is most active in leading the industry in finalizing the options for Pb-free soldering processes. In Japan, the New Industry and Industrial Technology Development Organization has committed 350 million yen over two years to find the answers, while in Europe, Improved Design Life and Environmentally Aware Manufacture of Electronic Assemblies by Lead-Free Soldering, a six-member European collaboration supported by the Brite-Euram project of the European Commission, is scheduled for a 3-year project (May 1996 to April 1999). ITRI has been involved in developing Pb-free solder options since the early 1990s.

11.15

OPINIONS OF CONSORTIA

In the United States, the NCMS recommends three alloys: Sn96.5/Ag3.5, Sn91.7/Ag3.5/Bi4.8, and Bi58/Sn42. NEMI maintains that SnAgCu without Bi (217 to 221°C) is the most reliable in the presence of Pb contamination. The highest-melt alloy with Bi is more manufacturable but the 96°C PbSnBi phase is an issue. The Brite-Euram project recommends Sn95.5/Ag3.8/Cu0.7 for general-purpose soldering. Other alloys with potential are Sn99.3/Cu0.7, Sn96.5/Ag3.5, and SnAgBi. In the UK, the Department of Trade and Industry perceives that the favored option varies depending on applications: high professional group (automotive, military)— SnAgCu(Sb); medium professional group (industrial, telecoms)—SnAgCu, SnAg; general consumer and low professional group (TV, audio-video, office equipment)— SnAgCu(Sb), SnAg, SnCu, SnAgBi. JEIDA favors SnAgCu (before Pb-free components are available) and SnAgBi (after Pb-free components are available). In Germany, the favored alloys appear to be Sn96.5/Ag3.5 and Sn99/Cu1.

11.14

CHAPTER ELEVEN

11.16 WHAT ARE THE SELECTIONS OF PIONEERS? Following is the list of the selections or seriously considered candidates of some Pbfree pioneering companies. Since new data are being generated rapidly, the favored options may change with time. ● ● ● ● ● ● ● ● ● ● ● ● ●

●

Nortel. Sn99.3/Cu0.7 (N2) wave and reflow Motorola. Sn95.5/Ag3.8/Cu0.7 and Sn96.5/Ag3.5 (most likely) Ford. Sn96.5/Ag3.5 Texas Instruments. SnAgCuSb (NiPd finish) Delco. SnAgCu (probably) Nokia. Sn95.5/Ag3.8/Cu0.7 Ericsson. Sn95.5/Ag3.8/Cu0.7 Hitachi. Sn91.75/Ag3.5/Bi5/Cu0.7 NEC. Sn94.25/Ag2/Bi3/Cu0.75, Sn97.25/Ag2/Cu0.75, and SnZnBi Matsushita. Sn90.5/Ag3.5/Bi6 and SnAgBiX series Fujitsu. Sn42.9/Bi57/Ag0.1 Toshiba. SnAgCu Sony. Sn93.4/Ag2/Bi4/Cu0.5/Ge0.1 (claimed to have five times the reliability of SnPb) Solectron. May end up with a high-temperature and low-temperature alloy, but would prefer only one for bar, paste, and rework

11.17

POSSIBLE PATH

The goal of NEMI is to have North American companies capable of producing Pbfree products by 2001 with a total elimination of Pb-based products by 2004 (participating companies will determine the actual timing of deployment). The possible path to Pb-free soldering according to NEMI7 can be shown in the following list. However, this sequence may vary by manufacturer. ● ● ● ● ●

SMT solder pastes and rework Board finishes Component metallization Wave soldering Internal component interconnects The implementation sequence expected by IPC is as follows, with no time schedule: Phase 1. Wave solder/solder paste used to manufacture products are Pb free. Phase 2. PWB finishes are Pb free and phase 1 is implemented. Phase 3. Pb-free component finishes are in place and phases 1 and 2 are implemented.

GLOBAL STATUS OF LEAD-FREE SOLDERING

11.15

Most likely the last industries that will be affected by this issue will be military and aerospace, which rely on unique, high-reliability products. On the other hand, consumer electronics, which usually carry a 2- to 3-year life expectancy, will easily become the primary focus in the initial stage. The experience accumulated at this first stage will be applied for future products that may have more stringent reliability requirements. It should be realized that lead-free implementation most likely will not be a concerted process, and overlap between phases should be expected. As a result, the choice of materials and processes for any phase should be compatible with those for other phases. As reported at the NEMI meeting,12 the Japanese scenario appears to be taking a cautious step, as shown in the following list: ●

●

Initial implementation of SnAgBiX in low-tier products; convert high-tier products when Pb-free components are available or utilize SnAgX alloys. Lower-temperature components usable vs. SnAgX (5 to 10°C higher).

11.18

IS Pb-FREE SAFE?

While the industry is moving quickly toward Pb-free soldering processes, and while everything seems to fall into place as far as supporting a green world, an odd question is asked: “Is Pb-free solder environmentally safe?” According to a recent study,4 five Pb-free solders—Sn96.3/Ag3.2/Cu0.5, Sn96.5/Ag3.5, Sn98/Ag2, Sn99.3/Cu0.7, and Sn95/Sb5—were leached using EPA methods designed to simulate waste disposal and groundwater contact. The results indicate that Sb and Ag alloys failed every test. SnCu has least environmental impact. Sn did not leach significantly, due to low solubility of Sn salt in water. Since both Sb and Ag elements—particularly Ag—are very likely to be included in the Pb-free alloy alternatives, these data definitely demonstrate that the road to a Pb-free soldering world may be bumpier than anticipated.

11.19

SUMMARY

Lead-free soldering for the electronics industry is a segment of the global trend toward a lead-free environment. Although initiated in the U.S. in early 1990s, it advanced much more rapidly in Japan and Europe. This differentiation in Pb-free progress triggered great concerns among users of Pb-containing solders about maintaining business opportunities, therefore further expediting the advancement of Pbfree soldering programs. The favored Pb-free solder alternatives vary from region to region. However, in general, high-tin alloys are preferred, including SnAg, SnCu, SnAgCu, SnAgBi, and various versions of those alloys with additions of small amounts of other elements, such as Sb. SnAgBi systems are used in some Japanese products already. However, SnAgCu systems are more tolerant toward Pb contamination than Bi-containing systems and therefore are more compatible with existing infrastructures for the transition stage. Pb-free surface finishes for PCBs include OSPs, immersion Ag, immersion Au/electroless Ni, hot-air solder leveling SnCu, SnBi, electroless Pd/electroless Ni, electroless Pd/Cu, and Sn. The challenge for components is greater than for solder materials or PCBs. Although some Pb-free

11.16

CHAPTER ELEVEN

surface finishes for components exist, such as Sn, PdNi, Au, Ag, NiPd, NiAu, AgPt, AgPd, PtPdAg, NiAuCu, Pd, and Ni, their performance remains to be verified. In addition, options for higher-melting-temperature solder are still not available for high-temperature applications, including first-level interconnect within the components. Thermal damage can be a concern for both PCBs and components.

11.20

INFORMATION RESOURCES

11.20.1

Legislation

Europe ●

Waste Electrical and Electronic Equipment Directive (WEEE) www.itri.co.uk/WEEE2.htm www.smtuk.demon.co.uk/ www.itri.co.uk/index.htm

Asia No legislation Americas ●

●

EPA information on Toxic Release Inventory Rule—www.epa.gov/tri/tri_pb_ rule.htm EPA information on elements—www.epa.gov/opptintr/pbt

11.20.2 INITIATIVES FROM INDEPENDENT CORPORATIONS AND ELECTRONICS INDUSTRY ORGANIZATIONS Europe ● ● ●

Department of Trade and Industry (DTI) Industry Evaluation of Lead-Free Soldering (IDEAL) International Tin Research Institute (ITRI)—www.itri.co.uk

Asia ●

●

●

● ●

●

Japanese Ministry of International Trade and Industry (MITI)—www.miti.go.jp/ index-e.html Japan Electronic Industry Development Association (JEIDA) www.jeida.or.jp/guide/gaiyou/index-e.html www.jeida.or.jp/document/geppou/etc/9802narmari.html Japanese Institute of Electronic Packaging (JIEP)—www3.famille.ne.jp/∼jiep/ index.html Japan Printed Circuit Association (JPCA)—www.ipc.org/html/nr7042.htm New Industry and Industrial Technology Development Organization (NEDO)— www.nedo.go.jp/index-e.html Matsushita (Panasonic) www.panasonic.co.jp/environment/98e/09e.htm www.panasonic.co.jp/environment/98e/13ae.htm

GLOBAL STATUS OF LEAD-FREE SOLDERING ● ● ● ●

11.17

Sony—www.sel.sony.com/semi/PDF/LeadFreePkg.pdf Toshiba—www.toshiba.com NEC—www.nec.co.jp/english/profile/kan/action/action.html Fujitsu—www.fujitsu.co.jp

Americas ● ● ● ●

● ●

National Center for Manufacturing Sciences (NCMS)—www.ncms.org National Institute of Standards and Technology (NIST)—www.nist.gov National Electronics Manufacturing Initiative (NEMI)—www.nemi.org IPC www.ipc.org/html/nr9071.htm www.leadfree.org Lehigh University—www.lehigh.edu/∼dj10/Research1.html High Density Packaging User Group International, Inc.—www.hdpug.org

11.20.3 ●

VIABLE ALLOYS UNDER CONSIDERATION

SnAgCu (patents—www.patents.ibm.com/patlist?icnt=US&patent_number= 5527628, JP5050286, Japan 08-215880)

REFERENCES 1. National Center for Manufacturing Sciences, “Lead and the Electronic Industry: A Proactive Approach,” May 1995. 2. Sax, N. I., Dangerous Properties of Industrial Materials, 6th ed., Van Nostrand Reinhold, New York, 1984. 3. JEIDA, “Lead-Free Solder Roadmap—A Scenario for Commercial Application,” www.jeida.or.jp/document/geppou/etc/9802namari.html, February 3, 1998. 4. Smith, E. B. III, and L. K. Swanger, “Are Lead-Free Solders Really Environmental Friendly?” SMT, 64–66, March 1999. 5. IPC Leadfree Website, www.leadfree.org, August 2001. 6. HDP User Group International, Inc., “Lead Free Soldering 1,” doc number Proj032, Rev A, June 1999. 7. NEMI, Lead Free Task Meeting, Northbrook, IL, May 26, 1999. 8. Evans, H., “EU Parliament’s Environment Committee Amends Waste Directives,” 703907-7576; [email protected]. 9. Gibbs, F., “Pb-Free Interconnect,” NEMI Lead Free Meeting, Chicago, May 25, 1999. 10. Samsung Electronics, “Samsung Electronics Develops Environmentally-Friendly Memory Module,” M2 Communications, May 9, 2001. 11. www.nec.co.jp/english/profile/kan/action/action.html 12. Bradley, E., “Overview of No-Lead Solder Issue,” NEMI meeting, Anaheim, CA, February 23, 1999. 13. Buetow, M., “The Latest on the Lead-Free Issue,” Technical Source, IPC 1999 Spring/ Summer Catalog.

11.18

CHAPTER ELEVEN

14. www.epa.gov/tri/tri_pb_rule.htm 15. Business Wire, July 12, 2001. 16. Furusawa, A., K. Suetsugu, A. Yamaguchi, and H. Taketomo, “Thermoset Pb-Free Solder Using Heat-Resistant Sn-Ag Paste,” National Technical Report, 43(1), February 1997. 17. Huang, B. L., and N. C. Lee, “Prospects of Lead Free Alternatives For Reflow Soldering,” Proceedings of IMAPS’99, Chicago, October 28, 1999. 18. Beghardt, E., and G. Petzow, “Ueber den Aufbau des Systems Silber-Kupfer-Zinn,” Zeitschrift fuer Metallkunde, 50:597–605, 1959. 19. Handwerker, C., “NCMS Lead Free Solder Project: A National Program,” NEMI Lead Free Solder Meeting, Chicago, May 25, 1999. 20. www.e-insite.net/epp/index.asp?layout=article&articleId=CA84263, e-mail from E. Bradley, June 21, 2001. 21. www.sel.sony.com/semi/PDF/LeadFreePkg.pdf, Suganuma, K., “Japan Leadfree 2001,” ISIR, Osaka University.

CHAPTER 12

DEVELOPMENT OF LEAD-FREE SOLDER ALLOYS 12.1

CRITERIA

There are many lead-free solders available in the industry. However, most of them are not considered viable options. The criteria for an acceptable lead-free solder alternative are as follows: ● ● ● ● ● ●

Nontoxic Available and affordable Acceptable processing temperature Acceptable wetting Forms reliable joints Material manufacturable

These criteria are key points of commonsense consideration. Quantified corresponding criteria primarily based on National Center for Manufacturing Sciences (NCMS) Pb-Free Solder Project consideration are shown in Table 12.1.1 Since 240°C is considered the maximum acceptable component temperature during assembly, and since soldering temperature typically is at least 15°C above liquidus temperature, the maximum acceptable liquidus temperature should accordingly be 225°C. On the other hand, a narrow pasty range is considered essential for preventing rupture during wave soldering as well as for achieving good wetting. Both wetability and area of coverage reflect the wetting ability of solders. Methods for determining wetability can include either reflow spread factor testing or wetting balance testing. The latter method is more meaningful for wave soldering applications. Thermomechanical fatigue, coefficient of thermal expansion, creep, and elongation provide good insight into the reliability of solder joints. Elongation also provides a clue on ductility, which is critical to the manufacturability of solders, such as solder wire or solder preforms.

12.2

TOXICITY

Toxicity information for elements that are potential solder constituents is shown in Table 12.2.1,2 Due to incomplete data, direct comparison among elements is often difficult. In addition, depending on the type of toxicity investigated, rankings may change. Rankings may also be affected by perceptions as a result of historical usage in human society. The ranking of elements in terms of increasing toxicity according to various criteria is shown in the following list. ●

OSHA PEL and ACGIH TLV. Bi < Zn oxide fume < Sn (inorganic) < Cu (dust) < Sb (and compounds) < Sn (organic) < Cu (fume) < In (and compounds) < Ag (dust and fume) < Ag (and soluble compounds) < Pb (inorganic) 12.1

Copyright © 2003 by The McGraw-Hill Companies, Inc. Click here for terms of use.

12.2 ●

●

CHAPTER TWELVE

Chronic toxicity. Bi < In < Zn (oxide) < Cu < Ag < Sn < Sb < Pb Surface Mount Council report.3 Bi < Zn < In < Sn < Cu < Sb < Ag < Pb

Table 12.2 shows toxicity ranking of elements.1,2 Pb is considered highly toxic due to the long history of human Pb toxicity problems and its well-documented impact on the young and elderly, although its LDLo value is higher than those of most other elements in Table 12.2. Cd, which is not listed in Table 12.2, is regarded as a carcinogen by the International Agency for Research on Cancer and is not considered an option. Sb has the same LDLo value as Cd and is highly toxic when inhaled or ingested; therefore, its use in solder should be minimized. Ag and Cu are probably similar, although Ag may be slightly higher in toxicity. Sn exhibits a moderately low toxicity, while Bi, Zn, and In are considered to cause low or no toxicity.

TABLE 12.1 Criteria for Alloy Selection Property

Acceptable levels

Notes

Toxicity

Considerably lower than that of Pb

Supply

Sufficient supply for 80% conversion

Cost

<$10/lb in bulk form

Solidus temperature

>Operating temperature considered

−55 to +100°C for consumer electronics and telecommunications −55 to +125°C for military electronics −55 to +180°C for aerospace and automotive electronics

Liquidus temperature

<225°C

To prevent component thermal damage

Pasty range

<30°C

To prevent rupture during wave soldering

Wetability

Comparable to eutectic Sn/Pb

Area of coverage

>85%

Thermomechanical fatigue

>75%

Of eutectic Sn/Pb

Coefficient of thermal expansion

<29 ppm/°C

Prevents local stress on solder joints

Creep

>500 psi

To cause failure in 10,000 min at room temperature

Elongation

>>10%

Under uniaxial tension at room temperature; also important for fabricating solder wires and preforms

On Cu in dip test

12.3

DEVELOPMENT OF LEAD-FREE SOLDER ALLOYS

TABLE 12.2 Toxicity Ranking of Elements Presented in Order of Increasing Occupational Chronic Toxicity

Element

LDLo (mg/kg body weight)

Bi

15

Moderate toxicity: heart, liver, lungs

None

None

None

In

10†

High toxicity: lungs, gastrointestinal tract

Irritation

None, related solely to indium metal

0.1 (any compound)

Zn

124‡

Minimal toxicity: skin

Irritation (oxide)

Metal fume fever (oxide)

5 (oxide fume)

Cu

0.12‡

High toxicity: reproductive organs, possible carcinogen and teratogen

Irritation (dust, mist)

Irritation, metal fume fever

1 (dust)

Ag

1§

High toxicity: skin

None

Permanent discoloration of skin, eyes, mucous membranes; irritation; metal fume fever

0.1 (dust and fume); 0.01 (Ag and soluble compounds)

Moderate to low toxicity: gastrointestinal tract

Irritation

Difficulty breathing

2 (inorganic); 0.1 (organic)

High toxicity (oral): heart, liver, lungs

Irritation

Emphysema, pulmonary edema

0.5 (Sb and compounds)

High toxicity: nervous system, carcinogen of lungs, suspected teratogen

None

Nervous system effects, anemia, kidney damage; reproductive and developmental effects

0.05 (inorganic)

Sn

No value found

Sb

15

Pb

450‡

Effects

Acute toxicity

Chronic toxicity

OSHA PEL and ACGIH TLV* (mg/m3)

* For a 5-day workweek with 8-h workdays. † LDLo based on animal studies; high toxicity when injected, low toxicity when inhaled. ‡ Toxic dose, lower limit. § Toxic concentration, lower limit (mg/m3). ACGIH, American Conference of Government Industrial Hygienists; LDLo, lethal dose, lower limit; OSHA, Occupational Safety and Health Administration; PEL, Permissible Exposure Limit; TLV, threshold limit value.

However, the selection or elimination of an element for solder should not only consider the toxicity of the element itself, but also the overall quantity of the element to be used in an electronic product. Figure 12.1 shows the chemical content of a printed circuit board for a mobile product. The estimated overall contribution of metallic elements on toxic potential can be roughly ranked in decreasing order as shown here: Pb > Cu > Ni > Ag > Al > Sn > Au

12.4

CHAPTER TWELVE

FIGURE 12.1 Chemical content of a printed circuit board of a typical mobile product.4 Light columns: material mass. Dark columns: material assessment by means of toxic potential indicator (TPI).

Many of these metallic elements, such as Cu and Ag, are not primarily used as solder. Cu is used as the circuitry conductor or ground plane, while Ag may be used as a thick film material or a surface finish.As long as Cu and Ag continue to be used for those applications, eliminating them from solder materials due to toxicity considerations is virtually meaningless.

12.3

COST AND AVAILABILITY

The cost and availability of potential elements to be used in solders are shown in Table 12.3.5 With Pb being the cheapest element, all Pb-free alternatives are destined to be more expensive than eutectic Sn-Pb solder. Zn, Cu, and Sb are relatively low in cost; however, it is questionable that they can serve as essential constituents. The high cost of Ag and In suggests that those elements should not compose more than a small percentage of the solder. The limited availability of Bi and In imparts constraints on using them as significant constituents.

12.4 12.4.1

DEVELOPMENT OF LEAD-FREE ALLOYS Existing Alloys

The first group of Pb-free solder candidates is the existing Pb-free alloys. This includes (1) binary eutectic Sn-containing alloys, such as Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-In, Sn-Sb, and Sn-Zn, (2) noneutectic binary Sn-containing alloys,6 such as 97.5Sn-2.5Ag (melting range 221 to 226°C), 95Sn-5Ag (221 to 240°C), 90Sn-10Ag (221 to 295°C), 97Sn-3Cu (227 to 300°C), and 60Sn-40Bi (138 to 170°C), (3) Pb-free

DEVELOPMENT OF LEAD-FREE SOLDER ALLOYS

12.5

TABLE 12.3 Cost and Availability of Elements

Element

Cost ($/lb, as of Feb. 3, 1999)

Density (lb/in3)

Annual U.S. consumption (millions of lb)*

Availability

Pb

$0.45

0.41

7040

Available

Zn

$0.50

0.258

1560

Available

Cu

$0.65

0.324

4900

Available

Sb

$0.80

0.239

100

Available

Bi

$3.40

0.354

9

Sn

$3.50

0.264

180

Limited

Ag

$84.20

0.379

3.5

Limited

In

$125.00

0.264

0.2

Scarce

Available

* As defined by the U.S. Bureau of Mines.

alloys without tin,6 such as 97In-3Ag (143°C), 99.3In-0.7Ga (150°C), 95In-5Bi (125 to 150°C), 67Bi-33In (109°C), and 88Au-12Ge (356°C), and (4) other Pb-free alloys,6 such as 65Sn-25Ag-10Sb (233°C), etc. Many of the materials in this group, particularly the binary eutectic Sn-containing alloys, have been used by the electronics industry for many years, and their properties and performance are well understood.

12.4.2

MODIFICATION

The second group of candidates is newly modified preexisting alloys. Modification is often accomplished by addition of a small amount of additional elements, such as Ag, Cu, Bi, In, Sb, Ge, P, Ni, Fe, Au, Ga, or Co, with the goals of improving the wetability, bond strength, oxidation resistance, and impurity tolerance level; reducing the melting temperature; refining the grain structure, and so on. 12.4.2.1 Wetting. The wetting process is favored by a low-surface-energy solder, which often can be regulated by addition of impurities. The general rule is that a small amount of surface-active impurity, usually low in surface energy, can produce a marked decrease in surface energy, while similar amounts of a surface-inactive impurity do not produce more than a very small rise in surface energy. It follows that the effects of surface-inactive impurities on solder should be too small to have any significant effect on wetting behavior.7 Figure 12.2 shows the effect of impurities on surface energies for some relevant binary systems with tin. The effect of the surface energy of additives on the surface energy of alloys can be further illustrated by examining the 60Sn-40Pb system. Surface tension isothermals (250°C) for 60Sn-40Pb with 0 to 4 percent Bi or 0 to 5 percent Sb show a nonlinear fall with increasing ternary addition, which may be explained by the low surface tension of the third elements. Surface tension isotherms for 60Sn-40Pb with 0 to 2 percent Ag (215 and 250°C) or 0 to 0.6 percent Cu (250°C) indicate higher values with increasing ternary addition, which may be explained by the higher surface tension of the third elements. However, there are exceptions to this rule; for example, increasing ternary addition of low-surface-tension P at 0 to 0.013 percent results in a higher surface tension.8

12.6

CHAPTER TWELVE

FIGURE 12.2 Effect of impurities on surface energies.

Another driving force for wetting is the rate of formation of intermetallic compounds. Since formation of intermetallics involves reaction between solder and base metal, this inevitably results in more spreading or more wetting. Accordingly, a higher formation rate typically results in a better wetting. The ability of Sn to easily form intermetallics with many metals is the primary reason it is the essential constituent in many solder alloys. Addition of other elements may affect the formation rate of intermetallics, thus affecting the wetting. Table 12.4 shows the common intermetallic compounds encountered in the electronics industry. 12.4.2.2 Melting Temperature and Bond Strength. Since tin, which is often the preferred primary constituent, exhibits a melting point of 232°C, additives that can lower the alloy melting temperature are often desired in order to minimize thermal damage to both components and boards. Although several elements such as Hg and Cd are capable of lowering the melting temperature of alloys, Bi and In are the two most commonly utilized elements for Pb-free solder applications due to their benign nature. Furusawa et al.9 reported that the addition of small amounts of some additive elements would reduce the melting temperature and the bond strength, but would initially increase the wetting of solders, then reach a maximum, then decrease wetting, as shown in Fig. 12.3. The wetting phenomenon observed in this case suggests that the relationship between wetting and surface energy may only be a secondary effect. The effect of additives on melting temperature seems to be applicable to Bi and In as additives, and is supported by the studies on the effect of Bi addition on Sn-Zn,10 Sn-3.5Ag,11 and Sn-Ag-Cu10 systems, including Sn-3.5Ag-1Cu,12 as shown in Figs. 12.4 through 12.6. It is also supported by the effect of In addition on Sn-3.5Ag,12 as shown in Fig. 12.5. Besides Bi and In, a number of other elements, such as Mg, Ag, Cu, Al, Ga, and Zn, also exhibit a melting temperature depression effect, as shown in Table 12.5.13 The effect of additives on bond strength reported by Furusawa also appears to be applicable to Bi and In as additives. Therefore, the effect of Bi content on the pull strength of the Sn-3.5Ag-Bi system (see Fig. 12.6) and the effect of addition of In and Bi on the tensile strength of the Sn-3.5Ag-1Cu alloy12 (see Fig. 12.7) all exhibit a decrease in mechanical strength with increasing content of additives.

DEVELOPMENT OF LEAD-FREE SOLDER ALLOYS

12.7

TABLE 12.4 Common Intermetallic Compounds Encountered in the Electronics Industry Solder

Substrate metallization

Intermetallic compound

Au-based

Cu-based

Au3Cu, AuCu, AuCu3

Au-based

Pb-based

AuPb2, Au2Pb Au2Bi

Bi-based

Au-based

Bi-based

In-based

BiIn, Bi3In5, BiIn2

In-based

Cu

Cu11In9, Cu4In, Cu2In

In-based

Au-based

Au7In, Au4In, Au3In, Au7In3, Au3In2, AuIn, AuIn2

In-based

Ag-based

Ag3In, Ag2In, AgIn2

In-based

Ni

Ni3In2, Ni3In, NiIn, Ni2In3

In-based

Sn solder coating

In3Sn, InSn4

Sb-based

Brass or Zn coating

ZnSb, Zn3Sb2

Sb-based

Cu-based

Cu3Sb, Cu5.5Sb, Cu4.5Sb, Cu3Sb, Cu3.3Sb, Cu2Sb

Sb-based

Ag-based

AgSb, Ag3Sb

Sb-based

Au-based

AuSb2

Sn-based

Cu

Cu6Sn5, Cu3Sn

Sn-based

Au-based

AuSn, AuSn2, AuSn4

Sn-based

Ag-based

Ag3Sn

Sn-based

Pd-based

PdSn4

Sn-based

Ni

Ni3Sn4

It should be pointed out that Furusawa’s observation on the relation between addition and wetting is not well supported by the work on Bi. Zhao et al.12 reported that for the Sn-3.5Ag-1Cu system, wetting improves with increasing addition of In but deteriorates with increasing addition of Bi, as shown in Fig. 12.8. The adverse effect of Bi on wetting cannot be explained by its reduced surface tension, as shown in Fig. 12.2. Presumably this can be attributed to the poor wetting ability of Bi itself.

(a)

(b)

FIGURE 12.3 Effect of additive amount on solder melting point, joint bond strength, and wetting (spread factor).

12.8

CHAPTER TWELVE

FIGURE 12.4 Effect of Bi content on the melting range of Sn-Ag-CuBi and Sn-Zn-Bi determined by differential scanning calorimeter.

It has been reported that, based on the wetting study on a series of eutectic binary solder alloys, the ability to promote spreading for several elements can be ranked as follows: Sn > Pb > Ag > In > Bi.14 Ackroyd et al.15 studied the effect of additives on the wetting of 60Sn-40Pb. Results indicate that Al, Sb, As, Cd, P, S, and Zn all cause a decrease in spread area. Bi shows adverse effects on steel and brass but no effect on Cu. On the other hand, Cu addition causes a decrease in spread area on steel but a slight increase on brass. 12.4.2.3 Oxidation Resistance. Elements such as P are sometimes used as deoxidants in the production of Cu and solders from secondary metals.15 At levels of 0.01 percent, P significantly reduced the oxidation of 60Sn-40Pb at all temperatures in the stirring tests.14

FIGURE 12.5 Effect of addition of In or Bi on the melting temperature of Sn-3.5Ag-1Cu alloy.

12.9

DEVELOPMENT OF LEAD-FREE SOLDER ALLOYS

FIGURE 12.6 Effect of Bi content on Sn-3.5Ag-Bi alloys.

12.4.2.4 Grain Structure. Creep is deformation of materials with time under a given tension or shear load. Creep occurs via thermally activated processes. It is important when the service temperature exceeds half the melting temperature (in degrees kelvin) of solder. Creep is the most important deformation mechanism of solder.16 Depending on the stress level, the deformation mechanism can be divided into three phases.17 With increasing stress τ, the creep mechanisms shift from dislocation climb-controlled bulk creep to grain boundary slide-controlled intergranular creep to dislocation glide-controlled creep. At high stress, the deformation mechanism undergoes transition to tertiary creep and elongation to failure. The creep is sensitive to microstructure, and the mechanisms include (1) onset of cavitation damage at grain boundaries and (2) plastic instability leading to inhomogeneous deformation. Morris et al.18 reported that cavitation is responsible for tertiary creep in bulk solder samples tested in tension. CavTABLE 12.5 Effect of Additive Elements in Depressing Melting Temperature of Sn-Binary Alloys Melting temperature depression (°C/wt%) Additive element

160–183°C

184–199°C

200–230°C 1.8

In

2.3

2.1

Bi

1.7

1.7

1.7

Mg

—

—

16.0

Ag

—

—

3.1 (above 221°C)

Cu

—

—

7.1 (above 227°C)

Al

—

—

7.4 (above 228°C)

Ga

2.6

2.5

2.4

Zn

—

3.8 (above 198°C)

—

12.10

CHAPTER TWELVE

FIGURE 12.7 Effect of addition of In and Bi on the tensile strength of Sn-3.5Ag-1Cu alloy.

ities nucleate primarily at three- or four-grain junctions. They grow with strain and merge to form larger voids to cause failure.This process is aggravated by (1) increase in grain size, which enhances the stress concentration at grain junctions; (2) irregular grain shapes, which introduce sites of unusual stress concentration; and (3) (possibly) intergranular precipitates, which constrain deformation at grain boundaries, thus resulting in uneven stress distribution. Plastic instability mainly incurs at shear bands, which often follow planes of microstructural weakness, such as phase boundaries and colony boundaries in eutectic materials.19,20 The development of shear bands is particularly pronounced in solders exhibiting unstable, eutectic microstructures that are easily recrystallizable, such as eutectic Sn-Pb. In these solders, the incipient shear bands cause development of the well-defined recrystallized bands for joints that are crept or fatigued in shear. Such a localized recrystallized material, usually observed near an intermetallic layer, accelerates damage processes and shortens the fatigue life of solder joints. Since a larger grain size results in a higher creep and failure rate, a microstructure with a refined grain structure is typically desired. In general, this is considered one

FIGURE 12.8 Effect of addition of In or Bi on the wetting angle of Sn-3.5Ag-1Cu alloys.

DEVELOPMENT OF LEAD-FREE SOLDER ALLOYS

12.11

of the most effective methods for improving the reliability of solder alloys, and is often accomplished through the addition of a small amount of elements such as Cu, Zn, As, Fe, or Ag into the alloy. These elements often precipitate at the grain boundary, thus retarding the further growth or recrystallization of the grains in the solder. For example, addition of 1 percent Cu dramatically slows coarsening of eutectic Sn-Bi.21–23 On the other hand, addition of insoluble dispersoid Fe particles using a magnetic distribution technique forms a three-dimensional network of finely dispersed iron particles in a Bi-43Sn eutectic solder. These iron particles reduce the coarsening and the onset of tertiary creep of 57Bi-43Sn, thus improving the microstructural stability, raising the service temperature, and resulting in a fivefold increase in creep resistance at 100°C.24–27 The addition of 1 percent Zn significantly improves the mechanical strength of 95.5Sn-3.5Ag alloy by as much as 48 percent while maintaining the same level of ductility. It also significantly improves creep resistance. The high-temperature creep resistance of Zn-containing alloy is improved more than an order of magnitude. Strengthening is attributed to a substantial refinement of and more spherical Ag3Sn precipitates in the solidification microstructure. In this case, Zn is incorporated in the more corrosion-resistant Ag3Sn precipitates. These precipitates suppress the formation of Sn dendrites and leave the Sn-rich matrix primarily free of Zn in solid form.28,29 The addition of a small amount (<1 percent) of Cu in 95Sn-3.5Ag-1Zn-0.5Cu alloy refines the effective grain size while retaining uniform distribution of Ag3Sn precipitates in the solidification microstructure, thus dramatically improving ductility in the 95.5Sn-3.5Ag-1Zn alloy. The quaternary 95Sn-3.5Ag-1Zn-0.5Cu alloy has better mechanical properties than 96.5Sn-3.5Ag because it has a uniform fine dispersion of precipitates and small effective grain size. However, addition of Cu or Zn > 1 percent is not desirable as it causes precipitates of additional intermetallic compound phases that deplete the finely dispersed precipitates in the surrounding matrix and induce nonuniformities in the microstructure that consequently deteriorate the mechanical properties.30 AT&T reported that small alloying additions of Ag dramatically improve the mechanical properties of 87Sn-8Zn-5In alloy (melting point 188°C) due to elimination of the coarse and nonuniform distribution of platelike dendrites and refining effective grain size in the solidified microstructure.25 However, care should be taken in the selection of elements because some elements may cause grain coarsening. For instance, addition of 0.001 percent Co to eutectic Sn-Bi inhibits dissolution of Cu and coarsens the microstructure relative to the solidified structure of the alloy in pure form or with small additions of As, Fe, or Cu.21–23 12.4.2.5 Impurity Tolerance. Some impurity elements have significant adverse impact on soldering performance and physical properties. The sensitivity of solder toward impurities is a function of the impurity element.15 Table 12.6 shows the detrimental effect of some impurities on the properties of 60Sn-40Pb. The tolerance of solder alloys toward impurities may be increased by the addition of some other elements. For instance, Mei et al. studied the effect of Pb contamination on Sn-Bi eutectic and found that formation of an Sn-Pb-Bi ternary eutectic phase resulted in drastic failure of the solder. The Pb dissolves into molten Bi-Sn during the soldering process, resulting in the formation of a 52Bi-30Pb-18Sn (melting point 96°C) ternary eutectic structure in the solidified solder joint. The solder joints became mechanically weak when subjected to thermal cycling at temperatures exceeding 96°C because the low-melting-point ternary eutectic phase

12.12

CHAPTER TWELVE

TABLE 12.6 Lowest Impurity Levels Producing Detrimental Effect on a 60Sn-40Pb Solder Impurity element Ag

Al

As

Au Bi

Cd Cu

Impurity, % 2

0.0005

Effect ●

Increases spread and strength of solder; grittiness in excess of solubility.

●

Ag3Sn intermetallic compound is soft, ductile, and nonembrittling.

●

Oxide-promoting element; causes a lack of adhesion, grittiness, and dull solder surface.

●

No dewetting on Cu or brass; 0.001% showed onset of dewetting on steel and nickel.

●

Sb eliminates Al by promoting rapid drossing out of AlSb compound.

0.2

●

25% decrease in area of spread.

0.005

●

Dewetting and grittiness on brass, probably due to formation of As-Zn intermetallic compound.

0.1

●

Gritty joints and surfaces.

●

Weakens solder dramatically at 4%.

●

Discoloration and oxidation of solder coating.

●

Very slightly reduces the area of spread.

●

Increases the rate of spread.

●

25% decrease in area of spread.

●

Dull surface due to oxide film.

●

Grittiness due to Cu-Sn intermetallic compound.

●

Excessive solder increases the liquidus temperature of the solder, making it more viscous or sluggish.

●

Negligible effect on wetting.

0.5

0.15 0.29

Fe

0.02

●

Grittiness of solder coating.

Ni

0.05

●

Grittiness at over 0.02%.

P

0.01

●

Deoxidant.

●

Dewetting at 0.012% on Cu and steel.

●

Grittiness at 0.1% on Cu.

●

Additions up to 0.25% produce no dewetting effects, but give a severe gritty appearance of the solder coating due to the presence of discrete intermetallic compound particles of SnS and PbS.

●

Powerful grain refiner.

●

Area of spread decreases slightly with increase in Sb content.

●

Prevents transformation of beta Sn to alpha Sn at subzero temperatures.

●

Drosses out An, Al, and Cd from solder.

●

Oxide-forming element.

●

Dewetting at 0.001%.

●

Loss of solder brightness at 0.005%.

S

Sb

Zn

0.0015

1

0.003

DEVELOPMENT OF LEAD-FREE SOLDER ALLOYS

12.13

accelerated grain growth and phase agglomeration. The addition of small amounts of indium (2 to 3 percent) into 58 Bi-42Sn solder may eliminate the formation of the ternary eutectic phase, as indicated by the disappearance of the ternary phase peak in differential scanning calorimeter measurements.31

12.5

LEAD-FREE ALLOYS INVESTIGATED

The Pb-free solder alloys investigated are summarized in Table 12.7.32 Also listed are the two controls, 63Sn-37Pb and 62Sn-36Pb-2Ag. The nomenclature of each alloy category is based on the elemental composition percentage, with the composition with a higher percentage listed first.

12.6

FAVORITE Pb-FREE ALLOYS

The favorite choice of Pb-free alloys differs from region to region, as discussed in the following text.

12.6.1

JAPAN

As discussed in Chap. 11, Japan is leading in terms of implementing Pb-free soldering processes. Although the selection of alloys in Japan is not standardized yet, the Japanese Electronic Industry Development Association (JEIDA) does provide recommendations about alloys based on applications, as shown in Table 12.8.106 The JEIDA recommendations can also be presented according to the melting temperature for mid–melting range applications, as shown in Fig. 12.9.105 Figure 12.10 shows the survey results on lead-free soldering implementation status in Japan conducted by Senju in April 2001.10 It is interesting to note the high overlap between JEIDA recommendations and industry implementation status, suggesting an active participation of Japanese industrial Pb-free soldering manufacturers in the JEIDA program. Due to the wide range of products in the electronics industry and the highly diversified coverage for major electronic manufacturers, the selection of Pb-free alloys may be a multiple choice. This phenomenon is well exemplified by Fig. 12.11, which shows the road map of Panasonic on Pb-free alloy development.11

12.6.2

EUROPE

The European consortium, BRITE-EURAM, recommends that 95.5Sn-3.8Ag0.7Cu be considered as an all-purpose alloy. Other alloys with potential are 99.3Sn0.7Cu, 96.5Sn-3.5Ag, and Sn-Ag-Bi. In the UK, the Department of Trade and Industry (DTI) provided its perception on Pb-free alloy choices as shown in the following list. ● ● ●

High professional group (automotive, military): Sn-Ag-Cu(Sb) Medium professional group (industrial, telecommunications): Sn-Ag-Cu, Sn-Ag General consumer and low professional group (TV, audio-video, office equipment): Sn-Ag-Cu(Sb), Sn-Ag, Sn-Cu, Sn-Ag-Bi

TABLE 12.7 Pb-Free Solders Investigated

Alloy category

Composition

Solidus/ liquidus (°C) 183

Advantages

Structural coarsening; prone to creep.

Manufacturer or investigator NCMS (control)1

12.14

Sn-Pb

63Sn-37Pb

Sn-Pb-Ag

62Sn-36Pb-2Ag

Au-Sn

80Au-20Sn

280

Bi-Cd

60Bi-40Cd

144

Toxic.

Indium

Bi-In

67Bi-33In

109

Poor wetting on Cu.

Indium

179/180

Overall good properties, low cost. UTS 4442 psi. YS 3950 psi. Elongation 48%, YM 15.7 GPa.33 σ 464 dyn/cm,34 380 dyn/cm.35 UTS 27 MPa,36 SS 39 MPa.37

Disadvantages

NCMS (control)1

UTS 6904 psi, elongation 31%, YS 6287 psi, YM 18.0 GPa.33 Creep and corrosion resistant.

79

Hard and brittle; melting point too high; expensive.

Bi-In-Sn

57Bi-26In-17Sn

Bi-Sn

50Bi-50Sn

138/152

YS 8263 psi, UTS 8965 psi, elongation 21% and 53%.33

Wide pasty range.

NCMS33

52Bi-48Sn

138/151

YS 6414 psi, UTS 8834 psi, elongation 57%.33

Wide pasty range.

NCMS33

57Bi-43Sn

Bi-Sn-Ag

Melting point too low.

YS 7972 psi, UTS 8540 psi, elongation 77%.33 Good fluidity. UTS 8766 psi.1 Elongation 46%.33 Low σ, 349 dyn/cm,34 300 dyn/cm.35

NCMS

58Bi-42Sn

138

Strain rate sensitivity; poor wetting. Concerns: (1) eutectic 52Bi-32Pb16Sn (96°C); (2) Bi is byproduct of Pb mining. YM 11.9 GPa.33

95Bi-5Sn

134/251

Indium

56Bi-43.5Sn-0.5Ag

Ternary eutectic

NCMS33

57Bi-42.9Sn-0.1Ag

NCMS33

138/140

57Bi-42Sn-1Ag

BGA bend strength using 95.8Sn-3.5Ag-0.7Cu ball and 57Bi-452Sn-1Ag paste is 65% of that of Sn63 paste.38

HP39

57Bi-41Sn-2Ag

140/14733

YS 9487 psi, UTS 10,390 psi.33 Thermal fatigue life > Sn63 > 58Bi-42Sn.40

Elongation 31%.33

NCMS

56Bi-40.5Sn-2Ag1.5Sb

137/14533

YS 9063 psi, UTS 9946 psi.33

Low elongation, 27%.33

NCMS

55.5Bi-40Sn-3Ag1.5Sb

137/14733

YS 8665 psi, UTS 9379 psi.33

Elongation 45%.33 Wide pasty range.

NCMS

55Bi-40Sn-3Ag-2Sb

138/15033

YS 8984 psi, UTS 9807 psi.33

Elongation 44%.33 Wide pasty range.

NCMS

54Bi-39Sn-3Ag-2Sb

138/15433

Low elongation, 3.7%.33 Wide pasty range.

NCMS

Bi-Sn-Ag-Sb-In

54Bi-39Sn-3Ag-2Sb2In

99/13833

YS 5055 psi, UTS 11,640 psi.33

Low elongation, 13%.33 Very wide pasty range.

NCMS

Bi-Sn-Ag-Sb-Cu

54Bi-39Sn-3Ag-2Sb2Cu

YS 11,440 psi UTS 12,280 psi.33

Low elongation, 4%.33

NCMS

Bi-Sn-Cu

55Bi-42Sn-3Cu

>400

High Cu, wide pasty range, high liquidus, low elongation.33

NCMS

55Bi-43Sn-2Cu 48Bi-48Sn-4Cu

138/14033 >400

Elongation 41%.33 High Cu, wide pasty range, high liquidus, low elongation.33

NCMS NCMS

Bi-Sn-Ag-Sb

12.15

Bi-Sn-Fe

54.5Bi-43Sn-2.5Fe

Bi-Sn-In

56Bi-42Sn-2In

137 126/14033

YS 8985 psi, UTS 9478 psi.33

Creep and fatigue resistance.

Developmental stage.

AT&T

YS 7224 psi, UTS 8429 psi, elongation 116%.33

Quenched alloy shows ternary melting (99°C), 116% total elongation.33

IBM, NCMS

(Continues)

TABLE 12.7 Pb-Free Solders Investigated (Continued)

Alloy category Bi-Sn-In (cont.)

Composition

Solidus/ liquidus (°C)

57Bi-42Sn-1In

132/13833

57Bi-41Sn-2In

33

127/140

Advantages

Disadvantages Poor wetting.33

YS 7304 psi, UTS 8436 psi, elongation 72%.33

Manufacturer or investigator IBM NCMS Ford41

(37-57)Bi-(37-53)Sn(6-10)In

12.16

Bi-Sn-In-Cu

56.7Bi-42Sn-1In0.3Cu

132/13833

YS 8359 psi, UTS 8985 psi.33

Low elongation, 38%.33

NCMS, IBM

Bi-Sn-Sb

57Bi-41Sn-2Sb

141/15033

YS 8521 psi, UTS 9586 psi.33

Elongation 47%.33 Wide pasty range.

NCMS

57Bi-42Sn-1Sb

138/14933

YS 8285 psi, UTS 8944 psi, elongation 60%.33

Bi-Sn-Zn

55Bi-43Sn-2Zn

Bi-Sb

95Bi-5Sb

In-Ag In-Bi-Sn In-Sn

NCMS NCMS33

Ternary eutectic ∼275/ ∼308

97In-3Ag

143

90In-10Ag

141/237

48.8In-31.6Bi-19.6Sn

59

51.0In-32.5Bi-16.5Sn

60

60In-40Sn

118/127

52In-48Sn

118

50In-50Sn

118/125

Ford Poor wetting; expensive.

Indium Indium Indium

Au soldering.

Melting point too low; poor fatigue and mechanical properties; expensive.

Indium

Indium

Sn

100Sn

Sn-Ag

95Sn-5Ag 96.5Sn-3.5Ag

98Sn-2Ag

232

Wetting. UTS 21 MPa vs. 17.5 MPa for Pb,36 SS 26 MPa vs. 13 MPa for Pb.37

221/24542

No coarsening. UTS 10,100 psi, SS 8,400 psi.42

221

Good strength; creep resistance, Fatigue life 1.1 times that of Sn63,13 better than 95.5Sn-3.8Ag-0.7Cu, comparable with 99Sn-1Cu.43 Shear strength not affected by baking time and better than for Sn62.44 YM 26.2 GPa,33 56 GPa.45 UTS 55 MPa vs. 31–46 MPa for Sn6345 and 21 MPa for Sn.36 UTS 8900 psi, SS 4600 psi.42 SS 61.2 MPa46 vs. 26 MPa for Sn.37

Whisker and tin pest growth.

Indium

Welco Castings42 Poor isothermal fatigue at low strain; melting point slightly too high. Pad trace may crack due to high rigidity of solder.44 UTS 3873 psi, YS 3256 psi, elongation 24%,33 35% vs. 35–176% for Sn63.45 σ 493 dyn/cm.34

Indium

NCMS33

221/226

12.17

Motorola47

Sn-Ag-Au

Balance Sn-(12.2)Ag-(1-2.2)Au

Sn-Ag-Bi

93.5Sn-3.5Ag-3Bi

200/217 or 208/21733

SMT defect rate <50% of that for Sn63.11

Matsushita Nihon Handa

95.5Sn-3.5Ag-1Bi

219/220

Fatigue much better than for Sn63.

H-Technol13

94Sn-3Ag-3Bi

213

95Sn-3Ag-2Bi

216/22033

95.5Sn-2.5Ag-2Bi Sn-Ag-Bi-Cu

92.6Sn-3.3Ag-3Bi-

33

215/221

YS 5463 psi, UTS 7930 psi.1,33 33

YS 6592 psi, UTS 7564 psi.

Low elongation, 30%.33

NCMS

Low elongation, 26%.33

NCMS

204/216

Ref. 48

1.1Cu Sn-Ag-Bi-Cu-Ge

92.7Sn-3.2Ag-3Bi1.1Cu-1Ge

Tensile strength 1.8 times that of Sn63.49

Impact strength 16% that of Sn63.49

Japanese Solder

(Continues)

TABLE 12.7 Pb-Free Solders Investigated (Continued)

Alloy category

Composition

Solidus/ liquidus (°C)

Advantages

Disadvantages

Manufacturer or investigator

Balance Sn-(1-4)Ag(Ag+1.23Bi+0.52In) >5

Mitsui50

Sn-Ag-Bi-In-Zn

Balance Sn-(1-6)Ag(0.2-0.6)Bi-(0.20.6)In-(0.2-0.6)Zn

Lucent51

Sn-Ag-Bi-Sb

94Sn-2.5Ag-2Bi1.5Sb

219/22633

YS 7070 psi, UTS 8117 psi.33

Low elongation, 21%.33

NCMS

93Sn-3Ag-2Bi-2Sb

219/22633

YS 6918 psi, UTS 9212 psi.33

Low elongation, 36%.33

NCMS

12.18

Sn-Ag-Bi-In

(90.3-99.2)Sn-(0.53.5)Ag-(0.1-2.8)Cu(0.2-2)Sb

AIM52

Sn-Ag-Bi-Zn-Cu

(93.5-94)Sn-(2.53)Ag-(1-20bi-(12)Zn-1Cu

IBM53

Sn-Ag-Cd-Sb

95Sn-3.5Ag-1Cd0.5Sb

221/223

YS 7545 psi.33

93.6Sn-4.7Ag-1.7Cu 95Sn-4Ag-1Cu 95.5Sn-4Ag-0.5Cu

95.5Sn-3.9Ag-0.6Cu

NCMS,33 Alpha IBM54

(89.4-95.1)Sn-(33.8)Ag-(0.7-1.3)Cd(0.2-0.5)Sb Sn-Ag-Cu

Low elongation, 15%.33 Low usage, contains Cd.

217/24433

Sandia, Iowa State University

217/220 217/22533 or 221/23055 217

Published 50 years ago. Creep slower than for Sn63.56

Heraeus

Recommended by NEMI.

NEMI

95.5Sn-3.8Ag-0.7Cu

217/220

95.4Sn-3.6Ag-1Cu

217/ 217.946

Nokia and Multicore—yield and reliability equal or better than for Sn63. BRITE-EURAM project reports better reliability and solderability than for SnAg and SnCu, recommends this alloy for general-purpose use.

Nokia and Multicore, BRITEEURAM

SS 67 MPa.46

95.2Sn-3.5Ag-1.3Cu

NIST alloy, NCMS33

95.6Sn-3.5Ag-0.9Cu

217

Eutectic.

95.75Sn-3.5Ag0.75Cu

218

Creep rate much lower than for Sn63.57 Impact strength 2.5 times that of Sn63.49

96.1Sn-3.2Ag-0.7Cu 12.19

217/218

95.4Sn-3.1Ag-1.5Cu

216/217

97.25Sn-2Ag-0.75Cu Sn-Ag-Cu-Bi-Zn

Balance Sn-(3.57.7)Ag-(1-4)Cu(0-10)Bi-(0-1)Zn(Si, Sb, Mg, Ca, rare earth, miscellaneous metal <1)

Senju,58 Hitachi

NIST alloy, NCMS59

96.3Sn-3.2Ag-0.5Cu

96.5Sn-3Ag-0.5Cu

NIST Tensile strength 0.9 times that of Sn63.49

Alpha Low cycle fatigue life 2.4 times that of Sn63.13

H-Technol Harris60

220 33

217/219

NEC Iowa State University, Sandia61

(Continues)

TABLE 12.7 Pb-Free Solders Investigated (Continued)

Alloy category Sn-Ag-Cu-Co

Composition

Solidus/ liquidus (°C)

Advantages

95.27Sn-3.59Ag0.99Cu-0.15Co

217/ 218.546

SS 65.5 MPa.46

95.12Sn-3.59Ag0.99Cu-0.30Co

217/ 219.346

SS 56.1 MPa.46

94.98Sn-3.58Ag0.99Cu-0.45Co

217/ 218.946

SS 65.7 MPa.46

Disadvantages

Manufacturer or investigator

12.20

Sn-Ag-Cu-Ni

(91.5-96.5)Sn-(25)Ag-(0-2.9)Cu(0.1-3)Ni

Ford62

Sn-Ag-Cu-P-Ni

Balance Sn-(<10)Ag(<3)Cu-(0.05-1.5)P(0.05-1.5)Ni

Fukuda63

Sn-Ag-Cu-Sb

93Sn-3Ag-2Cu-2Sb 96.2Sn-2.5Ag-0.8Cu0.5Sb

221/22433

YS 6684 psi, UTS 7655 psi.33

Elongation 32%.33

NCMS

211/226

Low cycle fatigue life 2.4 times that of Sn63.13 Elongation 50% vs. 53% for Sn63; UTS 5730 psi vs. 4920 psi for Sn63; YS 4860 psi vs. 4380 psi for Sn63, YM 7420 ksi vs. 4870 ksi for Sn63.64

Slightly high melting point. UTS 3749 psi.1 YS 3311 psi.33 Low elongation, 9%.33 High σ, 510 dyn/cm.35

AIM (CASTIN)

216/217

Good fatigue life, high modulus and strain. UTS equals that of Sn63.65

33

93Sn-3Ag-2Cu-2Sb 95Sn-3Ag-1.5Cu0.5Sb

NCMS H-Technol65

(93-98)Sn-(1.53.5)Ag-(0.2-2)Cu(0.2-2)Sb

AIM66

Balance Sn-(3-5)Ag(0.5-3)Cu-(0-5)Sb

Senju58

Sn-Ag-Cu-Ti-VZr-Ni-Cr

(35-95)Sn-(0.570)Ag-(0.5-20)Cu(0.1-4)Ti, V, Zr-(05)Ni-(0-2)Cr

Sn-Ag-In

95Sn-3.5Ag-1.5In

GTE30

214/22033

YS 4616 psi, UTS 4987 psi.33

Low elongation, 26%.33

Sn-Ag-In-Cu

95.3Sn-3Ag-1In0.7Cu

UTS comparable with that of Sn63. Impact strength 2.4 times that of Sn63.49

Sn-Ag-In-Bi

93Sn-3.5Ag-3In0.5Bi

UTS 1.1 times that of Sn63.49 Impact strength 1.5 times that of Sn63.49

Sn-Ag-Sb

65Sn-25Ag-10Sb

95Sn-3Ag-2Sb

NCMS, Alpha

49

233

225/22833

Harima, Mitsui Metals

High strength.

Expensive; melting point too high. Old Motorola die attach solder. Very brittle.

Motorola

YS 5749 psi, UTS 6124 psi.33

Low elongation, 25%.33

NCMS Motorola67

12.21

(61-69)Sn-(2328)Ag-(8-11)Sb 220/22433

YS 8361 psi, UTS 9256 psi.33

Low elongation, 21%,33 complex system, although meets NCMS criteria.

Sn-Ag-Sb-Bi-Cu

93.5Sn-3Ag-1.5Sb1Bi-1Cu

NCMS

Sn-Ag-Sb-Bi-In

Balance Sn-(0.85)Ag-(0.1-10)Sb(>0.1)Bi-(>0.1)In

Kabushiki68

Sn-Ag-Sb-Cd

95Sn-3.5Ag-0.5Sb1Cd

NCMS

Sn-Ag-Zn

95.5Sn-3.5Ag-1.0Zn

217

Sn-Ag-Zn-Cu

95Sn-3.5Ag-1.0Zn0.5Cu

219/22133

Sn-Au-Bi-Ag

Sn86.85Sn-5Au-5Bi3.15Ag

Good mechanical strength.

Slightly high melting point.

AT&T

Good ductility.

Slightly high melting point.

AT&T alloy, NCMS Sandia69

(Continues)

TABLE 12.7 Pb-Free Solders Investigated (Continued)

Alloy category

Composition

Solidus/ liquidus (°C)

Sn-Bi

55Sn-45Bi

138/16433

Sn-Bi-Ag

90.5Sn-7.5Bi-2Ag

190/21633

92Sn-5Bi-3Ag 91.8Sn-4.8Bi-3.4Ag

Advantages

Disadvantages 26°C pasty range.

Manufacturer or investigator NCMS Tamura Kaken

210 200/216, 201/205, or 211/21633

Considered one of most promising by the NMCS. 0–100°C temperature cycling much better than for Sn63.11 UTS 10,349 psi.1

Small peak at 137°C from quench.33 High σ, 420 dyn/cm.35

Sandia,70 NCMS

Sandia70

12.22

(91-96)Sn-(>3)Bi(3.2-4.83)Ag 91.7Sn-4.8Bi-3.5Ag

211/215

Low cycle fatigue comparable to that of Sn63. YS 6,712 psi, UTS 10,349 psi.33

96.5Sn-3Bi-0.5Ag

223/226

Low cycle fatigue better than Sn63.

90.5Sn-6Bi-3.5Ag

220

Low cycle fatigue life 0.9 times that of Sn63.13 Low elongation, 16%.33

H-Technol13

H-Technol13 Matsushita

90.8Sn-6.1Bi-3.1Ag

137/21533

Low solidus, very wide pasty range.

NCMS

86.5Sn-10Bi-3.5Ag

137/20833

Very wide pasty range.

Matsushita, NCMS

81.7Sn-15Bi-3.3Ag

137/20033

Very wide pasty range.

Matsushita, NCMS

78Sn-19.5Bi-2.5Ag

138/19633

Elongation 17%, wide pasty range.33

NCMS, Kester

63.2Sn-30Bi-6.8Ag

137/28233

Very wide pasty range.

NCMS

56Sn-41Bi-3Ag

138/16633

Elongation 39%, wide pasty range.33

NCMS, IBM, Endicott

(40-60)Sn-(>40)Bi(0.05-1)Ag

YS 12,070 psi, UTS 13,450 psi.33

YS 9287 psi, UTS 10,130 psi.33

Lucent71

Sn-Bi-Ag-Cu

86.6Sn-10Bi-2.8Ag0.6Cu

Ono

90Sn-7.5Bi-2Ag0.5Cu

193/21333

90.8Sn-5Bi-3.5Ag0.7Cu

198/213

91.0Sn-4.5Bi-3.5Ag1.0Cu

210

93.3Sn-3.1Bi-3.1Ag0.5Cu

209/212

YS 12,370 psi, UTS 13,440 psi.33

Low elongation, 12%.33

Alloy H, Alpha Metals, developed at ITRI; NCMS33 NCMS33 Senju

Low cycle fatigue life 1.8 times that of Sn63.13

H-Technol

12.23

94.25Sn-3Bi-2Ag0.75Cu

205/21733

NCMS

Sn-Bi-Ag-Cu-Ge

93.4Sn-4Bi-2Ag0.5Cu-0.1Ge

202/217

NCMS33

Sn-Bi-Ag-In

Balance Sn-(6-14)Bi(3-4)Ag-(2-5)In

Samsung72

Sn-Bi-Ag-In-Cu

(83-92)Sn-(5-18)Bi(2.5-4)Ag-(0-1.5)In(0-0.7)Cu

Matsushita59

Sn-Bi-Au

Balance Sn-(3070)Bi-Au bump

Motorola73

Sn-Bi-Cu

50Sn-48Bi-2Cu

Sn-Bi-Cu-Ag

48Sn-46Bi-4Cu-2Ag 90Sn-7.5Bi-2Ag0.5Cu

138/15333 137/146

YS 8899 psi, UTS 9495 psi.33

Low elongation, 19%,33 wide pasty range.

NCMS

YS 9806 psi, UTS 10,070 psi.33

Low elongation, 3%.33 Poor ductility.

IBM, NCMS NCMS

(Continues)

TABLE 12.7 Pb-Free Solders Investigated (Continued)

Alloy category

Composition

Solidus/ liquidus (°C)

Advantages

Disadvantages

Manufacturer or investigator Cookson74

12.24

Sn-Bi-Cu-Ag-P

(0.08-20)Bi-(0.021.5)Cu-(0.01-1.5)Ag(0-0.10)P-(0-0.2) rare earth mixture— balance Sn

Sn-Bi-In-Ag

80Sn-11.2Bi-5.5In3.3Ag

170/22133

Wide pasty range.

NCMS

80.8Sn-11.2Bi-5.5In2.5Ag

169/20033

Wide pasty range.

NCMS

Sn-Bi-Zn

65.5Sn-31.5Bi-3Zn

133/17133

Wide pasty range.

NCMS, Alpha

Sn-Bi-Zn-Sb-MgAl-Te

Balance Sn-(5-15)Bi(0.01-3)Zn-(0.013)Sb-(0.01-3)Mg(0.01-3)Al-(0.013)Te

Sn-Cd

67.8Sn-32.2Cd

Sn-Cu

Sn-Cu-Ag

97Sn-3Cu

Korea Institute of Machinery and Metals39

177

Toxic. 42

227/335

99Sn-1Cu

227

99.3Sn-0.7Cu

227

95.5Sn-4Cu-0.5Ag

Elongation 53%, UTS 11,210 psi, YS 10,500 psi.33

218/22633

UTS 6420 psi.

SS 29.8 MPa.46 σ 461 dyn/cm.34

Indium Ford, Welco Castings42

Fatigue resistance 0.3 times that of Sn63.13 UTS 0.5 times that of Sn63.75 Melting range too wide and too high. YS 3724 psi, UTS 4312 psi. Low elongation, 27%.33

Engelhard (Silvabrite 100), NCMS

93Sn-4Cu-3Ag

221/>300

YS 6276 psi, UTS 7006 psi.33

Low elongation, 22%. 95°C pasty range, liquidus >300°C.33

NCMS

12.25

(92-99)Sn-(0.7-6)Cu(0.05-3)Ag

Engelhard76

Sn-Cu-Ag-Bi-Se

(79-97)Sn-(3015)Cu(0-4)Ag-(0-1)Bi-(01)Se

Touchstone77

Sn-Cu-Ag-Ni

(92.5-96.9)Sn-(35)Cu-(0-5)Ag-(0.12)Ni

Harris78

Sn-Cu-Bi-Ag

(88-99.35)Sn-(0.56)Cu-(0.1-3)Bi-(0.053)Ag

Oaley79

Sn-Cu-In-Ag

(80-81)Sn-(1012)Cu-(5-6)In-(24)Ag

IBM80

Sn-Cu-Se-Te

Balance Sn-(3-6)Cu(0.1-1)Se-(0.1-1)Te

Tanacorp81

Sn-Cu-Sb-Ag

95.5Sn-3Cu-1Sb0.5Ag

256

Melting point too high.

Motorola

97Sn-2Cu-0.8Sb0.2Ag

219/23033

YS 3758 psi, UTS 4323 psi. Low elongation, 27%.33

Kester SAFA-LLOY, NCMS

Sn-Cu-Zn-Ag-Ni

Kale Sadashiv S82

95.68Sn-(2.8-3.5)Cu(0.2-0.5)Zn-(0.080.16)Ag-(0.080.16)Ni

Sn-In

58Sn-42In

118/145

Wide pasty range, high In.

70Sn-30In

120/∼175

Poor creep.

Indium

(Continues)

TABLE 12.7 Pb-Free Solders Investigated (Continued)

Alloy category Sn-In-Ag

Composition 77.2Sn-20.0In-2.8Ag

Solidus/ liquidus (°C)

Creep resistant; virtually drop-in replacement.

Disadvantages

Indium, NCMS

113/24233

Low solidus, very wide pasty range.

NCMS

80Sn-14.4In-5.6Ag

189/19933

High In content.

96.9Sn-10In-3.1Ag

204/205

82Sn-15In-3Ag

NCMS No Sn-In eutectic problem, potential use for flip chip applications.83

NCMS33 Indium

12.26

86.4Sn-8.6In-5Ag

NCMS

(70-92)Sn-(4-35)In(1-6)Ag

Indium83

(71.5-91.9)Sn-(4.825.9)In-(2.6-3.3)Ag

Indium83

(70.5-73.5)Snbalance In-(6.57.5)Ag

IBM84

Sn-In-Ag-Bi

91.5Sn-4In-3.5Ag1Bi

Sn-In-Ag-Cu

85.9Sn-10In-3.1Ag1Cu 88.5Sn-8In-3Ag0.5Cu

Sn-In-Ag-Sb

Manufacturer or investigator

Slightly expensive. 114°C small peak due to eutectic Sn-In. σ 390 dyn/cm.35

73.2Sn-20In-6.8Ag

175/186

Advantages

85.7Sn-10.9In-3Ag0.4Sb 88.5Sn-10.0In1.0Ag-0.5Sb

208/213

196/202 201/ 217.6 211

Low cycle fatigue life 3.3 times that of Sn63.13

Low cycle fatigue life 5.3 times that of Sn63.13

H-Technol Joints may deform due to phase change at temperature cycling.

Delphi Delco85,86

Low yield strength.

H-Technol87 Qualitek, NCMS Qualitek

86.4Sn-8.6In-5Ag2Sb Sn-In-Bi

200/20533 UTS 6938 psi.33

70Sn-20In-10Bi

Meets NCMS acceptance criteria.

NCMS33

Low elongation, 4%. High In content.33

NCMS NIST33

82Sn-15In-3Bi

113

80Sn-10In-10Bi

153/199 or 170/20033

Wide pasty range.

NCMS33

85Sn-10In-5Bi 90Sn-8In-2Bi

33

206/215

High strength. YS 7160 psi, UTS 7970 psi.33

Melting point too high. Low elongation, 25%; high In content.33

80Sn-10In-9.5Bi0.5Ag

179/201

Creep and fatigue resistant.

Slightly expensive.

YS 14,560 psi, UTS 15,380 psi.33

Low elongation, 7%.33 32°C pasty range, high In content.

Ford NCMS33

12.27

82Sn-10In-5Bi-3Ag 78.4Sn-9.8In-9.8Bi2Ag

IBM,88 NCMS

IBM89

(70-90)Sn-(8-20)In(2-10)Bi Sn-In-Bi-Ag

IBM, NCMS

163/19533

IBM,90 NCMS

80Sn-(5-14.5)In-(4.514.5)Bi-0.5Ag

Ford91

Sn-In-Bi-Ag-Cu

(86-97)Sn-(0-9.3)In(0-4.8)Bi-(0.34.5)Ag-(0-0.5)Cuintermetallic filler

U.S. Army92

Sn-In-Cu

93.3Sn-6In-0.7Cu

213/217

Low cycle fatigue life 2.1 times that of Sn63. YM 1.5 times that of Sn63. UTS 1.2 times that of Sn63.75

H-Technol75

94.3Sn-5In-0.7Cu

213/217

Low cycle fatigue life 1.4 times that of Sn63. YM 2.1 times that of Sn63. UTS 1.1 times that of Sn63.75

H-Technol75

(Continues)

TABLE 12.7 Pb-Free Solders Investigated (Continued)

Alloy category Sn-In-Cu-Ga

12.28 Sn-In-Zn

Sn-Sb

Sn-Sb-Ag-Bi

Composition

Solidus/ liquidus (°C)

Advantages

Disadvantages Low cycle fatigue life 0.8 times that of Sn63.

Manufacturer or investigator H-Technol75

92.5Sn-6In-1Cu0.5Ga

213/217

YM 1.7 times that of Sn63. UTS 1.2 times that of Sn63.75

92.8Sn-6In-0.7Cu0.5Ga

210/215

Low cycle fatigue life 3 times that of Sn63. YM 1.7 times that of Sn63. UTS 1.2 times that of Sn63.75

H-Technol13,75

93Sn-6In-0.5Cu0.5Ga

209/214

Low cycle fatigue life 1.7 times that of Sn63. YM 1.6 times that of Sn63. UTS 1.3 times that of Sn63.75

H-Technol75

94.5Sn-4In-1Cu0.5Ga

215/218

Low cycle fatigue life 1.2 times that of Sn63. YM 1.6 times that of Sn63.

UTS 0.9 times that of Sn63.75

H-Technol75

94.8Sn-4In-0.7Cu0.5Ga

215/218

Low cycle fatigue life 1.8 times that of Sn63. YM 1.4 times that of Sn63.

UTS 0.85 times that of Sn63.75

H-Technol75

95Sn-4In-0.5Cu0.5Ga

215/219

Low cycle fatigue life comparable with that of Sn63. YM 1.4 times that of Sn63.

UTS 0.96 times that of Sn63.75

H-Technol75

77.2Sn-20In-2.8Zn

106/18033

YS 5095 psi, UTS 5381 psi.33

Low elongation, 31%.33 Wide pasty range.

NCMS

83.6Sn-8.8In-7.6Zn

178/19533

YS 6033 psi, UTS 6445 psi.33

Low elongation, 14%.33

NCMS

Creep resistant; good hightemperature shear; mechanically strong. UTS 5110 psi, YM 44.5 GPa.33 UTS 5900 psi, SS 6200 psi.42

Melting point too high, poor wetting. YS 3720 psi. Low elongation, 22%.33

Motorola

95Sn-5Sb

232/240

97Sn-3Sb

232/238

99Sn-1Sb

232/235

90Sn-7.5Sb-2Ag-

229/23833

0.5Bi

Indium Indium YS 8230 psi, UTS 8773 PSI.33

Low elongation, 19%.33

Alpha

Sn-Sb-Ag-Cu Sn-Sb-Bi-Ag

Sn-Sb-Bi-Cu

88.9Sn-5Sb-4.5Ag-

Sandia alloy,

1.6Cu

NCMS33

(90-95)Sn-(3-5)Sb(1-4.5)Bi-(0.1-0.5)Ag

Willard Industries93

95Sn-3.9Sb-1Bi0.1Ag

Plumbing solder.

NCMS33

95Sn-3Sb-1.5Bi0.5Ag

Plumbing solder.

NCMS33

Low elongation, 28%.33

NCMS

93.5Sn-3Sb-2Bi1.5Cu

225/23133

YS 7343 psi, UTS 9350 psi.33

IBM94

(93-94)Sn-(2.53.5)Sb-(1.5-2.5)Bi(1-2)Cu

12.29

Sn-Sb-Cu

95Sn-3Sb-2Cu

227/234

Low cycle fatigue life 1.9 times that of Sn63.13

H-Technol

Sn-Sb-Cu-Ag

94.5Sn-3Sb-2Cu0.5Ag

218/232

Low cycle fatigue life 2 times that of Sn63.

H-Technol13

Sn-Sb-Cu-Ag-Ni

(87-92.9)Sn-(4-6)Sb(3-5)Cu-(0-0.5)Ag(0-2)Ni

Harris78

Balance Sn-(0.752)Sb-(0.05-0.6)Ag(0.05-0.6)Cu-(0.050.6)Ni

Johnson95

Sn-Sb-Zn-Ag

(90-98.5)Sn-(0.54)Sb-(0.5-4)Zn-(0.52)Ag

Harris96

Sn-Sb-Zn-Ag-Cu

(86.8-98.8)Sn-(0.54)Sb-(0.5-4)Zn-(0.13)Ag-(0.1-2)Cu

Harris60

(Continues)

TABLE 12.7 Pb-Free Solders Investigated (Continued)

Alloy category Sn-Zn

Composition 91Sn-9Zn

Solidus/ liquidus (°C) 199

Advantages Good strength; abundant. YS 7478 psi, UTS 7708 psi.33

Disadvantages

12.30

Poor corrosion resistance and wetting; high drossing. Low elongation, 27%.33 σ 487 dyn/cm.34

Manufacturer or investigator Indium, NCMS

Balance Sn-(4-12)Zn

Motorola47,97

Sn-Zn-Ag

(59-82)Sn-(16-30)Zn(2-11)Ag

Lucent98

Sn-Zn-Bi

89Sn-8Zn-3Bi

192/19733

88Sn-7Zn-5Bi

185/194

Matsushita, Senju, Showa Denko99 Zn drossing.

NCMS, Alpha

Sn-Zn-Bi-Cu

Balance Sn-(7-9)Zn(<3)Bi-(0.1-0.5)Cu

Mitsui100

Sn-Zn-Ge

(50-70)Sn-(25-40)Zn(0.1-10)Ge

Kronberg101

Sn-Zn-In

90Sn-9Zn-1In 87Sn-8Zn-5In

(72.8-89.4)Sn-(6.719.2)Zn-(2.7-16.4)In

175/188

Poor wetting; eutectic 52In-46Sn-2Zn (106°C) a concern.

AT&T

Indium102

Sn-Zn-In-Ag

87Sn-8Zn-5In-0.1Ag

Sn-Zn-In-Bi

86.5Sn-5.5Zn-4.5In3.5Bi

AT&T 181/189

Zn causes high dross and corrosion concerns.103

Indium103

(82-90)Sn-(4.5-6)Zn(3.5-6)In-(1-5)Bi

Indium103

Sn-Zn-In-Bi-AgCu-Sb-Au

(>70)Sn-(6-10)Zn-(310)In-(<10)Bi(<5)Ag-(<5)Cu(<5)Sb-(<5)Au

AT&T104

Sn-Zn-In-Cu

87Sn-8Zn-5In-0.1Cu

AT&T

Zn-Sn-Ag-Al

(15-98)Zn-(2-85)Sn(0-5)Ag-(0.01-0.5)Al

Asahi Glass105

SS, shear strength; UTS, ultimate tensile strength; YM, Young’s modulus; YS, yield strength; σ, surface tension.

12.31

TABLE 12.8 List of Lead-Free Solder Alloy Candidates Recommended by JEIDA

Process

Alloys used for practical applications

Composition preferred from point of view of cost and performance

Notes

Sn-3.5Ag Sn-(2–4)Ag-(0.5–1)Cu Wave

Sn-3Ag-0.5Cu

Sn-0.7Cu with a very small amount of other elements (Ag, Au, Ni, Ge, In, etc.) added Sn-3.5Ag Sn-(2–4)Ag-(0.5–1)Cu

12.32

Medium and high temperatures

Sn-3Ag-0.5Cu

Sn-(2–4)Ag-(1–6)Bi, including those with 1–2% In

Needs temperature control for reflow at higher temperatures. Incompatibility with Sn-Pb– plated components when it contains some percentage of Bi.

Reflow

Low temperatures

Sn-Pb plating on components might cause fillet lifting and damage to boards.

Sn-8Zn-(0–3)Bi

Sn-8Zn-3Bi

Sn-(57–58)Bi

Sn-57Bi-1Ag

Handle Sn-Zn carefully in corrosive environment. Ni-Au finishes preferred for Cu electrode at high temperatures. Incompatibility with Sn-Pb– plated components

Sn-3.5Ag Sn-(2–4)Ag-(0.5–1)Cu Manual/robot (thread solder)

Sn-0.7Cu with a very small amount of other elements (Ag, Au, Ni, Ge, In, etc.) added

Sn-3.5Ag-0.5Cu is JEIDA’s primary recommendation.

Sn-3Ag-0.5Cu

Incompatibility with different solder alloys in reworking.

DEVELOPMENT OF LEAD-FREE SOLDER ALLOYS

12.33

FIGURE 12.9 JEIDA road map of possible midrange melting temperature lead-free alloys.

12.6.3

NORTH AMERICA

In the U.S., the National Electronics Manufacturing Initiative (NEMI) recommends 99.3Sn-0.7Cu for wave soldering and 96.5Sn-3.5Ag and 95.5Sn-3.9Ag-0.6Cu for reflow soldering. The NCMS recommends 96.5Sn-3.5Ag, 91.7Sn-3.5Ag-4.8Bi, and 58Bi-42Sn.

12.6.4

COMPARISON OF REGIONAL PREFERENCES

Eutectic or near-eutectic Sn-based alloys containing Ag and/or Cu are the most commonly selected families, regardless of region. However, beyond that, discrepancies show up, as discussed in the following text. 12.6.4.1 Bi. In general, Bi is avoided in Europe and North America, mainly due to the general perception that Bi is a by-product of Pb and not a good choice environmentally.107 Bi-containing alloys generally are more rigid, and may pose concerns about impact resistance. For example, Richard D. Parker, staff engineering supervisor, advanced substrate assembly, advanced engineering at Delphi Automotive, says “Automotive components are subjected to intense vibration. Sn-Ag-Cu system solder is superior to Sn-Ag-Cu-Bi system solder in terms of mechanical strength, and offers better reliability.”108 Fillet lifting or lift-off is another reason Bi additives are not favored. This defect is common when using Bi-containing alloys such as Sn-Ag-Cu-Bi system solders, and occurs when a through-hole component is flow-soldered and the solder separates from the printed circuit board land. When Bi levels are high, the fillet lifting occurrence rate increases. On top of that, difficulty in separating Bi from Cu by smelter also presents challenges in recycling. At present, no manufacturers plan to use SnAg-Cu-Bi system solder.

12.34

CHAPTER TWELVE

(b)

(a)

FIGURE 12.10 Senju survey results on lead-free soldering implementation status in Japan.

In Japan, the Bi-containing alloy group represents the second most popular choice, and composes 20 to 30 percent of Pb-free solders used. This is attributed to its low melting temperature and superior wetting performance.109 The former reason may not be significant, since the addition of Bi allows for only a minor reduction in melting temperature. For instance, the melting point of the Sn-2.5Ag-0.5Cu-1Bi solder used by Sony is 222°C, about the same as that of normal Sn-Ag-Cu system sol-

DEVELOPMENT OF LEAD-FREE SOLDER ALLOYS

12.35

FIGURE 12.11 Panasonic lead-free alloy development: alloy groupings.

der. If the Bi content were increased further, the melting point could be dropped further, but with the consequence that the solder would become hard and brittle. Sony, Mitsubishi, and Hitachi all use Sn-Ag-Cu-Bi system solder, and Sharp is said to be considering using the same type in the future. NEC uses an Sn-Zn-Bi solder, and Matsushita uses an Sn-Ag-Bi-In blend. The Bi additive in Sn-Zn system solder is used to improve wetability and to reduce the sensitivity of Zn toward corrosion. The melting temperature remains almost unchanged from the 199°C of Sn-Zn alloy without Bi. The sensitivity toward Pb contamination presumably is addressed by limiting the applications to consumer electronics and by suppressing the sensitivity via the introduction of other elements such as In.31 Separating Bi from Cu was also noted by Suga as an issue resolved in the Japanese smelting industry.110 12.6.4.2 Zn. Zn-containing alloys are not considered in Europe and North America due to the high reactivity of Zn. This high reactivity poses problems such as (1) excessive oxidation of Zn during soldering, (2) poor wetting of Zn alloys,109 (3) finding a flux that can be compatible with Zn alloys,109 and (4) potential vulnerability of solder joints to corrosion. In Japan, Zn-containing alloys are used by NEC for laptops, presumably due to the low melting temperature of these alloys.To cope with this need, flux technology has been developed for reflow applications that is compatible with Zn systems.99,111 12.6.4.3 Sb. Toxicity of Sb appears to be more of a concern in Japan than in Europe or North America. In the UK, the DTI considers Sb-containing alloys one of primary choices. In North America, during the straw poll survey of preferred selections conducted by NEMI on November 16, 1999, Sb-containing alloys were number three in preference as Pb-free solder alternatives for both reflow and wave-soldering

12.36

CHAPTER TWELVE

applications. However, in Japan, Sb in general is dropped from consideration due to its toxicity. 12.6.4.4 In. At low In levels, In-containing alloys have received great interest worldwide. In Japan, Sn-Ag-Bi-In has already been adopted as the third most popular solder group for reflow applications. In North America, resistance against Incontaining alloys due to cost and availability concerns is gradually giving way to interest in their reliability.13,73,87,108,112–114

12.7

PATENT ISSUES

There are three lead-free solder patents that cover the prevailing Pb-free solders favored by the industry, as shown in Table 12.9.5 Of the three patents, the Japanese patent to Senju and Matsushita and the U.S. patent to the Iowa State University Research Foundation (ISURF) covering the Sn-Ag-Cu family are the most important, due to the fact that Sn-Ag-Cu alloys are the number one choice worldwide. The coverage of both patents on Sn-Ag-Cu composition is illustrated in Fig. 12.12.Also shown in Fig. 12.12 are the three Sn-Ag-Cu compositions recommended by JEIDA, BRITEEURAM, and NEMI. The numerical ranges for these three popular Sn-Ag-Cu compositions fall right in and only in the claim range of the Senju patent, suggesting that patent is the only valid patent affecting the global Pb-free solder implementation. However, the ISURF patent covers both joints and solder material. Since most electronic soldering involves the use of copper pad or leads, dissolution of Cu into solder may bring the joint composition into the ISURF patent range. In addition, the U.S. patent law’s “doctrine of equivalents” may allow the patent’s coverage to extend beyond the literal range of its claims and outlaw the compositions that differ somewhat from those that are claimed literally in the patent.115 Since Senju and Matsushita were granted the patent in Japan, while the Ames Laboratory held patent rights in the U.S., neither side could sell in the other country. In view of these considerations, a prudent business approach for a multinational company may be acquiring licensing agreement from both patent holders. However, this implies paying double royalty fee and thus incurring a higher manufacturing cost. Fortunately, this Pb-free solder patent problem is being resolved gradually. Senju and Nihon Superior have resolved their patent dispute concerning Sn-Ag-Cu–based Pb-free solder. Rights held by Senju and Matsushita, and other rights held by Nihon Superior and the U.S. Department of Energy’s Ames Laboratory at Ohio State University, have been unified into a set for licensing to other solder manufacturers. The move makes it possible for Japanese equipment manufacturers to purchase Sn-Ag-Cu solder from Senju, Nihon Superior, or any vendors licensed by both companies, TABLE 12.9 Patents Critical for Pb-Free Solder Implementation

Patent holder

Coverage

Sn-Ag-Cu family

Ames/Iowa State University

Solder and joints

U.S.

Yes

Senju Metals

Solder

Japan

Yes

Oaley

Solder

North America

Yes

Sn-Ag-Bi-Cu

Patent territory

Royalty requirement

Alloy

DEVELOPMENT OF LEAD-FREE SOLDER ALLOYS

12.37

FIGURE 12.12 Overview of SnAgCu coverage.58,61

and to sell equipment products in both Japan and America without fear of infringement.116 With Sn-Ag-Cu solder being the most promising Pb-free solder, the decision to unify rights is expected to accelerate its adoption by manufacturers as the standard lead-free material.

12.8

CONCLUSION

Numerous Pb-free solder systems, including preexisting alloys and newly modified alloys, have been developed and studied. The modification is often accomplished by addition of a small amount of additional elements to preexisting alloys with the goals of improving wetability, bond strength, oxidation resistance, and impurity tolerance level; reducing the melting temperature; refining the grain structure; and so on.The Sn-Ag-Cu family is the favorite choice. Other popular choices include Sn-Ag, Sn-Cu, Sn-Ag-Cu-Bi, Sn-Ag-Bi-In, and Sn-Zn-Bi systems. Patent overlap issues are being resolved through unifying rights.

REFERENCES 1. National Center for Manufacturing Sciences, “Lead-Free Solder Project—Final Report,” NCMS Report 0401RE96, August 1997. 2. Allenby, B. R., I.Artaki,T.A. Carroll, D.W. Dharinger,Y. Degani, J. R. Fisher, R. S. Freund, C. Gherman, T. E. Graedel, A. M. Lyons, C. Melton, G. C. Munie, J. T. Plewes, R. Reich, C. Schoenthaler, N. Socolowski, and H. Solomon, “An Assessment of the Use of Lead in Electronic Assembly,” Proceedings of the Technical Program. Surface Mount International, San Jose, CA, August 30–September 3, 1992. 3. Shina, S., H. Belbase, K. Walters, T. Bresnan, P. Biocca, T. Skidmore, D. Pinsky, P. Provencal, and D. Abbott, “Design of Experiments for Lead Free Materials, Surface Finishes and Manufacturing Processes of Printed Wiring Boards,” SMTA International, Chicago, IL, September 20–24, 2000.

12.38

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4. Griese, H., J. Muller, K.-H. Zuber, and H. Reichl, “Towards Green Electronics Packaging Technologies,” Proceedings of International Symposium on Electronic Packaging Technology, pp. 59–66, Beijing, China, August 8–11, 2001. 5. Lotosky, P., “Lead-Free Update,” IMAPS, São Paulo, Brazil, August 1–3, 2001. 6. Data sheet of Indium Corporation of America. 7. Steen, H.A.H., and G. Becker, “The Effect of Impurity Elements on the Soldering Properties of Eutectic and Near-Eutectic Tin-Lead Solder,” Brazing and Soldering, 11:4–11, Autumn 1986. 8. Carroll, M. A., and M. E. Warwick, “Surface Tension of Some Sn-Pb Alloys: Part 1—Effect of Bi, Sb, P, Ag, and Cu on 60Sn-40Pb Solder,” Materials Science and Technology, 3:1040–1045, December 1987. 9. Furusawa, A., K. Suetsugu, A. Yamaguchi, and H. Taketomo, “Thermoset Pb-Free Solder Using Heat-Resistant Sn-Ag Paste,” National Technical Report, 43(1), February 1997. 10. Toyoda, Y., “The Latest Trends in Lead-Free Soldering,” Proceedings of International Symposium on Electronic Packaging Technology, pp. 434–438, Beijing, China, August 8–11, 2001. 11. Baggio, T., “The Panasonic Mini Disk Player—Turning a New Leaf in a Lead-Free Market,” IPCWorks ’99, Minneapolis, MN, October 27, 1999. 12. Zhao, J., L. Huang, and J. Ma, “Effects of the Addition of In, Bi to Sn-Ag-Cu Lead-Free Solders,” Proceedings of International Symposium on Electronic Packaging Technology, pp. 471–474, Beijing, China, August 8–11, 2001. 13. Hwang, J. S., “Solder Materials,” SMT’s The Building Blocks, 11–17, July 2001. 14. Stoneman, A. M., C. A. MacKay, and C. J. Thwaites, “Oxidation and Drossing of Molten Solders: Effects of Impurities,” Metals Technology, 226–231, June 1980. 15. Ackroyd, M. L., C. A. MacKay, and C. J. Thwaites, “Effect of Certain Impurity Elements on the Wetting Properties of 60% Tin, 40% Lead Solders,” Metals Technology, 73–85, February 1975. 16. Glazer, J., “Metallurgy of Low Temperature Pb-Free Solders for Electronic Assembly,” International Materials Reviews, 40(2):65–93, 1995. 17. Grivas, D., M.S. thesis, University of California at Berkeley, January, 1974. 18. Morris, J. W. Jr., J. L. Freer Goldstein, and Z. Mei, “Microstructural Influences on the Mechanical Properties of Solder,” in The Mechanics of Solder Alloy Interconnects, Frear, D., H. Morgan, S. Burchett, and J. Lau, eds., Van Nostrand Reinhold, New York, p. 428, 1994. 19. Tribula, D., Ph.D. thesis, University of California at Berkeley, June 1990. 20. Tribula, D., and J. W. Morris Jr., ASME Journal of Electronic Packaging, 112:87, 1990. 21. Gonya, S. G., J. K. Lake, R. C. Long, and R. N. Wild, “Lead-Free Tin-Bismuth Solder Alloys,” IBM, Armonk, NY, U.S. Patent 5,368,814, 29 November, 1994. 22. Pao, Y.-H., S. Badgley, R. K. Govila, and E. Jih, “Thermomechanical and Fatigue Behavior of Four Lead and Lead-Free Solder Joints,” in Advances in Electronic Packaging, American Society of Mechanical Engineers, EEP, ASME, vol. 4-2, pp. 937–941, 1993. 23. Raeder, C. H., L. E. Felton, V. A. Tanzi, and D. B. Knorr, “The Effect of Aging on Microstructure, Room-Temperature Deformation, and Fracture of Sn-Bi/Cu Solder Joints,” Journal of Electronic Materials, 23(7):611–617, July 1994. 24. Jin, S., and M. McCormack, “Dispersoid Addition to a Pb-Free Solder for Suppression of Microstructural Coarsening,” J. Electronic Materials, 23(8):735–739, August 1994. 25. McCormack, M., and S. Jin, “Improved Mechanical Properties in New Pb-Free Solder Alloys,” J. Electronic Materials, 23(8):715–720, August 1994. 26. McCormack, M., S. Jin, and G. W. Kammlott, “Enhanced Solder Alloy Performance by Magnetic Dispersions,” IEEE Trans. on Components, Packaging, and Manufacturing Technology, Part A, 17(3):452–457, September 1994.

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12.39

27. McCormack, M., and S. Jin, “Progress in the Design of New Lead-Free Solder Alloys,” JOM, 45(7):36–40, July 1993. 28. McCormack, M., and S. Jin, “New, Lead-Free Solders,” J. Electronic Materials, 23(7):635–640, July 1994. 29. McCormack, M., S. Jin, G. W. Kammlott, and H. S. Chen, “New Pb-Free Solder Alloy with Superior Mechanical Properties,” Applied Physics Letters, 63(1):15–17, July 5, 1993. 30. McCormack, M., G. W. Kammlott, H. S. Chen, and S. Jin, “New Lead-Free, Sn-Ag-Zn-Cu Solder Alloy with Improved Mechanical Properties,” Applied Physics Letters, 65(10):1233–1235, September 5, 1994. 31. Mei, Z., F. Hua, and J. Glazer, “Sn-Bi-X Solders,” SMTA International, San Jose, CA, September 13–17, 1999. 32. Lee, N.-C., “Getting Ready for Lead-Free Solders,” European Surface Mount Conference, Brighton, UK, 1996. 33. National Center for Manufacturing Sciences, Technical Reports for the Lead Free Solder Project: Properties Reports: “Room Temperature Tensile Properties of Lead-Free Solder Alloys,” Lead Free Solder Project CD-ROM, NCMS, 1998. 34. Glazer, J., “Microstructure and Mechanical Properties of Pb-Free Solder Alloys for LowCost Electronic Assembly: A Review,” J. Electronic Materials, 23(8):693, 1994. 35. Artaki, I., D. W. Finley, A. M. Jackson, U. Ray, and P. T. Vianco, “Wave Soldering with PbFree Solders,” Proceedings of Surface Mount International, p. 495, San Jose, CA, August 27–31, 1995. 36. Inoue, H., Y. Kurihara, and H. Hachino, “Pb-Sn Solder for Die Bonding of Silicon Chips,” IEEE Trans. Components, Hybrids Manuf. Technol., 9:190–194, 1986. 37. Soldering Manual, 2d ed., American Welding Society, Inc., Miami, FL, 1977. 38. Schroeder,V., and F. Hua,“Feasibility Study of 57Bi-42Sn-1Ag Solder,” TMS Proceedings, New Orleans, LA, February 2001. 39. Korea Institute of Machinery and Metals, U.S. Patent 5,851,482. 40. Hua, F., Z. Mei, J. Glazer, and A. Lavagnino, “Eutectic Sn-Bi as an Alternative to Pb-Free Solder,” Proceedings of IPC, 1999. 41. Ford Motor Company, U.S. Patent 5,755,896. 42. Solder data sheet, Welco Castings, 2 Hillyard Street, Hamilton, Ontario, Canada. 43. Lauer, T., and S. Wege, “Behaviour of Lead-Free Solder Joints Under Thermal and Mechanical Stress,” Proceedings of SMT/ES&S/Hybrid 2000, Nuremberg, Germany, June 27–29, 2000. 44. Mawer, A., and K. Levis, “Automotive PBGA Assembly and Board-Level Reliability with Lead-Free Versus Lead-Tin Interconnect,” SMTA International, Chicago, IL, September 24–28, 2000. 45. Sigelko, J. D., and K. N. Subramanian, “Overview of Lead-Free Solders,” Adv. Mat. and Proc., 47–48, March 2000. 46. Anderson, I. E., T. E. Bloomer, R. L. Terpstra, J. C. Foley, B. A. Cook, and J. Harringa, “Development of Eutectic and Near-Eutectic Sn-Ag-Cu Solder Alloys for Lead-Free Electronic Assemblies,” IPCWorks ’99: An International Summit on Lead-Free Electronics Assemblies, Minneapolis, MN, October 25–28, 1999. 47. Motorola, U.S. Patent 5,390,080. 48. Feldmann, K., and M. Reichenberger, “Assessment of Lead-free Solders for SMT,” Apex 2000, Long Beach, CA, March 2000. 49. Tanaka, Y., J. Takahashi, and K. Kawashima, “Lead Free Soldering Technology for Mobile Equipment,” IMAPS, pp. 336–341, Boston, MA, September 20–22, 2000. 50. Mitsui Mining & Smelting Co. Ltd., U.S. Patent 5,658,528. 51. Lucent Technologies Inc., U.S. Patent 5,762,866.

12.40 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64.

65. 66. 67. 68. 69.

70. 71. 72. 73. 74. 75.

76. 77. 78. 79. 80. 81. 82. 83. 84. 85.

86.

CHAPTER TWELVE

AIM, U.S. Patent 5,405,577. IBM, U.S. Patent 5,393,489. IBM, U.S. Patent 3,607,253. Herzog, T., K.-J. Wolter, and T. Zerna, “Reliability of Lead Free Solder Joints on Manufacturing Conditions,” SMTA International, Chicago, IL, September 20–24, 2000. Grusd, A., “Connecting to Lead-Free Solders,” Circuit Assembly, 32–38, August, 1999. Amagai, M., “Chip Scale Package Solder Joint Reliability Modeling and Material Characterization,” Japanese Packaging Society Magazine, 3(1):45–56, 2000. Senju, patent JP5050286, covers 3–5% Ag, 0.5–3% Cu, 0–5% Sb, balance Sn. Matsushita Electric Industrial Co. Ltd., U.S. Patent 5,918,795. JW Harris Company, U.S. Patent 4,695,428. Iowa State University, Sandia, U.S. Patent 5,527,628. Ford Motor Company, U.S. Patent 5,863,493. Fukuda Metal Foil & Powder Co. Ltd., U.S. Patent 5,817,194. Seelig, K., and D. Suraski, “The Status of Lead-Free Solder Alloys,” Proceedings of 50th IEEE 2000 Electronic Components and Technology Conference, Las Vegas, NV, May 21–24, 2000. Hwang, J. S., and Z. Guo, “Effects of Pb Contamination on the Material Properties of Lead-Free Sn/Ag/Cu/Sb Solder,” Chip Scale Review, 73–74, April 2001. AIM, U.S. Patent 5,352,407. Motorola, U.S. Patent 4,170,472. Kabushiki Kaisha Toyota Chuo Kendyusho, U.S. Patent 5,733,501. Hernandez, C. L., P. T. Vianco, and J. A. Rejent, “Effect of Interface Microstructure on the Mechanical Properties of Pb-Free Hybrid Microcircuit Solder Joints,” Proceedings of SMTA/IPC Electronics Assembly Expo, p. S19-2, Providence, RI, October 24–29, 1998. Sandia National Laboratory, U.S. Patent 5,439,639. Lucent Technologies Inc., U.S. Patent 5,569,433. Samsung Electro-Mechanics Co. Ltd., U.S. Patent 5,843,371. Motorola, U.S. Patent 5,316,205. Cookson Group, U.S. Patent 4,929,423. Hwang, J. S., Z. Guo, and H. Koenigsmann, “A High Performance Lead-Free Solder—The Effects of In on 99.3Sn/0.7Cu,” Soldering and Surface Mount Technology, 13(2):7–13, 2001. Engelhard Corporation, U.S. Patent 4,778,733. Touchstone Inc., U.S. Patent 5,435,968. JW Harris Company, U.S. Patent 4,758,407. Oaley Company, U.S. Patent 4,879,096. IBM, U.S. Patent 5,730,932. Tanacorp. Inc., U.S. Patent 5,102,748. Kale Sadashiv S, U.S. Patent 5,094,813. Indium Corporation of America, U.S. Patent 5,256,370 and 5,580,520, Indalloy 254. IBM, U.S. Patent 5,874,043. Elenius, P., and S. Yeh, “Lead Free Solder for Flip Chip and Chip Scale Packaging (CSP) Applications,” Proceedings of IPCWorks ’99, pp. S-03-2-1–S-03-2-6, Minneapolis, MN, October 23–28, 1999. Yeh, S., “Fatigue Resistant Lead Free Solder,” Delphi Delco Electronic Systems, U.S. Patent 5,938,862.

DEVELOPMENT OF LEAD-FREE SOLDER ALLOYS

12.41

87. Hwang, J. S., and Z. Guo, “The Effects of Pb Contamination on Lead-Free Sn/Ag/Cu/In Solder,” Chip Scale Review, 99–100, July 2001. 88. IBM, U.S. Patent 5,344,607. 89. IBM, U.S. Patent 5,414,303. 90. IBM, U.S. Patent 5,328,660. 91. Ford Motor Company, U.S. Patent 5,429,689. 92. U.S. Army, U.S. Patent 5,527,628. 93. Willard Industries, U.S. Patent 4,808,309. 94. IBM, U.S. Patent 5,411,703. 95. Johnson Manufacturing Company, U.S. Patent 5,837,191. 96. JW Harris Company, U.S. Patent 4,670,271. 97. Motorola, U.S. Patent 5,452,842. 98. Lucent Technologies Inc., U.S. Patent 5,698,160. 99. Showa Denko, “Development of Sn-Zn Solder Paste of High Reliability,” IPCWorks ’99, Minneapolis, MN, October 27, 1999. 100. Mitsui Mining & Smelting Co. Ltd., U.S. Patent 5,728,868. 101. Kronberg, J. W., U.S. Patent 5,147,471. 102. Indium Corporation of America, U.S. Patent 5,242,658. 103. Indium Corporation of America, U.S. Patent 5,455,004, Indalloy 231. 104. AT&T Corporation, U.S. Patent 5,538,686. 105. Asahi Glass Company, U.S. Patent 4,042,725. 106. Japan Electronic Industry Development Association, “Challenges and Efforts Toward Commercialization of Lead-Free Solder—Road Map 2000 for Commercialization of Lead-Free Solder,” version 1.3. 107. Tanokura, Y., “Race for Lead-Free Solder Splits over Bi Contents,” Nikkei Electronics Asia, February 2001. 108. Lee, N.-C., “Lead-Free Soldering and Low Alpha Solders for Wafer Level Interconnects,” SMTA International, Chicago, IL, September 2000. 109. Huang, B. L., and N. C. Lee, “Prospects of Lead Free Alternatives For Reflow Soldering,” Proceedings of IMAPS ’99, Chicago, IL, October 28, 1999. 110. Private communication with Professor Tadatomo Suga of University of Tokyo, April 17, 2000. 111. Matsushita Electric Industrial Co., Ltd., and Senju Metal Industry Co., Ltd., U.S. Patent 6,159,304. 112. Lee, N.-C., and J. Slattery, “A Drop-In Lead-Free Solder Replacement,” Proceedings of Surface Mount International, San Jose, CA, September 1994. 113. Lee, N.-C., “Soldering Technology for Area Array Packages,” SMTA International, San Jose, CA, 1999. 114. Lee, N.-C., “Lead-Free Soldering—Where the World Is Going,” Advancing Microelectronics Magazine, September/October 1999. 115. Anderson, I. E., K. Kirkland, and W. Willenburg, “Implementing Pb-Free Soldering,” SMT’s Guide to Lead-Free Soldering, 6–9, June 2001. 116. Nikkei Electronics Asia, April 2001.

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CHAPTER 13

PREVAILING LEAD-FREE ALLOYS

Among the numerous lead-free solder options available, the following families are of particular interest and are the prevailing choices of industry: eutectic Sn-Ag, eutectic Sn-Cu, Sn-Ag-Bi, Sn-Ag-Bi-In, Sn-Ag-Cu, Sn-Ag-Cu-Bi, Sn-Ag-Cu-In, SnAg-Cu-Sb, Sn-Zn, and Sn-Zn-Bi. Their characteristics and potential performance in electronic applications follow.

13.1 13.1.1

EUTECTIC Sn-Ag PHYSICAL PROPERTIES

Eutectic Sn-Ag, 96.5Sn-3.5Ag, has been used in hybrid applications for many years. Some physical properties of this alloy, as well as 99.3Sn-0.7Cu and 63Sn-37Pb, are shown in Table 13.1.1–3 The melting temperature of 96.5Sn-3.5Ag is 38°C higher than eutectic Sn-Pb, suggesting that a considerable thermal stress can be introduced into the devices being assembled during soldering. The high surface tension of the eutectic Sn-Ag system predicts a higher contact angle during soldering, hence a greater difficulty in solder spreading. The lower density and lower electrical resistivity of eutectic Sn-Ag versus eutectic Sn-Pb promises a 12 percent reduction in the weight of solder materials to be used and about 30 percent improvement in signal quality dictated by the solder joint electrical conductivity. However, the lower thermal conductivity of eutectic Sn-Ag may hamper the heat dissipation of devices. The difference in the coefficient of thermal expansion (CTE) between eutectic Sn-Ag (30) and copper (16.6) is greater than the difference between eutectic Sn-Pb (25) and copper, suggesting a possibly greater local stress for Sn-Ag at the solder-copper interface. The higher hardness of eutectic Sn-Ag may have multiple implications, as will be discussed later.

13.1.2

MECHANICAL PROPERTIES

Some tensile and shear properties of 96.5Sn-3.5Ag, as well as of 99.3Sn-0.7Cu and 63Sn-37Pb, are shown in Table 13.2. Some data on alloy compositions close to the eutectic binary systems are also listed. Wide data scattering is observed from source to source and may be attributed to the variation in test conditions and sample preparation. To allow a better comparison of alloy systems, data from the same source are listed side by side. In general, the ultimate tensile strength and yield strength of eutectic Sn-Ag are about the same as eutectic Sn-Pb. Eutectic Sn-Ag also exhibits a higher Young’s modulus but a lower elongation than eutectic Sn-Pb, presumably due to the stiff nature of eutectic Sn-Ag, as indicated by its higher hardness shown in Table 13.1. The shear strength of eutectic Sn-Ag is comparable with or higher than eutectic Sn-Pb. 13.1 Copyright © 2003 by The McGraw-Hill Companies, Inc. Click here for terms of use.

13.2

CHAPTER THIRTEEN

TABLE 13.1 Some Physical Properties of 96.5Sn-3.5Ag, 99.3Sn-0.7Cu, and 63Sn-37Pb Property

96.5Sn-3.5Ag

99.3Sn-0.7Cu

Melting temperature (°C)

221

227

Surface tension (dyne/cm) at 260°C

460 at 260°C; 431 at 271°C (air); 493 at 271°C (nitrogen)

491 at 277°C (air); 461 at 277°C (nitrogen)

Density (gm/cm3) Electrical resistivity (µΩ-cm) Thermal conductivity (W/cm·°C) Coefficient of thermal expansion (CTE) at 20°C (ppm/K) Hardness

7.36

7.31

10.8

10–15

0.33 at 85°C

—

30

—

16.5 [Vickers hardness (VH)]; 40 (Brinell)

—

63Sn-37Pb 183 380 at 260°C; 417 at 233°C (air); 464 at 233°C (nitrogen) 8.36 15.0 0.509 at 30°C; 0.50 at 85°C 25 12.8 (HV); 17 (Brinell)

Compilation and comparison of room-temperature elongation of 96.5Sn-3.5Ag and eutectic Sn-Pb as a function of strain rate and loading geometry have also been done by Glazer,3 as shown in Fig. 13.1. Data measured in shear were compared by Glazer with data measured in tension by using equivalent strain, e = r/(3)1/2 if true strains in tension and shear are known. Again, a wide data scattering is observed, although in most cases the elongation of eutectic Sn-Ag for both tension and shear tests appears to be lower than that of eutectic Sn-Pb. Glazer reported that eutectic Sn-Ag has comparable elongation to eutectic Sn-Pb at moderate strain rates at room temperature, but is probably less strain rate sensitive (i.e., its elongation does not rise as rapidly at slow strain rates).22 At a strain rate of 6.2 × 10−4 s−1, strain hardening and softening rates were by far the slowest for 96.5Sn-3.5Ag and the fastest for 63Sn-37Pb, with eutectic Sn-Bi in between.22 Figure 13.2 shows the tensile stress-strain behavior of several alloys measured at 6.56 × 10−4/s and 300 K, as reported by Hwang.4 In this case, the eutectic Sn-Ag displays a lower tensile strength but a higher elongation than eutectic Sn-Pb. The creep rate of eutectic Sn-Ag is comparable with Sn-Ag-Cu and Sn-Ag-Bi, but is much lower than that of 60Sn-40Pb at low stress, suggesting a higher creep strength associated with those Pb-free solders. However, the difference rapidly diminishes with increasing stress, as indicated by Fig. 13.3.23 The National Institute of Standards and Technology (NIST) also reported that the creep strength of 96.5Sn3.5Ag is comparable with Sn-Ag-Cu and is higher than eutectic Sn-Cu or Sn, as shown in Table 13.3.8 The high creep strength of 96.5Sn-3.5Ag is also reflected in Grusd’s creeprupture study.24 At a given applied stress, time to failure increases in the following order: 60Sn-40Pb < 99.3Sn-0.7Cu < 96.5Sn-3.5Ag < Sn-Ag-Cu at 25°C, as shown in Fig. 13.4.24 At 100°C, 96.5Sn-3.5Ag exhibits the highest creep resistance, followed in decreasing order by Sn-Ag-Cu, 99.3Sn-0.7Cu, and 60Sn-40Pb, as shown in Fig. 13.5.24 This is consistent with the data reported earlier, where stress rupture life at room temperature of eutectic Sn-Ag, Sn-Bi, Sn-In, and Sn-Pb solders as a function of applied stress decreases in the following order: Sn-Ag > Sn-Bi > Sn-Pb > Sn-In.22

13.3

PREVAILING LEAD-FREE ALLOYS

TABLE 13.2 Tensile and Shear Properties of 96.5Sn-3.5Ag, 99.3Sn-0.7Cu, and 63Sn-37Pb

Property

96.5Sn-3.5Ag

99.3Sn0.7Cu

63Sn-37Pb

Notes/References

Ultimate tensile strength, in MPa

35 — 61.4 52 (as drawn) 54.6 (annealed) 58 61.4 69.6 (Sn-5Ag) 31.7 (Sn-5Ag) — — 55 26.7 — 20–56

23 — — — — — — — — — — — — — —

46 46 45.1 — — — 49.2 — — 40.7 33.92 31–46 30.6 26.7 19–56

Ref. 4 Ref. 5 Ref. 6 Ref. 7 Ref. 7 Ref. 8 Ref. 9 Ref. 9 Ref. 10 Ref. 11 Ref. 11 Ref. 12 Ref. 13 Ref. 2 Ref. 3

Yield strength, in MPa

49 24.8 (Sn-5Ag) — — 22.5

37 — — — —

37 — 28.1 30.2 27.2

Ref. 14 Ref. 10 Ref. 11 Ref. 11 Ref. 13

Young’s modulus, in GPa

— — — — — 56 26.2 —

— — — — — — — —

38.1 (−70°C) 30.2 (20°C) 19.7 (140°C) 32 33.58 35 15.7 31.03

Ref. 15 Ref. 15 Ref. 15 Ref. 16 Ref. 11 Ref. 17 Ref. 13 Ref. 2

Elongation, in %

39 38.9 — — 35 24 —

45 — — — — — —

31 35.5 43.66 52.87 35–176 48 35

Ref. 4 Ref. 6 Ref. 11 Ref. 11 Ref. 12 Ref. 13 Ref. 2

Shear strength, in MPa

27 17

20–23 16–21

23 14

61.2

29.8

36.5 (Sn-40Pb)

20.5

10.1

4.5 (Sn-40Pb)

39

28.5 (Sn-1Cu)

34.5 (Sn-40Pb)

At 0.1 mm/min, 20°C; Ref. 8 At 0.1 mm/min, 100°C; Ref. 8 At 0.1 mm/min; gap thickness: 76.2 µm; cooling rate = 10°/s, tested at 22°C; Ref. 18 At 0.1 mm/min; gap thickness: 76.2 µm; cooling rate = 10°/s; tested at 170°C; Ref. 18 At 1 mm/min at reflow temperature (RT); Ref. 19

13.4

CHAPTER THIRTEEN

TABLE 13.2 Tensile and Shear Properties of 96.5Sn-3.5Ag, 99.3Sn-0.7Cu, and 63Sn-37Pb (Continued)

Property Shear strength, in MPa

96.5Sn-3.5Ag 23.5 54.95 31.7; 57.9 (Sn-5Ag) 32.1 — 37.8

99.3Sn0.7Cu

63Sn-37Pb

Notes/References

21.2 21.6 At 1 mm/min at 100°C; Ref. 19 (Sn-1Cu) (Sn-40Pb) — 40.27 By ring-and-plug test; Refs. 2, 6, 12, 20, 21 — 41.8 — 28.4 — 23.8 — 48.4

Stress (MN m−2) to rupture in 1000 h as a function of temperature for eutectic Sn-Ag and Sn-Pb, Sn-Pb-Ag is as follows:22 96.5Sn-3.5Ag. 14 (at 20°C), 4 to 5.5 (at 100°C), 3.9 (at 125°C), and 2.3 (at 150°C) 60Sn-40Pb. 3.5 to 4 (at 20°C) and 1 to 1.1 (at 100°C) 62Sn-36Pb-2Ag. 5 (at 20°C) and 1 (at 100°C) Hwang et al.25 reported that the creep resistance, in descending order, was 62Sn36Pb-2Ag > 96.5Sn-3.5Ag > 63Sn-37Pb > 58Bi-42Sn > 60Sn-40Pb > 70Sn-30In > 60In-40Sn at room temperature. 96.5Sn-3.5Ag absorbed considerably more strain before failure than 63Sn-37Pb. The acceleration factor in a thermal cycling test versus field service will be greater for 96.5Sn-3.5Ag than for 63Sn-37Pb.22 96.5Sn-3.5Ag has far superior roomtemperature isothermal fatigue behavior to 63Sn-37Pb at high shear strain amplitudes, due to the resistance of 96.5Sn-3.5Ag to fatigue crack initiation, but is far inferior to 63Sn-37Pb at low strain amplitudes.22,26 The creep activation energy of the 96.5Sn-3.5Ag is higher for equivalent stresses and temperatures than the value of the eutectic tin-lead alloy, as reported by Villain.27

FIGURE 13.1 Comparison of elongation of 96.5Sn-3.5Ag and 63Sn37Pb as functions of strain rate at room temperature.

PREVAILING LEAD-FREE ALLOYS

FIGURE 13.2 Tensile test results of several solder alloys (96.5Sn-3.5Ag, 99.3Sn-0.7Cu, 93.3Sn-3.1Ag-3.1Bi-0.5Cu, and 63Sn-37Cu). The test condition is 6.56 × 10−4/s and 300 K.

FIGURE 13.3 Creep behavior of several eutectic or near-eutectic solder alloys.

13.5

13.6

CHAPTER THIRTEEN

TABLE 13.3 Creep Strength* of Several Lead-Free Solders

Temperature 20°C 100°C

Sn

96.5Sn-3.5Ag

99.3Sn-0.7Cu

95.8Sn-3.5Ag0.7Cu

95.5Sn-3.8Ag0.7Cu

3.3

13.7

8.6

13

13

5

2.1

5

5

1 2

* Creep strength (N/mm ) determined at 0.1 mm/min.

13.1.3

Wetting Properties

The wetting times determined with the use of wetting balance for several solder alloys are shown in Fig. 13.6, using an unactivated flux and copper coupons.28 The wetting ability descends in the following order: eutectic SnPb > SnAgCu > SnAg > SnCu under both air and nitrogen when tested at the same temperature, with nitrogen atmosphere always yielding a shorter wetting time than air atmosphere.28 On the other hand, Glazer reported that the wetting ability in three out of four cases decreases in the following order: 60Sn-40Pb > 100Sn > 95.5Sn-4Ag-0.5Cu > 95Sn5Sb > 96.5Sn-3.5Ag when tested at 260 to 280°C, as shown in Fig. 13.7 in a contact angle study and in Fig. 13.8 in a wetting time study.22,28 The difference in wetting time as a function of superheat temperature due to a variation in alloys or atmosphere diminishes if an activated flux is used on copper sheet, as shown in Fig. 13.9.28 However, it should be noted that while this may be true under certain conditions for wetting balance test results, considerable difference among those alloys is reported for solder paste reflow performance by Huang and Lee.29 On a scale of 0.0 to 10 for full spreading, the wettability of alloys at reflow increases in the following order: 89Sn-8Zn-3Bi (0.5) < 96.5Sn-3.5Ag (4.6) < 95Sn5Sb (4.7) < 99.3Sn-0.7Cu (5.2), 96.2Sn-2.5Ag-0.8Cu-0.5Sb (5.2) < 93.6Sn-4.7Ag1.7Cu (5.3) < 95.5Sn-3.8Ag-0.7Cu (5.4) < 58Bi-42Sn (6.0) < 91.7Sn-3.5Ag-4.8Bi (6.8) < 90.5Sn-7.5Bi-2Ag (7.0) < 63Sn-37Pb (9.8). The wetting behavior of alloys is affected by surface finishes as well.Therefore, for easily wettable surfaces, such as Sn-Pb surface finish on a small-outline integrated circuit (SOIC), both eutectic Sn-Ag and eutectic Sn-Pb exhibit virtually identical wet-

FIGURE 13.4 Creep-rupture data for several candidate lead-free alloys compared to 60Sn-40Pb at 25°C.

PREVAILING LEAD-FREE ALLOYS

13.7

FIGURE 13.5 Creep-rupture data for several candidate lead-free alloys compared to 60Sn-40Pb at 100°C.

ting time under air at the same superheat using an activated flux. However, if the surface is less wettable, such as a Pd-Ni surface finish, the wetting time for eutectic SnAg solder becomes considerably longer even if an activated flux is used, while that of Sn-Pb solder still remains about the same as that of the Sn-Pb surface finish.28 The wetting time of eutectic Sn-Ag may also be shorter than eutectic Sn-Pb, depending on the test condition, as shown in Fig. 13.10.30 At 260°C, the wetting time descends in the following order: 96Sn-2.5Ag-1Bi-0.5Cu > 96.2Sn-2.5Ag-0.5Sb0.8Cu > 63Sn-37Pb > 99.3Sn-0.7Cu > 96.5Sn-3.5Ag > 95.5Sn-4Ag-0.5Cu. Melton also reported that 96.5Sn-3.5Ag wets better than 63Sn-37Pb and is less sensitive to reflow atmosphere than 63Sn-37Pb.31

FIGURE 13.6 Wetting times as a function of temperature using copper coupons with a range of solder alloys and unactivated flux. (a) Air and (b) nitrogen.28

13.8

CHAPTER THIRTEEN

FIGURE 13.7 Contact angle of 60Sn-40Pb, 100Sn, 95Sn-5Sb, 96.5Sn-3.5Ag, and 95.5Sn-4Ag-0.5Cu at 260 to 280°C using four different fluxes.

Loomans et al. studied the contact angle of multicomponent lead-free solders and reported that for binary eutectic solders, the contact angles using rosin-IPA flux are: Sn-Bi, 40° (166°C); Sn-Zn, 60° (225°C); Sn-Ag, 45° (250°C).32 Vianco et al. reported the following contact angle values: 96.5Sn-3.5Ag, 60 to 75°; 95Sn-5Sb and 95.5Sn-4Cu-0.5Ag, 35 to 55°; 60Sn-40Pb, 20 to 35°. The high contact angle of 96.5Sn3.5Ag is probably related to the high surface tension of Ag,33 as well as the inability of flux to significantly lower the solder-flux interfacial tension.34 Here, 96.5Sn-3.5Ag was also noted to have a slower wetting than the rest of the alloys. The poor wetting of 96.5Sn-3.5Ag is consistent with the observation of Melton et al.35 In that study, compared with 63Sn-37Pb, the wetting of Sn on Cu is superior, 95.5Sn-4Cu-0.5Ag and eutectic Sn-Bi is acceptable, while 96.5Sn-3.5Ag is quite poor. Wetting of 96.5Sn-3.5Ag did not improve significantly in inert atmosphere, perhaps because Ag is not readily oxidized. On a Ni-Au-plated substrate, 96.5Sn3.5Ag and 58Bi-42Sn are acceptable on wetting, but poorer than 63Sn-37Pb.22 On thick film Au76-Pt21-Pd3 over Al2O3, eutectic Sn-Ag also wets more poorly than eutectic Sn-Pb.36

FIGURE 13.8 Wetting time of 60Sn-40Pb, 100Sn, 95Sn-5Sb, 96.5Sn-3.5Ag, and 95.5Sn-4Ag-0.5Cu at 260 to 280°C using four different fluxes.

13.9

PREVAILING LEAD-FREE ALLOYS

(a)

(b)

FIGURE 13.9 Wetting times as a function of superheat using copper coupons with a range of solder alloys and 0.5 percent activated flux. (a) Air and (b) nitrogen.

FIGURE 13.10 Effect of solder alloy and solder temperature on wetting time on oxidized copper.

13.10

CHAPTER THIRTEEN

Suganuma reported the wetting area decreases in the following order: 63Sn37Pb > 96.5Sn-3.5Ag > 75Sn-25Bi > 100Sn > 91Sn-9Zn. Wetting area of Sn increases with increasing doping level (up to 4 percent) of Ag, but decreases with increasing doping level (up to 9 percent) of Zn.37 The relative wetting performance of 96.5Sn3.5Ag and 100Sn contradicts the observation of Melton,35 as described earlier. The relative poorer wetting performance of eutectic Sn-Ag versus Sn-Pb is also reflected in the capillary flow test, as reported by Vianco et al.38 Here the capillary rise of 96.5Sn-3.5Ag (2.0 cm) is lower than that of 60Sn-40Pb (2.8 cm) at the 0.025cm gap, and is 1.8 cm versus infinity at the 0.008-cm gap. The rise rate (dyne/s) is 29 versus 32 and is consistent with the rise data. However, the void area (percent) of 96.5Sn-3.5Ag appears to be equal or smaller than 60Sn-40Pb, as indicated by 3.7 versus 3.8 at the 0.025-cm gap, and 11.9 versus 14.9 at the 0.008-cm gap. For 96.5Sn-3.5Ag and 63Sn-37Pb, at a lower soldering temperature Cu6Sn5 formation dominates, while at a higher temperature the Cu3Sn layer is much thicker. Activation energy for Cu3Sn growth is 58 kJ mol−1, and for the total compound layer it is 21 kJ mol−1.22 Au dissolves more rapidly into eutectic Sn-Ag and Sn than into eutectic Sn-Pb solder for the same amount of superheating.22,39–42

13.1.4

RELIABILITY

Eutectic Sn-Ag is more tolerant of Au than eutectic Sn-Pb. 96.5Sn-3.5Ag containing 5 percent Au is ductile and elongation deteriorated only very little due to much smaller AuSn4 intermetallic compound (IMC) grain size. 63Sn-37Pb containing 5% Au is brittle and the elongation decreased dramatically.22,39,40 96.5Sn-3.5Ag on Cu with thin IMC layers fractured at or near the solder-Cu6Sn5 layer. For joints with thicker IMC layers, fracture occurred at the Cu6Sn5-Cu3Sn interface.43 Glazer reported that for 95Sn-5Ag, no microstructural coarsening occurred and only the IMC layer thickness increased. Cracks propagated at the solder-intermetallic interface and through the solder. However, no complete failures were observed after 70 cycles.22 The fatigue test results indicate that the fatigue resistance of alloys can be ranked in increasing order: 63Sn-37Pb < 64Sn-36In < 58Bi-42Sn < 50Sn-50In < 99.25Sn-0.75Cu < 100Sn < 96Sn-4Ag.22 The microstructures of various Pb-free solder-Cu interfaces has been examined primarily by Suganuma.37 Most Sn alloys, including pure Sn, Sn-Ag, Sn-Bi, or their ternary alloys, form two IMCs at the interfaces with Cu [i.e., Cu6Sn5 (15 µm) and Cu3Sn (5 µm)]. The former is much thicker than the latter, and the interface integrity is strongly influenced by the presence of the Cu6Sn5 layer.37 A study of Siow et al. showed that 63Sn-37Pb solder joint has a higher toughness than that of 96.5Sn-3.5Ag. This trend could be attributed to the sharp Ag-rich phases present in the latter. Both types of solder joints failed by fracture through the solder instead of yielding, though there are signs of local plasticity. The failure mode was primarily microvoid nucleation and coalescence. Equiaxed dimples were observed in the fracture surface of the mode I loaded sample while elongated dimples were observed in the fracture surface of the mixed-mode loaded sample. Both solders preferred to fail in the shear mode.44 The temperature cycling performance of Pb-free solder joints has been reported in a number of works. Table 13.4 shows the brief summary on results of those work. Therefore, depending on the applications, the reliability of eutectic Sn-Ag may range from the best to the worst when compared with other alloys studied in those works. The performance of eutectic Sn-Ag appears to be comparable with eutectic Sn-Pb, with three cases being better46,48 and four cases being poorer14,50–52 than Sn-Pb.

TABLE 13.4 Temperature Cycling Performance of Sn-Ag-Bi, Sn-Ag-Bi-In, 96.5Sn-3.5Ag, 99.3Sn-0.7Cu, and SnPb—The Performance May Also Be Ranked in Descending Order for Some Works, with 1st Being the Best

Test condition

Application

SnPb

13.11

Pull strength, −40/+85°C

QFP with 90Sn10 Pb lead finish

Pull strength (Kgf), −40/+85°C

QFP

2nd; 3.1/0 cycle, 2.1/200 cycle, 1.9/500 cycle

−40/+80°C, crack

SMD

3rd

0/+100°C 10,000 cycles, shear strength

SMD

2nd

−50/+150°C

PBGA

1×

0/100°C, 30-min cycle

CBGA

Poorest

96.5Sn-3.5Ag

1st

99.3Sn-0.7Cu

Sn-Ag-Bi

Sn-Ag-Bi-In

Notes/ References

2nd (Sn-Ag-3Bi), ∼1st; 3rd (Sn-Ag-6Bi, or -10Bi, or -15Bi)

Ref. 45

1st (93.5Sn-3.5Ag3Bi) 2/0 cycle, 2.1/200 cycles, 2.2/500 cycles on Pd-Ni

Ref. 45

2nd

Ref. 46 1st (91.84Sn-3.33Ag4.83Bi), no electrical failure, shear strength higher than fresh Sn63

>2× Sn-Pb (but high modulus causes pad trace fracture)

Ref. 47

Ref. 48

96.5Sn-3.5Ag-3Bi ∼ 95.5Sn-3.8Ag-0.7Cu > 63Sn-37Pb

Ref. 49

TABLE 13.4 Temperature Cycling Performance of Sn-Ag-Bi, Sn-Ag-Bi-In, 96.5Sn-3.5Ag, 99.3Sn-0.7Cu, and SnPb—The Performance May Also Be Ranked in Descending Order for Some Works, with 1st Being the Best (Continued)

Test condition

Application

SnPb

96.5Sn-3.5Ag

99.3Sn-0.7Cu

Sn-Ag-Bi

Sn-Ag-Bi-In

Notes/ References

13.12

0/100°C, 60-min cycle

CBGA

Poorest

96.5Sn-3.5Ag-3Bi ∼ 95.5Sn-3.8Ag-0.7Cu > 63Sn-37Pb

Ref. 49

0/100°C, 240min cycle

CBGA

Poorest

96.5Sn-3.5Ag-3Bi > 95.5Sn-3.8Ag-0.7Cu ≥ 63Sn-37Pb

Ref. 49

−40/+125°C, 42min cycle, fatigue life

CBGA

1×

96.5Sn-3.5Ag-3Bi ≥ 95.5Sn-3.8Ag-0.7Cu ≥ 63Sn-37Pb

Ref. 49

−40/+125°C, 240-min cycle, fatigue life

CBGA

1×, poorer than 95.5Sn3.8Ag0.7Cu

96.5Sn-3.5Ag-3Bi slightly poorer than 63Sn-37Pb

Ref. 49

−40/+60°C, 30min cycle, fatigue life

CBGA

Poorest

95.5Sn-3.8Ag-0.7Cu ≥ 96.5Sn-3.5Ag-3Bi > 63Sn-37Pb

Ref. 49

−50/+150°C, fatigue life

PBGA

Sn-Ag ball/Sn-Pb paste > Sn-Ag ball/SAC paste Ⰷ Sn62 ball/SAC paste > Sn62 ball/Sn63 paste

Ref. 48

−40/+125°C, fatigue life

PBGA

Sn-Ag ball/Sn63 paste > Sn-Ag ball/SAC paste Ⰷ Sn62 ball/SAC paste, Sn62 ball/Sn63 paste

Ref. 48

−40/+125°C, fatigue life

FlexBGA Flip chip

6th–7th

8th

2nd

Ref. 50* Best on cracking

13.13

Fatigue life

Flip chip, unfilled

Fatigue life

Flip chip

0/+100°C

General

−40/+85°C, tensile test

General

1st

−40/+85°C, shear test

General

2nd ∼1st

Fatigue cycle life

General

1st

Fatigue cycle life

General

3rd

Ref. 14

30–60% of Sn63

2nd 2nd (on NiP-Au)

Ref. 51

3rd

1st

Ref. 52

3rd

1st

Ref. 14 2nd (Sn-Ag-3Bi), ∼1st

Ref. 45

1st (Sn-Ag-3Bi)

Ref. 45

2nd, close to 1st

Ref. 53 4th (3Bi), 7th (4.8Bi), 8th (7.5Bi)

2nd (2.5In2.5Bi), 6th (3In0.5Bi)

Refs. 54 and 55, with Sn-Ag-Cu best in cycle life

* CBGA, ceramic ball grid array; PBGA, plastic ball grid array; QFP, quad flat pack; SAC, Sn-Ag-Cu; SMD, surface-mount device. † Fatigue life: 1st (3.5Ag-1.5In), 2nd (Sn-2.5Ag-0.8Cu-0.5Sb), 3rd (Sn-4Ag-1Cu); 4th (Sn-4.6Ag-1.6Cu-1Sb-1Bi), 5th (Sn-4Ag-0.5Cu), 6th (Sn-3.4Ag-1Cu-3.3Bi) ∼ 7th.

13.14

CHAPTER THIRTEEN

Plastic ball grid arrays (PBGAs) with eutectic Sn-Ag spheres performed a minimum of two times better than Sn-Pb-Ag spheres in two automotive thermal cycling conditions, −50 to 150°C and −40 to 125°C,48 as shown in Figs. 13.11 and 13.12. The higher modulus of the Sn-Ag solder balls appeared to put more stress on the traces connected to non-solder-mask-defined (NSMD) motherboard pads resulting in fractures and opens, but only in the most severe cycling condition of −50 to 150°C. For Pb-free spheres, the Sn-Ni IMC appeared to grow at the same rate in both 125 and 150°C. whereas the growth rate in the Pb-containing PBGAs baked at 150°C was 2.6 times of that at 125°C. Shangguan reported that 96.5Sn-3.5Ag eutectic solder has superior overall properties and is suitable for solder interconnects in thick-film automotive electronics packages when used with a mixed bonded Ag conductor.56 For 0.4-mm-pitch surface-mount technology (SMT) assembly applications,Artaki et al. concluded that eutectic Sn-Ag, together with eutectic Sn-Bi and 91.8Sn-4.8Bi-3.4Ag, 77.2Sn-20In2.8Ag, and 96.2Sn-2.5Ag-0.8Cu-0.5Sb, are all feasible, although with narrower processing windows.57 This narrow processing window is concurred by Yang et al.,58 who studied the effect of processing conditions on joint quality, and concluded that low soldering temperatures, fast cooling rates, and short renew times are suggested for producing joints with the best shear strength, ductility, and creep resistance.

13.2 13.2.1

EUTECTIC Sn-Cu Physical Properties

Some physical properties of 99.3Sn-0.7Cu can be found in Table 13.1. The melting temperature of eutectic Sn-Cu is the highest among the prevailing Pb-free solders, suggesting a greater difficulty in adopting this alloy. Its surface tension, electrical resistivity, and density are comparable with eutectic Sn-Ag, presumably due to the high content of Sn in both alloys.

13.2.2

MECHANICAL PROPERTIES

The tensile and shear properties of 99.3Sn-0.7Cu are shown in Table 13.2 and Fig. 13.2. Eutectic Sn-Cu is lower in tensile strength but higher in elongation than both eutectic Sn-Ag and Sn-Pb, reflecting the softness and ductility of Sn-Cu. On the other hand, shear strength of Sn-Cu appears to be comparable with Sn-Pb, but lower than Sn-Ag. The creep strength of eutectic Sn-Cu is higher than 100Sn, but lower than eutectic Sn-Ag and Sn-Ag-Cu at both 20 and 100°C, as shown in Table 13.3. The data are consistent with the creep-rupture data shown in Figs. 13.4 and 13.5, where the time to rupture increases in the following order: eutectic Sn-Ag, Sn-Ag-Cu < eutectic SnCu < 60Sn-40Pb at 25 and 100°C.

13.2.3

WETTING PROPERTIES

The wetting properties of eutectic Sn-Cu and eutectic Sn-Ag are considered by Vincent et al. as having a great potential as replacements for Sn-Pb in wave and reflow processes.59 Wetting balance test results by Hunt et al., as shown in Fig. 13.6, indicate

13.15 FIGURE 13.11 Two-parameter Weibull plot as of 5619 thermal cycles of −50 to 150°C. No solder joint failures had been recorded on the configuration with SnAg solder balls assembled with Sn-Pb paste.

13.16 FIGURE 13.12 Two-parameter Weibull plot as of 9187 thermal cycles of −40 to 125°C. Only one failure had been recorded on the configuration with Sn-Ag solder balls assembled with Sn-Pb paste, and this occurred at 7555 cycles.

PREVAILING LEAD-FREE ALLOYS

13.17

that the wetting ability decreases in the following order: eutectic Sn-Pb > Sn-AgCu > Sn-Ag > Sn-Cu when an unactivated flux is used.28 The difference in wetting vanishes when an activated flux is used and when the wetting time is plotted against superheating, as shown in Fig. 13.9.28 However, depending on the test conditions of the wetting balance test, wetting time of eutectic Sn-Cu may also be shorter than eutectic Sn-Pb, as demonstrated in Fig. 13.10.30 In the Prismark report, Nortel found soldering quality equal to eutectic Sn-Pb in Meridian desktop telephone manufacturing. However, in air reflow the wettability was reduced, the fillet exhibited a rough and textured appearance, and the flux residue was dark brown.60 Preferably the use of eutectic Sn-Cu should be confined to wave soldering because low solder cost and inerting of waves is not costly. At reflow, on a full scale of 0 to 10, the reflow spreading of eutectic Sn-Cu (5.2/10) is better than eutectic Sn-Ag (4.6/10), but it is considerably poorer than eutectic Sn-Pb (9.8/10), as reported by Huang and Lee.29 Toyoda also studied spreading performance of several alloys, and observed the following spreading behavior in decreasing order: 63Sn-37Pb > Sn-Ag-Cu-4.5Bi, Sn-Ag-Cu-7.5Bi > Sn-3.5Ag0.75Cu > 99.25Sn-0.75Cu > 89Sn-8Zn-3Bi, as shown in Fig. 13.13.46

13.2.4

RELIABILITY

Although the tensile strength of eutectic Sn-Cu is fairly poor, the fatigue resistance is fairly good. In Glazer’s study, the fatigue resistance increases in the following order: 63Sn-37Pb < 64Sn-36In < 58Bi-42Sn < 50Sn-50In < 99.25Sn-0.75Cu < 100Sn < 96Sn-4Cu.22 However, the low-cycle isothermal fatigue (strain 0.2 percent, 0.1 Hz, R = 0.8, 300 K) performance shows a different trend, as shown in Table 13.5.4 Here the number of cycles to failure for eutectic Sn-Cu is less than one-third of that for eutectic Sn-Pb. Table 13.4 shows that for the two cases involving comparison of Sn-Cu with Sn-Pb, the former is consistently better than the latter.14,52 In addition, Syed studied the thermal cycling reliability of Pb-free solder joints for several package assemblies.50

FIGURE 13.13 Spreading performance of several Pb-free solders and eutectic Sn-Pb.

13.18

CHAPTER THIRTEEN

TABLE 13.5 Relative Performance in Fatigue Resistance of Lead-Free Solders in Low-Cycle Isothermal Fatigue Test* Melting temperature (°C)

Nf†

88.5Sn-3Ag-0.5Cu-8In

195–201

19,501

91.5Sn-3.5Ag-1Bi-4In

208–213

12,172

92.8Sn-0.7Cu-0.5Ga-6In

210–215

10,800

95.4Sn-3.1Ag-1.5Cu

216–217

8,936

96.2Sn-2.5Ag-0.8Cu-0.5Sb

216–219

8,751

95.5Sn-3.5Ag-1Bi

219–220

8,129

94.5Sn-0.5Ag-2Cu-3Sb

218–232

7,120

95Sn-2Cu-3Sb

227–234

6,821

93.3Sn-3.1Ag-3.1Bi-0.5Cu

209–212

6,522

96.5Sn-0.5Ag-3Bi

223–226

4,283

221

4,186

Alloy

96.5Sn-3.5Ag 92Sn-3.3Ag-4.7Bi 63Sn-37Pb 91.7Sn-3.5Ag-4.8Bi 99.3Sn-0.7Cu

210–215

3,850

183

3,650

211–215

3,179

227

1,125

* Strain, 0.2 percent; 0.1 Hz; R = 0.8; 300 K. † Nf: number of cycles to failure at 300 K (50 percent load drop, 0.2 percent strain range).

For a 27-mm, 256-PBGA assembly, at 0 to 100°C cycling, no failures in any alloys were observed after 9730 cycles.At −55 to 125°C cycling, after 6830 cycles, more than 50 percent failure rate occurred in eutectic Sn-Pb, Sn-Ag, and Sn-Cu. Eight failures occurred in Sn-3.4Ag-0.7Cu (30 percent higher life performance than Sn-Pb), and one failure at 6288 cycles occurred in Sn-4Ag-0.5Cu. At −40 to 125°C cycling, after 5080 cycles, Sn-Pb and Sn-Cu just started to fail, while no failures were observed in Sn-Ag, Sn-4Ag-0.5Cu, and Sn-3.4Ag-0.7Cu. For a 12-mm, 144-flexible ball grid array (fleXBGA) assembly, at 0 to 100°C cycling, eutectic Sn-Cu is 1.4 times better in performance than Sn-Pb, as shown in Fig. 13.14.50 Sn-4Ag-0.5Cu and Sn-3.4Ag-0.7Cu are similar in performance, and both are 1.6 to 1.7 times better in performance than eutectic Sn-Pb. Sn-Ag is the best, with no failure recorded after 10,740 cycles.At −55 to 125°C cycling, eutectic Sn-Cu is better in performance than Sn-Pb, as shown in Fig. 13.15.50 Sn-4Ag-0.5Cu and Sn-3.4Ag0.7Cu are comparable, both being 20 percent better in performance than Sn-Pb. Sn-Ag again is the best, with only three failures observed, and is 1.4 times better in performance than Sn-Pb. At −40 to 125°C cycling, Sn-Cu is similar to Sn-Pb in performance, as shown in Fig. 13.16.50 Not much improvement is observed for Sn-Ag-Cu over Sn-Pb, with Sn-4Ag-0.5Cu being slightly better than Sn-3.4Ag-0.7Cu. Eutectic Sn-Ag again comes to the top and is 1.4 times better in performance than Sn-Pb. For ball grid array (BGA) assembly, eutectic Sn-Cu may seem to be inferior to eutectic Sn-Ag in temperature cycling performance; however, the opposite trend is observed for flip chip assembly, as shown in Table 13.4. In Maestrelli’s study, eutectic Sn-Cu is observed to be the best in temperature cycling (0 to 100°C) performance, with Sn-4Ag-0.5Cu and eutectic Sn-Pb being the next, while eutectic Sn-Ag turns out to be the poorest in performance, as shown in Fig. 13.17.14 The higher reli-

PREVAILING LEAD-FREE ALLOYS

FIGURE 13.14 Temperature cycling (0 to 100°C) performance for 12-mm 144fleXBGA assembly.

13.19

13.20

CHAPTER THIRTEEN

FIGURE 13.15 Temperature cycling (−55 to 125°C) performance for 12-mm 144-fleXBGA assembly.

PREVAILING LEAD-FREE ALLOYS

13.21

FIGURE 13.16 Temperature cycling (−40 to 125°C) performance for 12-mm 144-fleXBGA assembly.

13.22

CHAPTER THIRTEEN

FIGURE 13.17 Plot of fatigue life as a function of thermal strain for a variety of solders over a temperature range of 0 to 100°C.

ability of eutectic Sn-Cu in flip chip applications is attributed to its compliant nature. Figure 13.18 shows the cross-section of flip chip solder joints after the same number of thermal cycles.14 Both Sn-Pb and Sn-Ag-Cu display a fracture without solder joint deformation. Sn-Cu solder joints, on the other hand, exhibits a deformed solder interconnect.This deformation of solder material due to the compliant nature of sol-

FIGURE 13.18 Flip chip solder interconnects after the same number of thermal cycles for eutectic Sn-Pb, Sn-Cu, and Sn-Ag-Cu.

PREVAILING LEAD-FREE ALLOYS

13.23

der is considered helpful in offsetting the impact of mismatch in the coefficient of thermal expansion (CTE), and hence is the main reason for Sn-Cu to be superior in fatigue life performance under an application with a large mismatch in CTE. Frear et al. also reported that for flip chip assembly, the thermal fatigue life descends in the following order: eutectic Sn-Cu > Sn-3.8Ag-0.7Cu, eutectic Sn-Pb > eutectic Sn-Ag.52

13.3

Sn-Ag-Bi AND Sn-Ag-Bi-In

As discussed in an earlier chapter, Sn-Ag-Bi is favored by Brite Euram, Department of Trade Industry of UK, NEMI of USA, and JEIDA. Sn-Ag-Bi-In is not investigated as extensively as Sn-Ag-Bi system. However, it is recommended by JEIDA, and is one of the major Pb-free alloys used for reflow soldering in Japan, as shown in Fig. 12.10.

13.3.1

PHYSICAL AND MECHANICAL PROPERTIES

The equilibrium phase diagram of the Sn-Ag-Bi system is shown in Fig. 13.19.61 The ternary eutectic point exhibits a melting temperature around 138°C, which is fairly comparable with the binary eutectic Sn-Bi alloy. For the ternary Sn-Ag-Bi composition with a narrow pasty range and a melting temperature close to 63Sn-37Pb, the

FIGURE 13.19 Equilibrium phase diagram for Sn-Ag-Bi system.

13.24

CHAPTER THIRTEEN

desirable composition can be prescribed by the shaded area in the lower left corner. Unlike the ternary eutectic point where the composition can be narrowed down easily, the desirable Sn-Ag-Bi composition for the higher melting temperature range cannot be identified easily. The most favorable composition appears to contain 1 to 5 at % Bi and 1 to 4 at% Ag, with the balance as Sn, as shown in Table 13.6. Also shown in Table 13.6 are the physical and mechanical properties of Sn-Ag-Bi and SnAg-Bi-In alloys, with eutectic Sn-Pb included for comparison. In most instances, the data listed from the same source were determined under the same test conditions. Most of the Sn-Ag-Bi alloys exhibit a pasty range from 210 to 220°C. Few alloys have a lower solidus temperature, but a wider pasty range, such as 90.5Sn-2Ag-7.5Bi. Additional Sn-Ag-Bi melting temperature information can be found in Fig. 12.6. In all instances except for 96.5Sn-0.5Ag-3Bi, the melting temperature is higher than that of 63Sn-37Pb, but lower than eutectic Sn-Cu (227°C) or Sn-Ag (221°C), suggesting a slight advantage on soldering temperature. On the other hand, the surface tension of Sn-3.5Ag-4.8Bi is higher than 63Sn-37Pb, implying a disadvantage in solder spreading. The density of Sn-3.4Ag-4.8Bi (7.53 g/cm3) is close to that of pure Sn (7.3 gm/cm3), due to the high content of Sn. The lower density of Sn-Ag-Bi system than eutectic Sn-Pb (8.4 g/cm3) indicates that a reduced solder weight of the joints can be expected. The hardness of Sn-Ag-Bi, as demonstrated by Sn-3Ag-5Bi (29.9 HV), is considerably higher than both eutectic Sn-Pb (12.9 HV) and Sn-Ag (16.5 HV) (see Table 13.1), and may pose a greater resistance against solder deformation during temperature cycling of assemblies. Tensile strength, yield strength, and shear strength of Sn-Ag-Bi systems are significantly higher than eutectic Sn-Pb, while the elongation or plasticity is much lower than Sn-Pb. This is consistent with the high hardness of Sn-Ag-Bi, mentioned earlier. Baggio studied the Sn-Ag-Bi system for Panasonic Mini Disk Player applications.45 By replacing some Sn of 96.5Sn-3.5Ag with Bi, the pull strength decreases linearly with increasing content of Bi, while the melting point decreases rapidly first, then decreases at a slower linear rate at Bi content above 6 percent, as shown in Fig. 12.6. Figs. 13.20 and 13.21 show examples of tensile stress-strain behavior for Sn-Ag-Bi and Sn-Ag-Bi-In systems, respectively, with 63Sn-37Pb and 96.5Sn-3.5Ag included for comparison.4 Addition of In to Sn-Ag-Bi enhances either the strength or the plasticity and is considered the optimal lead-free solder by Hwang4 in the absence of Cu, if aiming for a melting temperature of less than 215°C. In the study by Tanaka et al. on lead-free solders for mobile equipment, the impact resistance of solders descends in the following order: Sn-3.5Ag-0.75Cu > Sn-3Ag-1In-0.7Cu > Sn-3.5Ag0.5Bi-3In > 63Sn-37Pb > Sn-3.2Ag-3Bi-1.1Cu-Ge, Sn-Ag-X, as shown in Fig. 13.22.5 The superior impact resistance of Sn-Ag-Bi-In is attributed to the high plasticity of solder due to the presence of In. The creep rate of eutectic Sn-Ag-Bi is slightly lower than that of Sn-Ag-Cu and of Sn-Ag, and it is much lower than that of 60Sn-40Pb and eutectic Sn-Bi at low stress, presumably due to the high hardness and high strength of the Sn-Ag-Bi system, as indicated by Fig. 13.3. In the creep rupture tests conducted by Tanaka et al., the creep rupture performance of Sn-3.5Ag-0.5Bi-3In, as well as Sn-3.5Ag-0.75Cu, Sn-3Ag1In-0.7Cu, Sn-3.2Ag-3Bi-1.1Cu-Ge, and Sn-Ag-X, are all better than 63Sn-37Pb.5

13.3.2

WETTING PROPERTIES

Presence of Bi significantly improves the solder spreading properties of lead-free solders. In the reflow soldering compatibility study done by Huang and Lee, the solder spreading performance at solder paste reflow increases in the following order: 89Sn-8Zn-3Bi (0.5) < 96.5Sn-3.5Ag (4.6) < 95Sn-5Sb (4.7) < 99.3Sn-0.7Cu (5.2),

13.25

PREVAILING LEAD-FREE ALLOYS

TABLE 13.6 Physical and Mechanical Properties of Sn-Ag-Bi, Sn-Ag-Bi-In, and 63Sn-37Pb Systems Notes/ References

Property

Sn-Ag-Bi

Sn-Ag-Bi-In

63Sn-37Pb

Melting temperature (°C)

208–217 (93.5Sn3.5Ag-3Bi) 219–220 (95.5Sn3.5Ag-1Bi) 216–220 (95Sn3Ag-2Bi) 215–221 (95.5Sn2.5Ag-2Bi) 223–226 (96.5Sn0.5Ag-3Bi) 219–220 (95.5Sn3.5Ag-1Bi) 210 (92Sn-3Ag5Bi) 202–215 (91.8Sn3.5Ag-4.8Bi) 191–215 (90.5Sn2Ag-7.5Bi) 213 (94Sn-3Ag3Bi)

—

183

Ref. 13

208–213 (91.5Sn3.5Ag-1Bi-4In)— —

—

Ref. 4

—

Ref. 13

—

—

Ref. 13

—

—

Ref. 4

—

—

Ref. 4

—

—

—

—

Ref. 29

—

—

Ref. 29

—

—

—

—

Surface tension (dyne/cm)

420 (Sn-3.5Ag4.8Bi)

—

380 (260°C)

Ref. 62

Density (g/cm3)

7.53 (Sn-3.4Ag4.8Bi)

—

8.4

Ref. 29

Electrical resistivity (µΩ-cm)

11.6 (Sn-3Ag5Bi)

17

Ref. 63

Hardness [Vickers hardness (HV), kg/mm2]

29.9 (Sn-3Ag5Bi)

—

12.9

Ref. 63

Ultimate tensile strength (MPa)

82.5 (92Sn-3.3Ag4.7Bi) 43 (95.5Sn-3.5Ag1Bi) 54.7 (Sn-3Ag-2Bi)

—

46

—

—

52.2 (Sn-2.5Ag2Bi) 92.7 (Sn-2.5Ag19.5Bi) 71.4 (Sn-3.4Ag4.8Bi) Yield strength, 0.2% (MPa)

37.7 (Sn-3Ag-2Bi) 45.5 (Sn-2.5Ag2Bi) 83.2 (Sn-2.5Ag19.5Bi) 46.3 (Sn-3.4Ag4.8Bi)

12.1 (Sn-3Ag-5Bi5In)

106.0 (Sn-2Ag9.8Bi-9.8In) —

30.6

6.56 × 10−4/s, 300 K, Ref. 4 6.56 × 10−4/s, 300 K, Ref. 4 Ref. 13

—

Ref. 13

—

—

Ref. 13

—

—

Ref. 13

27.2

Ref. 13

—

Ref. 13

—

—

Ref. 13

—

—

Ref. 13

100.4 (Sn-2Ag9.8Bi-9.8In) —

13.26

CHAPTER THIRTEEN

TABLE 13.6 Physical and Mechanical Properties of Sn-Ag-Bi, Sn-Ag-Bi-In, and 63Sn-37Pb Systems (Continued)

Property Elongation (%)

Sn-Ag-Bi 10 (92Sn-3.3Ag4.7Bi) 31 (95.5Sn-3.5Ag1Bi) 30 (Sn-3Ag-2Bi) 26 (Sn-2.5Ag-2Bi) 17 (Sn-2.5Ag19.5Bi) 16 (Sn-3.4Ag4.8Bi)

Shear strength (MPa)

81.36 (Sn-3.33Ag4.83Bi)

Impact strength (J/cm2)

—

Sn-Ag-Bi-In

63Sn-37Pb

Notes/ References

48

6.56 × 10−4/s, 300 K, Ref. 4 6.56 × 10−4/s, 300 K, Ref. 4 Ref. 13

— —

Ref. 13 Ref. 13

—

—

Ref. 13

—

40.27

Ref. 36

31

Ref. 5

13 (90Sn-3.3Ag3Bi-3.7In) 30 (91.5Sn-3.5Ag1Bi-4In) 7 (Sn-2Ag-9.8Bi9.8In) — —

48 (Sn-3.5Ag0.5Bi-3In)

31 —

96.2Sn-2.5Ag-0.8Cu-0.5Sb (5.2) < 93.6Sn-4.7Ag-1.7Cu (5.3) < 95.5Sn-3.8Ag-0.7Cu (5.4) < 58Bi-42Sn (6.0) < 91.7Sn-3.5Ag-4.8Bi (6.8) < 90.5Sn-7.5Bi-2Ag (7.0) < 63Sn37Pb (9.8).29 The figures in parentheses represent the scores of spreading, with a score of 10 representing full spreading. 63Sn-37Pb exhibits the best spreading performance. Among the Pb-free alloys, except for Zn-containing solder, all Bicontaining solders, including 58Bi-42Sn, 91.7Sn-3.5Ag-4.8Bi, and 90.5Sn-7.5Bi-2Ag, display a better wetting than non-Bi-containing alloys. Among the three Bicontaining alloys, eutectic Sn-Bi is too low in melting temperature as a drop-in replacement for 63Sn-37Pb, and Sn-Ag-Bi systems are the most attractive due to their higher melting temperature and superior wettability.

13.3.3

RELIABILITY

Bi-containing Pb-free alloys are sensitive to the presence of Pb, due to the formation of a 52Bi-30Pb-18Sn ternary eutectic structure with a melting temperature of 96°C in the solidified solder joint. The solder joints become weak in mechanical strength when subjected to thermal cycling with the temperature exceeding 96°C because the low-melting ternary eutectic phase accelerates grain growth and phase agglomeration.64 Bi-containing solders also tend to have a fillet-lifting phenomenon, particularly at the wave-soldering stage, therefore posing reliability concerns.65 Both failure mechanisms will be discussed in detail in Chap. 16. Hwang studied the isothermal low-cycle fatigue performance of a series of Pb-free solders, as shown in Fig. 13.4.4 Among the alloys investigated, Sn-Ag-Bi systems are comparable or better than 96.5Sn-3.5Ag and 63Sn-37Pb, and are considerably better than 99.3Cu-0.7Sn. The low-cycle fatigue life performance (numbers in parentheses) can be ranked as follows: 95.5Sn-3.5Ag-1Bi (8129) > 96.5Sn-0.5Ag-3Bi (4283) > 96.5Sn-3.5Ag (4186) > 92Sn-3.3Ag-4.7Bi (3850) > 63Sn-37Pb (3650) > 91.7Sn-3.5Ag4.8Bi (3179) > 99.3Sn-0.7Cu (1125).

PREVAILING LEAD-FREE ALLOYS

13.27

FIGURE 13.20 Tensile stress-strain properties of 92Sn-3.3Ag-4.7Bi, 95.5Sn-3.5Ag-1Bi, 96.5Sn3.5Ag, and 63Sn-37Pb at 300 K and 6.56 × 10−4/s.

FIGURE 13.21 Tensile stress-strain properties of 90Sn-3.3Ag-3Bi-3.7In, 91.5Sn-3.5Ag1Bi-4In, 96.5Sn-3.5Ag, and 63Sn-37Pb at 300 K and 6.56 × 10−4/s.

13.28

CHAPTER THIRTEEN

FIGURE 13.22 Charpy impact test results for several lead-free alloys and 63Sn-37Pb.

It is interesting to note that all three In-containing alloys, including Sn-Ag-Bi-In, are ranked at the top of the list, with Sn-Ag-Cu or Sn-Ag-Cu-X being equal or better than Sn-Ag-Bi systems. Presumably, the superior low-cycle fatigue performance of In-containing alloys might be attributed to the enhanced plasticity introduced by In. The temperature cycling fatigue performance of Sn-Ag-Bi and Sn-Ag-Bi-In systems are shown in Table 13.4. Again, the performance is highly dependent on applications. Therefore, in four cases,45,49,54,55 Sn-Ag-Bi systems are inferior to Sn-Pb or 62Sn-36Pb-2Ag, while in eight other cases, the trend is opposite.45,47,49 Bradley studied the temperature cycling reliability of Sn-Ag-X systems, with results shown in Fig. 13.23.54,55 In his results, all three Sn-Ag-Bi alloys are more inferior than 62Sn-36Pb-2Ag, and the performance descends with increasing Bi content: SnAg-3Bi > Sn-Ag-4.8Bi > Sn-Ag-7.5Bi. The favorable performance of lower Bi content is also observed by Baggio, as shown in Fig. 13.24.45 Here the pull strength of solder joints is plotted as a function of number of cycles. Sn-Ag-Bi systems with 3 percent Bi exhibit the best performance, and are comparable with Sn-Pb. For Sn-Ag-Bi alloys with 6 to 15 percent Bi content, the pull strength dropped considerably, although it remains stable with an increasing cycle number. The work of Vianco et al. indicates that Sn-Ag-Bi is far more superior than eutectic Sn-Pb in a thermal fatigue test.47 In their study, an evaluation was performed that

FIGURE 13.23 Reliability performance of Sn-Ag-X alternatives.

PREVAILING LEAD-FREE ALLOYS

13.29

FIGURE 13.24 Reliability of Sn-Ag-Bi and Sn-Pb systems.

examined the reliability of surface-mount solder joints made with a 91.84Sn-3.33Ag4.83Bi alloy. A 1206-chip capacitor, an SOIC gull-wing, and plastic leaded chip carrier (PLCC) J-lead solder joints were thermally cycled between 0 and 100°C for 1,000, 2,500, 5,000, or 10,000 cycles. Continuous dc signal monitoring did not reveal any open events through the 10,000-cycle mark, and there was no evidence of solder degradation for any of the evaluated solder joint geometries through 2,500 cycles. Thermal cycles of 5,000 and 10,000 caused some surface cracks and isolated throughcracks in the thinner reaches of the solder fillets, as shown in Fig. 13.25.47 However, it should be pointed out that regardless of the development of cracks, the Sn-Ag-Bi still exhibits a shear strength greater than the as-fabricated 63Sn-37Pb solder joints after 10,000 thermal cycles, as shown in Fig. 13.26.47 Bartelo reported that at the 0/100°C temperature cycling condition with cycle times from 30 to 240 min, the joint reliability of 96.5Sn-3.5Ag-3Bi is comparable or better than 95.5Sn-3.8Ag-0.7Cu, which in turn is better than 63Sn-37Pb when assembling 625 I/O CBGA with 32 × 32 × 0.8 mm dimension.49 For temperature range −40/+125°C thermal cycling test, 96.5Sn-3.5Ag-3Bi was better than 63Sn-37Pb at 42 min cycle time, but slightly poorer than Sn-Pb at a 240-min cycle time.49 For −40/60°C temperature cycling condition with 30-min cycle time, Sn-Ag-Cu is slightly better than Sn-Ag-Bi, and both are better than 63Sn-37Pb. In Bartelo’s study, the alloys used for solder ball and solder paste are the same. The superior thermal cycling fatigue performance of the Sn-Ag-Bi system perhaps can be partly attributed to its high rigidity and thus low creep rate. This high rigidity is mainly caused by two solder-strengthening mechanisms. The first is solution strengthening, achieved by dissolving 4 to 5 percent Bi into Sn. The second is precipitation strengthening, achieved by Bi and Ag3Sn particles, as shown in Fig. 13.27.47 The high concentration of Ag3Sn and Bi precipitates is also responsible for the rough and grainy solder joint appearance, as shown in Fig. 13.28.47 Addition of In to the Sn-Ag-Bi systems significantly improves the fatigue resistance, as shown in Table 13.5 for isothermal low-cycle fatigue and in Fig. 13.21 for temperature cycling performance. In the former case, the Sn-Ag-Bi-In is far superior than eutectic Sn-Pb, while in the latter case, both systems are comparable in performance.

13.30

CHAPTER THIRTEEN

FIGURE 13.25 Maximum shear load (N) versus fillet-top cracking of the 1206-chip capacitor 91.84Sn-3.33Ag-4.83Bi solder joints as a function of number of thermal cycles at condition 0/+100°C. Note that the cracks developed with an increasing number of cycles.

FIGURE 13.26 Maximum shear load (N) versus fillet-top cracking of the 1206-chip capacitor 91.84Sn-3.33Ag-4.83Bi solder solder joints as a function of number of thermal cycles at condition 0/+100°C. Note that the shear load of Sn-Ag-Bi is higher than or equal to as-fabricated 63Sn-37Pb joints, even up to 10,000 thermal cycles.

13.31

PREVAILING LEAD-FREE ALLOYS

(a)

(b)

FIGURE 13.27 Microstructure of 91.84Sn-3.33Ag-4.83Bi. (a) Scanning electron microscope (SEM) photograph; (b) thermal expansion mismatch (TEM) photograph. The solder is strengthened by (1) solution strengthening (Sn with 4 to 5 percent Bi) and (2) precipitation strengthening (Bi and Ag3Sn particles).

13.4

Sn-Ag-Cu AND Sn-Ag-Cu-X

Sn-Ag-Cu is the most prevailing choice of Pb-free alternative globalwise. Besides that, the Sn-Ag-Cu-X family (including Sn-Ag-Cu-In, Sn-Ag-Cu-Bi, Sn-Ag-Cu-Sb— particularly the latter two) also received quite a lot of attention and will be introduced in more detail later.

13.4.1

PHYSICAL PROPERTIES

The physical properties of Sn-Ag-Cu, Sn-Ag-Cu-In, Sn-Ag-Cu-Bi, Sn-Ag-Cu-Sb, and 63Sn-37Pb are shown in Table 13.7. Figure 13.29 shows the Sn-Ag-Cu phase diagram, as reported by Handwerker.61 NIST experimental work showed that the ternary eutectic composition is approxi-

(a)

(b)

FIGURE 13.28 The as-fabricated solder joints made with the 91.84Sn-3.33Ag-4.83Bi solder. (a) SEM micrograph; (b) optical micrograph.

13.32

CHAPTER THIRTEEN

TABLE 13.7 Physical Properties of Sn-Ag-Cu, Sn-Ag-Cu-X, and 63Sn-37Pb

Properties Melting temperature (°C)

63Sn37Pb 183

Sn-Ag-Cu 217 (95.5Sn3.8Ag0.7Cu) 216–217 (95.4Sn3.1Ag1.5Cu)

Density (g/cm3)

8.36

8.4

Electrical resistivity (µΩ-cm)

17

Sn-AgCu-In

Sn-AgCu-Bi

Sn-AgCu-Sb

207–216 (Sn-3.3 Ag-3Bi1.1Cu) 195–201 (88.5Sn3Ag0.5Cu8In)

209–212 (93.3Sn3.1Ag3.1Bi0.5Cu)

Notes/ References Ref. 66

216–219 (Sn-2.5Ag0.8Cu0.5Sb)

Ref. 4

218–232 (94.5Sn0.5Ag-2Cu3Sb)

Ref. 4

217–244 (93.6Sn4.7Ag1.7Cu)

Ref. 67

217 (95.6Sn3.5Ag0.9Cu)

Ref. 61

217–225 (95.5Sn4Ag0.5Cu)

Ref. 68

218 (95.75Sn3.5Ag0.75Cu)

Ref. 69

220 (96.5Sn3Ag0.5Cu)

Ref. 70

7.44 (Sn4Ag0.5Cu)

7.56 (Sn2Ag0.5Cu7.5Bi)

7.39 (Sn2.5Ag0.8Cu0.5Sb)

Ref. 71

7.39 (Sn4Ag0.5Cu)

Ref. 72

7.5 (Sn3.8Ag0.7Cu)

Ref. 8

10.6 (Sn3Ag-3Cu2Bi)

12.1 (Sn2.5Ag0.8Cu0.5Sb)

Ref. 63

13.33

PREVAILING LEAD-FREE ALLOYS

TABLE 13.7 Physical Properties of Sn-Ag-Cu, Sn-Ag-Cu-X, and 63Sn-37Pb (Continued) 63Sn37Pb

Properties

14.5

Hardness

Sn-Ag-Cu

Sn-AgCu-In

Sn-AgCu-Bi

Sn-AgCu-Sb

10–15 (Sn4Cu0.5Ag)

Ref. 3

13 (Sn3.8Ag0.7Cu)

Ref. 8

12.8

[Vickers hardness (HV), kg/mm2], Ref. 6 (HV), kg/mm2), Ref. 7

10.25 (as drawn), 12.45 (annealed) Sn-4.7 Ag-1.7Cu 28.6 (Sn3Ag-2Cu2Sb)

(HV, kg/mm2), Ref. 63

10.08

18.28 (Sn2.5Ag0.8Cu0.5Sb)

Rockwell hardness, 15-W scale hardness, Ref. 11

12.2

13.5 (Sn2.5Ag0.8Cu0.5Sb)

Rockwell hardness, 16-W scale hardness, Ref. 11 Brinell hardness, Ref. 8

12.9

34.5 (Sn3Ag-3Cu2Bi)

15 (Sn3.8Ag0.7Cu) Surface tension (mN m−1)

380 at 260°C

510 (Sn2.5Ag0.8Cu0.5Sb)

417 (air), 464 (N2) at 233°C CTE (ppm)

Notes/ References

18.74

Ref. 62

Ref. 3

14.83 (Sn3Ag-4Cu)

Ref. 8

25

Ref. 2

21

Ref. 16

24 (−70°C, 20°C, 140°C)

Ref. 15

13.34

CHAPTER THIRTEEN

FIGURE 13.29 Sn-Ag-Cu phase diagram. Alloys in shaded area have a freezing range of less than 10°C.

mately 95.6Sn-3.5Ag-0.9Cu (±0.1 percent), with a melting point of 217°C. Around the ternary eutectic point, as shown by the shaded area in Fig. 13.29, there are a number of Sn-Ag-Cu compositions developed, with melting temperatures all within 10°C of the ternary eutectic melting temperature. Figure 13.30 shows several examples of differential scanning calorimeter (DSC) thermograms of such alloys.73 Although the exact ternary eutectic composition is to be determined, generally it is considered that the physical, mechanical, and soldering properties, and the reliability of Sn-AgCu compositions near this ternary eutectic point should be fairly comparable. The density and electrical resistivity of Sn-Ag-Cu and Sn-Ag-Cu-X are all comparable with each other, and are similar to other high-Sn alloys (see also Tables 13.1 and 13.6), due to the dominant presence of Sn. The hardness, however, does differ from system to system. Therefore, Sn-Ag-Cu is comparable with Sn-Pb, while Bicontaining alloys exhibit a considerably higher hardness than Sn-Pb. The high hardness can be explained by the precipitation and Bi-dissolution strengthening mechanisms, discussed in Sec. 13.3.3.

13.4.2

MECHANICAL PROPERTIES

The mechanical properties of Sn-Ag-Cu, Sn-Ag-Cu-In, Sn-Ag-Cu-Bi, Sn-Ag-Cu-Sb, and 63Sn-37Pb are shown in Table 13.8. Examples of tensile stress-strain relation at 300 K and 6.56 × 10−4/s for Sn-Ag-Cu, Sn-Ag-Cu-In, and Sn-Ag-Cu-Bi alloys, together with 63Sn-37Pb for comparison, are shown in Figs. 13.31, 13.32, and 13.33, respectively.4 Some additional information on the time to break in creep tests for several other alloys is shown in Fig. 13.34.46 The tensile strength of Sn-Ag-Cu is slightly higher [e.g., Sn-3.8Ag-0.7Cu or Sn3.5Ag-0.7Cu (Ref. 8)] or higher [e.g., Sn-4.7Ag-1.7Cu (Ref. 4)] than eutectic Sn-Pb. In the case of composition near the ternary eutectic point, such as Sn-3.8Ag-0.7Cu,

PREVAILING LEAD-FREE ALLOYS

13.35

FIGURE 13.30 Differential scanning calorimeter thermograms of four Sn-Ag-Cu solder alloys: (a) Sn-4Ag-0.5Cu, (b) Sn-3.6Ag-1Cu, (c) Sn-3.7Ag0.9Cu, and (d) Sn-3Ag-0.5Cu.

its yield strength,14 shear strength,8,18 impact strength,5 and creep resistance8 are all higher than Sn-Pb. Figure 13.34 shows that Sn-3.5Ag-0.75Cu exhibits the longest time to break in creep tests among all of the alloys tested, including both Pb-free and Sn-Pb alloys. For Sn-Ag-Cu alloys further away from ternary eutectic composition, such as 93.6Sn-4.7Ag-1.7Cu, not only does the melting temperature (217 to 244°C67) increase, but also the tensile4,7 and shear18 strengths increase, at the expense of reduction in elongation.4 The data on the mechanical properties of Sn-Ag-Cu-In system is fairly scarce. Hwang studied the yield strength σy, tensile strength σT, and plastic strain εp at fracture versus Ag contents for the Sn-Ag-Cu-In system at both 0.5Cu-8In and 0.5Cu4In, with results shown in Fig. 13.35.4 Results indicate that alloys with 8 percent In exhibit a higher yield strength and tensile strength but a lower plastic strain at fracture than alloys with 4 percent In. For an 8 percent In system, the optimal Ag content for tensile properties is 3 percent within the range of 0 to 4.1 percent Ag. The difference between 3 and 4.1 percent Ag alloys is fairly small, and all exhibit a higher tensile strength but a lower elongation than 63Sn-37Pb, as shown in Fig. 13.32. For a 4 percent In system, increasing Ag content from 3 to 4.1 percent results in a linear increase in tensile strength and yield strength, but a decrease in plastic strain.Tanaka et al.5 reported that Sn-3Ag-0.7Cu-1In exhibits a tensile strength comparable with that of 63Sn-37Pb. However, the former displays a considerably higher impact strength and an exceptionally lower creep rate than eutectic Sn-Pb (see Table 13.8 and Fig. 13.34).

13.36

CHAPTER THIRTEEN

TABLE 13.8 Mechanical Properties of Sn-Ag-Cu, Sn-Ag-Cu-In, Sn-Ag-Cu-Bi, Sn-Ag-Cu-Sb, and 63Sn-37Pb Properties Ultimate tensile strength (MPa)

63Sn-37Pb Sn-Ag-Cu 46

46

Sn-Ag-Cu-In

48.5 (95.4Sn3.1Ag1.5Cu); 75 (93.6Sn4.7Ag1.7Cu)

64

42 (Sn3.5Ag0.75Cu)

43 (Sn3Ag-1In0.7Cu)

(87.4Sn4.1Ag0.5Cu-8In); 63 (88.5Sn3Ag0.5Cu-8In)

Sn-Ag-Cu-Bi 78 (93.3Sn3.1Ag-3.1Bi0.5Cu)

Sn-Ag-Cu-Sb

Notes/References

36.5 (Sn2.5Ag0.8Cu0.5Sb)

6.56 × 10−4/s, 300 K, Ref. 4

Ref. 5

45.1

Ref. 6 44 (as drawn), 53 (annealed) 93.6Sn4.7Ag1.7Cu

Ref. 7

48 (for both Sn3.8Ag0.7Cu and Sn-3.5Ag0.7Cu)

Ref. 8

49.2

Ref. 9

40.7

38.3 (Sn2.5Ag0.8Cu0.5Sb)

Ref. 11

33.92

39.5 (Sn2.5Ag0.8Cu0.5Sb)

Ref. 11

52.8 (Sn3Ag-2Cu2Sb); 25.8 (Sn-2.6Ag0.8Cu0.5Sb); 29.8 (Sn0.2Ag-2Cu0.8Sb)

Ref. 13

31–46 30.6

Ref. 12 48.3 (Sn3Ag-4Cu); 29.7 (Sn0.5Ag4Cu)

92.7 (Sn-2Ag7.5Bi-0.5Cu)

26.7 Yield strength (MPa)

37

28.1, 30.2

Ref. 2 45 (Sn3.8Ag0.7Cu)

Ref. 14

27.8 and 33.5 (Sn-2.5Ag0.8Cu0.5Sb)

Ref. 11

13.37

PREVAILING LEAD-FREE ALLOYS

TABLE 13.8 Mechanical Properties of Sn-Ag-Cu, Sn-Ag-Cu-In, Sn-Ag-Cu-Bi, Sn-Ag-Cu-Sb, and 63Sn-37Pb (Continued) Properties

63Sn-37Pb Sn-Ag-Cu 27.2

Shear strength (MPa)

43.3 (Sn3Ag-4Cu); 25.7 (Sn0.5Ag4Cu)

Sn-Ag-Cu-In Sn-Ag-Cu-Bi 85.3 (Sn-2Ag7.5Bi-0.5Cu)

Sn-Ag-Cu-Sb

Notes/References

46.1 (Sn3Ag-2Cu2Sb); 22.8 (Sn-2.6Ag0.8Cu0.5Sb); 25.9 (Sn0.2Ag-2Cu0.8Sb)

Ref. 13

23

27 (Sn3.8Ag0.7Cu)

At 0.1 mm/min, 20°C, Ref. 8

14

17 (Sn3.8Ag0.7Cu)

At 0.1 mm/min, 100°C, Ref. 8

36.5 (Sn40Pb)

67 (Sn3.6Ag1.0Cu); 58 (Sn-4.7Ag1.7Cu); 63.8 (Sn3.8Ag0.7Cu)

64.1 (Sn3.8Ag0.7Cu0.5Sb)

At 0.1 mm/min; gap thickness: 76.2 µm; cooling rate = 10°/s, tested at 22°C, Ref. 18

4.5 (Sn40Pb)

24.4 (Sn3.6Ag1.0Cu); 21.6 (Sn4.7Ag1.7Cu); 25.1 (Sn3.8Ag0.7Cu)

28.9 (Sn3.8Ag0.7Cu0.5Sb)

At 0.1 mm/min; gap thickness: 76.2 µm; cooling rate = 10°/s; tested at 170°C, Ref. 18

34.5 (Sn40Pb)

At 1 mm/min at reflow temperature, Ref. 19

21.6 (Sn40Pb)

At 1 mm/min at 100°C, Ref. 19

40.27

Ring-and-plug test, Ref. 20

41.8

Ref. 21

28.4

Ref. 12

23.8

Ref. 2

48.4 Elongation (%)

31

Ref. 6 36.5 (95.4Sn3.1Ag1.5Cu); 20 (93.6Sn4.7Ag1.7Cu)

21.5 19 (93.3Sn(87.4Sn3.1Ag-3.1Bi4.1Ag0.5Cu) 0.5Cu-8In); 22.5 (88.5Sn3Ag0.5Cu-8In)

38.5 (Sn2.5Ag0.8Cu0.5Sb)

6.56 × 10−4/s, 300 K, Ref. 4

13.38

CHAPTER THIRTEEN

TABLE 13.8 Mechanical Properties of Sn-Ag-Cu, Sn-Ag-Cu-In, Sn-Ag-Cu-Bi, Sn-Ag-Cu-Sb, and 63Sn-37Pb (Continued) Properties

63Sn-37Pb Sn-Ag-Cu

Sn-Ag-Cu-In Sn-Ag-Cu-Bi

Sn-Ag-Cu-Sb

35.5

Ref. 6

43.66; 52.87

50 (Sn2.5Ag0.8Cu0.5Sb)

35–176 48

31

Young’s modulus (Gpa)

33.58

Creep

6

Ref. 11

Ref. 12 22 (Sn3Ag-4Cu); 27 (Sn0.5Ag4Cu)

12 (Sn-2Ag7.5Bi-0.5Cu)

32 (Sn3Ag-2Cu2Sb); 9 (Sn-2.6Ag0.8Cu0.5Sb); 27 (Sn-0.2Ag2Cu-0.8Sb)

35 Impact strength (J/cm2)

Notes/References

Ref. 68

Ref. 2 77 (Sn3.5Ag0.75Cu)

75 (Sn3Ag-1In0.7Cu)

Ref. 5

51.16 (Sn2.5Ag0.8Cu0.5Sb)

Ref. 11

(60Sn40Pb)

27 (Sn4Ag0.5Cu)

25°C, 100 h to failure, MPa, Ref. 24

2.8 (60Sn40Pb)

7.5 (Sn4Ag0.5Cu)

25°C, 1000 h to failure, MPa, Ref. 24

323 (Sn1Ag0.5Cu); 3849 (Sn3.5Ag0.75Cu)

1007 (Sn3Ag0.7Cu1In)

218 (Sn-Ag-Cu7.5Bi); 1747 (Sn-Ag-Cu4.5Bi); 2203 (Sn-Ag-Cu-2Bi)

Time to break (h), Ref. 46

13 for both Sn-3.5Ag0.7Cu and Sn-3.8Ag0.7Cu

Creep strength, N/mm2 at 0.1 mm/min, 20°C, Ref. 8

5.0 for both Sn3.5Ag0.7Cu and Sn-3.8Ag0.7Cu

Creep strength, N/mm2 at 0.1 mm/min, 100°C, Ref. 8

PREVAILING LEAD-FREE ALLOYS

13.39

FIGURE 13.31 Tensile stress-strain relationships of 93.6Sn-4.7Ag-1.7Cu, 95.4Sn-3.1Ag-1.5Cu, and eutectic Sn-Ag, Sn-Cu, and Sn-Pb alloys at 6.56 × 10−4/s, 300 K.

FIGURE 13.32 Tensile stress-strain relationships at 300 K and 6.56 × 10−4/s for 88.5Sn3Ag-0.5Cu-8In, 87.4Sn-4.1Ag-0.5Cu-8In, 95.4Sn-3.1Ag-1.5Cu, and 63Sn-37Pb.

13.40

CHAPTER THIRTEEN

FIGURE 13.33 Tensile stress-strain relationships at 300 K and 6.56 × 10−4/s for 93.3Sn-3.1Ag3.1Bi-0.5Cu, 96.5Sn-3.5Ag, 99.3Sn-0.7Cu, and 63Sn-37Pb.

FIGURE 13.34 Time to break for solder joints in creep tests for several solder alloys.

PREVAILING LEAD-FREE ALLOYS

13.41

FIGURE 13.35 Yield strength σy, tensile strength σT, and plastic strain εp at fracture versus Ag contents for Sn-Ag-Cu-In system at both 0.5Cu-8In and 0.5Cu-4In.

Sn-Ag-Cu-Bi alloys exhibit a higher tensile strength4,13 and yield strength,13 a lower elongation,4,68 and a slower creep rate46 than eutectic Sn-Pb. Figure 13.33 exemplifies the tensile stress-strain behavior of the Sn-Ag-Cu-Bi alloy versus eutectic Sn-Pb, Sn-Ag, and Sn-Cu systems. Toyoda observed that for the Sn-Ag-Cu system, the creep resistance, or time to break in creep test, increases considerably with addition of Bi, as shown in Fig. 13.34.46 Addition of 2 percent Bi results in a considerable increase in time to break (2203 h). However, further increase in Bi content results in a rapid drop in benefit in creep resistance, and the time to break is reduced down to 1747 h for 4.5 percent Bi and 218 h for 7.5 percent Bi, compared with 1 h for eutectic Sn-Pb. Figure 13.36 shows that the tensile strength of the Sn-Ag-Cu-Bi system increases with increasing Bi content, then levels off at around 10 percent Bi.46 On the other hand, the elongation of this system drops rapidly with increasing Bi content until it reaches the 3 percent level, then it decreases slowly and later levels off with further increase in Bi content. The Sn-Ag-Cu-Sb system exhibits a more diverse variation in mechanical properties as a function of composition. The most widely studied composition is 96.2Sn2.5Ag-0.8Cu-0.5Sb (CASTIN). CASTIN was reported to be comparable11 or lower4,13 in tensile strength, comparable11 or lower13 in yield strength, lower,68 comparable,4 or higher11 in elongation than eutectic SnPb. Other compositions of interest that were studied include Sn-3Ag-2Cu-2Sb,13 Sn-3.8Ag-0.7Cu-0.5Sb,18 and Sn-0.2Ag-2Cu-0.8Sb (SAF-A-LLOY).13 Sn-3Ag-2Cu-2Sb is higher in tensile strength and yield strength, but lower in elongation than eutectic Sn-Pb. Sn-3.8Ag0.7Cu-0.5Sb is higher in shear strength, while Sn-0.2Ag-2Cu-0.8Sb is comparable in tensile strength and yield strength, but lower in elongation than 63Sn-37Pb.

13.42

CHAPTER THIRTEEN

FIGURE 13.36 Effect of Bi content on the tensile strength and elongation of Sn-Ag-Cu-Bi and Sn-Zn-Bi alloys.

13.4.3

WETTING PROPERTIES

The wetting properties of Sn-Ag-Cu and Sn-Ag-Cu-X alloys are shown in Table 13.9. The contact angle results of Table 15.9, together with Fig. 13.7, indicate that alloy wetting decreases in the following order: 60Sn-40Pb > Sn-Ag-Cu > Sn-Ag-Cu-Sb.18,22 Spread test results of Baggio show 62Sn-36Pb-2Ag > Sn-Ag-Cu-Bi > Sn-Ag-Cu when tested with a profile with a peak temperature of 240°C, a dwell time above liquidus of 60 s for Pb-free alloys, and a peak temperature of 215°C, 60-s dwell for SnPb-Ag. Both forced-air convection, air reflow atmosphere, and vapor phase reflow were used in his study.45 The spread performance is rated with a scale of 1 to 5, with 5 being the best. Toyoda also studied spreading performance of several alloys, and observed the following spreading behavior in decreasing order: 63Sn-37Pb > Sn-AgCu-4.5Bi, Sn-Ag-Cu-7.5Bi > Sn-3.5Ag-0.75Cu > 99.25Sn-0.75Cu > 89Sn-8Zn-3Bi, as shown in Fig. 13.13.46 A wetting time study done by Baggio showed that there was no significant difference between 62Sn-36Pb-2Ag (at 235°C), Sn-3.8Ag-0.7Cu, and Sn-3.3Ag-3Bi1.1Cu (at 260°C) for metallized PCB surface finishes, including immersion Pd, immersion Sn, immersion Ag, and Ni/Au.45 However, 62Sn-36Pb-2Ag wetted slightly faster on organic solderability preservative (OSP) than Sn-Ag-Cu and SnAg-Cu-Bi.45 Lotosky’s results show that at 260°C when tested on oxidized copper, the wetting time increases in the following order: Sn-4Ag-0.5Cu (1.1 s) < 63Sn-37Pb (1.85 s) < Sn-2.5Ag-0.8Cu-0.5Sb (2.05 s) < 96.5Sn-2.5Ag-1Bi-0.5Cu (2.7 s).30 Toyoda studied the wetting time of meniscograph for Sn-Pb, Sn-Cu, Sn-Ag-Cu, and Sn-AgCu-Bi alloys, and observed that the wetting time increases in the following order: 63Sn-37Pb < Sn-Ag-Cu-2Bi ∼ Sn-Ag-Cu-1Bi < Sn-3.5Ag-0.75Cu < Sn-1Ag-0.5Cu < Sn-0.7Cu-0.3Ag < Sn-0.75Cu. The wetting time decreases with increasing temperature at a slightly different rate, as shown in Fig. 13.37.45 In Toyoda’s work, the Bi content between 1 and 2 percent seems to have no effect on the wetting performance, including spreading and wetting time, of Sn-Ag-Cu-Bi system. Both Sn-AgCu-1Bi and Sn-Ag-Cu-2Bi display a wetting behavior that is fairly comparable with 63Sn-37Pb.

13.43

PREVAILING LEAD-FREE ALLOYS

TABLE 13.9 Wetting Properties of 63Sn-37Pb, Sn-Ag-Cu, Sn-Ag-Cu-In, Sn-Ag-Cu-Bi, and Sn-Ag-Cu-Sb

Properties Contact angle (degree)

Wetting time (s)

63Sn37Pb 17 (Sn40Pb)

Sn-Ag-Cu

47

32

45

31

35

0.27 s at 235°C (Sn62) 0.20 s at 235°C (Sn62) 0.32 s at 235°C (Sn62) 0.20 s at 235°C (Sn62) 0.21 s at 235°C (Sn62) 0.24 s at 235°C (Sn62)

1.85 s Spread 4.55 (Sn62) 4.7 (Sn62) 4.4 (Sn62)

Sn-AgCu-Bi

21 (Sn4.70Ag1.70Cu)

22

0.36 s at 235°C (Sn62)

Sn-AgCu-In

0.28 s (Sn-3.8Ag0.7Cu) at 260°C 0.23 s (Sn-3.8Ag0.7Cu) at 260°C 0.25 s (Sn-3.8Ag0.7Cu) at 260°C 0.42 s (Sn-3.8Ag0.7Cu) at 260°C 0.26 s (Sn-3.8Ag0.7Cu) at 260°C 0.23 s (Sn-3.8Ag0.7Cu) at 260°C 0.27 s (Sn-3.8Ag0.7Cu) at 260°C

Sn-AgCu-Sb 44 (Sn3.8Ag0.7Cu0.5Sb)

Notes/References Ref. 18

Flux A611, 260– 280°C, Ref. 22 Flux A260HF, 260–280°C, Ref. 22 Flux B2508, 260–280°C, Ref. 22

1.1 s (Sn4Ag0.5Cu)

0.24 s (Sn3.3Ag-3Bi1.1Cu) at 260°C 0.26 s (Sn3.3Ag-3Bi1.1Cu) at 260°C 0.19 s (Sn3.3Ag-3Bi1.1Cu) at 260°C 0.44 s (Sn3.3Ag-3Bi1.1Cu) at 260°C 0.26 s (Sn3.3Ag-3Bi1.1Cu) at 260°C 0.25 s (Sn3.3Ag-3Bi1.1Cu) at 260°C 0.27 s (Sn3.3Ag-3Bi1.1Cu) at 260°C 2.75 s (96Sn2.5Ag-1Bi0.5Cu)

4.2 (Sn3.8Ag0.7Cu) 4.55 (Sn3.8Ag0.7Cu) 3.9 (Sn3.8Ag0.7Cu)

4 (Sn3.3Ag-3Bi1.1Cu) 4.6 (Sn3.3Ag-3Bi1.1Cu) 4.4 (Sn3.3Ag-3Bi1.1Cu)

Immersion Pd PCB, s, Ref. 45

Immersion Sn PCB, s, Ref. 45

Immersion Ag, PCB, s, Ref. 45

NiAu, PCB, s, Ref. 45

OSP 1, s, Ref. 45

OSP 2, s, Ref. 45

OSP 3, s, Ref. 45 2.05 s (Sn2.5Ag0.8Cu0.5Sb)

At 260°C, RF 800, oxidized Cu, Ref. 30

OSP 3*, Ref. 45 Immersion Ag*, Ref. 45

Immersion Pd*, Ref. 45

13.44

CHAPTER THIRTEEN

TABLE 13.9 Wetting Properties of 63Sn-37Pb, Sn-Ag-Cu, Sn-Ag-Cu-In, Sn-Ag-Cu-Bi, and Sn-Ag-Cu-Sb (Continued)

Properties

63Sn37Pb

5 (Sn62)

5 (Sn62) 4.7 (Sn62) 4.7 (Sn62)

5 (Sn62)

Sn-Ag-Cu 4.4 (Sn3.8Ag0.7Cu) 4.35 (Sn3.8Ag0.7Cu) 4.8 (Sn3.8Ag0.7Cu) 3.9 (Sn3.8Ag0.7Cu) 5 (Sn3.8Ag0.7Cu)

Sn-AgCu-In

Sn-AgCu-Bi 4.7 (Sn3.3Ag-3Bi1.1Cu) 4.45 (Sn3.3Ag-3Bi1.1Cu) 4.95 (Sn3.3Ag-3Bi1.1Cu) 4.65 (Sn3.3Ag-3Bi1.1Cu) 5 (Sn3.3Ag-3Bi1.1Cu)

Sn-AgCu-Sb

Notes/References

NiAu*, Ref. 45

OSP 3,† Ref. 45 Immersion Ag,† Ref. 45

Immersion Pd,† Ref. 45

NiAu,† Ref. 45

* Peak 240°C, dwell 60 s for Pb-free, 215°C, 60-s dwell for Sn-Pb-Ag, scale 1 to 5 (best), forced-air convection, air. † Peak 240°C, dwell 60 s for Pb-free, 215°C, 60-s dwell for Sn-Pb-Ag, scale 1 to 5 (best), 230°C bp VPR.

For Sn-Ag-Cu-In, no wetting information is available. For the Sn-Ag-Cu-Sb system, Seelig et al.11 studied the effect of Ag content on wetting performance when using rosin-based, mildly activated (RMA), no-clean, and organic acid (OA) fluxes. Results indicate that at around 2.5 percent Ag content, the Sn-Ag-Cu-Sb system exhibits the shortest wetting time for two out of three fluxes, as shown in Fig. 13.38.11

FIGURE 13.37 Wetting time of meniscograph for Sn-Pb, Sn-Cu, Sn-Ag-Cu, and Sn-Ag-CuBi alloys.

PREVAILING LEAD-FREE ALLOYS

13.45

FIGURE 13.38 Effect of Ag content on the wetting time of Sn-Ag-0.8Cu-0.5Sb system using RMA, no-clean, and OA fluxes.

13.4.4

RELIABILITY

The isothermal low-cycle fatigue (strain 0.2 percent, 0.1 Hz, R = 0.8, 300 K) performance of several Sn-Ag-Cu and Sn-Ag-Cu-X alloys was studied by Hwang,4 with results shown in Table 13.5. The number of cycles to failure at 300 K (50 percent load drop, 0.2 percent strain range) decreases in the following order: 88.5Sn-3Ag-0.5Cu-8In (19,501) > 95.4Sn-3.1Ag-1.5Cu (8,936) > 96.2Sn-2.5Ag-0.8Cu-0.5Sb (8,751) > 94.5Sn0.5Ag-2Cu-3Sb (7,120) > 93.3Sn-3.1Ag-3.1Bi-0.5Cu (6,522) > 63Sn-37Pb (3,650). The data above suggest that Sn-Ag-Cu-X is a very viable family as lead-free alternatives. Some temperature cycling and heat treatment reliability data for Sn-Ag-Cu, SnAg-Cu-In, Sn-Ag-Cu-Bi, Sn-Ag-Cu-Sb, and 63Sn-37Pb or 62Sn-36Pb-2Ag are shown in Table 13.10. Since all of the viable Pb-free alternatives comprise a high Sn content, the possibility of a high IMC formation rate and its impact on reliability are a concern. Grusd reported that the Cu dissolution rate during soldering increases in the following order: 60Sn-40Pb < Sn-Ag-1Cu < Sn-2.5Ag-0.8Cu-0.5Sb < Sn-Ag-Cu-Bi < Sn-Ag0.5Cu, and thus validates this concern.24 Figure 13.39 shows examples of intermetallic formations between Sn-Ag-Cu and copper substrate.73 Although the intermetallics thickness may be thicker than the Sn-Pb system, it does not adversely affect the solder joint reliability. Feldmann and Reichenberger studied the effect of 160°C storage aging time on the shear strength of chip resistor 1206.66 Results indicate that while 62Sn-36Pb-2Ag decreased in shear strength for about 30 percent after 1000 h of aging at 160°C, the Pb-free alternatives Sn-3.8Ag-0.7Cu and Sn-3.3Ag-3Bi-1.1Cu reduced only 12 and 4 percent, respectively, under the same test condition. In all of the results reported in Table 13.10, the Sn-Ag-Cu system is always equal or better than 63Sn-37Pb. This widely acceptable reliability performance of Sn-AgCu system, regardless of applications, strongly validates the acceptability of this system as a substitute for eutectic Sn-Pb. Figures 13.14 through 13.17 show the Weibull plots for Sn-Ag-Cu versus Sn-Pb in the BGA applications over several temperature cycling test conditions, thus demonstrating the superiority of the Sn-Ag-Cu system.

TABLE 13.10 Accelerated Life Testing Performance of Sn-Ag-Cu, Sn-Ag-Cu-In, Sn-Ag-Cu-Bi, Sn-Ag-Cu-Sb, and Sn-Pb—The Performance May Also Be Ranked in Descending Order for Some Works, with 1st Being the Best Test condition

Applications

Sn-Pb (or Sn62)

Sn-Ag-Cu

Sn-Ag-Cu-In

Sn-Ag-Cu-Bi

Sn-Ag-Cu-Sb

Notes/ References

13.46

0–100°C

General

Good (on NiP/Au)

Comparable with Sn63 (Sn-4Ag0.5Cu on TiW/Cu UBM)

Ref. 14

−40°C, 15 min/+125°C, 15 min, shear strength after 2000 cycles

TQFP64, CR1206

Good

Comparable with Sn62

Comparable with Sn62

Ref. 66

160°C heat treatment, shear strength (N): 0/500/1000 h

CR1206, 100Sn component finish to OSP board finish

68/55/48 (Sn62)

68/62/60 (Sn-3.8Ag0.7Cu)

80/83/77 (Sn-3.3Ag3Bi-1.1Cu)

Ref. 66

Single-lead shear strength (N)

TQFP64, Sn-Pb vs. Ni-Pd component finish to OSP board finish

7/6.9 (Sn62)

8.8/8 (Sn3.8Ag0.7Cu)

6.5/10.3 (Sn-3.3Ag3Bi-1.1Cu)

Ref. 66

−55/+125°C

Cylindrical resistor, crack vs. cycles

1st (Sn3.5Ag0.75Cu)

3rd (Sn-Ag-Cu7.5Bi)

Ref. 46

−40/80°C, crack

3rd

1st (Sn3.5Ag0.75Cu)

1st (Sn-Ag-Cu1In)

1st (Sn-Ag-Cu7.5Bi)

Ref. 46

13.47

−40/125°C, 42-min cycle time

625 I/O CBGA, 32 × 32 × 0.8 mm, same alloy for ball and paste

3rd, close to 2nd

2nd (Sn3.8Ag0.7Cu), close to Sn-Ag-Bi

Ref. 49

−40/125°C, 240-min cycle time

625 I/O CBGA, 32 × 32 × 0.8 mm, same alloy for ball and paste

2nd

1st (Sn3.8Ag0.7Cu)

Ref. 49

0/100°C, 30min cycle time

625 I/O CBGA, 32 × 32 × 0.8 mm, same alloy for ball and paste

2nd

1st (Sn3.8Ag0.7Cu), same as Sn-Ag-Bi, better than Sn63

Ref. 49

0/100°C, 60min cycle time

625 I/O CBGA, 32 × 32 × 0.8 mm, same alloy for ball and paste

2nd

1st (Sn3.8Ag0.7Cu), same as Sn-Ag-Bi, better than Sn63

Ref. 49

0/100°C, 240-min cycle time

625 I/O CBGA, 32 × 32 × 0.8 mm, same alloy for ball and paste

2nd

1st (Sn3.8Ag0.7Cu), better than Sn63

Ref. 49

TABLE 13.10 Accelerated Life Testing Performance of Sn-Ag-Cu, Sn-Ag-Cu-In, Sn-Ag-Cu-Bi, Sn-Ag-Cu-Sb, and Sn-Pb—The Performance May Also Be Ranked in Descending Order for Some Works, with 1st Being the Best (Continued) Test condition

Applications

Sn-Pb (or Sn62)

Sn-Ag-Cu

13.48

−40/60°C, 30-min cycle

625 I/O CBGA, 32 × 32 × 0.8 mm, same alloy for ball and paste

2nd, close to Sn-Ag-Cu

1st

−40/+125°C

fleXBGA

7th ∼ 6th

3rd (Sn4Ag-1Cu); 5th (Sn4Ag-0.5Cu)

Flip chip

Good

Comparable with Sn63

Flip chip of nonunderfilled systems

Flip chip

Sn-Ag-Cu-In

Sn-Ag-Cu-Sb

6th (Sn3.4Ag-1Cu3.3Bi) ∼ 7th

2nd (Sn2.5Ag0.8Cu0.5Sb)

Comparable with Sn63 (Sn-3.8Ag0.7Cu) Good (Sn3.5Ag0.75Cu)

General

Best

Ref. 51

Ref. 14 2nd, 96.2Sn2.5Ag0.8Cu-1Sb is about 80% of Sn63-Pb37

General

Notes/ References Ref. 49

1st

Good

Sn-Ag-Cu-Bi

Ref. 51

Ref. 52

Good (Sn3Ag-1In0.7Cu)

Ref. 5

Refs. 54, 55

FIGURE 13.39 SEM migrographs (2500×) using backscattered electron imaging to show the intermetallic layer between copper and Sn-3.6Ag-1Cu (top), Sn-3Ag-0.5Cu (middle), and Sn-4Ag0.5Cu (bottom).

13.49

13.50

CHAPTER THIRTEEN

Among the viable Sn-Ag-Cu compositions, Sn-3.8Ag-0.7Cu and Sn-4Ag-0.5Cu appear to be more commonly accepted. Sn-Ag-Cu-In is much less studied than Sn-Ag-Cu. Tanaka et al. studied Pb-free technology solder for mobile equipment at NEC, and concluded that Sn-3.1Ag-1In0.7Cu, which is similar to Sn-3.5Ag-0.75Cu and Sn-3.5Ag-0.5Bi-3In, is equal to 63Sn37Pb in the fatigue test, but is inferior to Sn-Ag-Bi-1.1Cu-Ge and Sn-Ag-X.5 However, the latter two alloys are unacceptable for the Charpy Impact Test. All five Pb-free alloys are excellent in the creep rupture test when compared with 63Sn37Pb. Overall,Tanaka et al. concluded that Sn-3Ag-1In-0.7Cu is equal to eutectic SnPb, is poorer than both Sn-3.5Ag-0.75Cu and Sn-3.5Ag-0.5Bi-3In, but is better than Sn-Ag-Bi-1.1Cu-Ge and Sn-Ag-X. Toyoda investigated the temperature cycling performance of several Pb-free solders.46 The cycling condition is −40 to +80°C, with a 30-min temperature cycle, using a wave-soldered nylon connector in a paper phenol substrate. The failure is monitored by observing externally the crack development. Results indicate that the fatigue resistance increases in the following order: 63Sn-37Pb < Sn-3.5Ag < Sn-AgCu-7.5Bi, Sn-Ag-Cu-1In, Sn-3.5Ag-0.75Cu up to 1000 cycles, as shown in Fig. 13.40.46 Hwang also studied the isothermal low-cycle fatigue behavior of Pb-free alloys at 300 K, 0.2 percent strain, 0.1 Hz, and R = 0.8.4 For the Sn-Ag-Cu-In system, she reported that the optimum In content for low-cycle fatigue life performance is 8 percent for both Sn-In-4.1Ag-0.5Cu and Sn-In-3.1Ag-0.5Cu systems, as shown in Fig. 13.41.4 Hwang also studied the optimum Ag content for Sn-Ag-In-0.5Cu, with In maintained at 4 and 8 percent. Results shown in Fig. 13.42 indicate that the Ag content may be better to be higher than 3 percent.4 In the fatigue life test, 88.5Sn-3Ag-0.5Cu-8In (19,501 in Nf value) is the best among all the rest alloys, as shown in Table 13.5. Sn-Ag-Cu-Bi is outstanding in creep resistance and wetting, as indicated in Figs. 13.34 and 13.37. However, the presence of the Bi ingredient brings up concerns on

FIGURE 13.40 Temperature cycling performance of 63Sn-37Pb, Sn-Ag-Cu-7.5Bi, Sn-Ag-Cu-1In, Sn-3.5Ag-0.75Cu, and Sn-3.5Ag (test conditions: −40°/+80°C at 30-min cycle time).

PREVAILING LEAD-FREE ALLOYS

13.51

FIGURE 13.41 Fatigue life Nf versus In content for the Sn-Ag-Cu-In system at both Sn-In-4.1Ag-0.5Cu and Sn-In-3.1Ag-0.5Cu.

FIGURE 13.42 Fatigue life Nf as a function of Ag content for Sn-Ag-Cu-In system at both Sn-Ag0.5Cu-8In and Sn-Ag-0.5Cu-4In.

13.52

CHAPTER THIRTEEN

the sensitivity toward lead contamination. Feldmann and Reichenberger evaluated the solder joint shear strength of TQFP64 with Sn-Pb or Ni-Pd component finishes soldered onto PCB with OSP board finish using 62Sn-36Pb-2Ag, Sn-3.8Ag-0.7Cu, and Sn-3.3Ag-3Bi-0.7Cu, with the results shown in Fig. 13.43.66 The joint strength of 62Sn-36Pb-2Ag and Sn-3.8Ag-0.7Cu is insensitive to the component finish type. However, in the case of Sn-3.3Ag-3Bi-1.1Cu, solder joints with the Sn-Pb component lead surface finish are much lower than joints with Ni-Pd finish due to the formation of a ternary eutectic low melting phase, 52Bi-30Pb-18Sn, as will be discussed in Chap. 16. The temperature cycling performance of Sn-Ag-Cu-Bi was studied by Toyoda.46 At test conditions of −40°/+80°C at a 30-min cycle time, Sn-Ag-Cu-7.5Bi outperforms 63Sn-37Pb and Sn-3.5Ag and, similar to Sn-Ag-Cu-1In and Sn-3.5Ag-0.75Cu, exhibits no failure up to at least 1000 cycles, as shown in Fig. 13.40. However, at test conditions of −55/+125°C and a cycle time of 30 min, the temperature cycling performance of the solder joints of a cylindrical chip resistor using Sn-Ag-Cu-7.5Bi is slightly poorer than 62Sn-36Pb-2Ag and is considerably poorer than Sn-3.5Ag0.75Cu, as shown in Fig. 13.44.46 In Syed’s work as part of the National Center for Manufacturing Sciences (NCMS) project, fatigue life of the fleXBGA package [144 input/output (I/O), 18mil ball size, 0.8-mm ball pitch) was determined at the following conditions: −40/+125°C, 15-min ramp and dwell, 1 cycle/h, single-zone cycling chamber for a series of Pb-free solders. The results are shown in Table 13.11, indicating that Sn-AgCu-Bi is comparable with or slightly better than control eutectic Sn-Pb solder, poorer than Sn-Ag-Cu, Sn-Ag-Cu-Sb, Sn-Ag-Cu-Sb-Bi, Sn-Ag-In, but better than Sn-Ag.50 The results are roughly consistent with the findings of Toyoda46 and Feldmann and Reichenberger.66 Sn-Ag-Cu-Sb is one of the alloy systems that received a relatively good evaluation in the early stage of Pb-free soldering development. In Syed’s results, Sn-2.5Ag0.8Cu-0.5Sb is leading in fatigue life evaluation (see Table 13.11). In Elenius and Yeh’s work, 96.2Sn-2.5Ag-0.8Cu-1Sb is about 80 percent of Sn63-Pb37 for unfilled

FIGURE 13.43 Single lead shear strength of TQFP64 with Sn-Pb or NiPd surface finishes. The component is soldered onto PCB with an OSP surface finish with 62Sn-36Pb-2Ag, Sn-3.8Ag-0.7Cu, and Sn-3.3Ag-3Bi-0.7Cu.

PREVAILING LEAD-FREE ALLOYS

13.53

FIGURE 13.44 Temperature cycling performance of 62Sn-36Pb-2Ag, Sn-Ag-Cu-7.5Bi, and Sn3.5Ag0.75-Cu (test conditions: −55°C/+125°C and cycle time 30 min).

flip chip assembly.51 Seelig and Suraski reported that the fatigue life of 96.1Sn2.6Ag-0.8Cu-0.5Sb is comparable with or better than 96.5Sn-3.5Ag, as shown in Table 13.12,11 according to ASTME 606, 1-Hz triangular waveform oscillated between 0.15 and −0.15 percent strain. The passing mark was set at 10,000 cycles. The reliability potential of Sn-Ag-Cu-Sb was also investigated by determining the intermetallics growth rate at 125°C on several commonly used base metals, including copper, brass, nickel, and alloy 42. Results indicate that 96.1Sn-2.6Ag0.8Cu-0.5Sb (CASTIN) is most stable when compared with 60Sn-40Pb, 96.5Sn3.5Ag, and 99.3Sn-0.7Cu, as shown in Fig. 13.45.11 The advantage in slow intermetallics growth rate of Sn-Ag-Cu-Sb is particularly profound on copper. TABLE 13.11 Relative Comparison of Fatigue Life of Pb-Free Alloys* Relative fatigue life By first failure

By mean life

A1 (Sn-Ag)

Alloy

0.69

0.94

A11 (Sn-Ag-Cu)

1.27

1.28

A14 (Sn-Ag-Cu)

1.14

1.26

A21 (Sn-Ag-Cu-Sb)

1.29

1.33

A32 (Sn-Ag-Cu-Sb-Bi)

1.17

1.31

A62 (Sn-Ag-Cu-Bi)

1.01

1.12

A66 (Sn-Ag-In)

1.29

1.25

B63 (Sn-Pb)

1.00

1.00

* At the following conditions: −40/+125°C, 15-min ramp and dwell, 1 cycle/h, single-zone cycling chamber, fleXBGA package, 144 I/O, 18-mil ball size, 0.8-mm ball pitch.

13.54

CHAPTER THIRTEEN

TABLE 13.12 Fatigue Life of 96.1Sn-2.6Ag-0.8Cu-0.5Sb and 96.5Sn-3.5Ag* 96.1Sn-2.6Ag-0.8Cu-0.5Sb

96.5Sn-3.5Ag

11,194

10,003

26,921

6,267

24,527

11,329

* Test conditions: ASTME 606, 1-Hz triangular waveform oscillated between 0.15 and −0.15 percent strain. The passing mark was set at 10,000 cycles.

13.5 13.5.1

Sn-Zn AND Sn-Zn-Bi PHYSICAL PROPERTIES

91Sn-9Zn is attractive mainly due to its relatively low melting temperature. However, the high activity of Zn results in a great challenge in solder paste reflow applications. Bi is added accordingly in order to reduce the corrosivity of Zn under humid conditions and to reduce the melting temperature further. Table 13.13 shows the physical properties of 91Sn-9Zn, 89Sn-8Zn-3Bi, and eutectic Sn-Pb, although information on Sn-Zn-Bi is very scarce. In general, the physical properties of the Sn-Zn alloy are dictated by the property of Sn due to high Sn content. Sn-Zn exhibits a higher surface tension than eutectic Sn-Pb, as predicted by Fig. 12.2, hence inferring a poorer wetting behavior. Addition of low-surface-energy Bi is expected to lower the surface tension of the Sn-Zn system (see Fig. 12.2), thus promising a better wetting.

FIGURE 13.45 Rate of intermetallic growth of 60Sn-40Pb, 96.5Sn-3.5Ag, 99.3Sn-0.7Cu, and 96.1Sn-2.6Ag-0.8Cu-0.5Sb (CASTIN) at 125°C on copper, brass, nickel, and alloy 42.

13.55

PREVAILING LEAD-FREE ALLOYS

TABLE 13.13 Physical and Mechanical Properties of 91Sn-9Zn and 89Sn-8An-3Bi

Property Melting temperature (°C) Density (g/cm3) Electrical resistivity (µΩ-cm)

63Sn-37Pb

91Sn-9Zn

183

199

8.4

7.27

17 15 10–15

14.5 14.6 Thermal conductivity [W/(m·K)] Specific heat [J/(g·K)] CTE (ppm/K)

Hardness

Surface tension (mN m−1)

13.5.2

50.9 61 0.167

0.239

16.8 24 (−70°C, 20°C, 140°C) 21 25 18.74

23.9

12.8

21.3

17

21.5

417 (air), 464 (N2) at 233°C

89Sn-8Zn-3Bi 187–197

Notes/ References Ref. 6 Ref. 1 Ref. 63 Ref. 1 Ref. 3 Ref. 2 Ref. 2 Ref. 1 Ref. 1 Ref. 6 Ref. 15 Ref. 16 Ref. 2 Ref. 8

518 (air), 487 (N2) at 249°C

HV; kg/mm2, Ref. 6 Brinel hardness, Ref. 1 Ref. 3

MECHANICAL PROPERTIES

The mechanical properties of 63Sn-37Pb, 91Sn-9Zn, and 89Sn-8Zn-3Bi are shown in Table 13.14. In general, the Sn-Zn alloy is higher in yield strength, equal or higher in tensile strength, equal in shear strength, and equal or lower in elongation than eutectic Sn-Pb. On the other hand, Sn-Zn-Bi is higher in creep resistance than Sn-Pb. The effect of Bi addition on tensile properties of Sn-Zn results in embrittlement of the alloy, and is fairly similar to that of Sn-Ag-Cu. Figure 13.36 shows that at 8 percent Bi content, the tensile strength of the Sn-Zn-Bi system is at the maximum and is about twice that of Sn-Zn, while the elongation is at the minimum and is about one-sixth of that of the Sn-Zn.

13.5.3

WETTING PROPERTIES

Zn-containing alloys are notorious in terms of wetting performance, mostly due to the susceptibility of Zn to oxidation and the high surface energy of the systems. The latter results in difficulty in wave soldering bath maintenance, as reported by Baggio.45 Toyoda studied the solder spread of Pb-free alloys, and concluded that 89Sn-8Zn-3Bi is the lowest in spread when compared with Sn-Pb, Sn-Cu, Sn-Ag-Cu, and Sn-Ag-Cu-Bi,

13.56

CHAPTER THIRTEEN

TABLE 13.14 Mechanical Properties of 63Sn-37Pb, 91Sn-9Zn, and 89Sn-8Zn-3Bi Properties

63Sn-37Pb

91Sn-9Zn

Ultimate tensile strength (MPa)

45.1 30.6 51.7

45.4 53.1 54.7

89Sn-8Zn-3Bi

Ref. 6 Ref. 13 Ref. 1

Yield strength, A (0.2%, MPa)

27.2

51.6

Ref. 13

Shear strength (MPa)

48.4

48.8

Ref. 6

Elongation (%)

35.5 48 35

40 27

Ref. 6 Ref. 13 Ref. 2 Ref. 1

Creep (time to break, h)

1

33 94

Notes/References

Ref. 46

as shown in Fig. 13.13.46 In his results, it is also interesting to note that, opposite to the behavior of other alloys, the spread of Sn-Zn-Bi decreases with increasing temperature. Presumably this can be attributed to the oxidation of Zn during testing. Huang and Lee studied the reflow spreading performance of Pb-free solders, with results shown in Fig. 13.46.29 In this work, each alloy was evaluated in solder paste form using 10 different flux chemistries, with the average performance expressed as a wetting index, where 10 and 0 represent full wetting and no wetting, respectively. The reflow was conducted at two different reflow profiles, one with a peak temperature of 15°C above the liquidus, and another one with a peak temperature of 30°C above liquidus temperature. The spreading of Sn-Zn-Bi was extremely poor, with the solder pastes barely reflowed in many cases. The poor wetting performance of Sn-Zn-Bi is presumably attributable to the highly oxidative nature of Zn. Loomans et al. studied the contact angle of binary eutectic alloys using rosin-IPA flux, and reported the following results: Sn-Bi, 40° (166°C); Sn-Zn, 60° (225°C); and Sn-Ag, 45° (250°C).32 These angles were little affected by a number of 1 percent ternary additions to the solders. The significantly larger contact angle of Sn-Zn than that of Sn-Bi and Sn-Ag reflects the greater difficulty in wetting, and is consistent with results discussed earlier. Suganuma studied the microstructure of lead-free solders and of their interfaces with copper. He reported that the Sn-Zn alloys only form different Cu-Zn IMCs (beta-Cu-Zn and gamma-Cu5Zn8) at the interface. Even with the small amount of Zn added to Sn, Zn segregates to the interface to form the Cu-Zn IMC with Sn. However, most other Sn alloys, including pure Sn, Sn-Ag, Sn-Bi, or their ternary alloys, form two IMCs at the interfaces with Cu [i.e., Cu6Sn5 (15 µm) and Cu3Sn (5 µm).The former is much thicker than the latter and the interface integrity is strongly influenced by the presence of the Cu6Sn5 layer.37 Sn-Zn-(Bi) is not stable with most fluxes when used as a solder paste, mainly due to the high reactivity of Zn. However, few solder paste products have been developed, including no-clean applications, for this alloy system.6

13.5.4

RELIABILITY

The reliability of Sn-Zn-Bi system was studied by determining the shear strength of solder joints as a function of storage time at 125°C, as shown in Fig. 13.47.6 The sur-

PREVAILING LEAD-FREE ALLOYS

13.57

FIGURE 13.46 Solder paste wetting (spreading) performance for Pb-free and 63Sn37Pb solder pastes when reflowed at a peak temperature 15 and 30°C above the liquidus temperature of alloys. An index value of 10 represents full wetting, and 0 represents no wetting.

face finishes for PCBs tested included Au-Ni and preflux. Results indicate that both Sn-Zn-Bi and Sn-Pb maintained a steady shear strength with storage time up to at least 3000 h. Ni-Au resulted in a slightly higher shear strength than preflux, and SnZn-Bi joints appear to be slightly stronger than those of Sn-Pb. However, in another test where the solder joints were pretreated with thermal cycling, the shear strength started to decline after 2000 cycles for Sn-Zn-Bi, and from the very beginning of the Sn-Pb system, as shown in Fig. 13.48.6 In the case of Sn-Zn-Bi, no difference in strength and reliability can be discerned between Ni-Au and preflux finishes. While Showa Denko’s results indicate a lack of sensitivity of Sn-Zn-Bi toward heat treatment, Suganuma reported that the tensile strength (MPa) of Cu/solder/Cu joints for Sn-Zn did deteriorate with heat treatment. Thus, the tensile strength for as-soldered/after-exposure at 150°C for 100 h can be shown as follows: Sn-8Zn (Au-Pd-Ni), 73/54; Sn-8Zn, 53/15; Sn-3.5Ag, 52/37; Sn-7.5Bi-2Ag-0.5Cu, 44/35; and Sn-37Pb, 28/18.37 The deterioration extent for Sn-Zn on Cu without Au-Pd-Ni surface finish is greater than the rest systems studied, suggesting a change in Sn-Zn solder joint microstructure may have occurred in the absence of Au-Pd-Ni. Indeed, this may very well be the case. In the absence of a Ni diffusion barrier for copper, Zn and Cu form Cu-Zn IMCs (beta-Cu-Zn and gamma-Cu5Zn8) at the interface, as reported by Suganuma for the Sn-Zn system.37 A similar Cu-Zn IMC is also observed in the Sn-Zn-Bi system on Cu, as shown in Fig. 13.49.6 The development of Cu-Zn IMC can be prevented by predepositing a Ni barrier on top of Cu, as shown in Fig. 13.50.6

FIGURE 13.47 Shear strength of 89Sn-8Zn-3Bi and Sn-Pb soldered onto Au-Ni or preflux-coated copper at 125°C storage temperature.

FIGURE 13.48 Shear strength of 89Sn-8Zn-3Bi and Sn-Pb soldered onto Au-Ni or preflux-coated copper as a function of thermal cycle number.

FIGURE 13.49 Effect of thermal cycle test on microstructure of 89Sn-8Zn-3Bi (electron probe microanalysis view).

13.58

PREVAILING LEAD-FREE ALLOYS

13.59

FIGURE 13.50 Effect of thermal cycle test on microstructure of 89Sn-8Zn-3Bi (electron probe microanalysis view) in the presence of a Ni barrier layer.

13.6

SUMMARY

Sn-Ag-Cu is the most attractive system, mainly due to overall superior reliability and acceptable soldering property and cost. Addition of In, Bi, or Sb introduces improved performance with a trade-off. Sn-Ag-Bi-X is outstanding on soldering, but sensitive to Pb-contamination and fillet lift. Reliability of Sn-Ag can range from being poor to good, and is highly dependent on applications. Its soldering performance is marginally acceptable. Sn-Cu is poor in mechanical strength, and its reliability can range from poor to good, too, depending on the applications. Sn-Zn-Bi is attractive mainly due to the low melting temperature. The high activity of Zn prohibits this system to be used in high-end applications.

REFERENCES 1. Indium Corporation of America, data sheet. 2. Lee, N.-C., J. A. Slattery, J. R. Sovinsky, I. Artaki, and P. T. Vianco, “A Drop-in Lead-Free Solder Replacement,” Proceedings of the NEPCON West Conference, Anaheim, CA, February 28–March 2, 1995. 3. Glazer, J., “Microstructure and Mechanical Properties of Pb-free Solder Alloys for LowCost Electronic Assembly: A Review,” J. Electronic Materials, 23(8):693, 1994. 4. Hwang, J. S., “Solder Materials,” SMT, 15(7), July 2001. 5. Tanaka, Y., J. Takahashi, and K. Kawashima, “Lead Free Soldering Technology for Mobile Equipment,” Proceedings of IMAPS, pp. 336–341, Boston, September 20–22, 2000. 6. Denko, S., “Development of Sn-Zn Solder Paste of High Reliability,” Proceedings of IPCWorks ’99, Minneapolis, MN, October 27, 1999. 7. Anderson, I. E., Ö. Ünal, T. E. Bloomer, and J. C. Foley, “Effects of Transition Metal Alloying on Microstructural Stability and Mechanical Properties of Tin-Silver-Copper Solder Alloys,” Proc. Third Pacific Rim International Conference on Advanced Materials and Processing (PRICM 3), The Minerals, Metals, and Materials Society, Honolulu, HI, July 12–16, 1998. 8. IPC Leadfree website: www.leadfree.org, “NIST Database for Solder Properties with Emphasis on New Lead-free Solders.” 9. Solder Data Sheet, Welco Castings, 2 Hillyard Street, Hamilton, ON, Canada. 10. Gray, D. E., ed., American Institute of Physics Handbook, pp. 2–61 ff., McGraw-Hill, New York, 1957. (Note: Original units were in dyn/cm2; 10 dyn/cm2 = 1 N/m2 = 1 Pa.)

13.60

CHAPTER THIRTEEN

11. Seelig, K., and D. Suraski, “The Status of Lead-Free Solder Alloys,” Proc. 50th IEEE 2000 Electronic Components and Technology Conference, Las Vegas, NV, May 21–24, 2000. 12. Sigelko, J. D., and K. N. Subramanian, “Overview of Lead-Free Solders,” Adv. Mat. & Proc., 47–48, March 2000. 13. Technical Reports for the Lead-Free Solder Project, Properties Reports, “Room Temperature Tensile Properties of Lead-Free Solder Alloys,” Lead-Free Solder Project CD-ROM, National Center for Manufacturing Sciences (NCMS), Ann Arbor, MI, 1998. 14. Maestrelli, L. M., and R. C. Pfahl, “Technology for Environmentally Preferred Products,” IMAPS-Brazil, São Paulo, Brazil, August 1–3, 2001. 15. Wong, T., and A. H. Matsunaga, “Ceramic Ball Grid Array Solder Joint Thermal Fatigue Life Enhancement,” Proceedings: NEPCON West Conference, Anaheim, CA, February 28–March 2, 1995. 16. Lau, J., C. Chang, R. Lee, T.-Y. Chen, D. Cheng, T. J. Tseng, and D. Lin, “Design and Manufacturing of Micro Via-in-Pad Substrates for Solder Bumped Flip Chip Applications,” Journal of Electronics Manufacturing, 10(1):79–87, 2000. 17. McCabe, R. J., and M. E. Fine, “Athermal and Thermally Activated Plastic Flow in Low Melting Temperature Solders at Small Stresses,” Scripta Materialia, 39(2):189, 1998. 18. Anderson, I. E., T. E. Bloomer, R. L. Terpstra, J. C. Foley, B. A. Cook, and J. Harringa, “Development of Eutectic and Near-Eutectic Tin-Silver-Copper Solder Alloys for LeadFree Electronic Assemblies,” IPCWorks ’99: An International Summit on Lead-Free Electronics Assemblies, Minneapolis, MN, October 25–28, 1999. 19. International Tin Research Institute, publ. no. 656, through Hampshire, W. B., “The Search for Lead-Free Solders,” Proc. Surface Mount International Conference, p. 729, San Jose, CA, September 1992. 20. Hernandez, C. L., P. T. Vianco, and J. A. Rejent, “Effect of Interface Microstructure on the Mechanical Properties of Pb-Free Hybrid Microcircuit Solder Joints,” IPC/SMTA Electronics Assembly Expo, p. S19-2-1, 1998. 21. Solder Data Sheet, Welco Castings, 2 Hillyard Street, Hamilton, ON, Canada. 22. Glazer, J., “Metallurgy of Low Temperature Pb-Free Solders for Electronic Assembly,” International Materials Reviews, 40(2):65–93, 1995. 23. Frear, D., and E. Bradley, Motorola, cited by A. Woosley, G. Swan, T. S. Chong, L. Matsushita, T. Koschmieder, and K. Simmons, “Development of Lead (Pb) and Halogen Free Peripheral Leaded and PBGA Components to Meet MSL3 260C Peak Reflow,” Electronics Goes Green, Fraunhofer Institute, Berlin, September 13, 2000. 24. Grusd, A., “Connecting to Lead-Free Solders,” Circuit Assembly, 10(8):32–38, August 1999. 25. Hwang, J. S., and R. M. Vargas, “Soldering and Surf,” Mount Technology, 5:38–45, 1990. 26. Guo, Z.,A. F. Sprecher, Jr., H. Conrad, and M. Kim, Proceedings of Materials Developments in Microelectronic Packaging: Performance and Reliability Conference, pp. 155–162, ASM International, Montreal, PQ, Canada, 19–22 August 1991. 27. Villain, J., O. Bruller, and T. Qasim, “Creep Behavior of the Lead-Free Solder Alloy Sn3.5Ag at High Homologues Temperatures using Laser Extensometry with Miniprobes,” Proceedings of SMT/ES&S/Hybrid 2000, Nuremberg, Germany, June 27–29, 2000. 28. Hunt, C., and D. Lea, “Solderability of Lead-Free Alloys,” Proceedings of Apex 2000, Long Beach, CA, March 2000. 29. Huang, B., and N.-C. Lee, “Prospect of Lead Free Alternatives for Reflow Soldering,” IMAPS, Chicago, October 1999. 30. Lotosky, P., “Lead-Free Update,” Tutorial at IMAPS-Brazil, São Paulo, Brazil, August 1–3, 2001. 31. Melton, C., “Reflow Soldering Evaluation of Lead Free Solder Alloys,” Proc. of IEEE 43rd Electronic Components and Technology Conference (ECTC’93), pp. 1008–1011, Orlando, FL, June 1993.

PREVAILING LEAD-FREE ALLOYS

13.61

32. Loomans, M. E., S. Vaynman, G. Ghosh, and M. E. Fine, “Investigation of Multi-component Lead-Free Solders,” J. Electronic Materials, 23(8):741–746, August 1994. 33. Vianco, P. T., F. M. Hosking, and J. A. Rejent, Proceedings: NEPCON West Conference, pp. 1730–1738, Anaheim, CA, Cahners Exposition Group, Des Plaines, IL, 1992. 34. Vianco, P. T., F. M. Hosking, and D. R. Frear, “Lead-Free Solders for Electronics Applications—Wetting Analysis,” Conference: Materials Developments in Microelectronic Packaging: Performance and Reliability, pp. 373–380, Montreal, PQ, Canada, August 1991. 35. Melton, C., A. Skipor, and J. Thome, Proceedings: NEPCON West Conference, pp. 1489–1494, Anaheim, CA, Cahners Exposition Group, Des Plaines, IL, February 1993. 36. Hernandez, C. L., P. T. Vianco, and J. A. Rejent, “Effect of Interface Microstructure on the Mechanical Properties of Pb-Free Hybrid Microcircuit Solder Joints,” Proc. of SMTA/IPC Electronics Assembly Expo, p. S19-2, Providence, RI, October 24–29, 1998. 37. Suganuma, K., “Microstructures of Lead-Free Solders and of Their Interfaces with Cu,” Proc. of the Third International Symposium of Electronic Packaging Technology, pp. 198–203, Beijing, China, August 17–21, 1998. 38. Vianco, P. T., and D. R. Frearr, “Issues in the Replacement of Lead-Bearing Solders,” JOM, 14–19, July 1993. 39. Humpston, G., and D. M. Jacobson, Principles of Soldering and Brazing, ASM International, Materials Park, OH, 1993. 40. Satoh, R., in Thermal Stress and Strain in Microelectronics Packaging, Lau, J. H., ed., Van Norstand Reinhold, New York, pp. 500–531, 1993. 41. Bader, W. G., Weld. Res. Suppl., 48:551s–557s, 1969. 42. Heinzel, H., and K. E. Saeger, Gold Bull., 9(1):7–11, 1976. 43. London, J., and D. W. Ashall, Brazing Soldering, 11:49–55, Autumn 1986. 44. Siow, K. S., and M. Manoharan, “Combined Tensile-Shear Fracture Toughness of a LeadTin and a Tin-Silver Solder,” Proc. of SMTA/IPC Electronics Assembly Expo, p. S19-3, Providence, RI, October 24–29, 1998. 45. Baggio, T., “The Panasonic Mini Disk Player—Turning a New Leaf in a Lead-Free Market,” Proceedings of IPCWorks ’99, Minneapolis, MN, October 27, 1999. 46. Toyoda, Y., “The Latest Trends in Lead-Free Soldering,” Proc. of International Symposium on Electronic Packaging Technology, pp. 434–438, Beijing, China, August 8–11, 2001. 47. Vianco, P.T., J.A. Rejent, I.Artaki, and U. Ray,“An Evaluation of Prototype Circuit Boards Assembled with a Sn-Ag-Bi solder,” Proceedings of IPCWorks ’99, Minneapolis, MN, October 22, 1999. 48. Mawer, A., and K. Levis, “Automotive PBGA Assembly and Board-Level Reliability with Lead-Free Versus Lead-Tin Interconnect,” SMTA International, Chicago, IL, September 24–28, 2000. 49. Bartelo, J. C., “The Effect of Temperature Range During Thermal Cycling on the Thermomechanical Fatigue Behavior of Selected Pb-Free Solders,” APEX, Long Beach, CA, 2001. 50. Syed, A., “Reliability of Pb Free Solder Joints for Area Array Packages,” APEX, San Diego, CA, January 18, 2001. 51. Elenius, P., and S. Yeh, “Lead Free Solder for Flip Chip and Chip Scale Packaging (CSP) Applications,” Proceedings of IPCWorks ’99, pp. S-03-2-1–S-03-2-6, Minneapolis, MN, October 23–28, 1999. 52. Frear, D. R., J. W. Jan, J. K. Lin, and C. Zhang, “Pb-Free Solders for Flip-Chip Interconnects,” JOM, 53(6):28–32, 2001. 53. Lauer, T., and S. Wege, “Behaviour of Lead-Free Solder Joints under Thermal and Mechanical,” Proceedings of SMT/ES&S/Hybrid 2000, Nuremberg, Germany, June 27–29, 2000. 54. Bradley, E., “Update on the State of Pb-free Solder Assembly Inside and Outside Motorola,” Hermes Symposium, Dublin, 2000.

13.62

CHAPTER THIRTEEN

55. Fu, H., and J. Liu, “The Development of Lead-Free Soldering,” Proc. of ISEPT, pp. 449–454, Beijing, China, August 8–11, 2001. 56. Shangguan, D., et al., “Application of Lead-Free Eutectic Sn-Ag Solder in No-Clean Thick Film Electronic Modules,” IEEE Trans. on Components, Packaging & Manufacturing Technology, Part B: Advanced Packaging 17(4):603–611, November 1994. 57. Artaki, I., A. M. Jackson, and P. T. Vianco, “Evaluation of Lead-Free Solder Joints in Electronic Assemblies,” J. Electronic Materials, 23(8):757–764, August 1994. 58. Yang, W,. L. E. Felton, and R. W. Messler, Jr., “The Effect of Soldering Process Variables on the Microstructure and Mechanical Properties of Eutectic Sn-Ag/Cu Solder Joints,” Journal of Electronic Materials, 24(10):1465–1472, October 1995. 59. Vincent, J. H., and G. Humpston, “Lead-Free Solders for Electronic Assembly,” Circuits Assembly, 38–41, July 1994. 60. Prismark Partners LLC,“Lead Free Electronic Products—The Sky is Clearing,” November 1999. 61. Handwerker, C., “NCMS Lead Free Solder Project: A National Program,” Proceedings of IPCWorks ’99, Minneapolis, MN, October 27, 1999. 62. Artaki, I., D. W. Finley, A. M. Jackson, U. Ray, and P. T. Vianco, “Wave Soldering with PbFree Solders,” Proc. Surface Mount International Conference, p. 495, San Jose, CA, August 27–31, 1995. 63. Kang, S. K., et al., “Pb-Free Solder Alloys for Flip Chip Applications,” 49th Electronic Components Technology Conference, San Diego, CA, June 1–4, 1999. 64. Mei, Z., F. Hua, and J. Glazer, “Sn-Bi-X Solders,” SMTA International, San Jose, CA, September 13–17, 1999. 65. “Lead-Free Solder Project Final Report,” NCMS Report 0401RE96, August 1997. 66. Feldmann, K., and M. Reichenberger, “Assessment of Lead-Free Solders for SMT,” Apex 2000, Long Beach, CA, March 2000. 67. Miller, C. M., I. E. Anderson, and J. F. Smith, “A Viable Tin-Lead Substitute: Sn-Ag-Cu,” J. Electronic Materials, 23(7):595–601, July 1994. 68. Technical Reports for the Lead-Free Solder Project, Properties Reports, “Room Temperature Tensile Properties of Lead-Free Solder Alloys,” Lead Free Solder Project CD-ROM, National Center for Manufacturing Sciences (NCMS), Ann Arbor, MI, 1998. 69. Senju, patent JP5050286, covers 3–5% Ag, 0.5–3% Cu, 0–5% Sb, balance Sn. 70. U.S. Patent 4,695,428, JW Harris Company patent. 71. Herbert, R., “Lead-Free Alloy Trends for the Assembly of Mixed Technology PWBs,” Proceedings: NEPCON West Conference, Anaheim, CA, February 27–March 2, 2000. 72. Adapted from Rae, A., and R. C. Lasky, “Economics and Implications of Moving to LeadFree Assembly,” Proceedings: NEPCON West 2000 Conference, Anaheim, CA, February 27–March 2, 2000. 73. Anderson, I. E., K. Kirkland, and W. Willenburg, “Implementing Pb-Free Soldering,” SMT Guide, June 2001.

CHAPTER 14

LEAD-FREE SURFACE FINISHES 14.1

INTRODUCTION

To accomplish a lead-free soldering environment, not only the solders used for forming solder joints but also the surface finishes of pads on printed circuit boards (PCBs) and leads of components have to be lead-free. This is based on the considerations of both environmental safety and joint reliability issues. At this stage, an SnPb surface finish is widely used in the electronics industry. Figure 14.1 shows the PCB surface finishes technology adoption status in the United States, published by IPC Technology Marketing Research Council.1 Although Sn-Pb hot-air solder leveling (HASL) still remains the dominant choice since 1998, its usage has definitely been declining with time even before the heat on lead-free soldering was felt by the industry. In Fig. 14.1, several lead-free surface finishes are cited, including organic solderability preservative (OSP), Ni-Au, and Pd. Because the pressure on lead-free soldering is increasing at a tremendous rate, many new lead-free surface finish technologies have emerged since the late 1990s. In this chapter, the options on lead-free surface finishes will be introduced, with the chemistry, process, and performance of the most promising choices discussed. Since the same surface finish may be used on products varying considerably in design and application, the considerations for selecting a surface finish need to address a wide range of possible applications, including solderability, compatibility with solder alloys, solder joint reliability, wire bondability, connector abrasion resistance, electrical contact resistance, shelf life, and contrast in automated optical inspection or registration system.

14.2 OPTIONS FOR PCB LEAD-FREE SURFACE FINISHES Table 14.1 lists the options of lead-free surface finishes for PCBs. The system is categorized by the key element used. Each category is further classified by the type of process and chemistry. Examples are given for certain groups.

14.3

OSP

Organic solderability preservative (OSP) refers to organic coating that is applied to PCB pads as a preservative for solderability, and is also referred to as antitarnish. It includes rosins, resins, and azole chemicals.2–17 Organic solderability preservative is widely used in Japan. Depending on the PCB type, single-sided PCBs use OSP as virtually the only means for preserving solderability. For double-sided, multilayer boards, 40 percent of the surface finishes are OSP types, as shown in Fig. 14.2.18 14.1 Copyright © 2003 by The McGraw-Hill Companies, Inc. Click here for terms of use.

14.2

CHAPTER FOURTEEN

FIGURE 14.1 Surface finish technology market study. (Source: IPC Technology Marketing Research Council, 1999.)

Within the azole group, benzotriazole, imidazoles, and substituted benzimidazoles are the most popular group, and will be discussed individually. Regarding the rosin or resin, it is often referred to as preflux, and will be discussed briefly. In general, the primary benefits of OSP surface finishes are low-cost and flat-surface.

14.3.1

BENZOTRIAZOLE

Use of benzotriazole (BTA) can be dated back to at least the early 1960s. Instead of relying on a physical layer that is mechanically applied onto the top of base-metal copper to provide protection against corrosion and oxidation, benzotriazole chemically reacts with cuprous oxide and forms polymeric copper salt, as shown in Fig. 14.3.19 These polymeric salt molecules align with each other and form a protective film composed of a semipermeable, colorless, three-dimensional polymeric layer on the surface of copper. Cuprous oxide is much faster in reacting with BTA than cupric oxides. Although this film thickness was considered a nominal 50 to 100 angstroms (Å), with an average of about 80 Å, the polymer thickness may continue to grow (within limits) if the metal is continually exposed to oxidant and triazole, especially at low (acidic) pH. This multilayer can be up to 5000 Å thick, depending on many factors, such as temperature, time, pH, corrodent, oxidation reduction environment, and so on.20 This continual growth can also repair defects in an existing film by reacting with entrapped BTA molecules.21 Additional work that was later done by Tornkvist et al. on the surface orientation of BTA suggests a mean orientation of the first BTA layer on a cuprous oxide surface. As shown in Fig. 14.4, the upper nitrogen allows the adsorbed BTA molecule to coordinate to another Cu(I) ion and thereby form a multilayer protective film, consisting of [-Cu(I)-BTA-]n chains.22 Some other surface absorption mechanism has also been postulated.23 However, the latter mechanism appears to allow monolayer BTA protection only.

14.3

LEAD-FREE SURFACE FINISHES

TABLE 14.1 List of Lead-Free Surface Finishes* Surface finish system OSP

Ni-Au

Finish process and chemistry

Example

Benzotriazole

COBRATEC, ENTEK CU-56

Imidazole

AT&T, Protecto 5630 (Kester)

Benzimidazole (substituted)

ENTEK PLUS CU-106A (EnthoneOMI), Glicoat (Shikoku)

Preflux (rosin/resin)

Sealbrite, Solderite RT-05R

Electrolytic Ni-Au, or EG Electroless Ni/electroless (immersion) Au, or ENIG Electroless Ni/electroless (autocatalytic) Au Electroless Ni/electroless (substrate-catalyzed) Au

Ag Bi

Electroless (immersion, or galvanic) Ag

Alpha Level (Alpha Metals); Sterling Silver (MacDermid)

Electroless (immersion) Bi Electrolytic Pd or Pd alloys

Pd

Electroless (autocatalytic) Pd Electroless (autocatalytic) Pd/electroless (immersion) Au

Ni-Pd

Electroless Ni/electroless (immersion) Pd Electroless Ni/electroless (autocatalytic) Pd Electroless Ni/electroless (autocatalytic) Pd/electroless (immersion) Au

Ni-Pd (X)

Electrolytic Ni/PdCo/Au flash (Electroless) Ni/(electroless) Pd-Ni/electroless (immersion) Au

Sn

Electrolytic Sn

Matte—Lucent (large, polygonized)

Electrolytic Sn

Florida CirTech

Electrolytic Sn Electroless (immersion) Sn

White (new)

Electroless (immersion) Sn

Gray (old)

Electroless (modified immersion + autocatalytic) Sn

Flat Solderable Tin (FST)—Dexter

Ni-Sn

Electrolytic Ni/electrolytic Sn

Satin bright Sn—Lucent ECS

Sn-Ag

Electrolytic Sn-Ag

96.5Sn-3.5Ag

Electrolytic Sn-Bi

90Sn-10Bi

Sn-Bi

Electroless (immersion) Sn-Bi

Motorola

Sn-Cu

Electrolytic Sn-Cu

99Sn-1Cu

Sn-Ni

Electrolytic Sn-Ni

* For multilayer designs, the sequence of materials starts from the bottom layer.

14.4

CHAPTER FOURTEEN

(a)

(b)

FIGURE 14.2 Organic solderability preservative in Japan. (a) Surface finishes for double-sided, multilayer boards, and (b) surface finishes for single-sided PCBs.

Substitution in the triazole ring (positions 1 and 2) results in a considerable decrease in inhibiting efficiency versus BTA. A methyl group in the benzene ring (positions 4 and 5) gives, on the other hand, a value of the inhibiting efficiency, which is even higher than that obtained for BTA. These results are closely related to the ability of the molecules to chemisorb and form stable film on the surface. Therefore, the inhibiting efficiency is 4Me- (30 Å) and 5Me-BTA (70 Å) > BTA (<100 Å) > 1Me- and 2Me-BTA.22 Fabrication Process. The application process of BTA is detailed in Fig. 14.5.20 After the initial acid clean, the copper surface is microetched to produce a subtle roughness in order to enhance subsequent solder bonding, as well as possible in-

LEAD-FREE SURFACE FINISHES

14.5

FIGURE 14.3 Scheme of triazole inhibitor mechanism and chemistry.

circuit test probe contact. The etchant is then removed by deionized (DI) rinse, followed by acid rinse, DI rinse, then BTA coating, and completed with DI rinsing and drying. This OSP application process is slightly simpler than the HASL application process: (1) acid clean, (2) water rinse, (3) etch, (4) water rinse, (5) flux application, (6) preheat to 105 to 150°C, (7) solder coat (2 to 10 s/250 to 260°C), (8) excess blowoff, (9) water rinse, and (10) dry.23 Following is a list that compares the application processes for HASL and OSP:

FIGURE 14.4 Surface orientation of BTA on copper.

14.6

CHAPTER FOURTEEN

FIGURE 14.5 Deposition process for BTA on copper.

1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

HASL Acid clean Water rinse Etch Water rinse Flux application Preheat 105–150°C Solder coat (2–10 s/250–260°C) Excess blowoff Water rinse Dry

1. 2. 3. 4. 5. 6. 7. 8. 9.

OSP Acid clean Water rinse Microetch Water rinse Acid rinse Water rinse OSP coat DIW rinse Dry

For BTA coating process, 2.5 percent concentration is satisfactory. The shelf life of BTA-coated PCB is about 2 years at normal storage condition. Generally, the CuBTA complex thickness is 40 to 140 Å.24 However, under high humidity, the shelf life may be as short as 3 to 6 months only.23

FIGURE 14.6 Effect of temperature on the oxidation of BTA-treated and -nontreated copper.

LEAD-FREE SURFACE FINISHES

14.7

FIGURE 14.7 Solderability for various treatments of copper foil.

Performance. Walker studied the effect of temperature on the oxidation extent of BTA-treated copper and nontreated copper by monitoring the weight gain of copper after thermal aging. Results indicate that BTA is much more effective in reducing oxidation at lower temperature than higher temperature, as shown in Fig. 14.6.25 Therefore, aging at 200°C for 400 min, the treated copper had no weight gain, whereas the nontreated sample exhibited a weight gain of about 2 mg/80 cm2. The difference between treated and nontreated copper diminished with increasing temperature. After aging at 400°C for 400 min, the BTA-treated copper only oxidized slightly less than the plain copper, and both exhibited a weight gain of around 50 mg/80 cm2. Obviously, increasing oxidation will deteriorate the solderability. Thwaites investigated the effect of aging on solder spread and wetting time of copper foil with various treatments, with results shown in Fig. 14.7.26 Benzotriazole, tin-lead coating, and preflux (resin lacquer) all preserved solderability very well in terms of area of spread after 6 months of normal storage. The uncoated copper showed no spread at all after the same period of storage. However, the difference between various treatments becomes more pronounced in terms of wetting time, with tin-lead being the most effective in retaining the wetting time, followed in order by resin lacquer, BTA, and uncoated copper. After 6 months’ storage, tin-lead coating increased only slightly in wetting time, while BTA increased from about 0.2 to around 5 s. For uncoated copper, no wetting can be observed at all.

14.3.2

IMIDAZOLES

The chemical structures and oxidation inhibition mechanism of alkylimidazoles is shown in Fig. 14.8. Similar to BTA, alkylimidazole reacts with copper oxide and forms polymeric alkylimidazolium copper film on the surface of copper. The

14.8

CHAPTER FOURTEEN

FIGURE 14.8 Scheme of chemical structure and inhibition mechanism of alkylimidazole.

thickness of this compound is approximately 100 Å.27 The reaction takes place almost immediately, on the order of seconds. Once the surface reaction has been completed, extended dwells in the bath do not advance the reaction; the process passivates. Consequently, the process is easily controlled. The chemistry is aqueous based and can be stored for long periods of time. The most critical part of the process is rinsing between the conditioner and OSP components of the process.27 The efficiency of oxidation inhibition of imidazole is temperature-sensitive. Ray et al. studied the effect of heat treatment on oxide thickness for imidazolecoated copper, with results shown in Fig. 14.9.5 At a low temperature (e.g., 100°C), the oxidation inhibition efficiency is very high, and no oxidation can be discerned after 4 h. The efficiency declines with increasing temperature. At 200°C, the oxide thickness increases about six times after 4 h of aging. The sensitivity toward aging temperature can result in poor wetting due to storage and due to multiple soldering processes, as demonstrated by Fig. 14.10.12 In reflow applications, poor wetting can cause opens for joints with the use of a zipper stencil aperture design.

14.3.3

BENZIMIDAZOLES

Use of benzimidazoles as an OSP for the electronics industry evolved from imidazole chemistry. In the 1970s, Sanwa of Shikoku Chemical Co. patented alkylimidazole and benzylimidazole coating. These were adopted in the United States in 1985. The coating thickness is typically around 0.3 µm, and may range from 0.2 to 0.5 µm. Product suppliers include MacDermid (M-Coat), Chemcut (Schercoat), Kester (Protecto), and Enthone-OMI (Entek).23,28 The protection mechanism is similar to that of imidazole, with a polymeric imidazolium copper film, as shown in Fig. 14.11.20

LEAD-FREE SURFACE FINISHES

14.9

FIGURE 14.9 Effect of heat treatment on oxide thickness for imidazole-coated Cu.

FIGURE 14.10 Examples of good wetting and poor wetting for PCBs with imidazole coating. (a) Incomplete wetting of pads, (b) open caused by a zipper stencil aperture pattern, (c) completely filled plated-through-hole (PTH) via, and (d) partially filled PTH via.

14.10

CHAPTER FOURTEEN

FIGURE 14.11 Inhibition mechanism of substituted benzimidazole on copper surface.

In 1997, Sirtori et al. from IBM-Semea studied the stability of a 2-butyl-5-chlorobenzimidazole film (BCB) before and after a thermal treatment, which simulated the annealing of a typical soldering process. The chemical bonds inside the BCB film and between this film and the copper substrate were investigated by x-ray photoelectron spectroscopy (XPS). The thickness of that film was measured by optical ellipsometry. Protection of the film versus oxidation and its physical modification during the thermal treatment was also investigated. The XPS valence data showed that a part of the chlorine was linked to the benzene ring, and the other part formed either copper chloride or another chloride linked to the nitrogen of the BCB molecule.The passivation film hardened and became an electric insulator during the thermal treatment, so that any successive electrical test was impaired.29 Introduction of substituted benzimidazoles (BAs) results in an improvement in soldering defect rate. In a study conducted by Siemens Information and Communication Networks, Inc., the board quality was the leading cause of wave-soldering defects in their experiment. When Entek 106A, a substituted BA, is used as an OSP, the bridging defect rate was slightly higher than HASL, and increased slightly with increasing residual oxygen level in the soldering atmosphere, as shown in Fig. 14.12.30 The solder mask quality is a more dominant factor than the oxygen level, with an improperly cured solder mask causing much more crossing and bridging than the oxygen does. Fabrication Process. The fabrication process of Entek 106A is shown in Fig. 14.13.20 The process is similar to that of other azole coating processes. Typically, BA chemistry deposits 0.1 to 0.4 µm and relies on ionic copper in the working solution to develop the protective coating. However, there is one limitation about this process: the mixed-metal surfaces can become stained or discolored when processed through the OSP. The discoloration is due to nonuniform deposition of the OSP on the different metals due to the presence of the copper ion.31 This problem can be corrected by utilizing a copper-free formula. By pretreating the copper surface with an alkaline precoat solution, the copper on the printed wiring board (PWB) becomes available to build a consistent OSP coating. The precoat is mildly alkaline and will not discolor active metal surfaces such as gold or aluminum, even if contaminated with copper. The ionic copper can be eliminated from the OSP solution since the copper on the PWB can react with OSP to form the desired coat-

LEAD-FREE SURFACE FINISHES

14.11

FIGURE 14.12 Effect of nitrogen purity on the wave-soldering defect rate. Most of the defects are bridging.

ing.20 This new process produces a slightly thinner OSP layer, about 0.2 to 0.25 µm thinner than the standard process. However, the resistance against being burned out by heat treatment under reflow atmosphere is still comparable with the standard OSP, as shown in Fig. 14.14. The new process produces a very thin, stain-free OSP coating on an active metal surface. The thickness is less than 0.05 µm and is virtually absent on the metal surface, as shown in Fig. 14.15 when tested on a Ni-Au or matte Ni surface.20 Like the original, it provides similar protection against incidental handling contact, 12 months’ shelf life, and similar solderability even with mixed technology in a no-clean air assembly environment. Because of this new mechanism, a thinner but equally robust OSP coating is possible while being selective to copper only. The OSP fabricated with a new process is more heat-resistant than the standard OSP, as shown in Table 14.2.32 Among the OSPs tested, BTA is the least heatresistant. Azoles react with metallic as well as with cuprous or cupric oxides. Ray et al. reported that films grown on the native oxide are more compact and polymerized to provide greater corrosion protection. Films grown from acidic media are thicker, but more permeable to oxygen.

FIGURE 14.13 Typical substituted BA application process.

14.12

CHAPTER FOURTEEN

FIGURE 14.14 Organic solderability preservative coating thickness on copper using the standard process and the new process.

Imidazole film thickness is typically 50 Å. Benzimidazole or alkylated BAs could range from 100 to 10,000 Å in film thickness, depending on solution concentration, immersion time, and other factors. The copper-BA film is polymerized and posesses a high degree of submicroscopic physical porosity. The alkylated BA is more nonporous and less polymerized. Unheated thick films may or may not be solderable, depending on azole chemistry. The thin films (<100 Å) decompose into volatile products at temperatures above 100°C and leave the copper substrate susceptible to oxidation. Films 50 to 100 times thicker than the monolayer azole films do not suffer a significant change in thickness during thermal treatment, but are still ineffective for solderability retention. These films undergo dealkylization/oxidation reactions during thermal treatment, which render them unsolderable. The chemical structure of substituted BAs has a great impact on the solderability. Figure 14.16 shows the effect of OSP coating thickness on wetting tension, calculated from wetting force.5 A short alkyl group on benzene ring C5 of the BA results in a higher wetting tension, whereas a long alkyl group on imidazole carbon provides the highest wetting tension and is independent of coating thickness. In summary, the benefits of substituted BAs include the following: ● ●

Simple conveyorizable process. Ability to withstand the rigors of multiple heat cycles. At least three reflow cycles (even more in an inert environment). However, this capability degrades if the boards are washed due to misprint or mishandling prior to reflow.

FIGURE 14.15 Impact of the new OSP coating process on the OSP thickness of Au and Ni surfaces.

14.13

LEAD-FREE SURFACE FINISHES

TABLE 14.2 Thickness Reduction Due to Reflow Atmosphere Std OSP

New OSP

BTA

0×

Reflow

0.32 µm

0.16 µm

∼80 ang.

218.4 ang.

1 × air

0.30 µm

0.16 µm

0*

219.5 ang.

1 × N2

0.14 µm

0.12 µm

0*

205.0 ang.

Reduction air

6.25%

0.0%

Reduction N2

56.25%

25%

Imidazole

100%

0.0%

100%

6.1%

* Based on presence test.

●

● ● ● ● ●

BA OSP thickness: −0.2 to 0.5 µm (0.3 µm is typical) Excellent coplanarity is offered. Microwave applications: best. Shelf life: 2 months. Cost of surface finish is 0.2 to 0.3 times that of HASL. Corrosion resistance of OSP-coated Cu pads may be a concern during the product service life.

FIGURE 14.16 Effect of the coating thickness of various OSPs on solderability.

14.14

14.3.4

CHAPTER FOURTEEN

PREFLUX

The preflux (rosin/resin-based coatings) have been used extensively as solderability preservatives. Adequate formulations could retain solderability of copper after several thermal excursions experienced by mixed technology. However, due to the nature of rosin/resin, the PCBs often remain somewhat tacky and, accordingly, can introduce contamination through manual handling or entrapment of particulates in the air. In addition, these preflux coatings are sensitive to flux chemistry that is utilized and are virtually compatible only with rosin-based solder pastes or fluxes. Prefluxes are not as robust as modified azole A in terms of heat and moisture resistance, as shown in Fig. 14.17.33 However, they are better than other azole chemistry.

14.4

Ni/Au

Au overcoat on top of Ni has been used as an alternative to HASL for many years, due to the advantages of a flat surface, stability against environment, good shelf life and solderability, and reduced bridging at assembly. It is one of the favorite surface finishes for fine-pitch surface-mount technology (SMT) and ball grid array (BGA) packages. Ni serves as a solderable diffusion barrier and prevents copper migration into solder. Upon soldering and aging, Ni forms a Ni3Sn4 intermetallic layer with Sn-Pb or Sn-Ag alloys, although other intermetallics may also be formed, such as (Cu1-p-qAupNiq)6Sn5 on top of (Ni1-yCuy)3Sn4 intermetallics when soldering with Sn-Ag-Cu alloys.34 Due to the lower coefficient of thermal expansion (CTE) of Ni than Cu (12.96 versus 16.56 ppm/°C), Ni can also stabilize plated-through-holes

FIGURE 14.17 Effect of various surface treatments on solderability after multiple reflows or after humidity treatment.

LEAD-FREE SURFACE FINISHES

14.15

during thermal excursion.35 Although Ni forms a more stable solder joint interface than does Cu, it is prone to oxidation, and the Au overcoat serves as an oxidation barrier for the Ni underlayer. If the Au layer is thin, it will quickly dissolve into solder and be removed from the interface, thus eliminating the concern about Au embrittlement. If the Au layer is not thin, Au embrittlement may be a concern. Au dissolves more rapidly into Sn than into eutectic Sn-Pb solder for the same amount of superheating.36,37 The same is true for eutectic Sn-Ag, although Sn-Ag is more tolerant of Au than eutectic Sn-Pb.38–40 The two most commonly used Ni/Au finishes are electrolytic Ni/Au and electroless Ni/immersion Au.

14.4.1

ELECTROLYTIC Ni/Au

Electrolytic Ni/Au comprises an inner layer of electrolytic Ni plus an outer layer of electrolytic Au (often expressed as EG). It is the traditional surface finish used for wire-bonded applications. This process requires the bars to make an electrical connection from the edge of the panel to the area to be plated. The tie bars complicate substrate layout and compromise the routing density of PCB traces. This becomes a critical issue when the circuit connection density increases and is the main reason that EG is less common than immersion gold, to be discussed later.11 The typical thickness of nickel in EG is 150 to 200 µin (3.75 to 5 µm), although 200 to 250 µin (5 to 6.25 µm) is desired in order to prevent slivering during etching and subsequent processing.35 For an EG surface finish, the thickness and hardness of Au are highly dependent on the applications. In general, 3 to 15 µin (0.075 to 0.375 µm) of hard Au is needed for soldering, with greater than 30 µin (0.75 µm) of hard Au for the connector and greater than 30 µin (0.75 µm) of soft Au for wire bonding.35 However, these amounts should only be considered as a guideline. This is particularly true when a surface finish is used for mixed applications. For instance, Nakajima et al., from Flextronics, employed a metal finish of 20 µin (0.5 µm) of soft Au and 200 µin (5 µm) of Ni as a wire-bondable and solderable surface finish in Personal Computer Memory Card International Association (PCMCIA) card assembly involving chip-scale packages (CSPs) and chips on board (COBs). Nonsolder-mask-defined (NSMD) pad designs were applied on this double-sided board.41 Fabrication Process. The steps of the fabrication process of EG itself can be described as follows35: 1. 2. 3. 4.

Use cleaner to clean the copper surface. Etch copper surface. Plate nickel at 52 to 57°C. Plate gold at 29 to 38°C.

The PCB fabrication process is affected by the type of surface finish selected. In the case of an EN surface finish, the steps of the PCB fabrication process are as follows35: 1. Inner-layer (IL) manufacture. 2. Layup and lamination.

14.16

3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.

CHAPTER FOURTEEN

Drill. Desmear and electroless copper plating. Outer-layer (OL) imaging. Plate copper. Plate nickel. Plate gold. Strip and etch. Surface preparation. Solder mask. Fabrication. Electrical test. Final inspection.

For connector applications using an EG surface finish, the steps of the PCB process are as follows35: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.

IL manufacture. Layup and lamination. Drill. Desmear and electroless copper plating. OL imaging. Plate copper. Plate Ni/Au. Acid clean. Flat mask. Plate gold tips. Strip and etch. Surface preparation. Solder mask. Fabrication. Electrical test. Final inspection.

Performance. For Au-Au thermosonic wire bonding, the bondability decreases with increasing hardness of the Au surface. At Au layer thickness of 0.15, 0.10, ∼0.05, and 0 µm, the Knoop hardness (HK) is 235, 554, 862, and 1007, respectively. A minimum Au layer of 0.1-µm thickness is considered to be necessary for good bondability by Lai and Liu.42 In general, the hardness of the Au surface decreases with increasing Au thickness, while the Au thickness increases with increasing P content in the Ni layer, and decreasing pH value of the nickel bath. For instance, at pH levels of 4 to 5, 8 to 9, and 9 to 10, the P level (wt%) in the Ni layer is 10 to 12, 5 to 8, and 2 to 5, respectively. Thus, at a P content (wt% in Ni) of 10.3, 9.6, 8.4, and 6.5, the Au layer thickness is 0.15, 0.10, 0.08, and 0.02 µm, respectively. For a good Au wire (25-µm diameter) bonding, the pull strength is 7.8 gf, and loops broke

LEAD-FREE SURFACE FINISHES

14.17

right above the ball. For a poor bond (pull strength of 2.7 gf), the bond ball lifted off the pad.42 For soldering applications, gold embrittlement is an issue if the gold content in solder joints exceeds 3 percent by weight.43–45 This is equivalent to about 30 µin (0.75 µm) of Au on the pad. Therefore, if the gold thickness is specified at 3 to 15 µin (0.075 to 0.375 µm), the gold embrittlement can be well prevented. Figure 14.18 shows the histogram of gold layer thickness in the EG process.35 The gold thickness ranges from 3 to 9 µin and holds a process capability (Cp) value better than 1.0. Electrolytic gold is less porous than immersion gold; therefore, it is more effective in preserving the solderability of the pad.35 Cinque and Morris, Jr., from

FIGURE 14.18 Histogram of EG gold thickness by x-ray fluorescence. Total of 297 measurements, mean = 5.1, Cp = 1.6.

14.18

CHAPTER FOURTEEN

Lawrence Berkeley Lab, investigated the possibility of flux soldering on an EG finish.46 The results suggest that electrodeposition of a thin gold plate (0.14 µm) and the concurrent reduction of nickel oxide produce a gold-nickel system that will wet without flux. Nickel oxidation was observed to occur via nickel outdiffusion and by direct exposure of the substrate through pinhole plating defects. Auger chemical analysis indicates that pinholes do not produce oxidation of the surrounding substrate area. In the work of Ludwig et al., the soldering performance of EG was compared with OSP and two new lead-free surface finishes: satin-bright Ni/Sn and Ni/PdCo/ Au.47 EG is found to be good in wettability and voiding, and medium in lap shear strength. It is not sensitive to aging, flux chemistry, reflow atmosphere; it is slightly sensitive to alloy type and profile length. Figures 14.19, 14.20, and 14.21 show the wetting, voiding, and lap shear bond strength performance of EG versus three other surface finishes, respectively.47 The data shown are the overall average performance of systems including five different fluxes and four lead-free solders, 42Sn-58Bi, 91.8Sn-4.8Bi-3.4Ag, 95.5Sn-3.8Ag-0.7Cu, 96.5Sn-3.5Ag, together with eutectic 63Sn-37Pb. The EG process does have a limited ability to throw nickel; therefore, it cannot be used without extreme measures in high–aspect ratio boards. Consequently, the process is not the finish of choice for thick boards with small holes. An aspect ratio of less than 8:1 is required.35 Other shortcomings experienced by the EG finish include: cost, solder joint embrittlement, slivers, contamination from solder mask fumes.43,48 The EG process is adequate for boards with connectors, PCMCIAs, memory, or technologies that do not require a high aspect ratio.

14.4.2

ELECTROLESS Ni/IMMERSION Au

Electroless nickel (100 to 200 µin, or 2.5 to 5.0 µm) with an immersion gold flash (6 to 10 µin, or 0.15 to 0.25 µm) (ENIG) is another major type of Ni/Au surface finish. Fabrication Process. The fabrication process of EG itself can be described as follows35: 1. 2. 3. 4. 5. 6. 7.

Use cleaner to clean the copper surface. Etch copper surface. Pre-dip. Catalyst. EN at 79 to 85°C. Neutralization. Immersion gold at 85 to 91°C.

The PCB fabrication process is affected by the type of surface finish selected. In the case of an ENIG surface finish, the PCB fabrication process is as follows35: 1. 2. 3. 4.

IL manufacture. Layup and lamination. Drill. Desmear and electroless copper plating.

FIGURE 14.19 Effect of surface finish on wetting.

FIGURE 14.20 Effect of surface finish on voiding.

FIGURE 14.21 Effect of surface finish on lap shear bond strength.

14.19

14.20

5. 6. 7. 8. 9. 10. 11. 12. 13. 14.

CHAPTER FOURTEEN

OL imaging. Plate copper. Plate nickel. Plate gold. Strip and etch. Surface preparation. Solder mask. Fabrication. Electrical test. Final inspection.

For connector applications using an ENIG surface finish, the PCB process can be shown as follows35: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.

IL manufacture. Layup and lamination. Drill. Desmear and electroless copper plating. OL imaging. Plate copper. Plate Ni/Au. Acid clean. Flat mask. Plate gold tips. Strip and etch. Surface preparation. Solder mask. Fabrication. Electrical test. Final inspection.

Chemistry of the ENIG Process. The first step in the ENIG process is to catalyze the copper surface for Ni deposition. Proper catalysis of the copper for nickel deposition has been demonstrated to affect the highest-priority failure modes. The electromotive potentials of nickel and several other elements are shown in Table 14.3. Since Ni is less noble than Cu, activation of the copper surface for EN plating can be achieved in several ways. Normally, it is done by seeding a noble metal such as palladium from an acidic solution of palladium sulfate/chloride.49 Recently, a galvanic displacement reaction is used to deposit a catalytic seed layer of ruthenium (Ru) metal onto the Cu. The use of ruthenium catalysis is a more selective and controllable process for catalyzing copper. Ruthenium is favored since it is readily available, cost-effective, resistant to colloid formation, and inspectable during deposition. The ruthenium-nickel-boron system reduces the occurrence and increases the detection of failure modes associated with EN deposition.50

14.21

LEAD-FREE SURFACE FINISHES

TABLE 14.3 Electromotive Potential of Several Selected Elements Element

Electromotive potential

Au

+1.40 V

Pd

+0.83 V

Ag

+0.80 V

Ru

+0.45 V

Cu

+0.34 V

H

0.00 V

Ni

−0.25 V

The Ni is then deposited from the solution onto the catalyzed copper surface. Table 14.4 shows the formulations, including components, functions, and examples of EN plating bath.51 The Ni deposition is aided by a hypophosphite (H2PO2−) reducing agent that decomposes during this reaction and results in the codeposition of phosphorous in the EN layer.49 3ΝaΗ2PΟ2 + 3Η2Ο + ΝiSΟ4 → 3ΝaΗ2PΟ3 + Η2SΟ4 + 2Η2 + Νi0 or alternatively Νi2+ + Η2PΟ2− + Η2Ο → Νi0 + Η2PΟ3− + 2Η+

TABLE 14.4 Formulations Including Components, Functions, and Examples of EN Plating Bath Components

Functions

Examples

Nickel ions

Source of nickel ions

Nickel chloride, nickel sulfate, nickel acetate

Hypophosphite Ions

Reducing agent

Sodium hypophosphite, sodium borohydride, hydrazine

Complexants

Form nickel complexes, prevent excess free-Ni ion concentration, so stabilizing the Ni bath.

Monocarboxylic acids, dicarboxylic acids, hydroxycarboxylic acids

Accelerators

Activate hypophosphite ions and accelerate deposition. Mode of action opposes stabilizers.

Sulfur compounds anions of some monodicarboxylic acids, fluorides

Stabilizers

Prevent solution breakdown by shielding catalytically active nuclei.

Sulfur compounds, transition metals, etc.

Buffers

pH stabilizers, for long-term pH control

Sodium salt of certain complexants

pH regulators

For subsequent pH control

Sulfuric acid/caustic soda ammonia

14.22

CHAPTER FOURTEEN

The nickel cation obtains two electrons from the hypophosphite and is reduced to nickel metal. However, release of electrons from hypophosphite occurs only at the site of a catalyst. The catalyst is a physical site where the reducing agent is adsorbed and rearranges to an intermediate product, donating its electrons. Figure 14.22 shows a scanning electron microscope (SEM) photo of ruthenium-catalyzed nickel deposition.50 Phosphorus is also codeposited with nickel as shown in the following: 2H2PO2− + Hads → H2PO3− + H2O + OH− + P 3H2PO2− → H2PO3− + H2O + 2OH− + 2P Table 14.5 shows characteristics of EN.50 Another EN plating chemistry is boron based, as shown in the following52: 3 2R2ΝΗ ⋅ ΒΗ3 + 3Νi++ + 2Η2Ο → ΝiΒ + 2Νi + 2R2ΝΗ + ΗΒΟ2 + 6Η+ + ᎏ 2 Η2 Mei et al. stated that EN becomes more corrosion-resistant with increasing phosphorus content.51 The phosphorus content in electroless Ni should not be too high, because the wetting on nickel-phosphorus degrades with the phosphorus content.51 The phosphorus content increases with decreasing pH value. Typically, the nickel-phosphorus

FIGURE 14.22 Scanning electron microscope image of ruthenium-catalyzed nickel deposition.

14.23

LEAD-FREE SURFACE FINISHES

TABLE 14.5 Physical Characteristics of EN Property Hardness

Density Melting point Thermal expansion Wear resistance

Measured value

Test method, comments

500–700 HV100

Vickers

500–700 HK100

Knoop

45–55 RC

Rockwell

7.9–8.3 g/cm3

Pure Ni = 8.90

890°C

7 < P < 10%

12–15 µm/m°C

0–100°C

14–18 TWI (Taber Wear Index)

Weight loss, 1000 rev, 10 N

55–90 µΩ⋅cm

Electrical resistivity Ductility

1–2.5% elongation

Instron pull test

Internal stress

0–5 Kpsi tensile

From 10–6% P, 1 mil

Thermal conductivity

0.01 cal/° cm s−1

Phosphorous Grain size Tensile strength

6–10%

ICP AA

0.001–0.01 µm (10–100 Å)

X-ray diffraction

500–750 N/mm2

Instron pull test

chemistry is categorized as low-phosphorus (1 to 5 percent), midphosphorus (6 to 10 percent), and high-phosphorus (>10 percent) content. Midphosphorus is the most commonly used for microelectronics applications.52 Atotech investigations have shown that the phosphorus content in the upper range of 8 to 10 percent gives many of the desired properties that are needed for the ENIG finish.The phosphorus content in an EN deposit normally increases 1 to 2 percent as the nickel metal turnovers (MTOs) increase, as shown in Fig. 14.23.49 Cullen noted that, in theory, 1 µm of electroless NiP will prevent any migration under soldering conditions. In addition to the migration of copper through nickel, the solder will also dissolve the nickel during reflow. The dissolution also occurs to a much lesser extent after soldering. Based on the dissolution rate of nickel into solder to form the Ni3Sn4 intermetallic, 0.5 µm is considered more than enough nickel thickness to perform this function at typical soldering conditions.50 As mentioned earlier, the commonly employed EN thickness is 2.5 to 5 µm. Immersion Gold Process. An immersion reaction is an oxidation/reduction system in which a metal ion in solution is reduced to the metal at the expense of the surface metal, which is oxidized to an ion. The exchange occurs in one direction only and is determined by the relative positions of the interacting metals in the electromotive force series. In principle, any metal ions in solution higher in the electromo-

FIGURE 14.23 Phosphorus content of EN as a function of nickel MTO.

14.24

CHAPTER FOURTEEN

tive series will displace any base metal below it in the series. Since the base metal is oxidized, it is also considered a corrosion process for the base metal. In immersion plating of gold over nickel, gold ions from solution are reduced to gold metal. The electrons needed for this reduction are supplied by the nickel substrate itself. Immersion deposition or displacement plating will cease as soon as the substrate is completely covered by the immersion coating52: Νi0 + 2Αu+ → Νi2+ + 2Αu0 or Νi + 2Αu(CΝ)2− → Νi2+ + 2Αu + 4CΝ− The typical thickness of gold flash layer is less than 5.0 µin, or 0.125 µm.53 The immersion gold thickness used in the electronics industry ranges from 2 to 8 µin (0.05 to 0.2 µm). The studies carried out by Atotech indicated that an ideal gold thickness is 3 to 4 µin, with an operating window of 2.5 to 4.5 µin. Too low gold thickness will result in oxidation of the nickel and consequently poor wetting of the solder during assembly.Too high gold thickness will result in high levels of attack on the nickel surface, resulting in the possibility of interfacial fracture leading to poor solderability.49 At 150 µin (3.75 µm) of nickel and 3 to 5 µin (0.075 to 0.125 µm) of gold, the copper circuits are completely encapsulated. The solderability of the nickel is preserved by the gold to at least a 1-year shelf life. Performance. Similar to EG, ENIG offers advantages such as coplanarity, Al-wire bondability, and the ability to survive multiple soldering cycles (up to three reflows). Again, the nickel layer allows multiple hand reworks without copper dissolution being a factor. As described in the EG section, the nickel also acts like a rivet to improve through-hole thermal integrity.49 The gold finish on the nickel has good reflectivity. This allows this finish to be suitable for automated optical inspection (AOI). The difference in color between the gold and the solder after assembly makes for ease of visual inspection at that stage. The electrical conductivity of the finish does not interfere with electrical testing before or after assembly.53 Electroless nickel/immersion gold is the more common Ni/Au surface finish specification. However, if not properly fabricated, its thin or porous gold can allow nickel to migrate to the surface and oxidize, causing a nonsolderable surface mount pad. The nickel thickness and phosphorus content in the nickel also play an important role in obtaining reliable solder connections.11 Other problems encountered by ENIG include black pad, skip plating, extraneous plating, and embrittlement of the solder mask. Black pad is a symptom that is associated with some weak solder joints formed on ENIG surface finishes. After the weak joint is ruptured, the exposed nickel pad is black. The black-pad defect was found to be due to a hyperactive corrosive immersion gold (IG) process that changes the near-surface microstructure of P-Ni into one with a marginal to total nonwetting state. Figure 14.24 shows a high-magnification cross-sectional view of a solder joint formed on black pad.54 The black-pad defect shall be classified in terms of hyperactive corrosive activity.55 Charge buildup near the module boundaries triggers hypercorrosion. Long traces (with several ohms of resistance) with differential pad plating surface area may induce the condition of charge buildup by the galvanic reaction. The minor difference in electrical potential among the packages and leads caused different types or different degrees of chemical reactions between the ENIG bath, resulting in the preferential occurrence of black pads. Johal reported that a rapid buildup of an immersion gold layer encourages a higher attack on the E-Ni. This rapid attack occurs along the E-Ni grain boundaries, resulting in a possible black-pad defect.49

LEAD-FREE SURFACE FINISHES

14.25

FIGURE 14.24 A 2000× cross-sectional view of a gullwing solder joint formed on a black pad. Severe corrosion can be noted at the side of the pad surface.

Skip plating is seen on some boards as areas with missing nickel on copper pads, as shown in Fig. 14.25.49 Extraneous plating is an excessive buildup of nickel on copper, as shown in Fig. 14.26.49 Both symptoms can be attributed to an activation process of the copper surface. As discussed earlier, activation of the copper surface for EN plating can be achieved in several ways, and is normally done by seeding a noble metal such as palladium from an acidic solution of palladium sulfate/chloride. However, there is a balance of the amount of palladium seeding in combination to the activity of the nickel bath that must be maintained; otherwise, the skip plating or extraneous plating will occur.49 Besides the unbalanced activation process as a cause of skip plating, it was also hypothesized that a static is created in the solder mask operation on certain capacitive areas of the circuitry and that this static attracts volatiles during the mask cure operation and is the underlying cause of skip plating.56 Embrittlement of the solder mask is mainly caused by the EN bath. This bath, as well as the immersion gold bath, is operated at around 82°C with a 20-min soak time for nickel and 10 min for gold. Besides being affected by the elevated temperature, the strong reducing agent may also be absorbed into the soft porous mask, making it brittle and, consequently, may lead to peeling at the mask surface junction. Baking the boards after the ENIG process may minimize this effect.56

14.4.3

ELECTROLESS Ni/ELECTROLESS (AUTOCATALYTIC) Au

Most wire-bonded COB assemblies include SMT components on the same substrate. Thick gold is necessary for the wire-bonded devices, but is unacceptable for the SMT devices. The electroless gold process can be selectively plated over the

14.26

CHAPTER FOURTEEN

FIGURE 14.25 Example of skip plating in the ENIG process.

immersion gold. Following the immersion gold, a plating mask is applied to the panel exposing only the area requiring the thicker gold. The electroless gold is then deposited onto the unmasked areas. The finished gold thickness is 20 to 60 µin over nickel. The plating chemistry of electroless gold (cyanide-based) can be expressed by the following: 3 − − R2ΝΗ ⋅ ΒΗ3 + 4ΟΗ− + 3Αu(CΝ)2− → R2ΝΗ + ᎏ 2 Η2 + ΒΟ2 + 2Η2Ο + 3Αu + 6CΝ

14.5

IMMERSION Ag

Immersion silver is another lead-free surface finish formed by galvanic reaction. Silver is selected due to the following four considerations: (1) electromotive potential of Ag (+0.80 V) relative to copper (+0.344 V) allows use of immersion deposition process; (2) high electrical conductivity of Ag is compatible with touchpad applications, in-circuit probe test processes, and signal transmission requirement; (3) Ag is a noble metal and thus promises good stability; (4) Ag dissolves into solder quickly and thus promises good solderability.1 Fabrication Process. The immersion silver coating process consists of four baths, a precleaner, a microetch followed by the conditioner, and finally the plating bath. Table 14.6 shows the detailed process conditions for organic modified silver (Sterling™ Silver).1 The Ag coating is applied by an immersion process that exchanges

14.27

LEAD-FREE SURFACE FINISHES

FIGURE 14.26 Example of extraneous plating in the ENIG process caused by overactivation of copper.

copper from the base metal for silver in the silver nitrate bath, as illustrated by Fig. 14.27.1 As discussed in the section on the immersion Au process, a particular benefit of immersion processes is the self-terminating feature; that is, the process terminates when the coating completely covers the base material. As a result, the plating thickness is consistent and easily controlled.54 The process can be horizontal or vertical, with 8 min of cycle time for a conveyorized process. Typically, 120 panels/h can be treated in 8-m equipment at 50°C process temperature. Figure 14.28 shows an example of PCB with an immersion Ag surface finish.1 Silver finish is applied after the solder mask, with the silver deposited on the exposed copper surface. Since silver surfaces are readily tarnished, an organic inhibitor is included in the plating bath to protect the surface. The thickness of TABLE 14.6 Immersion Process Conditions for Sterling™ Silver Process

Temperature (°C)

Conveyorized

Immersion

Sterling™ acid cleaner

50

30 s

5 min

Sterling™ surface prep

40

60 s

60 s

Sterling™ predip

30

30 s

30 s

Sterling™ Silver

50

60 s

60 s

14.28

CHAPTER FOURTEEN

organic modified silver is typically 0.2 to 0.3 µm, although other thickness ranges (e.g., 0.08 to 0.16 µm) have also been used. Obviously, the coplanarity will be excellent for such a thin coating. Figure 14.29 shows the topology of the organic modified silver.1 Inclusion of an organic inhibitor is fairly evenly distributed in the Ag layer down to a depth of about 3 µin (0.075 µm), as indicated by the FIGURE 14.27 Copper displaced by silver in Auger depth profiling for organic modithe immersion silver process. fied silver finish (see Fig. 14.30).1 For Alpha-Level immersion silver, the coating consists of a layer of silver approximately 4 to 5 µin (0.1 to 0.125 µm) thick with a thin inhibitor layer superimposed, as shown in Fig. 14.31.57 The inhibitor layer is essentially an OSP, which is approximately 5 Å thick.58 Microetch. The immersion Ag finish can be produced as a shiny or a matte finish. This shiny or matte surface characteristics are due to the surface roughness, and are controlled by the etching rate of copper. This microetch step provides a secondary cleaning of the copper surface. In addition, it also microroughens the surface and increases the surface area. As a result, after the immersion Ag coating process, the

FIGURE 14.28 Picture of a PCB with an immersion Ag surface finish.

LEAD-FREE SURFACE FINISHES

14.29

FIGURE 14.29 Topology of organic modified silver coating.

surface with increased surface roughness or greater surface area appears as a matte finish, and the surface with minimal surface roughness appears bright and shiny. Plating Chemistry. The reaction of the immersion Ag process can be expressed as follows: Cu + 2Αg+ → Cu2+ + 2Αg

FIGURE 14.30 Auger depth profiling for organic modified silver finish. The silver deposit contains 2 to 4 percent carbon (by wt%) or approximately 30 percent (by at%). (Source: Auger analysis data provided by Arch Chemicals, Inc.)

14.30

CHAPTER FOURTEEN

FIGURE 14.31 Schematic of alpha-level immersion Ag.

The chemicals used in the plating bath are listed in Table 14.7. Ag coating thickness is affected by time, temperature, pH, and Ag ion concentration of silver nitrate bath.54 Figure 14.32 shows the effect of immersion time on Ag coating thickness.59 Performance. Perhaps the first concern about immersion Ag is the potential for Ag migration. Cullen investigated the Bellcore TR-78 electromigration performance of immersion silver (Sterling™ Silver) together with copper and HASL.1 Results indicate that, at 85°C/85%RH and 10 VDC bias condition, immersion silver exhibits a resistance value higher than that of copper, and HASL finishes at both 96 and 596 h, as shown in Fig. 14.33, thus eliminating the concern on Ag migration. Figure 14.34 shows the posttest coupon from the electromigration test, displaying no sign of dendrite formation. Results on a surface insulation resistance (SIR) test also show a safe pass for Bellcore TR-78 specifications. Chada et al., from Motorola, also reported that the immersion Ag surface finish performs adequately in the SIR and electromigration (EM) tests and is not readily prone to dendritic growth in the presence of high humidity.60 However, ENIG and OSP are superior in the water droplet conditions simulating condensation and are less likely to electromigrate under those circumstances.

TABLE 14.7 Chemistry of Immersion Ag Plating Bath Chemicals

Functions

Ag

Metal source, 0.46 V relative to Cu

HNO3

Produce Ag anion, and accelerate reaction

Cu complexation

Prevent the copper in solution to affect reaction

Inhibitors

Prevent bath sensitivity to light, and assure deposit uniformity

Surfactants

Prevent electromigration and inhibit tarnish

Buffers

Control pH of bath

LEAD-FREE SURFACE FINISHES

14.31

FIGURE 14.32 Effect of immersion time on Ag coating thickness.

The solderability of immersion Ag finish has been tested by Beigle by evaluating the hole-filling performance at wave soldering. Results indicate that immersion Ag is almost as good as HASL Sn-Pb, and is considerably better than OSP for both steam-aged and unaged samples, as shown in Table 14.8.59 Beigle also studied the wetting force of immersion Ag, HASL, two OSPs, and electrolytic Ni-Au surface finishes in meniscograph test with five different aging treatments: (1) fresh, (2) three reflows, (3) 40°C/93% RH for 96 h, (4) 40°C/93% RH for 96 h, followed by three reflows, and (5) 150°C for 2 h. Results indicate that the wetting force for all systems is comparable for fresh samples. Aging treatment results in a declining wetting force for systems other than HASL. Immersion Ag is less sensitive to aging treatment than both electrolytic Ni-Au and OSPs. The wetting defect rate of reflow soldering is expected to be closely correlated with wetting force performance. Cullen studied the wetting defect rate (IPC-J-STD 003 Test F) of a convection reflow soldering system for OSP, ENIG, and immersion Ag with three different thicknesses. Results indicate that only the OSP finish exhibits wetting defects, as shown in Fig. 14.35. Gordon et al. also reported that the solderability of immersion silver is relatively insensitive to storage at 85°C/85% RH conditions. Depending on the type and thick-

FIGURE 14.33 Electromigration data of immersion Ag (Sterling), copper, and HASL at 96 and 596 h, per Bellcore TR-78 specifications: 85°C/85% RH, 10 VDC bias.

14.32

CHAPTER FOURTEEN

FIGURE 14.34 Posttest coupon from electromigration test, indicating no sign of dendrite formation from the silver-finished traces.

ness, however, the immersion silver is sensitive to assembly processes. Immersion silver has demonstrated superior moisture and insulation resistance behavior compared with HASL, and modules manufactured with an immersion silver finish have passed all appropriate module validation testing for automotive electronic applications.61 Chada and Bradley reported sensitivity of immersion Ag toward corrosive atmosphere storage condition.60 In their work, wetting and spreading of both Pbcontaining and Pb-free solder pastes over the immersion Ag surface are adequate even when the surface is mildly corroded. However, ENIG and OSP exhibit greater solder spread than immersion Ag finish for all testing conditions studied, although the silver was more consistent. Also, if subjected to a corrosive environment for extended periods of time (>96 h flowing mixed gas), wetting deteriorates drastically TABLE 14.8 Effect of Surface Finish Type and Aging Treatment on the Hole-Filling Performance Percentage of hole fill Coating

No aging

Steam-aged

Silver-plated

99.7

99.9

100

99.97

93.57

92.62

HASL Organic A

LEAD-FREE SURFACE FINISHES

14.33

FIGURE 14.35 Effect of PCB surface finish types on solderability defect rate per IPC-J-STD-003 Type F in convection reflow soldering process.

for immersion Ag and ENIG finishes. This sensitivity of immersion Ag toward corrosive storage environment is consistent with the findings of Reed, who reported that immersion Ag is sensitive to corrosive environments62: the solderability of immersion silver is severely impacted by exposure to Cl2, SO2, and NO2 gases in the presence of water vapor. It is recommended by Reed that boards be packaged in polyethylene bags no matter what the storage environment is. If the raw boards are stored in dry air, a 1-year shelf life can be expected. Reed also noted that exposed silver after assembly will corrode, although the products of this chemical attack appear to be benign for SIR and dendritic growth. Regardless, it may cause difficulties for field repairs. As to the unprotected immersion silver, the test points and etched-on symbols will tarnish, and the solder mask is considered an effective protectant for silver in corrosive environments in service. Since the amount of silver on the board termination is estimated to contribute less than 0.1 percent in a typical 20-mil pitch solder joint, no effect is expected on the solder joint life.62 Immersion Ag is also good for ultrasonic Al wire-bonding applications. Figure 14.36 shows comparison of clad Al pad and immersion Ag (Sterling Silver) finish on ultrasonic 10-mil Al wire bonding.1 Results indicate that immersion Ag is slightly better than clad Al, and thus it is adequate for wire-bonding applications. Cullen also reported the test results on touchpad applications. In this work, the contact resistance of four different surface finishes following 100,000 touchpad activations was compared, as shown in Table 14.9.1 Immersion Ag, electroless Pd, and ENIG remain very good electrical contact, while the resistance of conductive carbon increases to 0.28 mΩ. In-circuit test is another important criterion to be met by any PCB surface finishes. Gordon et al. studied the in-circuit test performance of immersion Ag.61 In their work, the test pad was probed with blade probes made of heat-treated steel, coated with gold on top of a hard-nickel finish. For each probe, a spring force of 8.1 oz was provided. Results indicate that percent of reseats and percent of failures

14.34

CHAPTER FOURTEEN

FIGURE 14.36 Effect of surface finish types on ultrasonic 10-mil Al wire-bonding performance.

decrease with increasing Ag thickness and increasing surface roughness (or etching rate).61 This increase in surface roughness appears to be crucial for enhancing the contact between pad and probe, at least in the case of blade probes. Chada et al. observed that immersion Ag/BGA solder joints appear to have lower load levels at failure than OSP and ENIG finishes in the as-reflowed condition. The effects of silver thickness and peak reflow temperature are insignificant on the reliability. However, solid-state aging and multiple reflows lead to a lowering of failure load.60 In Parker’s study at Viasystems, the rupture strength of the joints formed on immersion Ag finish consistently exceeds 1.0 lb, which is within the range generally attributed to a joint formed on an HASL surface. More important, however, is the fact that the rupture always occurs at the lead interface and never at the pad/board interface. This indicates that the bond at the pad is superior to that formed at the lead.54 Chase et al., at Raytheon and Nokia, compared the effect of surface finishes, including immersion Ag, Ni/Au (ENIG), and solder HASL on the second-level reliability of fine-pitch area array assemblies.63 A temperature cycling test with a temperature range of −40 to +125°C was used, with dwell times of at least 20 min at high temperature and 15 min at low temperature. Chamber temperature ramp rates were 8 to 10°C/min. The average time for 1 cycle was 75 min. Results indicate that, for 144 I/O and 0.8-mm-pitch BGAs, the reliability increases in the following order: Ni-Au < immersion Ag < HASL, as shown in Fig. 14.37.63 However, it should be noted that TABLE 14.9 Contact Resistance of Touchpads After 100,000 Activations Surface finishes Conductive carbon

Contact resistance (mΩ)

Note

0.2773

Heavy gloss on one pad, slight gloss on all others. Circuit board between one pad is worn to shine.

Immersion Ag (Sterling)

0

Pads slightly dulled.

Electroless Pd

0

Green circuit between is turning brown.

ENIG

0

Some nicks and cuts in gold pads.

14.35 FIGURE 14.37 Comparison of 144 I/O BGA test results by surface finish. The temperature cycling range is −40 to +125°C.

14.36

CHAPTER FOURTEEN

some premature failure points of the immersion Ag system started from 254 cycles were considered to fall in another failure mechanism and were not plotted. These premature failures were attributed to the presence of postassembly hairline cracks on the board side; the cause of formation of those hairline cracks is not understood yet. For 156 I/O with 1.0-mm-pitch BGA system, immersion Ag is comparable with HASL and is better than ENIG.

14.6

IMMERSION Bi

Immersion Bi was introduced in 1996 as a nonprecious metal surface finish intended to address the coplanarity problem experienced by HASL in fine-pitch applications.59 Fabrication Process. The immersion bismuth process features three steps: 1. An acidic cleaner that removes surface oils and solder mask residue. 2. Microetch step that prepares the copper substrate topography for the deposit of immersion bismuth. For the bismuth to deposit on copper, the bath is highly acidic. 3. Bi plating step. The immersion bismuth bath is operated at 50°C, and a typical contact time of 1 to 2 min to produce a deposit of pure metallic bismuth onto the copper surface. Similar to other immersion processes, the reaction is complete when the copper can no longer be released and the surface is completely covered. Performance. The plated Bi metal is uniform dark gray, and easily distinguished from the substrate copper. During aging or thermal excursions, the Bi finish becomes more copperlike in appearance. This is believed to be caused by diffusion of the bismuth into the underlying copper. Beigle considered this to be a cosmetic effect and has no major impact on solderability under normal conditions.59 The solderability of immersion Bi was found to be better than Pd in a throughhole filling test. For as-plated finishes, Bi exhibited 99 percent hole fill, while Pd only displayed 60 percent hole fill.59 In another experiment comparing Bi with OSP, PCBs with through-holes varying in hole size from 0.062 to 0.022 in were used to examine the hole fill with 11 different no-clean fluxes. A highly activated organic acid–based flux was used as a control. All boards were preconditioned with two air-atmosphere heating cycles with a profile having a peak temperature of 220°C and a dwell time of 40 s. At wave soldering, each board was applied with 600 to 800 µg/in2 of flux. The soldering performance was evaluated using complete topside pad coverage as the acceptance criteria. Results indicate that immersion Bi is less sensitive than OSP to flux selection, as shown in Fig. 14.38.59 The solderability of immersion Bi for reflow applications was also reported by Beigle.59 The spread performance of solder paste was determined on 20-mil-pitch QFP pads with 70-mil length, using the following procedure: 1. Steam-age half of the test boards. 2. Precondition test boards—one infrared reflow pass in air. 3. Screen solder paste.

LEAD-FREE SURFACE FINISHES

14.37

FIGURE 14.38 Effect of flux selection on the hole filling yield of immersion Bi and OSP finishes.

4. Reflow solder in the air. 5. Inspect and measure solder wetting distance. Results indicate that the reflow spread performance decreases in the following order: HASL > immersion Ag > OSP > immersion Bi, as shown in Table 14.10.59 All surface finishes are considered acceptable. The temperature cycling reliability of solder joints on immersion Bi has been studied by Beigle and Guy with the use of LCCC68 component.59,64 Both works indicate that immersion Bi provides comparable temperature cycling performance to HASL. For instance, Beigle used thermal cycle condition from −55 to 125°C with a 0.5-h ramp and an additional 0.5 h at temperature for 1000 cycles. The continuity of each component was monitored during each cycle, and resistance over 600 Ω was considered open and as a component failure. Results indicate that within statistical significance, immersion Bi is comparable with HASL in reliability, as shown in Fig. 14.39.59 The wire bondability of immersion Bi is very poor. No adhesion can be registered in a pull test of gold wire-bonding attempt. One of the concerns about TABLE 14.10 Reflow Spread immersion Bi finish is sensitivity toward Performance of Various Surface Finishes Pb. When used with Sn-Pb solder alloys, the ternary eutectic alloy 8Sn-52Pb-40Bi Mean solder wetting distance (melting point 95°C) formed may cause Coating Not aged Steam-aged early failure and extensive porosity durBismuth 65.85 64.72 ing temperature cycling or service. The failure mechanism induced by the formaSilver 68.46 68.24 tion of ternary eutectic alloy 8Sn-52PbHASL 69.28 68.39 40Bi was elucidated by Mei et al. on OSP 67.86 66.19 eutectic Sn-Bi system.65

14.38

CHAPTER FOURTEEN

FIGURE 14.39 Solder joint reliability in temperature cycling of −55 to 125°C test using LCCC68 component soldered on various surface finishes.

14.7

Pd

Palladium (Pd) is an attractive, cost-effective alternative finish for printed wiring boards (PWBs) that is both solderable and wire bondable. Similar to gold, Pd is a noble metal; therefore, it is stable against many chemical reactions, such as oxidation. In addition, Pd exhibits several advantages over Au as a potential surface finish constituent: 1. Pd is cheaper than Au. 2. Pd exhibits a density 38 percent lower than Au (12.02 versus 19.32 g/cm3), thus further reduces the cost of Pd needed for surface finish applications. 3. Pd displays a tensile strength about 35 percent higher than Au. 4. Pd exhibits a hardness at 250 to 290 Vickers, about twice that of copper and three times that of gold, thus making it more suitable for contact purposes. 5. Pd dissolves in molten 60Sn-40Pb at a much lower rate than Au (about 0.01 versus 5 µm/s), thus it is less prone to contaminate the solder pot.66,67

14.7.1

ELECTROLYTIC Pd WITH OR WITHOUT IMMERSION Au

Electrolytic Pd or electrolytic Pd with Au flash provides a thin deposit on top of copper. The Pd is less than 0.5 µm, and is typically 0.25 µm in thickness. The Au flash is 0.025 µm in thickness.The fabrication process is described in the following subsection. Fabrication Process. The electrolytic Pd plating process is integrated with the PCB patterning process as follows: 1. 2. 3. 4. 5.

Cu plate Pd plate Resist strip Cu etch Solder mask application

14.39

LEAD-FREE SURFACE FINISHES

During the plating cycle, Pd is applied immediately after acid copper plating. The dwell time in the Pd is 1 to 2 min. After Pd plating, the photoresist is stripped and the boards are processed through the copper etcher, and finally the solder mask is applied. The Pd etch resist can then be activated for further processing if required. For instance, electroless Pd and/or immersion Au can be selectively applied, depending on the specific solderability and bonding requirements.68 Performance. The major advantage of a Pd finish is its use as an etch resist replacement for Sn-Pb. It reduces the manufacturing steps and the cycle time by reducing the plating time, and it eliminates the Sn-Pb stripping step. Other advantages provided include: ● ● ●

It is wire bondable. It is solderable. It has uniform thickness and excellent coplanarity, thus making it suitable for highdensity interconnect applications.

The solderability stability of a Pd finish against storage conditions is evaluated with steam and thermal aging. Table 14.11 shows the solderability test results of Pd against Ni/Au and Ni/Ag finishes.68 Apparently, Pd exhibits a superior solderability and stability. This is attributed to the low porosity of Pd versus that of Ni/Au or Ni/Ag. Applying a layer of Au flash on top of the Pd layer further improves the storage stability. Kakija et al. also reported that Pd and Pd-alloy electrodeposits preserve the integrity of the surface finish and provide good solderability by limiting porosity, inhibiting thermal diffusion, and increasing wetting speeds.69 However, it also has been reported that Pd may not always be a good diffusion barrier.Wang and Tu, at UCLA, noted that an intermetallic compound (IMC), which grows at a rate greater than 1 µm/s, has been observed in the liquid/solid reaction at 250°C between molten eutectic Sn-Pb solder and solid Pd. The intermetallic PdSn4 that is formed does not serve as a diffusion barrier between the reactants. Instead, it grows as lamellae into the molten solder, with the growth direction being normal to the liquid/solid interface. The molten solder between the lamellae serves as fast diffusion channels during the reaction. On the other hand, molten Sn reacts with Pd at a rate that is slower by one order of magnitude than Sn-Pb. The IMCs formed here grow as a diffusion barrier between the Sn and Pd.70 The bond strength of solder joints on a Pd finish is considerably lower than several other finishes. Ray et al. examined the pull strength of 50-mil-pitch, 20 I/O gullTABLE 14.11 Solderability of Pd Versus Ni/Au and Ni/Ag After Steam Aging and Thermal Aging* After Cu etch

After Cu etch, 85°C/85% SA,† 16 h

After Cu etch, 150°C TA,† 16 h

0.25 µm Pd/Cu laminate

99

96

96

0.025 µm Au/0.25 µm Pd/Cu laminate

99

99

98

1.25 µm Ag/1.25 µm Ni/Cu laminate

96

55

70

0.375 µm Au/1.25 µm Ni/Cu laminate

99

60

85

* All values are expressed as percentages. † SA: steam aging; TA: thermal aging.

14.40

CHAPTER FOURTEEN

FIGURE 14.40 Mechanical pull test data for 50-mil-pitch SOICs before and after 5000 thermal cycling (0 to 100°C, 3 cycles/h) using alloy 96.2Sn-2.5Ag-0.8Cu-0.5Sb (CASTIN). The component is 20 I/O gullwing-leaded SOIC.

wing-leaded small-outline integrated circuits (SOICs) before and after thermal cycling (0 to 100°C, 3 cycles/h) using a Pb-free alloy, 96.2 Sn-2.5Ag-0.8Cu-0.5Sb (CASTIN).71 Four surface finishes were compared: (1) ENIG (150 µin Ni/5 to 10 µin Au), (2) EN (150 µin)/electroless Pd (5 to 10 µin), (3) Pd (20 µin, or 0.5 µm) on copper, and (4) imidazole. Results indicate that the bond strength of the Pd surface finish is the lowest one among the four surface finishes, as shown in Fig. 14.40.71 This can be attributed to the formation of a large quantity of PdSn4 intermetallic. Similar to Au, the volume of intermetallics formed between Pd and Sn is significantly higher than that formed between Sn and other metals such as Cu or Ag. This is because the amount of Sn consumed for formation of intermetallics is much higher for Au (AuSn4) and Pd (PdSn4) than for Cu (Cu6Sn5 or Cu3Sn) and Ag (Ag3Sn). Here the Pd

TABLE 14.12 Pull Test Results of 1-mil Au Wire on Au-Flashed Electrolytic Pd Before and After Aging at 150°C for 64 h Ball bond minimum setting Force (g) Power (mW)

50 3.0

Ball bond maximum setting 50 9.9

Temp (°C)

120

120

Time (µs)

10

10

Pull force,

5.35

6.53

as plated (g) Std. deviation

1.69

0.21

Pull force,

6.38

6.29

1.24

0.53

64 h, 150°C (g) Std. deviation

LEAD-FREE SURFACE FINISHES

14.41

FIGURE 14.41 Mechanical pull test data for 256 I/O, 4-mm-pitch gullwing-leaded PQFPs before and after thermal cycling using alloy 96.2Sn-2.5Ag-0.8Cu-).5Sb (CASTIN). The thermal cycling condition is 0 to 100°C, 3 cycles/h.

thickness (20 µin) in the Pd finish is thicker than the Au thickness (5 to 10 µin) in ENIG or the Pd thickness (5 to 10 µin) in Ni/Pd, thus causing a greater deterioration in bond strength. Additional cycling treatment does not cause further deterioration in bond strength for the Pd finish, suggesting that the Pd finish may be a viable option as a surface finish. Similar tests conducted using 256 I/O 0.4-mm-pitch plastic quad flat pack (PQFP) also shows that the Pd finish exhibits the lowest pull strength. However, treatment with 2500 thermal cycles results in a slight decrease in bond strength for both Pd and Ni/Pd systems, as shown in Fig. 14.41.71 Presence of a large quantity of PdSn4 intermetallics can be seen easily. The wire bondability of Pd with Au flash was studied with the use of a 1-mil Au wire-and-ball-bonding process. Results indicate that the wire bondability is maintained after thermal aging at 150°C for 64 h, as shown in Table 14.12.68

14.42

CHAPTER FOURTEEN

14.7.2 ELECTROLESS (AUTOCATALYTIC) Pd WITH OR WITHOUT IMMERSION Au An electroless Pd coating process is essentially an autocatalytic process with or without an immersion Au flash (<1 µin, or 0.025 µm). The thickness of Pd is dependent on the applications. For soldering purposes, a Pd thickness of 3 to 9 µin (0.075 to 0.225 µm), often at 4 to 6 µin (0.1 to 0.15 µm), is employed. For wire-bonding applications, the Pd thickness is about 0.6 µm. Fabrication Process. Milad and Roberts, from Atotech USA, Inc., reported that the fabrication process for PD-Tech PC, a trade name for their electroless Pd finish product, consists of the following four steps67: 1. 2. 3. 4.

Acid clean Microetch Activation Electroless Pd

The acid clean and microetch steps are required to provide a properly treated copper surface. The activator is formulated to be selective to copper only. The activation step is an immersion process and produces a thin layer of Pd with a thickness less than 1 µin via an exchange reaction with the copper. This immersion process is self-limiting and takes 3 to 5 min at 40°C for complete coverage in a bath buffered in the pH range of 1.1 to 1.4. The electroless Pd deposition step is linear over time, regardless of the dwell period.The deposition of a pure Pd is assured through the use of an exclusive reducing agent, with the Pd concentration of the solution maintained at around 1.0 g/L. The bath temperature is typically maintained between 60 and 70°C, while the pH of the process is maintained within a range of 5.3 to 5.7. The deposition rate of Pd is affected by bath temperature and is typically in the range of 1.0 to 2.5 µin/min. The Pd in the electroless bath will only deposit on a Pd metal surface formed in the activation step via the immersion Pd process. In the diffusion layer, adsorbed hydrogen on the Pd surface reduces the complexed Pd2+ in the electroless bath to the metallic state, which deposits and subsequently adsorbs additional hydrogen generated by the reducing agent. As a result, the reaction becomes autocatalytic and continues linearly. The process is maintained by control of the Pd concentration in the activation bath and the pH of the electroless Pd bath. Replenishment of the Pd in the electroless bath is determined by the concentration in the activation stage. Performance. Pd finish serves as a sacrificial layer. Pure Pd at a thickness of 4 to 6 µin provides a highly solderable finish, comparable with that of HASL. During wave or reflow soldering, the Pd layer is dissolved into the solder and is held in suspension. At the solder–base metal interface, the intermetallic that is formed is a coppertin intermetallic.67 The solderability performance of Pd is comparable with Au-Ni, but the advantage is primarily shelf life. Pd finishes perform better after accelerated aging tests than do those with Au/Ni. This is because Pd acts as a thermal/migration/diffusion barrier, whereas Au or Ag allows migration of Ni or Cu through to the surface. Since Cu will not readily diffuse through Pd, Pd can be applied directly over Cu and protect it from oxidation. Seto et al. studied the use of an electroless Pd surface finish for soft-touch switches and high-density SMT assemblies in a joint program between Chrysler Huntsville Electronics and Photocircuits Corporation.72 The Pd thickness employed ranges from 3 to 9 µin (0.075 to 0.225 µm). Surface insulation

14.43

LEAD-FREE SURFACE FINISHES

TABLE 14.13 Results of Tests Conducted at Chrysler on Pd-Finished PWB Assemblies Test performed

Results

Key contact resistance

Passed

After 22,000 cycles

Comments

Life test

Passed

Underhood environment; assembled by reflow

Thermal cycle

Passed

−40–105°C

Process sensitivity

Good

PWBs with Pd thickness extremes processed at high, nominal, and low reflow temperature profiles

resistance on Pd-finished PWBs was reported to be much lower than for an HASL product. Some other test results are shown in Table 14.13.72 Results indicate that the requirements of Chrysler are met for each test listed. Since April 1996, a running total of more than 2.5 million assemblies have been built at Chrysler, with an average production rate of 7500 assemblies per day. The inprocess PWB defect rate at the assembly level is reported to be less than 30 ppm. Pd has been qualified for Chrysler reflow processes for new SMT products employing double-sided, two-pass convection reflow. Electroless Pd with a thickness of 0.6 µm (24 µin) with a Au flash (<0.025 µm) was compared with Ni/Pd for wire-bonding performance. In the second finish, EN was deposited to a thickness of 5.0 µm (200 µin) followed by an electroless Pd deposit of 0.2 µm (8 µin) also with a Au flash. Both finishes were then subjected to Au (thermosonic) and Al (ultrasonic) wire bonding. Based on the test results, Milad and Roberts concluded that Pd over Cu with a Au flash or a Ni/Pd/Au flash both offer excellent Au wire-bonding properties. For Al bonding, similar results were only achieved for Ni/Pd/Au flash. Al wire bonding to Pd/Au flash, although possible, is limited due to a very narrow operating range of optimal bonding parameters.67

14.8

ELECTROLESS Ni/Pd/(Au FLASH)

Electroless Ni/Pd with or without an overcoat of immersion Au is a cheaper alternative to ENIG (Ni/Au). A thin layer of Pd on copper is sufficient for delivering a good solderable finish. However, in cases where Au wire bonding is required, an undercoat of Ni will be required for best performance. For soldering and Al wire-bonding applications, the thickness of an EN underlayer is typically 100 to 200 µin (2.5 to 5.0 µm). On top of that is the electroless Pd layer, with a thickness of 5 to 10 µin (0.125 to 0.25 µm), and more commonly 6 to 8 µin (0.15 to 0.2 µm).The overcoat immersion Au flash typically is less than 1 µin (0.025 µm). If the Pd layer is increased to 15.0 to 20.0 µin (0.375 to 0.50 µm), the surface finish is then solderable and gold-wirebondable. Fabrication Process. The EN process is the same as that described in Sec. 14.4.2. After the EN process, the surface to be Pd plated is catalyzed with an immersion deposit of Pd before electroless Pd plating can proceed. This catalyzation restricts the deposit to the metallic substrate without extraneous plating on the mask or laminate.

14.44

CHAPTER FOURTEEN

Electroless Pd is an autocatalytic process that involves using a chemical reducing agent to plate palladium metal out of solution. The reducing agent varies and may incorporate other elements in the deposit, such as phosphorus if sodium hypophosphite is the reducing agent. The thickness of the autocatalytic deposit is not selflimiting and will increase continuously as long as the bath chemistry balance and operating parameter are maintained properly. The Pd bath operates under relatively mild conditions, with a pH in the range of 4.0 to 6.0 and the temperature not exceeding 65°C.67 Performance. If properly fabricated, Ni/Pd preserves solderability better than Ni/Au, since Pd is inherently less porous than Au. This makes Ni migration less likely, thus giving a pure Pd surface on which to solder. Stacy et al. studied the solderability of EN/Pd with and without Au flash before and after steam aging (SA) with the use of three commercial fluxes. Results indicate that, for both finishes, no degradation in solderability can be discerned after 8 h of SA, as shown in Table 14.14.68 However, Toben and Kanzler reported that the use of a Ni underlayer compromises solderability somewhat for applications where both soldering and wire bonding are specified on the same board.73 The wire bondability of EN/Pd/Au flash is well preserved against storage condition. Table 14.15 shows the pull test results of 1-mil Au wire on EN/Pd/Au flash. No deterioration of the pull force can be discerned after 8 h of treatment at 85°C/85% RH.68 However, Pd dissolves much less readily into tin alloy solder than does Au. This requires that the Pd layer be extremely thin to prevent the formation of a weak interface layer between the nickel and solder. Melton and Fuerhaupter suggested a Pd thickness of 1 to 2 µin (0.025 to 0.05 µm). This thin layer is susceptible to mechanical damage from scratches and electrical test probes and can cause the Ni underlayer to be exposed, which is detrimental to the solderability of the Pd surface.11 Currently, the electroless Pd layer is about 6 to 8 µin (0.15 to 0.2 µm) in thickness. The mechanical pull test data for 50-mil-pitch SOICs on EN/Pd before and after 5000 thermal cycling (0 to 100°C, 3 cycles/h) indicate that the formation of a weak Pd interface layer between solder and nickel may not be an issue, as shown in Fig. 14.40. Here the alloy used is 96.2 Sn-2.5Ag-0.8Cu-0.5Sb (CASTIN), and the component is 20 I/O gullwing-leaded SOIC.71 TABLE 14.14 Solderability of EN/Pd with and Without Au Flash Before and After SA* K-135 Rosin No. Act.

K-951 MA

K-1515 Act. Rosin

As-plated electroless Pd/EN

95

98

98

As-plated GF/electroless Pd/EN

97

99

97

8 h SA electroless Pd/EN

95

95

97

8 h SA GF/electroless Pd/EN

97

98

98

Flux type

* All values are expressed as percentages.

14.45

LEAD-FREE SURFACE FINISHES

TABLE 14.15 Pull Test Results of 1-mil Au Wire on EN/Pd/Au Flash Before and After 8 h of Treatment at 85°C/85% RH Mean load (g)

Deviation (g)

GF eP2-EN,* as plated

5.21

1.09

GF eP2-EN, 8 h SA

6.45

0.93

Finish

* eP2: electroless Pd on immersion Pd; GF: Au flash.

Pd tends to react with organic molecules in the atmosphere to form an insulative, nonsolderable organic film over long periods of storage through catalytic reaction.11 Other typical problems encountered with Pd plating include: ●

●

●

●

Inability to visually discern Pd from Ni if plating over Ni, which may lead to shipping parts that have no Pd on them. Poor bath maintenance practice can lead to Pd deposits that won’t solder or wirebond. Poor activation of surface to be plated with Pd, hence delamination of Pd deposit occurs. Unclean rinses and poor handling after Pd plating causes solderability and wirebonding failures.

14.9 14.9.1

Ni/Pd(X) ELECTROLYTIC Ni/PdCo/Au FLASH

This surface finish, developed by Lucent Technology, is composed of a 100-µin nickel bottom layer, a 10-µin 80Pd-20Co (w/w) middle layer, and a 2- to 3-µin Au top layer. All three layers are electrolytically plated. Ludwig et al. studied the solder paste reflow soldering-related performance, and the results are compared with OSP, Ni/Au, and Ni/Sn. Four lead-free solders [Sn42-Bi58 (Sn-Bi), Sn91.8-Bi4.8-Ag3.4 (Sn-Bi-Ag), Sn95.5-Ag3.8-Cu0.7 (Sn-Ag-Cu), and Sn96.5-Ag3.5 (Sn-Ag)] were used, with eutectic Sn63-Pb37 (Sn-Pb) also included as a reference. Also included in the test matrix are five fluxes, three reflow profiles, two reflow atmospheres, and two aging treatments. The study concluded that, overall, the Ni/PdCo/Au is poor in wettability (see Fig. 14.42), fairly low in lap shear strength (see Fig. 14.43), and high in voiding (see Fig. 14.44). However, it is fairly stable, and its soldering performance is not sensitive to profile length, reflow atmosphere, aging treatment, and flux chemistry. It does seem to be sensitive to Bi-containing alloy in terms of voiding and lap shear strength.74

14.9.2

ELECTROLESS Ni/PdNi/Au FLASH

Electroless PdNi alloy with a Au flash over EN is the preferred contact metallurgy, reported by Yeung and Nakamura from Hitachi Micro Systems.75 It is said to provide

14.46

CHAPTER FOURTEEN

FIGURE 14.42 Effect of surface finish on wetting.

cost savings, extend contact life, and requires no organic lubricants. It also enhances corrosion resistance. Using this surface finish on contact pads enables the design of high-speed, high-density, small form-factor memory modules/cards with improved reliability, superior electrical characteristics, and enhanced resistance to corrosion compared with traditional electrolytic plating.75

14.10

Sn

Tin (Sn) is a very attractive option as a lead-free surface finish. Merits of Sn include: 1. It’s lead free. 2. It has good solderability.

FIGURE 14.43 Effect of surface finish on bond strength.

LEAD-FREE SURFACE FINISHES

14.47

FIGURE 14.44 Effect of surface finish on voiding.

3. 4. 5. 6. 7. 8. 9. 10. 11. 12.

It has good corrosion resistivity. It has reasonably good electrical conductivity. It has good mechanical strength. It is nontoxic. It is abundant in supply and low in cost. It is compatible with virtually all solders, particularly Sn-bearing alloys. It has a long history, with reliability data available. It has the option of being a metal etch resist. It is fusible, if needed. It provides a flat surface contour.

However, the following three concerns have to be addressed before full acceptance is possible: 1. Tin whisker 2. Tin pest 3. Sliver

14.10.1

ELECTROLYTIC Sn

Several decades ago, electroplated tin was used as a final surface finish. It was abandoned later as final finish due to problems with current distribution thickness and deposit stability, besides the whisker and tin pest problems.76 Today, improved versions of electrolytic tin processes are reintroduced as an option for lead-free surface finishes, mainly driven by the global lead-free soldering move. The thickness of a tin layer may vary from 3 µm for the SnTech Sn Satin Bright (SB) process to 7.5 µm to as much as 8 to 15 µm, depending on the process and chemistry.76–78

14.48

CHAPTER FOURTEEN

Fabrication Process. There is a wide variety of plating chemistry for electroplating tin in the electronics industry. Baths using pyrophosphate, potassium stannate, sodium stannate, and phenol sulfonic acid have been used in the past. However, they may not be compatible with the aqueous developing photo resists used for pattern plating. The most commonly used bath chemistries are the stannous sulfate, stannous fluoroborate, and methanesulfonic acid plating baths.79 Newer plating solutions (e.g., the neutral stannous sulfate/gluconate plating) may also be used. The stannous sulfate bath is the lowest in cost and it is cheaper than the tin-lead baths that are presently used, although the cost of the tin anodes is considerably more than the cost of 60Sn-40Pb anodes.78 The stannous sulfate plating solution is susceptible to reaction with the atmosphere to form stannic oxide.The stannic oxide codeposits with the tin and will cause grainy-appearing solder joints and dewetting at TABLE 14.16 Plating Bath soldering. Stannic oxide is a very fine-grained Producing Fine-Grained Tin Plate white crystal and extremely difficult to filter from the plating solution, unless a pertinent coagulant Item Condition is used for filtering the stannic oxide and clarifying the plating bath. Additives for grain refining Sn content 45 g/L and leveling often are available. Examples of a Acid content 200 mL/L plating bath producing a fine-grained pure-tin Additive 105 mL/L plate are given in Table 14.16. Figure 14.45 shows Temperature 40°C the topology of the electroplated pure tin obtained accordingly.80 Current density 20 Å/dm2

FIGURE 14.45 Topology of electroplated pure tin obtained with the use of a plating bath, as shown in Table 14.16.

14.49

LEAD-FREE SURFACE FINISHES

TABLE 14.17 Tin Plating Bath Produces Large Polygonized Grains Typical

Range

Sn as metal, g/L

Feature

40

10–100

70% methane sulfonic acid (MSA), mL/L

200

150–250

Surfactant, mL/L

40

20–60

Grain refiner

10

8–15

10–250

10–1000

Current density, ASF Agitation

Low to medium

Low to vigorous

Temperature, °C

55

50–60

Anode/cathode ratio

1:1

1:1–3:1

Zhang noted that a tin whisker can be depressed by tin coatings with large, wellpolygonized grains and a very low inclusion of organics, and reported a tin-plating chemistry that produces such, as shown in Table 14.17.77,81 Figure 14.46 shows the topology of the electroplated tin with large polygonized grains.77 For most operations the plating is semimatte to bright finish.The bright and semibright finishes are harder than the matte finishes, offer good storage life, and are resistant to fingerprinting. Unfused tin is preferable, if a flat surface is required for surface mount attachment. Figure 14.47 shows the roughness of a surface finish with

FIGURE 14.46 Optical micrograph of electroplated tin with large polygonized grains obtained with the use of a plating bath, as shown in Table 14.17.

14.50

CHAPTER FOURTEEN

FIGURE 14.47 Surface roughness of electroplated tin with large polygonized grains versus various treatments.

various treatments. Note that the reflow process deteriorates flatness only when a flux is used.77 Hinton estimated that the cost of tin plating on copper conductors is about equivalent to the hot-air-solder-level process, and it is slightly cheaper than the tin-lead pattern plating process, if the tin sulfate bath is used instead of the fluoroborate solutions.78 Performance. The tin deposit is highly pliable and ductile.76 The growth rate of the tin-copper IMCs on tin-coated copper is reported to be very nearly the same as 60Sn-40Pb solder-coated copper, therefore should not be a major issue for electrolytic tin finish.82,83 This minor effect of 100Sn on Cu-Sn intermetallics formation rate is further confirmed by Hunt. The data reported by Hunt indicate that although higher tin content results in a greater intermetallics formation rate, the difference between 100Sn and 60Sn-40Pb is less than 20 percent at 155°C.83 Zhang reported that, for electroplated pure tin, the deposit consistency in terms of reflectance, melting enthalpy, surface morphology, solderability, and SA resistance are very good up to at least 2.5 bath turnover.77 For large-grained coating, SA (95°C, 95% RH) was not sufficient to induce whiskers. A severe bending test (ASTM standard B489-85, bend coatings around a 0.5mm-diameter mandrel) did induce whiskers, but whiskers were only observed at tensile stressed areas. Four years later, the nonstressed area is still free from whiskers.

14.10.2

IMMERSION Sn

Immersion Sn has been in existence for many years, with only limited use. It is often used for low-cost products and has a process advantage since it is applied after the etching process of a PCB is complete. The old processes have a short storage life, from a few days to a few months. New processes, such as immersion white tin or flat solderable tin (FST), made considerable improvement in shelf life.76,84 The typical thickness is approximately 1 µm. Immersion white tin was defined by IBM in the 1980s, referring to an immersion tin coating that would have long-term solderable

LEAD-FREE SURFACE FINISHES

14.51

finish applications. This immersion white tin structure contains other properties that make it suitable for other production uses in fabricating PWBs. On the other hand, IBM used the term immersion gray tin to define an immersion tin coating that did not meet solderability requirements.76 Fabrication Process. The FST fabrication process is as follows84,85: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

Acid cleaner, 49°C, 4 min Cascade rinse, ambient Persulfate microetch, 0.75 to 1.0 µm Cu, 27°C Cascade rinse, ambient Sulfuric dip, ambient Tin module, 66°C, 8 min Warm rinse, 43°C, 1 min Cascade rinse Hot-air drying, ambient Finish

The tin is applied as a stannous sulfate or chloride solution, and a displacement reaction occurs with the copper. Since copper (+0.342 V) is more positive in electrochemical potential than Sn (−0.138 V), thiourea is used to drive the reverse potential needed for Sn to replace Cu as a deposit.The basic reaction is Sn2+ + Cu → Cu2+ + Sn. The bath usually contains a stannous halide and thiourea, and the tin is deposited on the surface of the copper. The reaction is self-limiting and stops as soon as the tin coating prevents any further transfer of copper into the solution. As a result, the finishes are thin and are on the order of 0.1 to 1.5 µm, depending on concentration, temperature, and porosity of the deposit. The immersion tin formulations often are modified to provide autocatalytic deposition of the metal to supplement the immersion deposit thickness. The immersion tin process will also codeposit copper with the immersion tin coating as the bath is used and as the copper concentration increases. As the copper concentration in the bath increases, the solderability of the board decreases and the tin coating thickness decreases.78 The modified immersion tin process incorporates an organometallic complex, which suppresses Cu-Sn intermetallics, surface oxidation, and whiskering. The immersion white tin process is similar to the FST process, as shown in the following76: 1. 2. 3. 4. 5. 6. 7. 8.

PC5009 cleaner. 10 percent, 2 to 4 min at 29 to 43°C for copper cleaning Water rinse. 1 to 2 min Acidic surface conditioner CirEtch 100 microetch. 1 lb/gal, 30 to 60 s, 24 to 29°C Water rinse. 1 to 2 min OV-4 predip. 25 percent, 1 to 2 min, 16 to 32°C OA-8 immersion tin solution. 100 percent, 6 to 12 min, 61 to 71°C Water rinse (warm). 2 to 4 min Water rinse. 1 to 2 min

Total operating cost should be comparable if not less than hot-air-solder-leveling costs. Immersion white tin is also used as an ammoniacal etch resist.

14.52

CHAPTER FOURTEEN

Performance. Earlier-immersion tin is more prone to oxidation. Ray et al., at AT&T, studied the influence of temperature and humidity on the wettability of immersion tin-coated PWBs.86 Exposure to temperature and humidity was varied from near ambient (35°C/85% RH) to harsh (SA). A minimum thickness of about 1.5 µm was reported to be critical for assembly operations involving multiple thermal excursions. Formation of Cu-Sn IMCs at the copper-tin interface in the immersion tin finish does not adversely affect the soldering performance, as long as the IMC phase is protected by a tin surface layer. Immersion tin finishes are relatively stable to thermal exposure, but oxidized readily under humid conditions and resulted in solderability degradation. An electroless copper substrate caused significantly more intermetallic formation, and consequently resulted in poor solderability even under moderate temperature and humidity conditions. Immersion white tin provided considerable improvement against oxidation resistance. Edgar studied the effect of aging conditions on the oxide thickness TABLE 14.18 Effect of Aging Condition on the Oxide Thickness Formed on Immersion Tin and the Remaining Tin Layer Thickness Aging treatment

Surface analysis

White tin

Immersion tin 1

Immersion tin 2

Immersion tin 3

Nonaged

Average thickness of Sn coating (µm)

0.99

1.01

0.98

1.05

Stannous oxide (Å)

30

32

28

32

Stannic oxide (Å)

3

4

7

5

6 months’ aging

155°C for 4h

Steam aging 8h

One-pass air reflow

Three-pass air reflow

Average thickness of Sn coating (µm)

0.95

Not tested

0.79

0.88

Stannous oxide (Å)

28

Not tested

30

35

Stannic oxide (Å)

3

Not tested

5

9

0.05

ND

Average thickness of Sn coating (µm)

0.49

ND

Stannous oxide (Å)

13

Oxidized IMC on surface

17

Oxidized IMC on surface

Stannic oxide (Å)

4

Oxidized IMC on surface

7

Oxidized IMC on surface

Average thickness of Sn coating (µm)

0.74

0.36

0.59

0.55

Stannous oxide (Å)

6

3

23

12

Stannic oxide (Å)

3

4

3

7

Average thickness of Sn coating (µm)

0.63

0.13

0.54

0.28

Stannous oxide (Å)

10

33

45

39

Stannic oxide (Å)

2

8

14

15

Average thickness of Sn coating (µm)

0.34

ND

0.05

ND

Stannous oxide (Å)

12

113

67

101

Stannic oxide (Å)

3

39

12

44

LEAD-FREE SURFACE FINISHES

14.53

formed on immersion tin and the remaining tin layer thickness with the use of sequential electrochemical reaction analysis (SERA). White tin was evaluated against three conventional immersion gray tin finishes, with results shown in Table 14.18.76 Aging consumes Sn and results in a decrease in the Sn layer. Immersion gray tin finishes show a more rapid decrease in tin thickness than immersion white tin. In testing various aging methods, it was noted that the tin surface stability was not determined by the original thickness of the coating. Deposit characteristics of tin influenced the stability of the coating. The wettability of the surface of aged coatings was tested by stenciling solder paste with a 1⁄4-in-diameter circle pattern. The solder paste spread on the coatings was measured and percentage comparison was noted. Results indicate that immersion white tin outperformed all three immersion gray tin finishes and is quite comparable with HASL for aged surface finishes, as shown in Fig. 14.48.76 The SERA can identify the coating’s thickness, but it does not identify the porosity of the coating. When the immersion tin coatings are aged at 155°C for 4 h and compared using SEM, the surface characteristic observed helps to explain the solderability results. The immersion gray tin has a honeycomb pattern that is not seen with an immersion white tin. Oxygen and moisture penetrate the surface and oxidize the copper. It is this porosity that allows for the failure of the coatings under aging conditions.An immersion white tin structure is completely different from immersion gray tin and allows for long-term stability and solderability. In Fig. 14.48, the wettability of immersion tin 1 and immersion tin 3 is extremely poor for samples conditioned at 155°C and 4 h. In Table 14.18 it can be seen that for samples treated with the same conditions, both finishes exhibit no detectable tin layer. Furthermore, oxidized intermetallics are present at the surface. This close correlation strongly indicates that oxidized intermetallics are not wettable. Obviously, the effect of oxidized intermetallics on wettability is much greater than that of solder oxide formed on the top of finishes. Ormerod studied the oxidation rate of modified immersion Sn (100Sn) compared with 80Sn-20Pb and 60Sn-40Pb. Results indicate that the oxidation rate is not sensitive to the Sn content of the surface finishes, as shown in Fig. 14.49.84 It is interesting to note that the effect of oxide thickness on wettability is fairly moderate. For instance, the wetting force of a 60Sn-40Pb surface finish decreases rapidly at first with increasing oxide thickness, then slowly at an oxide thickness that is greater than 4 nm.84

FIGURE 14.48 Effect of surface finish types and aging conditions on the solder paste spread percentage of surface finishes.

14.54

CHAPTER FOURTEEN

FIGURE 14.49 Effect of temperature and alloy composition of surface finishes on the oxidation rate.

The effect of temperature on the intermetallics formation rate of immersion tin (100Sn) on Cu is shown in Fig. 14.50.84 Besides the intermetallic thickness increasing with increasing temperature, the type of intermetallics may also alter with temperature. At higher temperatures another intermetallic species, Cu3Sn (ε phase), is formed below the Cu6Sn5 (η phase) material. These intermetallics consume the amount of fusible tin, and multiple heat cycles quickly degrade any remaining solderability. Since the immersion tin layer is typically 1 µm, care should be taken to ensure that the tin layer is not depleted by the formation of Cu-Sn intermetallics prior to assembly.

FIGURE 14.50 The effect of temperature on the intermetallic formation rate of immersion tin (100Sn) on Cu.

LEAD-FREE SURFACE FINISHES

14.55

FIGURE 14.51 Flat solderable tin ionic residue after processing compared with bare Cu, OSP, HASL, and Ni/Au. The readings are expressed as chloride equivalents based on conductivity measurement.

For FST finishes, the effect of the aging treatment on solderability is similar to that of immersion white tin, although the morphology of FST distinctly differs from that of white tin.The former exhibits a large round-grained texture influenced by the organics, while the latter exhibits a fine-grained texture. Raising the temperature to increase the deposit thickness will also increase the grain size. As a comparison, the conventional tin shows a characteristic angular crystal structure. Ormerod also reported that FST displays a very low ionics level after processing, as shown in Fig. 14.51.84 Here the FST ionics reading is comparable with Ni/Au, and is one order of magnitude lower than HASL. The IPC-TM 650# 2.6.14 electromigration performance of FST is comparable with bare copper, OSP, Ni/Au, and is considerably higher than HASL. Applications of the Immersion Sn. Applications of immersion Sn include the following: ● As a low-cost solderable metallic finish for non-wire-bonded applications ● As a replacement for OSPs as a more robust finish ● As a planar replacement for HASL ● As a lead eliminator ● As a solderable substrate for solid solder deposit technology.

14.11

ELECTROLYTIC Ni/Sn

Electrolytic tin with an electrolytic nickel underlayer is a low-cost alternative for precious-metal finishes, such as Ni-Au or Ni-Pd. Tin has an excellent solderability, probably only next to Sn-Pb finishes. Nickel is often used as a migration barrier

14.56

CHAPTER FOURTEEN

under the tin to prevent copper from forming a thick, brittle layer of intermetallics with solder. The cost of plated tin is approximately the same as HASL. The cost of the tin plate over nickel is more than the HASL process, especially if the copper, nickel, and tin-plating processes are not in the same continuous plating system. When comparing it with any of the noble metal finishes, tin over nickel will be the least expensive finish. The thickness of the Ni/Sn finish is plating chemistry and process dependent. For instance, Hinton, at Hinton PWB Engineering, reported a semimatte to bright tin finish with 8 to 15 µm thickness on top of the nickel underlayer (1 to 2 µm).78 On the other hand, Ludwig et al., at Lucent, reported a satin-bright tin (3 µm) electrolytically plated on a 2.5-µm nickel layer, which is electrolytically plated on the base metal copper.47 Melton and Fuerhaupter considered the typical electrolytic tin layer to be 7.5 to 10 µm in thickness.11 Fabrication Process. The fabrication process of EN itself can be described as follows, and it is the same as that in Sec. 14.4.135: 1. Use the cleaner to clean the copper surface. 2. Etch the copper surface. 3. Plate the nickel at 52 to 57°C. The typical electrolytic Sn plating process has been reviewed by Price.87 Some examples can be found in Sec. 14.10.1. Copper contamination in the plating predips, which precede the tin-plating bath, may cause depositions on the nickel. This copper deposit may also cause dewetting of the plated surface when soldered. All processes between the nickel bath and the tin bath (e.g., transport, rinse, and preplate clean dwell times) should be as short as possible to prevent the nickel from being passivated and, as a result, being dewetted at soldering. The nickel underplate is often plated from a low-stress nickel sulfamate chemistry. As discussed earlier, a 1- to 2-µm thickness of nickel is commonly applied in order to act as a barrier plate and etch resist. When a tin finish is required on only the solderable lands, a second layer of photoresist is applied after the nickel pattern plating operation. The second image allows for tin plate only on the lands that are to be soldered and is known as the Santa Clara process.Assembled printed boards made by the Santa Clara process will have all of the high-purity electrodeposited tin plating alloyed with lead, antimony, or other tin whisker and α-tin-inhibiting metals during the soldering process, thus reducing the chances of having those problems. Performance. The tin layer in the satin-bright tin process comprises large grains, with organic inclusion less than 0.004 w/w %, and exhibits the lowest propensity for tin whisker development.47 The performance in reflow wetting, lap shear strength, and voiding is shown in Figs. 14.42 through 14.44, respectively. In general, this electrolytic satin-bright tin Ni-Sn by Lucent, although being sensitive to aging (see Fig. 14.52), reflow atmosphere (see Fig. 14.53), solder alloy type (see Fig. 14.54), and variation in flux chemistry (see Fig. 14.55), it is the highest in wettability, one of the highest in lap shear strength, and the lowest in voiding.47 It performs better under long profile. The high sensitivity may be attributed to the relatively high reactivity of tin. Under most instances, the soldering performance is comparable with or better than OSP and Ni-Au.

LEAD-FREE SURFACE FINISHES

FIGURE 14.52 Effect of aging on wetting of satin-bright tin on nickel. Aging was regulated by sending the substrates through a Btu furnace 0 (aging 0) and 1 (aging 2) time using a medium-reflow atmosphere, 245°C peak temperature, and air reflow atmosphere. Aging 2 subjected the coupon to an 85°C/85% RH environment for 24 h prior to soldering.

FIGURE 14.53 Effect of reflow atmosphere on wetting of various surface finishes. A ratio value greater than 1 indicates a positive effect of nitrogen. Use of nitrogen provides a better spread for the Ni-Sn system, but a negligible effect for the remaining three systems.

14.57

14.58

CHAPTER FOURTEEN

FIGURE 14.54 Effect of solder alloy on wetting. Sn-Pb solder generally wets better than the Pb-free alloys. Most of the Pbfree alloys are comparable in wetting, except that Sn-Bi displays an exceptionally high spread for the Ni-Sn system. Overall, NiSn is more sensitive to alloy type than other surface finishes.

FIGURE 14.55 Effect of flux chemistry on wetting for a system with Sn-Pb alloy, medium profile, air reflow, and no aging treatment. Both Ni-Sn and OSP are sensitive to the variation in flux type. The sensitivity toward flux type can be ranked as follows: Ni-Sn > OSP > Ni-Au, Ni-PdCo-Au.

LEAD-FREE SURFACE FINISHES

14.12

14.59

Sn-Bi

Sn-Bi alloy is attractive as a surface finish because it is lead-free, has good solderability, is low-cost, and has stability against environment. It is one of the four leadfree alloys—Bi-Sn, In-Sn, Ag-Sn, and Ag-Sb—recommended by the Occupational Safety and Health Administration as a replacement for Sn-Pb, based on their relative safety in the manufacturing environment. It is also one of three solder alloys— Sn-Ag, Sn-Bi, and Sn-Ag-Bi—recommended by the National Center for Manufacturing Sciences as a lead-free solder alloy option. The tin-bismuth alloy has already been used in PCB manufacturing as an etch resist.88 However, Bi-containing finish is sensitive to lead contamination due to the formation of a low-melting (95°C) ternary eutectic alloy 52Bi-30Pb-18Sn, thus compromising the reliability of solder joints.65 Another concern is the potential of having fillet lifting. Both phenomena will be discussed in detail in Chap. 16.

14.12.1

IMMERSION Sn-Bi ALLOY

Motorola has developed an immersion plating process to deposit approximately a 1.0-µm thickness of 70Sn-30Bi alloy onto copper surface mount pads as a PCB surface finish.11,89,90 Fabrication Process. The immersion tin-bismuth process is relatively simple to perform. A mild etch should be given to the copper surfaces prior to plating with tin-bismuth, and a rinse should follow the actual tin-bismuth plating process. The plating reaction can be performed by dipping in a stationary tank, or spraying/ flooding in a horizontal conveyorized system. The chemistry is based on salts of methane sulfonic acid. The immersion plating process deposits approximately 1.0 µm of a 70/30 Sn-Bi alloy in 1 min at 30°C. As other immersion plating processes, this is self-limiting, and the plating reaction stops once the maximum thickness is reached. Performance. The finish has a matte gray appearance, and thus it can be easily distinguished from the rest of the PCB by automated optical assembly and inspection equipment. Melton, at Motorola, conducted various tests on PCBs coated with the immersion tin-bismuth surface finish. Overall, this surface finish passed all of the tests with similar results as tin-lead. Capital costs are expected to be low, since the process is immersion plating. Material costs are low due to the thin thickness to be formed. The cost per square foot of deposited Sn-Bi alloy is estimated to be slightly more than that charged for OSP surface finishes.

14.12.2

ELECTROLYTIC Sn-Bi ALLOY

The tin-bismuth alloy has already been used in PCB manufacturing as an etch resist.91 With the addition of Bi, the chance of tin whiskering is highly reduced. One of the features of this electroplated tin alloy is the prevention of tin whiskers. Therefore, M&T marketed one tin electroplating chemical as a whisker-free tin formulation, which contains a small amount of bismuth that is codeposited with the tin.92

14.60

CHAPTER FOURTEEN

TABLE 14.19 Properties of 63Sn-37Pb and 99Sn-1Cu95 Property

63Sn-37Pb

Melting point (°C) Density (g/ml) Thermal conductivity (W/m⋅K) Cost per kg (bar) Cost per kg (paste)

227

8.4

7.31

56.61

65.73

Electrical conductivity (M mho/cm)

14.13

99Sn-1Cu

183

8.73

9.52

$0.85

$1.03

$140.8

$163.2

Sn-Cu (HASL)

99Sn-1Cu is attractive as a board surface finish due to promising solder alloy performance. Table 14.19 shows comparison between eutectic Sn-Pb and eutectic SnCu. Through their 1991 to 1994 study, Notel concluded that Sn-Ag and Sn-Cu are the most promising solder alloys among 200 alloy candidates. In the 1994–1995 lab study, Sn-Cu HASL was selected as the most promising lead-free board finish. In 1997, vertical Sn-Cu HASL was tried, with encouraging results. In 1998, further development of the Sn-Cu HASL board finish was conducted, including a horizontal HASL process.93 Fabrication Process. The process condition for manufacturing Sn-Cu HASL is shown in Table 14.20.94 Also shown is the process for Sn-Pb HASL as a comparison. Performance. The performance of a 99Sn-1Cu HASL surface finish was evaluated by comparing the pull strengths of solder joints made on various surface finishes, as shown in Table 14.21.93 The components used were plastic leaded chip carrier with Sn-Pb surface finish. Results indicate that horizontal Sn-Cu HASL is comparable with horizontal Sn-Pb HASL, Entek 106, and immersion Ag (Alpha-Level), and is better than Ni-Au and vertical Sn-Pb HASL, thus is a very viable option as a board surface finish. It should be noted that the HASL process is pertinent for conventional SMT assembly, but inadequate for fine-pitch SMT applications, due to uneven

TABLE 14.20 Comparison of Process Conditions Between 63Sn37Pb and 99Sn-1Cu in HASL Process95 Parameter

63Sn-37Pb

99Sn-1Cu

Bath temperature (°C)

250

280

Air knife temperature (°C)

250

280

Oil temperature (°C)

230

255

Air heat exchanger

250

300

Lower

Higher

150

200

Air pressure PCB preheat (°C)

14.61

LEAD-FREE SURFACE FINISHES

TABLE 14.21 Comparison of Pull Strengths of Joints on Various Surface Finishes Using 63Sn-37Pb and 99Sn-1Cu for Solder Joints95 Pull strength (N) PCB finish Ni/Au

63Sn-37Pb

99Sn-1Cu

19.3

18.8

Alpha-Level

25.6

20.2

Entek 106

23.6

22.7

Vertical Sn-Pb HASL

15.4

17.9

Horizontal Sn-Pb HASL

21.2

23.5

Horizontal Sn-Cu HASL

22.5

21.5

thickness in solder coating for large and small pads. This constraint holds true, regardless of the alloys selected for pad coating.

14.14

ELECTROLYTIC Sn-Ni

Sn-Ni alloy electroplate has been used as a final finish for PCB applications.At a tinnickel ratio of 65 wt % tin and 35 wt % nickel, the alloy forms a metastable phase, Ni-Sn. Thickness of the plating for the higher process temperature environments is usually 5 µm. For the more benign, lower process temperature environments, onehalf of that thickness may be sufficient.78 Fabrication Process. Tin-nickel is typically plated from a chloride-fluoride plating solution containing ammonium ion.94 It can also be plated with the nickel chloride/tin chloride solution complexed with potassium pyrophosphate, mainly used in Asia.95 Organic additives are used with all of the solutions for grain refinement and leveling. The cost of tin-nickel electroplating is about the same as solder mask over bare copper, with one of the major costs being the plating anodes, which may be tin and nickel or tin-nickel. Performance. The solderability of the deposit, although not as good as a pure tin or solder coating, is good enough for surface mount land finish applications. It has a flat surface, good storage life, and is compatible with a variety of solders. The Sn-Ni finished board can be etched in normal etching chemistries and may have a number of other finishes (e.g., Au, Sn-Pb, or Sn) overplated on the Sn-Ni land. Being nonmelting in nature, the Sn-Ni finish accepts a solder mask easily and can be used to produce solder coating on the lands only by the HASL process. Sn-Ni final finish is most often used when a higher process temperature is required. Sn-Ni electroplate is much harder than copper, Sn, and 63Sn-37Pb, with hardness being 750, 30, 100, and 12.8 HV, respectively. It maintains a low electrical resistance and is very corrosion-resistant, thus it can be used for edge connector applications, although the contact resistance is not as low as a gold overplate. The Sn-Ni deposit is free from problems such as tin whiskers or tin pest. When aged for a long time at 150°C, it will form copper-tin intermetallics with the underlying copper plating in the holes and surface.78

14.62

14.15

CHAPTER FOURTEEN

SOLID SOLDER DEPOSITION (SSD)

Solid solder depositions (SSDs) are a method of depositing solid solder onto lands of PCB.96,97 This solid solder not only serves as the surface finish for board lands, but also provides solder needed for forming solder joints, thus eliminating the need for the solder paste stencil printing process. Since the solder paste printing step often contributes approximately two-thirds of the defect rate of the PCB assembly process, SSD represents a potential of improving the yields. This is particularly true for fine-pitch applications with certain SSD processes. Although SSDs are not confined to lead-free solders only, they definitely provide options for lead-free surface finishes to PCB. The types of SSD may include HASL, Optipad, Sipad, PPT, solder cladding, solder jetting, and Super Solder, and are discussed briefly.

14.15.1

HASL

Hot-air solder level (HASL) techniques were developed in the early 1980s in a vertical mode. In the mid-1980s, horizontal machines were designed and gradually became the choice of larger PWB manufacturers. As of today, about two-thirds of the PWBs are with HASL finish, and the majority of HASL finishes are processed in the horizontal mode.1,98 Fabrication Process. The typical fabrication process for HASL is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

Acid clean Water rinse Etch Water rinse Flux application Preheat (105 to 150°C) Molten solder coat (2 to 10 s at 250 to 260°C) Excess solder blowoff Water rinse Dry

In a vertical HASL process, after the solder mask is applied, the panels are dipped vertically into a molten solder bath, then drawn vertically out of the bath and past high-pressure hot-air knives, which drive the molten solder through the platedthrough-holes, and provide some leveling of the solder along the exposed copper surface. In a horizontal HASL process, after the solder mask is applied, the orientation of the panel is changed to the horizontal plane. The panel is then pulled through the molten solder bath and past high-pressure hot-air knives. The horizontal orientation of the panels allows a conveyorized process, reducing the effects of gravitational pull on the molten solder and thus minimizing the tendency for puddling. The angle at which a PWB is presented to the air knives is important; the best results are achieved on quad flat packs (QFPs) at 45° to the air knife. The PWB is usually in contact with solder for about 2 s, so the copper tin intermetallic

14.63

LEAD-FREE SURFACE FINISHES

formed in that time is typically 0.15 to 0.30 µm, although the thickness of IMC can be as high as 1.9 µm through the HASL process.98,99 Horizontal HASL is capable of providing a solder finish that meets assembly requirements. For 0.010- to 0.020in pitch, a mean solder coating thickness of 12.5 µm, with an LCL of 1.75 µm and a UCL of 25 µm, is achieved with no solderability problems on a large pad. Typically, the smaller the pad, the thicker the solder coating is.99,100 Table 14.22 shows the range of finished solder coating thicknesses of all pads for horizontal and vertical HASL processes. However, a coating thickness of up to 75 µm at the center of a via hole has been noted.101 Improper cleaning was a leading cause of exposed copper and dewetting in HASL process, and high viscosity with minimal thickness is desired.102 Performance. The advantages of the HASL process include: ● ● ● ● ● ● ● ● ● ●

Excellent solderability Long shelf life (12 months) Universal acceptance Multiple heat cycle capability Easy visual inspection Good mask integrity Fair electrical contact Fair microwave applications Compatible with solder mask on bare copper applications No solder reflow under solder mask The disadvantages of the HASL process include:

● ● ● ● ● ● ●

Difficult process Boards being thermally stressed Poor surface contrast between solder and pad Not compatible with wire-bonding process Inconsistent solder volume deposition from pad to pad Poor surface coplanarity Hole compensation needed (50 to 75 µm) due to the nonuniform HASL solder deposit

TABLE 14.22 Finished Solder Coating Thickness for Vertical and Horizontal Sn-Pb HASL Processes Process

Hole wall

Board surface

Note

Vertical HASL

12.5–25 µm

0.125–25 µm

Not recommended for 20 mil

Horizontal HASL

12.5–25 µm

0.25–15 µm

Recommended for fine pitch

pitch or less

14.64

14.15.2

CHAPTER FOURTEEN

Optipad

Optipad is a process that delivers flattened solder deposits on pads serving as both the surface finish of pads and solder source for joint formation. In this process, a temporary dry film (Optimask) is applied to the board, printed, and developed, forming photodefined wells.A liquid solder is forced into the wells.The board is kept flat as it moves through the machine and cools. The temporary dry film is then stripped from the board. The solder thickness is typically 50 to 200 µm, which is controlled by the temporary solder mask.96,97 Fabrication Process. Detailed fabrication process steps for Optipad follow and are schematically shown in Fig. 14.56.96 1. 2. 3. 4. 5. 6. 7.

Apply the temporary solder mask. Apply the molten solder. Flatten the solder. Remove the temporary solder mask. Apply the sticky flux. Place the components. Reflow the package.

FIGURE 14.56 Schematic of Optipad process. (a) Bare board, (b) application of temporary mask, (c) liquid solder application, (d) stripping of temporary mask.

LEAD-FREE SURFACE FINISHES

14.65

Performance. The primary benefit in the Optipad process is the consistent solder volume attained and the flat deposit. The negative aspects include ●

● ●

The cost associated with the application and removal of the temporary solder mask The initial cost of the equipment The inability of maintaining the planarity of the second side

14.15.3

Sipad

Similar to Optipad, Sipad also forms flattened solder deposit on pads serving as both surface finish and solder source for joint formation. Instead of using a temporary solder mask and molten solder for deposition, Sipad employs a permanent solder mask for solder volume control and solder paste as a solder source for deposition. The average thickness of solder deposits formed is 50 µm and can be as high as 130 µm. Fabrication Process. The detailed fabrication process for Sipad can be described as follows96,97,103: 1. Analyze and alter the computer-aided design (CAD) as necessary. 2. Apply a photoimagable dry-film solder mask (Simask) with a thickness of no less than 100 µm. 3. Laminate and develop the Simask to form a well around each pad. 4. Print solder paste into a well via the standard solder paste stencil printing process. 5. Reflow solder paste via the standard process for form bumps with meniscus above the plane of the solder mask. 6. Wash the board to remove flux residue and solder balls. 7. Place the PCB into a flattening system. 8. Reheat solder to the melting point. 9. Flatten the pads between the platens of a cold press to freeze the solder deposit into a planar SSD flush with the surface of the solder mask. 10. Print adhesive no-clean flux onto the planar SSD surface. 11. Dry the flux to a tacky finish. 12. Cover the tacky finish with a release paper. 13. Remove the release paper, and place the component. 14. Reflow to form solder joints. Performance. The benefits of Sipad include ● ● ● ●

The very flat deposit The ability to alter the volume of solder Excellent solderability Good compatibility with all other surface finishes (e.g., OSP or Ni/Au) for solder paste deposition process

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The solder volume is accomplished by regulating the opening of the solder mask around the surface mount pad and filling the entire well with solder paste. The concerns associated with the Sipad process include ● ● ● ●

The potential for foil formation The potential for meniscus formation The cost associated with the use of a thick dry film mask The inability of maintaining the planarity of the second side

14.15.4

PPT

Precision pad technology (PPT) forms a flattened solder deposit with the use of a regular solder mask and solder paste. A vibrating stainless-steel mesh is seated on top of the PCB printed with paste. The paste is then reflowed with a traveling hot-air knife, and solidified afterward with a pass of a cool-air knife. The thickness of solder is 50 to 200 µm. Fabrication Process. The fabrication process of PPT can be described as follows: 1. Prepare the PCB with a solder mask no less than 25 µm in thickness. 2. Stencil-print the solder paste onto the pads within the aperture of the solder mask. 3. Load the board into the reflow/formation system. 4. Place a vibrating tensioned stainless-steel screen onto the surface of the board. 5. Reflow the paste with a hot-air knife traveling over the board. 6. Solidify the solder with a pass of a cool-air knife. 7. Board-exit the system. 8. Clean the board, if necessary. TABLE 14.23 Typical Reflow Profile for PPT Process Using 63Sn-37Pb105 Peak temperature

214.5°C

Time over 150°C

57.5 s

Time over 180°C

15.0 s

Time over 200°C

6.0 s

Time over 210°C

2.5 s

The dwell time above liquidus temperature is normally less than 20 s. Table 14.23 shows a typical PPT reflow profile for a 63Sn-37Pb system.104 The screen serves as a mold to flatten, shape, and remove excess solder during reflow. Excess solder wicks above the mesh during reflow in the form of solder balls. The reflowed solder deposits are macroplanar with an embossed surface topography that facilitates retaining tack flux at subsequent assembly. Shorts and solder balls are eliminated at assembly, and the copper lands are encapsulated in a thick solder deposit, which increases bare-board shelf life.

Performance. The advantages of PPT are simplicity and the low cost associated with it. Furthermore, the mesh impression left on the surface of the board provides a flat surface for component leads to rest on and an area for tacky flux to pool prior to reflow at assembly. It offers the planarity and uniformity that are needed for finepitch and BGA assembly by reassigning solder paste printing responsibilities to the supplier. The limitation is the inability to maintain the planarity of the second side.

LEAD-FREE SURFACE FINISHES

14.15.5

14.67

SOLDER CLADDING

Solder cladding forms solid solder deposits by reflowing solder paste, a method in use since the 1960s.97 Fabrication Process. The fabrication process of solder cladding is described as follows: 1. 2. 3. 4. 5.

Print the solder paste. Reflow the solder paste. Apply the tacky flux. Place the components. Reflow the package.

Performance. Simplicity and cost are the two advantages to solder cladding. The main drawback is the formation of the rounded meniscus, thus causing potential difficulty in placing fine-pitch components.

14.15.6

SOLDER JETTING

The solder jetting process deposits liquid solder droplets of a controlled size to the land areas of the circuit board. Pressure and vibration via a piezoelectric mechanism are applied to a liquid metal reservoir, which forces the solder through an orifice to form a liquid droplet that flies through a charge electrode, electrostatic deflection plate, and a catcher, and then onto the surface mount pads. The size of the balls is in the range of 0.004 to 0.012 in.97 Fabrication Process. The fabrication process of solder jetting is described as follows: 1. Apply the jetted solder droplet onto the fine-pitch pads. 2. Apply the tacky flux to the fine-pitch pads. 3. Place components onto the fine-pitch sites. 4. Reflow via a hot bar. 5. Print the paste onto coarse-pitch sites. 6. Place the coarse-pitch components. 7. Reflow the coarse-pitch components. Performance. Ideally, this method allows the deposition of solder onto fine-pitch pads automatically through programming. Unfortunately, this is at the expense of being able to process the entire board in one step. Furthermore, uniformity, coplanarity, jetting landing precision, and throughput are issues that still need to be resolved before this process becomes widely acceptable.

14.15.7

SUPER SOLDER

Super Solder is a chemical deposition process. Applied in paste form, material mainly contains (RCOO)2Pb (a lead salt of an organic acid) and tin powder. Upon heating, the two components react, with lead being reduced to metal and tin being

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oxidized to tin salt. The lead metal forms alloys with tin powder to create particles; the particles then settle, forming a solder deposit. A minimum pitch of 0.1 to 0.15 mm can be sustained.106 The thickness of the solder deposit is between 40 and 70 µm. Fabrication Process. The fabrication process of Super Solder is described as follows: 1. Preclean the panels via the microetch process. 2. Apply Super Solder, a proprietary organic lead and tin powder paste. 3. Heat to bond Super Solder to fine-pitch sites to form solder bumps. 4. Clean the panels. 5. Apply tacky flux to the fine-pitch sites. 6. Place the fine-pitch components. 7. Reflow the fine-pitch sites via a hot bar. 8. Paste-print the coarse-pitch sites. 9. Place the components. 10. Reflow the coarse-pitch sites. Performance. This process is well suited for applications such as tape automated bonding, where the insertion of solder mask dams may be difficult but is not designed to predeposit solder over all of the component sites on a board.97 Super Solder is used in Toshiba’s notebook and Panasonic’s notebook.105 The solder deposit is dome-shaped. The cost of the complete system may make Super Solder prohibitive for some applications. Most important, the exchange chemistry deposition approach, adequate for a Sn-Pb alloy, is highly questionable to be applicable for Pb-free solder systems.

14.16

SUMMARY OF PCB SURFACE FINISHES

As discussed previously, there is a wide range of lead-free coating options available for PCB surface finish applications. However, due to the complicated functional requirement of various electronic products, it is virtually unlikely to identify a single surface finish that will satisfy all of the requirements. Following are the pros and cons of finish options for specific applications. ●

●

Solderability. Similar to Sn-Pb HASL, Pb-free HASL is also considered to be superior in solderability, particularly for a reflow temperature higher than the melting temperature of HASL materials. However, the primary limitation of HASL is the inability to provide even finish thickness and quality for fine-pitch applications. This is true whether the solder is Sn-Pb or Pb-free; this excludes HASL as a major candidate for PCB finish applications. Plated metallization surface finishes often exhibit better solderability, if the metal can be dissolved into solder rapidly during soldering.Therefore, options such as Au,Ag, and Sn are often better in solderability than others, including OSPs. Aging resistance. Metal surface finishes often exhibit better resistance than OSP against aging (e.g., thermal or steam). This is particularly true for noble metal fin-

LEAD-FREE SURFACE FINISHES

●

●

●

●

●

●

●

●

●

●

14.69

ishes. However, under corrosive gas storage conditions, OSPs turn out to be outstanding in retaining their solderability. Tolerance against Pb contamination. Bi-containing systems are sensitive to Pbcontamination, mainly due to the formation of low-melting ternary eutectic 52Bi30Pb-18Sn alloy. Thick-board through-holes. Due to the throw-power limitation, electrolytic platings typically fail to provide an even coating for thick-board through-holes. As a result, the immersion process becomes a favorite choice. Wire bonding. Only nonmelting metallic surface finishes can be considered for wire-bonding applications. This quickly rules out OSP, Sn-, or Bi-containing systems. Presence of nickel underlayer improves the wire bondability, although the solderability may be compromised, as demonstrated by Pd systems. In-circuit probe testing. For in-circuit probe testing purposes, finishes with either tarnish or too high a hardness will have greater difficulty in probe penetration. In general, OSPs are not the most promising in this regard. Metallic surface finishes with a matte appearance often are more promising, due to a greater contact area provided by the rough surface topology. Tolerance against cleaning. Organic solderability preservatives have a very low tolerance against PCB cleaning prior to paste reflow, because OSPs tend to be removed by the cleaners as well. Metallic surface finishes are all fairly robust against board cleaning. IMC formation. Both Au and Pd suffer excessive intermetallics formation issues when the thickness of those metals is greater than approximately 0.25 µm. This is particularly an issue for Au when the same finish is to be used for wire bonding as well. Connector applications. Usually surface finishes with high electrical conductivity, high abrasion resistance, high oxidation resistance, and high hardness are desired for connector applications. The OSPs are ruled out immediately due to poor electrical conductivity. Noble metallic finishes often shine in this category. Finish consistency/inspectability. Finishes with challenges in both quality consistency and inspection capability are the trickiest manufacturing issues. For instance, ENIG tends to have black-pad problems from time to time. And, unfortunately, the symptom is not easily inspectable prior to assembly, and it is not inspectable without destructive testing after assembly. Tin whisker/tin pest. All tin-based metals or alloys suffer from potential problems with tin whisker and tin pest. Although both symptoms can be prevented to a certain extent, such as nickel underlying or alloying tin with secondary elements, 100 percent symptom-proof is still unassured. These potential problems highly reduced the options of finding a low-cost lead-free surface finish, as will be discussed later. Cost. The OSP is probably the lowest in cost. Next to that may be nonpreciousmetal plating finishes, especially the immersion processes. Additional savings promised by the electroless process include elimination of tie bars from circuit board design, hence the additional size reduction that is achievable.

Overall, it can be seen that none of the surface finishes can be considered an ideal solution as the answer for all PCB finish requirements.Therefore, the finish selection has to be determined by the requirements of specific applications involved in the product design.

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14.17 OPTIONS FOR COMPONENT SURFACE FINISHES The requirements for component surface finishes are similar to those for PCB surface finishes. However, some of the features may be more important to components than to PCBs, such as ductility, due to the lead trimming and forming requirements. Shipley uses the following criteria as their plating process requirements80: ● ● ● ● ● ●

Must be compatible with existing high-speed plating equipment Must have a minimum deposition rate of 7.5 µm/min Must have familiar chemistry, preferably an MSA electrolyte Must have all products in the process that are fully analyzable Must have deposits that possess good solderability (same as or better than Sn-Pb) Must have deposits that possess good ductility (same as or better than Sn-Pb)

Table 14.24 lists the options of lead-free surface finishes for components. The system is categorized by the key element that is used. Each category is further classified by the type of process and chemistry. Examples are given for certain groups.

14.18

Ni/Au (ENIG)

Fabrication Process. The characteristics and manufacturing process of ENIG are the same as those discussed in Sec. 14.4.2. Performance. Popelar et al., at IC Interconnect, have investigated using ENIG for flip chip under-bump metallurgy (UBM) applications.106 In their process, the exposed aluminum I/O pads are plated with an EN cap with a typical thickness of 5

TABLE 14.24 List of Lead-Free Surface Finishes Surface finish system

Finish process and chemistry

Ni/Au

Electroless Ni/electroless (immersion) Au, or ENIG

Pd

Electrolytic Pd or Pd alloys

Ni/Pd

Example

Electroless Ni/electroless (autocatalytic) Pd Electroless Ni/electroless (autocatalytic) Pd/electroless (immersion) Au

Pd-Ni

Electrolytic Pd-Ni

Sn

Electrolytic Sn

Sn-Ag

Electrolytic Sn-Ag

96.5Sn-3.5Ag

Sn-Bi

Electrolytic Sn-Bi

90Sn-10Bi

Sn-Cu

Electrolytic Sn-Cu

99Sn-1Cu

For multilayer design, the sequence of materials starts from the bottom layer.

LEAD-FREE SURFACE FINISHES

14.71

µm, followed by a flash of immersion Au. The appropriate solder paste alloy is deposited via stencil printing, and subsequently reflowed and cleaned. No degradation in shear load or failure mode occurred among the three alloys (63Sn-37Pb, 90Pb-10Sn, and 95.5Sn-3.8Ag-0.7Cu) that were tested, indicating no critical UBM consumption (i.e., no excessive intermetallics growth) during reflow. Additional tests were performed comparing nickel UBM thicknesses of 1, 2, and 5 µm.Again, all bumps exhibit comparable shear strength, indicating no critical UBM consumption. These data suggest that ENIG can be a viable candidate as UBM for flip chip solder paste bumping applications.

14.19

ELECTROLYTIC Pd

Fabrication Process. See Sec. 14.7.1. Performance. Fan et al., from Lucent Technologies, studied electrolytic Pd or electrolytic Pd with Au flash as a potential leadframe surface finish.107 The postetch solderability comparison was made on 34 µm of copper laminate of 0.25 µm of palladium, 0.025 µm of gold flash over 0.25 µm of palladium, 1.25 µm of silver over 1.25 µm of nickel, and 0.38 µm soft gold over 1.25 µm of nickel. Both gold-flashed palladium and palladium alone passed the steam and thermal aging with only a slight degradation. The gold-flashed palladium was better than all of the samples tested, probably due to the gold on the palladium performing two functions: (1) inhibiting the diffusion of copper into the palladium, and (2) acting as an oxidation barrier. The failure of both silver and gold over nickel after thermal and steam aging were probably due to migration of nickel through the silver or gold layer and forming an oxide on the surface. Palladium, as an excellent migration/diffusion barrier, unlike gold and silver, produces a more stable final finish, which does not require an active flux to be solderable.The results conclude that thin deposits (<0.5 µm in thickness) of palladium and gold-flashed palladium provide good solderability and good wire and die bondability.

14.20

ELECTROLESS Ni/Pd

Fabrication Process. See Sec. 14.8. Performance. Fan et al. studied the potential of EN/Pd as a surface finish for leadframe, with emphasis on the solderability.107 Samples consisted of 0.015 gm/cm2 (0.5 oz/ft2) of copper laminate plated with 2.5 µm 6 percent phosphorous EN and then 0.5 µm of electroless palladium with and without a gold flash. Samples were solderability-tested in the as-plated condition and again after an 85% RH/85°C 8-h steam age.Three different fluxes were used.All deposits exhibited 95 percent or higher solder coverage, even with a rosin nonactive flux. The electroless palladium with the gold flash performed slightly better than the palladium without gold, presumably due to the oxidation barrier function of gold flash. Results indicate that EN/electroless Pd is promising as a leadframe surface finish. The preceding findings are supported by the work at UCLA.108 In the soldering reaction at 200°C between eutectic Sn-Pb and plated Ni/Pd on Cu leadframes, two

14.72

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thicknesses of Pd—760 and 2500 Å—were used. Even very thin Pd can lead to continuous spreading of the solder on the leadframe, as evidenced by the lack of a stable wetting angle. Anisotropic spreading and spike formation were found to be caused by the mechanical effect of rolling of the leadframe. This phenomenon is more pronounced in the thinner Pd samples. In the interfacial reaction, formation of a ternary Pd-Ni-Sn compound and Ni3Sn4 were observed. While spalling of the ternary compound occurs, no spalling of the Ni3Sn4 was found. The latter forms a rather uniform layer consisting of small scallop-type grains. The growth rate of Ni3Sn4 is about one order of magnitude slower than that of Cu6Sn5 in the reaction between Cu and eutectic Sn-Pb.108 For a component leadframe surface finish, either a two-layer plate [consisting of Pd flash (0.075 to 0.25 µm) over Ni preplating] or a four-layer plate (consisting of Ni flash–Pd flash–Ni plate–Pd flash) is utilized. Plating cracks occur on all outer-bend radii of the lead. Solderability is poorer than Sn-Pb plated leadframes. For connectors or contacts, the thickness of Pd used is around 0.5 to 0.75 µm.

14.21

ELECTROLYTIC Pd/Ni

Fabrication Process. See Sec. 14.9.2. Performance. An electrolytic Pd-Ni alloy with 80/20 (w/w) composition on copper was tested for its potential as a leadframe surface finish.107 The coating thickness is 0.12 µm. A Pd-Ni alloy exhibits good solderability for an as-plated sample. However, the solderability degraded after thermal aging when using a nonactivated rosin flux. The nickel in the palladium/nickel alloy is believed to oxidize at 125°C, and using a mildly active or fully active flux is necessary to remove the oxide before soldering.

14.22

Sn

Fabrication Process. See Sec. 14.10. Performance. Hunt, at the National Physical Laboratory, investigated the solderability of tin on leadframes made of Cu, Ni, and Alloy 42. He concluded that oxide growth degrades wetting, but it is intermetallic growth at the surface that has been shown to be the critical factor influencing solderability. Good-quality coatings should be a minimum of 5 µm to protect components, and 10 µm is recommended as ideal for Sn-Pb coating. A similar thickness requirement may also be applicable to Sn coating. An intermetallic oxide is impervious to flux. Hence, for thin or inferior tin coatings, it is the presence of intermetallic oxide at the surface that spells the end of a component’s solderability.83

14.23

ELECTROLYTIC Sn-Ag

Eutectic Sn-Ag alloy (96.5Sn-3.5Ag) exhibits a low electrical resistivity (12.31 µΩcm) and high elongation (73 percent). The metal supply is sufficient at a reasonably

LEAD-FREE SURFACE FINISHES

14.73

low cost. Although Ag extract in the groundwater may still be a concern, overall it is still a promising option as lead-free surface finish. Fabrication Process. Due to the electrochemical potential shown, Ag tends to deposit much more readily than does Sn. Consequently, it is very difficult to codeposit tin-rich alloys of Sn-Ag: Ag+ + 1e− → Ag0 0.7996 V Sn2+ + 2e− → Sn0 −0.1375 V Sn4+ + 4e− → Sn0 −0.9450 V TABLE 14.25 Electroplating Parameters for Sn-Ag Finish Parameter

Setting

Sn content (g/L)

40

Ag content (g/L)

7

Additive (mL/L)

20

Codeposition of near-eutectic Sn-Ag alloys requires use of complexing agents with exotic chemistries. This inevitably complicates the waste treatment. Table 14.25 shows the plating parameter for an Sn-Ag surface finish.80 Figure 14.57 shows the topology of the electrolytic Sn-Ag surface finish.80

Performance. The Sn-Ag deposition composition is sensitive to the plating current Current density (Å/dm ) 0.2 density. Figure 14.58 shows the relation between current density and Ag content in Sn-Ag deposition.80 The Ag content decreases rapidly initially, then slowly with increasing current density. Unlike eutectic Sn-Pb, the melting temperature of which Temperature (°C)

45

2

FIGURE 14.57 Topology of electroplated Sn-Ag surface finish.

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FIGURE 14.58 Sn-Ag.

Effect of current density (Å/dm2, or ASD) on the Ag content in electroplated

is not sensitive to composition variation, variation in Ag content causes a significant change in melting temperature of Sn-Ag binary alloys. For instance, the liquidus temperatures of 96.5Sn-3.5Ag and 90Sn-10Ag are 221 and 300°C, respectively. As a result, a very tight composition control is required. Overall, the electrolytic Sn-Ag finish exhibits good mechanical properties, good solderability, and good compatibility with solder alloys and fluxes. However, it suffers low deposition rates, complicated plating chemistry, and requires the use of complexing agents; therefore, it is not easy to get implemented.

14.24

ELECTROLYTIC Sn-Bi

The electrolytic Sn-Bi used as a component surface finish has been reported by Schetty, from Shipley Ronal, with a composition of 90Sn-10Bi (w/w).80 TABLE 14.26 Process Parameters for Sn-Bi Electroplating Parameter Sn content (g/L) Bi content (g/L)

Fabrication Process. The electroplating process parameters for a 90Sn-10Bi finish are described in Table 14.26.80

Setting 60 8.5

Acid content (mL/L)

200

Additive (mL/L)

105

Temperature (°C)

40

Current density (Å/dm2)

15

Performance. The topology of a 90Sn-10Bi surface finish is shown in Fig. 14.59.80 Overall, Sn-Bi finishes have good mechanical properties and low toxicity. Due to abundant global supply, the cost is also low, as discussed in the immersion Sn-Bi section. With the use of methane sulfonic acid chemistry, the deposition rate is high. However, Bi immersion onto

LEAD-FREE SURFACE FINISHES

14.75

FIGURE 14.59 Scanning electron microscopic image of a 90Sn-10Bi surface finish.

anodes forms gray deposit. The solderability is very good. Prasad et al. conducted plating chemical evaluations and reliability of Pb-free leadframe packages.109 When compared with pure Sn and Sn-Cu, the Sn-Bi system exhibits the minimum whiskers, although no plating system is totally whisker-free. Whisker growth is found to be related to substrate materials, and alloy 42 leadframe does not seem to have whisker problems for the Pb-free plating chemical systems within the time frame studied. The main disadvantage is incompatibility with Sn-Pb solder due to formation of ternary eutectic Sn-Pb-Bi solder, as discussed earlier. As a result, Sn-Pb solder joints contaminated with Bi are prone to fracture. Therefore, a Sn-Bi finish is only recommended where total control of the assembly parts and process is maintained.

14.25

Sn-Cu

Shipley has developed electrolytic Sn-Cu alloy plating chemistry for component surface finish.80 Sn-Cu alloy with a composition of 99.3Sn-0.7Cu exhibits the following attractive features as a component surface finish: ● ● ● ● ●

Low electrical resistivity (11.67 µΩ-cm) High elongation (>30 percent) Low toxicity Abundant world reserve Low cost

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TABLE 14.27 Plating Parameters for Sn-Cu Alloy Electrolyte Parameter Sn content (g/L)

Setting

Fabrication Process. The reportedly highspeed, methane sulfonic acid–based electrolyte chemistry developed by Shipley can be described in Table 14.27.80

60

Performance. The topology (2000×) of SnCu, plated at 20 Å/dm2 current density, is shown Acid content (mL/L) 200 in Fig. 14.60.80 The Sn-Cu deposit composition Additive (mL/L) 105 is fairly insensitive to variation in temperature and current density, as shown in Fig. 14.61.80 Temperature (°C) 40 To evaluate the potential of tin whisker Current density (Å/dm2) 25 growth, two Sn-Cu samples deposited with 25 and 30 Å/dm2 current density, respectively, were subjected to 60°C/95% RH for 500 h. As a control, pure tin after 500 h of aging showed tin whisker formation, while Sn-Cu finishes exhibit no whiskers at all for both samples. The solderability of Sn-Cu was studied by determining the zero-force cross time (ZCT) in the wetting balance test.Also evaluated were 90Sn-10Pb, 100Sn, 90Sn-10Bi, and 97Sn-3Ag. Results shown in Table 14.28 indicate that the solderability decreases in the following order: 90Sn-10Pb > 90Sn-10Bi > 97Sn-3Ag > 100Sn and 99Sn-1Cu.80 All finishes are considered acceptable in solderability. Cu content (g/L)

1.1

14.26 SUMMARY OF COMPONENT SURFACE FINISHES Schetty has compared the pros and cons of several viable component surface finishes, with results summarized in Table 14.29.80 Ni/Pd is too expensive and marginal TABLE 14.28 Solderability Test Results for Various Component Surface Finishes Component finish

ZCT (s)

Coverage (%)

Sn-Pb 90-10

Aging condition As plated

0.29

>95

Sn-Pb 90-10

Steam aged

0.46

>95

Sn-Pb 90-10

Heat aged

0.32

>95

Sn

As plated

0.58

>95

Sn

Steam aged

0.83

>95

Sn

Heat aged

0.68

>95

Sn-Bi 90-10

As plated

0.33

>95

Sn-Bi 90-10

Steam aged

0.41

>95

Sn-Bi 90-10

Heat aged

0.37

>95

Sn-Ag 97-3

As plated

0.42

>95

Sn-Ag 97-3

Steam aged

0.54

>95

Sn-Ag 97-3

Heat aged

0.53

>95

Sn-Cu 99-1

As plated

0.39

>95

Sn-Cu 99-1

Steam aged

0.83

>95

Sn-Cu 99-1

Heat aged

0.79

>95

LEAD-FREE SURFACE FINISHES

14.77

FIGURE 14.60 Topology (2000×) of a Sn-Cu surface finish plated at 20 Å/dm2 current density.

FIGURE 14.61 Effect of current density and temperature on Sn-Cu deposit composition.

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TABLE 14.29 Pb-Free Electronic Finish Comparison Summary Pb-free Solderability finish

Mechanical properties

Melting point

Whiskering

Compatibility

Plating feasibility

Relative cost

NiPd

∗

∗

G

G

G

G

X

Sn

G

G

∗

X

G

G

G G

SnBi

G

G

∗

G

X

G

SnAg

G

G

G

G

G

X

∗

SnCu

G

G

G

G

G

G

G

Note: G: good; ∗: marginal; X: unacceptable.

on soldering and mechanical properties. Sn still suffers concerns on tin whiskering and tin pest problems. Sn-Bi is sensitive to Pb contamination. Sn-Ag is very difficult to plate high Sn deposit because of unfavorable electrochemical potentials of Sn versus Ag. Overall, the most promising component finish appears to be Sn-Cu, due to the lack of any obvious weakness.80

REFERENCES 1. Cullen, D., “Immersion Silver Performance Results,” Proceedings: IPCWorks ’99 Conference, Minneapolis, MN, October 27, 1999. 2. Ray, U., I. Artaki, H. M. Gordon, and P. T. Vianco, “The Influence of Temperature and Humidity on Printed Wiring Board Surface Finishes: Immersion Tin vs. Organic Azoles,” J. Electronic Materials, 23(8):779–785, August 1994. 3. Parker, J. L., and J. S. Horton, “Assembly of Printed Wiring Boards Coated with an Organic Solderability Preservative,” Surface Mount International Conference, San Jose, CA, 1992. 4. Artaki, I., et al., “Corrosion Protection of Copper Using Organic Solderability Preservatives,” Surface Mount International Conference, San Jose, CA, 1992. 5. Ray, U., I. Artaki, H. M. Gordon, and R. L. Opila, “Solderability and Thermal Stability of Azole Corrosion Inhibitors,” Proc. of NEPCON West, pp. 423–435, Anaheim, CA, 1993. 6. Wenger, G. M., and D. A. Machusak, “Soldering Evaluation of Organic Solderability Preservatives,” Proc. of NEPCON West, pp. 436–451, Anaheim, CA, 1993. 7. Wengenroth, K., “OSPs: Guidelines for Successful Soldering,” Proc. of NEPCON West, Anaheim, CA, February 23–27, 1997. 8. Castaneda, C., K. Chandler, N. Nguyen, R. G. Robertson, and J. White, “Evaluating Alternative PCB Fabrication Processes,” Circuits Assembly, pp. 58–61, January 1994. 9. Carano, M., “OSP evolution [PCB surface finishes],” Printed Circuit Fabrication, 20(7):28–31, July 1997. 10. Verbockhaven, D., G. Conard, and K. McKean, “Using Nitrogen on OSP-Coated Printed Circuit Boards,” Electronic Packaging and Production, 37(5):59–60, 62, April 1997. 11. Melton, C., and H. Fuerhaupter, “Lead-Free Tin Surface Finish For PCB Assembly,” Proc. of NEPCON West, Anaheim, CA, February 25–29, 1996. 12. Charbonneau, R. A., “An Evaluation of Anti-oxidant Coatings as an Alternative to HASL,” Proc. of NEPCON West, Anaheim, CA, February 25–29, 1996. 13. Langston, K. F., and S. Gutierrez, “Evaluating OSPs Used in the Card Assembly Process,” Proc. of NEPCON West, Anaheim, CA, February 25–29, 1996.

LEAD-FREE SURFACE FINISHES

14.79

14. Parquet, D. T., and D. W. Boggs, “Alternatives to HASL: A User’s Guide for Surface Finishes,” Electronic Packaging and Production, pp. 38–42, August 1995. 15. Ivankovits, J. C., and B. M. Adams, “Effects of Controlled Atmospheres on Solder Wetting,” Surface Mount Technology, pp. 23–26, October 1993. 16. Ewell, G. J., “New Approaches to Preserving Solderability on PCBs,” Proc. of NEPCON West, Anaheim, CA, February 23–27, 1997. 17. Wetz, L. A.