High-speed VLSI interconnections

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High-Speed VLSI Interconnections Second Edition

Ashok K. Goel Department of Electrical Engineering Michigan Technological University

WILEY-INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION

High-Speed VLSI Interconnections

High-Speed VLSI Interconnections Second Edition

Ashok K. Goel Department of Electrical Engineering Michigan Technological University

WILEY-INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION

Copyright ß 2007 by John Wiley & Sons, Inc. All rights reserved Published by John Wiley & Sons, Inc., Hoboken, New Jersey Published simultaneously in Canada No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400, fax 978-750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, 201-748-6011, fax 201-748-6008, or online at http://www.wiley.com/go/permission. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and speciﬁcally disclaim any implied warranties of merchantability or ﬁtness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of proﬁt or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at 877-762-2974, outside the United States at 317-572-3993 or fax 317-572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic formats. For more information about Wiley products, visit our web site at www.wiley.com. Wiley Bicentennial Logo: Richard J. Paciﬁco Library of Congress Cataloging-in-Publication Data: Goel, Ashok K., 1953High-speed VLSI interconnections / by Ashok K. Goel. – 2nd ed. p. cm. Includes bibliographical references. ISBN 978-0-471-78046-5 (cloth) 1. Very high speed integrated circuits–Mathematical models. 2. Very high speed integrated circuits–Defects–Mathematical models. 3. Integrated circuits–Very large scale integration–Computer simulation. 4. Semiconductors– Junctions. I. Title. TK7874.7.G63 2007 621.390 5–dc22 2007001710 Printed in the United States of America 10 9 8 7 6 5 4 3 2 1

In loving memory of my father

Shri D. N. Goel

Contents PREFACE 1

xv

Preliminary Concepts and More

1

1.1 Interconnections for VLSI Applications 1.1.1 Metallic Interconnections: Multilevel, Multilayer, and Multipath Conﬁgurations 1.1.2 Optical Interconnections 1.1.3 Superconducting Interconnections

2

1.2 Copper Interconnections 1.2.1 Advantages of Copper Interconnects 1.2.2 Challenges Posed by Copper Interconnects 1.2.3 Fabrication Processes for Copper Interconnects 1.2.4 Damascene Processing of Copper Interconnects

5 6 6 7 9

2 5 5

1.3 Method of Images

10

1.4 Method of Moments

15

1.5 Even- and Odd-Mode Capacitances 1.5.1 Two Coupled Conductors 1.5.2 Three Coupled Conductors

17 17 19

1.6 Transmission Line Equations

21

1.7 Miller’s Theorem

23

1.8 Inverse Laplace Transformation

25

1.9 Resistive Interconnection as Ladder Network 1.9.1 Open-Circuit Interconnection

27 27 vii

viii

CONTENTS

1.9.2 1.9.3

2

Short-Circuited Interconnection Application of Ladder Approximation to Multipath Interconnection

29 31

1.10 Propagation Modes in Microstrip Interconnection

31

1.11 Slow-Wave Mode Propagation 1.11.1 Quasi-TEM Analysis 1.11.2 Comparison with Experimental Results

32 33 37

1.12 Propagation Delays

41

Exercises

41

References

42

Parasitic Resistances, Capacitances, and Inductances

46

2.1

Parasitic Resistances: General Considerations

47

2.2

Parasitic Capacitances: General Considerations 2.2.1 Parallel-Plate Capacitance 2.2.2 Fringing Capacitances 2.2.3 Coupling Capacitances

50 51 51 52

2.3

Parasitic Inductances: General Considerations 2.3.1 Self and Mutual Inductances 2.3.2 Partial Inductances 2.3.3 Methods for Inductance Extraction 2.3.4 Effect of Inductances on Interconnection Delays

52 53 55 55 57

2.4

Approximate Formulas for Capacitances 2.4.1 Single Line on a Ground Plane 2.4.2 Two Lines on a Ground Plane 2.4.3 Three Lines on a Ground Plane 2.4.4 Single Plate with Finite Dimensions on a Ground Plane

57 58 58 59

Green’s Function Method: Using Method of Images 2.5.1 Green’s Function Matrix for Interconnections Printed on Substrate 2.5.2 Green’s Function Matrix for Interconnections Embedded in Substrate 2.5.3 Application of Method of Moments 2.5.4 Even- and Odd-Mode Capacitances 2.5.5 Ground and Coupling Capacitances

60

2.5

59

60 67 72 73 76

CONTENTS

2.5.6 2.5.7

The Program IPCSGV Parametric Dependence of Interconnection Capacitances

ix

76 77

2.6

Green’s Function Method: Fourier Integral Approach 2.6.1 Green’s Function for Multilevel Interconnections 2.6.2 Multiconductor Interconnection Capacitances 2.6.3 Piecewise Linear Charge Distribution Function 2.6.4 Calculation of Interconnection Capacitances

84 84 87 89 90

2.7

Network Analog Method 2.7.1 Representation of Subregions by Network Analogs 2.7.2 Diagonalized System for Single-Level Interconnections 2.7.3 Diagonalized System for Multilevel Interconnections 2.7.4 Interconnection Capacitances and Inductances 2.7.5 The Program ICIMPGV 2.7.6 Parametric Dependence of Interconnection Capacitances 2.7.7 Parametric Dependence of Interconnection Inductances

91 92 93 97 97 99 99 104

Simpliﬁed Formulas for Interconnection Capacitances and Inductances on Silicon and GaAs Substrates 2.8.1 Line Capacitances and Inductances 2.8.2 Coupling Capacitances and Inductances

109 112 113

Inductance Extraction Using FastHenry 2.9.1 The Program FastHenry 2.9.2 Extraction Results Using FastHenry

114 115 116

2.8

2.9

2.10 Copper Interconnections: Resistance Modeling 2.10.1 Effect of Surface/Interface Scattering on Interconnection Resistivity 2.10.2 Effect of Diffusion Barrier on Interconnection Resistivity 2.11 Electrode Capacitances in GaAs MESFET: Application of Program IPCSGV 2.11.1 Ground and Coupling Capacitances 2.11.2 The Program EPCSGM 2.11.3 Dependence on MESFET Dimensions 2.11.4 Comparison with Internal MESFET Capacitances

119 120 121 122 122 123 127 132

Exercises

132

References

133

x

3

CONTENTS

Interconnection Delays

136

3.1 Metal–Insulator–Semiconductor Microstripline Model of an Interconnection 3.1.1 The Model 3.1.2 Simulation Results

138 138 140

3.2 Transmission Line Analysis of Single-Level Interconnections 3.2.1 The Model 3.2.2 The Program PDSIGV 3.2.3 Dependence on Interconnection Parameters

145 145 150 150

3.3 Transmission Line Analysis of Parallel Multilevel Interconnections 3.3.1 The Model 3.3.2 Numerical Simulation Results

154 154 158

3.4 Analysis of Crossing Interconnections 3.4.1 Simpliﬁed Analysis of Crossing Interconnections 3.4.2 Comprehensive Analysis of Crossing Interconnections 3.4.3 The Program SPBIGV 3.4.4 Simulation Results Using SPBIGV

168 169 174 178 178

3.5 Parallel Interconnections Modeled as Multiple Coupled Microstrips 3.5.1 The Model 3.5.2 Simulation Results

190 190 193

3.6 Modeling of Lossy Parallel and Crossing Interconnections as Coupled Lumped Distributed Systems 3.6.1 The Model 3.6.2 Simulation Results

195 195 197

3.7 Very High Frequency Losses in Microstrip Interconnection 3.7.1 The Model 3.7.2 Simulation Results 3.7.3 Interconnection Delays with High-Frequency Effects

203 203 207 213

3.8 Compact Expressions for Interconnection Delays 3.8.1 The RC Interconnection Model 3.8.2 The RLC Interconnection Model: Single Semi-Inﬁnite Line 3.8.3 The RLC Interconnection Model: Single Finite Line

216 217 219 221

CONTENTS

3.8.4 3.8.5 3.9

4

Single RLC Interconnection: Delay Time Two and Three Coupled RLC Interconnections: Delay Times

xi

223 224

Interconnection Delays in Multilayer Integrated Circuits 3.9.1 The Simpliﬁed Model 3.9.2 Simulation Results and Discussion

226 226 228

3.10 Active Interconnections 3.10.1 Interconnection Delay Model 3.10.2 Active Interconnection Driven by Minimum-Size Inverters 3.10.3 Active Interconnection Driven by Optimum-Size Inverters 3.10.4 Active Interconnection Driven by Cascaded Inverters 3.10.5 Dependence of Propagation Time on Interconnection Driving Mechanism

230 230 231 232 234 235

Exercises

236

References

237

Crosstalk Analysis

242

4.1

Lumped-Capacitance Approximation

243

4.2

Coupled Multiconductor MIS Microstripline Model of Single-Level Interconnections

245

4.2.1 4.2.2 4.2.3

245 248 251

4.3

4.4

The Model Numerical Simulations Crosstalk Reduction

Frequency-Domain Modal Analysis of Single-Level Interconnections 4.3.1 General Technique 4.3.2 Two-Line System 4.3.3 Three-Line System 4.3.4 Four-Line System 4.3.5 Simulation Results

253 254 255 257 258 260

Transmission Line Analysis of Parallel Multilevel Interconnections 4.4.1 The Model 4.4.2 The Program DCMPVI 4.4.3 Numerical Simulations Using DCMPVI

264 264 268 268

xii

CONTENTS

4.5 Analysis of Crossing Interconnections 4.5.1 Mathematical Analysis 4.5.2 Simulation Results

280 280 284

4.6 Compact Expressions for Crosstalk Analysis 4.6.1 Distributed RC Model for Two Coupled Interconnections 4.6.2 Distributed RLC Model for Two Coupled Interconnections 4.6.3 Distributed RLC Model for Three Coupled Interconnections

293

4.7 Multiconductor Buses in GaAs High-Speed Logic Circuits 4.7.1 The Model 4.7.2 Lossless MBUS with Cyclic Boundary Conditions 4.7.3 Simulation Results

5

294 296 299 302 303 305 306

Exercises

309

References

310

Electromigration-Induced Failure Analysis

313

5.1 Electromigration in VLSI Interconnection Metallizations: Overview 5.1.1 Problems Caused by Electromigration 5.1.2 Electromigration Mechanism and Factors 5.1.3 Electromigration Under Pulsed DC and AC Conditions 5.1.4 Testing and Monitoring of Electromigration 5.1.5 General Guidelines for Testing Electromigration 5.1.6 Reduction of Electromigration

314 314 315 323 323 325 327

5.2 Models of IC Reliability 5.2.1 Arrhenius Model 5.2.2 Mil-Hdbk-217D Model 5.2.3 Series Model 5.2.4 Series–Parallel Model

328 329 329 330 330

5.3 Modeling of Electromigration Due to Repetitive Pulsed Currents 5.3.1 Modeling of Physical Processes 5.3.2 First-Order Model Development 5.3.3 Modeling Results for Direct Currents 5.3.4 Modeling Results for Pulsed Currents

331 332 333 337 340

CONTENTS

6

xiii

5.4 Electromigration in Copper Interconnections 5.4.1 Electromigration under DC Conditions 5.4.2 Electromigration under Pulsed DC Condition 5.4.3 Electromigration under Bipolar AC Conditions

341 341 342 342

5.5 Failure Analysis of VLSI Interconnection Components 5.5.1 Reduction of Components into Straight Segments 5.5.2 Calculation of MTF and Lognormal Standard Deviation 5.5.3 The Program EMVIC 5.5.4 Simulation Results Using EMVIC

344 344 348 349 350

5.6 Computer-Aided Failure Analysis 5.6.1 RELIANT for Reliability of VLSI Interconnections 5.6.2 SPIDER for Checking Current Density and Voltage Drops in Interconnection Metallizations

356 357 358

Exercises

360

References

362

Future Interconnections

371

6.1 Optical Interconnections 6.1.1 Advantages of Optical Interconnections 6.1.2 Systems Issues and Challenges 6.1.3 Material Processing Issues and Challenges 6.1.4 Design Issues and Challenges

371 372 373 374 374

6.2 Transmission Line Models of Lossy Optical Waveguide Interconnections 6.2.1 Lossy Waveguide with Single Propagating Wave 6.2.2 Equivalent Circuits for Waveguide Drivers and Loads 6.2.3 Lossy Waveguide in Inhomogenous Medium

375 375 378 379

6.3 Superconducting Interconnections 6.3.1 Advantages of Superconducting Interconnections 6.3.2 Propagation Characteristics of Superconducting Interconnections 6.3.3 Comparison with Normal Metal Interconnections

386 386

6.4 Nanotechnology Circuit Interconnections: Potential Technologies 6.4.1 Silicon Nanowires and Metallic Interconnections 6.4.2 Nanotube Interconnections 6.4.3 Quantum-Cell-Based Wireless Interconnections Exercises References

390 391 392 399 400 400

386 388

xiv

CONTENTS

APPENDICES

(ftp://ftp.wiley.com/public/sci_tech_med/ high_speed_VLSI)

Appendix 2.1

The Program IPCSGV for Calculating the Parasitic Capacitances for Single-Level Interconnections on GaAs-Based Using the Green’s Function Method

Appendix 2.2

The Program ICIMPGV for Calculating the Parasitic Capacitances and Inductances for Multilevel Interconnections on GaAs-Based (ftp://ftp.wiley.com/public/ sci_tech_med/high_speed_VLSI) Using the Network Analog Method

Appendix 2.3

The Program EPCSGM for Calculating the Electrode Parasitic Capacitances in a Single-Gate GaAs MESFET

Appendix 3.1

The Program PDSIGV for Calculating the Propagation Delays in the Single-Level Interconnections on GaAs-Based (ftp://ftp.wiley.com/public/sci_tech_med/high_speed_VLSI)

Appendix 3.2

The Program IPDMSR for Calculating the Propagation Delays in an Interconnection Driven by Minimum-Size Repeaters

Appendix 3.3

The Program IPDOSR for Calculating the Propagation Delays in an Interconnection Driven by Optimum-Size Repeaters

Appendix 3.4

The Program IPDCR for Calculating the Propagation Delays in an Interconnection Driven by Cascaded Repeaters

Appendix 4.1

The Program DCMPVI for Delay and Crosstalk Analysis of Multilevel Parallel (ftp://ftp.wiley.com/public/sci_tech_med/ high_speed_VLSI) Interconnections

Appendix 4.2

The Program SPBIGV for Signal Propagation Analysis of Bilevel Crossing Interconnections on GaAs-Based (ftp://ftp.wiley.com/public/sci_tech_med/high_speed_VLSI)

Appendix 5.1

The Program EMVIC for Electromigration-Induced Failure Analysis of (ftp://ftp.wiley.com/public/sci_tech_med/ high_speed_VLSI) Interconnection Components

INDEX

405

Preface Continuous advances in very large scale integrated (VLSI) circuit technology have resulted in complex chips that have millions of interconnections that integrate the components on the integrated circuit (IC) chip. Customer demand for higher speeds and smaller chips has led to the use of interconnections in multilevel and multilayer conﬁgurations. At present, the interconnections play the most signiﬁcant role in determining the size, power consumption, and clock frequency of a digital system. Parasitic capacitances, resistances, and inductances and their effects on the crosstalk and propagation delays associated with interconnections in high-density environments have become the major factors in the evolution of very high speed IC technology. It has been over 10 years since the ﬁrst edition of this book was published. During this period, several developments have taken place in the ﬁeld of VLSI interconnections such as the introduction of copper interconnections for VLSI applications, realization of the importance of including inductances in the delay and crosstalk models for very high speed circuits, further research on optical interconnections, and the possibility of realizing nanotechnology ICs using nanowires, nanotubes, and wireless interconnections. An attempt has been made to include these developments in the present second edition. This book focuses on the various issues associated with VLSI interconnections used for high-speed applications. These include parasitic capacitances and inductances, propagation delays, crosstalk, and electromigration-induced failure. It has been written as a textbook for a graduate-level course and as a reference book for practicing professionals who want to gain a better understanding of the several factors associated with high-speed interconnections. The reader is expected to have a basic understanding of electromagnetic wave propagation. The chapters in this book are designed such that they can be read independently of one another while, at the same time, being parts of one coherent unit. To maintain independence among the chapters, some material has been intentionally repeated. Several appropriate exercises are provided at the end of each chapter which are designed to be challenging as well as help the student gain further insight into the xv

xvi

PREFACE

contents of the chapter. The six chapters in this book can be described brieﬂy as follows. In Chapter 1, a few basic techniques and some advanced concepts regarding wave propagation in an interconnection are presented. Various types of interconnections employed in VLSI applications, including multilevel, multilayer, and multipath interconnections, are discussed. Advantages of copper interconnections and their fabrication techniques are reviewed. The method of images used to ﬁnd the Green’s function matrix is presented, and the method of moments, which can be used to determine the interconnection capacitances, is discussed. The even- and odd-mode capacitances for two and three coupled conductors are discussed, and the transmission line equations are derived. Miller’s theorem, which can be used to uncouple the coupled interconnections, is presented. An efﬁcient numerical inverse Laplace transformation technique is described. A resistive interconnection has been modeled as a ladder network. The various modes that can exist in a microstrip interconnection are described, and a quasi–transverse electromagnetic (TEM) analysis of slow-wave mode propagation in the interconnections is presented. The various measures of propagation delays, including delay time and rise time, are deﬁned. In Chapter 2, numerical techniques that can be used to determine the interconnection resistances, capacitances, and inductances on a high-density VLSI chip are discussed as well as the dependence of these parasitic elements on the various interconnection design parameters. Approximate formulas for calculating the parasitic capacitances for a few interconnection structures are presented. An algorithm to obtain the interconnection capacitances by the Green’s function method, where the Green’s function is calculated using the method of images, is presented. The Green’s function is also calculated by using the Fourier integral approach, and a numerical technique to determine the capacitances for a multilevel interconnection structure in the Si–SiO2 composite is presented. An improved network analog method to determine the parasitic capacitances and inductances associated with the high-density multilevel interconnections on the GaAs-based ICs is presented. Simpliﬁed formulas for the interconnection capacitances and inductances on the oxide-passivated silicon and semi-insulating gallium arsenide substrates are provided. A program called FastHenry, which can be used to determine the inductances associated with an interconnection structure, is described. A model for understanding the resistances for copper interconnections is presented. Source codes of a few computer programs to compute the parasitic capacitances and inductances are given in the appendices on the accompanying Ftp site. One of these programs has been extended to determine the electrode parasitic capacitances in a GaAs metal–semiconductor ﬁeld effect transistor (MESFET). In Chapter 3, numerical algorithms that can be used to calculate the propagation delays in the single and multilevel parallel and crossing interconnections are presented, and the dependence of the interconnection delays on the various interconnection design parameters is discussed. An analysis of interconnection

PREFACE

xvii

delays on very high speed VLSI chips using a metal–insulator–semiconductor microstripline model is presented. A computer-efﬁcient model based on the transmission line analysis of the high-density single-level interconnections on GaAs-based ICs is presented. The signal propagation in the single-, bi-, and trilevel high-density interconnections on GaAs-based ICs is studied, and a computerefﬁcient model of the propagation delays in the bilevel parallel and crossing interconnections on GaAs-based ICs is presented. A SPICE model for the lossless parallel interconnections modeled as multiple coupled microstrips is presented, and this model is extended to include lossy parallel and crossing interconnections. The high-frequency effects such as conductor loss, dielectric loss, skin effect, and frequency-dependent effective dielectric constant are studied for a microstrip interconnection. Compact expressions of propagation delays for the single and coupled interconnections modeled as RC and RLC circuits are provided. The active interconnections driven by several mechanisms are analyzed and a simpliﬁed model of the interconnection delays in multilayer ICs is presented. The source codes of a few computer programs used to determine the propagation delays in the normal and active interconnections are included in the appendices. In Chapter 4, the mathematical algorithms which can be used to study the crosstalk effects in the single and multilevel parallel and crossing interconnections are discussed and the dependence of the crosstalk effects on the various interconnection design parameters is studied. Crosstalk among neighboring interconnections is calculated by using a lumped-capacitance approximation. Crosstalk in very high speed VLSI circuits is analyzed by using a coupled multiconductor metal–insulator– semiconductor microstripline model for the interconnections. Single-level interconnections are investigated by the frequency-domain modal analysis, and a transmission line model of the crosstalk effects in the single-, bi-, and trilevel highdensity interconnections on the GaAs-based ICs is presented. This is followed by an analysis of the crossing bilevel interconnections on the GaAs-based ICs. Compact expressions for studying the crosstalk effects in the interconnections modeled as RC and RLC circuits are provided. The crosstalk effects in the multiconductor buses in the high-speed GaAs logic circuits are analyzed. The source codes of a few computer programs used to analyze the crosstalk effects are included in the appendices. In Chapter 5, the degradation of the reliability of an interconnection due to electromigration is discussed. First, several factors related to electromigration in the VLSI interconnections are reviewed. The basic problems that cause electromigration are outlined, the mechanisms and dependence of electromigration on several factors are discussed, testing and monitoring techniques and guidelines are presented, and the methods of reducing electromigration in the VLSI interconnections are brieﬂy discussed. Electromigration in copper interconnections is studied. The various models of IC reliability including the series model of failure mechanism in the VLSI interconnections are presented. A model of electromigration due to repetitive pulsed currents is developed. The series model has been used to analyze the electromigration-induced failure in the several VLSI interconnection components. The several computer programs available for studying electromigration in VLSI

xviii

PREFACE

interconnections are discussed brieﬂy. The source code of a computer program used to study electromigration-induced failure effects in the various interconnection components is included as an appendix. In Chapter 6, a few interconnection technologies that seem promising for future ICs are discussed. The advantages, issues, and challenges associated with the optical interconnections are discussed and a lossy waveguide interconnection is modeled as a transmission line. The propagation characteristics and the comparison of superconducting interconnections with the normal metal interconnections are presented. Various technologies that seem promising for nanotechnology circuits, including nanowires, nanotubes, and quantum-cell-based wireless interconnections, are brieﬂy discussed. The appendices for this book containing source codes can be found at: ftp://ftp.wiley.com/public/sci_tech_med/high_speed_VLSI. It should be noted that the various computer models presented in this book may not have been validated by experimental measurements and therefore should be used in computer-aided design programs with caution. In addition, the computer programs provided in the appendices are written for different computer systems and may need modiﬁcations to become suitable for the user’s system. Finally, in the Internet-based information age, it is necessary to give references to certain websites. Though these websites were active at the time of preparation of this manuscript, it is possible that they may become inactive in the future.

ACKNOWLEDGMENTS I would like to thank several individuals for their help and encouragement during the preparation of this book. I am grateful to Professor Kai Chang of Texas A&M University and editor of Microwave and Optical Technology Letters for inviting me to write this book. I am also thankful to Professor Martha Sloan of Michigan Technological University for her support. I also would like to thank my graduate students Yiren R. Huang, P. Joy Prabhakaran, Manish K. Mathur, Wei Xu, Matthew M. Leipnitz, and Jaikumar K. Parambil for their assistance with developing the computer programs and for obtaining the simulation results presented at several instances in this book. I am thankful to the Institute of Electrical and Electronics Engineers (United States) and the Institution of Electrical Engineers (United Kingdom) for their permission to use copyrighted material from over 30 papers published in IEEE Transactions, IEE Proceedings, and their other publications and I would like to take this opportunity to thank the authors of these papers whose work has been showcased in this book. I also owe special thanks to my wife, Sangita, for her constant love and encouragement. Finally, I express my deep appreciation to my son, Sumeet, and daughter, Rachna, for their patience and understanding during the preparation of this book.

PREFACE

xix

DISCLAIMER The information presented in this book is believed to be accurate and great care has been taken to ensure its accuracy. However, no responsibility is assumed by the author for its use and for any infringement of patents or other rights of third parties that may result from its use. Further, no license is granted by implication or otherwise under any patent, patent rights, or other rights. A. K. G. Houghton, Michigan

CHAPTER ONE

Preliminary Concepts and More In this chapter, some of the basic concepts and techniques used in this book are presented. The chapter is organized as follows: Various types of interconnections employed in very large scale integration (VLSI) applications are discussed in Section 1.1. Advantages and challenges posed by the copper interconnections and the techniques used for their fabrication are presented in Section 1.2. Method of images used to ﬁnd the Green’s function matrix in Chapter 2 is presented in Section 1.3. Method of moments used to determine the various interconnection capacitances in Chapter 2 is discussed in Section 1.4. Even- and odd-mode capacitances for two and three coupled conductors are discussed in Section 1.5. Transmission line equations are derived and coupled transmission lines are discussed in Section 1.6. Miller’s theorem used to uncouple the coupled interconnections in Chapter 3 is presented in Section 1.7. A computer-efﬁcient numerical inverse Laplace transformation technique used at several instances in this book is described in Section 1.8. A resistive interconnection has been modeled as a ladder network in Section 1.9. Various propagation modes that can exist in a microstrip interconnection are described in Section 1.10. A quasi–transverse electromagnetic (TEM) analysis of slow-wave mode propagation in interconnections is presented in Section 1.11. High-Speed VLSI Interconnections, Second Edition By Ashok K. Goel Copyright # 2007 John Wiley & Sons, Inc.

1

2

PRELIMINARY CONCEPTS AND MORE

Deﬁnitions of propagation delays used in the literature, including delay time and rise time, are presented in Section 1.12.

1.1

INTERCONNECTIONS FOR VLSI APPLICATIONS

Continuous advances in integrated circuit (IC) technology have resulted in smaller device dimensions, larger chip sizes, and increased complexity. There is an increasing demand for circuits with higher speeds and higher component densities. In recent years, growth of GaAs on silicon (Si) substrate has met with a great deal of interest because of its potential application in new hybrid technologies [1–11]. GaAs-on-Si unites the high-speed and optoelectronic capability of GaAs circuits with the low material cost and superior mechanical properties of the Si substrate. The heat sinking of such devices is better since the thermal conductivity of Si is three times more than that of GaAs. This technology is expanding rapidly from research to device and circuit development [12–15]. So far, the various IC technologies have employed metallic interconnections, and there is a possibility of using optical interconnections in the near future. Recently, the possibility of using superconducting interconnections is also being explored. Optical and superconducting interconnections are discussed in Chapter 6. 1.1.1

Metallic Interconnections: Multilevel, Multilayer, and Multipath Conﬁgurations

The VLSI chips require millions of closely spaced interconnection lines that integrate the components on a chip. As VLSI technology advanced to meet the needs of customers, it became necessary to use multilayer interconnections in two or more levels to achieve higher packing densities, shorter transit delays, and smaller chips. In this book, the term level will be used to describe conductors which are separated by an insulator and the term layer to describe different conductors tiered together in one level of interconnection, as shown in Fig. 1.1.1. In most cases, because of its low resistivity and silicon compatibility as shown in Table 1.1.1 [16], aluminum has been used to form metal interconnections. However, as device dimensions are decreased, current density increases, resulting in decreased reliability due to electromigration and hillock formation causing electrical shorts between successive levels of Al [17–20]. Tungsten has also been used for interconnects [21–23] and, sometimes, Al/Cu is used to solve problems characteristic of pure Al [1.24] though this choice has not been without problems [25, 26]. There have been several studies [27–34] aimed at reducing electromigration. All these studies have used layers of two or more metals in the same level of the interconnection. Some of the multilayer structures studied so far have been Al/Ti/Cu [28], Al/Ta/Al [30], Al/Ni [31], Al/Cr [32], Al/Mg [33], and Al/Ti/Si [34]. Coevaporation of Al–Cu–Ti, Al–Cu–Ti, Al–Cu–Co, and Al–Co has also been shown to decrease electromigration [27]. There

INTERCONNECTIONS FOR VLSI APPLICATIONS

3

FIGURE 1.1.1 Schematic of layered interconnection structures using (a) Ti layer used to match aluminum and silicon expansion coefﬁcients; (b) Ti or W layer on top of aluminum to constrain hillocks; (c, d) multiple layers of Ti or W alternated with aluminum.

have been many studies on the problem of hillock formation as well [16, 35–44]. One method of reducing these hillocks on silicon-based circuits has been to deposit a ﬁlm of WSi [36] or MoSi between Al and the silicon substrate. Complete elimination of hillocks is reported in studies where the VLSI interconnections were fabricated by layering alternately Al and a refractory metal (Ti or W) [16, 42–44]. Recently, in an attempt to solve the ‘‘interconnect problem,’’ that is, the problem of unprecedented high density of interconnections operating at extremely high speeds and carrying high current densities, a modiﬁed version of the traditional metallic interconnection called the ‘‘multipath interconnect’’ has been proposed [45]. The modiﬁed interconnection consists of using the concept of parallel processing by providing two or more paths between the driving gate and the loading

4

PRELIMINARY CONCEPTS AND MORE

TABLE 1.1.1

Resistivity and Expansion Coefﬁcients

Material

Resistivity (m cm)

Pure aluminum (bulk) Sputtered Al and Al/Si Sputtered Al/2% Cu/1% Si LPCVD aluminum Pure tungsten (bulk) CVD tungsten Evaporated/sputtered tungsten Ti (bulk) TiAl3 (bulk) CuAl2 (bulk–y phase) WAl12 Si SiO2

2.65 2.9–3.4 3.9 3.4 5.65 7–15 14–20 42.0 17–22 5–6 — — —

Thermal Expansion Coefﬁcient ( C1) 25.0 106 25.0 106 25.0 106 25.0 106 4.5 106 4.5 106 4.5 106 8.5 106 — — — 3.3 106 0.5 106

Melting Point ( C) 660 660 660 660 3410 3410 3410 1660 1340 591 647 — —

Source: From [16]. # 1985, by IEEE.

gate. A schematic of a three-section multipath interconnect (side view) connecting the driver and the load is shown in Fig. 1.1.2. These paths are stacked vertically isolated from one another by insulating layers between any two consecutive paths thereby taking the same area on the chip as a single-path interconnect. Depending on the number of paths, an array of such multipath interconnects could carry much higher currents on the chip. Furthermore, this interconnect structure could be built by an extension of the available microelectronics fabrication techniques.

FIGURE 1.1.2 Schematic of three-path multipath interconnection (side view) connecting driver and load on (a) semi-insulating substrate such as GaAs and (b) silicon substrate.

COPPER INTERCONNECTIONS

1.1.2

5

Optical Interconnections

As an alternative to electrical interconnections, optical interconnections have emerged in recent years which offer fast, reliable, and noise-free data transmission [46–50]. So far, they have been used for computer-to-computer communications and processor-to-processor interconnections. At this time, however, their applicability at lower levels of the packaging hierarchy, such as for module-to-module connections at the board level, chip-to-chip connections at the module level, and gate-to-gate connections at the chip level, is still under investigation. The principal advantages of optical interconnections over electrical connections are higher bandwidth, lower dispersion, and lower attenuation. Some of the problems with optical interconnections under investigation are size incompatibility with ICs, high power consumption, and tight alignment requirements.

1.1.3

Superconducting Interconnections

In recent years, the advent of high-critical-temperature superconductors has opened up the possibility of realizing high-density and very fast interconnections on siliconas well as GaAs-based high-performance ICs. The major advantages of superconducting interconnections over normal metal interconnections can be summarized as follows: (a) Signal propagation time on a superconducting interconnection will be much smaller as compared to that on a normal metal interconnection, (b) the packing density of the IC can be increased without suffering from the high losses associated with high-density normal metal interconnections, and (c) there is virtually no signal dispersion on superconducting interconnections for frequencies up to several tens of gigahertz.

1.2

COPPER INTERCONNECTIONS

To be able to produce high-speed ICs, it is always desirable to use interconnections that would allow rapid transmission of information, that is, signals among the various components on the chip. For the last 40 years, aluminum has been used almost exclusively to make metallic interconnection lines on ICs. More recently, aluminum–copper alloys have been used because they have been shown to provide better reliability than pure aluminum. In December 1997, in order to lower the resistance of metallic interconnections, IBM announced plans to replace aluminum with copper, a metal with lower resistivity of less than 2 m cm compared to that of about 3 m cm for aluminum. It is worth mentioning that while copper interconnections have been a hot topic in the semiconductor industry since the IBM announcement, the race to improve the aluminum interconnect technology has not slowed down. In fact, semiconductor companies are exploring new technologies for aluminum-based interconnections. These include ionized plasma deposition, hot aluminum physical vapor deposition (PVD), and aluminum damascene structures. It is expected that while advanced microprocessors and fast memory circuits may

6

PRELIMINARY CONCEPTS AND MORE

switch to copper interconnections, aluminum-based interconnections deposited by using the latest techniques will continue to coexist at least in the near future. While the semiconductor industry has known the potential advantages of using copper interconnects since the 1960s, it took over 30 years for it to overcome the associated challenges until it was announced in a paper on the complementary metal–oxide–semiconductor (CMOS) 7S technology presented at the Institute of Electrical and Electronics Engineers’ IEDM conference by IBM in December 1997. Following is a summary of the advantages of copper interconnects and the challenges in implementing this technology: 1.2.1

Advantages of Copper Interconnects

1. An obvious advantage of copper is its lower electrical resistivity compared with aluminum. In fact, copper interconnects offer 40% less resistance to electrical conduction than the corresponding aluminum interconnects, which results in speed advantages of as much as 15% in microprocessor circuits employing copper interconnects. 2. The phenomenon of electromigration that results in the movement of atoms and molecules in the interconnects under high-stress conditions of high temperatures and high current densities causing open- and short-circuit failures of interconnects through the formation of voids and hillocks is known to occur much less frequently in copper interconnects than in aluminum interconnects. That is why aluminum–copper alloys have been preferred over pure aluminum as the interconnect material. 3. Copper interconnects can be fabricated with widths in the range of 0.2 mm while it has been difﬁcult to reduce dimensions below 0.35 mm with aluminum interconnects. This reduction in interconnection dimensions allows much higher packing densities of the order of 200 million transistors per chip. 4. It has been claimed that the deposition of copper interconnects can be achieved with a potential cost saving of up to 30%, which translates into a saving of about 10–15% for the full wafer [51]. 1.2.2

Challenges Posed by Copper Interconnects

In the United States, a consortium of 10 leading chip-making semiconductor companies known as SEMATECH (Semiconductor Manufacturing Technology) has worked hard to overcome the challenges posed by the replacement of aluminum interconnects by copper interconnects. Following is a list of technical challenges that must be addressed and met within acceptable standards to fabricate copper-based IC chips [52]: 1. Copper is considered poisonous for silicon-based circuits. It diffuses rapidly into the active source, drain, and gate regions of transistors built on the silicon

COPPER INTERCONNECTIONS

7

substrate and alters their electrical properties affecting the functionality of the transistors. 2. In order to meet the above challenge alone, an entirely new fabrication process is required for implementation of copper interconnects. 3. Fabrication of copper interconnects requires the production and use of a large amount of ultrapure water, which is rather expensive. 4. The release of waste discharges containing copper to the environment must be handled very carefully. 1.2.3

Fabrication Processes for Copper Interconnects

As shown in Fig. 1.2.1, a conventional photolithographic process for depositing aluminum interconnects on the silicon substrate involves the following steps: 1. 2. 3. 4.

Deposit a layer of silicon dioxide insulator on the silicon wafer. Deposit a layer of metal on the silicon dioxide layer. Cover the metal layer by depositing a layer of photoresist on it. Project a shadow of the interconnect pattern (drawn on a reticle) on the photoresist layer by using ultraviolet rays and an optical projection system. 5. Develop the photoresist that was exposed to the ultraviolet light.

FIGURE 1.2.1 Conventional photolithographic process steps for depositing aluminum metallization on silicon substrate.

8

PRELIMINARY CONCEPTS AND MORE

6. Using proper chemicals, etch away parts of the metal layer that are not covered by the hardened photoresist. 7. Finally, remove the hardened photoresist, leaving the interconnect metal in the desired pattern on the silicon dioxide layer. Since copper can contaminate the silicon substrate and the silicon dioxide dielectric layer of an IC resulting in increased junction leakages and threshold voltage instabilities, barrier layers are required to isolate the copper interconnects from the substrate and the dielectric layer. The barrier layer, usually made from tungsten or titanium nitride, should be as thin as possible to minimize the resistance and to maximize the reliability of the copper interconnects. It is applied after the interconnect channels have been etched out in the dielectric layer by photolithography. The barrier layer is covered by a microscopic seed layer of copper to ease further deposition of copper on the entire wafer by electroplating. Finally, the excess copper is removed by a chemical–mechanical polishing process leaving the desired pattern of copper interconnects on the wafer. The various steps are shown in Fig. 1.2.2. Various techniques have been studied for deposition of copper interconnects on silicon-based circuits. These include chemical vapor deposition (CVD), electroless plating, and electrolytic plating [51]. In each case, the objective was to deposit very thin and even layers of copper interconnects in the horizontal direction and vias in

FIGURE 1.2.2

Various steps involved in depositing copper metallizations.

COPPER INTERCONNECTIONS

9

FIGURE 1.2.3 Schematic of (a) voids and (b) seams that may be formed during late stages of copper deposition.

the vertical direction for connecting interconnects in different levels. It was found that the CVD and electroless plating techniques encountered several problems during fabrication whereas electrolytic plating worked satisfactorily, resulting in even copper ﬁlms with a faster rate of deposition. 1.2.4

Damascene Processing of Copper Interconnects

At present, the damascene electroplating process is used frequently to make copper on-chip interconnects. The term ‘‘damascene’’ originates from the fact that a

FIGURE 1.2.4 Steps involved in depositing copper interconnections and vias using singledamascene process.

10

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.2.5 Steps involved in depositing copper interconnections and vias using dualdamascene process.

somewhat similar technique was used by the metallurgists of old Damascus to produce sharpest polished swords in the medieval era. In the world of semiconductor processing, this technique was initially used to form vias that are used to connect interconnects at different levels of an IC. In damascene processing, the patterns of interconnects or vias are formed ﬁrst by etching the oxide on the substrate. Then the seed layer is deposited on the patterned substrate/oxide. This is followed by copper electroplating which deposits inside and outside the patterned features. Special care is taken to avoid the formation of voids and seams (shown in Fig. 1.2.3) during the late stages of copper deposition. The excess copper is ﬁnally removed by the chemical– mechanical planarization process. The steps involved in making copper interconnects using the damascene process are shown in Fig. 1.2.4. This process is repeated several times to form interconnects and vias for a multilevel interconnect structure required on an IC chip. The process described above is called the ‘‘single’’ damascene process because it differs from the more widely used ‘‘dual’’ damascene process in which both the interconnects and the vias are ﬁrst patterned by etching of the substrate/oxide before the seed layer is formed and copper is deposited. It reduces the number of processing steps by avoiding one copper deposition step and one planarization step for each level of the interconnect structure. The steps involved in making copper interconnects using the dual damascene process are shown in Fig. 1.2.5.

1.3

METHOD OF IMAGES

The method of images can be used to ﬁnd the potential due to a given electric charge in the presence of conducting planes and dielectric surfaces. To illustrate this

METHOD OF IMAGES

11

FIGURE 1.3.1 Line charge r lying in medium of dielectric constant e1 at distance d above second medium of dielectric constant e2 .

method, let us consider a line charge r lying in a medium of dielectric constant e1 and at a distance d above a second medium of dielectric constant e2 , as shown in Fig. 1.3.1. At the interface of the two media, the following two boundary conditions must be satisﬁed: 1. The normal component of the electric ﬂux density (Dn ) is the same on the two sides of the interface. 2. The tangential component of the electric ﬁeld (Et ) is also the same across the interface. Using the coordinate system of Fig. 1.3.1, it means that at y ¼ 0 Dn1 ¼ Dn2

or

e1 Ey1 ¼ e2 Ey2

ð1:3:1Þ

and Ex1 ¼ Ex2

ð1:3:2Þ

The potential V due to an inﬁnite line charge ( r) in a medium of dielectric constant e at a distance r is given by V¼

r lnðr 2 Þ 4pe

ð1:3:3Þ

When a second dielectric is present, the real charge r produces image charges across the dielectric interface. If the observation point P is above the interface, that is, on the same side as the real line charge (see Fig. 1.3.2a), an image charge r1 will be at a distance d below the interface. With the real line charge at x ¼ 0 and y ¼ d,

12

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.3.2 (a) Observation point P on same side as real line charge. (b) Observation point P below dielectric interface.

the distance between the real charge and the observation point is given by qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ x2 þ ðy dÞ2

r¼

and with the image charge at x ¼ 0 and y ¼ d, the distance between the image charge and the observation point is given by ri ¼

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ x2 þ ðy þ dÞ2

Using Eq. (1.3.3), the potential at all points above the interface, that is, for y 0, will be V1 ¼

1 ½r lnðr 2 Þ þ r1 lnðri2 Þ 4pe1

Now since Ex1 ¼

@V1 @x

METHOD OF IMAGES

13

for y 0 Ex1 ¼

1 @ fr ln½x2 þ ðy dÞ2 þ r1 ln½x2 þ ðy þ dÞ2 g 4pe1 @x

or " # 1 2x 2x r þ r1 Ex1 ¼ 4pe1 x2 þ ðy dÞ2 x2 þ ðy þ dÞ2

ð1:3:4Þ

Similarly Ey1 ¼

@V1 @y

Therefore, for y 0 Ey1 ¼

1 @ fr ln½x2 þ ðy dÞ2 þ r1 ln½x2 þ ðy þ dÞ2 g 4pe1 @y

or " # 1 2ðy dÞ 2ðy þ dÞ r þ r1 Ey1 ¼ 4pe1 x2 þ ðy dÞ2 x2 þ ðy þ dÞ2

ð1:3:5Þ

If the observation point P lies below the dielectric interface, that is, in the medium with dielectric constant e2 (see Fig. 1.3.2b), then the real line charge r must be modiﬁed to take care of the effect of the dielectric interface. This modiﬁed charge, say r2, can be found in terms of r as shown below. The distance between the observation point and the charge r is again given by

r¼

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ x2 þ ðy dÞ2

The potential V2 below the interface is then given by V2 ¼

1 ½r lnðr 2 Þ 4pe2 2

Now, since Ex2 ¼

@V2 @x

14

PRELIMINARY CONCEPTS AND MORE

for y 0 Ex2 ¼

1 @ fr ln½x2 þ ðy dÞ2 g 4pe2 @x 2

or " # 1 2x r Ex2 ¼ 4pe2 2 x2 þ ðy dÞ2

ð1:3:6Þ

Similarly Ey2 ¼

@V2 @y

Therefore, for y 0 Ey2 ¼

1 @ fr ln½x2 þ ðy dÞ2 g 4pe2 @y 2

or " # 1 2ðy dÞ r Ey2 ¼ 4pe2 2 x2 þ ðy dÞ2

ð1:3:7Þ

Applying the continuity condition (1.3.2) to Eqs. (1.3.4) and (1.3.6), we get 1 2x r2 2x ¼ ½r þ r1 2 4pe2 x2 þ d 2 4pe1 x þ d2 From this, it follows that r þ r1 r2 ¼ e1 e2

ð1:3:8Þ

Applying the continuity condition (1.3.1) to Eqs. (1.3.5) and (1.3.6), we ﬁnd that e1 2d e2 r2 2d ¼ ðr þ r1 Þ 2 4pe1 4pe2 x2 þ d2 x þ d2 from which it follows that r þ r1 ¼ r2

ð1:3:9Þ

METHOD OF MOMENTS

15

Combining Eqs. (1.3.8) and (1.3.9), we get r þ r1 r r1 ¼ e1 e2 from which the image charges r1 and r2 can be found in terms of the real charge r and the dielectric constants e1 and e2 to be r1 ¼ r

e1 e2 e1 þ e2

r2 ¼ r

2e2 e1 þ e2

ð1:3:10Þ

ð1:3:11Þ

To ﬁnd the image of a charge in a grounded conducting plane, it is well known that the image charge has the same magnitude as the real charge but an opposite sign and that it lies as much below the ground plane as the real charge is above it.

1.4

METHOD OF MOMENTS

The method of moments is a basic mathematical technique for reducing functional equations to the matrix equations [53]. Consider the inhomogenous equation Lðf Þ ¼ g

ð1:4:1Þ

where L is a linear operator, f is a ﬁeld or response (the unknown function to be determined), and g is a source or excitation (a known function). We assume that the problem is deterministic, that is, there is only one solution function f associated with a given excitation g. Let us expand the function f in a series of basis functions f1 ; f2 ; f3 ; . . . ; fn in the domain of L as f ¼

X

an fn

ð1:4:2Þ

n

where the an are constants. The functions fn are called expansion functions or the basis functions. For exact solutions, Eq. (1.4.2) is usually an inﬁnite summation and the functions fn form a complete set of basis functions. For approximate solutions, Eq. (1.4.2) is usually a ﬁnite summation. Substituting Eq. (1.4.2) into Eq. (1.4.1) and using the linearity of the operator L, we have X n

an Lðfn Þ ¼ g

ð1:4:3Þ

16

PRELIMINARY CONCEPTS AND MORE

Now, deﬁning a set of weighting functions or testing functions w1 , w2 , w3 ; . . . in the range of L and taking the inner product with each wm , the result is X

an hwm ; Lfn i ¼ hwm ; gi

m ¼ 1; 2; 3; . . .

n

This set of equations can be written in matrix form as ½lmn ½an ¼ ½gm where ½lmn ¼ ½hwm; Lfn i and ½an and ½gm are column vectors. If the matrix ½lmn is nonsingular, then the matrix ½lmn 1 exists. The constants an are then given by ½an ¼ ½lmn 1 ½gm and the solution function f is given by Eq. (1.4.2) as f ¼

X

an fn ¼ ½lmn 1 ½gm ½fn

n

This solution may be exact or approximate depending upon the choice of functions fn and weighting functions wn . The particular choice wn ¼ fn is known as the Galerkin method. If the matrix ½lmn is of inﬁnite order, it can be solved only in special cases, for example, if it is diagonal. If the sets fn and wn are ﬁnite, then the matrix ½lmn is of ﬁnite order and can be inverted by known methods such as the Gauss–Jordan reduction method. In most problems of practical interest, the integration involved in evaluating lmn ¼ hwm ; Lfn i is usually difﬁcult to perform. A simple way to obtain approximate solutions is to require that Eq. (1.4.3) be satisﬁed at certain discrete points in the region of interest. This process is called a point-matching method. In terms of the method of moments, it is equivalent to using Dirac delta functions as the weighting functions. Another approximation useful for practical problems involves dividing the region of interest into several small subsections and requiring that the basis functions fn are constant over the areas of the subsections. This procedure, called the method of subsections, often simpliﬁes the evaluation of the matrix ½1mn . Sometimes, it is more convenient to use the method of subsections in conjunction with the point-matching method. One of the most important tasks in any particular problem is the proper choice of the functions fn and wn . The functions fn should be linearly independent and chosen so that some superposition (1.4.3) can approximate the function f reasonably accurately. The functions wn should also be linearly independent and chosen so that

EVEN- AND ODD-MODE CAPACITANCES

17

the products hwn ; gi depend on the relative independent properties of g. Some additional considerations while choosing the functions fn and wn are accuracy of the solution desired, ease of evaluation of the matrix elements, size of the matrix that can be inverted, and realization of a well-conditioned matrix.

1.5

EVEN- AND ODD-MODE CAPACITANCES

In this section, the even- and odd-mode capacitances associated with systems of two or three coupled conductors are discussed. 1.5.1

Two Coupled Conductors

Two coupled conductors of different dimensions lying in the same plane at a distance d above the ground plane are shown in Fig. 1.5.1. We are interested in ﬁnding the self and mutual (or coupling) capacitances for this system. In other words, we want to ﬁnd the capacitances between each conductor and the ground (denoted by C11 and C22 ) and the capacitance between the two conductors (denoted by C12 ). To simplify the analysis, the problem can be split into the even and odd modes. In the even mode, each conductor is assumed to be at 1 V potential with the same sign for each conductor. In the odd mode, the ﬁrst conductor is assumed to be at a þ1 V potential while the second conductor is kept at a 1 V potential. First, we will determine the even- and odd-mode capacitances for each conductor separately. In the even mode shown in Fig. 1.5.2, there are no electric ﬁeld lines at the center between the two conductors. Therefore, this plane can be treated as a magnetic wall which represents an open circuit to any mutual capacitance between the two

FIGURE 1.5.1 Two coupled conductors of different dimensions lying in same plane at distance d above ground plane.

18

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.5.2 (a) Electric ﬁeld lines for two conductors in even mode. (b) Equivalent circuit for two conductors in even mode.

conductors. Therefore, we can say that ðeÞ

ð1:5:1Þ

ðeÞ

ð1:5:2Þ

C1 ¼ C11 C2 ¼ C22 ðeÞ

ðeÞ

where C1 is the even-mode capacitance for the ﬁrst conductor while C2 is that for the second conductor. In the odd mode shown in Fig. 1.5.3, the plane of symmetry between the two conductors can be treated as a grounded electric wall. This represents a short circuit to the mutual capacitance C12 . Therefore, in this case ðoÞ

ð1:5:3Þ

ðoÞ

ð1:5:4Þ

C1 ¼ C11 þ 2C12 C2 ¼ C22 þ 2C12

EVEN- AND ODD-MODE CAPACITANCES

19

FIGURE 1.5.3 (a) Electric ﬁeld lines for two conductors in odd mode. (b) Equivalent circuit for two conductors in odd mode.

ðoÞ

ðoÞ

where C1 and C2 are the odd-mode capacitances for the ﬁrst and second conductors, respectively. The mutual capacitance C12 can be expressed in terms of ðoÞ ðeÞ C1 and C1 using Eqs. (1.5.1) and (1.5.3) as h i ðoÞ ðeÞ C12 ¼ 12 C1 C1 while the self-capacitances are given by Eqs. (1.5.1) and (1.5.2). 1.5.2

Three Coupled Conductors

As in the case of two conductors, the three-conductor case can also be treated by splitting it into the even and odd modes. In the even mode, each conductor is again assumed to be at a þ1 V potential. In the odd mode, one conductor is kept at a þ1 V potential while the other two conductors are assumed to be at 1 V potential. This means that when ﬁnding the odd-mode charge on the ﬁrst conductor, for example, the potentials on the second and third conductors are of the opposite sign to that on

20

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.5.4

Self- and mutual capacitances for three conductors.

the ﬁrst conductor. Figure 1.5.4 shows the self and mutual capacitances for the three conductors. These capacitances can be found in terms of the even- and odd-mode capacitances of the three conductors. In the even mode, ðeÞ

ðeÞ

C1 ¼ C11

ðeÞ

C2 ¼ C22

C3 ¼ C33

ð1:5:5Þ

In the odd mode, ðoÞ

C1 ¼ C11 þ 2C12 þ 2C13 ðoÞ

ð1:5:6Þ

C2 ¼ C22 þ 2C12 þ 2C23 ðoÞ

C3 ¼ C33 þ 2C13 þ 2C23 Solving these equations, we can ﬁnd that the mutual capacitances are given by ðeÞ

ðeÞ

ðeÞ

ðoÞ

ðoÞ

ðoÞ

ðeÞ

ðeÞ

ðeÞ

ðoÞ

ðoÞ

ðoÞ

C12 ¼ 14 ½C1 C2 þ C3 þ C1 þ C2 C3 C13 ¼ 14 ½C1 þ C2 C3 þ C1 C2 þ C3 ðeÞ

ðeÞ

ðeÞ

ðoÞ

ðoÞ

ðoÞ

C23 ¼ 14 ½C1 C2 C3 C1 þ C2 þ C3 The self-capacitances are given by Eqs. (1.5.5).

ð1:5:7Þ

TRANSMISSION LINE EQUATIONS

1.6

21

TRANSMISSION LINE EQUATIONS

A transmission line can be treated as a repeated array of small resistors, inductors, and capacitors. In fact, the transmission line theory can be developed in terms of alternating current (AC) circuit analysis, but the equations become extremely complicated for all but the simple cases [54]. It is more convenient to treat such lines in terms of differential equations which lead naturally to a wave equation which is of fundamental importance to electromagnetic theory in general. We can develop the differential equations for a uniform transmission line by a simple circuit analysis of its equivalent circuit, shown in Fig. 1.6.1, consisting of several incremental lengths and then taking the limit as the length of the increment approaches zero. The notations of voltage and current at some general points x and x þ x along the line are shown in Fig. 1.6.1. The parameters R, L, G, and C are the resistance, inductance, conductance, and capacitance values per unit length of the line, respectively. As x is changed, these values remain the same. We assume that the voltage and current are sinusoidal and that at any point x along the line the time variation of voltage is given by vx ¼ v0 ejot Now, if we apply Kirchhoff’s voltage law around the ﬁrst incremental loop in Fig. 1.6.1, we obtain vx ¼ ix R x þ ix ðjoLÞ x þ vxþx or vxþx vx ¼ ix ðR þ joLÞ x

FIGURE 1.6.1

Equivalent circuit for uniform transmission line.

ð1:6:1Þ

22

PRELIMINARY CONCEPTS AND MORE

In the above equations, R and L have been multiplied by x to get the actual values of resistance and inductance for an incremental section of length x. Now, the total current ix into the ﬁrst incremental section at x minus the total current ixþx into the next section at x þ x must be equal to the total current through the shunt capacitance C and the parallel resistance Rp , that is, ix ixþx ¼

vx vx þ Rp =x 1=ðjoC xÞ

or, setting 1=Rp ¼ G, the conductance per unit length, we get ixþx ix ¼ vx ðG þ joCÞ x

ð1:6:2Þ

In Eq. (1.6.1), the left-hand side represents the incremental voltage drop along the line denoted by vx. Dividing both sides of Eq. (1.6.1), we get vx ¼ ix ðR þ joLÞ x Similarly, Eq. (1.6.2) can be expressed as ix ¼ vx ðG þ joCÞ x Now, if x is made very very small, then the incremental voltage or current change per incremental distance becomes the corresponding derivative. Thus we get the two fundamental differential equations for a uniform transmission line, dvx ¼ ðR þ joLÞix dx

ð1:6:3Þ

dix ¼ ðG þ joCÞvx dx

ð1:6:4Þ

where all line parameters are per unit distance. These equations can be solved if they can be written in terms of one unknown (vx or ix ). An equation in terms of vx can be written by ﬁrst taking the derivative of Eq. (1.6.3) with respect to x to yield d2 vx dix ¼ ðR þ joLÞ 2 dx dx

ð1:6:5Þ

and then substituting Eq. (1.6.4) in Eq. (1.6.5) to get d 2 vx ¼ ðR þ joLÞðG þ joCÞvx ¼ g2 vx dx2

ð1:6:6Þ

MILLER’S THEOREM

23

where g2 ¼ ðR þ joLÞðG þ joCÞ

ð1:6:7Þ

Similarly, an equation in terms of ix can be obtained by ﬁrst differentiating Eq. (1.6.4) and then substituting Eq. (1.6.3) to yield d2 ix ¼ ðR þ joLÞðG þ joCÞix ¼ g2 ix dx2

ð1:6:8Þ

Equations (1.6.6) and (1.6.8) are the fundamental relationships governing wave propagation along a uniform transmission line. The symbol g as deﬁned by Eq. (1.6.7) is known as the propagation constant, that is, pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ g ¼ ðR þ joLÞðG þ joCÞ In general, g is a complex number. The real part of g gives the reduction in voltage or current along the line. This quantity, when expressed per unit length of the line, is referred to as the attenuation constant a given by a ¼ Re

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ðR þ joLÞðG þ joCÞ

For a transmission line with no losses, a ¼ 0, that is, a line with no losses has no attenuation. The imaginary part of g, when expressed per unit length of the line, is known as the phase constant b given by b ¼ Im

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ðR þ joLÞðG þ joCÞ

For a lossless line where R ¼ G ¼ 0, the phase constant becomes pﬃﬃﬃﬃﬃﬃ b ¼ o LC with dimensions of radians per meter in rationalized meter–kilogram–second (RMKS) units. Phase shift per unit length along the line is a measure of the velocity of propagation of a wave along the line, that is, v¼

1.7

o 1 ¼ pﬃﬃﬃﬃﬃﬃ b LC

MILLER’S THEOREM

Miller’s theorem is an important theorem which can be used to uncouple nodes in electric circuits. Consider a circuit conﬁguration with N distinct nodes 1, 2, 3,. . ., N

24

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.7.1 (a) Circuit conﬁguration with N distinct nodes. (b) Circuit conﬁguration equivalent to that shown in Fig. 1.7.1a.

as shown in Fig. 1.7.1a. The node voltages can be denoted by V1, V2 , V3 ,. . ., VN , where VN is zero because N is the reference node. Nodes 1 and 2 are connected by an impedance Zc . We assume that the ratio V2 =V1 is known or can be determined by some means. Let us denote this ratio by K, which, in general, can be a complex number. It can be shown that the conﬁguration shown in Fig. 1.7.1a is equivalent to that shown in Fig. 1.7.1b provided Z1 and Z2 have certain speciﬁc values. These values of Z1 and Z2 can be found by equating the currents leaving nodes 1 and 2 in the two conﬁgurations. The current I1 leaving node 1 through impedance Zc in conﬁguration (a) is given by I1 ¼

V1 V 2 1K V1 ¼ V1 ¼ Zc Zc =ð1 KÞ Zc

while the current leaving node 1 through impedance Z1 in conﬁguration (b) is given by V1 =Z1. Therefore, we conclude that Z1 ¼

Zc 1K

In a similar manner, the current I2 leaving node 2 through impedance Zc in conﬁguration (a) is given by I2 ¼

V 2 V1 1 ð1=KÞ V2 ¼ V2 ¼ Zc Zc =ð1 1=KÞ Zc

while the current leaving node 2 in conﬁguration (b) is V2 =Z2 . Therefore, the value of impedance Z2 should be Z2 ¼

Zc K ¼ Zc 1 1=K K 1

INVERSE LAPLACE TRANSFORMATION

25

Since conﬁgurations (a) and (b) have identical nodal equations, these are identical. However, we note that Miller’s theorem is useful only if the value of the ratio K can be determined by some independent means.

1.8

INVERSE LAPLACE TRANSFORMATION

In several cases, it is more convenient to solve the equations in the frequency domain, that is, the s domain, and then obtain the time-domain solution by an inverse Laplace transformation of the s-domain solution. Various techniques for numerical inverse Laplace transformation are available in the literature. The technique presented in this section is simple yet efﬁcient and can be easily incorporated in computer programs. It uses the Pade´ approximation and does not require the computation of poles and residues [55, 56]. The inverse Laplace transform of VðsÞ is given by vðtÞ ¼

1 2pjt

Z

cþj1

VðsÞest ds

ð1:8:1Þ

cj1

The variable t can be removed from est by the transformation z ¼ st

ð1:8:2Þ

and then using an approximation for ez. Substituting Eq. (1.8.2) in Eq. (1.8.1), we obtain 1 vðtÞ ¼ 2pjt

Z

c0 þj1

VðsÞez dz

ð1:8:3Þ

c0 j1

According to the Pade´ approximation, the function ez can be approximated by a rational function RN;M ðzÞ ¼

PN ðzÞ QM ðzÞ

ð1:8:4Þ

where PN ðzÞ and QM ðzÞ are polynomials of order N and M, respectively. Inserting Eq. (1.8.4) in Eq. (1.8.3), we obtain 1 ^vðtÞ ¼ 2pj

Z

c0 þj1

V c0 j1

z RN;M ðzÞ dz t

ð1:8:5Þ

where ^vðtÞ is the approximation for vðtÞ. The integral (1.8.5) can be evaluated by using residue calculus and choosing the path of integration along the inﬁnite arc

26

PRELIMINARY CONCEPTS AND MORE

either to the left or to the right. To ensure that the path along the inﬁnite arc does not contribute to the integral, M and N are chosen such that the function FðzÞ ¼ V

z RN;M ðzÞ t

ð1:8:6Þ

has at least two more poles than zeros. This gives Z

FðzÞ dz ¼ 2pj

X

ðresidue at poles inside closed pathÞ

ð1:8:7Þ

C

where the positive sign is used when the path C is closed in the left-half plane and the negative sign is applied when C is closed in the right-half plane. For N < M, we have M X Ki z zi i¼1

RN;M ðzÞ

ð1:8:8Þ

where zi are the poles of RN;M ðzÞ and Ki are the corresponding residues. Closing the path of integration around the poles of RN;M ðzÞ in the right-half plane, we get the basic inversion formula ^vðtÞ ¼

M z 1X i Ki V t t i¼1

ð1:8:9Þ

When M is even, we can write M h z i 1X i ^vðtÞ ¼ Re Ki0 V t t i¼1 0

ð1:8:10Þ

where M 0 ¼ M=2 and Ki0 ¼ 2Ki . When M is odd, M 0 ¼ ðM þ 1Þ=2 and Ki0 ¼ Ki for the residue corresponding to the real poles. The poles zi and residues Ki0 have been calculated with high precision and are used in the programs in this book. To summarize, for a given function VðsÞ in the s domain, the response vðtÞ at any time t can be obtained by the following steps: 1. Select appropriate values of N and M and take values of zi and Ki0 from the computed tables [55, 56]. 2. Divide each zi by t and substitute ðzi =tÞ for each s in VðsÞ. 3. Multiply each Vðzi =tÞ by the corresponding Ki0 and add the products. 4. Retain only the real part of the result in step 3 and divide by t.

RESISTIVE INTERCONNECTION AS LADDER NETWORK

27

Note that, because of division by t, the value of vðtÞ at t ¼ 0 cannot be calculated by the above procedure. However, either this value can be obtained by using the initial-value theorem or an approximate value can be found by selecting a very small initial value of t. The technique described above is suitable for the calculation of the system response to a nonperiodic excitation such as a step or an impulse.

1.9

RESISTIVE INTERCONNECTION AS LADDER NETWORK

It is well known that interconnections made of high-resistivity materials such as polycrystalline silicon (poly-Si) result in much higher signal delays than the lowresistivity metallic interconnections. However, in the past, poly-Si has remained a principal material for the second-level interconnections. In order to analyze highspeed signal propagation in resistive interconnections, it is important to understand their transmission characteristics. In this section, it will be shown that resistive interconnections can be modeled as ladder RC networks under open-circuit, shortcircuit, as well as capacitive loading conditions [57, 58]. Finally, the ladder approximation has been applied to a multipath interconnect to perform a ﬁrst-order analysis of the dependence of the propagation delays expected in such an interconnect on the number of paths. 1.9.1

Open-Circuit Interconnection

From transmission line theory [59], the open-circuit voltage transfer function of a resistive transmission line is given by V2 1 pﬃﬃﬃﬃﬃﬃﬃﬃﬃ ¼ V1 cosh sRC

ð1:9:1Þ

where R is the total line resistance and C is the total line capacitance including the capacitance due to the fringing ﬁelds as described by Ruehli and Brennan [60]. Using inﬁnite partial-fraction expansions [61], Eq. (1.9.1) can be written as " # 1 V2 1 4X 2k 1 ðkþ1Þ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ ¼ ¼ ð1Þ V1 cosh sRC p k¼1 ð2k 1Þ2 þ sRCð4=p2 Þ

ð1:9:2Þ

If v1 ðtÞ is a Dirac pulse, then the voltage v2 ðtÞ can be found easily by ﬁnding the inverse Laplace transforms of the terms on the right side of Eq. (1.9.2). If v1 ðtÞ is a unit step voltage, then V1 ¼ V0 =s (with V0 ¼ 1) and v2 ðtÞ can be obtained after a simple integration to be

v2 ðtÞ ¼ L

1

" !# X 1 1=s 4 ð2k 1Þ2 p2 t ðkþ1Þ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ ¼ 1 exp ð1Þ pð2k 1Þ 4RC cosh sRC k¼1

28

PRELIMINARY CONCEPTS AND MORE

or 4 1 1 1 4 p2 t=ð4RCÞ 1 9p2 t=ð4RCÞ 1 þ þ e e þ v2 ðtÞ ¼ p 3 5 7 p 3 ¼ 1 1:273 ep

2

t=ð4RCÞ

þ 0:424 e9p

2

t=ð4RCÞ

2

0:254 e25p t=ð4RCÞ þ ð1:9:3Þ

It should be noted that the expression (1.9.3) differs from the corresponding approximate expression in reference [57], 2

2

vout ðtÞ ¼ 1 1:172 ep t=ð4RCÞ þ 0:195 e9p t=ð4RCÞ 0:023 e25p

2

t=ð4RCÞ

ð1:9:4Þ

which was obtained by a ﬁnite partial-fraction expansion of an inﬁnite expansion of Eq. (1.9.1). It can be seen that the terms of second and higher orders in Eq. (1.9.4), which are particularly important at low values of time, are far from correct. A T network and the corresponding n-stage ladder network for an interconnection line are shown in Figs. 1.9.1a and b, respectively. In Fig. 1.9.1b, ri ¼ R=ðn þ 1Þ and ci ¼ C=n. Now, we need to determine the number of ladder stages required to generate the output voltage based on the transmission line model given by Eq. (1.9.3). Assuming unit step input, a comparison of the plots of the output voltage versus time for an open-circuited interconnection obtained by using Eq. (1.9.3), obtained by a numerical simulation of the T network and those obtained by

FIGURE 1.9.1 Representation of interconnection line as (a) T network and (b) n-stage ladder network. (From [54]. # 1983 by IEEE.)

RESISTIVE INTERCONNECTION AS LADDER NETWORK

29

FIGURE 1.9.2 Output voltage versus time for open resistive transmission line for unit step input voltage. (From [55]. # 1983 by IEEE.)

numerical simulations of the ladder network with different number of stages, is shown in Fig. 1.9.2. For the sake of comparison, the output voltage plot obtained by using the approximate expression (1.9.4) is also included in Fig. 1.9.2. It can be seen that the plot obtained by using Eq. (1.9.3) almost coincides with that obtained for the ladder network with 5 stages. In fact, there is negligible difference between the results for the 5- and 10-stage ladder networks. For an interconnection line loaded with a capacitance CL , the voltage transfer function can be easily obtained in the s domain, but its analytical inverse Laplace transformation is not possible. Therefore, lumped-circuit approximations have to be used. It can be shown that, for a wide range of CL =C values, a ﬁve-stage ladder network yields sufﬁcient accuracy. Thus, the conclusion for an open-circuit interconnection also holds for a capacitively loaded interconnection. 1.9.2

Short-Circuited Interconnection

For a short-circuited RC transmission line, the output current for a step input voltage V0 =s is given by 1 pﬃﬃﬃﬃﬃﬃﬃﬃﬃ I ¼ CV0 pﬃﬃﬃﬃﬃﬃﬃﬃﬃ sRC sinh sRC

ð1:9:5Þ

Using inﬁnite partial-fraction expansion [61], Eq. (1.9.5) can be written as "

1 1 2 X 1 ð1Þk I ¼ CV0 þ sRC RC k¼1 s þ ½p2 k2 =ðRCÞ

# ð1:9:6Þ

30

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.9.3 Output current versus time for short-circuited resistive transmission line for unit step input voltage. (From [55]. # 1983 by IEEE.)

The output current in the time domain can then be easily obtained by ﬁnding the inverse Laplace transforms of the terms on the right side of Eq. (1.9.6) to be iðtÞ ¼

V0 2 2 2 ½1 2 ep t=ðRCÞ þ 2 ep 4t=ðRCÞ 2 ep 9t=ðRCÞ þ R

ð1:9:7Þ

Assuming unit step input, a comparison of the plots of the output current versus time for a short-circuited interconnection obtained by using Eq. (1.9.7), obtained by a numerical simulation of the T network and those obtained by numerical simulations of the ladder network with different number of stages, is shown in Fig. 1.9.3. It can be seen that, for a short-circuited interconnection, at least 10 stages

FIGURE 1.9.4 Ten-stage RC ladder network approximation applied to each path of multipath interconnection.

PROPAGATION MODES IN MICROSTRIP INTERCONNECTION

31

FIGURE 1.9.5 Dependence of propagation delay on number of paths of multipath interconnection included in SPICE model of Fig. 1.9.4. Results obtained by simulation of multipath interconnection by semiconductor TCAD tool also shown.

are required in the ladder network to obtain good agreement with the analytical solution.

1.9.3

Application of Ladder Approximation to Multipath Interconnection

For this analysis, an n-path multipath interconnection on the GaAs substrate is considered and the 10-stage ladder network approximation is used for each path of the multipath interconnection. In other words, each path is represented by a ladder of RC combinations as shown in Fig. 1.9.4. As shown in this ﬁgure, the interconnection is driven by a 50- voltage source and is terminated by a 50- load. The symbols R1 , R2 , and Rn represent the total resistances of the ﬁrst, second, and nth paths of the interconnection whereas C1, C2 and Cn represent the total ground capacitances (including the fringing ﬁelds) of the ﬁrst, second, and the nth paths. In this analysis, the coupling capacitances between the consecutive paths have been ignored because essentially the same voltage signal is propagating along the different paths of the same interconnection. The dependence of the propagation delay on the number of paths included in the above model using SPICE is shown in Fig. 1.9.5. For the sake of comparison, this ﬁgure also includes the results obtained by simulation of the multipath interconnection by a semiconductor technological computer-aided design (TCAD) tool.

1.10

PROPAGATION MODES IN MICROSTRIP INTERCONNECTION

A resistivity–frequency mode chart of the metal–insulator–semiconductor (MIS) microstripline [62] is shown in Fig. 1.10.1, where d is the skin depth and r is the semiconductor resistivity. It can be seen from this ﬁgure that the propagation mode

32

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.10.1 Resistivity-frequency mode chart of MIS microstripline. (From [62]. # 1984 by IEEE.)

in the microstrip depends on the substrate resistivity and the frequency of operation. Figure 1.10.1 shows the following: 1. When the substrate resistivity is low (less than approximately 103 cm), the substrate acts like an imperfect metal wall having a large skin effect resulting in the skin effect mode. 2. When the substrate resistivity is high (greater than approximately 104 cm) then the substrate acts like an insulator and the dielectric quasi-TEM mode propagates. 3. For an MIS waveguide, the slow-wave mode propagates when the substrate is semiconducting and the frequency is low. The slow-wave mode results because, in the low-frequency limit (note that this frequency limit extends into the gigahertz range at certain substrate resistivities), the electric ﬁeld lines do not penetrate into the semiconductor whereas the magnetic ﬁeld lines can fully penetrate into it causing spatially separated storage of electric and magnetic energies. 1.11

SLOW-WAVE MODE PROPAGATION

In this section, a quasi-TEM analysis of slow-wave mode propagation in the micrometer-size coplanar MIS transmission lines on heavily doped semiconductors [63] is presented. The analysis includes metal losses as well as semiconductor losses. The quantities derived from the quasi-TEM analysis are compared with those

SLOW-WAVE MODE PROPAGATION

33

FIGURE 1.11.1 (a) Cross-sectional view and (b) plan view of micrometer-size coplanar MIS transmission lines. (From [63]. # 1986 by IEEE.)

measured experimentally for a system of four micrometer-size coplanar MIS transmission lines fabricated on Nþ silicon. 1.11.1

Quasi-TEM Analysis

The geometry of the microstructure MIS transmission lines used in this analysis is shown in Fig. 1.11.1. For the experimental results presented below, these structures consist of coplanar aluminum strips (fabricated by evaporating Al on SiO2) separated from antimony-doped Nþ silicon substrate of doping density Nd 3 1018 cm3 and electrical conductivity 80 ( cm)1 by a thin SiO2 layer. For the four transmission lines used in the experimental results, the wafer thickness d is 530 mm, the length l is 2500 mm, and the metal thickness t is 1 mm. The values of the other dimensions shown in Fig. 1.11.1 and the capacitance scaling factor used later in this analysis for each of the four lines are listed in Table 1.11.1. Because of the low impedance of the Nþ semiconductor, most of the electrical energy is conﬁned to the insulating layer immediately below the center conductor. However, because the semiconductor is a nonmagnetic material, the magnetic ﬁeld freely penetrates the Nþ substrate. This separation of the electric and magnetic energies results in the slow-wave mode propagation. For quasi-TEM propagation of the slow-wave mode of coplanar microstructure MIS transmission line, its equivalent circuit used in this analysis is shown in

34

PRELIMINARY CONCEPTS AND MORE

TABLE 1.11.1 Dimensions S, W, and h and Capacitance Scaling Factor K of Experimental lines Line 1 2 3 4

S

W

h

K

4.2 4.2 8.7 4.7

6.0 14.0 9.5 13.5

0.53 0.53 0.28 0.28

1.3 1.3 1.1 1.2

Source: From [65]. # 1987 by IEEE. Note: All dimensions are in micrometers.

Fig. 1.11.2. The inductance per unit length, L, is given by L¼

1 c2 C

ð1:11:1Þ air

where c is the phase velocity in vacuum and Cair is the capacitance per unit length of an equivalent air-ﬁlled transmission line. Here, Cair can be determined by conformal mapping [64] leading to the following expression for L: L¼

1 4c2 e0 F

ð1:11:2Þ

where e0 is the permittivity of free space and F is a geometric factor given approximately by [64]

F¼

8 pﬃﬃﬃ pﬃﬃﬃ > ln½2ð1 þ kÞ=ð1 kÞ > > > < p

0:707 k 1

> > > > :

0 k 0:707

p pﬃﬃﬃﬃ pﬃﬃﬃﬃ ln½2ð1 þ k0 Þ=ð1 k0 Þ

ð1:11:3Þ

FIGURE 1.11.2 ‘‘Slow-wave’’ mode equivalent circuit of micrometer-size coplanar MIS transmission line used in quasi-TEM analysis. (From [63]. # 1986 by IEEE.)

SLOW-WAVE MODE PROPAGATION

35

with k¼

S S þ 2W

ð1:11:4Þ

k0 ¼

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 1 k2

ð1:11:5Þ

In Fig. 1.11.2, the resistance Rm in series with L represents the correction due to the metal conductive losses. Its value in ohms per unit length is approximately equal to the effective resistance of the center conductor given by

Rm ¼

8 1 > > > > < sm tS > > > > :

for t dm ð1:11:6Þ

1 for t dm s m dm S

where sm and dm are the conductivity and skin depth of aluminum, respectively. The ground-plane contribution to Rm can be ignored because the current densities in it are much smaller than those in the center conductor. The resistance RL is inserted in the equivalent circuit of Fig. 1.11.2 to account for the loss caused by the longitudinal current ﬂowing in the Nþ semiconductor parallel to the current in the center conductor. Since the longitudinal semiconductor current ﬂows in addition to the longitudinal current in the metal, a parallel connection has been used. The value of RL is given by

RL ¼

1 s S dS S

ð1:11:7Þ

where sS and dS are the conductivity and skin depth of the Nþ semiconductor, respectively. Equation (1.11.7) is based on the assumption that the longitudinal electric ﬁeld under the center conductor decays exponentially in the vertical direction with decay constant dS . To account for the energy storage and loss associated with the transverse electric ﬁeld and current, the transverse capacitance Ct and transverse resistance Rt have been included in Fig. 1.11.2. The transverse capacitance per unit length is given approximately by

Ct ¼

ei e0 SK h

ð1:11:8Þ

36

PRELIMINARY CONCEPTS AND MORE

where ei is the dielectric constant of SiO2 and K is a geometric factor listed in Table 1.11.1 introduced to account for the capacitance associated with the fringing ﬁelds. Equation (1.11.8) is based on the assumption that most of the electric energy is stored in the dielectric layer under the center conductor. The value of the transverse resistance is given approximately by

Rt ¼

1 2sS F

ð1:11:9Þ

where F is the geometric factor given by Eq. (1.11.3). In this analysis, we have ignored the ﬁnite transverse capacitance through the air because its susceptance is very small compared with that of Ct and Rt in series. For a transmission line consisting of the circuit elements of Fig. 1.11.2, the complex propagation constant g and the complex characteristic impedance Z0 are given by g ¼ a þ jb ¼

Z0 ¼

Z00

þ

jZ000

pﬃﬃﬃﬃﬃﬃ ZY

ð1:11:10Þ

rﬃﬃﬃﬃ Z ¼ Y

ð1:11:11Þ

where

Z¼

1 1=RL þ 1=ðRm þ joLÞ

ð1:11:12Þ

Y¼

1 Rt þ 1=ðjoCt Þ

ð1:11:13Þ

and the quality factor Q and the ‘‘slowing factor’’ l0 =lg are given by b 2a

ð1:11:14Þ

l0 b ¼ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ lg o m0 e0

ð1:11:15Þ

Q¼

SLOW-WAVE MODE PROPAGATION

37

FIGURE 1.11.3 Contours of constant Q for transmission line 2. Dashed line corresponds to experiment parameters. (From [63]. # 1986 by IEEE.)

The quasi-TEM mode analysis presented above is valid only at frequencies which satisfy both f f1 and f f2 , where f1 ¼

f2 ¼

1 psS m0 ðW þ S=2Þ2 sS 2pe0 eS

ð1:11:16Þ

ð1:11:17Þ

The contours of constant Q for the transmission line 2 are shown in Fig. 1.11.3. This ﬁgure shows that, at frequencies satisfying f f1 and f f2 , the mode of propagation is the ‘‘slow-wave’’ mode because, in this region, the magnetic ﬁeld freely penetrates the substrate while the electric ﬁeld does not. When f2 < f < f1 , both transverse electric and magnetic ﬁelds freely penetrate the semiconductor substrate and the ‘‘dielectric quasi-TEM’’ is the mode of propagation. On the other hand, when f1 < f < f2 , neither ﬁeld penetrates the substrate and the mode of propagation is the ‘‘skin effect mode.’’ Using worstcase parameters for the four transmissions lines studied in this section, we can determine that f1 ¼ 120 GHz and f2 ¼ 12; 000 GHz. Therefore, all four lines satisfy the criteria for the slow-wave mode propagation and for validity of the quasi-TEM analysis.

1.11.2

Comparison with Experimental Results

The experimental results presented below are obtained by measuring the S parameters over the frequency range 1.0–12.4 GHz [63]. The attenuations of the

38

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.11.4 Dependence of attenuation on frequency for (a) line 1, (b) line 2, (c) line 3, and (d) line 4. Solid lines represent theoretical values obtained from quasi-TEM analysis. Symbols are experimental values. [63]. # 1986 by IEEE.)

four lines versus frequency are shown in Figs. 1.11.4a–d. Solid lines represent theoretical values obtained from the quasi-TEM analysis presented above. The real (Z00 ) and imaginary (Z000 ) parts of the characteristic impedance as functions of frequency for the four lines are shown in Figs. 1.11.5a–d. It can be seen that the characteristic impedances of all four lines are nearly real, of the order of 50 , and almost independent of frequency. The dependences of the ‘‘slowing factors’’ (l0 =lg ) on frequency for the four lines are shown in Figs. 1.11.6a–d, which also display the quality factor Q versus frequency. It can be seen that each of the four quality factors increases with frequency, reaching values in the range 3.6–4.3 at 12.4 GHz. It is obvious that there is excellent agreement between theory and experiments over the full frequency range from 1.0 to 12.4 GHz for all four transmission lines. It can be concluded from this close agreement that the slow-wave mode propagating on these micrometer-size MIS transmission lines is, in fact, a quasi-TEM mode and can therefore be analyzed by elementary techniques.

SLOW-WAVE MODE PROPAGATION

39

FIGURE 1.11.5 Dependence of real and imaginary parts of characteristic impedance on frequency for (a) line 1, (b) line 2, (c) line 3, and (d) line 4. Solid lines represent theoretical values obtained from quasi-TEM analysis. Symbols are experimental values. (From [63]. # by 1986 IEEE.)

In this analysis, we have included three loss mechanisms, namely metal loss, longitudinal semiconductor loss, and transverse semiconductor loss. It can be shown that the relative contribution of each loss mechanism in the above model can be approximately (within 1%) calculated by keeping the corresponding resistance in the circuit of Fig. 1.11.2 while setting the other two resistances to zero. The results for transmission line 2 are shown in Fig. 1.11.7. It can be seen that the metal loss contribution is dominant at frequencies below 25 GHz and decreases with increasing frequency though, even at 100 GHz, it accounts for nearly 20% of the total loss. It can also be noted that both the transverse and the longitudinal semiconductor losses increase with frequency though the transverse loss component is very small.

40

PRELIMINARY CONCEPTS AND MORE

FIGURE 1.11.6 Dependence of quality and slow-wave factors on frequency for (a) line 1, (b) line 2, (c) line 3, and (d) line 4. Solid lines represent theoretical values obtained from quasi-TEM analysis. Symbols are experimental values. (From [63]. # 1986 by IEEE.)

FIGURE 1.11.7 Relative contributions of three loss mechanisms for transmission line 2. (From [63]. # 1986 by IEEE.)

EXERCISES

1.12

41

PROPAGATION DELAYS

In the literature, three measures of propagation delays in an electric circuit are deﬁned [65]: Delay Time. The time required by the output signal (current or voltage) to reach 50% of its steady-state value. Rise Time. The time required by the output signal (current or voltage) to rise from 10 to 90% of its steady state value. Propagation Time. The time required by the output signal (current or voltage) to reach 90% of its steady-state value. EXERCISES E1.1 In the circuit shown below using an ideal voltage ampliﬁer of gain 0.5, determine the input resistance Rin .

E1.2 In the circuit shown below using an ideal voltage ampliﬁer of gain 10, determine the input capacitance Cin .

E1.3 Following the steps in Section 1.5, write the expressions for the even- and odd-mode capacitances for a system of four coupled conductors and solve them for the self and mutual capacitances for the four conductors. Comment on the accuracy of your results.

42

PRELIMINARY CONCEPTS AND MORE

E1.4 Following the steps in Section 1.5, write the expressions for the even- and odd-mode capacitances for a system of ﬁve coupled conductors and solve them for the self and mutual capacitances for the ﬁve conductors. Comment on the accuracy of your results. E1.5 Suggest situations where it will be preferable to model an interconnection as a lumped circuit or as a transmission line.

REFERENCES 1. R. M. Lum and J. K. Klingert, ‘‘Improvements in the Heteroepitaxy of GaAs on Si,’’ Appl. Phys. Lett., vol. 51, July 1987. 2. J. Varrio, H. Asonen, A. Salokatve, and M. Pessa, ‘‘New Approach to Growth of High Quality GaAs Layers on Si Substrates,’’ Appl. Phys. Lett., vol. 51, no. 22, Nov. 1987. 3. P. C. Zalm, C. W. T. Bulle-Lieuwma, and P. M. J. Maree, ‘‘Silicon Molecular Beam Epitaxy on GaP and GaAs,’’ Phillips Tech. Rev., vol. 43, May 1987. 4. N. Yokoyama, T. Ohnishi, H. Onodera, T. Shinoki, A. Shibatomi, and H. Ishikawa, ‘‘A GaAs 1K Static RAM Using Tungsten Silicide Gate Self-Aligned Technology,’’ IEEE J. Solid-State Circuits, Oct. 1983. 5. H. K. Choi, G. W. Turner, T. H. Windhorn, and B. Y. Tsaur, ‘‘Monolithic Integration of GaAs/AlGaAs Double-Heterostructure LED’s and Si MOSFET’s,’’ IEEE Electron Device Lett., Sept. 1986. 6. M. I. Aksun, H. Morkoc, L. F. Lester, K. H. G. Duh, P. M. Smith, P. C. Chao, M. Longerbone, and L. P. Erickson, ‘‘Performance of Quarter-Micron GaAs MOSFETs on Si Substrates,’’ Appl. Phys. Lett., vol. 49, Dec. 1986. 7. T. C. Chong and C. G. Fonstad, ‘‘Low-Threshold Operation of AlGaAs/GaAs Multiple Quantum Lasers Grown on Si Substrates by Molecular Beam Epitaxy,’’ Appl. Phys. Lett., vol. 27, July 1987. 8. W. Dobbelaere, D. Huang, M. S. Unlu, and H. Morkoc, ‘‘AlGaAs/GaAs Multiple Quantum Well Reﬂection Modulators Grown on Si Substrates,’’ Appl. Phys. Lett., July 1988. 9. W. T. Masselink, T. Henderson, J. Klem, R. Fischer, P. Pearah, H. Morkoc, M. Haﬁch, P. D. Wang and G. Y. Robinson, ‘‘Optical Properties of GaAs on (100) Si Using Molecular Beam Epitaxy,’’ Appl. Phys. Lett., vol. 45, no. 12, Dec. 1984. 10. J. B. Posthill, J. C. L. Tran, K. Das, T. P. Humphreys, and N. R. Parikh, ‘‘Observation of Antiphase Domains Boundaries in GaAs on Silicon by Transmission Electron Microscopy,’’ Appl. Phys. Lett., Sept. 1988. 11. R. Fischer, H. Morkoc, D. A. Neuman, H. Zabel, C. Choi, N. Otsuka, M. Longerbone, and L. P. Erickson, ‘‘Material Properties of High-Quality GaAs Epitaxial Layers Grown on Si Substrates,’’ J. Appl. Phys., vol. 60, no. 5, Sept. 1986. 12. L. T. Tran, J. W. Lee, H. Schichijo, and H. T. Yuan, ‘‘GaAs/AlGaAs Heterojunction Emitter-Down Bipolar Transistors Fabricated on GaAs-on-Si Substrate,’’ IEEE Electron Devices Lett., vol. EDL-8, no. 2, Feb. 1987. 13. N. El-masry, J. C. Tarn, T. P. Humphreys, N. Hamaguchi, N. H. Karam, and S. M. Bedair, ‘‘Effectiveness of Strained-Layer Superlattices in Reducing Defects in GaAs Epilayers Grown on Silicon Substrates,’’ Appl. Phys. Lett., vol. 51, no. 20, Nov. 1987.

REFERENCES

43

14. J. H. Kim, A. Nouhi, G. Radhakrishnan, J. K. Liu, R. J. Lang, and J. Katz, ‘‘High-Peak-Power Low-Threshold AlGaAs/GaAs Stripe Laser Diodes on Si Substrate Grown by Migration-Enhanced Molecular Beam Epitaxy,’’ Appl. Phys. Lett., Oct. 1988. 15. S. Sakai, S. S. Chang, R. V. Ramaswamy, J. H. Kim, G. Radhakrishnan, J. K. Liu, and J. Katz, ‘‘AlGaAs/AlGaAs Light-Emitting Diodes on GaAs-Coated Si Substrates Grown by Liquid Phase Epitaxy,’’ Appl. Phys. Lett., Sept. 26, 1988. 16. D. S. Gardner et al., ‘‘Layered and Homogeneous Films of Aluminum and Aluminum/ Silicon with Titanium and Tungsten for Multilevel Interconnects,’’ IEEE Trans. Electron Devices, vol. ED-32, no. 2, pp. 174–183, Feb. 1985. 17. K. C. Saraswat and F. Mohammadi, ‘‘Effect of Scaling of Interconnections on the Time Delay of VLSI Circuits,’’ IEEE Trans. Electron Devices, vol. ED-29, no. 4, p. 645, Apr. 1982. 18. M. H. Woods, ‘‘The Implications of Scaling on VLSI Reliability,’’ Seminar Notes from 22 Int. Reliability Physics Seminar. 19. E. Philofsky and E. L. Hall, ‘‘A Review of the Limitations of Aluminum Thin Films on Semiconductor Devices,’’ Trans. Parts Hybrids Packaging, vol. PHP-11, no. 4, p. 281, Dec. 1975. 20. R. A. Levy and M. L. Green. ‘‘Characterization of LPCVD Aluminum for VLSI Processing,’’ Proc. 1984 Symp. on VLSI Technology, The Japan Society of Applied Physics and the IEEE Electron Devices Society, p. 32, Sept. 1984. 21. K. C. Saraswat, S. Swirhun, and J. P. McVittie, ‘‘Selective CVD of Tungsten for VLSI Technology,’’ Proc. Symp. on VLSI Science and Technol., The Electrochemical Society, May 1984. 22. J. P. Roland, N. E. Handrickson, D. D. Kessler, D. E. Novy, Jr., and D. W. Quint, ‘‘TwoLayer Refractory Metal IC Process,’’ Hewlett-Packard J., vol. 34, no. 8, pp. 30–32, Aug. 1983. 23. D. L. Brors, K. A. Monnig, J. A. Fair, W. Coney and K. Saraswat, ‘‘CVD Tungsten—A Solution for the Poor Step Coverage and High Contact Resistance of Aluminum,’’ Solid State Technol., vol. 27, no. 4, p. 313, Apr. 1984. 24. F. M. d’Heurle, ‘‘The Effect of Copper Additions on Electromigration in Aluminum Thin Films,’’ Metallurg. Trans., vol. 2, pp. 693–689, Mar. 1971. 25. R. Rosenberg, M. J. Sullivan, and J. K. Howard, ‘‘Effect of Thin Film Interactions on Silicon Device Technology,’’ in Thin Films Interdiffusion and Reactions, J. M. Poeate, K. N. Tu, and J. W. Mayer, Eds., Electrochemical Society, New York: Wiley, 1978, pp. 48–54. 26. J. McBrayer, ‘‘Diffusion of Metals in Silicon Dioxide,’’ Ph. D. Dissertation, Stanford University, Stanford, CA, Dec. 1983. 27. J. K. Howard, J. F. White, and P. S. Ho, ‘‘Intermetallic Compounds of Al and Transitions Metals: Effect of Electromigration in 1–2 mm Wide Lines,’’ J. Appl. Phys., vol. 49, no. 7, p. 4083, July 1978. 28. S. S. Iyer and C. Y. Ting, ‘‘Electromigration study of the Al-Cu/Ti/Al-Cu Systems,’’ Proc. 1984 Int. Reliability Physics Symp., Apr. 1984. 29. J. P. Tardy and K. N. Tu, ‘‘Interdiffusion and Marker Analysis in Aluminum Titanium Thin Film Bilayers,’’ in Proceedings of the Electronic Materials Conference, T. C. Harman, Ed., Metallurgical Society of AIME, June 1984, p. 12.

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30. K. Hinode, S. Iwata, and M. Ogirima, ‘‘Electromigration Capacity and Microstructure of Layered Al/Ta Film Conductor,’’ Extended Abstr., Electrochem. Soc., vol. 83–1, p. 678, May 1983. 31. F. M. d’Heurle, A. Gangulee, C. F. Aliotta, and V. A. Ranieri, ‘‘Electromigration of Ni in Al Thin-Film Conductors,’’ J. Appl. Phys., vol. 46, no. 11, p. 4845, Nov. 1975. 32. F. M. d’Heurle and A. Gangulee, ‘‘Solute Effects on Grain Boundary Electromigration and Diffusion,’’ in The Nature and Behavior of Grain Boundaries, H. Hu, Ed., New York: Plenum, 1972, p. 339. 33. F. M. d’Heurle, A. Gangulee, C. F. Aliotta, and V. A. Ranieri, ‘‘Effects of Mg Additions on the Electromigration Behavior of Al Thin Film Conductors,’’ J. Electron. Mat., vol. 4, no. 3, p. 497, 1975. 34. F. Fishcher and F. Neppl, ‘‘Sputtered Ti-Doped Al-Si for Enhanced Interconnect Reliability,’’ Proc. 1984 Int. Reliability Physics Symp., IEEE Electron Devices and Reliability Societies, 1984. 35. C. J. Santoro, ‘‘Thermal Cycling and Surface Reconstruction in Aluminum Thin Films,’’ J. Electrochem. Soc., vol. 116, no. 3, p. 361, Mar. 1969. 36. K. C. Cadien and D. L. Losee, ‘‘A Method for Eliminating Hillocks in Integrated-Circuit Metallizations,’’ J. Vac. Sci. Technol., pp. 82–83, Jan.–Mar. 1984. 37. A. Rev, P. Noel, and P. Jeuch, ‘‘Inﬂuence of Temperature and Cu Doping on Hillock Formation in Thin Aluminum Film Deposited on Ti:W,’’ Proc. First Int. IEEE VLSI Multilevel Interconnection Conf., IEEE Electron Devices Society and Components, Hybrids, and Manufacturing Society, p. 139, June 1984. 38. P. B. Ghate and J. C. Blair, ‘‘Electromigration Testing of Ti:W/Al and Ti:W/Al-Cu Film Conductors,’’ Thin Solid Films, vol. 55, p. 113, Nov. 1978. 39. W. Barbee, Jr., in ‘‘Synthesis of Metastable Materials by Sputter Deposition Techniques,’’ in Synthesis and Properties of Metastable Phases, E. S. Machlin, and T. J. Rowland, Eds., The Metallurgical Society of AIME, Oct. 1980, p. 93. 40. T. W. Barbee, Jr., ‘‘Synthesis of Multilayer Structures by Physical Vapor Deposition Techniques,’’ in Multilayer Structures, G. Chang, Ed., New York: Academic, 1984. 41. W. Barbee, Jr., ‘‘Multilayers for X-ray Optical Applications,’’ in Springer Series in Optical Sciences, vol. 43: X-Ray Microscopy, G. Schmahl and D. Rudolph, Eds., Berlin, Heidelberg: Springer-Verlag, 1984, p. 144. 42. D. S. Gardner, T. L. Michalka, T. W. Barbee, Jr., K. C. Saraswat, J. P. McVittie, and J. D. Meindl, ‘‘Aluminum Alloys with Titanium, Tungsten, and Copper for Multilayer Interconnections,’’ Proc. 42nd Annual Device Res. Conf., The IEEE Electron Devices Society, p. IIB-3, June 1984. 43. D. S. Gardner, T. L. Michalka, T. W. Barbee, Jr., K. C. Saraswat, J. P. McVittie, and J. D. Meindl, ‘‘Aluminum Alloys with Titanium, Tungsten, and Copper for Multilayer Interconnections,’’ 1984 Proc. First Int. IEEE VLSI Multilevel Interconnection Conf., IEEE Electron Devices Society and Components, Hybrids, and Manufacturing Society, p. 68, June 1984. 44. D. S. Gardner, R. B. Beyers, T. L. Michalka, K. C. Saraswat, T. W. Barbee, Jr., and J. D. Meindl, ‘‘Layered and Homogeneous Films of Aluminum and Aluminum/Silicon with Titanium, Zirconium, and Tungsten for Multilevel Interconnects,’’ IEDM Tech. Dig., Dec. 1984.

REFERENCES

45

45. A. K. Goel, ‘‘Nanotechnology Circuit Design: The Interconnect Problem’’, Proc. IEEE NANO- 2001, Maui, Hawaii, Oct. 27–30, 2001. 46. J. W. Goodman, F. I. Leonberger, S. Y. Kung, and R. A. Athale, ‘‘Optical Interconnections for VLSI Systems,’’ Proc. IEEE, vol. 72, no. 7, pp. 850–866, July 1984. 47. L. D. Hutcheson, P. Haugen, and A. Hussain, ‘‘Optical Interconnects Replace Hardwire,’’ IEEE Spectrum, pp. 30–35, Mar. 1987. 48. J. W. Goodman, R. K. Kostuk, and B. Clymer, ‘‘Optical Interconnects: An Overview,’’ Proc. IEEE VLSI Multilevel Interconnection Conference, Santa Clara, CA, pp. 219–224, June 1985. 49. T. Bell, ‘‘Optical Computing: A Field in Flux,’’ IEEE Spectrum, Aug. 1986. 50. Special Issue on Optical Interconnections, Opt. Eng., Oct. 1986. 51. ‘‘Back to the Future: Copper Comes of Age.’’ Available: http://domino.research.ibm.com/ comm/wwwr_thinkresearch.nsf/pages/copper397.html. 52. ‘‘Meeting the Challenge of Making Semiconductor Chips with Copper Interconnects.’’ Available: http://www. ornl.gov/sci/nuclear_science_technology/cscp/rd/copper.htm. 53. R. F. Harrington, ‘‘Matrix Methods for Field Problems,’’ Proc. IEEE, vol. 55, no. 2, pp. 136–149, Feb. 1967. 54. L. V. Kantorovich and V. I. Krylov, Approximate Methods of Higher Analysis, 4th ed. translated by C. D. Benster, New York: Wiley, 1959, Chapter 4. 55. J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design, New York: Van Nostrand Reinhold, 1983, Chapter 10. 56. K. Singhal and J. Vlach, ‘‘Computation of Time Domain Response by Numerical Inversion of the Laplace Transform,’’ J. Franklin Inst., vol. 299, no. 2, pp. 109–126, Feb. 1975. 57. R. J. Antinone and G. W. Brown, ‘‘The Modeling of Resistive Interconnects for Integrated Circuits,’’ IEEE. J. Solid State Circuits, vol. SC-18, no. 2, pp. 200–203, Apr. 1983. 58. G. D. Mey, ‘‘A Comment on ‘The Modeling of Resistive Interconnects for Integrated Circuits,’’ IEEE J. Solid State Circuits, vol. SC-19, no. 4, pp. 542–543, Aug. 1984. 59. L. N. Dworsky, Modern Transmission Line Theory and Applications. New York: Wiley, 1979. 60. A. E. Ruehli and P. A. Brennan, ‘‘Accurate Metallization Capacitances for Integrated Circuits and Packages,’’ IEEE J. Solid State Circuits, vol. SC-8, pp. 289–290, Aug. 1973. 61. I. Gradshteyn and I. Ryzhik, Tables of Integrals, Series and Products, New York: Academic, 1980, p. 36. 62. H. Hasegawa and S. Seki, ‘‘Analysis of Interconnection Delay on Very High-Speed LSI/ VLSI Chips Using a MIS Microstrip Line Model,’’ IEEE Trans. Electron Devices, vol. ED-31, pp. 1954–1960, Dec. 1984. 63. Y. R. Kwon, V. M. Hietala, and K. S. Champlin, ‘‘Quasi-TEM Analysis of ‘Slow-Wave’ Mode Propagation on Coplanar Microstructure MIS Transmission Lines,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-35, no. 6, pp. 545–551, June 1987. 64. K. C. Gupta, R. Garg, and I. J. Bahl, Microstrip Lines and Slotlines. Dedham, MA: Artech House, 1979. 65. H. E. Kallman and R. E. Spencer, ‘‘Transient Response,’’ Proc. IRE, vol. 33, pp. 169–195, 1945.

CHAPTER TWO

Parasitic Resistances, Capacitances, and Inductances An electrical interconnection is characterized by three parameters: resistance, capacitance, and inductance. Series resistance is an important parameter and can be rather easily determined by the material and dimensions of the interconnection. Parasitic capacitances and inductances associated with interconnections in the highdensity environment of ICs have become the primary factors in the evolution of the very high speed IC technology. This chapter is organized as follows: A few general considerations regarding parasitic interconnection resistances are presented in Section 2.1. A few general considerations regarding parasitic interconnection capacitances are presented in Section 2.2. A few general considerations regarding parasitic interconnection inductances are presented in Section 2.3. Approximate formulas for calculating the parasitic capacitances for a few interconnection structures are presented in Section 2.4. An algorithm to obtain the interconnection capacitances by the Green’s function method which employs the method of moments in conjunction with a Green’s function appropriate for the geometry of the interconnections is presented in Section 2.5. The Green’s function is calculated using the method of multiple images. Green’s function is calculated using the Fourier integral approach and a numerical technique to determine the capacitances for a multilevel interconnection structure on the Si–SiO2 composite is presented in Section 2.6.

High-Speed VLSI Interconnections, Second Edition By Ashok K. Goel Copyright # 2007 John Wiley & Sons, Inc.

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PARASITIC RESISTANCES: GENERAL CONSIDERATIONS

47

An improved network analog method to determine the parasitic capacitances and inductances associated with the high-density multilevel interconnections on GaAs-based ICs is presented in Section 2.7. A few simpliﬁed formulas for calculating the interconnection capacitances on oxide-passivated silicon and semi-insulating gallium arsenide substrates are given in Section 2.8. A program called FastHenry for inductance extraction is discussed in Section 2.9. A resistance model for copper interconnections is presented in Section 2.10. In Section 2.11, the electrode parasitic capacitances in a GaAs metal– semiconductor ﬁeld effect transistor (MESFET) have been determined by an application of the program IPCSGV developed earlier in the chapter.

2.1

PARASITIC RESISTANCES: GENERAL CONSIDERATIONS

Resistance is a material property by which the metal resists the ﬂow of current. It is fairly easy to predict or calculate the resistance of a material once its dimensions are known. The following formula is used for the calculation of resistance for a slab of any conducting material: R¼r

L Wt

¼ RS

L W

ð2:1:1Þ

where L ¼ length of slab W ¼ width of slab t ¼ thickness of slab r ¼ resistivity of slab’s material The parameter Rs is called the sheet resistance of the material and is measured in ohms per square. The sheet resistance of any metal is a function of its thickness and the resistivity of the material. The material resistivity is a function of the chemical composition of the material and the density of impurities in that material. The process of resistance extraction may be a fairly simple task. With prior knowledge of the interconnection layout of a circuit, any circuit simulator may be able to calculate the overall resistance with very little error. However, there are important considerations that need to be kept in mind for reducing and managing the onchip resistances: 1. The use of copper interconnections will certainly complicate the resistance calculation process. This is because, as discussed in Chapter 1 and shown in Fig. 2.1.1, it is necessary for copper to have a shielding metal to prevent it from poisoning the silicon substrate. The shield material is however not laid evenly as it is required to be thicker at some circuit locations than at others,

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FIGURE 2.1.1

Shielding layer in copper interconnection structure.

such as at contacts and vias. Accurate extraction must take this shield or seed layer into account. 2. When the frequency of operation is increased, metals display a phenomenon known as skin effect. Skin effect is a tendency for the alternating current to ﬂow near the outer surface of a solid electrical conductor such as metal wire at frequencies above the audio range. The effect becomes more and more pronounced as the frequency is increased. The skin effect increases the effective resistance of a wire at moderate to high frequencies, as shown in Fig. 2.1.2. Skin effect becomes crucial only when the width and thickness of the conductor exceed twice the material’s skin depth. The skin effect must be modeled into the resistance extraction tools for the high-frequency circuits. 3. Full scaling, that is, reducing all dimensions of an interconnection, increases the metal’s sheet resistance mainly due to the reduction in its thickness. The only solution for this is to try and use selective scaling or keep the thickness constant. However, this makes the process of scaling more complex and would increase the fringe capacitances as well as the interwire capacitances.

FIGURE 2.1.2 Approximate frequency dependence of rise of interconnection resistance due skin effect.

PARASITIC RESISTANCES: GENERAL CONSIDERATIONS

49

Another option would be to ﬁnd materials with lower sheet resistance such as copper or some silicides. 4. The resistance of local interconnections grows linearly with the scaling factor. This is more so with global interconnections which actually grow longer with the scaling process. One solution is to use multilevel interconnections, which tend to reduce the wire lengths and allow straight connections between interconnections on two levels. Another important consideration is to use thicker and wider upper layers for global interconnections. 5. It is also necessary to reduce the contact resistances by avoiding the use of an excessive number of contacts and vias by making larger holes. Making holes tends to encourage current crowding around the perimeters of the holes. 6. The current densities at different points in an interconnection may be different due to a phenomenon called electromigration, discussed in Chapter 5. This phenomenon refers to the transport of metal ions and molecules in a metal line due to a direct current running through it for long periods of time, especially under high-stress conditions such as high current densities and high temperature. Electromigration can cause the interconnection to break open or to short circuit with another neighboring interconnection. The formation of voids and hillocks due to electromigration can be observed using scanning electron microscopy of an interconnection line subjected to high currents for long periods of time. The growth of a void formed by electromigration in an interconnection line with time is shown schematically in Fig. 2.1.3. The rate of electromigration in an interconnection depends on various material properties such as crystal structure in addition to temperature and current density. Overall, electromigration is the result of a vicious cycle in the sense that

FIGURE 2.1.3

Growth of electromigration-induced void in interconnection line with time.

50

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

high current density speeds up the electromigration process, which further increases current density due to an effective decrease of line width due to the formation of voids. This process also increases the overall resistance of the interconnection line.

2.2

PARASITIC CAPACITANCES: GENERAL CONSIDERATIONS

The dynamic response of a chip is a strong function of the capacitances associated with the transistors and gates in the circuit and the parasitic resistances and capacitances associated with the interconnection lines present in the circuit layout. Until the recent past, the circuit delay was mostly due to the transistor design characteristics and, for this reason, much effort has been put into the scaling of devices. At present, the propagation delays in an IC result primarily from the interconnection capacitances and the device and interconnection resistances. These are usually referred to as RC delays. An accurate model of the capacitances must include the contribution of the fringing ﬁelds as well as the shielding effects due to the presence of neighboring conductors. In the literature, several numerical techniques have been presented that can be used to characterize the interconnection lines though with limited applications. For example, the Schwarz–Christoffel conformal mapping technique [1] can be used to obtain exact results in terms of elliptic integrals for a symmetric two-strip conductor; for more than two strip conductors or for asymmetric two-strip conductors, the method becomes very cumbersome and signiﬁcant results cannot be obtained. The technique employing Galerkin’s method [2] in the spectral domain uses a Fourier series which becomes quite complicated for mixed or inhomogenous dielectric multiconductor structures. The Green’s function integral equation technique [3] is suitable for conductors of rectangular or annular shapes but becomes extremely difﬁcult for irregular geometric shapes. The ﬁnite-element method [4] and the ﬁnitedifference method [5] involve determination of the charge distributions on the conductor surfaces and can be applied to several conductor geometries. The network analog method, evolved from the ﬁnite-difference representation of partial differential equations [6], has been used for ﬁnite substrates in two dimensions [7], open substrates in three dimensions [8, 9], and lossy, anisotropic and layered structures [10–14]. In the past, capacitance models have been developed for IC metallization wires [15–17], and the system of equations for inﬁnite printed conductors has been solved [18–20]. There has also been reported work on systems of conductors with ﬁnite dimensions [21–27]. According to the semiconductor industry association’s roadmap, the RC wiring delay will increase by over 900% from the 0.35- to the 0.l-mm-generation ICs. During the same time interval, gate delays are expected to drop from about 70 ps to about 20 ps while the clock period will reduce by nearly 70%. As the interconnection is scaled with each technology generation, several trade-offs are made. In order to reduce the interconnection resistance and improve its electromigration properties, the thickness of the metal is kept fairly constant, that is, it is not scaled with its pitch.

PARASITIC CAPACITANCES: GENERAL CONSIDERATIONS

51

FIGURE 2.2.1 Electric ﬁeld lines that result in parallel-plate capacitance of interconnection line on silicon substrate (side view).

The increasing aspect ratio (thickness/width) results in larger coupling capacitances and more crosstalk among the interconnections (see Chapter 4 for a discussion of crosstalk). This problem worsens as the number of interconnection levels is increased with almost every new generation. It is obvious that interconnection capacitance characterization is an important aspect of current and future process development as well as circuit design. In order to give the circuit designers an accurate assessment of the speed and crosstalk issues, parasitic capacitances associated with interconnections must be understood very well. In general, there are three types of capacitances observed in an interconnection layout and all of these are important to the overall capacitance extraction. 2.2.1

Parallel-Plate Capacitance

It is known that most of the total interconnection capacitance is accounted for by parallel-plate capacitances though their relative contribution to the total capacitance decreases as the interconnection dimensions are scaled down. In silicon-based circuits, as shown in Fig. 2.2.1 the interconnection layout usually forms a parallelplate structure with the underlying silicon substrate separated by a dielectric layer usually made of silicon dioxide, and the parallel-plate capacitance is given by WL ð2:2:1Þ CPP ¼ eox tox where L and W are the length and width of the interconnection line, respectively, whereas tox and eox are the thickness and dielectric constant of the oxide layer, respectively. For circuits built on a resistive substrate such as GaAs (which is several thousand times more resistive than silicon), an oxide layer is not required and tox and eox are replaced by the thickness and dielectric constant of the GaAs substrate itself. 2.2.2

Fringing Capacitances

For any parallel-plate interconnection structure, there are always electric ﬁeld lines that emerge from the edges of the interconnection to form the so-called fringing

52

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.2.2

Fringing ﬁeld lines of interconnection line on silicon substrate (side view).

ﬁelds as shown in Fig. 2.2.2. These fringing ﬁelds increase with the circumference and thickness of the interconnection line and add to the overall capacitance of an interconnection structure. Relative contribution of the fringing ﬁelds to the total interconnection capacitance increases as the interconnection dimensions are scaled down. 2.2.3

Coupling Capacitances

In an interconnection layout consisting of two or more interconnections, as shown in Fig. 2.2.3, there are eletric ﬁeld lines and hence capacitances that exist among the interconnections. These capacitances that exist between any pair of interconnections are called coupling or mutual capacitances. These coupling capacitances are the major cause of crosstalk among the interconnections due to which the signal integrity is severely distorted due to an increase in noise.

2.3

PARASITIC INDUCTANCES: GENERAL CONSIDERATIONS

The CMOS and other circuits consist of both active and passive devices. Active devices are the transistors while passive devices are the interconnection structures that connect the transistors and gates in the circuit. These interconnections are mostly made of a metal such as aluminum and copper. In addition to its resistance, each interconnection has capacitances to the substrate and to the neighboring

FIGURE 2.2.3 Electric ﬁeld lines resulting in coupling capacitances among interconnection lines on same level or different levels (side view).

PARASITIC INDUCTANCES: GENERAL CONSIDERATIONS

53

interconnections in the same level as well as to the interconnections in other levels. Furthermore, each interconnection also has self-inductance and mutual inductance caused by magnetic couplings of the interconnections. Until a few years ago, the gate parasitics of transistors were much larger than the interconnection parasitic impedances due to their relatively large sizes. The interconnection could be modeled as a short circuit and its impedance was ignored. Over the years, continuous scaling of the minimum gate feature size has increased the chip performance tremendously and reduced the cost of production. At the same time, it has reduced the gate capacitances, making the interconnection capacitances more comparable. Furthermore, decreasing cross-sectional areas and increasing lengths of the interconnection wires have signiﬁcantly increased their resistances. The design methodologies used to reduce the time delays on the chip have concentrated on reducing the RC time constants of the interconnection lines. More recently, this has been achieved fairly successfully by replacing aluminum with copper as the interconnection material to reduce the line resistance, and breakthroughs in the use of ultra low-k dielectrics in the place of silicon dioxide have helped reduce the interconnection capacitance. So far, on-chip inductances have largely been ignored in the interconnection models. Currently ICs are designed for high clock frequencies with much faster signal rise and fall times. Considering the use of wider interconnections for power/ ground buses and with faster rise times, the on-chip inductances can no longer be ignored [28–32]. These inductances lead to several undesirable effects, such as increased ringing, increased crosstalk, and worse power/ground bounce. In order to optimize the circuit performance, it is important to understand the dependences of these inductances on the various interconnection design parameters. 2.3.1

Self and Mutual Inductances

Each interconnection line has an associated self-inductance as well as a mutual inductance with respect to each of the surrounding interconnection lines. Both self and mutual inductances are loop quantities and can be determined only if the current loop is known exactly. The self-inductance of a loop is deﬁned as the ratio of the magnetic ﬂux passing through the loop to the value of the loop current. The mutual or coupling inductance of a (victim) loop with respect to another (aggressor) loop is deﬁned as the ratio of the magnetic ﬂux passing through the victim loop caused by the current in the aggressor loop to the aggressor current. These magnetic ﬂuxes that give rise to the self and mutual inductances are shown in Fig. 2.3.1. The magnetic interactions that takes place among the current-carrying conductors can be decomposed into three effects that take place concurrently: 1. Currents ﬂowing through conductors create magnetic ﬁelds (Ampere’ law).

54

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.3.1 loops.

Magnetic ﬁelds that result in self and mutual inductances for two coupled

2. Time-varying magnetic ﬁelds create induced electric ﬁelds (Faraday’ law). 3. Induced electric ﬁelds exert forces on the electrons in the conductors and cause electric voltage drops. These three effects may be combined to state that a voltage drop is produced in the victim loop b due to a time-variant current ﬂowing in a loop a as shown in Fig. 2.3.2. It can be shown that the resulting induced voltage in loop b is given by

Vb ¼ Lba

dIa dt

ð2:3:1Þ

where Lba is the mutual inductance between loops a and b and Ia is the current ﬂowing through loop a. For the special case where loops a and b are the same, the coefﬁcient Laa becomes the self-inductance of loop a.

FIGURE 2.3.2

Voltage induced in loop b by time-variant current in loop a.

PARASITIC INDUCTANCES: GENERAL CONSIDERATIONS

2.3.2

55

Partial Inductances

Calculation of the loop inductances for large-scale ICs can prove to be cumbersome and uneconomical in several ways. Two most signiﬁcant problems in the calculations are as follows: 1. Need to know the current loops, that is, the return paths of the currents a priori, especially since these return paths have not been deﬁned in the VLSI circuits. 2. The fact that a current can take several return paths. To overcome these problems, the concept of partial inductances was developed by Rosa and was introduced to the circuit-modeling and analysis community by Ruehli. Since the actual current loops are not known, partial inductance is deﬁned in terms of the magnetic ﬂux created by the current of one aggressor segment through the virtual loop that the victim segment forms with inﬁnity, as shown in Fig. 2.3.3. It can be shown that the total self and mutual loop inductances are equivalent to the sums of the partial self and mutual inductances of the segments that form all the loops in the system. In other words, the relationship between the loop and partial inductances is given by Lab;loop ¼

XX i

sij Lij;partial

ð2:3:2Þ

j

where i and j represent segments of loops a and b, respectively. In Eq. (2.3.2), the coefﬁcients sij are 1 if one of the currents in segments i and j is ﬂowing opposite to the direction assumed when the coupling partial inductance Lij;partial was computed and is þ1 otherwise. Thus, by deﬁning each current segment as forming its own return loop with inﬁnity, partial inductances are used to represent the total loop interactions without prior knowledge of the actual current loops. 2.3.3

Methods for Inductance Extraction

Over the years, several models have been developed to calculate the self and mutual inductances. All models make a trade-off between computational efﬁciency and

FIGURE 2.3.3 Illustration of partial inductances.

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

accuracy and choose between speciﬁc two-dimensional (2D) models versus the general three-dimensional (3D) inductance models. Advocates of the 2D models insist that the return currents are equal and opposite to the interconnection currents and the inductances can therefore be extracted by using simpler 2D models which greatly limit the complexity of the problem by using several approximations and hence are more computer efﬁcient though less accurate. The users of the 2D models assert that the sensitivity of a signal waveform is rather low to errors in the inductance values, particularly for the propagation delay and rise time analyses. It is claimed that the errors in propagation delay and rise times are below 9.4 and 5.9%, respectively, assuming a 30% relative error in the extracted inductance values and that this level of error may be acceptable when compared to the corresponding errors of 51 and 71% in propagation delay and rise times when using an RC model, that is, without using the inductances at all. On the other hand, the 3D model advocates claim that the return current paths in ICs are fundamentally unknown and employ sophisticated analysis methods to cope with the increased complexity of these models which are more accurate though less computer efﬁcient. The biggest advantage of 3D modeling techniques lies in the fact that they provide a way to go around the need to know the current return paths a priori. The 3D ﬁeld solvers employ ﬁnite-difference or ﬁnite-element methods to the governing Maxwell equations which represent one of the most elegant and concise ways to state the fundamentals of electricity and magnetism. Starting from the Maxwell equations, one can develop the working relationships in terms of the electric and magnetic ﬁelds or the current density distributions in a complex IC interconnection layout. This approach generates a global 3D mesh for all parts of the interconnection structure and the surrounding space, causing the number of unknowns to increase dramatically. There are many commercially available 3D ﬁeld solvers for inductance extraction in the market. The exact analysis and extraction methods employed in these solvers may vary widely, but the underlying principles are almost always based on the steps mentioned above.

FIGURE 2.3.4 Dependence of propagation delays on interconnection lengths in range 50 nm–10 mm using RC and RLC delay models [33].

APPROXIMATE FORMULAS FOR CAPACITANCES

57

FIGURE 2.3.5 Dependence of propagation delays on interconnection widths in range 50 nm–1 mm using RC and RLC delay models [33].

2.3.4

Effect of Inductances on Interconnection Delays

The relative effects of including inductances in the interconnection delay models have been studied recently for a system of ﬁve single-level interconnections [33]. Propagation delays obtained by using the approximate RC and RLC models have been compared as functions of the interconnection lengths, interconnection widths, and interconnection separations, as shown in Figs. 2.3.4, 2.3.5, and 2.3.6, respectively. It is clear from these ﬁgures that the RLC delays signiﬁcantly exceed the RC delays in all cases. These results further demonstrate the importance of including on-chip inductances in the chip design models. 2.4

APPROXIMATE FORMULAS FOR CAPACITANCES

In order to accurately determine the interconnection capacitances on the VLSI circuits, 2D and 3D effects must be taken into account. This requires rigorous

FIGURE 2.3.6 Dependence of propagation delays on interconnection separations in range 50 nm–1.25 mm using RC and RLC delay models [33].

58

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.4.1 Schematic of (a) single line on conducting ground plane, (b) two lines on ground plane, (c) three lines on ground plane, and (d) single plate of ﬁnite dimensions on ground plane. (From [23]. # 1983 by IEEE.)

numerical analysis which can be too time consuming when used in the computeraided design (CAD) programs. Therefore, approximate formulas to estimate the interconnection capacitances are sometimes desirable. This section presents such empirical formulas suggested by Sakurai and Tamaru [23] for a few interconnection structures. 2.4.1

Single Line on a Ground Plane

A schematic of a single interconnection line placed on bulk silicon (considered as the ground plane) is shown in Fig. 2.4.1a. The capacitance C1 per unit length in terms of the various dimensions shown in Fig. 2.4.1a can be estimated from the approximate formula " C1 ¼ eox

0:222 # W T 1:15 þ 2:80 H H

ð2:4:1Þ

where eox is the dielectric constant of the insulator such as SiO2 for which eox ¼ 3:9 8:855 1014 F=cm. The relative error of formula (2.4.1) is within 6% for 0:3 < W=H < 30 and 0:3 < T=H < 30. 2.4.2

Two Lines on a Ground Plane

A schematic of two interconnection lines placed on bulk silicon (considered as the ground plane) is shown in Fig. 2.4.1b. In this case, the total capacitance C2 of one line per unit length includes the ground capacitance C10 and the coupling

APPROXIMATE FORMULAS FOR CAPACITANCES

59

capacitance C12 between the lines, that is, C2 ¼ C10 þ C12 . In terms of the various dimensions shown in Fig. 2.4.1b, C2 can be estimated from the approximate formula " C2 ¼ C1 þ eox

0:222 # 1:34 W T T S þ 0:83 0:07 0:03 H H H H

ð2:4:2Þ

The relative error of formula (2.4.2) is less than 10% for 0:3 < W=H < 10, 0:3 < T=H < 10, and 0:5 < S=H < 10. It should be noted that formula (2.4.2) tends to the single-line formula (2.4.1) as the line separation S approaches inﬁnity. 2.4.3

Three Lines on a Ground Plane

A schematic of three interconnection lines placed on bulk silicon (considered as the ground plane) is shown in Fig. 2.4.1c. In this case, the total capacitance of one line includes the ground capacitance C20 and the coupling capacitance C21 between the lines. For example, the total capacitance C3 of the middle line per unit length is equal to C20 þ 2C21 . In terms of the various dimensions shown in Fig. 2.4.1c, C3 can be estimated from the approximate formula " C3 ¼ C1 þ 2eox

0:222 # 1:34 W T T S 0:03 þ 0:83 0:07 H H H H

ð2:4:3Þ

The relative error of formula (2.4.3) is less than 10% for 0:3 < W=H < 10, 0:3 < T=H < 10, and 0:5 < S=H < 10. It should be noted that formula (2.4.3) tends to the single-line formula (2.4.1) as the line separation S approaches inﬁnity.

2.4.4

Single Plate with Finite Dimensions on a Ground Plane

A schematic of a single plate with ﬁnite dimensions placed on bulk silicon (considered as the ground plane) is shown in Fig. 2.4.1d. In this case, the capacitance Cp between the plate and the ground includes the 3D effects. In terms of the various dimension parameters shown in Fig. 2.4.1d, Cp can be estimated from the approximate formula " Cp ¼ eox

0:222 0:728 # plate area T T 1:15 ðplate circumferenceÞþ4:12 H þ1:40 H H H ð2:4:4Þ

Compared to the data published by Ruehli et al. [17], the relative error of formula (2.4.4) is within 10% for 0 < W=L < 1, 0:5 < W=H < 40, and 0:4 < T=H < 10. It should be noted that formula (2.4.4) tends to formula (2.4.1) as the plate length approaches inﬁnity.

60

2.5

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

In this section, the parasitic capacitances for a system of closely spaced conducting interconnection lines printed on the GaAs substrate which in turn is placed on a conducting ground plane are determined by using the method of moments [34] in conjunction with a Green’s function appropriate for the geometry of the interconnections. The Green’s function is obtained by using the method of multiple images [3, 35]. It is assumed that the interconnections are of negligible thickness. 2.5.1

Green’s Function Matrix for Interconnections Printed on Substrate

The Green’s function is a solution of a partial differential equation for a unit charge and with speciﬁed boundary conditions. To ﬁnd the Green’s function, the ﬁrst step is to determine the potential due to the source charge everywhere in the region of interest. In this section, the problem will be solved in two dimensions and then it will be extended to the 3D case in the next section. Consider the case of charged interconnections printed on a dielectric substrate which in turn is placed on a conducting ground plane as shown in Fig. 2.5.1. Obviously, there are more than one interface and we need to consider the formation of image charges about the dielectric interface and about the ground plane by a process known as multiple imaging. Each image of the real charge also images across all other interfaces. For example, the real charge r will form an image across the dielectric interface as rðe1 e2 Þ=ðe1 þ e2 Þ. This image will then form another image about the bottom ground plane as ðrÞðe1 e2 Þ=ðe1 þ e2 Þ. This new image will in turn image back across the dielectric interface with its magnitude changed by a factor of ðe2 e1 Þ=ðe1 þ e2 Þ, and so on. Also, the real charge will image about the bottom ground plane as r. This image charge itself will image back across the

FIGURE 2.5.1 Schematic of few interconnections printed on top of substrate, which in turn is placed on conducting ground plane.

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

61

FIGURE 2.5.2 Magnitudes and locations of images formed when line charge r lies in medium of dielectric constant e0 above medium of dielectric constant e with conducting ground plane under it.

dielectric interface modiﬁed by a factor of ðe2 e1 Þ=ðe1 þ e2 Þ. This process will continue to inﬁnity and produce an inﬁnite number of image charges. For the 2D case of a line charge r lying in a medium of dielectric constant e0 above a medium of dielectric constant e with a conducting ground plane under it, the magnitudes and locations of a number of images are shown in Fig. 2.5.2. First, the real charge reﬂects across the dielectric interface. Then both the real charge and this ﬁrst image reﬂect across the ground plane changing in sign. These two new images then reﬂect back across the dielectric interface changing by a factor k where k¼

e e0 e þ e0

and the process continues to inﬁnity. Now, the potential at any ﬁeld point ðxi ; yi Þ due to a line charge r at the location ðxj ; yj Þ can be determined. In general, if r is the distance from the source charge to the ﬁeld point, then Vðxi ; yi Þ ¼

r lnðr 2 Þ 4pe0

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

However, the distance between the source charge and the ﬁeld point will be different for each image, that is, the potential due to the nth image is given by Vn ðxi ; yi Þ ¼

r lnðrn2 Þ 4pe0

and the total potential at the ﬁeld point is given by Vðxi ; yi Þ ¼

1 X

Vn

n¼1

Therefore, it follows from Fig. 2.5.2 that, for yi T and yj T, Vðxi ; yi Þ ¼

r f ln½ðxi xj Þ2 þ ðyi yj Þ2 4pe0 þ k ln½ðxi xj Þ2 þ ðyi yj 2TÞ2 k2 ln½ðxi xj Þ2 þ ðyi yj 4TÞ2 þ þ k ln½ðxi xj Þ2 þ ðyi þ yj 2TÞ2 k2 ln½ðxi xj Þ2 þ ðyi þ yj 4TÞ2 þ k3 ln½ðxi xj Þ2 þ ðyi þ yj 6TÞ2 þ k ln½ðxi xj Þ2 þ ðyi yj þ 2TÞ2 þ k2 ln½ðxi xj Þ2 þ ðyi yj þ 4TÞ2 k3 ln½ðxi xj Þ2 þ ðyi yj þ 6TÞ2 þ þ ln½ðxi xj Þ2 þ ðyi þ yj Þ2 k ln½ðxi xj Þ2 þ ðyi þ yj þ 2TÞ2 þ k2 ln½ðxi xj Þ2 þ ðyi þ yj þ 4TÞ2 þ g

ð2:5:1Þ

The Green’s function Gðxi ; yi ; xj ; yj Þ for the real charge at ðxj ; yj Þ and the ﬁeld point at ðxi ; yi Þ can now be determined from Eq. (2.5.1) by setting r ¼ 1. Therefore

Gðxi ; yi ; xj ; yj Þ ¼

1 1 X ðð1Þn kn1 lnfðxi xj Þ2 þ ½yi yj 2ðn 1ÞT2 g 4pe0 n¼1

þ ð1Þnþ1 kn ln½ðxi xj Þ2 þ ðyi þ yj 2nTÞ2 ð1Þnþ1 kn ln½ðxi xj Þ2 þ ðyi yj þ 2nTÞ2 ð1Þn kn1 lnfðxi xj Þ2 þ ½yi þ yj þ 2ðn 1ÞT2 gÞ ð2:5:2Þ

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

63

If all the interconnections are printed in the same plane on the substrate, then yi ¼ yj ¼ T. Then Eq. (2.5.2) becomes Gðxi ; T; xj ; TÞ ¼

1 1 X ðð1Þn kn1 lnfðxi xj Þ2 þ ½2ðn 1ÞT2 g 4pe0 n¼1

þ ð1Þnþ1 kn lnfðxi xj Þ2 þ ½2ðn 1ÞT2 g ð1Þnþ1 kn ln½ðxi xj Þ2 þ ð2nTÞ2 ð1Þn kn1 ln½ðxi xj Þ2 þ ð2nTÞ2 Þ or Gðxi ; T; xj ; TÞ ¼

1 1 X ð½ð1Þn kn1 þ ð1Þnþ1 kn lnfðxi xj Þ2 þ ½2ðn 1ÞT2 g 4pe0 n¼1

½ð1Þnþ1 kn þ ð1Þn kn1 ln½ðxi xj Þ2 þ ð2nTÞ2 Þ or Gðxi ; T; xj ; TÞ ¼

X 1 1 ð1 kÞ½ð1Þnþ1 kn1 4pe0 n¼1 ðlnfðxi xj Þ2 þ ½2ðn 1ÞT2 g ln½ðxi xj Þ2 þ ð2nTÞ2 Þ

Since 1k ¼1

e e0 2e0 ¼ e þ e0 e þ e0

Therefore Gðxi ; T; xj ; TÞ ¼

1 X 1 ½ð1Þnþ1 kn1 2pðe þ e0 Þ n¼1

ðln½ðxi xj Þ2 þ ð2nTÞ2 lnfðxi xj Þ2 þ ½2ðn 1ÞT2 gÞ We can rewrite this expression for the 2D Green’s function element as Gðxi ; T; xj ; TÞ ¼

1 X

An ½gijn1 gijn2

n¼1

where An ¼

1 ½ð1Þnþ1 kn1 2pðe þ e0 Þ

ð2:5:3Þ

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

gijn1 is the free-space Green’s function for the nth image at a distance yj yi ¼ 2nT from the ﬁeld point, and gijn2 is the free-space Green’s function for the nth image at a distance yj yi ¼ 2ðn 1ÞT from the ﬁeld point. Now, we can extend Eq. (2.5.3) to the case when the charge is limited to a ﬁnite length and a ﬁnite width. First, we need to ﬁnd the expression for the free-space potential due to a charge in three dimensions. Consider a conductor on the surface of a dielectric which is divided into a large number of rectangular subsections. Consider a subsection of length xj , width yj , and area sj located at the source point ðxj ; yj ; zj Þ. For this rectangular subsection in free space (i.e., without the dielectric present) the potential at a ﬁeld point ðxi ; yi ; zi Þ can be determined by integration over the surface of the subsection, that is, for a unit charge density,

1 Vðxi ; yi ; zi Þ ¼ 4pe0

Zx2 Zy2

1 2

x1

y1

½ðxi xj Þ þ ðyi yj Þ2 þ ðzi zj Þ2 1=2

dx dy

where x1 ¼ xj 12 xj

y1 ¼ yj 12yj

x2 ¼ xj þ 12 xj

y2 ¼ yj þ 12yj

After the integration is performed, we get 1 ðc þ A1 Þðd þ B1 Þ ðxj xi Þ ln Vðxi ; yi ; zi Þ ¼ 4pe0 ðd þ C1 Þðc þ D1 Þ xj ðd þ B1 Þðd þ C1 Þ þ ln ðc þ D1 Þðc þ A1 Þ 2 ða þ A1 Þðb þ B1 Þ þ ðyj yi Þ ln ðb þ D1 Þða þ C1 Þ yj ðb þ B1 Þðb þ D1 Þ þ ln 2 ða þ C1 Þða þ A1 Þ ac bd þ atan h atan hA1 hB1 ad bc þ h atan þ atan hC1 hD1

ð2:5:4Þ

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

65

where h ¼ zj z i

a ¼ xj xi 12xj

c ¼ yj yi 12yj pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ A1 ¼ a 2 þ c 2 þ h2 pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ C1 ¼ a2 þ d 2 þ h2

b ¼ xj xi þ 12xj

d ¼ yj yi þ 12yj pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ B 1 ¼ b2 þ d 2 þ h 2 pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ D1 ¼ b2 þ c2 þ h2

Extension of Eq. (2.5.3) to the three dimensions is accomplished by multiplying this equation by 4pe0, by replacing the term gijn1 by the free-space Green’s function for the nth image at a distance h ¼ zj zi ¼ 2nT from the ﬁeld point, and by replacing the term gijn2 by the free-space Green’s function for the nth image at a distance h ¼ zj zi ¼ 2ðn 1ÞT from the ﬁeld point. The new expressions for gijn1 and gijn2 will become 1 ðc þ A2 Þðd þ B2 Þ gijn1 ¼ ðxj xi Þ ln 4pe0 ðd þ C2 Þðc þ D2 Þ xj ðd þ B2 Þðd þ C2 Þ þ ln 2 ðc þ D2 Þðc þ A2 Þ ða þ A2 Þðb þ B2 Þ þ ðyj yi Þ ln ðb þ D2 Þða þ C2 Þ yj ðb þ B2 Þðb þ D2 Þ þ ln 2 ða þ C2 Þða þ A2 Þ ac bd 2 nT atan þ atan 2nTA2 2nTB2 ad bc þ 2 nT atan þ atan ð2:5:5Þ 2nTC2 2nTD2 where

and gijn2 ¼

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ A2 ¼ a2 þ c2 þ ð2nTÞ2 qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ C2 ¼ a2 þ d 2 þ ð2nTÞ2

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ B2 ¼ b2 þ d 2 þ ð2nTÞ2 qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ D2 ¼ b2 þ c2 þ ð2nTÞ2

1 ðc þ A3 Þðd þ B3 Þ xj ðd þ B3 Þðd þ C3 Þ þ ln ðxj xi Þ ln 2 4pe0 ðd þ C3 Þðc þ D3 Þ ðc þ D3 Þðc þ A3 Þ ða þ A3 Þðb þ B3 Þ yj ðb þ B3 Þðb þ D3 Þ þ ðyj yi Þ ln þ ln 2 ðb þ D3 Þða þ C3 Þ ða þ C3 Þða þ A3 Þ ac bd 2ðn 1ÞT atan þ atan 2ðn 1ÞTA3 2ðn 1ÞTB3 ad bc þ 2ðn 1ÞT atan þ atan ð2:5:6Þ 2ðn 1ÞTC3 2ðn 1ÞTD3

66

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

where A3 ¼

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ a2 þ c2 þ ð2ðn 1ÞTÞ2

B3 ¼

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ b2 þ d 2 þ ð2ðn 1ÞTÞ2

C3 ¼

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ a2 þ d2 þ ð2ðn 1ÞTÞ2

D3 ¼

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ b2 þ c2 þ ð2ðn 1ÞTÞ2

Substituting for gijn1 and gijn2 from Eqs. (2.5.5) and (2.5.6) in Eq. (2.5.3) and multiplying by the factor 4pe0 and simplifying, we get for the Green’s function element in three dimensions Gij ¼ Gðxi ; T; xj ; TÞ ¼

1 X 1 ð1Þnþ1 kn1 ðT1 þ T2 þ T3 þ T4 T5 þ T6 þ T7 T8 Þ 2pðe þ e0 Þ n¼1

ð2:5:7Þ where T1 ¼ ðxj xi Þ ln

T2 ¼

ðc þ A3 Þðd þ B3 Þðd þ C2 Þðc þ D2 Þ ðd þ C3 Þðc þ D3 Þðc þ A2 Þðd þ B2 Þ

xj ðd þ B3 Þðd þ C3 Þðc þ D2 Þðc þ A2 Þ ln ðc þ D3 Þðc þ A3 Þðd þ B2 Þðd þ C2 Þ 2

ða þ A3 Þðb þ B3 Þðb þ D2 Þða þ C2 Þ T3 ¼ ðyj yi Þ ln ðb þ D3 Þða þ C3 Þða þ A2 Þðb þ B2 Þ

yj ðb þ B3 Þðb þ D3 Þða þ C2 Þða þ A2 Þ ln T4 ¼ 2 ða þ C3 Þða þ A3 Þðb þ B2 Þðb þ D2 Þ T5 ¼ 2ðn 1ÞT atan T6 ¼ 2ðn 1ÞT atan

ac 2ðn 1ÞTA3

ad 2ðn 1ÞTC3

þ atan

þ atan

ac bd þ atan T7 ¼ 2nT atan 2nTA2 2nTB2 ad bc þ atan T8 ¼ 2nT atan 2nTC2 2nTD2 and T is the substrate thickness.

bd 2ðn 1ÞTB3

bc 2ðn 1ÞTD3

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

2.5.2

67

Green’s Function Matrix for Interconnections Embedded in Substrate

If all the interconnections are embedded in the substrate, then their heights above the bottom ground plane denoted by H will be less than the thickness of the substrate denoted by T. First, as in the previous section, the Green’s function for a line charge r in two dimensions will be found by using the method of images and, next, the expression for the Green’s function will be extended to the 3D case. The results can be checked for accuracy by reducing them to the case when the interconnections are printed on the substrate by setting H ¼ T and ensuring that the resulting expression for the Green’s function agrees with Eq. (2.5.7). First, we ﬁnd the magnitudes and locations of the image charges when a real line charge is placed at a height HðH < TÞ above the bottom ground plane. The real charge will ﬁrst reﬂect up across the dielectric interface and give rise to an image charge equal to kr. This ﬁrst image and the real charge will then both reﬂect across the ground plane changing in signs. These two new images will then reﬂect back across the dielectric interface and so on. The process will continue to inﬁnity giving rise to the images shown in Fig. 2.5.3. To ﬁnd the potential at a point ðxi ; yi Þ inside the dielectric, we need to ﬁnd the sum of all the potentials at this point due to the real charge and all its image charges, that is, 1 X r lnðrn2 Þ Vn ¼ Vðxi ; yi Þ ¼ 4pe 0 n¼1

FIGURE 2.5.3 Magnitudes and locations of images formed when line charge r is embedded in medium of dielectric constant e with conducting ground plane under it and surrounded by another medium of dielectric constant e0 .

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

where e ¼ e0 er . It follows from Fig. 2.5.3 that, for yi T and yj T, r f ln½ðxi xj Þ2 þ ðyi HÞ2 Vðxi ; yi Þ ¼ 4pe þ k ln½ðxi xj Þ2 þ ðyi H 2TÞ2 k2 ln½ðxi xj Þ2 þ ðyi H 4TÞ2 þ k ln½ðxi xj Þ2 þ ðyi þ H 2TÞ2 þ k2 ln½ðxi xj Þ2 þ ðyi þ H 4TÞ2 k3 ln½ðxi xj Þ2 þ ðyi þ H 6TÞ2 þ þ ln½ðxi xj Þ2 þ ðyi þ HÞ2 k ln½ðxi xj Þ2 þ ðyi þ H þ 2TÞ2 þ k2 ln½ðxi xj Þ2 þ ðyi þ H þ 4TÞ2 þ þ k ln½ðxi xj Þ2 þ ðyi H þ 2TÞ2 k2 ln½ðxi xj Þ2 þ ðyi H þ 4TÞ2 þ k3 ln½ðxi xj Þ2 þ ðyi H þ 6TÞ2 þ g

ð2:5:8Þ

The Green’s function Gðxi ; yi ; xj ; yj Þ for the real charge at ðxj ; yj Þ and the ﬁeld point at ðxi ; yi Þ can now be determined from Eq. (2.5.8) by setting r ¼ 1. Therefore Gðxi ; yi ; xj ; yj Þ ¼

1 1 X ðð1Þnþ1 kn1 lnfðxi xj Þ2 þ ½yi H 2ðn 1ÞT2 g 4pe n¼1

þ ð1Þn kn ln½ðxi xj Þ2 þ ðyi þ H 2nTÞ2 ð1Þn kn ln½ðxi xj Þ2 þ ðyi H þ 2nTÞ2 ð1Þnþ1 kn1 lnfðxi xj Þ2 þ ½yi þ H þ 2ðn 1ÞT2 gÞ ð2:5:9Þ If all the interconnections are in the same plane, then yi ¼ yj ¼ H and Eq. (2.5.9) becomes 1 1 X ðð1Þn kn ln½ðxi xj Þ2 þ ð2H 2nTÞ2 Gðxi ; H; xj ; HÞ ¼ 4pe n¼1 ð1Þn kn ln½ðxi xj Þ2 þ ð2nTÞ2 þ ð1Þnþ1 kn1 lnfðxi xj Þ2 þ ½2H þ 2ðn 1ÞT2 g ð1Þnþ1 kn1 lnfðxi xj Þ2 þ ½2ðn 1ÞT 2 gÞ We can rewrite this expression for the 2D Green’s function element as 1 X ½An ðgijn1 gijn2 Þ þ Bn ðgijn3 gijn4 Þ Gðxi ; H; xj ; HÞ ¼ n¼1

ð2:5:10Þ

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

69

where An ¼ ð1Þn kn

Bn ¼ ð1Þnþ1 kn1

gijn1 is the free-space Green’s function for the nth image at a distance yj yi ¼ 2H 2nT from the ﬁeld point, gijn2 is the free-space Green’s function for the nth image at a distance yj yi ¼ 2nT from the ﬁeld point, gijn3 is the freespace Green’s function for the nth image at a distance yj yi ¼ 2H þ 2ðn 1ÞT from the ﬁeld point, and gijn4 is the free-space Green’s function for the nth image at a distance yj yi ¼ 2ðn 1ÞT from the ﬁeld point. Extension of Eq. (2.5.10) to the three dimensions is accomplished by replacing the term gijn1 by the free-space Green’s function for the nth image at a distance h ¼ zj zi ¼ 2H 2nT from the ﬁeld point, replacing the term gijn2 by the freespace Green’s function for the nth image at a distance h ¼ zj zi ¼ 2nT from the ﬁeld point, replacing the term gijn3 by the free-space Green’s function for the nth image at a distance h ¼ zj zi ¼ 2H 2ðn 1ÞT from the ﬁeld point, and replacing the term gijn4 by the free-space Green’s function for the nth image at a distance h ¼ zj zi ¼ 2ðn 1ÞT from the ﬁeld point. The new expressions for gijn1 , gijn2 , gijn3 , and gijn4 become 1 ðc þ A4 Þðd þ B4 Þ xj ðd þ B4 Þðd þ C4 Þ þ ln gijn1 ¼ ðxj xi Þ ln 2 4pe ðd þ C4 Þðc þ D4 Þ ðc þ D4 Þðc þ A4 Þ ða þ A4 Þðb þ B4 Þ yj ðb þ B4 Þðb þ D4 Þ þ ðyj yi Þ ln þ ln 2 ðb þ D4 Þða þ C4 Þ ða þ C4 Þða þ A4 Þ ac bd ð2H 2nTÞ atan þ atan ð2H 2nTÞA4 ð2H 2nTÞB4 ad bc þð2H 2nTÞ atan þ atan ð2H 2nTÞC4 ð2H 2nTÞD4 ð2:5:11Þ where qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ a2 þ c2 þ ð2H 2nTÞ2 B4 ¼ b2 þ d 2 þ ð2H 2nTÞ2 qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 2 2 2 C4 ¼ a þ d þ ð2H 2nTÞ D4 ¼ b2 þ c2 þ ð2H 2nTÞ2 1 ðc þ A5 Þðd þ B5 Þ xj ðd þ B5 Þðd þ C5 Þ þ ln ðxj xi Þ ln ¼ 2 4pe ðd þ C5 Þðc þ D5 Þ ðc þ D5 ÞðC þ A5 Þ ða þ A5 Þðb þ B5 Þ yj ðb þ B5 Þðb þ D5 Þ þ ðyj yi Þ ln þ ln 2 ðb þ D5 Þða þ C5 Þ ða þ C5 Þða þ A5 Þ ac bd 2nT atan þ atan 2nTA5 2nTB5 ad bc þ2nT atan þ atan ð2:5:12Þ 2nTC5 2nTD5 A4 ¼

gijn2

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

where

gijn3

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 2 2 2 B5 ¼ b2 þ d 2 þ ð2nTÞ2 A5 ¼ a þ c þ ð2nTÞ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ D5 ¼ b2 þ c2 þ ð2nTÞ2 C5 ¼ a2 þ d 2 þ ð2nTÞ2 1 ðc þ A6 Þðd þ B6 Þ ðxj xi Þ ln ¼ 4pe ðd þ C6 Þðc þ D6 Þ xj ðd þ B6 Þðd þ C6 Þ ða þ A6 Þðb þ B6 Þ þ ln þ ðyj yi Þ ln 2 ðc þ D6 Þðc þ A6 Þ ðb þ D6 Þða þ C6 Þ yj ðb þ B6 Þðb þ D6 Þ þ ln ð2H þ 2ðn 1ÞTÞ 2 ða þ C6 Þða þ A6 Þ ac bd atan þ atan ½2H þ 2ðn 1ÞTA6 ½2H þ 2ðn 1ÞTB6 ad þ ½2H þ 2ðn 1ÞT atan ½2H þ 2ðn 1ÞTC6 bc ð2:5:13Þ þ atan ½2H þ 2ðn 1ÞTD6

where A6 ¼

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ a2 þ c2 þ ð2H þ 2ðn 1ÞTÞ2

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ C6 ¼ a2 þ d2 þ ð2H þ 2ðn 1ÞTÞ2

B6 ¼

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ b2 þ d 2 þ ð2H þ 2ðn 1ÞTÞ2

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ D6 ¼ b2 þ c2 þ ð2H þ 2ðn 1ÞTÞ2

and gijn4

1 ðc þ A7 Þðd þ B7 Þ ðxj xi Þ ln ¼ 4pe ðd þ C7 Þðc þ D7 Þ xj ðd þ B7 Þðd þ C7 Þ þ ln 2 ðc þ D7 Þðc þ A7 Þ ða þ A7 Þðb þ B7 Þ þ ðyj yi Þ ln ðb þ D7 Þða þ C7 Þ yj ðb þ B7 Þðb þ D7 Þ þ ln 2 ða þ C7 Þða þ A7 Þ ac bd 2ðn 1ÞT atan þ atan 2ðn 1ÞTA7 2ðn 1ÞTB7 ad bc þ 2ðn 1ÞT atan þ atan 2ðn 1ÞTC7 2ðn 1ÞTD7 ð2:5:14Þ

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

71

where A7 ¼

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ a2 þ c2 þ ½2ðn 1ÞT2

B7 ¼

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ b2 þ d2 þ ð2ðn 1ÞTÞ2

C7 ¼

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ a2 þ d 2 þ ð2ðn 1ÞT 2 Þ

D7 ¼

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ b2 þ c2 þ ð2ðn 1ÞTÞ2

Substituting for gijn1, gijn2 , gijn3 , and gijn4 from Eqs. (2.5.11)–(2.5.14) in Eq. (2.5.10) and simplifying, we get for the Green’s function element in three dimensions Gij ¼ Gðxi ; H; xj ; HÞ 1 1 X ¼ ð½1n1 kn ½T9 þ T10 þ T11 þ T12 T13 þ T14 þ T15 T16 4pe n¼1 þ ½1n kn1 ½T17 þ T18 þ T19 þ T20 T21 þ T22 þ T23 T24 Þ ð2:5:15Þ where ðc þ A4 Þðd þ B4 Þðd þ C5 Þðc þ D5 Þ T9 ¼ ðxj xi Þ ln ðd þ C4 Þðc þ D4 Þðc þ A5 Þðd þ B5 Þ xj ðd þ B4 Þðd þ C4 Þðc þ D5 Þðc þ A5 Þ ln T10 ¼ 2 ðc þ D4 Þðc þ A4 Þðd þ B5 Þðd þ C5 Þ ða þ A4 Þðb þ B4 Þðb þ D5 Þða þ C5 Þ T11 ¼ ðyj yi Þ ln ðb þ D4 Þða þ C4 Þða þ A5 Þðb þ B5 Þ yj ðb þ B4 Þðb þ D4 Þða þ C5 Þða þ A5 Þ ln T12 ¼ 2 ða þ C4 Þða þ A4 Þðb þ B5 Þðb þ D5 Þ ac bd þ atan T13 ¼ ð2H 2nTÞ atan ð2H 2nTÞA4 ð2H 2nTÞB4 ad bc þ atan T14 ¼ ð2H 2nTÞ atan ð2H 2nTÞC4 ð2H 2nTÞD4 ac bd þ atan T15 ¼ 2nT atan 2nTA5 2nTB5 ad bc þ atan T16 ¼ 2nT atan 2nTC5 2nTD5 ðc þ A6 Þðd þ B6 Þðd þ C7 Þðc þ D7 Þ T17 ¼ ðxj xi Þ ln ðd þ C6 Þðc þ D6 Þðc þ A7 Þðd þ B7 Þ

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

xj ðd þ B6 Þðd þ C6 Þðc þ D7 Þðc þ A7 Þ ln 2 ðc þ D6 Þðc þ A6 Þðd þ B7 Þðd þ C7 Þ ða þ A6 Þðb þ B6 Þðb þ D7 Þða þ C7 Þ ¼ ðyj yi Þ ln ðb þ D6 Þða þ C6 Þða þ A7 Þðb þ B7 Þ yj ðb þ B6 Þðb þ D6 Þða þ C7 Þða þ A7 Þ ln ¼ 2 ða þ C6 Þða þ A6 Þðb þ B7 Þðb þ D7 Þ ac bd þ atan ¼ ½2H þ2ðn1ÞT atan ½2H þ 2ðn1ÞTA6 ½2H þ 2ðn 1ÞTB6 ad bc þ atan ¼ ½2H þ2ðn 1ÞT atan ½2H þ 2ðn1ÞTC6 ½2H þ 2ðn 1ÞTD6 ac bd ¼ 2ðn 1ÞT atan þ atan 2ðn 1ÞTA7 2ðn 1ÞTB7 ad bc þ atan ¼ 2ðn 1ÞT atan 2ðn 1ÞTC7 2ðn 1ÞTD7

T18 ¼ T19 T20 T21 T22 T23 T24

2.5.3

Application of Method of Moments

The algorithm presented below is suitable for a system of four interconnection lines and can be easily modiﬁed for a different number of lines. For a system of four conducting lines, the known potential Vi on the ith ði ¼ 1; 2; 3; 4Þ conductor is related to the unknown surface charge density sj on each conductor by the following system of integral equations: Vi ¼

4 Z X j¼1

Gðxi ; yi ; xj ; yj ; zÞsj ðxj ; yj Þdxj dyj

Sj

where G is the Green’s function and Sj is the area of the jth conductor. If the conductors are divided into a total of N subsections with areas dsj , then the potential Vi of the ith subsection is given by Vi ¼

4 X

sj Gij

j¼1

where sj is now the unknown surface charge density of the jth subsection and Gij is the element of the Green’s function pertinent to the problem. If the subsections are made small enough so that the charge density can be assumed constant over the area of each subsection, then the method of moments can be used to convert this equation into its matrix form ½V ¼ ½sj ½G

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

73

Then, by matrix inversion, the unknown sj can be determined from ½sj ¼ ½G1 ½V where ½sj and ½V are two N-dimensional column matrices and ½G is the N-dimensional square matrix. The total charge on the jth conductor is given by

Qj ¼

Nj X

sj dsj

j ¼ 1; 2; 3; 4

j¼1

where Nj is the number of subsections on the jth conductor. 2.5.4

Even- and Odd-Mode Capacitances

For the system of four interconnection lines, an even- and odd-mode excitation can be used to calculate the even- and odd-mode capacitances of each line separately. For the even-mode excitation, each line is assumed to be þ1 V potential with respect to the conducting ground plane. For the odd-mode excitation, one line is kept at þ1 V while the other three lines are kept at 1 V potential. This means that when ﬁnding the odd-mode charge on the ﬁrst line, the potential on the ﬁrst line is kept at þ1 V while the potentials on each of the second, third, and fourth lines are kept at 1 V, and so on. First, the four lines are divided into N1 , N2 , N3 , and N4 number of subsections. Thus, the total number of subsections becomes N ¼ N1 þ N2 þ N3 þ N4 Then, the voltage excitation for the even mode of each interconnection line is an N-row unit column matrix, that is,

½Veven

2 3 1 6 .. 7 6.7 6 7 617 6 7 617 6.7 .7 ¼6 6.7 617 6 7 617 6 7 6 .. 7 4.5 1

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

while the odd-mode excitation for the ﬁrst line is represented by the matrix 2

½Vodd;1

6 6 6 6 6 6 6 6 6 6 ¼6 6 6 6 6 6 6 6 6 6 4

3 1 .. 7 . 7 17 7 1 7 7 .. 7 .7 7 1 7 7 1 7 .. 7 7 .7 7 1 7 7 1 7 .. 7 .5 1

and similarly for ½Vodd;2, ½Vodd;3 , and ½Vodd;4 . If the inverse of the Green’s function matrix is denoted by ½R, then we can deﬁne the following 16 quantities by summing the ijth elements in the 16 submatrices of the matrix ½R:

R1 ¼

N1 X N1 X

Rij

i¼1 j¼1

R2 ¼

N1 NX 1 þN2 X

Rij

i¼1 j¼N1 þ1

R3 ¼

N1 X

N1 þN 2 þN3 X

Rij

i¼1 j¼N1 þN2 þ1

R4 ¼

N1 X

N X

Rij

i¼1 j¼N1 þN2 þN3 þ1

R5 ¼

NX 1 þN2

N X

Rij

i¼N1 þ1 j¼1

R6 ¼

NX 1 þN2 NX 1 þN2 i¼N1 þ1 j¼N1 þ1

Rij

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

R7 ¼

NX 2 þN3 1 þN2 N1 þN X

75

Rij

i¼N1 þ1 j¼N1 þN2 þ1

R8 ¼

NX 1 þN2

N X

Rij

i¼N1 þ1 j¼N1 þN2 þN3 þ1

R9 ¼

N1 þN 2 þN3 X

N1 X

Rij

i¼N1 þN2 þ1 j¼1

R10 ¼

N1 þN 2 þN3 NX 1 þN2 X

Rij

i¼N1 þN2 þ1 j¼N1 þ1

R11 ¼

N1 þN 2 þN3 N1 þN 2 þN3 X X

Rij

i¼N1 þN2 þ1 j¼N1 þN2 þ1

R12 ¼

N X

N1 þN 2 þN3 X

Rij

i¼N1 þN2 þ1 j¼N1 þN2 þN3 þ1 N X

R13 ¼

N1 X

Rij

i¼NN4 þ1 j¼1 N X

R14 ¼

NX 1 þN2

Rij

i¼NN4 þ1 j¼N1 þ1 N X

R15 ¼

N1 þN 2 þN3 X

Rij

i¼NN4 þ1 j¼N1 þN2 þ1 N X

R16 ¼

N X

Rij

i¼NN4 þ1 j¼NN4 þ1

The even- and odd-mode capacitances for each of the four lines can be determined from the relations ðe;oÞ

ðe;oÞ

Cj

¼

Qj

ðe;oÞ

j ¼ 1; 2; 3; 4

Vj

Since ½s ¼ ½G1 ½V

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

the even- and odd-mode capacitances for the four lines can be expressed as C1e ¼ ðR1 þ R2 þ R3 þ R4 Þs1 C2e ¼ ðR5 þ R6 þ R7 þ R8 Þs2 C3e ¼ ðR9 þ R10 þ R11 þ R12 Þs3 C4e ¼ ðR13 þ R14 þ R15 þ R16 Þs4 C1o ¼ ðR1 R2 R3 R4 Þs1 C2o ¼ ðR6 R5 R7 R8 Þs2 C3o ¼ ðR11 R9 R10 R12 Þs3 C4o ¼ ðR16 R13 R14 R15 Þs4

2.5.5

Ground and Coupling Capacitances

The ground and coupling interconnection capacitances can be obtained by solving the following set of equations: C1e ¼ C11 C2e ¼ C22 C3e ¼ C33 C4e ¼ C44 C1o ¼ C11 þ 2C12 þ 2C13 þ 2C14 C2o C3o C4o

ð2:5:16Þ

¼ C22 þ 2C12 þ 2C23 þ 2C24 ¼ C33 þ 2C13 þ 2C23 þ 2C34 ¼ C44 þ 2C14 þ 2C24 þ 2C34

Since the number of unknowns is greater than the number of equations, Eqs. (2.5.16) cannot be solved exactly. One way is to use the method of unconstrained multivariable optimization to solve the equations. 2.5.6

The Program IPCSGV

The source code of a program called IPCSGV developed to determine the interconnection parasitic capacitances on the GaAs-based VLSI is presented in Appendix 2.1, which can be found at the ftp site: ftp://ftp.wiley.com/public/ sci_tech_med/high_speed_VLSI. It is based on the various calculation steps presented above and is written in FORTRAN. The program can be modiﬁed to include more interconnections though the relative precision of the results will be

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77

affected. One can utilize the method of unconstrained multivariable optimization to solve Eqs. (2.5.16) for an interconnection conﬁguration consisting of four interconnections, three on the top plane and one embedded in the substrate, as shown in Fig. 2.5.4.

2.5.7

Parametric Dependence of Interconnection Capacitances

The program IPCSGV can be used to study the dependences of the ground and coupling interconnection capacitances on the various interconnection parameters shown in Fig. 2.5.4. In the following results, one of the parameters is varied in a speciﬁc range while the others are kept ﬁxed at their selected typical values. These typical values are chosen to be the following: interconnection lengths 100 mm each, widths 1 mm each, separations 2 mm, interlevel distances 2 mm, and thickness of GaAs substrate 200 mm. The dependences of the ground and coupling capacitances on the lengths of the bilevel interconnections are shown in Figs. 2.5.5 and 2.5.6, respectively. Figure 2.5.5 shows that C22 is always less than C11 and C33 . This is due to larger shielding of the electric ﬁeld lines that constitute the capacitance C22 by those that constitute the capacitances C12 and C23 . This ﬁgure also shows that for the interconnection lengths above about 10 mm the ground capacitances vary almost linearly with length. Departure from linearity for smaller lengths is due to a more dominant role played by the fringing ﬁelds for smaller interconnection dimensions. The dependences of the ground and coupling capacitances on the widths of the interconnection lines are shown in Figs. 2.5.7 and 2.5.8, respectively. As functions of the interconnection separation, the ground and coupling capacitances are shown in Figs. 2.5.9 and 2.5.10, respectively. The dependences of the ground and coupling capacitances on the interlevel separation of the interconnection lines are shown in Figs. 2.5.11 and 2.5.12, respectively. As functions of the thickness of the GaAs substrate, the ground and coupling capacitances are shown in Figs. 2.5.13 and 2.5.14, respectively. Figures 2.5.15 and 2.5.16 show the effects of changing the relative angle of the

FIGURE 2.5.4 IPCSGV.

Schematic of four interconnections in bilevel conﬁguration used in program

78

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.5.5 Dependence of ground capacitances for four bilevel interconnections on interconnection lengths.

FIGURE 2.5.6 Dependence of coupling capacitances for four bilevel interconnections on interconnection lengths.

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

79

FIGURE 2.5.7 Dependence of ground capacitances for four bilevel interconnections on interconnection widths.

FIGURE 2.5.8 Dependence of coupling capacitances for four bilevel interconnections on interconnection widths.

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.5.9 Dependence of ground capacitances for four bilevel interconnections on interconnection separations.

FIGURE 2.5.10 Dependence of coupling capacitances for four bilevel interconnections on interconnection separations.

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

81

FIGURE 2.5.11 Dependence of ground capacitances for four bilevel interconnections on interlevel separation.

FIGURE 2.5.12 Dependence of coupling capacitances for four bilevel interconnections on interlevel separation.

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.5.13 Dependence of ground capacitances for four bilevel interconnections on substrate thickness.

FIGURE 2.5.14 Dependence of coupling capacitances for four bilevel interconnections on substrate thickness.

GREEN’S FUNCTION METHOD: USING METHOD OF IMAGES

83

FIGURE 2.5.15 Dependence of ground capacitances for four bilevel interconnections on relative angle of fourth interconnection.

FIGURE 2.5.16 Dependence of coupling capacitances for four bilevel interconnections on relative angle of fourth interconnection.

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

fourth line in the bilevel conﬁguration on the various ground and coupling capacitances. Figure 2.5.16 shows that C14 , C24 , and C34 decrease sharply while C12 , C23 , and C13 increase when the angle is increased.

2.6

GREEN’S FUNCTION METHOD: FOURIER INTEGRAL APPROACH

The parasitic capacitances for a system of multilevel conducting interconnections can also be determined by the Green’s function method obtained by the Fourier integral approach and by using a piecewise linear approximation for the charge density distributions [24] on the conducting interconnections. This method reduces the order of integration and the number of equations needed, thereby reducing the computation time and the memory required. In this section, the Green’s function for the Si–SiO2 system is derived by using the Fourier integral approach and the integral equations are solved for a multilevel interconnection structure using a piecewise linear approximation for the charge density distributions [24]. 2.6.1

Green’s Function for Multilevel Interconnections

A representation of three multilevel conducting interconnections in the Si–SiO2 composite is shown in Fig. 2.6.1. The solution of the Laplace equation governing the potentials on the conductors can be written as ðpÞ ¼

Z Gðp; qÞsðqÞdq

ð2:6:1Þ

all charge

where sðqÞ is the charge density at point qðx0 ; y0 ; z0 Þ in Fig. 2.6.1 and Gðp; qÞ is the appropriate Green’s function describing the potential induced at point pðx; y; zÞ by a unit point charge at point qðx0 ; y0 ; z0 Þ. For a system of N conductors, the potential on the jth conductor is given by

j ðpÞ ¼

N Z X i¼1

Gðp; qÞsi ðqÞdsi ðqÞ

j ¼ 1; 2; . . . ; N

ð2:6:2Þ

Si

where si ðqÞ denotes the charge density on the surface Si of the ith conductor. The Green’s function Gðp; qÞ can be expressed as a Fourier integral [36] as Gðp; qÞ ¼

1 4pe1

Z

1 0

J0 ðmrÞemjz1 j dm

ð2:6:3Þ

GREEN’S FUNCTION METHOD: FOURIER INTEGRAL APPROACH

85

FIGURE 2.6.1 Representation of three multilevel interconnections in Si–SiO2 composite. (From [24]. # 1987 by IEEE.)

where e1 is the dielectric constant of SiO2, J0 is the Bessel function of ﬁrst kind and zero order, m is the variable of integration, z1 ¼ z z0 , and r¼

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ðx x0 Þ2 þ ðy y0 Þ2

The Green’s function in region 1 ð0 < z dÞ shown in Fig. 2.6.1 can now be written as Z 1 1 J0 ðmrÞ½emjz1 j þ 1 ðmÞemz1 þ 2 ðmÞemz1 dm ð2:6:4Þ G1 ðp; qÞ ¼ 4pe1 0 and that in region 2 ðd z < 1Þ is given by Z 1 1 J0 ðmrÞ½1 ðmÞemz1 þ 2 ðmÞemz1 dm G2 ðp; qÞ ¼ 4pe1 0

ð2:6:5Þ

where the unknown functions 1 , 2 , 1 , and 2 are determined by using the boundary conditions G1 ðp; qÞ ¼ G2 ðp; qÞ at z ¼ d @G1 @G2 e1 ¼ e2 at z ¼ d ð2:6:6Þ @z1 @z1 G1 ðp; qÞ ¼ 0 at z ¼ 0 at z ¼ 1 G2 ðp; qÞ ¼ 0

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

to be given by

2

3 2 3 0 1 bKðae2mz 1Þ 6 2 7 6 ðbK 1Þe2mz0 bKa 7 6 7 6 7 0 4 1 5 ¼ 4 5 bgða e2mz Þ 2 0

ð2:6:7Þ

with e1 e2 e1 þ e2 1 b¼ K þ e2md

K¼

0

0

a ¼ em½ðjdz jÞðdz Þ g ¼ ð1 þ KÞe2md

Substituting Eq. (2.6.7) into Eqs. (2.6.4) and (2.6.5) and solving the resulting integrals, we can ﬁnd that the Green’s function for the case when points p and q are both in region 1 is given by 2 1 X 1 6 1 1 ﬃ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ þ ð1Þn K nþ1 G11 ðp; qÞ ¼ 4pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 4pe1 2 z21 þ r2 0 2 n¼0 ð2z þ z1 Þ þ r 0 1 1 B @qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 2 ½2ðn þ 1Þd ð2z0 þ z1 Þ þ r2 ½2ðn þ 1Þd þ z1 2 þ r2 13 1 1 C7 þ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃA5 2 2 0 2 2 ½2ðnþ1Þdþð2z þz1 Þ þr ½2ðnþ1Þdz1 þ r

ð2:6:8Þ

the Green’s functions for the cases when points p and q are located in different regions are given by 2 1 6 1 1 ﬃ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ G12 ðp; qÞ ¼ 4pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 4pe1 z21 þ r2 ð2z0 þ z1 Þ2 þ r2 0 1 X 1 1 B ð1Þn K nþ1 @qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ þ n¼0 ð2nd z1 Þ2 þ r2 ð2nd þ 2z0 þ z1 Þ2 þ r2 13 1 1 C7 þ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃA5 2 2 ½2ðn þ 1Þd þ 2z0 þ z1 þ r2 ½2ðn þ 1Þd z1 þ r2 ð2:6:9Þ

GREEN’S FUNCTION METHOD: FOURIER INTEGRAL APPROACH

G21 ðp; qÞ ¼

87

1þK 4pe1 0 31 2 1 1 1 BX 7C 6 @ ð1Þn K n 4qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ5A 2 2 2 0 2 n¼0 ð2nd þ z1 Þ þ r ð2nd þ 2z þ z1 Þ þ r ð2:6:10Þ

and the Green’s function for the case when points p and q are both in region 2 is given by 0 X 1 1þK B B G22 ðp; qÞ ¼ ð1Þn K n 4pe1 @ n¼0 31

2

1 1 7C 6 4qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ5A 2 2 ½2ðn 1Þd þ 2z0 þ z1 þ r2 ð2nd þ 2z0 þ z1 Þ þ r2 ð2:6:11Þ

2.6.2

Multiconductor Interconnection Capacitances

For the three-conductor problem shown in Fig. 2.6.2a, the total charges Qi ði ¼ 1; 2; 3Þ on the three conductors are given in terms of the ground and coupling capacitances shown in Fig. 2.6.2b and the potentials j ðj ¼ 1; 2; 3Þ of the three conductors by the equations

Q1 ¼ C11 1 þ C12 ð1 2 Þ þ C13 ð1 3 Þ Q2 ¼ C21 ð2 1 Þ þ C22 2 þ C23 ð2 3 Þ

ð2:6:12Þ

Q3 ¼ C31 ð3 1 Þ þ C32 ð3 2 Þ þ C33 3 For a system of N conductors, Eqs. (2.6.12) can be written as

Qi ¼ Cii i þ

N X j¼0

Cij ði j Þ

i ¼ 1; 2; . . . ; N

ð2:6:13Þ

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.6.2 (a) Three ﬁnite interconnection metallization lines. (b) Equivalent circuit showing ground and coupling capacitances. (From [24]. # 1987 by IEEE.)

which can be rewritten in terms of the short-circuit capacitances Csij as

Qi ¼

N X

Csij j

i ¼ 1; 2; . . . ; N

ð2:6:14Þ

j¼1

Comparing Eqs. (2.6.13) and (2.6.14), the ground and coupling interconnection capacitances can be obtained from the short-circuit capacitances by using the relations

Cii ¼

N X

Csij

i ¼ 1; 2; . . . ; N

ð2:6:15Þ

j¼1

Cij ¼ Csij

i 6¼ j

ð2:6:16Þ

GREEN’S FUNCTION METHOD: FOURIER INTEGRAL APPROACH

89

FIGURE 2.6.3 (a) Division of conductor into discrete elements. (b) Shape of piecewise linear charge function on each element. (From [24]. # 1987 by IEEE.)

which in turn require determination of the charge on each conductor for known values of the potentials j .

2.6.3

Piecewise Linear Charge Distribution Function

For a system of N conductors, each conductor is divided into a number of discrete elements as shown in Fig. 2.6.3a and, on each of these elements, the charge density is approximately expressed by a linear combination of four piecewise linear functions. Thus, the charge density si ðqÞ on the ith element is given by si ðqÞ ¼

4 X

ail fil ðqÞ

ð2:6:17Þ

l¼1

where fil ðqÞ is the lth of the four charge shape functions used to describe the charge distribution on the ith element and ail are the unknown coefﬁcients which need to be determined. If the ith conductor is divided into Ni elements, then the total charge on this conductor is given by

Qi ¼

Ni Z X j¼1

mth element

sm ðqÞdsm ðqÞ

ð2:6:18Þ

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

where m¼jþ

i X

Nk1

k¼2

For a single conductor having a rectangular cross section, the charge shape function is shown in Fig. 2.6.3b and is given by

fqi2

8 > < Aðs ai Þ ¼ Bðs bi Þ > : 0

for qi2 s < qi3 for qi1 < s qi2 for qi4 s qi1

or qi3 s qi4

ð2:6:19Þ

where 2 wi ðwi þ ti Þ 2 B¼ ti ðwi þ ti Þ

A¼

ai ¼ six0 þ wi

2.6.4

bi ¼ siz0 þ ti

Calculation of Interconnection Capacitances

In order to determine the interconnection capacitances, we need to ﬁnd the 4N unknown coefﬁcients ða11 ; . . . ; a14 ; a21 ; . . . ; aN4 Þ. Substituting for charge density from Eq. (2.6.17) in Eq. (2.6.2), we get

j ðpÞ ¼

N X 4 X

ail Fil ðpÞ

j ¼ 1; 2; . . . ; N

ð2:6:20Þ

i¼1 l¼1

where Fil ðpÞ ¼

Z

Gðp; qÞfil ðqÞ dsi ðqÞ

ð2:6:21Þ

ith element

Following the Ritz–Rayleigh method [37], both sides of Eq. (2.6.20) are projected onto the space spanned by the original charge shape functions. Using the following

NETWORK ANALOG METHOD

91

equations for the jth element: ðj ðpÞ; fil ðpÞÞ ¼

0 j

when i 6¼ j when i ¼ j

we get from Eq. (2.6.20) N X 4 X

ail Pijl ¼ ðj ðpÞ; fjl ðpÞÞ

j ¼ 1; 2; . . . ; N

ð2:6:22Þ

Gðp; qÞfjl ðpÞfil ðqÞdsj ðpÞdsi ðqÞ

ð2:6:23Þ

i¼1 l¼1

where

Pijl ¼

Z ith element

Z jth element

Equation (2.6.22) can be written in matrix form as ½P½A ¼ ½F½

ð2:6:24Þ

where A ¼ ða11 ; . . . ; a14 ; a21 ; . . . ; aN4 ÞT is the vector of 4N unknown coefﬁcients, P is the 4N 4N matrix of the evaluated double integrals, ¼ ð1 ; 2 ; . . . ; N ÞT is the vector of N known potentials of the N conductors, and F is a 4N N incidence matrix of elements and conductors. Using any standard technique, Eq. (2.6.24) can be solved for the unknown coefﬁcients. Then the charge densities can be obtained using Eq. (2.6.17) and the charges on each conductor can be found from Eq. (2.6.18). Finally, the short-circuit capacitances required for the determination of the interconnection capacitances can be obtained using Eqs. (2.6.14) and (2.6.18) or can be found directly using Cs ¼ ½FT ½P1 ½F

2.7

ð2:6:25Þ

NETWORK ANALOG METHOD

In this section, the parasitic capacitances and inductances associated with the single-, bi-, and trilevel interconnections on GaAs-based ICs are determined by a network analog method [25]. The developed algorithm is suitable for open

92

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

substrates and ﬁnite interconnection dimensions in single or multilevels. Furthermore, the algorithm allows greater ﬂexibility in the choice of the spatial domains, thereby reducing the number of nodes and hence the computer processing time. In principle, the method allows for any number of lines in the interconnection conﬁgurations. However, the amount of computation time as well as the memory size required for solving the problem will increase with an increase in the number of interconnection lines. The method involves division of the interconnection lines and the underlying substrate into subregions, representation of each subregion by an appropriate network analog, diagonalization of the network analog system and calculation of the parasitic capacitances for the diagonalized system using a recursive scheme, and ﬁnally determination of the parasitic capacitances for the system of interconnection lines.

2.7.1

Representation of Subregions by Network Analogs

For the semi-insulating and nonmagnetic GaAs substrate, Maxwell’s equations in the quasi-static case (i.e., ð@=@tÞB ¼ 0) reduce to =E¼0

ð2:7:1Þ

and

= H ¼ sE þ e

@ E @t

ð2:7:2Þ

Deﬁning a potential V such that E ¼ rV and using the identity ==H¼0 we obtain from Eq. (2.7.2) @ r sþe V¼0 @t 2

ð2:7:3Þ

NETWORK ANALOG METHOD

93

In 3D rectangular coordinates, the ﬁnite-difference form of Eq. (2.7.3) can be written as @ Vðx þ xÞ Vðx xÞ s þ ex @t ðxÞ2 @ Vðyþ yÞVðy yÞ @ Vðz þ zÞ Vðz zÞ þ sþ ey þ sþe ¼0 z @t @t ðyÞ2 ðzÞ2 ð2:7:4Þ where ex , ey , and ez and are the permittivities along the x, y, and z directions, respectively. Multiplying each term of Eq. (2.7.4) by 2ð xÞðyÞðzÞ, it becomes @ Vðx þ xÞ Vðx xÞ 2ðyÞðzÞ s þ ex @t x

@ Vðy þ yÞ Vðy yÞ þ 2ðxÞðzÞ s þ ey @t y @ Vðz þ zÞ Vðz zÞ ¼0 þ 2ðxÞðyÞ s þ ez @t z

ð2:7:5Þ

Equation (2.7.5) implies that the entire region consisting of the lower substrate (GaAs) placed on a conducting ground plane, metallic lines, and the upper open substrate can be divided into subregions each of dimensions x, y, and z consisting of circuit elements whose values depend on the conductivity s and the permittivity e.

2.7.2

Diagonalized System for Single-Level Interconnections

A schematic of the three single-level interconnections printed on the GaAs substrate is shown in Fig. 2.7.1a. In this case, the total admittance matrix G for the nodes in the plane of the interconnection lines is given by G ¼ Gu þ Gl

ð2:7:6Þ

where Gu and Gl are the admittance matrices for the upper and lower substrates, respectively. The matrix G can be determined by ﬁrst determining the impedance

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.7.1 Schematic of (a) three single-level, (b) six bilevel, and (c) six trilevel interconnections printed on or embedded in GaAs substrate.

matrix Zk for the kth layer ðk ¼ 1; 2; . . . ; L1 Þ using a recurrence formula Zk ¼ zk1 þ ½Gk1 þ ½Zk1 1 1

ð2:7:7Þ

where Gk , the admittance matrix for the network analog of the kth layer, is given by 2 Gk ¼

ð1Þ

4 Gk

ð2Þ Gk

h

i ð2Þ T

Gk

ð1Þ Gk

3 5

NETWORK ANALOG METHOD

95

where 2

ð1Þ

Gk

2ða þ bÞ 6 a 6 6 6 0 ¼6 6 .. 6 . 4 0 2

ð2Þ

Gk

6 6 6 ¼6 6 6 4

a 2ða þ bÞ a .. . 0

0 0

2ða þ bÞ .. .. . .

0 .. .

0 a

0

b

0

0

0 0 .. . 0

b 0 .. . 0

0 b .. . 0

.. .

a

3 7 7 7 7 7 7 7 5

2ða þ bÞ

3

ð2:7:8Þ

0 7 7 7 0 7 7 .. 7 . 5 b

and the values of a and b are determined by the dimensions, conductivity and permittivity of the subsections on the kth layer as given by ðyÞðzk Þ ðyÞðzkþ1 Þ þ x x ðxÞðzk Þ ðxÞðzkþ1 Þ 1 þ b ¼ 2ðjoer e0 þ sÞ y y a ¼ 12ðjoer e0 þ sÞ

ð2:7:9Þ

In Eq. (2.7.7) zk is the impedance of each element on the kth layer and is given by zk ¼

zk ðjoer e0 þ sÞðxÞðyÞ

ð2:7:10Þ

Gl ¼ ½ZLl 1 þGLl

ð2:7:11Þ

Then, for the lower substrate

Similarly, for the upper substrate Gu ¼ ½ZLu 1 þGLu In the past, the network analog method has been restricted to the case when x ¼ y. However, greater ﬂexibility can be introduced if x is not necessarily equal to y. Furthermore, computer processing time can be lowered if z is increased as the distance of the layer from the interconnections increases. With these modiﬁcations, the admittance matrix Gk has a special band form as shown in Eq. (2.7.8) and can be diagonalized. If Nði; jÞ denotes the node number corresponding to

96

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

the ith row ði ¼ 1; 2; . . . ; Nx Þ and the jth column ðj ¼ 1; 2; . . . ; Ny Þ, then the eigenvalue corresponding to this node is given by

ip l½Nði; jÞ ¼ 2a 1 cos Nx þ 1

jp þ 2b 1 cos Ny þ 1

ð2:7:12Þ

and an element of the corresponding orthonormal eigenvector matrix E is given by 2 imp jnp E½Nðm; nÞ; Nði; jÞ ¼ pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃpﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ sin sin Nx þ 1 Ny þ 1 Nx þ 1 Ny þ 1

ð2:7:13Þ

where Nx and Ny are the number of subdivisions along the x and the y directions, respectively. It can be proved that the eigenvector E in Eq. (2.7.13) is orthonormal, that is, ET ¼ E1 . The diagonalized admittance matrix can now be written as

GD k ¼ Diag l1 ; l2; . . . ; lNx Ny and is related to the matrix Gk by T Gk ¼ EGD kE

Similarly, the diagonalized impedance matrix ZkD is related to the matrix Zk by Zk ¼ EZkD ET and the recurrence formula for the diagonalized system becomes h D 1 i1 þ Zk1 ZkD ¼ zk1 I þ GD k1

k ¼ 1; 2; . . . ; Lu;l

ð2:7:14Þ

and then, for the upper and lower substrates, h i1 D GD u;l ¼ Zu;l

ð2:7:15Þ

The representation of the node Nði; jÞ due to the lower substrate in the diagonalized system is shown in Fig. 2.7.2a. The corresponding representation due to the upper substrate can be obtained on the same lines. First, the matrices GD u and GD l are obtained and then the total impedance matrix Z is obtained by

D 1 T Z ¼ E GD E u þ Gl

ð2:7:16Þ

NETWORK ANALOG METHOD

97

FIGURE 2.7.2 (a) Representation of node on single-level interconnections in diagonalized system. (b) Representation of node between any two levels of multilevel interconnections in diagonalized system.

2.7.3

Diagonalized System for Multilevel Interconnections

Schematics of the interconnections in the bi- and trilevel conﬁgurations are shown in Figs. 2.7.1b and c, respectively. In this case, the network analogs for the upper open substrate and for the substrate between the lowest interconnection level and the bottom ground plane can be reduced by the technique used for the single-level interconnections. However, the substrate between the successive levels needs to be considered. The diagonalized system for a node in the x–y plane on a layer between any two levels can be shown as in Fig. 2.7.2b. The values of the elements z1 ; z2 ; . . . ; zL and l1 ; l2 ; . . . ; lL are determined by the dielectric permittivity, conductance, and dimensions of the subsections at the node. In order to save the computation time, the substrate between the two successive interconnection levels can be divided into two symmetric halves and then the reduced network for the upper half can be combined with the equivalent network for the lower half.

2.7.4

Interconnection Capacitances and Inductances

It can be shown that only the nodes located on the interconnection lines determine the interconnection characteristics. For multilevel interconnections, the total impedance matrix contains submatrices which connect nodes on the interconnection

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lines on all levels. For example, for three interconnection lines in any conﬁguration, the impedance matrix is given by 2

½Zi11 ½Z ¼ 4 ½Zi21 ½Zi31

3 ½Zi13 ½Zi23 5 ½Zi33

½Zi12 ½Zi22 ½Zi32

where the matrix ½Zi12 represents coupling between the nodes on the ﬁrst and second interconnections and so on. The ground and coupling capacitances associated with the multilevel interconnections can then be determined as follows: Let 2

½Y ¼ ½Z1

½Yi11 ¼ 4 ½Yi21 ½Yi31

½Yi12 ½Yi22 ½Yi32

3 ½Yi13 ½Yi23 5 ½Yi33

s Further, let Yixy denote the sum of the elements of the submatrix ½Yixy , that is,

s ¼ Yixy

M X N X

Yixy ðm; nÞ

m¼1 n¼1

Then the ground interconnection capacitances are given by X s s Cxx ¼ Yixx þ Yixy x6¼y

and the coupling interconnection capacitances are given by s Cxy ¼ Yixy

x 6¼ y

ð2:7:17Þ

The inductance matrix can be computed from the capacitance matrix for the corresponding two-dimensional interconnection conﬁguration (consisting of inﬁnite-length interconnections) in free space by the matrix inversion. The telegraphist’s equations for the lossless case in free space are @V @I ¼ L @x @t and @I @V ¼ C0 @x @t or @2V @2V ¼ LC 0 @x2 @t2

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99

In free space, the wave should travel with the speed of light, that is, @2V 1 @2V ¼ @x2 v2 @t2 Therefore LC0 ¼

1 ¼ m0 e0 v2

In matrix form ½L ¼ m0 e0 ½C0 1

ð2:7:18Þ

In Eq. (2.7.18), m0 and e0 are the permeability and permittivity for free space and ½C0 is the capacitance matrix for the 2D interconnection conﬁguration in free space. 2.7.5

The Program ICIMPGV

The listing of a computer program called ICIMPGV used to compute the parasitic capacitances and inductances for the multilevel parallel interconnections on the GaAs-based high-density ICs and based on the numerical technique presented above is included in Appendix 2.2 on the accompanying ftp site. In the next two sections, the program ICIMPGV has been used to study the dependences of the interconnection capacitances and inductances on the various interconnection parameters. 2.7.6

Parametric Dependence of Interconnection Capacitances

For the single-level interconnections, the capacitance results are compared to those obtained by using the Green’s function method and an excellent agreement can be seen. For example, as a function of the interconnection length, the dependences of the ground and coupling capacitances as determined by using the two methods are shown in Figs. 2.7.3 and 2.7.4, respectively, and the same comparisons as functions of the interconnection width are shown in Figs. 2.7.5 and 2.7.6, respectively. For a system of more than four interconnections, the results obtained by the Green’s function method can be only approximate at best. Therefore, the results for the bilevel and trilevel conﬁgurations as shown below are obtained by the network analog method only. For the bilevel interconnections shown in Fig. 2.7.1b, the dependences of the various ground and coupling capacitances on the lengths of the interconnection lines in the range 20–2000 mm keeping the other parameters at their ﬁxed typical values are shown in Figs. 2.7.7 and 2.7.8, respectively. As functions of the interlevel distance in the range 1–20 mm, the ground and coupling capacitances for the same bilevel conﬁguration are shown in Figs. 2.7.9 and 2.7.10, respectively.

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FIGURE 2.7.3 Dependences of ground capacitances for interconnections shown in Fig. 2.7.1a on interconnection lengths as determined by Green’s function and network analog methods.

FIGURE 2.7.4 Dependences of coupling capacitances for interconnections shown in Fig. 2.7.1a on interconnection lengths as determined by Green’s function and network analog methods.

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101

FIGURE 2.7.5 Dependences of ground capacitances for interconnections shown in Fig. 2.7.1a on interconnection widths as determined by Green’s function and network analog methods.

FIGURE 2.7.6 Dependences of coupling capacitances for interconnections shown in Fig. 2.7.1a on interconnection widths as determined by Green’s function and network analog methods.

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FIGURE 2.7.7 Dependences of ground capacitances for interconnections shown in Fig. 2.7.1b on interconnection lengths.

FIGURE 2.7.8 Dependences of coupling capacitances for interconnections shown in Fig. 2.7.1b on interconnection lengths.

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103

FIGURE 2.7.9 Dependences of ground capacitances for interconnections shown in Fig. 2.7.1b on interlevel distance T12 .

FIGURE 2.7.10 Dependences of coupling capacitances for interconnections shown in Fig. 2.7.1b on interlevel distance T12 .

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FIGURE 2.7.11 Dependences of ground capacitances for interconnections shown in Fig. 2.7.1c on interconnection widths.

For the trilevel interconnections shown in Fig. 2.7.1c, the dependences of the ground and coupling capacitances on the widths of the interconnection lines in the range 0.5–5 mm are shown in Figs. 2.7.11 and 2.7.12, respectively. The values of the ﬁxed parameters are also shown in the ﬁgures. As functions of the interconnection separation in the range 0.5–10 mm, the ground and coupling capacitances for the trilevel interconnections are shown in Figs. 2.7.13 and 2.7.14, respectively. Figures 2.7.15 and 2.7.16 show the variation of the various ground and coupling capacitances for the trilevel conﬁguration on the interlevel distance T23 in the range 2–50 mm.

2.7.7

Parametric Dependence of Interconnection Inductances

While modeling the interconnections for very high speed signal propagations, the inductances coupling the various interconnection lines should also be considered. The program ICIMPGV can be used to study the dependences of the various coupling inductances for the single-, bi-, and trilevel interconnection conﬁgurations shown in Fig. 2.7.1 on the various interconnection parameters. For example, for the three single-level interconnections, Fig. 2.7.17 shows the dependences of the

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105

FIGURE 2.7.12 Dependences of coupling capacitances for interconnections shown in Fig. 2.7.1c on interconnection widths.

FIGURE 2.7.13 Dependences of ground capacitances for interconnections shown in Fig. 2.7.1c on interconnection separations.

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FIGURE 2.7.14 Dependences of coupling capacitances for interconnections shown in Fig. 2.7.1c on interconnection separations.

FIGURE 2.7.15 Dependences of ground capacitances for interconnections shown in Fig. 2.7.1c on interlevel distance T23 .

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107

FIGURE 2.7.16 Dependences of coupling capacitances for interconnections shown in Fig. 2.7.1c on interlevel distance T23 .

FIGURE 2.7.17 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1a on interconnection widths.

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FIGURE 2.7.18 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1a on interconnection separations.

FIGURE 2.7.19 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1b on interconnection widths.

SIMPLIFIED FORMULAS FOR INTERCONNECTION CAPACITANCES

109

FIGURE 2.7.20 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1b on interconnection separations.

coupling inductances in nanohenrys per centimeter on the interconnection widths in the range 0.5–5 mm while Fig. 2.7.18 shows those on the interconnection separations in the range 0.5–10 mm. For the bilevel conﬁguration, the dependences of the various coupling inductances on the interconnection widths are shown in Fig. 2.7.19 while those on the interconnection separations are shown in Fig. 2.7.20. For the bilevel conﬁguration, the dependences of the various coupling inductances on the thickness of the GaAs substrate in the range 3–200 mm are shown in Fig. 2.7.21 while those on the interlevel distance T12 in the range 1–50 mm are shown in Fig. 2.7.22. For the trilevel interconnections, the various coupling inductances as functions of the interconnection widths in the range 0.5–4 mm are shown in Fig. 2.7.23, those as functions of the interconnection separations in the range 0.5–5 mm are shown in Fig. 2.7.24, and those as functions of the interlevel distance T23 are shown in Fig. 2.7.25.

2.8

SIMPLIFIED FORMULAS FOR INTERCONNECTION CAPACITANCES AND INDUCTANCES ON SILICON AND GaAs SUBSTRATES

In recent years, insulating substrates such as Cr-doped semi-insulating gallium arsenide (GaAs) have emerged as alternatives to silicon. This is partially because of the argument that interconnections fabricated on these substrates offer considerably

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FIGURE 2.7.21 Dependences of the coupling inductances for interconnections shown in Fig. 2.7.1b on substrate thickness.

FIGURE 2.7.22 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1b on interlevel distance T12 .

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111

FIGURE 2.7.23 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1c on interconnection widths.

FIGURE 2.7.24 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1c on interconnection separations.

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FIGURE 2.7.25 Dependences of coupling inductances for interconnections shown in Fig. 2.7.1c on interlevel distance T23 .

lower capacitances than those fabricated on silicon. In this section, simpliﬁed formulas for ﬁnding the line and coupling capacitances and inductances for interconnections fabricated on the oxide-passivated silicon and semi-insulating GaAs substrates are presented [26]. 2.8.1

Line Capacitances and Inductances

The cross section of an interconnection fabricated on an insulating substrate is shown in Fig. 2.8.1a. It is deﬁned by its width ðwÞ, height of the substrate ðhÞ, and relative dielectric constant of the material of the substrate ðer Þ. It is assumed that the thickness of the interconnection line is negligibly small. The approximate values of

FIGURE 2.8.1 Schematic of cross section of typical interconnection on (a) insulating substrate and (b) oxide-passivated silicon substrate. (From [26]. # 1982 by IEEE.)

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the line capacitance and inductance of the interconnection can be determined by using the formulas [26] 2pe0 eeff ln½8h=w þ w=ð4hÞ m 8h w þ L ¼ 0 ln w 4h 2p

C¼

wh ð2:8:1Þ

where eeff is the effective dielectric constant of the substrate material given by eeff ¼

er þ 1 er 1 h 0:5 þ 1 þ 10 2 2 w

The cross section of an interconnection fabricated on an oxide-passivated silicon substrate is shown in Fig. 2.8.1b. In this ﬁgure, tox is the oxide thickness and tSi is the thickness of the silicon substrate. For frequencies below 1 GHz, the approximate values of the line capacitance and inductance of the interconnection on an oxidepassivated silicon substrate can be determined by using the formulas 8 > <

2pe0 eeff ln½8h=w þ w=ð4hÞ C¼ h i > : e e w þ 2:42 0:44 tox þ 1 tox 6 0 r tox w w m 8h w þ h ¼ tox þ tSi L ¼ 0 ln 2p w 4h 2.8.2

w tox w tox

ð2:8:2Þ

Coupling Capacitances and Inductances

The Maxwellian capacitance matrix for an array of n conductors referring to a common ground plane has the general form 2

3

C11

C12

C1n

6C 6 21 6 . 6 . 4 . Cn1

C22 .. . Cn2

C2n 7 7 .. .. 7 7 . . 5 Cnn

The diagonal element Cii is the self-capacitance of conductor i and is a measure of the capacitance of a single conductor when all other conductors are grounded. The diagonal element Cij is the coefﬁcient of induction and is a measure of the negative of mutual capacitance between conductor i and conductor j. The Maxwellian capacitance matrices for a system of ﬁve conductors with equal line widths equal to 1 mm each and equal separations equal to 1 mm each fabricated on oxide-passivated silicon and semi-insulating gallium arsenide [26] are given below:

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Substrate: 1mm SiO2 2 0:776 6 0:043 6 Cij ¼ 6 0:004 4 0:002 0 Substrate GaAs: 2 1:066 6 0:520 6 Cij ¼ 6 0:154 4 0:092 0:090

on Si: 0:043 0:760 0:045 0:004 0:002

0:004 0:045 0:759 0:004 0:004

0:002 0:004 0:004 0:760 0:044

3 0 0:001 7 7 0:004 7 0:044 5 0:776

pF=cm

0:520 1:315 0:454 0:124 0:092

0:154 0:454 1:329 0:454 0:155

0:092 0:124 0:454 1:315 0:520

3 0:090 0:092 7 7 0:155 7 0:520 5 1:066

pF=cm

For a nonmagnetic and lossless substrate, the inductance matrix for the system of conductors can be derived from the Maxwellian capacitance matrix pﬃﬃﬃﬃﬃﬃ for the same system of conductors in free space, that is, for er ¼ 1. If vo ¼ 1= LC is the speed of light in free space, then the inductance matrix is given by 1 ½Lij ¼ 2 ½Cij 1 vo The inductance matrix for a system of ﬁve conductors with equal line widths equal to 1 mm each and equal separations equal to 1mm each fabricated on either oxide-passivated silicon or gallium arsenide substrates is given as 2 3 15:126 10:597 9:235 8:429 7:859 6 10:597 15:086 10:579 9:227 8:429 7 6 7 nH=cm Lij ¼ 6 9:235 10:579 15:080 10:579 9:235 7 4 8:429 9:227 10:579 15:086 10:597 5 7:859 8:429 9:235 10:597 15:115 Note that this inductance matrix is valid for all frequencies on insulating substrates but only below 1 GHz on silicon substrates. From an examination of the capacitance and inductance matrices, it can be seen that the magnetic couplings have a longer range than the electrical couplings. For example, the mutual inductance between lines 1 and 5 is only 30% less than that between lines 1 and 2 whereas the mutual capacitance has decreased by almost a factor of 5. 2.9

INDUCTANCE EXTRACTION USING FastHenry

Interconnection inductances, unlike capacitances and resistances, are not material properties since they are produced by induced magnetic ﬁelds in an interconnection layout. Interconnection capacitances and resistances can be reduced by an understanding of the electrical properties of the interconnection material. On the other hand, the interconnection inductances are considered a loop property and their values depend on the current return paths in an interconnection layout. Without prior knowledge of these current return paths or the so-called current loops, it would be very difﬁcult to obtain the exact values of the inductances in an IC. The only way out of this is to use a

INDUCTANCE EXTRACTION USING FastHenry

115

3D ﬁeld solver to calculate the exact current distributions in an interconnection layout and then determine the inductive impedances present in the system. This method can prove to be extremely time consuming, computer intensive, and uneconomical and the only alternative is to use a partial or approximate analysis technique which makes a trade-off between accuracy and computing efﬁciency. One such tool developed for the accelerated extraction of inductances is called FastHenry and is available under the broad title of Fast Field Solvers (http://www.fastﬁeldsolvers.com). 2.9.1

The Program FastHenry

FastHenry is a program capable of computing the frequency-dependent self and mutual inductances as well as the resistances of a 3D system of conductors. The data describing the geometry of the conductors and the frequencies of interest must be provided in an input ﬁle. This ﬁle speciﬁes every conductor in the system as a sequence of rectilinear segments connected between nodes where a node is a point in 3D space, as shown in Fig. 2.9.1. Every segment has a ﬁnite conductivity and has the shape of a parallelepiped whose height and width can be assigned. Any section of a segment can be further divided into an arbitrary number of parallel ﬁlaments, that is, parallelepipeds with smaller cross sections than the original one. This is done to validate the assumption that every ﬁlament carries a uniform current. In fact, the current may no longer be uniformly distributed along the cross section of a conductor segment when the frequency increases due to the skin effect. However, if the section is divided into smaller ﬁlaments, the current can be reasonably approximated as uniform in the ﬁlaments. In this way, it is possible to model the high-frequency effects on the segments. Ability to specify an arbitrary discretization of the volume of the conductors affects the accuracy of the results and is better as the discretization is reﬁned. It is interesting to note that the computational complexity of the analysis technique used in FastHenry grows only linearly with the number of ﬁlaments required to discretize the conductors. The results are provided in the form of a Maxwell impedance matrix ½Z ¼ ½R þ j½L. The results can then be converted into equivalent SPICE-like lumped-element circuit models with a utility called MakeLCircuit provided with

FIGURE 2.9.1

Splitting of conductors into segments and modeling them as RLC circuits [37].

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FastHenry. The network thus obtained is valid only for a single frequency. Alternatively, it is possible to generate a SPICE-like circuit capable of modeling the frequency-dependent inductances and resistances. This capability is very useful because it allows the user to see how signals are degraded in the time domain by the frequency-dependent responses of the conductors [38]. FastHenry is often used with a user interface tool called FastModel that allows the user to model and simulate the structure of conductors in a 3D editor making it possible to see the conductors described in a FastHenry input ﬁle in real time. FastModel can be integrated with FastHenry and provides features such as input ﬁle editing, unlimited number of 2D/3D views of the model, and print ﬁle capabilities. FastModel makes the inductance extraction process using FastHenry a much easier experience with the advantage that it allows the user to view the structure under analysis. 2.9.2

Extraction Results Using FastHenry

In this section, two examples illustrating the applications of FastHenry and FastModel are presented [33]. The ﬁrst example studies inductances for a single conductor placed at a certain distance above a ground plane while the second example deals with two coupled conductors above a ground plane. Copper has been chosen as the conductor material in both examples though the inductances, unlike the resistances and capacitances, are not a function of the material. The thickness and the area of the ground plane are chosen randomly because these values do not affect inductances in general. The current return path for the conductor is assumed to ﬂow through the ground plane. Dielectrics are not included in the layouts because they are known to have no effect on the inductances. 2.9.2.1 Single Conductor Above a Ground Plane In this example, the layout consists of a single conducting interconnection in 3D space above a ground plane. The default values of the conductor dimensions in the layout and other parameters are as follows: length 100 nm, width l0 nm, thickness 5 nm, distance of the conductor from the ground plane 30 nm, and frequency 500 MHz. The screen shot of this layout in FastModel is shown in Fig. 2.9.2 and the input ﬁle for FastHenry in this case is presented below:

FIGURE 2.9.2

Screen shot of single conducting interconnection above ground plane [33].

INDUCTANCE EXTRACTION USING FastHenry

117

************************************************************* FastHenry Input File for a Single Conductor Above a Ground Plane ************************************************************* * Setting the unit for all dimensions .units um * Deﬁning the ground plane g l x l ¼ 0 yl ¼ 0 zl ¼ 0 þ x2 ¼ 0.1 y2 ¼ 0 z2 ¼ 0 þ x3 ¼ 0.l y3 ¼ 0.1 z3 ¼ 0 * Thickness of the ground plane þ thick ¼ 0.025 * Discretization þ segl ¼ 5 seg2 ¼ 5 * Nodes for later reference þ nin (0.1,0.05,0) þ nout (0,0.05,0) * The straight conductor * The nodes N1 x ¼ 0 y ¼ 0.05 z ¼ 0.03 N2 x ¼ 0.1 y ¼ 0.05 z ¼ 0.03 * Elements connecting the node El N1 N2 w ¼ 0.01 h ¼ 0.005 nhinc ¼ l nwinc ¼ 2 * Shorting the end of the conductor with a corresponding * point on the ground plane beneath it .equiv nin N2 * Computing the loop inductance from N1 to a point directly underneath on the groundplane .external N1 nout * Computing the impedance for one frequency .freq fmin ¼ 5e8 fmax ¼ 5e8 ndec ¼ 0 * End of ﬁle .end *******************************************************

The dependence of inductance on the length of the conductor in the range 20–100 nm is shown in Fig. 2.9.3. This ﬁgure shows that the inductance increases rapidly with an increase in the conductor length and suggests that inductances for very short lines may be neglected safely. Figure 2.9.4 plots the dependence of the inductance on the width of the conductor in the range 10–50 nm and shows that the inductance reduces gradually with an increase in width. 2.9.2.2 Two Conductors Above a Ground Plane In this example, the system consists of two identical conducting interconnections placed above a conducting ground plane. The default values of the interconnection dimensions in the layout and other parameters are as follows: length 100 nm, width l0 nm, thickness 5 nm; spacing between the interconnections 30 nm, distance of the conductor from the ground plane 30 nm, and frequency 500 MHz. The screen shot of this layout in FastModel is shown in Fig. 2.9.5.

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FIGURE 2.9.3

Dependence of inductance on length of conductor [33].

FIGURE 2.9.4

Dependence of inductance on width of conductor [33].

FIGURE 2.9.5

Screen shot of two conducting interconnections above ground plane [33].

COPPER INTERCONNECTIONS: RESISTANCE MODELING

119

FIGURE 2.9.6 Dependences of self and coupling inductances for system of two interconnections on spacing between interconnections [33].

The dependences of the self and coupling inductances for a system of two identical interconnections on the spacing between the interconnections in the range 1–30 nm are shown in Fig. 2.9.6. In this ﬁgure, the mutual inductances are plotted for currents in the two interconnections ﬂowing in the same as well as opposite directions. This ﬁgure suggests that the self-inductances of the two interconnections are essentially independent of the spacing between them whereas the mutual inductances decrease with an increase in the interconnection spacing with a change of sign of the mutual inductance for the cases of similar and opposite currents.

2.10

COPPER INTERCONNECTIONS: RESISTANCE MODELING

The resistance of a relatively low frequency aluminum or another metallic interconnection of a regular shape can be determined from its dimensions (length and cross-sectional area) and the resistivity of its material. The high-frequency effect on the resistance can be accounted for by incorporating the decrease of the effective cross section due to skin effect. However, a copper interconnection deserves a special treatment because of its unique fabrication. The effective resistivity of a copper interconnection is expected to increase due to scattering of the currentcarrying electrons from the interconnection surfaces and other grain boundaries [39]. Further, as the cross section of the copper interconnection is reduced, the area occupied by the highly resistive diffusion barrier around the copper line will no longer be negligibly small, thereby increasing the effective resistance of the copper interconnection structure. Both the barrier effect and the surface scattering effect depend on the quality of the interface between copper and the diffusion barrier, proﬁle of the barrier layer in the overall cross-sectional proﬁle of the interconnection, minimum barrier thickness dictated by the reliability constraints, and operating temperature of the interconnection line. The barrier proﬁle is determined by the deposition technology employed for the interconnection fabrication, such as atomic layer deposition (ALD), PVD, collimated physical vapor deposition (CPVD), or ionized physical vapor deposition (IPVD).

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As the interconnection dimensions are scaled down in the future, the adverse effects of diffusion barrier and surface scattering are likely to become more and more important. With reduction in the interconnection dimensions, the mean free path of electrons in the bulk of the metal can become comparable to the wire dimensions resulting in signiﬁcant scattering from the copper–barrier interface. Further, the reliability constraints will not permit the barrier layer to scale down as rapidly as the copper metal dimensions, thereby increasing the relative effect of the high-resistance barrier material on the interconnection resistance. It is also expected that the operating temperature of the interconnection will go up due to self-heating because of increasing chip power density due to higher current densities combined with the use of low-dielectric material dielectrics with poor heat dissipation. These effects are expected to be less dominant in aluminum than in copper, and it is possible that the effective resistance of the copper interconnection may exceed that of a comparable aluminum interconnection in the near future. 2.10.1

Effect of Surface/Interface Scattering on Interconnection Resistivity

The effects of scattering of electrons from the interconnection surface and from the barrier interface on the resistivity have been modeled by [39]:

3ð1 PÞl rs ¼ r o 1 2d

Z 1

1

1 1 5 3 x x

1 1 ekx dx 1 Pekx

ð2:10:1Þ

where rs ¼ surface scattering-dependent resistivity ro ¼ bulk resistivity at operating temperature l ¼ mean free path of electrons in bulk of ﬁlm at temperature of operation d ¼ smallest thickness of metallic ﬁlm k ¼ ratio of smallest ﬁlm thickness to bulk mean free path ¼ d=l and P is an empirical parameter signifying the fraction of electrons undergoing elastic collisions at the interface: P ¼ 0 corresponds to diffuse scattering at the interface resulting in lower mobility of electrons whereas P ¼ 1 corresponds to elastic scattering resulting in no change in the mobility of electrons. Equation (2.10.1) indicates that the surface/interface scattering-dependent resistivity rs is always greater than the bulk resistivity ro. It also indicates that for a smaller value of k which corresponds to a smaller ﬁlm thickness and/or a higher mean free path of electrons, the surface scattering dominates the resistivity. At higher operating temperatures when the mean free path of electrons is smaller, k will be larger resulting in a smaller rs =ro ratio though the bulk resistivity ro itself is higher at higher temperatures. It is interesting to note that the effect of surface scattering will be more pronounced in a copper interconnection than that in an aluminum interconnection. This is because copper has a lower intrinsic resistivity and a higher mean free path of electrons resulting in smaller values of the parameter k.

COPPER INTERCONNECTIONS: RESISTANCE MODELING

2.10.2

121

Effect of Diffusion Barrier on Interconnection Resistivity

The presence of the required diffusion barrier around the copper interconnection has an adverse effect on the overall effective resistivity of the interconnection. (An aluminum interconnection does not require such a barrier and hence does not suffer from this effect.) The increased interconnection effective resistivity rb due to the presence of the diffusion barrier can be found from the equation [39]

1 rb ¼ ro 1 Ab =ðhwÞ

ð2:10:2Þ

where ro ¼ bulk resistivity of interconnection material, that is, copper Ab ¼ cross-sectional area occupied by barrier material w ¼ total width of interconnection (including copper and barrier layer) h ¼ total thickness of interconnection (including copper and barrier layer) The deﬁnitions of h and w are illustrated in Fig. 2.10.1 for a conformal barrier and for a nonconformal barrier where the shaded area shows the area Ab occupied by the barrier layer. Equation (2.10.2) is based on the assumption that there is no current ﬂowing in the barrier layer. This is a reasonable assumption because the resistivity of the barrier material is of the order of a few hundreds m cm whereas the resistivity of copper is a few m cm. This equation shows that the effective resistivity of the interconnection increases as the barrier area Ab increases. This area depends on two factors: (a) the minimum barrier thickness required for stopping the copper diffusion into the substrate and (b) the barrier proﬁle which is dictated by the barrier deposition technology. The barrier area is a minimum when a conformal deposition technology such as ALD is employed whereas a nonconformal deposition technology such as a PVD-based technology would require a thicker barrier at critical points resulting in a larger barrier area. It is expected that nonconformal barrier deposition technologies will become unsuitable as the interconnection dimensions are scaled down.

FIGURE 2.10.1 Barrier proﬁles of (a) conformal barrier and (b) nonconformal barrier. (From [39]. # 2002 by IEEE.)

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2.11

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

ELECTRODE CAPACITANCES IN GaAs MESFET: APPLICATION OF PROGRAM IPCSGV

In this section, the program IPCSGV presented in Section 2.5 is modiﬁed into a program called EPCSGM which is then used to determine the electrode parasitic capacitances in a GaAs MESFET [27]. The program EPCSGM is utilized to study the dependence of these capacitances on the various MESFET design parameters. The electrode capacitances have also been compared with the internal capacitances in a GaAs MESFET. Consider the schematic of a recessed-gate MESFET as shown in Fig. 2.11.1. For a self-aligned MESFET, the source, gate, and drain electrodes will be printed in the same plane on the GaAs substrate. The Green’s function elements for a recessedgate MESFET can be determined by following the steps outlined in the Section 2.5.1 and those for a self-aligned MESFET can then be obtained by setting the depth of recession of the gate electrode denoted by DR equal to zero. 2.11.1

Ground and Coupling Capacitances

The electrode capacitances in a MESFET can be found by ﬁrst reducing Eqs. (2.5.16) for the even- and odd-mode capacitances for a system of three electrodes, resulting in Cse ¼ Cs

Cge ¼ Cg

Cde ¼ Cd

Cso ¼ Cs þ 2Csg þ 2Csd Cgo ¼ Cg þ 2Csg þ 2Cgd Cdo ¼ Cd þ 2Csd þ 2Cgd

FIGURE 2.11.1 Schematic of a GaAs MESFET with a deep-recessed gate: DR is depth of recession of gate; DR ¼ 0 corresponds to MESFET with self-aligned gate.

ELECTRODE CAPACITANCES IN GaAs MESFET

123

and then solving these equations exactly resulting in the following expressions for the ground and coupling electrode parasitic capacitances in a MESFET: Cs ¼ Cse

Cg ¼ Cge

Cd ¼ Cde

Csg ¼ 14ðCde Cse Cge þ Cso þ Cgo Cdo Þ Csd ¼ 14ðCge Cse Cde þ Cso þ Cdo Cgo Þ Cgd ¼ 14ðCse Cge Cde þ Cgo þ Cdo Cso Þ

2.11.2

The Program EPCSGM

Source code of a computer program called Electrode Parasitic Capacitances in Single-Gate GaAs MESFETs (EPCSGM) that incorporates the steps outlined above is provided in Appendix 2.3 on the accompanying ftp site. For a given set of MESFET dimensions, the program computes the locations and dimensions of the rectangular subsections on the three electrodes, calculates the elements of the Green’s function matrix, inverts the matrix, evaluates the even- and odd-mode capacitances for each electrode separately, and ﬁnally determines the ground and coupling electrode parasitic capacitances in the MESFET in femtofarads. The inversion of the Green’s function matrix can be achieved by using the subroutine called MINV provided within the appendix or another matrix inversion subroutine. 2.11.2.1 Locations and Dimensions of Subsections The Cartesian coordinate system used to specify the locations of the subsections is shown in Fig. 2.11.2. Along the x direction, the source, gate, and drain electrodes are divided into N1x , N2x , and N3x sections, respectively, whereas, along the y direction,

FIGURE 2.11.2 Coordinate system used for determining locations and dimensions of rectangular subsections.

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PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

all three electrodes are divided into Ny sections. Then the number of sections on the three electrodes are given by Source N1 ¼ N1x N1y Gate N2 ¼ N2x Ny Drain N3 ¼ N3x Ny and the total number of subsections becomes N ¼ N1 þ N2 þ N3 If the source length is denoted by SL, the gate length by GL, the drain length by DL, the source–gate separation by DSG, the gate–drain separation by DGD, and width of the MESFET by W, then the length of the subsection along the x direction on the three electrodes will be given by Source x1 ¼

SL N1x

x2 ¼

GL N2x

x3 ¼

DL N3x

Gate

Drain

and the width of each subsection along the y direction on each electrode is given by y ¼

W Ny

If i denotes the number of a subsection ði ¼ 1; 2; 3; . . . ; NÞ, then the x coordinates of the midpoints of the subsections on the three electrodes can be found by the following scheme:

ELECTRODE CAPACITANCES IN GaAs MESFET

125

Source 1 xi ¼

2 3 2

x1 x1

for i ¼ 1; . . . ; Ny for i ¼ Ny þ 1; . . . ; 2Ny

and so on, until, for i ¼ N1 Ny þ 1; . . . ; N1,

xi ¼ N1x 12 x1 Gate xi ¼

SL þ DSG þ 12 x2 SL þ DSG þ 32 x2

for i ¼ N1 þ 1; . . . ; N1 þ Ny for i ¼ N1 þ Ny þ 1; . . . ; N1 þ 2Ny

and so on, until, for i ¼ N1 þ N2 Ny þ 1; . . . ; N1 þ N2,

xi ¼ SL þ DSG þ N2x 12 x2 Drain SL þ DSG þ GL þ DGD þ 12 x3 for i ¼ N1 þ N2 þ 1; . . . ; N1 þ N2 þ Ny xi ¼ SLþ DSGþGLþDGDþ 32 x3 for i ¼ N1 þ N2 þ Ny þ 1; . . . ; N1þN2 þ2Ny and so on, until for i ¼ N Ny þ 1; . . . ; N,

xi ¼ SL þ DSG þ GL þ DGD þ N3x 12 x3 The y coordinates of the midpoints of the subsections can be determined by the following scheme: ( yi ¼

1 2 3 2

y y

for i ¼ 1; Ny þ 1; 2Ny þ 1; . . . ; N Ny þ 1 for i ¼ 2; Ny þ 2; 2Ny þ 2; . . . ; N Ny þ 2

and so on, until, for i ¼ Ny, 2Ny , 3Ny ; . . . ; N,

yi ¼ Ny 12 y The z-coordinates of the midpoints of the subsections can be determined by the following scheme: For the self-aligned MESFET zi ¼ T

for

i ¼ 1; 2; 3; . . . ; N

126

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

for the deep-recessed-gate MESFET zi ¼ T

for

i ¼ 1; 2; 3; . . . ; N1

and

i ¼ N1 þ N2 þ 1; . . . ; N

while for the subsections on the gate electrode, that is, for i ¼ N1 þ 1; . . . ; N1 þ N2, zi ¼ T DR The central processing unit (CPU) time needed for running the program EPCSGM for a given set of MESFET dimensions increases approximately as the square of the total number of subsections. In principle, to justify the assumption of constant charge density over the surface of the subsection, its dimensions should be as small as possible and therefore the number of subsections should be as large as possible. However, the dependence of the values of the various electrode parasitic capacitances on the number of subsections used in the program is shown in Fig. 2.11.3. It shows that, for the typical MESFET dimensions, the capacitances increase as the number of subsections is increased, but after a particular value of N the capacitances converge to their true values. Therefore, one way to reduce the CPU time will be to determine the capacitance values using a small number of subsections and then to use an appropriate extrapolation scheme to determine the true values. For example, in the present case, it can be veriﬁed that capacitance values within 10% of their true values can be obtained by ﬁrst using only six to eight subsections in EPCSGM and then multiplying the self-capacitances (Cs , Cg , and Cd ) by 1.1 and the coupling capacitances (Csg , Cgd , and Csd ) by 1.2. It is possible to develop other extrapolation schemes to reduce the CPU time.

FIGURE 2.11.3 Dependence of electrode parasitic capacitances for GaAs MESFET with typical dimensions on number of rectangular subsections.

ELECTRODE CAPACITANCES IN GaAs MESFET

2.11.3

127

Dependence on MESFET Dimensions

The program EPCSGM can be used to study the dependence of the electrode parasitic capacitances in a GaAs MESFET on the various MESFET dimensions. For the following results, one of the dimensions is varied in a speciﬁc range while the other dimensions are set at some ﬁxed typical values which are chosen to be the following: SL ¼ DL ¼ 10 mm, GL ¼ 0.5 mm, DSG ¼ DGD ¼ 2 mm, T ¼ 200 mm, and device width W ¼ 100 mm. The dependence of the electrode parasitic capacitances in a self-aligned GaAs MESFET on the height of the electrodes above the bottom ground plane in the range 10–200 mm is shown in Fig. 2.11.4. It shows that all the electrode capacitances, particularly Csg and Cgd , decrease sharply when the electrodes are printed on the substrate as compared to when they are embedded in the substrate. Therefore, the following results were obtained for the case when the electrodes are printed on top of the substrate. Figure 2.11.5 shows the dependence of the electrode capacitances on the source and drain lengths (keeping SL ¼ DL) in the range 0.1–50 mm. It shows that Cg decreases as SL and DL are increased. This is because of the increased shielding of the electric ﬁeld lines between the gate electrode and the ground by the ﬁeld lines between the source and the gate and by those between the drain and the gate electrodes. Such a shielding also explains the rapid increase in Cg when the

FIGURE 2.11.4 Electrode parasitic capacitances in self-aligned GaAs MESFET as function of height of electrodes above bottom ground plane.

128

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.11.5 Electrode parasitic capacitances in self-aligned GaAs MESFET as function of source and drain lengths (keeping SL ¼ DL).

source–gate and gate–drain separations (keeping DSG ¼ DGD) are increased, as shown in Fig. 2.11.6. This ﬁgure also shows the signiﬁcant decreases in Csg , Cgd , and Csd when DSG and DGD are increased. The dependence of the electrode capacitances on the gate length in the range 0.05–10 mm is shown in Fig. 2.11.7.

FIGURE 2.11.6 Electrode parasitic capacitances in self-aligned GaAs MESFET as function of the source–gate and gate–drain separations (keeping DSG ¼ DGD).

ELECTRODE CAPACITANCES IN GaAs MESFET

129

FIGURE 2.11.7 Electrode parasitic capacitances in self-aligned GaAs MESFET as function of gate length.

Figure 2.11.8 shows the dependence of the electrode capacitances on the substrate thickness in the range 2–500 mm. It suggests that all self-capacitances increase while mutual capacitances decrease when substrate thickness is decreased. As a function of the width of the MESFET, the variation of the various capacitances is shown in Fig. 2.11.9. It shows that as the device width is increased, all the capacitances

FIGURE 2.11.8 Electrode parasitic capacitances in self-aligned GaAs MESFET as function of substrate thickness.

130

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

FIGURE 2.11.9 Electrode parasitic capacitances in self-aligned GaAs MESFET as function of width of MESFET.

increase almost linearly. Variations from near-linear behavior for small device widths are due to the increased contribution of the fringing ﬁelds. For a GaAs MESFET with a deep recessed gate, Fig. 2.11.10 shows the variation of the electrode capacitances as the depth of recession of the gate is increased in the range 0.1–10

FIGURE 2.11.10 Electrode parasitic capacitances in deep-recessed GaAs MESFET as function of depth of recession of gate electrode.

131

ELECTRODE CAPACITANCES IN GaAs MESFET

FIGURE 2.11.11 Equivalent circuit diagram for GaAs MESFET including electrode parasitic capacitances.

mm. In the above results, the possible shielding of the electric ﬁeld lines between the electrodes and the bottom ground plane by the active layer (see Fig. 2.11.2) in the conducting state has not been considered. Such a shielding, if present, will increase Cs , Cg , and Cd and decrease Csg , Cgd , and Csd .

TABLE 2.11.1 Comparison of Internal Capacitances and Electrode Parasitic Capacitances in GaAs MESFETs MESFET Dimensions

Internal Capacitancesa

GL ¼ 1 mm

ðiÞ Cgs ðiÞ Cgd

W ¼ 500 mm

GL ¼ 15 mm

ðiÞ Cdc

ðiÞ Cgs

Electrode Parasitic Capacitances

¼ 620 fF

ðeÞ Cgs

¼ 26 fF

¼ 14 fF

ðeÞ Cgd

¼ 26 fF

¼ 20 fF

ðeÞ Csd

¼ 25 fF

ðeÞ Cd

¼ 26 fF

CgðeÞ

¼ 4 fF

ðeÞ Cgs

¼ 34 fF

¼ 675 fF

ðeÞ

Cgd ¼ 34 fF W ¼ 600 mm

ðiÞ

Cgd ¼ 20 fF

ðeÞ

Csd ¼ 30 fF ðeÞ

Cd ¼ 31 fF CgðeÞ ¼ 6 fF a b

Internal capacitances are at Vgs ¼ 0 and Vd5 ¼ 5 V. Internal capacitances are measured values for high-pinchoff-voltage devices.

References 40

41b

132

2.11.4

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

Comparison with Internal MESFET Capacitances

The equivalent circuit diagram for a GaAs MESFET with the source electrode grounded including the electrode parasitic capacitances [denoted by the ðiÞ ðiÞ ðiÞ superscript (e)] is shown in Fig. 2.11.11. The parameters Csg , Cgd and Cdc ðiÞ represent the internal capacitances in the MESFET, where Cdc stands for the capacitance of the dipole layer while the other symbols are self-explanatory. A comparison of the internal capacitances and the electrode parasitic capacitances for two GaAs MESFETs [27] is shown in Table 2.11.1. Electrode parasitic capacitances are determined by using the given values of GL and W while the other dimensions are set equal to their typical values. Table 2.11.1 shows ðiÞ ðeÞ that while Cgd is more than 20 times Cgs , the other electrode capacitances ðiÞ are comparable or even more in magnitude than the internal capacitances Cgd ðiÞ and Cdc . EXERCISES E2.1 Consider a charge placed in air above a dielectric material of permittivity e1 which is deposited on another material of permittivity e2 which in turn is placed on a bottom ground plane. (a) Draw a diagram showing the image charges for this system. (b) Determine an expression for the Green’s function matrix element Gij for this system. E2.2 Consider a charge embedded in a dielectric material of permittivity e1 which is deposited on another material of permittivity e2 which in turn is placed on a bottom ground plane. (a) Draw a diagram showing the image charges for this system. (b) Find the Green’s function matrix element Gij for this system. E2.3 Modify the program IPCSGV given in Appendix 2.1 to include one more interconnection exactly below the fourth interconnection. Comment on the relative accuracy of the results obtained with the modiﬁed program. E2.4 Use Eqs. (2.8.1) and (2.8.2) to calculate the line capacitances of an interconnection on 250-mm-thick silicon (assume 1 mm SiO2 thickness) and GaAs for line widths in the range 1–100 mm. Plot your values and make comments on the relative lowering of capacitance on an insulating substrate as the interconnection width increases. E2.5 Using Eqs. (2.8.1) and (2.8.2), calculate and plot the line inductances of an interconnection on 250-mm-thick silicon (assume 1 mm SiO2 thickness) and GaAs for line widths in the range 1–100 mm.

REFERENCES

133

E2.6 Discuss the characteristics of a numerical model that make it suitable for inclusion in a CAD tool. Review the techniques presented in this chapter for their suitability for inclusion in the CAD tools.

REFERENCES 1. K. J. Binns and P. J. Lawrenson, Analysis and Computation of Electric and Magnetic Field Problems, New York: MacMillan, 1963. 2. Y. Rahmat-Samii, T. Itoh, and R. Mittra, ‘‘A Spectral Domain Technique for Solving Coupled Microstrip Line Problems,’’ Arch. Electron. Ubertragungstechnik, vol. 27, pp. 69–71, 1973. 3. N. G. Alexopoulos, J. A. Maupin, and P. T. Greiling, ‘‘Determination of the Electrode Capacitance Matrix for GaAs FETs,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-28, no. 5, pp. 459–466, 1980. 4. K. H. Huebner, The Finite Element Method for Engineers, New York: Wiley, 1975. 5. J. W. Duncan, ‘‘The Accuracy of Finite-Difference Solutions of Laplace’s Equations,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-15, pp. 575–582, Oct. 1967. 6. G. Liebmann, ‘‘Solutions of Partial Differential Equations with a Resistance Network Analogue,’’ Br. J. Appl. Phys., vol. 1, pp. 92–103, Apr. 1950. 7. B. L. Lennartson, ‘‘A Network Analog Method for Computing the TEM Characteristics of Planar Transmission Lines,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-20, pp. 586–591, Sept. 1972. 8. C. L. Chao, ‘‘A Network Reduction Technique for Computing the Characteristics of Microstrip Lines,’’ Proc. IEEE Symp. Circuits Syst., pp. 537–541, 1977. 9. C. L. Chao, ‘‘A Network Reduction Technique for Microstrip Three Dimensional Problems,’’ IEEE MTT-S Int. Symp. Dig., pp. 73–75, 1978. 10. V. K. Tripathi and R. J. Bucolo, ‘‘A Simple Network Analog Approach for the Quasi-Static Characteristics of General Lossy, Anisotropic, Layered Structures’’. 11. V. K. Tripathi and R. J. Bucolo, ‘‘Analysis and Modelling of Multilevel Parallel and Crossing Interconnection Lines,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-34, no. 3, Mar. 1987. 12. C. L. Chao, ‘‘Characteristics of Unsymmectrical Broadside-Coupled Strips in an Inhomogenous Dielectric Medium,‘‘ IEEE Int. Microwave Symp. Digest, pp. 119–121, May 1975. 13. C. P. Wen, ‘‘Coplanar-Waveguide Directional Couplers,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-18, pp. 318–322, June 1970. 14. T. Hatsuda, ‘‘Computation of Coplanar-Type Strip-Line Characteristics by Relaxation Method and Its Application to Microwave Circuits,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-23, pp. 795–802, Oct. 1975. 15. A. E. Ruehli and P. A. Brennan, ‘‘Efﬁcient Capacitance Calculations for ThreeDimensional Multiconductor Systems,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-21, p. 2, Feb. 1973. 16. A. E. Ruehli and P. A. Brennan, ‘‘Capacitance Models for Integrated Circuit Metallization Wires,’’ IEEE J. Solid State Circuits, vol. SC-10, pp. 530–536, Dec. 1975.

134

PARASITIC RESISTANCES, CAPACITANCES, AND INDUCTANCES

17. A. E. Ruehli and P. A. Brennan, ‘‘Accurate Metallization Capacitances for Integrated Circuits and Packages,’’ IEEE J. Solid State Circuits, vol. SC-8, pp. 288–290, Aug. 1973. 18. C. D. Taylor, G. N. Elkhouri, and T. E. Wade, ‘‘On the Parasitic Capacitances of Multilevel Parallel Metallization Lines,’’ IEEE Trans. Electron Devices, vol. ED-32, no. 11, Nov. 1985. 19. W. H. Dierking and J. D. Bastian, ‘‘VLSI Parasitic Capacitance Determination by Flux Tubes,’’ IEEE Circuits Syst. Mag., pp. 11–18, Mar. 1982. 20. N. G. Alexopoulos and N. K. Uzunoglu, ‘‘A Simple Analysis of Thick Microstrip on Anisotropic Substrates,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-26, pp. 455–456, June 1978. 21. A. Farrar and A. T. Adams, ‘‘Computation of Lumped Microstrip Capacities by Matrix Methods—Rectangular Sections and End Effects,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-19, pp. 495–497, May 1971. 22. P. D. Patel, ‘‘Calculation of Capacitance Coefﬁcients for a System of Irregular Finite Conductors on a Discreet Sheet,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-19, no. 11, pp. 862–869, Nov. 1971. 23. T. Sakurai and K. Tamaru, ‘‘Simple Formulas for Two- and Three-Dimensional Capacitances,’’ IEEE Trans. Electron Devices, vol. ED-30, pp. 183–185, Feb. 1983. 24. Z. Ning, P. M. Dewilde, and F. L. Neerhoff, ‘‘Capacitance Coefﬁcients for VLSI Multilevel Metallization Lines,’’ IEEE Trans. Electron Devices, vol. ED-34, no. 3, pp. 644–649, Mar. 1987. 25. A. K. Goel and Y. R. Huang, ‘‘Parasitic Capacitances and Inductances for Multilevel Interconnections on GaAs-Based Integrated Circuits,’’ J. Electromag. Waves Appl, vol. 5, nos. 4/5, pp. 477–502, 1991. 26. H. T. Youn, Y. Lin, and S. Y. Chiang, ‘‘Properties of Interconnections on Silicon, Sapphire and Semiinsulating Gallium Arsenide Substrates,’’ IEEE Trans. Electron Devices, vol. ED-29, pp. 439–444, Apr. 1982. 27. A. K. Goel, ‘‘Electrode Parasitic Capacitances in Self-Aligned and Deep-Recessed GaAs MESFETs,’’ Solid State Electron., vol. 31, no. 10, pp. 1471–1476, 1988. 28. Y. I. Ismail, E. G. Friedman, and J. L. Neves ‘‘Exploiting On-Chip Inductance in High Speed Clock Distribution Networks,’’ IEEE Trans.VLSI Syst., vol. 9, no. 6, pp. 963–973, Dec. 2001. 29. Y. I. Ismail, E. G. Friedman, and J. L. Neves ‘‘Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines,’’ IEEE Trans. Circuits Syst. I, vol. CAS-46, pp. 950–961, Aug. 1999. 30. Y. I. Ismail and E. G. Friedman, ‘‘Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits,’’ IEEE Trans. VLSI Syst., vol. 8, no. 2, pp. 195–206, Apr. 2000. 31. M. Chowdary, Y. I. Ismail, C. V. Kashyap, and B. L. Krauter, ‘‘Performance Analysis of Deep Sub-Micron VLSI Circuits in the Presence of Self and Mutual Inductance,’’ IEEE Int. Symp. Circuits Syst. ISCAS, Low-Noise Circuits Interconnect Issues, vol. IV, pp. 197–200, May 2002. 32. Y. Massoud, S. Majors, J. Kawa, T. Bustami, D. MacMillen, and J. White, ‘‘Managing OnChip Inductive Effects, IEEE Trans. VLSI Syst., vol. 10, no. 6, Dec. 2002.

REFERENCES

135

33. J. K. Parambil, ‘‘Extraction of On-Chip Inductances in the Nano to Micro Scale Range,’’ M. S. Thesis, Michigan Tech. University, 2004. 34. R. F. Harrington, Field Computation by Moment Methods. New York: MacMillan, 1968. 35. J. A. Maupin, ‘‘Self- and Mutual-Capacitance of Printed or Embedded Patch Conductors,’’ M. S. Thesis, University of California, Los Angeles, 1979 36. E. Weber, Electromagnetic Fields Theory and Applications. New York: Wiley, 1957. 37. I. Stakgold, Boundary Value Problems of Mathematical Physics, Vol. 2, New York: Macmillan, 1968. 38. M. Kamon, M. J. Tsuk, and J. White ‘‘FastHenry—A Multipole-Accelerated 3-D Inductance Extraction Program,’’ IEEE Trans. Microwave Theory Techn., vol. 42, pp. 1750–1758, Sept. 1994. 39. P. Kapur, J. P. McVittie, and K. C. Saraswat, ‘‘Technology and Reliability Constrained Future Copper Interconnects—Part I: Resistance Modeling,’’ IEEE Trans. Electron Devices, vol. 49, no. 4, pp. 590–597, Apr. 2002. 40. C. A. Liechti, IEEE Trans. Microwave Theory Tech, vol. MTT-24, no. 6, pp. 279–300, June 1976. 41. T. Chen and M. S. Shur, IEEE Trans. Electron Devices, vol. ED–12, no. 5, pp. 883–891, May 1985.

CHAPTER THREE

Interconnection Delays Among some of the advancements in VLSI technology in the recent years, highspeed silicon and GaAs technologies have been developed rapidly and propagation delay times of less than a picosecond per gate have been achieved. For VLSI circuits, the propagation delays and crosstalk noise associated with signal transmissions on interconnections have become the primary factors in limiting circuit speed and chip density. In most cases, interconnection delays on an IC chip account for more than 50% of the total delays. A comprehensive understanding of the dependence of the interconnection delays on the various interconnection parameters is needed for optimum chip design. The modern interconnection layout is an extremely high density structure with millions of metal lines running vertically and horizontally on various levels and layers. The interconnection delay models used in the industry have changed over time since the relative signiﬁcance of the different interconnection parasitics has changed over time. Until a few years ago, only interconnection capacitances were considered to be signiﬁcant enough to contribute to the overall chip delay. Then with the advent of complex circuits, heavy scaling and the use of longer interconnection lines made interconnection resistance an important factor in delay models. Interconnection delay models could be classiﬁed as lumped-capacitance models, simple RC models, lumped RC models, and distributed RC models. There has been an emphasis on ﬁnding different materials, fabrication techniques, and interconnection layouts to minimize RC delays. For modern ICs which are much faster and smaller, it is important to include interconnection inductances in the delay models. In fact, inductance is becoming as important as capacitance was a few years ago.

High-Speed VLSI Interconnections, Second Edition By Ashok K. Goel Copyright # 2007 John Wiley & Sons, Inc.

136

INTERCONNECTION DELAYS

137

In the literature, numerous numerical techniques are available to model timedomain pulse propagation in interconnection lines on high-speed digital circuits, including multilevel interconnections [1–33]. The method of characteristics modiﬁed to include frequency-dependent losses has been employed [4–6] and the well-known transmission line theory has been used to analyze high-speed interconnections [16, 17, 22–25]. The use of congruent modeling techniques where the researchers have attempted to model the interconnections in terms of lumped and distributed circuit elements available in CAD programs such as SPICE has been demonstrated [9, 13] and SPICE-like models have been developed [26, 27]. Specialized techniques to compute the time-domain pulse responses of interconnection structures terminated in linear and nonlinear networks from their frequencydomain analysis have been reported [12, 15]. In most cases, interconnections have been modeled as single lossy lines or multiple coupled lossless microstriplines. High-frequency effects such as conductor loss, dielectric loss, skin effect, and frequency-dependent effective dielectric constant have also been studied for a microstrip interconnection [18]. More recently, research has focused on developing approximate models for the transient response of distributed RLC lines [19, 20, 29– 33]. This chapter is organized as follows: An analysis of interconnection delays on very high speed VLSI chips using a metal–insulator–semiconductor microstripline model is presented in Section 3.1. A computer-efﬁcient model based on the transmission line analysis of propagation delays in high-density single-level interconnections on GaAsbased very high speed ICs is presented in Section 3.2. An algorithm for studying signal propagation in single-, bi-, and trilevel highdensity interconnections on GaAs-based ICs is presented in Section 3.3. A model of propagation delays in bilevel parallel and crossing interconnections on GaAs-based ICs is presented in Section 3.4. A SPICE model for lossless parallel interconnections modeled as multiple coupled microstrips is presented in Section 3.5. The SPICE model presented in Section 3.5 is extended to lossy parallel and crossing interconnections in Section 3.6. High-frequency effects such as conductor loss, dielectric loss, skin effect, and frequency-dependent effective dielectric constant are discussed in Section 3.7. A model of interconnection delays including the very high frequency effects is presented in Section 3.8. Closed-form expressions for interconnection delays using RC and RLC models for an interconnection are presented in Section 3.9. A simpliﬁed model of the interconnection delays in multilayer ICs is presented in Section 3.10. Delay analyses of an active interconnection driven by several mechanisms are presented in Section 3.11.

138

INTERCONNECTION DELAYS

FIGURE 3.1.1 IEEE.)

3.1

An MIS microstripline model for interconnection. (From [11]. # 1984 by

METAL–INSULATOR–SEMICONDUCTOR MICROSTRIPLINE MODEL OF AN INTERCONNECTION

In this section, interconnection delays on a very high speed IC chip are investigated using a metal-insulator-semiconductor (MIS) microstripline model for the interconnection [11]. 3.1.1

The Model

The MIS single microstripline used in this section is shown in Fig. 3.1.1. Note that the microstripline is formed on a surface-passivated semiconductor substrate which in turn is placed on a metallized back. Figure 3.1.2 shows the equivalent circuit per

FIGURE 3.1.2 Equivalent circuit per unit length of MIS microstripline. (From [11]. # 1984 by IEEE.)

METAL–INSULATOR–SEMICONDUCTOR MICROSTRIPLINE MODEL

139

unit length of the MIS microstripline used in the following analysis. The symbols used in Fig. 3.1.2 are deﬁned as follows: C1 ¼ insulator capacitance C2 ¼ semiconductor capacitance Gs ¼ transverse conductance of semiconductor L1 ¼ inductance of insulator L2 ¼ inductance of air region Zs ðoÞ ¼ impedance of semiconductor region including semiconductor inductance and longitudinal resistance In terms of the length parameters shown in Fig. 3.1.3, which shows the inhomogenous parallel waveguide mapped from the MIS microstripline by Schwarz–Christoffel transformation, the various circuit elements are given by the following expressions [11]: C1 ¼ Gs ¼ s?

aþ bþ 2

aþ a ¼ e1 b bþ 1 1 L1 ¼ m0

C2 ¼ eeff bþ 1 a0

aþ bþ 2

L2 ¼ m0

bþ 2 aþ a0

and the impedance of the semiconductor region, Zs ðoÞ, is given by the expression Zs ðoÞ ¼ jom0

bþ 2 a0

1 gm bþ 2

tanhðgm bþ 2Þ

where gm ¼

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ jom0 s11

h2 s11 ¼ s

h ¼

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ jE0 ðE0 K 0 k2 Þj

FIGURE 3.1.3 Inhomogenous parallel waveguide mapped from MIS microstripline by Schwarz–Christoffel transformation. (From [11]. # 1984 by IEEE.)

140

INTERCONNECTION DELAYS

and, referring to Fig. 3.1.3, h is the average scaling parameter between the center of the top plane and the center of the bottom plane. The scaling parameter (h) of the Schwarz–Christoffel transformation is given by 2 0 0 2 2 pW h ¼ E K k sn 2b where sn is the Jacobi elliptic function and K0 and E0 are complete elliptic integrals of the ﬁrst and second kinds with modulus k, respectively. Note that Zs ðoÞ is frequency dependent because of the skin effect in the semiconductor. For a given interconnection geometry, the transient waveforms can be calculated by the following steps: (a) calculation of equivalent circuit parameters; (b) calculation of characteristic impedance and propagation constants based on the equivalent circuit shown in Fig. 3.1.2; and (c) calculation of the transient waveforms under arbitrary excitation and termination conditions by the inverse Laplace transformation. The last step involving inverse Laplace transformation can be carried out using the standard trigonometric function expansion method. 3.1.2

Simulation Results

3.1.2.1 Semi-Inﬁnite Interconnections For an interconnection of semi-inﬁnite length (which is equivalent to the line of ﬁnite length terminated with a hypothetical matched load), the dependences of the propagation delay time (time to 50% rise) and rise time (time from 10 to 90% rise) of the step response on the width of the interconnection are shown in Fig. 3.1.4, and

FIGURE 3.1.4 Dependences of delay time and rise time on interconnection width for semiinﬁnite interconnection. The rise time of the input pulse is assumed to be 8 ps. (From [11]. # 1984 by IEEE.)

METAL–INSULATOR–SEMICONDUCTOR MICROSTRIPLINE MODEL

141

FIGURE 3.1.5 Dependences of delay time and rise time on distance z from signal source for semi-inﬁnite interconnection. The rise time of the input pulse is assumed to be 8 ps. (From [11]. # 1984 by IEEE.)

Fig. 3.1.5 shows these dependences on the distance z from the signal source. For a semi-inﬁnite interconnection, the dependences of the delay and rise times on the substrate resistivity in the range 104–105 cm are shown in Fig. 3.1.6. The responses are calculated at positions with distances of z ¼ 1 mm and z ¼ 3 mm from the signal source. The results of Fig. 3.1.6 can be explained in terms of the three fundamental modes, that is, the skin effect mode, the slow-wave mode, and the dielectric quasi-TEM mode, as follows: (a) The increase of the delay time in the mid resistivity range is because of the slow-wave mode and (b) the rise time peaks on both sides of the delay time peak are due to mode transitions from the slow-wave mode either to the dielectric quasi-TEM mode or to the skin effect mode. 3.1.2.2 Interconnections between Logic Gates For an interconnection connecting two logic gates shown in Fig. 3.1.7a, an equivalent model is shown in Fig. 3.1.7b, where Rs is the output resistance of the driving gate and corresponds to the resistance of the input signal source while CL is the input capacitance of the driven gate and corresponds to the load capacitance of the interconnection line. In gates consisting of FET-type devices such as MESFETs, metal–oxide–semiconductor FETs (MOSFETs), and high electron mobility transistors (HEMTs), Rs is approximately equal to the inverse of the transconductance gm . To determine CL , it can be used as a rule of thumb that a standard 1-mm-gate GaAs MESFET has approximately an input gate capacitance of 1 fF per 1 mm gate width. The transconductance gm and the output resistance Rs of

142

INTERCONNECTION DELAYS

FIGURE 3.1.6 Calculated dependences of delay time and rise time on substrate resistivity for semi-inﬁnite interconnection. The rise time of the input pulse is assumed to be 8 ps. (From [11]. # 1984 by IEEE.)

various FET devices each of gate length 1 mm and gate width 10 mm are given in Table 3.1.1. The calculated voltage waveforms for an interconnection of width 3 mm and length 3 mm for two source resistances of 1 k and 100 and for various values of the substrate resistivity are given in Figs. 3.1.8a and b, respectively. For the sake of

FIGURE 3.1.7 (a) Schematic of interconnection between two logic gates. (b) Its equivalent model. (From [11]. # 1984 by IEEE.)

METAL–INSULATOR–SEMICONDUCTOR MICROSTRIPLINE MODEL

TABLE 3.1.1

143

Transconductance gm and Rs of Various FET Devices

Device GaAs MESFET Si MOSFET HEMT (77K)

gm (mS) 1.4 0.8 2.9

Rs () 710 1250 350

Source: From [11]. # 1984 IEEE. Note: Gate length, 1 mm; gate width, 10 mm.

comparison, the waveforms based on the lumped-capacitance approximation for r ¼ 1 and r ¼ 0 are also included in Figs. 3.1.8a and b. It can be concluded that the lumped-capacitance approximation yields reasonably good results when the source resistance is high and the response is slow. However, if the source resistance is low and the response is fast, then the results based on the lumped-capacitance approximation become rather inadequate. The dependences of the calculated delay times and rise times on the signal source resistance for several values of substrate resistivity are shown in Figs. 3.1.9 and 3.1.10, respectively. For the sake of comparison, the values based on the lumpedcapacitance approximation for r ¼ 1 and r ¼ 0 are also included in Figs. 3.1.9 and 3.1.10. It can be seen that the lumped-capacitance approximation yields reasonably good results when the delay time is nearly over 200 ps. The results in Figs. 3.1.9 and 3.1.10 also indicate that the semi-insulating substrates offer a signiﬁcant advantage over semiconducting substrates in both delay and rise times.

FIGURE 3.1.8 Calculated step response waveforms for (a) Rs ¼ 1 k and (b) Rs ¼ 100 . Dimension parameters: a ¼ 3 mm, z ¼ 3 mm, b1 ¼ 1 mm, b2 ¼ 200 mm. Results based on lumped-capacitance approximation shown by dashed curves. (From [11]. # 1984 by IEEE.)

144

INTERCONNECTION DELAYS

FIGURE 3.1.9 Dependence of calculated delay times on signal source resistance for several values of substrate resistivity. Results based on lumped-capacitance approximation shown by dashed curves. (From [11]. # 1984 by IEEE.)

FIGURE 3.1.10 Dependence of calculated rise times on signal source resistance for several values of substrate resistivity. Results based on lumped-capacitance approximation shown by dashed curves. (From [11]. # 1984 by IEEE.)

TRANSMISSION LINE ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

3.2

145

TRANSMISSION LINE ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

In this section, an algorithm for calculating propagation delays in high-density, single-level interconnections on GaAs-based very high speed ICs is presented. The interconnection has been modeled as a distributed-element equivalent circuit and the effects of capacitive coupling with the neighboring interconnections have been included. The technique presented in the model can be applied to lossy as well as lossless lines and can be easily extended to include coupling with any number of neighboring lines. The interconnection capacitances can be determined by the method of moments in conjunction with a Green’s function appropriate for the geometry of the interconnections [34]. As mentioned earlier, the capacitances thus determined include the fringing ﬁelds as well as the shielding effects due to the presence of neighboring conductors. The model has been used to determine the dependences of delay times and rise times (deﬁned as the times taken by the output voltages to rise from 0–50% and 10–90% of their steady state values, respectively [35]) on the interconnection dimensions and other parameters. 3.2.1

The Model

An interconnection modeled as a transmission line driven by a unit step voltage source and terminated by a load ZL is shown in Fig. 3.2.1. All the elements shown in

FIGURE 3.2.1 Interconnection modeled as transmission line driven by unit step voltage source and terminated by load ZL . Coupling of interconnection with its nearest two neighbors on each side also shown.

146

INTERCONNECTION DELAYS

the ﬁgure are per unit length of the interconnection. Capacitive couplings of the line with its ﬁrst and second neighbors are also shown in the ﬁgure. The series resistance and inductance elements for the neighboring interconnections will not affect the propagation characteristics along the interconnection in question; therefore, these are not included in the model. The symbols used in the equivalent circuit of Fig. 3.2.1 are deﬁned as follows: R ¼ resistance of interconnection line L ¼ inductance of interconnection line Ci ¼ self-capacitance (i.e., capacitance between conductor and ground plane) of interconnection line Cil1 ¼ mutual capacitance between interconnection and its ﬁrst neighbor on its left Cir1 ¼ mutual capacitance between interconnection and its ﬁrst neighbor on its right Cil2 ¼ mutual capacitance between interconnection and its second neighbor on its left Cir2 ¼ mutual capacitance between interconnection and its second neighbor on its right Cl1 ¼ self-capacitance of ﬁrst neighbor on left of interconnection Cl2 ¼ self-capacitance of second neighbor on left of interconnection Cr1 ¼ self-capacitance of ﬁrst neighbor on right of interconnection Cr2 ¼ self-capacitance of second neighbor on right of interconnection As far as the propagation along the interconnection is concerned, the effect of its coupling with its ﬁrst right neighbor is to connect an impedance Z1 in parallel with the capacitance Ci , where Z1 ¼

Cir1 þ Cr1 sCr1 Cir1

ð3:2:1Þ

Similarly, the contributions of coupling of the interconnection with its second right neighbor, the ﬁrst left neighbor, and the second left neighbor are to connect impedances Z2 , Z3 , and Z4 , respectively, in parallel with Ci , where Cir2 þ Cr2 sCr2 Cir2 Cil1 þ Cl1 Z3 ¼ sC11 Cil1 Cil2 þ Cl2 Z4 ¼ sCl2 Cil2

Z2 ¼

ð3:2:2Þ ð3:2:3Þ ð3:2:4Þ

Therefore, the equivalent circuit of Fig. 3.2.1 reduces to that shown in Fig. 3.2.2. Figure 3.2.2 shows one section of the equivalent circuit only and can be used to

TRANSMISSION LINE ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

147

FIGURE 3.2.2 One section of uncoupled interconnection line equivalent to each section of coupled lines of Fig. 3.2.1.

determine the propagation constant for the interconnection line as follows. The propagation constant g is deﬁned by the relationship sﬃﬃﬃﬃﬃ Zs g¼ ð3:2:5Þ Zp where the series impedance per unit length Zs is given by Zs ¼ R þ sL

ð3:2:6Þ

and the parallel impedance per unit length, Zp , is the impedance of the parallel combination of Ci , Z1 , Z2 , Z3 , and Z4 , that is, 1 1 1 1 1 ¼ þ þ þ þ sCi Zp Z1 Z 2 Z 3 Z 4 ¼ ðY1 þ Y2 þ Y3 þ Y4 þ Ci Þs

ð3:2:7Þ

where Cr1 Cir1 Cir1 þ Cr1 Cr2 Cir2 Y2 ¼ Cir2 þ Cr2 Cl1 Cil1 Y3 ¼ Cil1 þ Cl1 Cl2 Cil2 Y4 ¼ Cil2 þ Cl2 Y1 ¼

The propagation constant will then be given by vﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ !ﬃ u 4 X u Yi þ Ci g ¼ tðR þ sLÞs i¼1

ð3:2:8Þ ð3:2:9Þ ð3:2:10Þ ð3:2:11Þ

ð3:2:12Þ

148

INTERCONNECTION DELAYS

and the characteristic impedance will be given by vﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ u R þ sL Z0 ¼ u u 4 P t s Ci þ Yi

ð3:2:13Þ

i¼1

In the Laplace transform domain, the voltage and current distributions along an interconnection satisfy the following transmission line equations: d2 V ¼ g2 V dz2

ð3:2:14Þ

d2 I ¼ g2 I dz2

ð3:2:15Þ

The most general solutions for the voltage and current along the interconnection length (denoted by the coordinate z) are given by vz ¼ Aegz þ Begz Aegz Begz iz ¼ Z0

ð3:2:16Þ ð3:2:17Þ

where the constants A and B can be determined by employing the known boundary conditions. If the interconnection is driven at the end z ¼ 0 by a source of voltage Vs having an internal impedance Rs , then at this end vz ¼ Vs iRs

ð3:2:18Þ

Furthermore, if the interconnection is terminated by a load ZL at z ¼ ‘, then at this end vz ¼ ZL ð3:2:19Þ iz Substituting conditions (3.2.18) and (3.2.19) in Eqs. (3.2.16) and (3.2.17), the values of A and B can be obtained to be Vs Z0 Rs þ Z0 ½ðZL Z0 Þ=ðZL þ Z0 ÞðRs Z0 Þe2g‘ ZL Z0 2g‘ e B¼A ZL þ Z0

A¼

ð3:2:20Þ ð3:2:21Þ

In order to determine the propagation delays (i.e., the delay time and rise time) for an interconnection, one needs to know how the voltage at the load varies as a function of time in response to a unit step voltage applied at z ¼ 0. In the s space, a unit step voltage source is represented by Vs ¼

1 s

ð3:2:22Þ

TRANSMISSION LINE ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

149

The voltage at the load end (z ¼ ‘) is given by Eq. (3.2.16) to be VðsÞ ¼ Aeg‘ þ Beg‘

ð3:2:23Þ

where the propagation constant g in the s space is given by Eqs. (3.2.5)–(3.2.12) and the constants A and B are given by Eqs. (3.2.20) and (3.2.21), respectively. The time-domain response of the output voltage can be obtained by an inverse Laplace transformation of VðsÞ. Because of the presence of the branch points associated with the propagation constant g, inverse transformation can be obtained by using the concept of Bromwich integrals, that is, 1 vðtÞ ¼ 2pj

Z

VðsÞest ds

ð3:2:24Þ

Br

Using Simpson’s rule, it can be written as vðtÞ

N 1 X VðsÞest s 2pj n¼N

ð3:2:25Þ

Writing the complex frequency in terms of its real and imaginary parts as s ¼ s þ jo

ð3:2:26Þ

s ¼ j o

ð3:2:27Þ

s ¼ s þ jn o

ð3:2:28Þ

we have

and

Therefore vðtÞ

N 1 X Vðs þ jn oÞeðsþjnoÞt o 2p n¼N

ð3:2:29Þ

In principle, any positive s and o that will cause two consecutive terms in the summation in Eq. (3.2.29) to be sufﬁciently close to each other can be used. However, these should be carefully chosen to optimize the speed of convergence. The best values for s and o depend on the time t (in seconds) and can be found to be s ¼ 0:5t and o ¼ 0:05=t. The best choice for N depends on t also. It can be found to range from 500 to 1000 for small t and large t, respectively.

150

INTERCONNECTION DELAYS

3.2.2

The Program PDSIGV

Listing of a computer program called Propagation Delays in the Single-Level Interconnections on the GaAs-based VLSI (PDSIGV) which incorporates the steps given above is given in Appendix 3.1 on the accompanying ftp site. For a given set of interconnection dimensions, that is, interconnection lengths, interconnection widths and interconnection separations, resistivity of the interconnection material, load capacitance, and resistance of the unit step voltage source, the program computes the characteristic impedance and the propagation constant for the interconnection, performs the summation in Eq. (3.2.29), and ﬁnally calculates the normalized voltage at the load as a function of time in any desired time range. The output voltage is normalized in the sense that it is the ratio of the voltage at the load at a given time t to its value at time t ¼ 1. The resistance and inductance of the interconnection line are kept as R ¼ 2 r 104 =m and L ¼ 106 H/m, where r is the resistivity of the interconnection material. The value of R is for 0.5 mm thickness of the interconnection. The values of the self and mutual capacitances for the system of interconnections are determined by using the model developed earlier [34]. The overshoot and ringing observed in the curves below are due to a ﬁnite number of terms included in the approximation expressed by Eq. (3.2.29) used to ﬁnd vðtÞ. 3.2.3

Dependence on Interconnection Parameters

The program PDSIGV can be used to study the dependences of the delay time and rise time on the interconnection dimensions, namely the length and width of the interconnection and the resistivity of the interconnection material. All the results are obtained for load capacitance of 100 fF and with the resistance of the unit step voltage source set to 700 . This corresponds to the interconnection line being driven by a typical GaAs MESFET with gate width equal to 10 mm. Figure 3.2.3 shows the normalized output voltages for interconnection lengths of 100 mm and

FIGURE 3.2.3 Normalized output voltages for interconnection lengths of 100 mm and 1 cm. Insert shows output voltage for interconnection length of 5 cm.

TRANSMISSION LINE ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

FIGURE 3.2.4

151

Dependence of delay time on interconnection length.

1 cm. The inset in this ﬁgure shows that for ‘‘long’’ interconnections no output voltage is expected to be observed for some time. Figure 3.2.4 shows the dependence of delay time on interconnection length while the dependence of rise time on interconnection length is shown in Fig. 3.2.5. These ﬁgures indicate that for interconnection lengths above 100 mm the delay time and rise time increase signiﬁcantly whereas these are almost constant below about 100 mm. As a function of the width of the interconnection, the delay time and rise time are shown in the Figs. 3.2.6 and 3.2.7, respectively. Figure 3.2.8 shows the normalized output voltages for interconnection widths of 1.0 and 0.1 mm. Figures 3.2.6 and 3.2.7 indicate that the propagation delays decrease when the interconnection width is increased from 0.1 to about 1 mm. For interconnection widths above about 1 mm both delay time and rise time increase somewhat. The initial decrease in the transit times below about 1 mm is due to the decreasing line resistance whereas the increase observed above about 1 mm is due to the increasing interconnection capacitances. Figure 3.2.9 shows the normalized output voltages when the interconnection metal is aluminum, WSi2, or polysilicon. These correspond to the interconnection metal resistivities of 3, 30, and 500 m cm, respectively. It shows that, as the resistivity is

FIGURE 3.2.5

Dependence of rise time on interconnection length.

152

INTERCONNECTION DELAYS

FIGURE 3.2.6

FIGURE 3.2.7

Dependence of delay time on interconnection width.

Dependence of rise time on interconnection width.

FIGURE 3.2.8 Normalized output voltages for interconnection widths of 1.0 and 0.1 mm. Insert shows output voltage for interconnection width of 1.0 mm for times less than 1.0 ps.

TRANSMISSION LINE ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

FIGURE 3.2.9 polysilicon.

153

Normalized output voltages for interconnection metals of Al, WSi2, and

FIGURE 3.2.10 Dependences of delay time and rise time on interconnection metal resistivity.

FIGURE 3.2.11 Normalized output voltages for load capacitances of 10 fF and 1 pF.

154

INTERCONNECTION DELAYS

FIGURE 3.2.12 Effect of coupling of interconnection with its neighbors on output voltage.

increased, the time for the output voltage to reach its steady-state value increases as well. The resulting increases in delay time and rise time are shown in Fig. 3.2.10. Figure 3.2.11 shows normalized output voltages for load capacitances of 10 fF and 1 pF. The effect of including the coupling of the interconnection with the neighboring lines in the present model is shown in Fig. 3.2.12. It shows that it takes longer for the output voltage to reach its steady-state value when the coupling is present, as expected.

3.3

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

In this section, a transmission line analysis of signal propagation in multilevel, including the single-, bi-, and trilevel high-density, interconnections on GaAs-based ICs is presented. The model has been utilized to study the dependences of load voltages and delay times on interconnection parameters such as their length, widths, separations, interlevel distances, driving transistor resistance, and load capacitance. 3.3.1

The Model

As shown in Fig. 3.3.1, the interconnection line can be modeled as a transmission line driven by a unit step voltage source having resistance Rs loaded by the capacitance CL and coupled to the neighboring interconnection lines by the mutual capacitances and inductances (not shown in the ﬁgure). The resistance Rs is determined by the dimensions of the driving transistor and the capacitance CL is determined by the parasitic capacitances of the transistor loading the interconnection line. For the interconnection lines printed on or embedded in the semi-insulating

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

155

FIGURE 3.3.1 Interconnection driven by unit step voltage source Vs of resistance Rs and terminated by load capacitance CL . Terminal endings on neighboring interconnections also shown. Interconnection capacitances and capacitive and inductive couplings between interconnections not shown.

GaAs substrate, quasi-TEM is the dominant mode of wave propagation and the transmission line equations are given by @ @ Vðx; tÞ ¼ R þ L Iðx; tÞ ð3:3:1Þ @x @t @ @ Iðx; tÞ ¼ G þ C Vðx; tÞ ð3:3:2Þ @x @t where L and C are the inductance and capacitance matrices per unit length of the interconnections, R is determined by the resistance per unit length of the interconnections, and G is the conductance matrix determined by the conductivity of the substrate. For the semi-insulating GaAs substrate, G can be neglected. The matrices L and C can be determined by the network analog method developed earlier in Chapter 2. In the s domain, Eqs. (3.3.1) and (3.3.2) can be written as d Vðx; sÞ ¼ ½R þ sLIðx; sÞ dx d Iðx; sÞ ¼ ½G þ sCVðx; sÞ dx

ð3:3:3Þ ð3:3:4Þ

Deﬁning Z ¼ R þ sL Y ¼ G þ sC Eqs. (3.3.3) and (3.3.4) can be solved in the s domain to yield pﬃﬃﬃﬃ pﬃﬃﬃﬃ Vðx; sÞ ¼ e ZY ðxÞ Vi ðsÞ þ e ZY ð‘xÞ Vr ðsÞ rﬃﬃﬃﬃ pﬃﬃﬃﬃ Y pﬃﬃﬃﬃ Iðx; sÞ ¼ ½e ZY ðxÞ Vi ðsÞ e ZY ð‘xÞ Vr ðsÞ Z

ð3:3:5Þ ð3:3:6Þ

156

INTERCONNECTION DELAYS

In Eqs. (3.3.5) and (3.3.6), ‘ is the total length of the transmission line, Vi ðsÞ is the voltage vector of the incident wave at x ¼ 0, and Vr ðsÞ is that of the reﬂected wave at x ¼ ‘. At the end points, x ¼ 0 and x ¼ ‘, Eqs. (3.3.5) and (3.3.6) yield pﬃﬃﬃﬃ Vð0; sÞ ¼ Vi ðsÞ þ e ZY ‘ Vr ðsÞ rﬃﬃﬃﬃ pﬃﬃﬃﬃ Y Ið0; sÞ ¼ ½Vi ðsÞ e ZY ‘ Vr ðsÞ Z pﬃﬃﬃﬃ Vð‘; sÞ ¼ e ZY ‘ Vi ðsÞ þ Vr ðsÞ rﬃﬃﬃﬃ Y pﬃﬃﬃﬃ Ið‘; sÞ ¼ ½e ZY ‘ Vi ðsÞ Vr ðsÞ Z

ð3:3:7Þ ð3:3:8Þ ð3:3:9Þ ð3:3:10Þ

Incorporating the boundary conditions determined by the lumped circuit elements connected to the interconnection line, that is, Vð0; sÞ ¼ Vs ðsÞ RIð0; sÞ Vð‘; sÞ ¼

1 Ið‘; sÞ sCL

ð3:3:11Þ ð3:3:12Þ

we have rﬃﬃﬃﬃ pﬃﬃﬃﬃ Y Vi ðsÞ þ e Vr ðsÞ ¼ ðRs Þ ½Vi ðsÞ e ZY ‘ Vr ðsÞ þ Vs ðsÞ Z rﬃﬃﬃﬃ pﬃﬃﬃﬃ 1 Y pﬃﬃﬃﬃ ZY ‘ Vi ðsÞ þ Vr ðsÞ ¼ ½e ZY ‘ Vi ðsÞ Vr ðsÞ e sCL Z pﬃﬃﬃﬃ ð ZY Þ‘

ð3:3:13Þ ð3:3:14Þ

which can be solved to yield, for Vi ðsÞ and Vr ðsÞ, 8 " " rﬃﬃﬃﬃ# rﬃﬃﬃﬃ#1 " rﬃﬃﬃﬃ# < ﬃﬃﬃﬃ Y pZY 1 Y 1 Y 1þ Vr ðsÞ ¼ Vs ðsÞ 1 þ Rs ½e ‘ 1 : Z sCL Z sCL Z )1 rﬃﬃﬃﬃ# pﬃﬃﬃﬃ Y ZY ‘ ½1=e þ 1 Rs Z "

" Vi ðsÞ ¼ e

pﬃﬃﬃﬃ ZY ‘

1 sCL

#1 rﬃﬃﬃﬃ Y pﬃﬃﬃﬃ 1 pﬃﬃﬃﬃ ZY ‘ ZY ‘ Vr ðsÞ 1þ e e Z sCL

ð3:3:15Þ

ð3:3:16Þ

The values for Vi ðsÞ and Vr ðsÞ can be substituted in Eqs. (3.3.7)–(3.3.10) to obtain the expressions for current and voltage at x ¼ 0 and x ¼ ‘ in the s domain. The load voltage is the element of Vð‘; sÞ that corresponds to the line on which the voltage source is applied.

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

157

In principle, the time-domain response can be obtained by inverse Laplace transformation or by Fourier transformation. However, Fourier transformation results in errors due to a ﬁnite number of terms included in the summation. Therefore, the inverse Laplace transformation technique is preferred. If FðsÞ denotes the Laplace transform of f ðtÞ, then

FðsÞ ¼

Z1

f ðtÞest dt

ð3:3:17Þ

0

It can be shown [21] that, for t on the interval (0; 2T), f ðtÞ ¼ hðtÞ EðtÞ

ð3:3:18Þ

where hðtÞ is given by 1 hðtÞ ¼ T

! 1 FðaÞ X kpt kpt kpt kpt cos Im F a þ sin Re F a þ þ 2 T T T T k¼1 ð3:3:19Þ

and the error EðtÞ is bounded by EðtÞ M

eat

e2TðaaÞ 1

ð3:3:20Þ

where 1=T is the frequency step, M is a constant, and a is related to f ðtÞ such that f ðtÞ is an exponential of order a (i.e., jf ðtÞj Ceat ). When 2Tða a) is large enough and we want our precision to be e, then a can be chosen to be [21] a¼a

lnðeÞ 2T

ð3:3:21Þ

Choosing a suitable value of T for the desired accuracy depends on the time range of interest (e.g., 0 to tmax ) and the computation time. When t is much smaller than 2T, then the approximation of f ðtÞ by Eq. (3.3.19) converges very slowly because the frequency step determined by 1=T is too small and we need to include many terms for the summation to converge. On the other hand, if t is too close to 2T, then the error due to the term EðtÞ in Eq. (3.3.18) becomes large, as can be seen from Eq. (3.3.20). A good choice for T lies in the range (0:8tmax ; 1:2tmax ). Numerical computations show that if we apply inverse Laplace transformation directly, then the summation converges very slowly for small values of t. This is because the frequency step determined by 1=T is too small for small t. To solve this problem, we can divide the time range [0; tmax ] into several time ranges [0; pk tmax ],

158

INTERCONNECTION DELAYS

(pk tmax , pk1 tmax ],. . .,(ptmax ,tmax ] and choose a different value of T for each time range such that T is not too large and the summation in Eq. (3.3.19) converges faster. The value of p can be determined by a compromise between the desired accuracy and the computation time and is chosen to be 0.8. The summation in Eq. (3.3.19) usually converges very slowly; it takes more than 5000 terms to achieve an accuracy of four signiﬁcant digits. To overcome this problem, we can use the Wynn algorithm [36, 37] to accelerate the summation. The algorithm can be described as follows: For a summation series S deﬁned as S¼

m X

m ¼ 1; 2; 3; . . .

an

ð3:3:22Þ

n¼1

we deﬁne a 2D array as m em pþ1 ¼ ep1 þ

1 em1 em p p

p ¼ 1; 2; 3; . . .

ð3:3:23Þ

with em 0 ¼0

ð3:3:24Þ

em 1

ð3:3:25Þ

¼ Sm

m m m In principle, em 3 , e5 , e7 , e9 , . . ., will be better approximations for the summation Sm in Eq. (3.3.22). From numerical experiments it can be found that em 9 is the best choice for the present problem because higher order transformations result in rounding errors.

3.3.2

Numerical Simulation Results

The computer program DCMPVI based on the inverse Laplace transformation technique using the Wynn algorithm and the improved time range selection described above and written in FORTRAN is provided as Appendix 4.1 on the accompanying ftp site. The program has been used to study the dependences of the load voltage and delay time for interconnections in the conﬁgurations shown in Figs. 3.3.2a–c. One of the parameters is varied in a speciﬁc range while the others are kept ﬁxed at their typical values. Typical values of the various parameters are chosen to be interconnection length ‘ ¼ 1000 mm, interconnection width W ¼ 1 mm, interconnection separation S ¼ 1 mm, interconnection metal resistivity r ¼ 3 m cm, interlevel distances T12 and T23 equal to 2 mm, GaAs substrate thickness T ¼ 200 mm, driving transistor output resistance or source resistance Rs ¼ 100 , and loading transistor input capacitance or load capacitance CL ¼ 100 fF. The thickness of each interconnection line is kept equal to 0.5 W. In the following, the single-level interconnection conﬁguration shown in Fig. 3.3.2a is assumed unless otherwise speciﬁed and the source is applied to one end of the second interconnection on the ﬁrst level. Further, as in the literature [20], the delay time is deﬁned as the time taken by the output voltage to reach 50% of its steady-state value.

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

159

FIGURE 3.3.2 Schematic of (a) three single-level, (b) six bilevel, and (c) six trilevel interconnection conﬁgurations.

Variations of load voltages with time in the range 0–50 ps for several values of interconnection lengths are shown in Fig. 3.3.3 while Fig. 3.3.4 shows the dependence of delay time on interconnection lengths in the range 20–1000 mm. Figure 3.3.4 shows that the delay time increases almost linearly for interconnection lengths above about 100 mm. For lengths below about 100 mm, the delay is caused

160

INTERCONNECTION DELAYS

FIGURE 3.3.3 Load voltage waveforms in range 0–50 ps for several interconnection lengths in single-level conﬁguration.

FIGURE 3.3.4 Dependence of propagation delay time on interconnection lengths in singlelevel conﬁguration.

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

161

FIGURE 3.3.5 Load voltage waveforms in range 0–50 ps for several interconnection widths in single-level conﬁguration.

mainly by the RC delay of the source resistance and load capacitance. For several values of interconnection widths, load voltage waveforms in the time range 0–50 ps are shown in Fig. 3.3.5 and the dependence of delay time on interconnection widths in the range 0.5–5 mm is shown in Fig. 3.3.6. Figure 3.3.6 shows that the delay time becomes a minimum when the interconnection widths are about 2 mm each. The increase in delay time for widths below about 2 mm is due to the increasing line resistance due to decreasing cross-sectional area whereas the increase in delay time for widths above about 2 mm is due to the increasing ground and coupling capacitances of the interconnection lines. For four different values of interconnection separation, load voltage waveforms in the range 0–50 ps are shown in Fig. 3.3.7 and the dependence of delay time on interconnection separations in the range 0.5– 5 mm is shown in Fig. 3.3.8. Figure 3.3.8 shows that the delay time decreases as the separations are increased. This is because the coupling capacitances decrease as the distances between the neighboring interconnection lines are increased. Load voltage waveforms in the time range 0–500 ps for several values of interconnection metal resistivity are shown in Fig. 3.3.9 and the dependence of delay time on resistivities in the range 0.1–1,000 m cm is shown in Fig. 3.3.10. This ﬁgure shows that for resistivities above about 10 m cm the delay time increases signiﬁcantly. It should be noted that, besides aluminum, WSi2 and poly-Si have also

162

INTERCONNECTION DELAYS

FIGURE 3.3.6 Dependence of propagation delay time on interconnection widths in singlelevel conﬁguration.

FIGURE 3.3.7 Load voltage waveforms in range 0–50 ps for several interconnection separations in single-level conﬁguration.

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

163

FIGURE 3.3.8 Dependence of propagation delay time on interconnection separation in single-level conﬁguration.

FIGURE 3.3.9 Load voltage waveforms in range 0–500 ps for several interconnection resistivities for single-level interconnections.

164

INTERCONNECTION DELAYS

FIGURE 3.3.10 Dependence of propagation delay time on interconnection resistivity in single-level conﬁguration.

been used as interconnection metals with resistivities of about 30 and 500 m cm, respectively. For several values of source resistance, load voltage waveforms in the time range 0–200 ps are shown in Fig. 3.3.11. On a realistic IC chip, source resistance corresponds to the output resistance of the transistor driving the interconnection. For a 100-mm-wide GaAs MESFET with 1 mm gate length, this resistance is approximately 700 . Dependence of delay time on source resistance in the range 0.1–1000 is shown in Fig. 3.3.12. It shows that for source resistance above about 10 the delay time increases considerably. Figure 3.3.13 shows load voltage waveforms in the range 0–200 ps for several values of load capacitance. In practice, load capacitance refers to the input capacitance of the loading transistor. For a typical GaAs MESFET of 1 mm gate length and 100 mm width, this is approximately 100 fF. Dependence of delay time on load capacitance in the range 1–1000 fF is shown in Fig. 3.3.14. It shows that for load capacitances above about 10 fF the delay time increases signiﬁcantly. Load voltage waveforms for different numbers of interconnection lines in the single-level conﬁguration are shown in Fig. 3.3.15. Three interconnections correspond to one neighbor on each side of the driven line whereas ﬁve interconnections correspond to two neighboring lines on each side of the driven line. This ﬁgure shows that the effect of the second neighbors on delay time is much smaller than that of the ﬁrst neighbors. For the bilevel interconnections shown in Fig. 3.3.2b, load voltage waveforms in the range 0–200 ps resulting from application of the driving source to different interconnection lines are shown in Fig. 3.3.16. This

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

165

FIGURE 3.3.11 Load voltage waveforms in range 0–200 ps for several source resistances in single-level conﬁguration.

FIGURE 3.3.12 Dependence of propagation delay time on source resistance in single-level conﬁguration.

166

INTERCONNECTION DELAYS

FIGURE 3.3.13 Load voltage waveforms in range 0–200 ps for several load capacitances in single-level conﬁguration.

FIGURE 3.3.14 Dependence of propagation delay time on load capacitance in single-level conﬁguration.

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

167

FIGURE 3.3.15 Load voltage waveforms in range 0–200 ps for different number of interconnections in single-level conﬁguration.

FIGURE 3.3.16 Load voltage waveforms in range 0–200 ps for driving source applied to different interconnections in bilevel conﬁguration.

168

INTERCONNECTION DELAYS

FIGURE 3.3.17 Load voltage waveforms in range 0–200 ps for driving source applied to different interconnections in trilevel conﬁguration.

ﬁgure shows that the signal delays are longer for the interconnection lines embedded in the substrate compared to those printed on the substrate. Similar conclusions can be drawn from Fig. 3.3.17, which shows load voltage waveforms when the source is applied to different interconnection lines in the trilevel conﬁguration shown in Fig. 3.3.2c.

3.4

ANALYSIS OF CROSSING INTERCONNECTIONS

A schematic of the bilevel crossing interconnections and the substrate is shown in Fig. 3.4.1. As shown in the previous section, the interconnection lines which run parallel to each other can be studied by using the transmission line equations. However, when the interconnections cross each other, the transmission line approximation is no longer valid. This is because, in this case, the coupling of the lines is no longer uniform along the entire length of the interconnection but rather is localized to the crossing areas. In this section, ﬁrst, the effect of several crossing lines embedded in the substrate on the propagation delay in the main (driven) line printed on the top plane will be studied using a simpliﬁed model. Only the capacitive couplings will be considered in this analysis. Then, a more complete model of

ANALYSIS OF CROSSING INTERCONNECTIONS

FIGURE 3.4.1

169

Schematic of layout of bilevel crossing interconnections and substrate.

the crossing interconnections having several parallel interconnections on the top plane and including the capacitive as well as inductive couplings between the interconnections will be considered. 3.4.1

Simpliﬁed Analysis of Crossing Interconnections

A schematic of the crossing interconnections analyzed in this section is shown in Fig. 3.4.2. A driving source is applied only to the main line on the top plane and the crossing lines in the second plane are not energized. One way of analyzing this interconnection conﬁguration is to divide it into three sections called the transmission line section, the crossing section, and the load section. The equivalent circuit used for the interconnections is shown in Fig. 3.4.3 with the following deﬁnitions of the elements used: Vs ¼ voltage source Rs ¼ source resistance LB ¼ self-inductance of portion of driven line between two consecutive crossing lines

FIGURE 3.4.2

Schematic of bilevel crossing interconnections analyzed in this section.

170

INTERCONNECTION DELAYS

FIGURE 3.4.3 Equivalent circuit of bilevel crossing interconnections including capacitive couplings. Inductive couplings not included.

RB Cc Rcl Rcr Lcl Lcr CL Rr Lr Cr

¼ resistance of portion of driven line between two consecutive crossing lines ¼ coupling capacitance between main line and crossing line ¼ line resistance of crossing line on left side of main line ¼ line resistance of crossing line on right side of main line ¼ self-inductance of crossing line on left side of main line ¼ self-inductance of crossing line on right side of main line ¼ load capacitance ¼ resistance of portion of main line after crossing lines ¼ self-inductance of portion of main line after crossing lines ¼ ground capacitance of portion of main line after crossing lines (load section portion)

3.4.1.1

Source Section

A schematic of the source-side transmission line section including its source and load is shown in Fig. 3.4.4. In the ﬁgure ZTX represents the load driven by this section and includes the loading effects of the crossing interconnections, the load section, and the load capacitance CL ; Vs is the driving source voltage and Rs is the source resistance. In practice, the source will be the output stage of a driving transistor or gate. For the quasi-TEM wave propagation, the transmission line equations are @ @ Vðx; tÞ ¼ R þ L Iðx; tÞ ð3:4:1Þ @x @t @ @ Iðx; tÞ ¼ G þ C Vðx; tÞ ð3:4:2Þ @t @t

ANALYSIS OF CROSSING INTERCONNECTIONS

FIGURE 3.4.4

171

Schematic of source section.

where L is the inductance per unit length, C is the capacitance per unit length, R is the resistance per unit length, and G is the conductance per unit length of the interconnection line. Conductance G is determined by the conductivity of the substrate. For semi-insulating substrates (e.g., GaAs), G can be considered negligibly small. In the complex-frequency (s) domain, Eqs. (3.4.1) and (3.4.2) can be written as @ Vðx; sÞ ¼ ½R þ sLIðx; sÞ @x @ Iðx; sÞ ¼ ½G þ sCVðx; sÞ @x

ð3:4:3Þ ð3:4:4Þ

Deﬁning Z ¼ R þ sL

ð3:4:5Þ

Y ¼ G þ sC

ð3:4:6Þ

the transmission line equations can be solved for V and I to yield pﬃﬃﬃﬃ pﬃﬃﬃﬃ Vðx; sÞ ¼ e ZY x Vi ðsÞ þ e ZY ð‘xÞ Vr ðsÞ rﬃﬃﬃﬃ pﬃﬃﬃﬃ Y pﬃﬃﬃﬃ Iðx; sÞ ¼ ½e ZY x Vi ðsÞ e ZY ð‘xÞ Vr ðsÞ Z

ð3:4:7Þ ð3:4:8Þ

where ‘ is the total length of the source section transmission line, Vi ðsÞ is the Laplace transform of the incident voltage waveform, and Vr ðsÞ is that of the reﬂected wave at x ¼ ‘. At the boundary points, that is, at x ¼ 0 and x ¼ ‘, we get pﬃﬃﬃﬃ ð3:4:9Þ Vð0; sÞ ¼ Vi ðsÞ þ e ZY ‘ Vr ðsÞ rﬃﬃﬃﬃ pﬃﬃﬃﬃ Y Ið0; sÞ ¼ ð3:4:10Þ ½Vi ðsÞ e ZY ‘ Vr ðsÞ Z pﬃﬃﬃﬃ Vð‘; sÞ ¼ e ZY ‘ Vi ðsÞ þ Vr ðsÞ ð3:4:11Þ rﬃﬃﬃﬃ Y pﬃﬃﬃﬃ ð3:4:12Þ Ið‘; sÞ ¼ ½e ZY ‘ Vi ðsÞ Vr ðsÞ Z

172

INTERCONNECTION DELAYS

Boundary conditions will be used at the source and load ends, that is, Vð0; sÞ ¼ Vs ðsÞ Rs Ið0; sÞ

ð3:4:13Þ

Vð‘; sÞ ¼ ZTX Ið‘; sÞ

ð3:4:14Þ

where ZTX ¼ Zp1 k ZX þ RB

ð3:4:15Þ

1 est s

ð3:4:16Þ

Vs ðsÞ ¼

where Zp1 and ZX are deﬁned in the crossing section next. Equations (3.4.9)–(3.4.14) can be solved to yield, for Vi ðsÞ and Vr ðsÞ, pﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ Vs ðsÞe ZY ‘ ½1 ZTX Y=Z pﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ Vr ðsÞ ¼ ½1 Rs Y=Z ½1 ZTX Y=Z e2 ZY ‘ ½1 þ Rs Y=Z ½1 þ ZTX Y=Z ð3:4:17Þ Vi ðsÞ ¼

1þ ½1 ZTX

pﬃﬃﬃﬃ ZTX e ZY ‘ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃ Y=Z e ZY ‘

Vr ðsÞ

ð3:4:18Þ

Using the expressions for Vi ðsÞ and Vr ðsÞ from Eqs. (3.4.17) and (3.4.18), we can get the expressions for voltage and current in the s domain at the end of the transmission line section, that is, at x ¼ ‘, from Eqs. (3.4.11) and (3.4.12). The current Ið‘; sÞ is indeed the input current for the next section, that is, the crossing section. 3.4.1.2 Crossing Section This is the section where the driven line on the top plane and the second-level interconnections embedded in the substrate cross each other. This section is driven by the output of the transmission line section, and the output of this section drives the next section, that is, the load section. The driven line is coupled to the crossing lines by the coupling capacitances, which depend on the crossing area (which in turn depends on the line widths and the crossing angle), the interlevel separation, and the substrate’s dielectric constant. It is assumed that all the interconnection lines are of the same width, thickness, and material. The algorithm can be easily modiﬁed for different situations. The schematic of a typical crossing section is shown in Fig. 3.4.5. Its impedance as seen by the current ﬂowing in the driven line is given by 1 1 ð3:4:19Þ þ ðRcl þ sLcl þ Rs Þ k Rcr þ sLcr þ Zx ¼ sCc sCL

ANALYSIS OF CROSSING INTERCONNECTIONS

FIGURE 3.4.5

173

Schematic of crossing section involving ith crossing line.

If ITX denotes the current ﬂowing from the transmission line section in to the crossing section, then the currents Ii ﬂowing in the driven line after ‘‘seeing’’ the ith crossing line are given by I1 ¼ ITX

Zx Zx þ Zp1

I2 ¼ I1

Zx Zx þ Zp2

and so on until In ¼ In1

Zx 0 Zx þ ZL

ð3:4:20Þ

0

where ZL is the total impedance of the load section. Here, In represents the current ﬂowing in to the load section. The partial loads Zpi used in Eqs. (3.4.20) are given by Zp1 ¼ Zp2 k Zx þ ZB where ZB ¼ RB þ sLB

Zp2 ¼ Zp3 k Zx þ ZB

and so on, until Zpðn2Þ ¼ Zpðn1Þ k Zx þ ZB Zpðn1Þ ¼ Zpn k Zx þ ZB Zpn

1 1 sLr þ ¼ Z L ¼ Rr þ sCr sCL 0

ð3:4:21Þ

174

INTERCONNECTION DELAYS

FIGURE 3.4.6

Schematic of load section.

3.4.1.3 Load Section The load section refers to the portion of the driven line after the crossing section and includes the load CL driven by the line. Its schematic representation is shown in Fig. 3.4.6. This section can also be modeled as a transmission line driven by a source voltage given by Vs ðsÞ ¼ ½In Iðn1Þ Zx

ð3:4:22Þ

where n is the number of crossing lines. Proceeding as in the transmission line section, it can be easily shown that the voltage across the load will now be given by rﬃﬃﬃﬃ 0 Y pﬃﬃﬃﬃ 1 ½e ZY ‘ Vi ðsÞ Vr ðsÞ VL ðsÞ ¼ Z sCL

ð3:4:23Þ

where pﬃﬃﬃﬃ 0 pﬃﬃﬃﬃﬃﬃﬃﬃﬃ Vs ðsÞe ZY ‘ ½1 ZTX Y=Z pﬃﬃﬃﬃ 0 pﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ Vr ðsÞ ¼ ½1 ZTX Y=Z e2 ZY ‘ ½1 þ ZTX Y=Z pﬃﬃﬃﬃ 0 1 þ ZTX e ZY ‘ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃ 0 Vr ðsÞ Vi ðsÞ ¼ ½1 ZTX Y=Z e ZY ‘

ð3:4:24Þ

ð3:4:25Þ

and ‘0 is the length of the load section transmission line. The load voltage in the time domain can then be obtained by an inverse Laplace transformation of the expression in Eq. (3.4.23). 3.4.2

Comprehensive Analysis of Crossing Interconnections

Now we will note the modiﬁcations required to extend the above analysis by adding two neighboring interconnections on each side of the driven line on the top plane.

ANALYSIS OF CROSSING INTERCONNECTIONS

175

FIGURE 3.4.7 Layout of bilevel crossing interconnections including line endings for ﬁrstlevel interconnections. Each crossing line also terminated by source resistance (Rs ) on one side and load capacitance (CL ) on other side (not shown).

The resulting layout of the interconnection lines including the driving step source, source resistances, and capacitive loads is shown in Fig. 3.4.7. In this analysis, the inductive couplings among the interconnections on the top plane and those between the two levels will also be included. Once again, the transmission line model cannot be applied to the whole problem and therefore we can again divide it into three sections called the source section, crossing section, and load section. The source section along with its source and its load is shown in Fig. 3.4.8, where Vs is the driving source voltage and Rs is the source resistance. The load of this section includes the effects of the crossing section, the load section, and the load capacitance on the interconnection line. As shown earlier, the effects of the two

FIGURE 3.4.8

Schematic of source section.

176

INTERCONNECTION DELAYS

neighboring parallel interconnection lines on each side of the driven line can be simulated by additional capacitances parallel to the ground capacitance of the driven line resulting in an additional capacitive impedance ZC;coup and the inductive effects can be accounted for by an additional inductive impedance ZL;coup in series with the line. The value of ZC;coup is given by the expression 1 1 1 1 1 ¼ þ þ þ ZC;coup Zcl1 Zcl2 Zcr1 Zcr2 where Cil1 þ Cl1 sCl1 Cil1 Cir1 þ Cr1 ¼ sCr1 Cir1

Cil2 þ Cl2 sCl2 Cil2 Cir2 þ Cr2 ¼ sCr2 Cir2

Zcl1 ¼

Zcl2 ¼

Zcr1

Zcr2

where Cil1 , Cil2 , Cir1 , and Cir2 are the coupling capacitances between the driven line and the ﬁrst and second neighboring interconnections on its left and right and Cl1 , Cl2 , Cr1 , and Cr2 are the ground capacitances of the ﬁrst and second neighbors on the left and right of the driven interconnection. The value of ZL;coup is given by the expression ZL;coup ¼

2 2 2 2 s2 ðMr1 þ Mr2 þ Ml1 þ Ml2 Zs

where Mr1 , Mr2 , Ml1 , and Ml2 are the mutual inductances between the driven lines and the two neighboring interconnections on its right and left and Zs is the series impedance of each of the neighboring lines. Then, the transmission line equations of the source section in Section 3.4.1 can be modiﬁed by replacing its series impedance by Z ¼ R þ sL þ ZL;coup where R and L are the resistance and self-inductance of the driven line, and by replacing the parallel admittance of the transmission line by Y ¼ sC þ

1 ZC;coup

where C is the ground capacitance of the driven line. It is understood that all quantities are per unit lengths of the respective lines. The load on the transmission line is given by Tload . With these modiﬁcations, the output voltage and current from the source section can be determined as in Section 3.4.1. The output voltage from the source section is the input signal for the next section, that is, the crossing section. An equivalent circuit of one section of the crossing section incorporating the effects of the ith crossing line is shown in Fig. 3.4.9. The driven line is coupled to the

ANALYSIS OF CROSSING INTERCONNECTIONS

FIGURE 3.4.9

177

Schematic of crossing section.

crossing line by the coupling capacitance, which in turn depends on the line widths, interline separations, interlevel separation, and dielectric constant of the substrate. As mentioned earlier, this stage cannot be expressed in terms of the transmission line equations because the coupling between the driven line and the crossing lines is not uniform along the length of the driven line. The load section is shown in Fig. 3.4.10. As before, this is the last section of the driven line and includes the portion of the driven line which is after the crossing section. This section can again be represented as a transmission line but now using the coupling and other parameters used in the source section. The output from this transmission line drives the load represented by the capacitance CL resulting in the load impedance ZL ¼

1 sCL

FIGURE 3.4.10 Schematic of load section.

178

INTERCONNECTION DELAYS

The boundary conditions for the load section are given by Vð0; sÞ ¼ Vs ðsÞ Vð‘0 ; sÞ ¼ ZL Ið‘0 ; sÞ where Vs ðsÞ is the output voltage of the crossing section and ‘0 is the length of the load section. Using these boundary conditions, the expressions for the incident and reﬂected voltages will be given by 0 Z0 þ ZL Vs ðsÞ Vr ðsÞ ¼ g‘0 Vi ðsÞ ¼ Vr ðsÞeg‘ 0 Z0 ZL e þ eg‘ ½ðZ0 þ ZL Þ=ðZ0 ZL Þ The load current is then given by 0

eg‘ Vi ðsÞ Vr ðsÞ IL ¼ Ið‘ ; sÞ ¼ Z0 0

The current Ið‘0 ; sÞ from the transmission line charges the load capacitance CL and we get the load voltage VL in the s domain as VL ðsÞ ¼ Ið‘0 ; sÞZL The load voltage in the time domain can then be obtained by an inverse Laplace transformation of VL ðsÞ. 3.4.3

The Program SPBIGV

To simulate the propagation delays in the bilevel crossing interconnection on the GaAs substrate as shown in Fig. 3.4.7, the computer program SPBIGV is presented in Appendix 4.2 on the accompanying ftp site. It incorporates the steps outlined above to ﬁnd the load voltages in the s domain and then uses the Pade´ approximation to carry out the inverse Laplace transformation. The program assumes that the lengths of the source section and the load section are equal, all interconnections are made of the same material and are of the same dimensions. The program also assumes that the separations between the neighboring parallel lines on the top level as well as on the second level are the same and that the crossing interconnection lines are perpendicular to those on the ﬁrst level. 3.4.4

Simulation Results Using SPBIGV

In the results illustrated in this section obtained using SPBIGV, one of the parameters is varied in a speciﬁc range while the other parameters are kept ﬁxed at their typical values, which are selected to be the following: interconnection length (IL) 100 mm each, interconnection widths (IW) 1.0 mm each, interconnection thickness (Th) 0.5 mm each, interconnection separation (IS) 1.0 mm each, interconnection material resistivity 3.0 m cm for aluminum, interlevel distance

ANALYSIS OF CROSSING INTERCONNECTIONS

179

FIGURE 3.4.11 Load voltage waveforms in time range 0–150 ps for several values of interconnection lengths.

(ID) 2.0 mm, substrate thickness 200.0 mm, driving source resistance (RS) 100 , and load capacitance (CL) 100 fF. In addition, the number of crossing lines is 16. Load voltage waveforms for several values of interconnection length in the time range 0–150 ps are shown in Fig. 3.4.11. It shows that longer lines take a longer time to transmit the energy from the input source to the output load, as expected. The dependences of delay time and rise time as functions of interconnection length in the range 50–5000 mm are shown in Fig. 3.4.12. For two values of interconnection width, load voltage waveforms in the time range 0–150 ps are shown in Fig. 3.4.13. Figure 3.4.14 shows the dependences of delay time and rise time as functions of interconnection widths in the range 0.1–4 mm. These ﬁgures suggest that the propagation delays are minimum when the interconnection widths are nearly 1 mm each. This can be understood qualitatively by considering the two opposing effects of increasing the interconnection widths on the propagation delays, that is, decreasing interconnection resistance and increasing interconnection capacitances. For two values of interconnection thickness while keeping the other parameters ﬁxed, load voltage waveforms in the time range 0–100 ps are shown in Fig. 3.4.15 while Fig. 3.4.16 shows the dependences of delay time and rise time on interconnection thicknesses in the range 0.1–10 mm. For two values of interconnection separation while keeping the other parameters ﬁxed, load voltage waveforms in the time range 0–150 ps are shown in Fig. 3.4.17 while Fig. 3.4.18 shows the dependences of delay time the rise time on interconnection separations in the range 1–6 mm.

180

INTERCONNECTION DELAYS

FIGURE 3.4.12 Dependences of delay time and rise time on interconnection lengths.

FIGURE 3.4.13 Load voltage waveforms in time range 0–150 ps for two values of interconnection widths.

ANALYSIS OF CROSSING INTERCONNECTIONS

FIGURE 3.4.14

181

Dependences of delay time and rise time on interconnection widths.

FIGURE 3.4.15 Load voltage waveforms in time range 0–100 ps for two values of interconnection thicknesses.

182

INTERCONNECTION DELAYS

FIGURE 3.4.16 Dependences of delay time and rise time on interconnection thicknesses.

FIGURE 3.4.17 Load voltage waveforms in time range 0–150 ps for two values of interconnection separations.

ANALYSIS OF CROSSING INTERCONNECTIONS

183

FIGURE 3.4.18 Dependences of delay time and rise time on interconnection separations.

For several values of interconnection material resistivity, load voltage waveforms in the time range 0–150 ps are shown in Fig. 3.4.19 while the dependences of delay time and rise time on resistivities in the range 1–500 m cm are shown in Fig. 3.4.20. For several values of driving source resistance, load voltage waveforms in the time range 0–150 ps are shown in Fig. 3.4.21 while the dependences of delay time and rise time on source resistance in the range 10–1000 are shown in Fig. 3.4.22. Load voltage waveforms for several values of load capacitance in the time range 0–150 ps are shown in Fig. 3.4.23 while the dependences of delay time and rise time on load capacitance in the range 10–2000 fF are shown in Fig. 3.4.24. As expected, the propagation delays in the driving interconnection increase with increases in material resistivity, load capacitance, or source resistance and vice versa. Figure 3.4.25 shows the dependences of delay time and rise time on the thickness of the GaAs substrate in the range 10–500 mm. For several values of interlevel distance, that is, the distance between the top level containing the driven interconnection and the second level containing the crossing interconnections, load voltage waveforms in the time range 0–150 ps are shown in Fig. 3.4.26 while the dependences of delay time and rise time on interlevel distance in the range 0.1–10 mm are shown in Fig. 3.4.27. As expected, the effect of crossing lines on the propagation delays in the driven line decreases as the distance between the two levels increases. The relative effects of coupling of the driven interconnection with its two neighbors on each side on the top plane and with the crossing lines in the second level are shown by the load voltage waveforms in Fig. 3.4.28. For several values of the number of crossing lines, load voltage waveforms in the time range 0–150 ps are shown in

184

INTERCONNECTION DELAYS

FIGURE 3.4.19 Load voltage waveforms in time range 0–150 ps for several values of interconnection material resistivities.

FIGURE 3.4.20 Dependences of delay time and rise time on interconnection material resistivities.

ANALYSIS OF CROSSING INTERCONNECTIONS

185

FIGURE 3.4.21 Load voltage waveforms in time range 0–150 ps for several values of source resistance.

FIGURE 3.4.22 Dependences of delay time and rise time on source resistance.

186

INTERCONNECTION DELAYS

FIGURE 3.4.23 Load voltage waveforms in time range 0–150 ps for several values of load capacitance.

FIGURE 3.4.24 Dependences of delay time and rise time on load capacitance.

ANALYSIS OF CROSSING INTERCONNECTIONS

187

FIGURE 3.4.25 Dependences of delay time and rise time on substrate thickness.

FIGURE 3.4.26 Load voltage waveforms in time range 0–150 ps for several values of interlevel distance.

188

INTERCONNECTION DELAYS

FIGURE 3.4.27 Dependences of delay time and rise time on interlevel separation.

FIGURE 3.4.28 Effects of coupling of driven interconnection with its parallel and crossing neighbors on its load voltage waveform: case I, without coupling; case II, parallel lines only (single level); case III, parallel and crossing lines.

ANALYSIS OF CROSSING INTERCONNECTIONS

189

FIGURE 3.4.29 Load voltage waveforms in time range 0–150 ps for several values of number of crossing lines.

FIGURE 3.4.30 Dependences of delay time and rise time on number of crossing interconnection lines.

190

INTERCONNECTION DELAYS

Fig. 3.4.29 while the dependences of delay time and rise time on number of crossing lines in the range 1–80 are shown in Fig. 3.4.30. This ﬁgure suggests that the greater the number of crossing lines, the greater will be their effect on the propagation delays in the driven interconnection, as expected.

3.5

PARALLEL INTERCONNECTIONS MODELED AS MULTIPLE COUPLED MICROSTRIPS

In the literature, multiple coupled distributed parameter systems, including coupled transmission lines, have been analyzed in detail. For example, the normal-mode propagation constants, impedances, and eigenvectors for coupled n-line structures are derived in matrix form [38–45], and these properties are available in explicit closed-form for two-, three-, and four-line systems [45–48]. The coupled line equations can also be used to model the propagation characteristics of interconnections in the high-speed digital circuits. Such a model [13] is presented in this section. 3.5.1

The Model

A schematic of a general multiple coupled line structure is shown in Fig. 3.5.1. The voltages and currents on a lossless n-line system are described by the transmission line equations @ @ v ¼ ½L i @z @t @ @ i ¼ ½C v @z @t

ð3:5:1aÞ ð3:5:1bÞ

where the vectors v ¼ ½v1 ; v2 ; . . . ; vn T

i ¼ ½i1 ; i2 ; . . . ; in T

FIGURE 3.5.1 Cross-sectional view of multiple coupled line structure. (From [13]. # 1985 by IEEE.)

PARALLEL INTERCONNECTIONS MODELED AS MULTIPLE COUPLED MICROSTRIPS

191

represent voltages and currents in the time domain along the n lines of the coupled structure, the superscript T denotes the transpose, and the matrices [L] and [C] are the inductance and capacitance matrices per unit length of the lines. As is well known, [L] is a positive-deﬁnite matrix while [C] is a hyperdominant matrix. Now, we can consider Eqs. (3.5.1a) and (3.5.1b) in the frequency domain. If V and I are the voltage and current vectors in the frequency domain, then, for ejðotbzÞ variation in the time domain, these equations can be easily decoupled to result in the following eigenvalue equations for voltages and currents in the frequency domain: ½½L½C l½UV ¼ ½0

ð3:5:2aÞ

½½C½L l½UI ¼ ½0

ð3:5:2bÞ

where l ¼ b2 =o2 , [U] is the unit matrix, and [0] is the null vector. The above equations can be rewritten as ½CV ¼ l½L1 V 1

½LI ¼ l½C I

ð3:5:3aÞ ð3:5:3bÞ

In most cases, the dielectric substrates used in the interconnection structures are nonmagnetic; that is, their magnetic properties are the same as those of free space. For these cases, if ½L0 and ½C0 are the inductance and capacitance matrices for the interconnection structure with the dielectric removed, then the inductance matrix for the interconnection structure with the dielectric is given by ½L ¼ ½L0 ¼ m0 e0 ½C0 1

ð3:5:4Þ

Using Eq. (3.5.4), Eqs. (3.5.3a) and (3.5.3b) can be written in terms of the capacitance matrices only. If [MV ] and [MI ] denote the voltage and current eigenvector matrices, then, using the orthogonality requirement, we have ½MI ¼ ½½MV T 1

ð3:5:5Þ

Further, writing v ¼ ½MV e

ð3:5:6aÞ

i ¼ ½MI j

ð3:5:6bÞ

we can write v ½MV e 0 ¼ T j i 0 ½MV

ð3:5:7Þ

192

INTERCONNECTION DELAYS

Substituting Eqs. (3.5.6a) and (3.5.6b), Eqs. (3.5.1a) and (3.5.1b) can be rewritten as @ @ e ¼ diag½Lk j @z @t @ @ j ¼ diag½Ck e @z @t

ð3:5:8aÞ ð3:5:8bÞ

where diag[Lk ] and diag[Ck ] are the diagonal matrices with elements given by Lk ¼ ½MV 1 ½L½½MV T 1 ¼ Ck ¼ ½MV T ½C½MV

1 u2k Ck

ð3:5:9aÞ ð3:5:9bÞ

where uk is the phase velocity of the kth mode. The characteristic impedance of the kth mode is given by 1=2 Lk Zk ¼ ð3:5:10Þ Ck For a general n-line system, Eqs. (3.5.6)–(3.5.8) lead to the equivalent circuit model shown in Fig. 3.5.2. In other words, the model shown in Fig. 3.5.2 is a circuit that is the solution of the coupled transmission line equations (3.5.1a) and (3.5.1b).

FIGURE 3.5.2 IEEE.)

Equivalent circuit model for multiple coupled lines. (From [13]. # 1985 by

PARALLEL INTERCONNECTIONS MODELED AS MULTIPLE COUPLED MICROSTRIPS

3.5.2

193

Simulation Results

Because all the model elements shown in Fig. 3.5.2 are available in the CAD program SPICE, the simulation results given below can be obtained by using SPICE [13]. For an asymmetric coupled two-line system (also called a 4-port), the SPICE model, model parameters, and its step response are shown in Figs. 3.5.3a–e. The step

FIGURE 3.5.3 Step response of asymmetric coupled microstrip four-port: (a) schematic of coupled lines; (b) equivalent SPICE model for W1 =H ¼ 2W2 =H ¼ 0:46; S=H ¼ 0:038, and er ¼ 9:8; (c, d) step response for characteristic non-mode-converting terminations Z1 ¼ 46.8 and Z2 ¼ 73:4 ; (e, f) step response for 50- terminations. (From [13]. # 1985 by IEEE.)

194

INTERCONNECTION DELAYS

FIGURE 3.5.3

(Continued).

responses for characteristic non-mode-converting terminations Z1 ¼ 48:6 and Z2 ¼ 73:4 are shown in Figs. 3.5.3c and d and, for the sake of comparison, the step response of the same structure terminated in 50 resistance is also included in Figs. 3.5.3e and f. Figure 3.5.3 shows that mismatch in normal-mode phase velocities

FIGURE 3.5.4 Step response of three-line structure terminated in ECL OR gates on alumina substrate and with W=H ¼ S=H ¼ 1. Termination symbols denote 50 consisting of two resistors in parallel: 81 to ground and 130 to 5.2 V. (From [13]. # 1985 by IEEE.)

MODELING OF LOSSY PARALLEL AND CROSSING INTERCONNECTIONS

FIGURE 3.5.4

195

(Continued).

results in a ﬁnite pulse at the isolated port for both the nonmode terminations and the 50- terminations. In order to illustrate the application of the model to nonlinear terminations, it has been applied to a three-line system terminated in logic gates shown in Fig. 3.5.4a. When the input signal is applied to the gate on the outside lines, the step response results at all other ports are shown in Figs. 3.5.4b–d. The effects of interactions among the gates and the interconnections are apparent in the results. The rise time and the gate propagation delays correspond to subnanosecond performance.

3.6

MODELING OF LOSSY PARALLEL AND CROSSING INTERCONNECTIONS AS COUPLED LUMPED DISTRIBUTED SYSTEMS

In this section, a model of the parallel and crossing interconnections in terms of coupled lumped distributed lossy networks [14] is presented. This method is an extension of that presented in the last section for lossless parallel interconnections. 3.6.1

The Model

A schematic of the interconnections analyzed in this section is shown in Fig. 3.6.1. The interconnection lines at the same or different levels that are parallel to each other are modeled as lossy parallel coupled transmission lines. The coupling between the crossing interconnections in adjacent levels is assumed to be in the immediate vicinity of the cross-over and has been modeled as a lumped element. Therefore, the crossing interconnections have been modeled as lumped distributed circuits.

196

INTERCONNECTION DELAYS

FIGURE 3.6.1 Schematic of parallel and crossing interconnections modeled in this section. (From [14]. # 1987 by IEEE.)

In terms of the normal propagation modes, the voltages and currents in an n-line system are described by the following transmission line equations: @ @ v ¼ ½Ri ½L i @z @t

ð3:6:1Þ

@ @ i ¼ ½Gv ½C v @z @t

ð3:6:2Þ

where the vectors v ¼ ½v1 ; v2 ; . . . ; vn T

i ¼ ½i1 ; i2 ; . . . ; in T

represent voltages and currents in the time domain along the n lines of the coupled structure, the superscript T denotes the transpose, and the matrices [R], [L], [G], and [C] are the series resistance, series inductance, shunt conductance, and shunt capacitance matrices per unit length of the lines, respectively. Now, we can consider Eqs. (3.6.1) and (3.6.2) in the frequency domain. If V and I are the voltage and current vectors in the frequency domain, then, for ejotgz variation in the time domain, these equations can be easily decoupled to result in the following eigenvalue equations for voltages and currents in the frequency domain: ½½ZS ½YSH l½UV ¼ ½0

ð3:6:3Þ

½½YSH ½ZS l½UI ¼ ½0

ð3:6:4Þ

MODELING OF LOSSY PARALLEL AND CROSSING INTERCONNECTIONS

197

where ½ZS ¼ ½R þ jo½L; ½YSH ¼ ½G þ jo½C; l ¼ g2 ; ½U is the unit matrix, and [0] is the null vector. Equations (3.6.3) and (3.6.4) represent the generalized matrix eigenvalue and eigenvector problem. If [Mv ] denotes the complex eigenvector matrix associated with the characteristic matrix [ZS ][YSH ], then, following the same procedure as in the last section, it can be shown that the voltage eigenvector e and the current eigenvector j are solutions of the following set of decoupled equations: d g ð3:6:5Þ e ¼ diag k j yk dz d ð3:6:6Þ j ¼ diag½gk yk e dz where gk is the propagation constant of the kth mode equal to the square root of the kth eigenvalue of [ZS ][YSH ], yk is the characteristic admittance of the kth mode equal to the corresponding element of the diagonal matrix [Yk ] given by ½Yk ¼ ½Mv 1 ½YSH ½Mv

ð3:6:7Þ

and

V I

¼

½Mv ½0

e T 1 j ½½Mv ½0

ð3:6:8Þ

For a system of n lossy parallel interconnection lines, the above equations lead to the 2n-port circuit model shown in Fig. 3.6.2, which consists of lossy uncoupled lines with a modal decoupling network at the input end and a complementary coupling network at the output end. The values of the linear real or complex dependent sources in the network are given by the elements of the voltage eigenvector matrix [Mv ]. The model presented in Fig. 3.6.2 differs from that presented in the last section for the lossless lines in that, in the present case, the uncoupled lines are lossy having complex impedances and propagation constants and the dependent sources are generally not in phase with the independent variables. It should be noted that, given the frequency-dependent behaviors of the impedances and propagation constants of these lossy lines, they can be represented as 2-ports consisting of lossless lines and lumped elements as shown in Fig. 3.6.3 for the skin effect losses. The time-domain response of the interconnection lines can be calculated directly using the model for linear as well as nonlinear terminations. 3.6.2

Simulation Results

The simulation results presented below are obtained by modeling the multiple coupled lumped distributed parameter networks representing the interconnections terminated in passive or active elements on the CAD program SPICE [14]. The

198

INTERCONNECTION DELAYS

FIGURE 3.6.2 The 2n-port circuit model representing n parallel lossy coupled interconnections. (From [14]. # 1987 by IEEE.)

FIGURE 3.6.3 Model for single lossy uncoupled line with frequency-dependent skin effect losses. (From [14]. # 1987 by IEEE.)

MODELING OF LOSSY PARALLEL AND CROSSING INTERCONNECTIONS

199

FIGURE 3.6.4 Step response for pair of crossing lines in SiO2 medium. Schematic of interconnections shown in inset. Line widths and separation are 10 mm each, length is 3 mm, and terminations are 100 each. (From [14]. # 1987 by IEEE.)

FIGURE 3.6.5 SPICE results for step response for two-level interconnection structure consisting of four lines in Si–SiO2 system. Geometry of interconnection structure and its schematic shown in (a) with W ¼ H1 ¼ H2 ¼ 2D ¼ S=2 ¼ 5 mm, H3 ¼ 250mm, length 10 mm, and Z ¼ 100 . (From [14]. # 1987 by IEEE.)

200

INTERCONNECTION DELAYS

FIGURE 3.6.5

(Continued).

parasitic elements for the interconnections have been calculated by the network analog method applied to the 3D interconnection structures in layered lossy media including the frequency-dependent coupling between the crossing lines. The step response for a pair of crossing lines in the SiO2 medium is shown in Fig. 3.6.4. The schematic of the interconnections is shown in the inset. The line widths and the separation are 10 mm each, length is 3 mm, and terminations are 100 each. For a two-level interconnection structure consisting of four lines in the Si–SiO2 system, the SPICE results for the step response are shown in Fig. 3.6.5. The geometry of the interconnection structure and its schematic are shown in Figs. 3.6.5a and b, respectively, with W ¼ H1 ¼ H2 ¼ 2D ¼ S=2 ¼ 5 mm, H3 ¼ 250 mm, ‘ ¼ 10 mm, and Z ¼ 100 . The SPICE model parameters for this case can be obtained from Fig. 3.6.2 with N ¼ 4 to be: Normal-mode Normal-mode Normal-mode Normal-mode

line line line line

1: 2: 3: 4:

impedance impedance impedance impedance

Z1 Z2 Z3 Z4

¼ 11:23 ¼ 55:16 ¼ 49:79 ¼ 179:7

; ; ; ;

delay delay delay delay

Td Td Td Td

¼ 54:24 ¼ 59:98 ¼ 75:69 ¼ 68:79

ps ps ps ps

MODELING OF LOSSY PARALLEL AND CROSSING INTERCONNECTIONS

201

FIGURE 3.6.6 SPICE results for step response of coupled crossing lines at adjacent levels in SiO2 medium. Line lengths are 3 mm, separation is 10 mm, layer thickness is 7 mm, and terminations are 100 each. (From [14]. # 1987 by IEEE.)

The dependent sources in the SPICE subcircuit denoted by xjk in Fig. 3.6.2 are given by the elements of the following voltage eigenvector matrix: 2

2:0 6 1:86303 ½Mv ¼ 6 4 0:54591 0:43182

1:01726 1:09345 0:16732 0:22045

1:02429 0:99017 1:40569 1:39422

3 0:050117 0:077621 7 7 0:415290 5 0:424816

The SPICE results for the step response of coupled crossing lines at adjacent levels in the SiO2 medium, including the effects of distributed as well as lumped couplings, are shown in Fig. 3.6.6. For these results, line lengths are 3 mm, separation is 10 mm, layer thickness is 7 mm, and terminations are 100 each. Figure 3.6.7 shows the schematic, the SPICE model, and the step response of a pair of coupled interconnections on the semi-insulating GaAs substrate including the skin effect losses. The losses are modeled in terms of the RL circuits (see Fig. 3.6.3) represented by the impedances Z1 and Z2 in the inset of Fig. 3.6.7. Other parameters are W ¼ S ¼ 10 mm, T ¼ 2 mm, H1 ¼ 2 mm, H2 ¼ 100 mm, ‘ ¼ 2 mm, and terminating impedances 100 each. The results for a general lossy layered structure consisting of three interconnection lines on a GaAs system, including the frequency-dependent skin effect losses, and the dielectric losses, are shown in Fig. 3.6.8. The interconnection structure cross section and its schematic are shown in the insets. Input signal is a 100-ps pulse with Z1 ¼ 0 and all other Z’s are 100 each.

202

INTERCONNECTION DELAYS

FIGURE 3.6.7 Schematic, SPICE model, and step response of pair of coupled interconnections on semi-insulating GaAs substrate including skin effect losses. Parameters: W ¼ S ¼ 10 mm, T ¼ 2 mm, H1 ¼ 2 mm, H2 ¼ 100 mm, length 2 mm, and terminating impedances 100 each. (From [14]. # 1987 by IEEE.)

FIGURE 3.6.8 Step response for general lossy layered structure consisting of three interconnection lines on GaAs system including frequency-dependent skin effect losses and dielectric losses. Interconnection structure cross section and its schematic diagram shown in insets. Input signal is 100ps pulse with Z1 ¼ 0 and all other Z’s are 100 each. (From [14]. # 1987 by IEEE.)

VERY HIGH FREQUENCY LOSSES IN MICROSTRIP INTERCONNECTION

3.7

203

VERY HIGH FREQUENCY LOSSES IN MICROSTRIP INTERCONNECTION

For very high speed VLSI circuits, several phenomena such as reﬂections at discontinuities, substrate losses, conductor losses, geometric dispersion, and inductive effects become important and should be included in the interconnection delay models. The interconnection line is dispersive because the propagation factor of the corresponding transmission line varies nonlinearly with the width of the line. This is further caused by the geometric dispersion in the microstripline reﬂected in the frequency dependence of the effective dielectric constant, by the ﬁnite conductivity of the silicon substrate, and by the frequency dependence (due to the skin effect) of the resistance of the metal conductor. In this section, a model of pulse propagation in an isolated microstrip interconnection on Si substrate, including several of the high-frequency effects [49], is presented. Quasi-TEM mode propagation is assumed and the analysis is valid for frequencies up to the lowest frequency at which non-TEM modes can propagate in the microstrip interconnection. This limit corresponds to the cutoff frequency for the surface wave mode [50], which is inversely related to the substrate thickness and is 50 GHz for a silicon wafer of 450 mm thickness. 3.7.1

The Model

A schematic of the microstrip interconnection on the Si substrate is shown in Fig. 3.7.1. We assume that the dielectric constant er of the substrate is real and constant, which is valid in Si for frequencies up to 1013 Hz. Furthermore, we include the effect of the insulator (the oxide layer) by treating it as an open circuit at zero frequency and as a short circuit at all other frequencies. This assumption is valid because, even at 100 MHz, the impedance introduced by the capacitance of the oxide layer is negligible as long as its thickness (t0 ) is much smaller than the substrate thickness

FIGURE 3.7.1

Schematic of microstrip interconnection line on silicon substrate [49].

204

INTERCONNECTION DELAYS

(h). As stated above, we also assume quasi-TEM mode propagation, which is justiﬁed at the substrate resistivities and frequencies used in this section. This can be further justiﬁed by ﬁnding the ratio of the longitudinal and tangential electric ﬁelds of the mode and verifying that this ratio is much smaller than 1. Using the parallelplate model, this ratio is given by jEz j 2er e0 ¼ jEx j sdm0

t d

ð3:7:1aÞ

jEz j er e0 ¼ jEx j stm0

td

ð3:7:1bÞ

where t is the conductor thickness, s is the conductivity of the conductor, and d is the skin depth in the conductor. For the results presented in this section, this ratio is much smaller than 1. In fact, it is the largest (0.1) for the 0.5-mm-thick poly-Si line (resistivity 500 m cm) for frequencies below 1012 Hz. For a given voltage waveform vð0; tÞ at one end of the microstrip, we need to ﬁnd the voltage waveform vðz; tÞ at any point z along the microstripline. This can be accomplished by carrying out the Fourier decomposition of vð0; tÞ, multiplying the various terms by the corresponding propagation factors, and then performing the inverse Fourier transformation, that is, vðz; tÞ ¼ F 1 ½Ffvð0; tÞg eðaþjbÞz

ð3:7:2Þ

where a is the attenuation constant, b is the propagation constant, F denotes Fourier transformation, and F 1 represents the inverse Fourier transformation. Using the symbols shown in Fig. 3.7.1, the effective dielectric constant eeff and the characteristic impedance Z0 at zero frequency have been calculated by Schneider [51] to be " # er 1 ð3:7:3Þ eeff ¼ 0:5 ðer þ 1Þ þ pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 1 þ 10ðh=wÞ

Z0 ¼

8 > > > < > > > :

60 8h w þ pﬃﬃﬃﬃﬃﬃﬃ ln eeff w 4h 120p

w
pﬃﬃﬃﬃﬃﬃﬃ w > h ½w=h þ 2:42 0:44h=w þ ð1 h=wÞ6 eeff

The maximum relative error in expressions (3.7.3) and (3.7.4) is less than 2%; however, corrections [52] are required for t=h > 0:005. The expression for eeff at high frequencies has been derived by Yamashita et al [53] and is given by pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃ er eeff ð0Þ eeff ð f Þ ¼ eeff ð0Þ þ 1 þ 4F 1:5

ð3:7:5Þ

VERY HIGH FREQUENCY LOSSES IN MICROSTRIP INTERCONNECTION

205

where n 4fh pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ wo2 er 1 0:5 þ 1 þ 2 log 1 þ F c h f is the frequency, and c is the speed of light in a vacuum. The error in the expression (3.7.5) is less than 1%. For a lossless material, the propagation constant b0 is given by b0 ¼

pﬃﬃﬃﬃﬃﬃﬃ 2pf eeff c

ð3:7:6Þ

However, for a conductor of ﬁnite resistivity and substrate material of ﬁnite conductivity, the attenuation should be considered. At low frequencies where the current distribution in the conductor can be considered uniform, the conductor loss factor ac is given in nepers as rc ac ¼ ð3:7:7Þ 2wtZ0 where rc is the resistivity of the metal. However, at high frequencies where the current distribution is not uniform due to the skin effect, the conductor loss is given by [54] 8 " 0 2 # > R w h hflnð4pw=tÞ þ t=wg w 1 s > > 1 < 1þ 0þ > > 0 > 2pZ h 4h w pw h 2p 0 > > > > > > > > " 0 2 # > > R w h hflnð4h=tÞ t=hg 1 w > s > > 1 < <2 1þ 0þ > < 2pZ0 h 4h w pw0 2p h : ac ¼ > > > > Rs =ðZ0 hÞ w0 w0 =ðphÞ > > > þ > 2 > 0 0 h 0:94 þ w0 =ð2hÞ > ½w =h þ ð2=pÞ lnf2pe½0:94 þ w =ð2hÞg > > > > > > > > h hflnð2h=tÞ t=hg w > > : 1þ 0þ >2 0 w pw h ð3:7:8Þ where m is the permeability of the metal, Rs

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pf mrc , and

8 t 4pw w 1 > > < > < w þ p 1 þ ln t h 2p w0 ¼ > t 2h w 1 > > > : w þ 1 þ ln p t h 2p

206

INTERCONNECTION DELAYS

FIGURE 3.7.2 [49].

Dependences of conductor loss, dielectric loss, and line loss on frequency

The dielectric loss ad caused by the nonzero conductivity of the substrate has been derived by Welch and Pratt [55] and is given by ad ¼

60pss ðeeff 1Þ pﬃﬃﬃﬃﬃﬃﬃ ðer 1Þ eeff

ð3:7:9Þ

where ss is the conductivity of the substrate. For a 50-, 0.5-mm-thick aluminum microstripline on a 450-mm-thick Si wafer of resistivity 100 cm, the dependences of the conductor loss, dielectric loss, and line loss on frequency in the range 108–1013 Hz are shown in Fig. 3.7.2. The circuit diagram and circuit equations for the transmission line model of the microstrip interconnection are given in Fig. 3.7.3, where L and C denote

FIGURE 3.7.3 Circuit diagram and circuit equations for transmission line model of microstrip interconnection [49].

VERY HIGH FREQUENCY LOSSES IN MICROSTRIP INTERCONNECTION

207

the inductance and capacitance per unit length for the lossless line and Rc and Rd denote the resistances per unit length introduced by the conductor resistance and the substrate conductance. The circuit equations can be solved to yield the following expressions for the general attenuation constant a and propagation constant b: qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃ ﬃ 1 ð f þ f2 Þ 1 2 qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃ b ¼ 12ðf1 þ f2 Þ

a¼

ð3:7:10aÞ ð3:7:10bÞ

where Rc f1 ¼ o2 LC Rd " 2 #" 2 # Rc Z0 2 2 f2 ¼ o LC þ o LC þ Z0 Rd

ð3:7:11Þ

with Z0 ¼ ðL=CÞ0:5 . For low-loss conditions, the circuit model of Fig. 3.7.3 yields ac ¼

Rc 2Z0

ad ¼

Z0 2Rd

pﬃﬃﬃﬃﬃﬃ b0 ¼ o LC

ð3:7:12Þ

Equations (3.7.11) and (3.7.12) can be combined to rewrite f1 and f2 in terms of, b0 , ac , and ad as f1 ¼ b20 4ac ad

f2 ¼ b20 þ 4a2c b20 þ 4a2d

ð3:7:13Þ

Then Eqs. (3.7.6)–(3.7.9) can be combined with Eqs. (3.7.10) and (3.7.13) to obtain a and b for all loss conditions. If ac and ad are small as compared to b0 , as will be the case under low-loss conditions, then a and b are given by

a ¼ ac þ ad

3.7.2

b¼

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ðac ad Þ2 þ b20

ð3:7:14Þ

Simulation Results

The simulation results are obtained for two input high-speed logic waveforms consisting of square-wave and exponential pulses. The input square-wave pulses are of 50 ps duration with 12 ps rise and fall times. The input exponential pulses are of the form vðtÞ ¼ eðt=t1 Þ ½1 eðt=t2 Þ

ð3:7:15Þ

208

INTERCONNECTION DELAYS

FIGURE 3.7.4 Circuits used to produce (a) exponential and (b) square-wave input pulses for simulation results presented in this section [49].

Input pulses vsw ð0; tÞ and vex ð0; tÞ with ﬁnite rise and fall times can be produced by applying ideal square-wave and exponential pulses to the circuits shown in Fig. 3.7.4. By choosing the circuit parameters in Fig. 3.7.4, a variety of pulses can be obtained. The Fourier transforms of the input square-wave pulses are given by

1 ejot1 Vsw ð0; f Þ ¼ jo

1 1 þ jot2 o2 =o21

ð3:7:16Þ

where o21 ¼

1 LC

t2 ¼

L Z0

The Fourier transforms of the input exponential pulses are given by Vex ð0; f Þ ¼

1 jo þ 1=t1

1 1 þ jot2 þ t2 =t1

ð3:7:17Þ

where t1 ¼ Z0 C

t2 ¼ RC

As stated earlier, the voltage response vðz; tÞ at a distance z along the microstripline are obtained by multiplying the Fourier transform of the input waveform (at z ¼ 0) by the propagation factor exp½ða þ jbÞz and then taking the inverse Fourier transform. The dependences of the characteristic impedance on frequency for two microstrips of widths 10 and 300 mm on a Si wafer of thickness 450 mm are shown in Fig. 3.7.5. This ﬁgure shows that the region of geometric dispersion extends from 10 to 300 GHz and that this effect is more pronounced for the narrow line width of 10 mm. Figure 3.7.6 shows the line losses versus frequency for microstriplines made

VERY HIGH FREQUENCY LOSSES IN MICROSTRIP INTERCONNECTION

209

FIGURE 3.7.5 Characteristic impedance versus frequency for two microstrip interconnections of widths 10 and 300 mm [49].

FIGURE 3.7.6 Plots of line loss versus frequency for interconnection materials of Al (r ¼ 2:7 m cm), W (r ¼ 10 m cm), WSi2 (r ¼ 30 m cm), and poly-Si (r ¼ 500 m cm) on 450-mm-thick Si wafer [49].

210

INTERCONNECTION DELAYS

FIGURE 3.7.7 Plots of phase velocity versus frequency for interconnection materials of Al (r ¼ 2:7 m cm), W (r ¼ 10 m cm), WSi2 (r ¼ 30 m cm), and poly-Si (r ¼ 500 m cm) on 450-mm-thick Si wafer [49].

of aluminum, tungsten, WSi2, and poly-Si of widths 10 and 300 mm on two substrates with resistivities of 10 and 100 cm. The dependences of the phase velocity on frequency for the same set of parameters as in Fig. 3.7.6 are shown in Fig. 3.7.7. For exponential input pulse (with t1 ¼ 15 ps and t2 ¼ 1 ps) and square-wave input pulse (with t1 ¼ 50 ps, t2 ¼ 5 ps, and o1 ¼ 1012 Hz), the time-domain waveforms for aluminum interconnections of widths 10 and 300 mm on two substrates with resistivities of 10 and 100 cm at z values of 3 and 6 mm are shown in Figs. 3.7.8 and 3.7.9. It should be noted that for the substrate resistivity of 10 cm the signal is severely attenuated by 6 mm whereas for the substrate resistivity of 100 cm it is not affected as much. Thus, it can be concluded that high-resistivity substrates are more appropriate when designing microstrip interconnections for high-frequency ICs. For interconnection materials of tungsten, WSi2, and poly-Si and for the squarewave input pulses, the time-domain waveforms at a few locations on the microstrip interconnection on two substrates with resistivities of 10 and 100 cm are shown in Figs. 3.7.10–3.7.12. It should be noted that the conductor loss becomes increasingly signiﬁcant from aluminum to tungsten to WSi2 lines but the changes are not

VERY HIGH FREQUENCY LOSSES IN MICROSTRIP INTERCONNECTION

211

FIGURE 3.7.8 Plots of time-domain exponential pulses after 0, 3, and 6 mm of propagation on Al microstriplines on 450-mm-thick Si wafer [49].

FIGURE 3.7.9 Plots of time-domain square-wave pulses after 0, 3, and 6 mm of propagation on Al microstriplines on 450-mm-thick Si wafer [49].

212

INTERCONNECTION DELAYS

FIGURE 3.7.10 Plots of time-domain square-wave pulses after 0, 3, and 6 mm of propagation on W microstriplines on 450-mm-thick Si wafer [49].

FIGURE 3.7.11 Plots of time-domain square-wave pulses after 0, 1.5, and 3 mm of propagation on WSi2 microstriplines on 450-mm-thick Si wafer [49].

VERY HIGH FREQUENCY LOSSES IN MICROSTRIP INTERCONNECTION

213

FIGURE 3.7.12 Plots of time-domain square-wave pulses after 0, 1.5, and 3 mm of propagation on poly-Si microstriplines on 450-mm-thick Si wafer [49].

dramatic. Figure 3.7.12 shows that, for poly-Si lines, the loss becomes very large for very high speed pulses though signiﬁcant improvement is achieved by choosing higher resistivity substrates, as is the case with other lines as well. 3.7.3

Interconnection Delays with High-Frequency Effects

The transmission line model for the single-level interconnections presented in Section 3.2 can be modiﬁed to include the high-frequency losses described above. Then each section of the transmission line will be modiﬁed to that shown in Fig. 3.7.13. The propagation constant for the interconnection line will be given by vﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ " !#ﬃ u 4 X u 1 þ s Ci þ Yi g ¼ tðRc þ sLi Þ Rd i¼1

ð3:7:18Þ

FIGURE 3.7.13 One section of transmission line including very high frequency effects [56].

214

INTERCONNECTION DELAYS

and the characteristic impedance will be given by vﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ u Rc þ sLi u ! Z0 ¼ u 4 u1 X t þs C þ Yi i Rd i¼1

ð3:7:19Þ

where the Yi ’s are deﬁned in Section 3.2. The rest of the analysis can be completed following the steps outlined in Section 3.2. In the following simulation results [56], one of the parameters is changed while the others are set as follows: frequency f ¼ 10 GHz, interconnection widths 1 mm each, interconnection lengths 1 mm each, source resistance Rs ¼ 700 , load capacitance CL ¼ 100 fF, substrate thickness 200 mm, and interconnection material resistivity 2.82 m cm for aluminum. Figure 3.7.14 shows the dependence of the delay time on the frequency of the input signal. It can be seen that the dependence of propagation delay on the frequency is minimal until it is near and above the 1-MHz range when the propagation delay becomes quite responsive to a change in the frequency. After 1 GHz, the delay suggests signiﬁcant skin effect and dielectric losses. Figure 3.7.15 shows the delay time as a function of the interconnection width at f ¼ 10 GHz. It shows that the delay time increases steadily as the width and hence the interconnection capacitance are increased. Decreasing the line resistance with increasing width does not seem to play an important role because of the dominant skin effect at high frequencies.

FIGURE 3.7.14 Dependence of delay time on frequency of input signal [56].

VERY HIGH FREQUENCY LOSSES IN MICROSTRIP INTERCONNECTION

215

FIGURE 3.7.15 Dependence of delay time on width of interconnection line at 10 GHz [56].

Delay time as a function of the interconnection material resistivity is shown in Fig. 3.7.16. Figure 3.7.17 displays the dependence of delay time on load capacitance, which corresponds to the input capacitance of the gate loading the interconnection. Figure 3.7.18 shows the dependence of delay time on source resistance, which corresponds to the output resistance of the gate/transistor driving the interconnection line.

FIGURE 3.7.16 10 GHz [56].

Dependence of delay time on resistivity of interconnection material at

216

INTERCONNECTION DELAYS

FIGURE 3.7.17 Dependence of delay time on load capacitance at 10 GHz [56].

FIGURE 3.7.18 Dependence of delay time on driving source resistance at 10 GHz [56].

3.8

COMPACT EXPRESSIONS FOR INTERCONNECTION DELAYS

In this section, compact, that is, closed-form, expressions for the voltage waveforms and the coresponding delays at the load end of an interconnection are presented. First, the interconnection will be modeled as a distributed RC network [57] and then

COMPACT EXPRESSIONS FOR INTERCONNECTION DELAYS

217

it will be treated as an RLC network [19]. The expressions are useful for obtaining quick estimates of the interconnection delays though at the cost of some accuracy. 3.8.1

The RC Interconnection Model

Consider a single-level interconnection of length ‘ driven by a transistor or a gate and connected to another transistor or gate at its load end, as shown in Fig. 3.8.1. It can be modeled as an interconnection line driven by a voltage source of internal resistance RS and loaded by a capacitor CL. Inductive effects are neglected in this treatment. Voltage wave propagation along this line is represented by the differential equation 1 @2V @V ¼ c r @x2 @t

ð3:8:1Þ

where r and c are the resistance and capacitance of the interconnection line per unit length, respectively. The voltage waveform Vð‘; tÞ at the interconnection load can be expressed as a series [58]: 1 X Vð‘; tÞ ¼1þ Kk esk t=RC 1 þ K1 es1 t=RC VS k¼1

ð3:8:2Þ

where R and C are the total resistance and capacitance of the interconnection line, respectively, that is, R ¼ ðrÞð‘Þ and C ¼ ðcÞð‘Þ. The sk ’s are the roots of the equation [57] pﬃﬃﬃﬃﬃﬃ 1 RT CT sk tan sk ¼ pﬃﬃﬃﬃﬃﬃ ðRT þ CT Þ sk

ð3:8:3Þ

subject to the condition

pﬃﬃﬃﬃﬃﬃ

k 32 p < sk < k 12 p

FIGURE 3.8.1 Single-level interconnection of length ‘ driven by a voltage source of internal resistance RS and loaded by capacitance CL .

218

INTERCONNECTION DELAYS

where RT ¼

RS R

CT ¼

CL C

The coefﬁcients Kk can be calculated from the equation pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 2 ð1 þ R2T sk Þð1 þ CT2 sk Þ Kk ¼ ð1Þ pﬃﬃﬃﬃﬃﬃ sk ð1 þ R2T sk Þð1 þ CT2 sk Þ þ ðRT þ CT Þð1 þ RT CT sk Þ k

ð3:8:4Þ

The approximation in Eq. (3.8.2) is excellent for t > 0:1RC and therefore K1 and s1 are the most important coefﬁcients. The approximate values of these two coefﬁcients are given by

RT þ C T þ 1 K1 ¼ 1:01 RT þ CT þ p=4 s1 ¼

1:04 RT CT þ RT þ CT þ ð2=pÞ2

ð3:8:5Þ ð3:8:6Þ

The relative errors of the above functions are less than 3% for K1 and less than 4% for s1 for any values of RT and CT . It should be noted that the exact value of K1 is 4=p and that of s1 is ðp=2Þ2 for RT ¼ CT ¼ 0. When RT ¼ CT 1, the exact value of K1 is 1 and that of s1 is 1=½ðRT þ 1ÞðCT þ 1Þ. Both these asymptotic values are correctly produced by expressions (3.8.5) and (3.8.6). The voltage waveform at the load end of the interconnection can be expressed as Vð‘; tÞ t=ðRCÞ 0:1 ¼ 1 exp VS RT CT þ RT þ CT þ 0:4

ð3:8:7Þ

Equation (3.8.7) can be solved for t in terms of Vð‘Þ. The time t taken by the load voltage to reach v ¼ V=VS is given by 1 ðRT CT þ RT þ CT þ 0:4Þ t ¼ RC 0:1 þ ln 1v

ð3:8:8Þ

Equation (3.8.8) can be further solved to ﬁnd the times t0:5 and t0:9 for v ¼ 0:5 and v ¼ 0:9, respectively, as t0:5 ¼ RC½0:377 þ 0:693ðRT CT þ RT þ CT Þ t0:9 ¼ RC½1:02 þ 2:3ðRT CT þ RT þ CT Þ

ð3:8:9Þ ð3:8:10Þ

COMPACT EXPRESSIONS FOR INTERCONNECTION DELAYS

219

Comparisons of the load voltage waveforms and the corresponding delays obtained using the compact expressions (3.8.9) and (3.8.10) with those obtained using the exact analysis show that the error in Eq. (3.8.8) is less than 3.5% of RC [57]. The accuracy of this equation is better than that given by the widely used Elmore’s delay expression [59]. 3.8.2

The RLC Interconnection Model: Single Semi-Inﬁnite Line

A single semi-inﬁnite interconnection line modeled as a distributed RLC network driven by a step input voltage source VS with a source resistance RS is shown in Fig. 3.8.2. The voltage Vinf ðx; tÞ along this line is described by the partial differential equation @2 @2 @ Vinf ðx; tÞ ¼ lc 2 Vinf ðx; tÞ þ rc Vinf ðx; tÞ 2 @x @t @t

ð3:8:11Þ

where r, l, and c are the distributed resistance, inductance, and capacitance per unit length of the interconnection line, respectively. Assuming that the voltage and current along the line are zero at t ¼ 0, Laplace transformation of Eq. (3.8.11) yields the differential equation @2 r V ðx; sÞ ¼ lcs s þ ð3:8:12Þ Vinf ðx; sÞ inf @x2 l In the Laplace (s) domain, a general solution of Eq. (3.8.12) can be written as rﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ rﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ﬃ ﬃ pﬃﬃﬃﬃ pﬃﬃﬃﬃ r r Vinf ðx; sÞ ¼ A exp x lc s s þ þ B exp x lc s s þ ð3:8:13Þ l l

FIGURE 3.8.2 Single semi-inﬁnite interconnection line (a) modeled as distributed RLC network and (b) driven by input voltage source VS with source resistance RS .

220

INTERCONNECTION DELAYS

The coeﬁcient A can be determined from applying the known boundary condition at x ¼ 0 that Vinf ð0; sÞ is equal to the input source voltage VS ðsÞ minus the voltage drop across the source impedance in the s domain while B can be determined from the requirement that at x ¼ 1 the voltage must be ﬁnite and well behaved, resulting in B ¼ 0. Then the voltage along the line in the s domain is given by ﬃ rﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃ ZðsÞ r exp x lc s s þ Vinf ðx; sÞ ¼ VS ðsÞ ð3:8:14Þ ZðsÞ þ RS l where ZðsÞ is the characteristic impedance of the lossy interconnection given by rﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ rﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ r þ sl s þ r=l ¼ Z0 ZðsÞ ¼ sc s

ð3:8:15Þ

pﬃﬃﬃﬃﬃﬃ where Z0 is the characteristic impedance of the lossless line given by Z0 ¼ l=c. The voltage along the semi-inﬁnite line in the time domain can be obtained by an inverse Laplace transformation of Eq. (3.8.14) to be [19]

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃ Z0 r=ð2lÞt e I0 s t2 ðx lcÞ2 Vinf ðx; tÞ ¼ VS Z0 þ RS pﬃﬃﬃﬃ!k=2 h qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 1 i pﬃﬃﬃﬃ 2 1 X t x lc 2 pﬃﬃﬃﬃ Ik s t ðx lcÞ 4 ð1 þ Þ2 k1 þ 1 k¼1 t þ x lc pﬃﬃﬃﬃ u0 ðt x lcÞ

ð3:8:16Þ

where s ¼ r=ð2lÞ, Ik is the kth-order modiﬁed Bessel function, u0 is a unit step function, and is the reﬂection coefﬁcient deﬁned by ¼

RS Z0 RS þ Z0

The voltage along the lossless semi-inﬁnite line can be obtained from Eq. (3.8.16) after substituting r ¼ 0 to be Vinf ðx; tÞ ¼ VS

pﬃﬃﬃﬃ Z0 u0 ðt x lcÞ Z0 þ RS

ð3:8:17Þ

because the zero-order modiﬁed Bessel function has a value of unity and all higher order modiﬁed Bessel functions become zero. pﬃﬃﬃﬃ It is interesting to note from Eq. (3.8.16) that at t ¼ x lc the voltage wavefront traveling down the lossy semi-inﬁnite line is given by Vinf ðx; tÞ ¼ VS

Z0 er=ð2Z0 Þx Z0 þ RS

ð3:8:18Þ

COMPACT EXPRESSIONS FOR INTERCONNECTION DELAYS

221

FIGURE 3.8.3 Single interconnection of ﬁnite length modeled as distributed RLC network driven by input voltage source VS with a source resistance RS and terminated by open circuit.

3.8.3

The RLC Interconnection Model: Single Finite Line

A global interconnection for gigascale integration can be represented by a ﬁnite line of length ‘ driven by a source with an arbitrary source impedance and terminated by an open circuit [60] as shown in Fig. 3.8.3. The reﬂection diagram for a line of ﬁnite length is shown in Fig. 3.8.4. In the s domain, the voltage at the end of the line is given by

Vfin ð‘; sÞ ¼ 2Vinf ð‘; sÞ þ 2

q X RS ZðsÞ n n¼1

RS þ ZðsÞ

Vinf ½ð2n þ 1Þ‘; s

ð3:8:19Þ

where n is the reﬂection number, q is the maximum reﬂection number shown in Fig. 3.8.4, and ZðsÞ is deﬁned by Eq. (3.8.15). In the time domain, the voltage at the

FIGURE 3.8.4 Reﬂection diagram for single interconnection of ﬁnite length. (From [19]. # 2000 by IEEE.)

222

INTERCONNECTION DELAYS

end of the ﬁnite line is given by [19] q X n X 1 X Z0 nðn 1þ jÞ! Vfin ð‘; tÞ ¼ 2Vinf ð‘; tÞ þ 2VS er=ð2lÞt ð1Þi niþj Z0 þ RS i!j!ðn iÞ! n¼1 i¼0 j¼0 ( ! pﬃﬃﬃﬃ ðiþjÞ=2 qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃ t ð2n þ 1Þ‘ lc 1 pﬃﬃﬃﬃ Iiþj s t2 ½ð2n þ 1Þ‘ lc2 þ 1 t þ ð2n þ 1Þ‘ lc ! pﬃﬃﬃﬃ ðiþjþkÞ=2 qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 1 X pﬃﬃﬃﬃ t ð2n þ 1Þ‘ lc p ﬃﬃﬃﬃ Iiþjþk s t2 ½ð2n þ 1Þ‘ lc2 t þ 2n þ 1Þ‘ lc k¼1 ) pﬃﬃﬃﬃ ½4 ð1 þ Þ2 k1 u0 ½t ð2n þ 1Þ‘ lc ð3:8:20Þ where q, deﬁned earlier as the maximum reﬂection number for a given time, can be written as a function of time as t 1:0 ð3:8:21Þ q ¼ 0:5 pﬃﬃﬃﬃ þ 1:0 x lc with the notation hxi representing the decimal truncation of x, that is, h2:3i ¼ h2:8i ¼ 2: For the special case when the driving source resistance RS is equal to the characteristic impedance of the lossless line Z0 and the reﬂection coefﬁcient becomes zero, the voltage at the end of the ﬁnite line is given by q X Vfin ð‘; tÞ ¼ 2Vinf ð‘; tÞ þ VS er=ð2lÞt ð1Þn (

n¼1

pﬃﬃﬃﬃ!n=2 qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃ t ð2n þ 1Þ‘ lc pﬃﬃﬃﬃ In s t2 ½ð2n þ 1Þ‘ lc2 t þ ð2n þ 1Þ‘ lc pﬃﬃﬃﬃ!ðnþkÞ=2 1 X t ð2n þ 1Þ‘ lc pﬃﬃﬃﬃ : þ t þ ð2n þ 1Þ‘ lc k¼1 ) qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ n pﬃﬃﬃﬃ 2 pﬃﬃﬃﬃ o k1 2 Inþk s t ½ð2n þ 1Þ‘ lc ð4 0 Þ u0 ½t ð2n þ 1Þ‘ lc ð3:8:22Þ Comparisons of the normalized end-of-line voltages obtained by the compact expression (3.8.20) with those obtained by HSPICE with 1, 10, 50, and 500 lumped RLC elements are shown in Fig. 3.8.5 [19]. For these comparisons, the interconnection metal is assumed to be copper surrounded by a low-k dielectric. The various interconnection parameters are as follows: Interconnection length 3.6 cm Interconnection cross section 2.1 mm 2.1 mm Resistance per unit length 37.9 /cm

1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0

0.0e+00

Normalized End of Line Voltage, V(L,t)/Vdd

HSPICE Simulation New Compact Expressions

2.0e–00

4.0e–10 6.0e–10 Time [sec] (a)

8.0e–10

Normalized End of Line Voltage, V(L,t)/Vdd

1.5 1.4 1.3

1.5 1.4 1.3 1.2 1.1 1.0 0.9 HSPICE Simulation 0.8 New Compact Expressions 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0e+00 2.0e–00 4.0e–10 6.0e–10 8.0e–10 1.0e–09 Time [sec] (c)

223

1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6

HSPICE Simulation New Compact Expressions

0.5 0.4 0.3 0.2 0.1 0.0

0.0e+00

1.0e–09

Normalized End of Line Voltage, V(L,t)/Vdd

Normalized End of Line Voltage, V(L,t)/Vdd

COMPACT EXPRESSIONS FOR INTERCONNECTION DELAYS

2.0e–00

4.0e–10 6.0e–10 Time [sec] (b)

8.0e–10

1.0e–09

1.5 1.4 1.3 1.2 1.1 1.0 0.9 HSPICE Simulation 0.8 New Compact Expressions 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0e+00 2.0e–00 4.0e–10 6.0e–10 8.0e–10 1.0e–09 Time [sec] (d)

FIGURE 3.8.5 Comparisons of normalized end-of-line voltages obtained by compact expression (3.8.20) with those obtained by HSPICE with 1, 10, 50, and 500 lumped RLC elements. (From [19]. # 2000 by IEEE.)

Driving source resistance 133.2 Lossless characteristic impedance 266.5 Figure 3.8.5 shows that the HSPICE waveforms approach the compact expression waveform as the number of RLC elements is increased in the HSPICE simulation. For the typical values of the interconnection and driving source parameters chosen in these comparisons, there is virtually complete agreement between the two waveforms for 500 or more RLC elements, lending excellent support to the compact expression (3.8.20). 3.8.4

Single RLC Interconnection: Delay Time

For a distributed RC interconnection line, Sakurai [57] has derived the following compact expression for the delay time deﬁned as the time taken by the load voltage to reach 50% of its steady-state value: Td;RC ¼ 0:693RS c‘ þ 0:377rc‘2

ð3:8:23Þ

224

INTERCONNECTION DELAYS

For a distributed RLC interconnection line, this expression has been extended by Davis and Meindl as follows [19]: 8 ‘ R 4Z0 > > > pﬃﬃﬃﬃ and RS < 3Z0 ð3:8:24Þ for ln < RS þ Z0 Z0 lc Td;RLC ¼ > R 4Z0 > 2 > or RS > 3Z0 ð3:8:25Þ :0:693RS c‘ þ 0:377rc‘ for 2 ln RS þ Z0 Z0 A comparison of the time delay obtained by the above closed-form expressions with that obtained from the compact RLC expression shows that the error in the simpliﬁed expression is less than 5% when RS =Z0 < 0:2 or when R=Z0 > 2:3. Outside this region, more accurate delay time can be obtained by using the compact distributed RLC expressions. 3.8.5

Two and Three Coupled RLC Interconnects: Delay Times

An analysis of two and three coupled RLC interconnects with open-circuit terminations [20] is presented in Chapter 4. For a system of two coupled distributed RLC interconnects A (active) and Q (quiet) shown in Fig. 3.8.6, the worst-case time delay occurs when the mutual capacitance between the lines is the highest, that is, when the two lines are switching with opposite polarities. The solution for the voltage in this case is given by V, which is effectively the solution for a single ﬁnite line with inductance l ¼ ðls lm Þ and capacitance c ¼ cs þ 2cm . It is given by VA ð‘; tÞ ¼ Vfin ð‘; t; l ¼ ls lm ; c ¼ cgnd þ 2cm Þ

ð3:8:26Þ

For a system of three parallel coupled interconnects, each driven by a voltage source VS having an internal source resistance RS sandwiched between two virtual ground planes as shown in Fig. 3.8.7, the worst-case time delay occurs when the inner interconnection is active and the two outer lines simultaneously switch with an opposite polarity. After adjusting the initial and boundary conditions (see detailed analysis in Chapter 4), the load voltage waveform on the inner (active) interconnection is given by 4 1 ; c ¼ 2c þ 3c VA ð‘; tÞ ¼ Vfin ‘; t; l ¼ gnd m 3 ð2cgnd þ 3cm Þv2 1 1 ð3:8:27Þ Vfin ‘; t; l ¼ ; c ¼ 2c gnd 3 2cgnd v2

FIGURE 3.8.6 Two coupled distributed RLC interconnects A (active) and Q (quiet). (From [20]. # 2000 by IEEE.)

COMPACT EXPRESSIONS FOR INTERCONNECTION DELAYS

225

FIGURE 3.8.7 Three parallel coupled interconnects sandwiched between two virtual ground planes. (From [20]. # 2000 by IEEE.)

In Eqs. (3.8.26) and (3.8.27), Vfin ðx; tÞ represents the voltage waveform along a single interconnection line given by Vfin ð‘; tÞ ¼ 2Vinf ðx ¼ ‘; t; m ¼ 0Þ q X n X 1 X nðn 1 þ jÞ! þ 2er=ð2lÞt ð1Þi ðniþjÞ i!j!ðn iÞ! n¼1 i¼0 j¼0 Vinf ðx ¼ ð2n þ 1Þ‘; t; m ¼ iþ jÞ

ð3:8:28Þ

where Vinf ðx; t; mÞ denotes the voltage waveform along the semi-inﬁnite line given by pﬃﬃﬃﬃ!m=2 qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃ Z0 t x lc r pﬃﬃﬃﬃ er=ð2lÞt I0 t2 ðx lcÞ2 Vinf ðx; t; mÞ ¼ VS Z0 þ R S 2l t þ x lc !ðkþmÞ=2 p ﬃﬃﬃﬃ 1 1X t x lc pﬃﬃﬃﬃ þ er=ð2lÞt ½4 ð1 þ Þ2 k1 2 k¼1 t þ x lc qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃ pﬃﬃﬃﬃ r t2 ðx lcÞ2 uðt x lcÞ ð3:8:29Þ IðkþmÞ 2l

In the above analysis, we have assumed that the interconnects are open circuited at the load ends and the capacitance of the driving source has been neglected. It has been shown [21] that, for an interconnection driven by a large driver, neglecting the source capacitance causes about 5% error in the 50% delay time whereas neglecting both the driver and load capacitances results in an error of about 14%. For a detailed treatment of capacitively terminated single and coupled distributed RLC interconnects, readers are referred to [21].

226

3.9

INTERCONNECTION DELAYS

INTERCONNECTION DELAYS IN MULTILAYER INTEGRATED CIRCUITS

There has always been an interest in extending the concept of multilevel interconnections to 3D integrated circuits with active devices such as transistors, gates, cells, and so on, on several planes. The potential for fabricating IC chips with multiple planes of almost independent circuits [61–66] has been demonstrated by researchers by using silicon-on-insulator (SOI) techniques [67], and this can be called multilayer circuit (MLC) technology. In this section, a simpliﬁed model of interconnection delays in multilayer ICs [68] is presented. The interconnection delay in an MLC chip is normalized to that in an equivalent single-plane chip. This is followed by a study of the dependences of these interconnection delays on several parameters of the MLC chip, such as the number of devices on the chip, the number of circuit planes, the interconnection complexity, and the characteristics of the interconnection material. 3.9.1

The Simpliﬁed Model

For this analysis, a multilayer circuit is deﬁned as one consisting of independent circuits on more than one plane; that is, an MLC chip looks like a stack of two or more independent chips with vertical interconnections between them. In other words, the placement of transistors and interconnections on each plane does not depend on the fabrication and other characteristics on other planes. An example of a four-layer MLC is shown in Fig. 3.9.1. Generally, aluminum is considered to be a suitable interconnection material for the top plane of an MLC chip while, for the other planes, the interconnection material is chosen from refractory metals, silicides, and polysilicon.

FIGURE 3.9.1

Schematic of four-layer MLC structure. (From [68]. # 1986 by IEEE.)

INTERCONNECTION DELAYS IN MULTILAYER INTEGRATED CIRCUITS

227

In this analysis, several simplifying assumptions are made. First, it is assumed that each plane of the MLC chip uses the same basis technology and that it is the same as that for the single-plane chip used for normalization. Next, it is assumed that the various devices are evenly divided among all planes of the MLC chip; that is, if n is the number of devices and p is the number of planes, then the number of devices on each plane is equal to n=p. It is further assumed that there exists an interconnection complexity factor m which represents the degree to which the interconnection complexity inﬂuences the circuit area and that m is the same for each plane. If k represents a technology-dependent normalization constant, then the chip area A is modeled as m n ð3:9:1Þ A¼k p Therefore, when m ¼ 1, the total area required for constructing the MLC chip will be the same as that of the corresponding single-plane chip and, when m > 1, it will be less than that for the single-plane chip because of the reduction in fractional area required for the interconnections. A simple model for the interconnection delay t can be constructed in terms of the RC time constant associated with the interconnection line. For an interconnection of length L and width W, t can be written as L ð3:9:2Þ ðcLWÞ ¼ rp cL2 t ¼ RC ¼ rp W where rp is the thin-ﬁlm resistivity of the interconnection material and c is its capacitance per unit area. The fringing ﬁelds as well as the coupling capacitances with the neighboring conductors have been neglected. Obviously, the maximum interconnection delay is associated with the longest interconnection line, and an estimate of the maximum interconnection length Lp on any one plane of the MLC chip of area A is given by [62] pﬃﬃﬃ Lp ¼ 12 A ð3:9:3Þ Assuming that all planes of the MLC chip are equal in area, each plane can have interconnections of maximum length given by Eq. (3.9.3). If f is the number of planes that have interconnection lines to be driven by the same device, then the effective total length of the interconnection is given by Ltot, where Ltot ¼ fLp

1f p

ð3:9:4Þ

Combining Eqs. (3.9.1)–(3.9.4), an estimate of the maximum interconnection delay for the MLC chip is given by m n tp ¼ rp cL2tot ¼ rp cf 2 L2p ¼ 14rp cf 2 A ¼ 14rp cf 2 k ð3:9:5Þ p

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INTERCONNECTION DELAYS

TABLE 3.9.1

Thin-Film Resistivities of Interconnection Materials Thin-Film Resistivity (m cm)

Material Aluminum Refractory metals Silicides Polysilicon

2 5–10 15–100 1000

r 1.0 2.5–5 7.5–50 500

Source: From [68]. # 1986 IEEE.

On the other hand, the time constant for the corresponding single-plane chip (p ¼ 1) is given by t1 ¼ 14r1 ckðnÞm1

ð3:9:6Þ

where r1 and m1 are the thin-ﬁlm resistivity of the interconnection material and the interconnection complexity factor for the single-plane chip. Then, assuming that the capacitance per unit area c is the same for the single-plane and MLC chips, the ratio Rr of the maximum interconnection delay on the MLC chip to that on the singleplane chip becomes Rr ¼

m tp f 2 ðn=pÞ rp ¼ ¼ rf 2 ðpÞm ðnÞmm1 t1 ðnÞm1 r1

ð3:9:7Þ

where r ¼ rp =r1 . Assuming that the single-plane chip uses aluminum interconnections, the thin-ﬁlm resistivities [63] and the corresponding r values for aluminum, refractory metals, silicides, and polysilicon are listed in Table 3.9.1. 3.9.2

Simulation Results and Discussion

The dependences of the normalized interconnection delays on the interconnection complexity factor for several values of the number of circuit planes keeping r ¼ 1 and f ¼ 1 are shown in Fig. 3.9.2. The normalized interconnection delays as functions of the circuit size for several values of the interconnection complexity factor keeping r ¼ 3, f ¼ 1, m1 ¼ 1:2, and p ¼ 4 are shown in Fig. 3.9.3. Based on the discussion of MLC circuits presented in this section and from the results presented in Figs. 3.9.2 and 3.9.3, the following comments can be made: 1. Partitioning of the IC into virtually independent subcircuits fabricated on separate planes reduces the lengths of interconnection lines on any one plane, thereby reducing the interconnection delays. 2. When the availability of the third dimension in an MLC circuit permits the reduction of interconnection complexity factor m compared to m1 for a single-plane chip, the area per plane is reduced by a factor of pm nmm1 with a proportional reduction in the normalized interconnection delay Rr.

INTERCONNECTION DELAYS IN MULTILAYER INTEGRATED CIRCUITS

229

FIGURE 3.9.2 Dependences of normalized interconnection delays on interconnection complexity factor for several values of number of circuit planes. Fixed parameters: r ¼ 1 and f ¼ 1. (From [68]. # 1986 by IEEE.)

3. An important factor in maximizing the speed of an MLC is partitioning the original IC such that a device on a given plane drives a maximum-length interconnection on one plane only. This will minimize f and hence Rr because Rr / f 2 . 4. The assumptions made in the above analysis can be considered extrapolations of the best-case MLC technology. If these assumptions are modiﬁed to account for more realistic MLCs, the resulting interconnection delay will increase.

FIGURE 3.9.3 Dependences of normalized interconnection delays on circuit size for several values of interconnection complexity factor. Fixed parameters: r ¼ 3, f ¼ 1, m1 ¼ 1:2, and p ¼ 4. (from [68]. # 1986 by IEEE.)

230

3.10

INTERCONNECTION DELAYS

ACTIVE INTERCONNECTIONS

It has been known for some time that transistors can be scaled down in size in such a way that the device propagation delay decreases in direct proportion to the device dimensions. However, if the interconnections are scaled down, it results in RC delays that begin to dominate the IC chip performance at submicrometer dimensions. In other words, for the high-density, high-speed submicrometer geometry chips, it is mostly the interconnection rather than the device performance that determines the chip performance. So far, the interconnection delays have been reduced by using higher conductivity materials such as replacing aluminum with copper to lower the interconnection resistance, replacing silicon dioxide with a lowdielectric-constant material to lower the interconnection capacitance, and keeping the interconnection thickness almost constant irrespective of the scaling of devices. For example, in scaling from the 10- to the 1-mm design rules, the interconnection thicknesses were reduced by a factor of 2 or less. Now, because of the limitations of the optical lithography systems, it is essential that other approaches be developed to lower the interconnection delays. One way of solving this problem is to replace the passive interconnections on a chip by the active interconnections, that is, by inserting inverters or ‘‘repeaters’’ at appropriate spacings depending on the preferred driving mechanism. However, this technique does require more area on the chip and results in higher power consumption. In the literature [69, 70], several methods have been discussed for the reduction of transit delays in an interconnection. These include driving the interconnection using minimum-size inverters, optimum-size inverters, and cascaded inverters. An analysis of these driving methods for the silicon-based ICs is presented in [69]. In this section, these methods have been examined for the GaAs-based ICs [70]. Propagation times (time taken by the output signal to go from 0 to 90% of its steadystate value) have been calculated for each of these three methods for several interconnection dimensions and have been compared with each other and with the case when the interconnection is driven by a single typical GaAs MESFET. Results are given for two interconnection materials: aluminum with resistivity ðrÞ ¼ 3 m cm and WSi2 with r ¼ 30 m cm. 3.10.1

Interconnection Delay Model

An interconnection having total resistance Ri and capacitance Ci driven by a transistor of resistance Rs and driving a load capacitance CL is shown in Fig. 3.10.1. Assuming a unit step voltage source, the propagation times in distributed and lumped RC networks can be approximated as 1.0RC and 2:3RC, respectively [71]. Therefore, an approximate expression for the total delay in the interconnection shown in Fig. 3.10.1 will be T90% ¼ 1:0Ri Ci þ 2:3ðRs CL þ Rs Ci þ Ri CL Þ

ð3:10:1Þ

Ignoring the terms containing the load capacitance CL , we have T90% Ri Ci þ 2:3Rs Ci

ð3:10:2Þ

ACTIVE INTERCONNECTIONS

231

FIGURE 3.10.1 Interconnection delay model. (From [69]. # 1985 by IEEE.)

This expression is in agreement with that derived by Sakurai [72]. Since both interconnection resistance and capacitance increase linearly with length, the propagation time expressed by Eq. (3.10.2) will increase nearly as the square of the interconnection length. It can be shown that this dependence can be made linear if the entire interconnection length is divided into smaller sections and each section is driven by a repeater. 3.10.2

Active Interconnection Driven by Minimum-Size Inverters

A schematic of an active interconnection driven by minimum-size inverters as repeaters is shown in Fig. 3.10.2. As shown in the ﬁgure, the use of inverters divides the interconnection into smaller subsections. The symbols used in the ﬁgure are: Ri ¼ total resistance of interconnection line Ci ¼ total capacitance of interconnection line Rr ¼ output resistance of minimum-size inverter Cr ¼ input capacitance of minimum-size inverter

FIGURE 3.10.2 Schematic of interconnection driven by minimum-size inverters. (From [69]. # 1985 by IEEE.)

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INTERCONNECTION DELAYS

Rs ¼ resistance of GaAs MESFET CL ¼ load capacitance n ¼ number of inverters To achieve the shortest total propagation time using minimum-size inverters, the optimum number of inverters can be found using calculus to be [69] rﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ Ri C i n¼ 2:3Rr Cr

ð3:10:3Þ

The propagation time for each subsection driven by the minimum-size inverters can be determined using the algorithm presented in Section 3.2, whereas the additional delay caused by the ﬁrst stage can be found by the approximate expression for lumped RC networks given by Wilnai [71] to be 2:3Rs Cr . The computer program IPDMSR for determining the propagation time in an active interconnection driven by minimum-size repeaters is given in Appendix 3.2 on the accompanying ftp site. The results using aluminum as the interconnection material are listed in Tables 3.10.1 and 3.10.2 whereas those using WSi2 as the interconnection material are listed in Tables 3.10.3 and 3.10.4. 3.10.3

Active Interconnection Driven by Optimum-Size Inverters

Propagation times can be improved by increasing the size of the inverters by a factor of k, where k is given by [69] k¼

rﬃﬃﬃﬃﬃﬃﬃﬃﬃ Rr Ci Ri Cr

ð3:10:4Þ

TABLE 3.10.1 Propagation Times in Four Driving Methods for Selected Interconnection Lengths Interconnection Length 1 mm 2 mm 5 mm 1 cm 2 cm 5 cm 10 cm

GaAs MESFET (ns) 0.05 0.08 0.17 0.33 0.80 3.5 15.1

Minimum-Size Repeaters (ns)

Optimum-Size Repeaters (ns)

—a —a 2.31 4.16 7.87 18.98 37.51

—a —a 0.11 0.20 0.29 0.54 0.97

Cascaded Drivers (ns) 0.24 0.27 0.34 0.46 0.76 2.79 11.49

Note: Interconnection material aluminum (r ¼ 3 m cm). Interconnection width ¼ interconnection separation ¼ 1 mm; load ¼ 100 fF; source resistance ¼ 700 . a

For interconnect lengths below 2 mm, method was found unsuitable because number of repeaters as given by equation for n was less than 1.

233

ACTIVE INTERCONNECTIONS

TABLE 3.10.2 Propagation Times in Four Driving Methods for Selected Interconnection Widths Interconnection Width (mm) 0.1 0.2 0.5 1.0 2.0 5.0 10.0

GaAs MESFET (ns) 0.98 0.50 0.39 0.33 0.31 0.25 0.27

Minimum-Size Repeaters (ns) 3.01 3.10 3.56 4.03 4.5 —a —a

Optimum-Size Repeaters (ns)

Cascaded Drivers (ns)

0.04 0.08 0.15 0.20 0.35 —a —a

0.85 0.52 0.38 0.46 0.70 1.38 2.39

Note: Interconnection material aluminum (r ¼ 3 m cm). Interconnection length ¼ 1 cm; load ¼ 100 fF; source resistance ¼ 700 . a For interconnect widths above 5.0 mm, method was found unsuitable because number of repeaters as given by equation for n was less than 1.

This is because the current driving capability of the inverter is directly proportional to its width–length ratio. When this ratio is increased by a factor of k, the output resistance of the inverter becomes Rr =k and the input capacitance of the inverter becomes kCr . A schematic of an active interconnection driven by optimum-size inverters is shown in Fig. 3.10.3. In this case, the additional delay caused by the ﬁrst stage will be approximately 2:3kRs Cr. The computer program IPDOSR for determining the propagation time in an active interconnection driven by optimum-size repeaters is given in Appendix 3.3 on the accompanying ftp site. The total propagation times for this case are also listed in Tables 3.10.1–3.10.4.

TABLE 3.10.3 Propagation Times in Four Driving Methods for Selected Interconnection Lengths Interconnection Length 1 mm 2 mm 5 mm 1 cm 2 cm 5 cm 10 cm

GaAs MESFET (ns) 0.07 0.14 0.41 1.35 4.62 9.6 19.98

Minimum-Size Repeaters (ns)

Optimum-Size Repeaters (ns)

Cascaded Drivers (ns)

—a 1.11 2.14 3.85 7.28 17.55 34.69

—a 0.13 0.23 0.39 0.71 1.67 3.26

0.27 0.34 0.62 1.42 4.49 22.3 80.28

Note: Interconnection material WSi2 (r ¼ 30 m cm). Interconnection width ¼ interconnection separation ¼ 1 mm; load ¼ 100 fF; source resistance ¼ 700 . a

For interconnect lengths below 2 mm, method was found unsuitable because number of repeaters as given by equation for n was less than 1.

234

INTERCONNECTION DELAYS

TABLE 3.10.4 Propagation Times in Four Driving Methods for Selected Interconnection Widths Interconnection Length (mm) 0.1 0.2 0.5 1.0 2.0 5.0 10.0

GaAs MESFET (ns)

Minimum-Size Repeaters (ns)

Optimum-Size Repeaters (ns)

8.9 5.0 2.21 1.35 0.8 0.52 0.36

2.79 2.99 3.5 3.82 4.34 5.23 6.34a

0.05 0.09 0.38 0.39 0.42 0.56 0.82a

Cascaded Drivers (ns) 10.6 5.85 2.18 1.42 1.19 1.59 2.48

Note: Interconnection material WSi2 (r ¼ 30 m cm). Interconnection width ¼ interconnection separation ¼ 1 mm; load ¼ 100 fF; source resistance ¼ 700 . a For interconnect widths above 10 mm, method was found unsuitable because number of repeaters as given by equation for n was less than 1.

3.10.4

Active Interconnection Driven by Cascaded Inverters

A schematic of an active interconnection driven by cascaded inverters is shown in Fig. 3.10.4. In this case, instead of a single driver, a chain of inverters is used that increase in size until the last inverter is large enough to drive the interconnection. The optimal delay is obtained using a sequence of n inverters that increase gradually in size (each by a factor of 2.71828 over the previous one). The optimum value of n is given by [69] Ci n ¼ ln Cr

ð3:10:5Þ

FIGURE 3.10.3 Schematic of interconnection driven by optimum-size inverters. (From [69]. # 1985 by IEEE.)

ACTIVE INTERCONNECTIONS

235

FIGURE 3.10.4 Schematic of interconnection driven by cascaded drivers. (From [69]. # 1985 by IEEE.)

In this case, the additional delay caused by the ﬁrst stage and the ﬁrst n 1 inverters is given approximately by 2:3Rs Cr þ 2:3ð2:71828Þðn 1ÞRr Cr

ð3:10:6Þ

and the propagation time in the interconnection driven by the last inverter can be found using the algorithm presented in Section 3.2. The program IPDCR for determining the propagation time in an active interconnection driven by cascaded repeaters is given in Appendix 3.4 on the accompanying ftp site. The results for this case are listed in Tables 3.10.1–3.10.4. 3.10.5

Dependence of Propagation Time on Interconnection Driving Mechanism

A comparison of the propagation times for each of the four methods of driving an interconnection—that is, using a single GaAs MESFET, minimum-size inverters, optimum-size inverters, and cascaded inverters—for several values of the interconnection lengths in the range 1 mm–10 cm is shown in Table 3.10.1. For these results, the interconnection material is taken to be aluminum and the other parameters are shown in the table. This table shows that minimum- and optimumsize inverters cannot be used to drive interconnections of lengths 2 mm and below. Otherwise, among the four methods, using optimum-size inverters yields the lowest propagation times. For interconnection lengths of 1 and 2 mm, using a single GaAs MESFET results in lower propagation times than using cascaded inverters. Table 3.10.2 shows the propagation times for each of the four methods for several interconnection widths in the range 0.1–10.0 mm. This table shows that the methods of using minimum- and optimum-size inverters are not suitable for interconnection widths of 5 mm and above. Otherwise, for interconnection widths below about 1 mm, using optimum-size inverters results in the lowest propagation times among the four

236

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methods. For interconnection widths between 2 and 10 mm, using a single GaAs MESFET yields the lowest propagation times. When the interconnection material is changed to WSi2, propagation times for the four methods of driving an interconnection for several values of interconnection length and interconnection width are shown in the Tables 3.10.3 and 3.10.4, respectively. These tables show that, in this case, minimum- and optimum-size inverters cannot be used for interconnection lengths of 1 mm and below and for interconnection widths above 10 mm. Using optimum-size inverters is found to result in the lowest propagation times for all interconnection lengths (see Table 3.10.3) and for interconnection widths below 5 mm (see Table 3.10.4). For interconnection widths above 5 mm, driving the interconnection with a single GaAs MESFET results in the lowest propagation times. EXERCISES E3.1 List and discuss the desirable characteristics of a numerical model that make it more suitable for inclusion in a CAD tool. Review the techniques presented in this chapter from the point of view of their suitability for inclusion in a CAD tool. E3.2 Comment on the validity of the assumptions and approximations used in the analysis of crossing interconnections in Section 3.4. E3.3 Refering to Section 3.7, comment on the relative signiﬁcance of the highfrequency losses in an aluminum interconnection on GaAs in the following frequency ranges: (a) below 10 MHz; (b) 10 MHz–1 GHz; (c) 1–10 GHz; (d) 10– 100 GHz; and (e) above 100 GHz. E3.4 Show that for the shortest total propagation time using minimum-size inverters the optimum number of inverters is given by the expression (symbols are deﬁned in Section 3.10.2) rﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ Ri C i n¼ 2:3Rr Cr E3.5 Show that the value of k for optimum-size inverters is given by the expression (symbols deﬁned in Section 3.10.3) rﬃﬃﬃﬃﬃﬃﬃﬃﬃ Rr Ci k¼ Ri Cr E3.6 Show that the optimal delay is obtained by using a sequence of n inverters that increase gradually in size (each by a factor of 2.71828 over the previous one), where n is given by the expression (symbols deﬁned in Section 3.10.4) Ci n ¼ ln Cr

REFERENCES

237

REFERENCES 1. N. C. Cirillo, Jr. and J. K. Abrokwah, ‘‘8.5 Picosecond Ring Oscillator Gate Delay with Self-Aligned Gate Modulation-Doped nþ(Al,Ga)/As/GaAs FET’s,’’ IEEE Trans. Electron Devices, vol. ED-32, p. 2530, Nov. 1985. 2. N. J. Shah, S. S. Pei, C. W. Tu, and R. C. Tiberio, ‘‘Gate-Length Dependence of the Speed of SSI Circuits Using Submicrometer Selectively-Doped Heterostructure Transistor Technology,’’ IEEE Trans. Electron Devices, vol. ED-33, pp. 543–547, May 1986. 3. R. K. Jain, ‘‘Electro-Optic Sampling of High-Speed III-V Devices and ICs,’’ paper presented at the IEEE/Cornel Conference on High Speed Semiconductor Devices and Circuits, IEEE Cat. No. 87CH2526-2, pp. 22–25, 1987. 4. C. W. Ho, ‘‘Theory and Computer Aided Analysis of Lossless Transmission Lines,’’ IBM J. Res. Dev., vol. 17, pp. 249–255, 1973. 5. A. E. Ruehli, ‘‘Survey of Computer-Aided Electrical Analysis of Integrated Circuit Interconnections,’’ IBM J. Res. Dev., vol. 22, pp. 526–539, Nov. 1979. 6. A. J. Gruodis and C. S. Chang, ‘‘Coupled Lossy Transmission Line Characterization and Simulation,’’ IBM J. Res. Dev., vol. 25, pp. 25–41, Jan. 1981. 7. H. T. Youn et al., ‘‘Properties of Interconnections on Silicon, Sapphire and Semiinsulating Gallium Arsenide Substrates,’’ IEEE Trans. Electron Devices, vol. ED-29, pp. 439–444, Apr. 1982. 8. I. Chilo and T. Arnaud, ‘‘Coupling Effects in the Time Domain for an Interconnecting Bus in High Speed GaAs Logic Circuits,’’ IEEE Trans. Electron Devices, vol. ED-31, pp. 347–352, Mar. 1983. 9. V. K. Tripathi et al., ‘‘Accurate Computer Aided Analysis of Crosstalk in Single and Multilayered Interconnections for High Speed Digital Circuits,’’ Proc. 34th Electronic Components Conf., New Orleans, May 1984. 10. S. Seki and H. Hasegawa, ‘‘Analysis of Crosstalk in Very High-Speed LSI/VLSIs Using a Coupled Multi-Conductor Stripline Model,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-32, pp. 1715–1720, Dec. 1984. 11. H. Hasegawa and S. Seki, ‘‘Analysis of Interconnection Delay on Very High-Speed LSI/ VLSI Chips Using a MIS Microstrip Line Model,’’ IEEE Trans. Electron Devices, vol. ED-31, pp. 1954–1960, Dec. 1984. 12. F. Fukuoka et al., ‘‘Analysis of Multilayer Interconnection Lines for a High Speed Digital Integrated Circuit,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-33, pp. 527–532, June 1985. 13. V. K. Tripathi and J. B. Rettig, ‘‘A SPICE Model for Multiple Coupled Microstrips and Other Transmission Lines,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-33, no. 12, pp. 1513–1518, Dec. 1985. 14. V. K. Tripathi and R. J. Bucolo, ‘‘Analysis and Modelling of Multilevel Parallel and Crossing Interconnection Lines,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-34, no. 3, Mar. 1987. 15. A. R. Djordevic, T. K. Sarkar, and R. F. Harrington, ‘‘Analysis of Lossy Transmission Lines with Arbitrary Nonlinear Terminal Networks,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-34, pp. 660–666, June 1986.

238

INTERCONNECTION DELAYS

16. A. K. Goel, ‘‘Transit Times in the High-Density Interconnections on GaAs-Based VHSIC,’’ IEE Proc., vol. 135, pt. I, no. 5, pp. 129–135, Oct. 1988. 17. A. K. Goel and Y. R. Huang, ‘‘Efﬁcient Characterization of Multilevel Interconnections on the GaAs-Based VLSIC’s,’’ Microwave Opt. Tech. Lett., vol. 1, no. 7, pp. 252–257, 1988. 18. K. W. Goossen and R. B. Hammond, ‘‘Modeling of Picosecond Pulse Propagation in Microstrip Interconnections on Integrated Circuits,’’ IEEE Trans. Microwave Theory Tech., vol. 37, no. 3, pp. 469–478, Mar. 1989. 19. J. A. Davis and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Models—Part I: Single Line Transient, Time Delay and Overshoot Expressions,’’ IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2068–2077, Nov. 2000. 20. J. A. Davis and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Molels—Part II: Coupled Line Transient Expressions and Peak Crosstalk in Multivel Networks,’’ IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2078–2087, Nov. 2000. 21. R. Venkatesaran, J. Davis, and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Molels—Part III: Transients in Single and Coupled Lines with Capacitive Load Termination,’’ IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 1081–1093, Apr. 2003. 22. R. Venkatesan, J. A. Davis, and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Models—Part IV: Uniﬁed Models for Time Delay, Crosstalk and Repeater Insertion,’’ IEEE Trans. Electron Devices, vol. 50, pp. 1094–1102, Apr. 2003. 23. F. Y. Chang, ‘‘Transient Simulation of Nonuniform Coupled Lossy Transmission Lines Characterized with Frequency-Dependent Parameters—Part I: Waveform Relaxation Analysis,’’ IEEE Trans. Circuits Syst., vol. 39, pp. 585–603, Aug. 1992. 24. F. Y. Chang, ‘‘Transient Simulation of Nonuniform Coupled Lossy Transmission Lines Characterized with Frequency-Dependent Parameters—Part II: Discrete-Time Analysis,’’ IEEE Trans. Circuits Syst. I, vol. 39, pp. 907–927, Nov. 1992. 25. J. E. Bracken, V. Raghavan, and R. A. Rohrer, ‘‘Interconnect Simulation with Asymptotic Waveform Evaluation (AWE),’’ IEEE Trans. Circuits Syst. I, vol. 39, pp. 869–878, Nov. 1992. 26. L. M. Silveira, I. M. Elfadel, J. K. White, M. Chilukuri, and K. S. Kundert, ‘‘Efﬁcient Frequency-Domain Modeling and Circuit Simulation of Transmission Lines,’’ IEEE Trans. Comp. Packag. Manufact. Technol. B, vol. 17, pp. 505–513, Nov. 1994. 27. D. B. Kuznetsov and J. E. Schutt-Aine, ‘‘Optimal Transient Simulation of Transmission Lines,’’ IEEE Trans. Circuits Syst. I, vol. 43, pp. 110– 121, Feb. 1996. 28. J. S. Roychowdhury, A. R. Newton, and D. O. Pederson, ‘‘Algorithms for the Transient Simulation of Lossy Interconnect,’’ IEEE Trans. Computer Aided Design, vol. 13, pp. 96– 104, Jan. 1994. 29. Y. I. Ismail and E. G. Friedman, ‘‘Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits,’’ IEEE Trans. VLSI Syst., vol. 8, pp. 195–206, Apr. 2000. 30. Y. Cao, X. Huang, D. Sylvester, N. Chang, and C. Hu, ‘‘A New Analytical Delay and Noise Model for On-Chip RLC Interconnect,’’ Proc. IEDM, San Francisco, CA, 2000, pp. 823– 826.

REFERENCES

239

31. K. Banerjee and A. Mehrotra, ‘‘Accurate Analysis of On-Chip Inductance Effects and Implications for Optimal Repeater Insertion and Technology Scaling,’’ Proc. IEEE Symp. VLSI Circuits, Kyoto, Japan, 2001, pp. 195–198. 32. K. Banerjee and A. Mehrotra, ‘‘Accurate Analysis of On-Chip Effects Using a Novel Performance Optimization Methodology for Distributed RLC Interconnnects,’’ Proc. Design Automation Conf., Las Vegas, NV, 2001, pp. 798–803. 33. K. Banerjee and A. Mehrotra, ‘‘Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects,’’ IEEE Trans. Computer-Aided Design, vol. 21, pp. 904–915, Aug. 2002. 34. A. K. Goel and C. R. Li, ‘‘Microcomputer Simulation of Single-Level High-Density VLSI Interconnection Capacitances,’’ Proc. SCS Multiconf. on Modelling & Simulation on Microcomputers, San Diego, CA, 1988, pp. 132–137. 35. H. E. Kallman and R. E. Spencer, ‘‘Transient Response,’’ Proc. IRE, vol. 33, pp. 169–195, 1945. 36. K. S. Crump, ‘‘Numerical Inversion of Laplace Transforms Using a Fourier Series Approximation,’’ J. ACM, vol. 23, pp. 89–96, Jan. 1976. 37. R. M. Simon, M. T. Stroot, and G. H. Weiss, ‘‘Numerical Inversion of Laplace Transforms with Application to Percentage Labeled Mitoses Experiments,’’ Computer Biomed. Res., vol. 5, pp. 596–607, 1972. 38. C. W. Ho, ‘‘Theory and Computer Aided Analysis of Lossless Transmission Lines,’’ IBM J. Res. Dev., vol. 17, p. 249, 1973. 39. F. Y. Chang, ‘‘Transient Analysis of Lossless Coupled Transmission Lines in a Nonhomogeneous Dielectric Medium,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-18, pp. 616–626, Sept. 1970. 40. A. J. Gruodis and C. S. Chang, ‘‘Coupled Lossy Transmission Line Characterization and Simulation,’’ IBM J. Res. Dev., vol. 25, pp. 25–41, Jan. 1981. 41. J. E. Carroll and P. R. Rigg, ‘‘Matrix Theory for n-Line Microwave Coupler Design,’’ Proc. IEE, vol. 127, pt. H, pp. 309–314, Dec. 1980. 42. H. Lee, ‘‘Computational Methods for Quasi TEM Parameters of MIC Planar Structures’’, Ph.D. Thesis, Oregon State University, 1983. 43. V. K. Tripathi et al., ‘‘Accurate Computer Aided Analysis of Crosstalk in Single and Multilayered Interconnections for High Speed Digital Circuits,’’ Proc. 34th. Electronic Component Conf., New Orleans, May 1984. 44. P. L. Kuznetsov and R. L. Stratonovich, The Propagation of Electromagnetic Waves in Multiconductor Transmission Lines, Elmsford, NY: Pergamon, 1984. 45. H. Uchida, Fundamentals of Coupled Lines and Multiwire Antennas. Sendai: Sesaki Publishing, 1967. 46. V. K. Tripathi, ‘‘Asymmetric Coupled Transmission Lines in an Inhomogenous Medium,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-23, pp. 734–739, Sept. 1975. 47. Y. K. Chin, ‘‘Analysis and Applications of Multiple Coupled Line Structures in an Inhomogenous Medium,’’ Ph.D. Thesis, Oregon State University, 1982. 48. V. K. Tripathi, ‘‘On the Analysis of Symmetrical Three Line Microstrip Lines,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-25, pp. 726–729, Sept. 1977.

240

INTERCONNECTION DELAYS

49. K. W. Goossen and R. B. Hammond, ‘‘Modeling of Picosecond Pulse Propagation in Microstrip Interconnections on Integrated Circuits,’’ IEEE Trans. Microwave Theory Tech., vol. 37, no. 3, pp. 469–478, Mar. 1989. 50. D. G. Corr and J. B. Davies, ‘‘Computer Analysis of Fundamental and Higher Order Modes in Single and Coupled Microstrip,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-20, pp. 669–678, 1972. 51. M. V. Schneider, ‘‘Microstrip Lines for Microwave Integrated Circuits,’’ Bell Syst. Tech. J., vol. 48, p. 1421, 1969. 52. K. C. Gupta, R. Garg, and R. Chadha, Computer-Aided Design of Microwave Circuits, Dedham, MA: Artech House, 1981, p. 62. 53. E. Yamashita, K. Atsuki, and T. Ueda, ‘‘An Approximate Dispersion Formula of Microstrip Lines for Computer-Aided Design of Microwave Integrated Circuits,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-27, p. 1036, 1979. 54. R. A. Pucel, D. J. Masse and C. P. Hartwig, ‘‘Losses in Microstrip,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-16, p. 342, 1968. 55. J. D. Welch and H. J. Pratt, ‘‘Losses in Microstrip Transmission Systems for Integrated Microwave Circuits,’’ NEREM Rec., vol. 8, p. 100, 1966. 56. A. K. Goel and S. Weitemeyer, ‘‘Modeling of Very High-Frequency Effects in the VLSI Interconnections,’’ Microwave Opt. Tech. Lett., vol. 31, no. 3, pp. 229–233, Nov. 2001. 57. T. Sakurai, ‘‘Closed-Form Expressions for Interconnection Delay, Coupling and Crosstalk in VLSI’s,’’ IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 118–124, Jan. 1993. 58. T. Sakurai, ‘‘Approximation of Wiring Delay in MOSFET LSI,’’ IEEE J. Solid-State Circuits, vol. SC-18, no. 4, pp. 418–426, Aug. 1983. 59. W. C. Elmore, ‘‘The Transient Response of Damped Linear Networks with Particular Regard to Wideband Ampliﬁers,’’ J. Appl. Phys., vol. 19, pp. 55–63, Jan. 1948. 60. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI, Reading, MA: Addison-Wesley, 1990. 61. S. Kawamura et al., ‘‘Three-Dimensional CMOS IC’s Fabricated by Using Beam Recrystallization,’’ IEEE Electron Devices Lett., vol. EDL-4, p. 366, 1983. 62. S. Akiyama et al., ‘‘Multilayer CMOS Device Fabricated on Laser Recrystallized Silicon Islands,’’ IEDM Tech. Dig., p. 352, 1983. 63. Y. Akasaka et al., ‘‘Integrated MOS Devices in Double Active Layers,’’ Proc. Symp. VLSI Technol., p. 90, 1984. 64. M. Nakano, ‘‘3-D SOI/CMOS,’’ IEDM Tech. Dig., p. 792, 1984. 65. S. Kataoka, ‘‘An Attempt Towards an Artiﬁcial Retina: 3-D Technology for an Intelligent Image Sensor,’’ Proc. Int. Conf. Solid State Sensors and Actuators, p. 440, 1985. 66. K. Sugahara et al., ‘‘SOI/SOI/Bulk-Si Triple-Level Structure for Three-Dimensional Devices,’’ IEEE Electron Devices Lett., vol. EDL-7, p. 193, 1986. 67. D. A. Antoniadis, ‘‘Three-Dimensional Integrated Circuit Technology,’’ Proc. Materials Res. Soc. Meeting, Nov. 1983. 68. A. L. Robinson, L. A. Glasser, and D. A. Antoniadis, ‘‘A Simple Interconnect Delay Model for Multilayer Integrated Circuits,’’ Proc. IEEE VLSI Multilevel Interconnection Conf., pp. 267–273, 1986.

REFERENCES

241

69. H. B. Bokaglu and J. D. Meindl, ‘‘Optimal Interconnection Circuits for VLSI,’’ IEEE Trans. Electron Devices, vol. ED-32, no. 5, pp. 903–909, May 1985. 70. A. K. Goel, ‘‘Dependence of Interconnection Delays on Driving Mechanism for GaAsBased VLSI,’’ Elec. Lett., vol. 23, no. 20, pp. 1066–1067, Sept. 1987. 71. A. Wilnai, ‘‘Open-Ended RC Line Model Predicts MOSFET IC Response’’, EDN, pp. 53–54, Dec. 1971. 72. T. Sakurai, ‘‘Approximation of Wiring Delay in MOSFET LSI,’’ IEEE J. Solid State Circuits, vol. SC-18, pp. 418–426, Aug. 1983.

CHAPTER FOUR

Crosstalk Analysis Continuous advancements in the ﬁeld of very large scale integrated circuits (VLSICs) and very high speed integrated circuits (VHSICs) have resulted in smaller chip sizes, smaller device geometries, and millions of closely spaced interconnections in one or more levels that connect the various components on the chip. There are continuous customer demands for higher speeds in the areas of signal processing, high-speed computation, data links, and related instrumentation. Crosstalk among the interconnections in single as well as multilevel conﬁgurations has become a major problem in the development of the next-generation high-speed integrated circuits. In the literature, modeling and analysis of coupled interconnections have received considerable attention. Several authors have used multiconductor transmission line theory [1–7] and the analysis of coupled lossy transmission lines has also been reported [8–10]. Nonlinearity of the source and load networks has been addressed by several workers [6, 9, 11]. Plenty of effort has been made to get closed-form expressions for the signal waveforms on two or three coupled interconnections. For example, the analytical solutions valid for weak-coupling cases (because they ignore the second-degree coupling) are reported [10, 12, 13] and formulas for voltage transfer functions for a two-line system without the weak-coupling assumption are presented [14]. Closed-form solutions for a system of N lossless lines using cyclic boundary conditions are developed [15] and a general crosstalk analysis technique without making the weak coupling or cyclic boundary condition assumption is presented [16]. Crosstalk analysis of parallel multilevel interconnections on GaAsbased ICs is presented [17, 18], and an analysis of bilevel crossing interconnections has been carried out [19, 20]. Recently, attention has focused on developing compact models for the transient analysis of distributed RLC interconnections [21–24]. This chapter is organized as follows:

High-Speed VLSI Interconnections, Second Edition By Ashok K. Goel Copyright # 2007 John Wiley & Sons, Inc.

242

LUMPED-CAPACITANCE APPROXIMATION

243

Crosstalk among the neighboring interconnections is studied using a lumpedcapacitance approximation in Section 4.1. Crosstalk in very high-speed VLSICs is analyzed using a coupled multiconductor MIS microstripline model for the interconnections in Section 4.2. Single-level interconnections have been investigated by the frequency-domain modal analysis in Section 4.3. A transmission line model of crosstalk effects in single-, bi-, and trilevel highdensity interconnections on GaAs-based VHSICs is presented in Section 4.4. An analysis of crossing bilevel interconnections on GaAs-based ICs is presented in Section 4.5. Closed-form expressions for crosstalk waveforms using distributed RC and RLC interconnection models are presented in Section 4.6. Crosstalk effects in multiconductor buses in high-speed GaAs logic circuits are analyzed in Section 4.7.

4.1

LUMPED-CAPACITANCE APPROXIMATION

The lumped-capacitance model of two interconnections coupled by the capacitance Cc is shown in Fig. 4.1.1, where C denotes the ground capacitance of each interconnection. The ﬁrst interconnection is driven by the unit voltage source of resistance Rs on the left and terminated by the load capacitance CL on the right. The second interconnection is terminated by the resistance Rs on the left and the load capacitance CL on the right. Crosstalk voltage is deﬁned as the voltage V2 ðtÞ induced across the load CL on the second interconnection. It can be shown that the amplitude of the crosstalk voltage at time t is given by V2 ðtÞ ¼ 12½et=t1 et=t2

ð4:1:1Þ

FIGURE 4.1.1 Lumped-capacitance model of two interconnections coupled by capacitance Cc . (From [5]. # 1984 by IEEE.)

244

CROSSTALK ANALYSIS

where t1 ¼ RðC þ CL Þ

t2 ¼ Rð2Cc þ C þ CL Þ

ð4:1:2Þ

Using calculus, it can be shown that the maximum value of the crosstalk voltage is given by V2;max

1 nc 1 1 þ nc nc þ 1 1 þ nc ln exp ln ¼ exp 1 nc 1 nc 2 2nc 2nc ð4:1:3Þ

where the capacitance coupling coefﬁcient nc is given by nc ¼

Cc C þ Cc þ CL

ð4:1:4Þ

Based on the lumped-capacitance model, the dependences of the crosstalk voltage V2 on time in the range 0–500 ps for interconnections of widths and separation equal to 2 mm and lengths of 1 and 3 mm are shown in Fig. 4.1.2. Figure 4.1.2 also shows the dependence of the maximum crosstalk voltage on the coupling coefﬁcient nc in the range 0–1. It will be shown in the next section that the ‘‘lumped-capacitance’’ approximation becomes inadequate in high-speed circuits. In fact, it can be shown that this approximation is applicable for interconnections which are at least a few millimeters long and the circuit rise time is above 200–300 ps.

FIGURE 4.1.2 Crosstalk waveform and amplitude derived from lumped-capacitance approximation. (From [5]. # 1984 by IEEE.)

COUPLED MULTICONDUCTOR MIS MICROSTRIPLINE MODEL

4.2

245

COUPLED MULTICONDUCTOR MIS MICROSTRIPLINE MODEL OF SINGLE-LEVEL INTERCONNECTIONS

In this section, a system of parallel single-level interconnections is modeled as a coupled multiconductor MIS microstripline system having many conductors [5]. Interconnections are formed on a surface-passivated semiconductor substrate with a metallized back. This model is particularly suitable for situations where many closely spaced interconnections run parallel for a long time, such as in the semicustom gate array shown in Fig. 4.2.1. For simplicity, losses in the semiconductor substrate are ignored, making the model specially applicable to interconnections on semi-insulating GaAs or InP or silicon-on-sapphire substrates. 4.2.1

The Model

The MIS microstripline model for a system of n strip conductors is shown in Fig. 4.2.2a. To incorporate the boundary conditions existing on both sides of the stripline system, a periodic boundary condition is adopted where it is assumed that the same system of n stripline conductors is repeated indeﬁnitely, as shown in

FIGURE 4.2.1

Schematic of semicustom gate array. (From [5]. # 1984 by IEEE.)

246

CROSSTALK ANALYSIS

FIGURE 4.2.2 (a) Coupled multiconductor MIS microstripline model having n conductors. (b) Periodic boundary condition applied to model. (From [5]. # 1984 by IEEE.)

Fig. 4.2.2b. This periodic boundary condition is quite useful for providing a ﬁrstorder estimate of crosstalk without going into the speciﬁc layout design details. Now, on this n-conductor stripline system, there exist n quasi-TEM modes. Consider a mode, called the y mode, where the phase angle difference of voltage and current between two adjacent conductors is constant and equal to y. Possible values of y that satisfy the periodic boundary condition are given by y ¼ 0;

2p 2kp 2ðn 1Þp ;...; ;...; n n n

ð4:2:1Þ

Then the characteristic impedance Z0y and the phase velocity vy of the y mode are given by 1 vy Cy 1=2 Cy0 vy ¼ c 0 Cy

Z0y ¼

ð4:2:2aÞ ð4:2:2bÞ

where c0 is the velocity of light in a vacuum and Cy and cy0 are the static capacitances of the y mode per conductor per unit length with and without the dielectric loadings, respectively. The static mode capacitances can be found by the Green’s function method. The Green’s function on the strip plane (y ¼ 0 in Fig. 4.2.2b) for the y mode,

247

COUPLED MULTICONDUCTOR MIS MICROSTRIPLINE MODEL

denoted by Gy ðx; x0 Þ, is deﬁned as the potential at a point x on the strip plane when a unit charge with a phase factor of ejmy is placed at points x0 þ mp, where m ¼ 0; 1; 2; . . . ; 1 and p is the pitch in Fig. 4.2.2b. Yamashita et al. have determined Gy ðx; x0 Þ by making a Fourier transformation of the 2D Laplace equation and solving the resultant equation with respect to y, resulting in 1 X ejbm ðxx0 Þ pjbm j m¼1 e1 cothðb1 bm Þ þ e2 cothðb2 bm Þ ½e2 cothðb2 bm Þ½e0 þ e1 cothðb1 bm Þ þ e1 ½e1 þ e1 cothðb1 bm Þ

Gy ðx; x0 Þ ¼

ð4:2:3Þ where bm ¼

2mp þ y p

Then, the potential on the strip under consideration, denoted by V0, can be found from the charge density function ry ðxÞ for the y mode at point x on the strip conductor by solving the following equation numerically: V0 ¼

Z

a=2

a=2

Gy ðx; x0 Þry ðx0 Þ dx0

ð4:2:4Þ

Then, the static capacitance of the y mode per conductor will be given by Cy ¼

1 V0

Z

a=2 a=2

ry ðxÞ dx

ð4:2:5Þ

The voltage and current on the kth conductor can be expressed in terms of the normal modes deﬁned above by the equations X jðk1Þy jo½tðz=vy Þ jðk1Þy joðtþz=vy Þ Vk ðzÞ ¼ Ayf e e þ Ayr e e y

Ik ðzÞ ¼

X Ayf y

Z0y

ejðk1Þy e jo½tz=vy Þ

Ayr jðk1Þy joðtþz=vy Þ e e Z0y

ð4:2:6Þ

ð4:2:7Þ

where z denotes the position on the conductor, o is the angular frequency, and Ayf and Ayr are the amplitudes of the forward and backward voltage waves in the y mode. The mode wave amplitudes Ayf and Ayr can be determined using the known terminal conditions at both ends of each strip conductor. The values of voltage and current in the time domain can be found by an inverse Laplace transformation of the above equations.

248

CROSSTALK ANALYSIS

FIGURE 4.2.3 Calculated characteristic impedance Z0y of various modes. (From [5]. # 1984 by IEEE.)

4.2.2

Numerical Simulations

In the following results [5], unless otherwise speciﬁed, it is assumed that the interconnections are of width a ¼ 2 mm, the substrate is of thickness b2 ¼ 200 mm and relative permittivity e2 ¼ 12, and the insulator is of thickness b1 ¼ 1 mm and relative permittivity e1 ¼ 4. First, for the case of b1 ¼ 0 and b2 ¼ 1, the dependences of the characteristic impedance Z0y on the width-to-pitch ratio (a=p) for various values of y are shown in Fig. 4.2.3. It is interesting to note the high-impedance nature of the interconnection system even for a typical practical case when a ¼ 2 mm, p ¼ 4 mm, and b2 ¼ 200 mm. This is because of the relatively small value of a=b2 (which leads to a smaller value of the ground capacitance). For a system of 10 semi-inﬁnite interconnections with a unit step voltage applied to the input end of the ﬁrst interconnection and the input ends of other interconnections open circuited, the induced voltage Vi on the ith interconnection is plotted versus i in Fig. 4.2.4. It can be seen that the voltage applied to one line tends to have its effect over a long range. This is because of the small shielding effect of the metallized back plane, which in turn is due to a small value of the a=b2 ratio. For a system of ﬁve semi-inﬁnite interconnections, the dependence of the induced voltage at an adjacent strip on the interconnection spacing s ð¼ p aÞ is shown in Fig. 4.2.5. The long-range nature of the induced voltage can again be noted.

COUPLED MULTICONDUCTOR MIS MICROSTRIPLINE MODEL

249

FIGURE 4.2.4 Calculated crosstalk amplitude at ith interconnection for system of 10 semiinﬁnite interconnections. (From [5]. # 1984 by IEEE.)

For a system of ﬁve ﬁnite-length interconnections with the excitation and loading conditions shown in the inset of Fig. 4.2.6, the crosstalk voltage waveform across the load capacitance of interconnection 4 is shown in Fig. 4.2.6. The waveform shows an initial time delay (due to the propagation of wavefront) followed by ringing-type decaying oscillation superposed by ripplelike smaller oscillations. These small oscillations are caused by the velocity mismatches among the various modes involved. For the sake of comparison, the corresponding waveform calculated by the lumped-capacitance approximation (using the network shown in the inset) is also

FIGURE 4.2.5 Crosstalk amplitude at adjacent interconnection versus spacing for system of 5 semi-inﬁnite interconnections. (From [5]. # 1984 by IEEE.)

250

CROSSTALK ANALYSIS

FIGURE 4.2.6 Calculated step response waveforms. The dashed curve is the waveform using the lumped-capacitance approximation. (From [5]. # 1984 by IEEE.)

included in Fig. 4.2.6, which shows that, as stated earlier, this approximation is not adequate for high-speed circuits. Figure 4.2.7 shows the dependences of the amplitudes of the crosstalk waveforms on the interconnection lengths for two sets of terminal conditions shown in the insets. This ﬁgure shows that the presence of ﬂoating interconnections increases the crosstalk amplitude because it effectively increases mutual coupling by reducing the line capacitances. For a system of ﬁve ﬁnite-length interconnections, the crosstalk voltage waveforms for signal source resistance Rs of 5 k, 700 , and 10 are shown in

FIGURE 4.2.7 Crosstalk amplitude versus interconnection length for two systems of ﬁve interconnections with different terminal conditions. (From [5]. # 1984 by IEEE.)

COUPLED MULTICONDUCTOR MIS MICROSTRIPLINE MODEL

251

FIGURE 4.2.8 (a) Crosstalk waveforms for different values of signal source resistance Rs . (b) Crosstalk amplitude versus Rs . (From [5]. # 1984 by IEEE.)

Fig. 4.2.8a. The dependence of the maximum crosstalk voltage on the source resistance in the range 10–10,000 is shown in Fig. 4.2.8b. These ﬁgures show that the oscillations become more dominant and determine the crosstalk amplitude as the signal source resistance is reduced. As Rs is reduced down to a few tens of ohms, multiple reﬂections of the wavefront appear at the initial times, and the ﬁrst negative peak of this transient determines the amplitude of the crosstalk waveform. The result calculated using the lumped-capacitance approximation is also included in Fig. 4.2.8b, which shows that this approximation is valid when Rs is above 2– 3 k and the response is slow. 4.2.3

Crosstalk Reduction

The above results suggest that for reliable operation of very high speed VLSI circuits with sufﬁcient noise margins, it is very important to consider methods of reducing crosstalk. One method of reducing crosstalk is to reduce the substrate thickness in

252

CROSSTALK ANALYSIS

FIGURE 4.2.9 Crosstalk coupling coefﬁcient versus spacing for several values of substrate thickness. (From [5]. # 1984 by IEEE.)

order to provide a solid shielding ground plane in close vicinity to the interconnections. However, this method will be effective only if the substrate thickness is reduced below 10 mm. This is clear from Fig. 4.2.9, which shows the dependence of the crosstalk coupling coefﬁcient on spacing for several values of substrate thickness. Reducing substrate thickness below 10 mm may not be practically possible unless a new technology, such as silicon on insulator (SOI) is used. Crosstalk can also be reduced by providing shielding ground lines adjacent to the active interconnections. This is a very effective method, as shown by Fig. 4.2.10, which gives the dependences of the crosstalk voltage on spacing for two systems of ﬁve interconnections with and without the shielding ground lines between the

FIGURE 4.2.10 Effect of shielding lines on crosstalk. (From [5]. # 1984 by IEEE.)

FREQUENCY-DOMAIN MODAL ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

253

FIGURE 4.2.11 Waveforms at centers of adjacent line ðV2 Þ, shielding line ðVS Þ, and active line ðV3 Þ. (From [5]. # 1984 by IEEE.)

interconnections. The drawback of this method is that it signiﬁcantly reduces the wiring channel capacity, particularly when the availability of interconnection capacity is itself a big problem in the design of VLSI circuits. It is interesting to note that the potential on a narrow shielding line is not zero all along the line even if it is grounded on both ends. This is clear from Fig. 4.2.11, which shows the waveforms at the centers of the adjacent line, the shielding line, and the active line.

4.3

FREQUENCY-DOMAIN MODAL ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

In this section, a general technique for analyzing crosstalk in coupled single-level lossless interconnections [16] is presented. The analysis is carried out without

254

CROSSTALK ANALYSIS

FIGURE 4.3.1 Schematic of system of N coupled interconnection lines. (From [16]. # 1990 by IEEE.)

making the weak-coupling or cyclic boundary condition assumption. First, modal analysis has been done in the frequency domain to obtain the closedform expressions for the voltage and current transfer functions. Then the transfer function is expanded into its Taylor series and the inverse Fourier transformation is applied to the terms considered signiﬁcant depending on the accuracy desired in the solution. 4.3.1

General Technique

Consider the system of N interconnection lines shown in Fig. 4.3.1. Let ½C, ½L, and ½R denote the capacitance, inductance, and resistance matrices of the system. Further, let En ðtÞ, ZGn , and ZLn denote the input signal, the source impedance, and the load impedance for the nth line, where n ¼ 1; 2; . . . ; N. Let ‘ be the length of each interconnection line. We deﬁne the series impedance matrix ½Z and the parallel admittance matrix ½Y as ½Z ¼ ½R þ jo½L and ½Y ¼ jo½C. The N propagation modes that exist in a system of N conductors are deﬁned by N complex modal propagation constants gn ¼ an þ jobn , where n ¼ 1; 2; . . . ; N. Then elements of the voltage eigenvector matrix ½Sv are solutions of the eigenvalue equation ðg2 ½I þ ½Z½YÞ½Sv ¼ ½0

ð4:3:1Þ

and the current eigenvector matrix ½SI is given by ½SI ¼ ½Z1 ½Sv ½

ð4:3:2Þ

where ½I is the identity matrix and ½ ¼ diagfg1 ; g2 ; . . . ; gn g. The characteristic impedance matrix ½Zc is given by ½Sv ½SI 1 and the characteristic admittance matrix ½Yc is equal to ½Zc 1 . Then the voltage and current vectors on the interconnection

FREQUENCY-DOMAIN MODAL ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

255

line can be expressed in terms of ½Sv and ½SI as ½VðxÞ ¼ ½Sv ð½Wi ðxÞ þ ½Wr ðxÞ

ð4:3:3Þ

½IðxÞ ¼ ½Yc ½Sv ð½Wi ðxÞ ½Wr ðxÞÞ

ð4:3:4Þ

where ½Wi ðxÞ ¼ ½Wi;n ð0Þðegn x Þ

½Wr ðxÞ ¼ ½Wr;n ð0Þðegn x Þ

ð4:3:4aÞ

and Wi;n and Wr;n are the amplitudes of the incident and reﬂected components of the nth mode. The voltage and current vectors satisfy the boundary conditions ½Vð0Þ ¼ ½E ½ZG ½Ið0Þ

½Vð‘Þ ¼ ½ZL ½Ið‘Þ

ð4:3:5Þ

where ½E ¼ ½En , ½ZG ¼ diagfZG1 ; ZG2 ; . . . ; ZGN g, ½ZL ¼ diagfZL1 ; ZL2 ; . . . ; ZLN g, En is the input voltage signal applied to the nth line, ZGn is the internal impedance of the nth input signal source, and ZLn is the load impedance of the nth line. Substituting Eqs. (4.3.3) and (4.3.4) into Eq. (4.3.5), we obtain the following linear equations for ½Wi ð0Þ and ½Wr ð0Þ: "

½Sv þ ½ZG ½SI

#"

½Sv ½ZG ½SI

ð½Sv ½ZL ½SI ½P ð½Sv þ ½ZL ½SI Þ½P1

½Wi ð0Þ ½Wr ð0Þ

#

" ¼

½E ½0

# ð4:3:6Þ

where ½P ¼ diagfexpðgnl Þg. After solving Eq. (4.3.6) for ½Wi ð0Þ and ½Wr ð0Þ, the voltage and current transfer functions can be determined from the voltage and current spectra obtained from Eq. (4.3.3). In general, ﬁrst, the voltage and current are calculated at a ﬁnite number of discrete frequencies and then the time-domain waveforms are obtained using the fast Fourier transform (FFT) technique. If the lines can be considered lossless and are terminated at one or both ends by the line characteristic impedances, then analytical inverse Fourier transformation can be used to obtain the closed-form expressions for the time-domain waveforms as shown below for two-, three-, and four-line systems. 4.3.2

Two-Line System

The capacitance and inductance matrices for a two-line system can be written as

C11 ½C ¼ C21

C12 C22

L11 ½L ¼ L21

L12 L22

ð4:3:7Þ

with C11 ¼ C22 , C12 ¼ C21 , L11 ¼ L22 , and L12 ¼ L21 . The propagation modes gn ¼ jobn ðn ¼ 1; 2Þ of the two modes can be obtained by solving Eqs. (4.3.1)

256

CROSSTALK ANALYSIS

and (4.3.2) to be g1 ¼ jo

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ðL11 þ L12 ÞðC11 C12 Þ

g2 ¼ jo

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ðL11 L12 ÞðC11 þ C12 Þ ð4:3:8Þ

Then, the voltage and current eigenvector matrices and the characteristic impedance matrix are given by 1 1 ½Sv ¼ 1 1 2 3 1 1 6 Z1 Z2 7 7 ½SI ¼ 6 ð4:3:9Þ 41 15 Z Z2 1 1 Z1 þ Z2 Z1 Z2 ½Zc ¼ 2 Z1 Z2 Z1 þ Z2 where

L11 þ L12 Z1 ¼ C11 C12

1=2

L11 L12 Z2 ¼ C11 þ C12

1=2 ð4:3:10Þ

Suppose that the load impedances of the two lines are the same, that is, ZL1 ¼ ZL2 ¼ ZL ; the source impedances of the two lines are the same, that is, ZG1 ¼ ZG2 ¼ ZG ; and the signal source E1 ðtÞ is applied to line 1. Then the voltage transfer functions can be obtained to be V1;2 ðx; oÞ 1 1 eg1 x þ rL1 eg1 ð2‘xÞ 1 eg2 x þ rL2 eg2 ð2‘xÞ ¼ E1 ðoÞ 2 P1 P2 1 rL1 rG1 e2g1 ‘ 1 rL2 rG2 e2g2 ‘ ð4:3:11Þ where rLn ¼

ZL Zn ZL þ Zn

n ¼ 1; 2

rGn ¼

ZG Zn ZG þ Zn

n ¼ 1; 2

and Pn ¼ 1 þ

ZG Zn

n ¼ 1; 2

ð4:3:12Þ

If the source impedances applied to the two interconnection lines are each equal to Zcc deﬁned as the characteristic impedance of an isolated line, that is, ZG Zcc ,

FREQUENCY-DOMAIN MODAL ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

257

then rGn 0 ðn ¼ 1; 2Þ and Eq. (4.3.11) becomes V1;2 ðx; oÞ 1 1 g1 x 1 g2 x g1 ð2‘xÞ g2 ð2‘xÞ ¼ ðe þ rL1 e Þ ðe þ rL2 e Þ ð4:3:13Þ E1 ðoÞ 2 P1 P2 Further, if the load impedances of the two lines are each equal to Zcc , then Eq. (4.3.13) still holds but with rLn 0 ðn ¼ 1; 2Þ. The closed-form expressions in the time domain can now be determined by the inverse Fourier transformations of the voltage transfer functions given by Eq. (4.3.13) to be 1 1 x 1 x E1 t E1 t 2 P1 v1 P2 v2 rL1 2‘ x rL2 2‘ x E1 t E1 t þ P1 P2 v1 v2

V1;2 ðx; tÞ ¼

ð4:3:14Þ

where vn ¼ jo=gn ¼ 1=bn ðn ¼ 1; 2Þ are the two propagation velocities. It is clear from Eq. (4.3.14) that one source of crosstalk noise is the mismatch between the propagation velocities of different modes. In addition, Eq. (4.3.13) indicates that the coupling of the active line with its neighbors degrades the input signal as it travels along the active line. 4.3.3

Three-Line System

Consider a system of three interconnection lines with matched loads having three propagation modes. If the matrix ½A denotes the product of the matrices ½L and ½C, that is, ½A ¼ ½L½C, then the propagation constants of the three modes will be given by g1 ¼ joðA11 A13 Þ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ0:5 1 g2 ¼ pﬃﬃﬃ jo A11 þ A13 þ A22 þ ðA11 þ A13 A22 Þ2 þ 8A12 A21 2 qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ0:5 1 g3 ¼ pﬃﬃﬃ jo A11 þ A13 þ A22 ðA11 þ A13 A22 Þ2 þ 8A12 A21 2

ð4:3:15Þ

and the voltage eigenvector matrix is given by 2

1 ½Sv ¼ 4 0 1

1 Z2 1

3 1 Z3 5 1

ð4:3:16Þ

258

CROSSTALK ANALYSIS

where Z2 ¼ Z3 ¼

ðA22 A11 A13 Þ þ

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ðA22 A11 A13 Þ2 þ 8A12 A21

2A12 ﬃ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ðA22 A11 A13 Þ ðA22 A11 A13 Þ2 þ 8A12 A21

ð4:3:17Þ

2A12

If the input signal E1 ðtÞ is applied to line 1 (the active line), source impedances are much smaller as compared to the line characteristic impedances Zcc , that is, ZGn ¼ 0, and if the load impedances are each equal to Zcc , that is, ZLn ¼ Zcc ðn ¼ 1; 2; 3Þ, then the closed-form expressions for the line voltage waveforms can be determined by following the same steps as for the two-line system to be 1 x Z3 x Z2 x þ E1 t E1 t V1 ðx; tÞ ¼ E1 t Z2 Z3 Z2 Z3 2 v1 v2 v3 1 Z2 Z3 x x E1 t þ E1 t V2 ðx; tÞ ¼ 2 Z2 Z3 v2 v3 1 x Z3 x Z2 x þ E1 t E1 t V3 ðx; tÞ ¼ E1 t 2 v1 v2 v3 Z2 Z3 Z2 Z3 ð4:3:18Þ 4.3.4

Four-Line System

Consider a system of four interconnection lines with matched loads having four propagation modes. If the matrix ½A denotes the product of the matrices ½L and ½C, that is, ½A ¼ ½L½C, then the propagation constants of the four modes will be given by jo g1 ¼ pﬃﬃﬃ ðA11 þ A14 þ A22 þ A23 Þ 2 qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ0:5 þ ðA11 þ A14 A22 A23 Þ2 þ 4ðA12 þ A13 ÞðA21 þ A31 Þ jo g2 ¼ pﬃﬃﬃ ðA11 þ A14 þ A22 þ A23 Þ 2 qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ0:5 ðA11 þ A14 A22 A23 Þ2 þ 4ðA12 þ A13 ÞðA21 þ A31 Þ ð4:3:19Þ jo g3 ¼ pﬃﬃﬃ ðA11 þ A14 þ A22 A23 Þ 2 qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ0:5 þ ðA11 A14 A22 þ A23 Þ2 þ 4ðA12 A13 ÞðA21 A31 Þ jo g4 ¼ pﬃﬃﬃ ðA11 þ A14 þ A22 A23 Þ 2 qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ0:5 ðA11 A14 A22 þ A23 Þ2 þ 4ðA12 A13 ÞðA21 A31 Þ

FREQUENCY-DOMAIN MODAL ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

259

and the voltage eigenvector is given by 2

1 6 Z1 ½Sv ¼ 6 4 Z1 1

1 Z2 Z2 1

1 Z3 Z3 1

3 1 Z4 7 7 Z4 5 1

ð4:3:20Þ

where Z1 ¼ ðA11 A14 þ A22 þ A23 Þ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ðA11 þ A14 A22 A23 Þ2 þ 4ðA12 þ A13 ÞðA21 þ A31Þ þ 2ðA12 þ A13 Þ Z2 ¼ ðA11 A14 þ A22 þ A23 Þ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ðA11 þ A14 A22 A23 Þ2 þ 4ðA12 þ A13 ÞðA21 þ A31 Þ 2ðA12 þ A13 Þ

ð4:3:21Þ

Z3 ¼ ðA11 þ A14 þ A22 A23 Þ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ðA11 A14 A22 þ A23 Þ2 þ 4ðA12 A13 ÞðA21 A31 Þ þ 2ðA12 A13 Þ Z4 ¼ ðA11 þ A14 þ A22 A23 Þ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ðA11 A14 A22 þ A23 Þ2 þ 4ðA12 A13 ÞðA21 A31 Þ 2ðA12 A13 Þ If the input signal E1 ðtÞ is applied to line 1 (the active line), source impedances are much smaller as compared to the line characteristic impedances Zcc , that is, ZGn ¼ 0, and if the load impedances are each equal to Zcc , that is, ZLn ¼ Zcc ðn ¼ 1; 2; 3; 4Þ, then the closed-form expressions for the line voltage waveforms can be determined by following the same steps as for the two-line system to be 1 x x x x V1 ðx; tÞ ¼ a2 E1 t þ a1 E1 t a4 E1 t þ a3 E1 t 2 v1 v2 v3 v4 1 x x x x þ E1 t þ b2 E1 t þ E1 t V2 ðx; tÞ ¼ b1 E1 t 2 v1 v2 v3 v4 1 x x x x V3 ðx; tÞ ¼ b1 E1 t þ E1 t b2 E1 t þ E1 t 2 v1 v2 v3 v4 1 x x x x V4 ðx; tÞ ¼ a2 E1 t þ a1 E1 t þ a4 E1 t a3 E1 t 2 v1 v2 v3 v4 ð4:3:22Þ

260

CROSSTALK ANALYSIS

where vn ¼ a1 ¼

Z1 Z1 Z2

a2 ¼

jo gn

Z2 Z1 Z2

n ¼ 1; 2; 3; 4 a3 ¼

Z3 Z3 Z4

b1 ¼ a1 Z2 ¼ a2 Z1

4.3.5

a4 ¼

Z4 Z3 Z4

ð4:3:23Þ

b2 ¼ a3 Z4 ¼ a4 Z3

Simulation Results

A schematic of the coupled interconnections in high-speed circuits and systems is shown in Fig. 4.3.1 and the layout of the N uniformly coupled 50- interconnections used in the simulations given below [16] is shown in Fig. 4.3.2. Referring to Fig. 4.3.1, we have set ZGn ¼ 0 and ZLn ¼ 50 , where n ¼ 1; 2; . . . ; N. In Fig. 4.3.2, unless otherwise stated, the interconnections are assumed to be of negligible thickness, the substrate is aluminum with permittivity er ¼ 10, the width of each interconnection ðWÞ is equal to the substrate thickness ðHÞ, the distance between any two adjacent conductors ðSÞ is 1.5 H, the length of each coupled line is 20 cm, and a ramp signal having amplitude of 1 V and rise time of 100 ps is applied to line 1 (the active line). For a system of two interconnection lines, the time-domain voltage waveforms at the load ends of the active line and the neighboring line determined by Eq. (4.3.14) are shown in Fig. 4.3.3. The capacitance and inductance matrices used in these results were determined by the Green’s function method and are

1:737 0:073 ½C ¼ 0:073 1:737 4:276 0:529 ½L ¼ 0:529 4:276

pF=cm

nH=cm

FIGURE 4.3.2 Layout of N uniformly coupled 50- interconnections on aluminum substrate. (From [16]. # 1990 by IEEE.)

FREQUENCY-DOMAIN MODAL ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

261

FIGURE 4.3.3 Signal waveforms at load ends for two-line system in Fig. 4.3.2 with N ¼ 2. (From [16]. # 1990 by IEEE.)

For the sake of comparison, Fig. 4.3.3 also shows the analysis results from [12], where weak coupling was assumed. It is clear that the weak-coupling approximation can result in signiﬁcant errors in crosstalk calculations. For the two-line system, the amplitude of the coupling noise at the load end as a function of the layout parameter S=W is plotted in Figure 4.3.4. Fig. 4.3.5 shows the inﬂuences of the length of the coupled lines and the rise time of the input signal on the amplitude of the coupling noise. For a system of three interconnection lines, the time-domain voltage waveforms at the load ends of the active line and the neighboring lines determined by Eq. (4.3.18) are shown in Fig. 4.3.6. The capacitance and inductance

FIGURE 4.3.4 Amplitude of load-end coupling noise as function of layout parameter S=W for two-line system in Fig. 4.3.2 with N ¼ 2. (From [16]. # 1990 by IEEE.)

262

CROSSTALK ANALYSIS

FIGURE 4.3.5 Dependences of peak coupling noise on length (‘) of coupled lines of two-line system for different values of rise time ðTr Þ of signal source. (From [16]. # 1990 by IEEE.)

FIGURE 4.3.6 Signal waveforms at load ends for three-line system in Fig. 4.3.2 with N ¼ 3. (From [16]. # 1990 by IEEE.)

FREQUENCY-DOMAIN MODAL ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS

263

matrices used in these results were determined by the Green’s function method and are 3 2 1:737 0:073 0:005 7 6 pF=cm ½C ¼ 4 0:073 1:741 0:073 5 0:005 0:073 1:737 2 3 4:276 0:527 0:159 6 7 ½L ¼ 4 0:527 4:269 0:527 5 nH=cm 0:159 0:527 4:276 The results assuming weak coupling from [12] are also included in Fig. 4.3.6 and indicate that this approximation is not satisfactory for typical interconnection conﬁgurations. For a system of four interconnection lines, the time-domain voltage waveforms at the load ends of the active line and the disturbed lines determined by Eq. (4.3.22) are shown in Fig. 4.3.7. The capacitance and inductance matrices used in these results were determined by the Green’s function method and are 2

3

1:737

0:073

0:004 0:002

6 0:073 6 ½C ¼ 6 4 0:004

1:742 0:073

0:073 0:004 7 7 7 1:742 0:073 5

0:002

0:004

0:073

2

pF=cm

1:737 3

4:276 6 0:527 6 ½L ¼ 6 4 0:158

0:527

0:158

0:072

4:269 0:526

0:526 4:269

0:158 7 7 7 0:527 5

0:072

0:158

0:527

4:276

nH=cm

FIGURE 4.3.7 Signal waveforms at load ends for four-line system in Fig. 4.3.2 with N ¼ 4. (From [16]. # 1990 by IEEE.)

264

CROSSTALK ANALYSIS

FIGURE 4.3.8 Load waveforms for signal–signal (S–S), signal–ground–signal (S–G–S) and ground–signal–ground–signal–ground (G–S–G–S–G) conﬁgurations. (From [16]. # 1990 by IEEE.)

The reduction of crosstalk by placing grounded conductors between the signal lines is demonstrated in Fig. 4.3.8, which shows the load voltage waveforms on line 2 when a ramp signal having amplitude of 1 V and rise time of 80 ps is applied to line 1 for the cases of two signal lines only (S–S), two signal lines with a grounded shield conductor in between (S–G–S), and two signal lines with grounded shield conductors in between as well as on both sides (G–S–G–S–G). It is clear from the simulation results that the grounded conductors should be placed on both sides of each signal line to signiﬁcantly reduce crosstalk. However, it should be noted that the insertion of ground conductors not only increases the complexity of the circuit but also causes waveform distortion for the signal on the active line.

4.4

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

In this section, the crosstalk among the parallel multilevel interconnections including the single-, bi-, and trilevel conﬁgurations is studied by modeling the interconnections as transmission lines. The model has been utilized to study the dependences of crosstalk voltage on interconnection parameters such as length, width, separation, interlevel distance, driving transistor resistance, and load capacitance. 4.4.1

The Model

As shown in Fig. 4.4.1, the interconnection line can be modeled as a transmission line driven by a unit step voltage source having resistance Rs , loaded by the capacitance CL , and coupled to the neighboring interconnection lines by the mutual capacitances and inductances (not shown in the ﬁgure). The resistance Rs is determined by the dimensions of the driving transistor and the capacitance CL is determined by the parasitic capacitances of the transistor loading the interconnection line. For the interconnection lines printed on or embedded in the semi-insulating

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

265

FIGURE 4.4.1 Interconnection driven by unit step voltage source Vs of resistance Rs and terminated by load capacitance CL . The terminal endings on the neighboring interconnections are also shown. Interconnection capacitances as well as capacitive and inductive couplings between interconnections not shown.

GaAs substrate, quasi-TEM is the dominant mode of wave propagation and the transmission line equations are given as @ @ Vðx; tÞ ¼ R þ L Iðx; tÞ @x @t @ @ Iðx; tÞ ¼ G þ C Vðx; tÞ @x @t

ð4:4:1Þ ð4:4:2Þ

where L and C are the inductance and capacitance matrices per unit length of the interconnections, R is determined by the resistance per unit length of the interconnections, and G is the conductance matrix determined by the conductivity of the substrate. For semi-insulating GaAs substrate, G can be neglected. The matrices L and C can be determined by the network analog method developed in Chapter 2. In the s domain, Eqs. (4.4.1) and (4.4.2) can be written as d Vðx; sÞ ¼ ½R þ sLIðx; sÞ dx d Iðx; sÞ ¼ ½G þ sCVðx; sÞ dx

ð4:4:3Þ ð4:4:4Þ

Deﬁning Z ¼ R þ sL

Y ¼ G þ sC

Eqs. (4.4.3) and (4.4.4) can be solved in the s domain, yielding pﬃﬃﬃﬃ pﬃﬃﬃﬃ Vðx; sÞ ¼ e ZY ðxÞ Vi ðsÞ þ e ZY ð‘xÞ Vr ðsÞ rﬃﬃﬃﬃ pﬃﬃﬃﬃ Y pﬃﬃﬃﬃ Iðx; sÞ ¼ ½e ZY ðxÞ Vi ðsÞ e ZY ð‘xÞ Vr ðsÞ Z

ð4:4:5Þ ð4:4:6Þ

266

CROSSTALK ANALYSIS

In Eqs. (4.4.5) and (4.4.6), ‘ is the total length of the transmission line, Vi ðsÞ is the voltage vector of the incident wave at x ¼ 0, and Vr ðsÞ is that of the reﬂected wave at x ¼ ‘. At the end points x ¼ 0 and x ¼ ‘, Eqs. (4.4.5) and (4.4.6) yield pﬃﬃﬃﬃ Vð0; sÞ ¼ Vi ðsÞ þ e ZY ‘ Vr ðsÞ rﬃﬃﬃﬃ pﬃﬃﬃﬃ Y Ið0; sÞ ¼ ½Vi ðsÞ e ZY ‘ Vr ðsÞ Z pﬃﬃﬃﬃ ZY ‘ Vð‘; sÞ ¼ e Vi ðsÞ þ Vr ðsÞ rﬃﬃﬃﬃ Y pﬃﬃﬃﬃ Ið‘; sÞ ¼ ½e ZY ‘ Vi ðsÞ Vr ðsÞ Z

ð4:4:7Þ ð4:4:8Þ ð4:4:9Þ ð4:4:10Þ

Incorporating the boundary conditions determined by the lumped circuit elements connected to the interconnection line, that is, Vð0; sÞ ¼ Vs ðsÞ Rs Ið0; sÞ 1 Vð‘; sÞ ¼ Ið‘; sÞ sCL

ð4:4:11Þ ð4:4:12Þ

we have rﬃﬃﬃﬃ pﬃﬃﬃﬃ Y Vi ðsÞ þ e Vr ðsÞ ¼ ðRs Þ ½Vi ðsÞ e ZY ‘ Vr ðsÞ þ Vs ðsÞ Z rﬃﬃﬃﬃ pﬃﬃﬃﬃ pﬃﬃﬃﬃ 1 Y ZY ‘ Vi ðsÞ Vr ðsÞ ½e e ZY ‘ Vi ðsÞ þ Vr ðsÞ ¼ sCL Z pﬃﬃﬃﬃ ð ZY Þ‘

ð4:4:13Þ ð4:4:14Þ

which can be solved to yield, for Vi ðsÞ and Vr ðsÞ, 8 " " rﬃﬃﬃﬃ# rﬃﬃﬃﬃ#1 " rﬃﬃﬃﬃ# < Y pﬃﬃﬃﬃ 1 Y 1 Y ZY ‘ I Iþ Vr ðsÞ ¼ Vs ðsÞ 1 þ Rs ½e : Z sCL Z sCL Z rﬃﬃﬃﬃ# )1 Y 1 pﬃﬃﬃﬃ þ I Rs Z e ZY ‘ " #1 rﬃﬃﬃﬃ pﬃﬃﬃﬃ 1 Y pﬃﬃﬃﬃ 1 pﬃﬃﬃﬃ ZY ‘ ZY ‘ Vi ðsÞ ¼ e Iþ e ZY ‘ Vr ðsÞ e sCL Z sCL "

ð4:4:15Þ

ð4:4:16Þ

The values for Vi ðsÞ and Vr ðsÞ can be substituted in Eqs. (4.4.7)–(4.4.10) to obtain the expressions for current and voltage at x ¼ 0 and x ¼ ‘ in the s domain. The load voltage is the element of Vð‘; sÞ that corresponds to the line on which the voltage source is applied. The other elements of Vð‘; sÞ represent the crosstalk voltages induced on the neighboring interconnection lines.

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

267

In principle, the time-domain response can be obtained by inverse Laplace transformation or by Fourier transformation. However, Fourier transformation results in errors due to a ﬁnite number of terms included in the summation. Therefore, the inverse Laplace transformation technique is used. If FðsÞ denotes the Laplace transform of f ðtÞ, then Z 1 f ðtÞest dt ð4:4:17Þ FðsÞ ¼ 0

It can be shown [25] that, for t on the interval ð0; 2TÞ, f ðtÞ ¼ hðtÞ EðtÞ

ð4:4:18Þ

where hðtÞ is given by ( ) 1 1 FðaÞ X kpt kpt kpt kpt hðtÞ ¼ Re F aþ þ cos Im F aþ sin T 2 T T T T k¼1 ð4:4:19Þ and the error EðtÞ is bounded by EðtÞ M

eat

e2TðaaÞ 1

ð4:4:20Þ

where 1=T is the frequency step, M is a constant, and a is related to f ðtÞ such that f ðtÞ is an exponential of order a (i.e., jf ðtÞj Ceat ). When 2Tða aÞ is large enough and we want our precision to be e, then a can be chosen to be [25] a¼a

lnðeÞ 2T

ð4:4:21Þ

Choosing a suitable value of T for the desired accuracy depends on the time range of interest (e.g., 0; . . . ; tmax ) and the computation time. When t is much smaller than 2T, then the approximation of f ðtÞ by Eq. (4.4.19) converges very slowly because the frequency step determined by 1=T is too small and we need to include many terms for the summation to converge. On the other hand, if t is too close to 2T, then the error due to the term EðtÞ in Eq. (4.4.18) becomes large, as can be seen from Eq. (4.4.20). A good choice for T lies in the range ð0:8 tmax , 1:2 tmax Þ. Numerical computations show that if we apply inverse Laplace transformation directly, then the summation converges very slowly for small values of t. This is because the frequency step determined by 1=T is too small for small t. To solve this problem, we can divide the time range ½0; tmax into several time ranges ½0; pk tmax , ðpk tmax ; pk1 tmax ; . . . ; ðptmax ; tmax and choose a different value of T for each time range such that T is not too large and the summation in Eq. (4.4.19) converges faster.

268

CROSSTALK ANALYSIS

The value of p can be determined by a compromise between the desired accuracy and the computation time and is chosen to be 0.8. Summation in Eq. (4.4.19) usually converges very slowly; it takes more than 5000 terms to achieve an accuracy of four signiﬁcant digits. To overcome this problem, we can use the Wynn algorithm [25, 26] to accelerate the summation. The algorithm can be described as follows: For a summation series S deﬁned as S¼

m X

an

m ¼ 1; 2; 3; . . .

ð4:4:22Þ

n¼1

we deﬁne a 2D array as m em pþ1 ¼ ep1 þ

1 epm1 em p

p ¼ 1; 2; 3; . . .

ð4:4:23Þ

with em 0 ¼0

ð4:4:24Þ

em 1 ¼ Sm

ð4:4:25Þ

m m m In principle, em 3 ; e5 ; e7 ; e9 ; . . . will be better approximations for the summation Sm in Eq. (4.4.22). From numerical experiments, it can be found that em 9 is the best choice for the present problem because higher order transformations result in rounding errors.

4.4.2

The Program DCMPVI

The computer program DCMPVI is based on the inverse Laplace transformation technique using the Wynn algorithm and the improved time range selection described above and was written in FORTRAN. It is presented in Appendix 4.1 on the accompanying ftp site. The interconnection capacitances and inductances used in the program are determined using the network analog method presented in Chapter 2 and include the fringing ﬁelds as well as the effects of shielding by the neighboring interconnections. 4.4.3

Numerical Simulations Using DCMPVI

The program DCMPVI has been used to study the dependence of the crosstalk among the interconnections in the conﬁgurations shown in Figs. 4.4.2a–c. One of the parameters is varied in a speciﬁc range while the others are kept ﬁxed at their typical values, chosen to be as follows: interconnection length ‘ ¼ 1000 mm, interconnection width W ¼ 1 mm, interconnection separation S ¼ 1 mm, interconnection metal resistivity r ¼ 3 m cm, interlevel distances T12 and T23 are 2 mm, GaAs substrate thickness T ¼ 200 mm, driving transistor output resistance or

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

269

FIGURE 4.4.2 Schematic of (a) three single-level, (b) six bilevel, and (c) six trilevel interconnection conﬁgurations.

source resistance Rs ¼ 100 , and loading transistor input capacitance or load capacitance CL ¼ 100 fF. The thickness of each interconnection line is kept at 0.5W. In the following discussion, the single-level interconnection conﬁguration shown in Fig. 4.4.2a is assumed unless otherwise speciﬁed and the source is applied to one end of the second interconnection on the ﬁrst level. Magnitudes of the crosstalk voltages at the load on the ﬁrst or third interconnection as functions of time in the range 0–200 ps for several values of the interconnection length are shown in Fig. 4.4.3. Figure 4.4.4 shows the

270

CROSSTALK ANALYSIS

FIGURE 4.4.3 Crosstalk voltage waveforms in range 0–200 ps for several interconnection lengths for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.4 Dependence of maximum crosstalk voltage on interconnection length for single-level interconnections in Fig. 4.4.2a.

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

271

FIGURE 4.4.5 Crosstalk voltage waveforms in range 0–200 ps for several interconnection widths for single-level interconnections in Fig. 4.4.2a.

dependence of the maximum crosstalk voltage on the interconnection length in the range 20–1000 mm. It shows that crosstalk increases almost linearly with length in the range 20–1000 mm. This is because the capacitance coupling the interconnections increases almost linearly with length. For several interconnection widths, variations of the crosstalk voltages with time in the range 0–200 ps are shown in Fig. 4.4.5, and Fig. 4.4.6 shows that the maximum crosstalk voltage is almost a logarithmic function of the interconnection width in the range 0.5–5 mm. As functions of time in the range 0–200 ps, crosstalk voltages for several interconnection separations are shown in Fig. 4.4.7, and Fig. 4.4.8 shows the dependence of the maximum crosstalk voltage on the interconnection separation in the range 0.5–5 mm. This ﬁgure shows that for separation of 0.5 mm and typical values of the other parameters, the maximum crosstalk voltage is nearly 15% of the input signal, which may be too large to allow error-free operation of some ICs. Crosstalk voltages as a function of time in the range 0–200 ps for several values of the thickness of the GaAs substrate are shown in Fig. 4.4.9, and the dependence of maximum crosstalk voltage on substrate thickness in the range 5–200 mm is shown in Fig. 4.4.10. Crosstalk decreases somewhat with the decrease in the substrate thickness because of the increased shielding of the coupling ﬁeld lines by the ground plane. For various values of interconnection metal resistivity, variations of the crosstalk voltage on time in the range 0–500 ps

272

CROSSTALK ANALYSIS

FIGURE 4.4.6 Dependence of maximum crosstalk voltage on interconnection width for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.7 Crosstalk voltage waveforms in range 0–200 ps for several interconnection separations for single-level interconnections in Fig. 4.4.2a.

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

273

FIGURE 4.4.8 Dependence of maximum crosstalk voltage on interconnection separation for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.9 Crosstalk voltage waveforms in range 0–200 ps for several substrate thicknesses for single-level interconnections in Fig. 4.4.2a.

274

CROSSTALK ANALYSIS

FIGURE 4.4.10 Dependence of maximum crosstalk voltage on substrate thickness for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.11 Crosstalk voltage waveforms in range 0–500 ps for several interconnection metal resistivities for single-level interconnections in Fig. 4.4.2a.

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

275

FIGURE 4.4.12 Dependence of maximum crosstalk voltage on interconnection metal resistivity for single-level interconnections in Fig. 4.4.2a.

are shown in Fig. 4.4.11, and the dependence of maximum crosstalk voltage on resistivity in the range 0.1–200 m cm is shown in Fig. 4.4.12. It shows that the crosstalk decreases when the interconnection metal resistivity is increased. This is perhaps because increasing the interconnection resistance ﬁlters the highfrequency components from the input signal and their effect on the neighboring lines is reduced. For several values of source resistance, that is, the output resistance of the driving transistor, crosstalk voltages in the time range 0–200 ps are shown in Fig. 4.4.13, and Fig. 4.4.14 shows the dependence of maximum crosstalk voltage on source resistance in the range 0.1–1000 . The effect of increasing the source resistance on the crosstalk can be understood in the same way as that of the interconnection resistivity, that is, the RC ﬁltering effect on the input signal increases, thereby reducing the crosstalk voltage. Variations of the crosstalk voltage with time in the range 0–200 ps for several values of load capacitance, that is, the input capacitance of the loading transistor, are shown in Fig. 4.4.15, and Fig. 4.4.16 shows the dependence of maximum crosstalk voltage on load capacitance in the range 5–1000 fF. Figure 4.4.16 shows that crosstalk decreases rapidly with the increase of load capacitance. This is again due to increased ﬁltering of the high-frequency components on the source line, resulting in reduced induced voltages on the neighboring lines.

276

CROSSTALK ANALYSIS

FIGURE 4.4.13 Crosstalk voltage waveforms in range 0–200 ps for several source resistances for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.14 Dependence of maximum crosstalk voltage on source resistance for single-level interconnections in Fig. 4.4.2a.

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

277

FIGURE 4.4.15 Crosstalk voltage waveforms in range 0–200 ps for several load capacitances for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.16 Dependence of maximum crosstalk voltage on load capacitance for singlelevel interconnections in Fig. 4.4.2a.

278

CROSSTALK ANALYSIS

FIGURE 4.4.17 Crosstalk voltage waveforms in range 0–200 ps for three and ﬁve interconnections in single-level conﬁguration in Fig. 4.4.2a.

When the number of interconnection lines in the single-level conﬁguration of Fig. 4.4.2a is increased from 3 to 5, Fig. 4.4.17 shows that the crosstalk voltage at the load end of the ﬁrst-neighbor interconnections is reduced somewhat. This is due to the shielding effect of the second-neighbor lines. Crosstalk voltages induced at the load ends of the ﬁrst- and second-neighbor interconnections in the time range 0–200 ps are shown in Fig. 4.4.18. This ﬁgure shows that the crosstalk on the secondneighbor interconnections is much less than that on the ﬁrst-neighbor interconnections. This is because the coupling capacitance between the source line and the second-neighbor interconnection line is less than that for the ﬁrst-neighbor interconnection. The crosstalk can also be calculated for the bilevel interconnection conﬁguration shown in Fig. 4.4.2b, and the crosstalk voltages induced at the load ends of the ﬁrst, fourth, and ﬁfth interconnections in the time range 0–200 ps are shown in Fig. 4.4.19. It can be seen that the crosstalk on the ﬁfth interconnection is the largest while that on the fourth interconnection is the smallest. This is because the ﬁfth interconnection line is located just below the source interconnection, which results in the coupling capacitance being the largest while the coupling capacitance between the source interconnection and the fourth interconnection is the smallest due to the shielding effects of the ﬁrst and the ﬁfth interconnections. Comparison of these results with those for the single-level interconnections shows that the crosstalk voltage induced on the ﬁrst-neighbor interconnections in the bilevel conﬁguration is almost half of that in the single-level conﬁguration. For the trilevel interconnection

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS

279

FIGURE 4.4.18 Crosstalk voltage waveforms in range 0–200 ps at load ends of ﬁrst- and second-neighbor lines for ﬁve single-level interconnections.

FIGURE 4.4.19 Crosstalk voltage waveforms in range 0–200 ps for ﬁrst, fourth, and ﬁfth lines in the bilevel interconnection conﬁguration in Fig. 4.4.2b.

280

CROSSTALK ANALYSIS

FIGURE 4.4.20 Crosstalk voltage waveforms in range 0–200 ps for ﬁrst, fourth, and sixth lines in the trilevel interconnection conﬁguration in Fig. 4.4.2c.

conﬁguration, the crosstalk results are shown in Fig. 4.4.20 and can be understood in the same way as those for the bilevel interconnections.

4.5

ANALYSIS OF CROSSING INTERCONNECTIONS

In this section, the crosstalk signal induced in each crossing line embedded in the substrate due to the signal source applied to the main (driven) line printed on the top plane will be studied. Only the capacitive couplings will be considered in this analysis. 4.5.1

Mathematical Analysis

A schematic of the crossing interconnections analyzed in this section is shown in Fig. 4.5.1. A driving source is applied only on the main line on the top plane and the crossing lines in the second plane are not energized. As in the previous chapter, one way of analyzing this interconnection conﬁguration is to divide it into three sections called the transmission line section, the crossing section, and the load section with the difference that each of the two sections of every crossing line on either side of the point of coupling with the main line should be modeled as a transmission line. The

ANALYSIS OF CROSSING INTERCONNECTIONS

281

FIGURE 4.5.1 Schematic of bilevel crossing interconnections analyzed in this section. Each crossing line is also terminated by source resistance Rs on one side and load capacitance CL on the other (not shown).

equivalent circuit used for studying the crosstalk in the crossing interconnections is shown in Fig. 4.5.2. The elements are deﬁned as follows: Vs ¼ voltage source Rs ¼ source resistance LB ¼ self-inductance of portion of driven line between two consecutive crossing lines RB ¼ resistance of portion of driven line between two consecutive crossing lines Cc ¼ coupling capacitance between main line and a crossing line Rcl ¼ line resistance of a crossing line on left side of main line Rcr ¼ line resistance of a crossing line on right side of main line Lcl ¼ self-inductance of a crossing line on left side of main line Lcr ¼ self-inductance of a crossing line on right side of main line CL ¼ load capacitance Rr ¼ resistance of portion of main line after crossing lines

FIGURE 4.5.2 Equivalent circuit of bilevel crossing interconnections including capacitive couplings. Inductive couplings not included.

282

CROSSTALK ANALYSIS

Lr ¼ self-inductance of portion of main line after crossing lines Cr ¼ ground capacitance of portion of main line after crossing line (load section portion) Other symbols are deﬁned as they appear. Following the same steps as in Section 3.4.1, the voltage and current in the s domain at the end of the transmission line section, that is, at x ¼ ‘, are given by pﬃﬃﬃﬃ Vð‘; sÞ ¼ e ZY ‘ Vi ðsÞ þ Vr ðsÞ rﬃﬃﬃﬃ Y pﬃﬃﬃﬃ Ið‘; sÞ ¼ ½e ZY ‘ Vi ðsÞ Vr ðsÞ Z where pﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ Vs ðsÞe ZY ‘ 1 ZTX Y=Z pﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ Vr ðsÞ ¼ ½1 Rs Y=Z ½1 ZTX Y=Z e2 ZY ‘ ½1 þ Rs Y=Z ½1 þ ZTX Y=Z pﬃﬃﬃﬃ 1 þ ZTX e ZY ‘ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃ Vr ðsÞ Vi ðsÞ ¼ ½1 ZTX Y=Z e ZY ‘

ZTX ¼ Zp1 k ZX þ RB Vs ðsÞ ¼

1 est s

where Zx is the impedance of the crossing line as seen by the current ﬂowing in the driven line given by 1 1 Zx ¼ þ ðRcl þ sLcl þ Rs Þ k Rcr þ sLcr þ sCc sCL and the partial load Zp1 is given by Zp1 ¼ Zp2 k Zx þ ZB where ZB ¼ RB þ sLB

Zp2 ¼ Zp3 k Zx þ ZB

and so on, until Zpðn2Þ ¼ Zpðn1Þ k Zx þ ZB Zpðn1Þ ¼ Zpn k Zx þ ZB 0

Zpn ¼ ZL ¼ Rr þ

1 k sCr

sLr þ

1 sCL

The current Ið‘; sÞ is the s domain input current for the crossing section.

ANALYSIS OF CROSSING INTERCONNECTIONS

283

In the crossing section, the driven line on the top plane and the second-level interconnections embedded in the substrate cross each other. This section is driven by the output of the transmission line section, and the output of this section drives the next section, that is, the load section. The driven line is coupled to the crossing lines by the coupling capacitances, which depend on the crossing area (which in turn depends on the line widths and the crossing angle), the interlevel separation, and the substrate’s dielectric constant. It is assumed that all the interconnection lines are of the same width, thickness, and material. The algorithm can be easily modiﬁed for different situations. After some manipulation, it can be shown that the crosstalk voltage on the jth crossing line, that is, the voltage across the load capacitance on the jth crossing line, is given by the expression rﬃﬃﬃﬃ Y ðpﬃﬃﬃﬃ 1 0 ½e ZY Þ‘ Vi ðsÞ Vr ðsÞ Vcross; j ðsÞ ¼ Z sCL where ‘0 is the length of the jth crossing line from the point of its coupling with the main line to its load CL , Z ¼ R þ sL

Y ¼ G þ sC

pﬃﬃﬃﬃ 0 pﬃﬃﬃﬃﬃﬃﬃﬃﬃ Vs;j ðsÞe ZY ‘ ½1 ZTX Y=Z pﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ Vr ðsÞ ¼ ½1 ZTX Y=Z e2 ZY ‘0 ½1 þ ZTX Y=Z pﬃﬃﬃﬃ 0 1 þ ZTX e ZY ‘ pﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃ Vr ðsÞ Vi ðsÞ ¼ ½1 ZTX Y=Z e ZY ‘0

and the equivalent of the source voltage for the jth crossing line is given by 1 Vs; j ðsÞ ¼ ðIj Ij1 Þ Zx sCc where Ij is the current ﬂowing in the driven line after ‘‘seeing’’ the jth crossing line. The currents Ij ð j ¼ 1; 2; . . . ; nÞ are given by

I1 ¼ ITX I2 ¼ I1

Zx Zx þ Zp1

Zx Zx þ Zp2

284

CROSSTALK ANALYSIS

and so on, until In ¼ In1

Zx Zx þ ZL0

where ZL0 is the total impedance of the load section and In represents the current ﬂowing into the load section. 4.5.2

Simulation Results

As mentioned earlier, the crosstalk effect can be studied by analyzing the plot of crosstalk voltage for a given set of interconnection parameters in a speciﬁc time range and plotting the maximum crosstalk voltage as a function of the interconnection parameter under investigation. To simulate the crosstalk effects in the embedded crossing interconnections due to a driven interconnection printed on top of the GaAs substrate, the computer program SPBIGV is presented in Appendix 4.2 on the accompanying ftp site. It incorporates the steps outlined above to ﬁnd Vcross ðsÞ and then uses the Pade´ approximation to carry out the inverse Laplace transformation. In the following results, one of the parameters is varied in a speciﬁc range while the other parameters are kept ﬁxed at their typical values, which were selected to be the following: interconnection length 1000 mm, each, interconnection width 1.0 mm each, interconnection thickness 0.5 mm each, interconnection separation 1.0 mm each, interconnection material resistivity 3.0 m cm, interlevel distance 2.0 mm, substrate thickness 200.0 mm, driving source resistance 100 , and load capacitance 10 fF. In addition, the number of crossing lines is 25 and the crosstalk plots are those for the 13th crossing interconnection. The frequency of the input square-wave train is 1 GHz. Crosstalk voltage waveforms for several values of the interconnection length in the time range 0–100 ps are shown in Fig. 4.5.3, and the dependence of maximum crosstalk voltage on interconnection length in the range 100–2000 mm is shown in Fig. 4.5.4. For various values of the interconnection width, crosstalk voltage waveforms in the time range 0–100 ps are shown in Fig. 4.5.5, while the dependence of the maximum crosstalk voltage on the interconnection widths in the range 0.2– 2.0 mm is shown in Fig. 4.5.6. For several values of the interconnection material resistivity, crosstalk voltage waveforms in the time range 0–100 ps are shown in Fig. 4.5.7, and the dependence of maximum crosstalk voltage on resistivity in the range 1–100 m cm is shown in Fig. 4.5.8. Crosstalk voltage waveforms for several values of load capacitance in the time range 0–100 ps are shown in Fig. 4.5.9, and the dependence of maximum crosstalk voltage on load capacitance in the range 5–200 fF is shown in Fig. 4.5.10. For various values of the driving source resistance, crosstalk voltage waveforms in the time range 0–100 ps are shown in Fig. 4.5.11, while the dependence of maximum crosstalk voltage on source resistance in the range 10–300 is shown in Fig. 4.5.12.

ANALYSIS OF CROSSING INTERCONNECTIONS

FIGURE 4.5.3 0–100 ps.

285

Crosstalk voltage waveforms for several interconnection lengths in range

FIGURE 4.5.4 Dependence of maximum crosstalk voltage on interconnection lengths in range 100–2000 mm.

286

CROSSTALK ANALYSIS

FIGURE 4.5.5 0–100 ps.

Crosstalk voltage waveforms for several interconnection widths in range

FIGURE 4.5.6 Dependence of maximum crosstalk voltage on interconnection widths in range 0.2–2.0 mm.

ANALYSIS OF CROSSING INTERCONNECTIONS

287

FIGURE 4.5.7 Crosstalk voltage waveforms for several interconnection material resistivities in range 0–100 ps.

FIGURE 4.5.8 Dependence of maximum crosstalk voltage on interconnection material resistivity in range 1–100 m cm.

288

CROSSTALK ANALYSIS

FIGURE 4.5.9

Crosstalk voltage waveforms for several load capacitances in range 0–100 ps.

FIGURE 4.5.10 Dependence of maximum crosstalk voltage on load capacitance in range 5–200 fF.

ANALYSIS OF CROSSING INTERCONNECTIONS

FIGURE 4.5.11

289

Crosstalk voltage waveforms for several source resistances in range 0–100 ps.

FIGURE 4.5.12 Dependence of maximum crosstalk voltage on source resistance in range 10–300 .

290

CROSSTALK ANALYSIS

FIGURE 4.5.13 Crosstalk voltage waveforms for several interlevel distances in range 0–100 ps.

FIGURE 4.5.14 Dependence of maximum crosstalk voltage on interlevel distance in range 1–5 mm.

ANALYSIS OF CROSSING INTERCONNECTIONS

291

FIGURE 4.5.15 Crosstalk voltage waveforms for several crossing angles in range 0–100 ps.

FIGURE 4.5.16 Dependence of maximum crosstalk voltage on crossing angle in range 20 –90 .

292

CROSSTALK ANALYSIS

FIGURE 4.5.17 Crosstalk voltage waveforms for several values of number of crossing interconnections in range 0–100 ps.

FIGURE 4.5.18 Dependence of maximum crosstalk voltage on number of crossing interconnections in range 8–70.

COMPACT EXPRESSIONS FOR CROSSTALK ANALYSIS

293

FIGURE 4.5.19 Crosstalk voltage waveforms for several values of frequency of input source in range 0–100 ps.

Crosstalk voltage waveforms for several values of interlevel distance in the time range 0–100 ps are shown in Fig. 4.5.13, and the dependence of maximum crosstalk voltage on interlevel distance in the range 1–5 mm is shown in Fig. 4.5.14. For various values of the crossing angle, crosstalk voltage waveforms in the time range 0–100 ps are shown in Fig. 4.5.15, while the dependence of maximum crosstalk voltage on crossing angle in the range 20 –100 is shown in Fig. 4.5.16. For several values of the number of crossing lines, crosstalk voltage waveforms for the middle interconnection in the time range 0–100 ps are shown in Fig. 4.5.17, and the dependence of maximum crosstalk voltage on number of crossing lines in the range 8–70 is shown in Fig. 4.5.18. For several values of signal of frequency, crosstalk voltage waveforms in the time range 0–100 ps are shown in Fig. 4.5.19.

4.6

COMPACT EXPRESSIONS FOR CROSSTALK ANALYSIS

In this section, compact, that is, closed-form, expressions for the voltage waveforms under worst-case crosstalk conditions at the load end of a quiet interconnection are presented. First, two coupled interconnections are modeled as distributed RC networks [27], and then these are treated as open-circuit distributed RLC networks [22]. Finally, the analysis is extended to three coupled open-circuit interconnections modeled as distributed RLC networks [22]. An analysis of capacitively terminated single and coupled RLC interconnections is presented in [23].

294

CROSSTALK ANALYSIS

FIGURE 4.6.1 Two interconnection lines represented as coupled RC lines. (From [27]. # 1993 by IEEE.)

4.6.1

Distributed RC Model for Two Coupled Interconnections

Consider two interconnection lines of length ‘ each represented as distributed RC networks as shown in Fig. 4.6.1. Let R and C represent the total resistance and capacitance of each line, respectively, assumed equal for simplicity and CC represent the total coupling capacitance between the two interconnections. The two interconnections are driven by two step voltage sources VS1 and VS2 with internal resistances RS1 and RS2 , respectively. Here, CL1 and CL2 are the capacitive loads on the two interconnections. The basic differential equations which govern the voltage waveforms V1 and V2 along these two coupled interconnections are described as I @ 2 V1 @V1 @V2 c ¼ ðc þ c Þ 1 2 c @t @t r1 @x2

ð4:6:1Þ

1 @ 2 V2 @V2 @V1 ¼ ðc1 þ c2 Þ cc @t @t r2 @x2

ð4:6:2Þ

where r1 and r2 denote the resistances of the two lines per unit length, c1 and c2 denote the capacitances of the two lines, while cc denotes the coupling capacitance between the two lines per unit length. In other words, R1 ¼ r1 ð‘Þ, R2 ¼ r2 ð‘Þ, and CC ¼ cc ð‘Þ. For simplicity, we will assume that r1 ¼ r2 ¼ r and c1 ¼ c2 ¼ c. Equations (4.6.1) and (4.6.2) can be solved to yield the following closed-form expressions for the load voltage waveforms V1 ð‘; tÞ and V2 ð‘; tÞ: s t K1 s1 t 1 ðVS1 þ VS2 Þ exp V1 ð‘; tÞ Vs1 þ þ ðVS1 VS2 Þ exp 2 RC RC þ 2RCC ð4:6:3Þ

295

COMPACT EXPRESSIONS FOR CROSSTALK ANALYSIS

V2 ð‘; tÞ Vs2 þ

s t K1 s1 t 1 ðVS1 þ VS2 Þ exp ðVS1 VS2 Þ exp 2 RC RC þ 2RCC ð4:6:4Þ

where K1 and s1 are given by

RT þ CT þ 1 K1 ¼ 1:01 RT þ CT þ p=4 s1 ¼

1:04 RT CT þ RT þ CT þ ð2=pÞ2

ð4:6:5Þ

ð4:6:6Þ

with RT ¼ RS1 =R ¼ RS2 =R and CT ¼ CL1 =C ¼ CL2 =C. The relative errors of these coefﬁcients are less than 3% for K1 and less than 4% for s1 for any values of RT and CT . It should be noted that the exact value of K1 is 4=p and that of s1 is ðp=2Þ2 for RT ¼ CT ¼ 0. When RT ¼ CT 1, the exact value of K1 is 1 and that of s1 is 1=½ðRT þ 1ÞðCT þ 1Þ. Both these asymptotic values are correctly produced by the expressions (4.6.5) and (4.6.6). It is clear from expressions (4.6.3) and (4.6.4) that if VS1 ¼ VS2 , that is, the two lines are driven by in-phase source signals, each line behaves as a distributed RC line with a capacitance C. On the other hand, if the two lines are driven by out-of-phase source signals, that is, if VS2 ¼ VS1 , then each line behaves as a distributed RC line with a capacitance equal to C þ 2CC . The peak value of V2 ð‘; tÞ when VS2 ¼ 0 is the maximum crosstalk voltage induced at the load end of the second line by the coupling capacitance. It is this value that the designer needs to keep in mind to avoid malfunction of the circuit. It can be determined by differentiating Eq. (4.6.4) to be V2; max ¼ VS1 K1

1=2Z 1 Z 1 Z VS1 1 þ 2Z 1 þ 2Z 2 1þZ

ð4:6:7Þ

where Z¼

CC C

The approximation at the right end of Eq. (4.6.7) holds when RT ¼ CT ¼ 0 and Z 2. In a special case when RS1 is zero and RS2 is ﬁnite, the maximum crosstalk voltage is given by 0:5 þ RT2 Z V2;max VS1 1 þ RT2 1þZ In this case, the crosstalk becomes worse than that predicted from Eq. (4.6.7).

296

CROSSTALK ANALYSIS

A comparison between the voltage waveforms obtained using the compact expression (4.6.7) with that using SPICE (with each interconnection modeled as a 10-step RC ladder network) shows that the maximum error in the compact expression is less than 3% of VS1 . Simple expressions for the coupling capacitances between the interconnections can be derived from those given in Section 2.4. For a system of two lines on a ground plane, the coupling capacitance C12 is given by [27] " 1:08 0:32 # 1:38 T W S C12 ¼ eox 1:82 þ ð4:6:8Þ þ 0:43 H H H while for a system of three interconnections on a ground plane, the coupling capacitances are given by [27] " C12 ¼ eox

1:1 0:31 # 1:45 T W S 1:93 þ1:14 þ 0:51 H H H

ð4:6:9Þ

Relative errors of these capacitance expressions are less than 15% for the values of T=H, W=H, and S=H between 0.3 and 3.0.

4.6.2

Distributed RLC Model for Two Coupled Interconnections

Two coupled distributed RLC interconnections A (active) and Q (quiet) shown in Fig. 4.6.2 are described by the following partial differential equations [22]: @2 @ @ VQ ðx; tÞ ¼ rðcgnd þ cm Þ VQ ðx; tÞ rcm VA ðx; tÞ þ ½ls ðc þ cm Þ @x2 @t @t lm cm

@2 @2 V ðx; tÞ þ ½l ðc þ c Þ l c VA ðx; tÞ Q m gnd m s m @t2 @t2

ð4:6:10Þ

FIGURE 4.6.2 Two coupled distributed RLC interconnections A (active) and Q (quiet). (From [22]. # 2000 by IEEE.)

COMPACT EXPRESSIONS FOR CROSSTALK ANALYSIS

@2 @ @ VA ðx; tÞ ¼ rðcgnd þ cm Þ VA ðx; tÞ rcm VQ ðx; tÞ þ ½ls ðcgnd þ cm Þ @x2 @t @t @2 @2 lm cm 2 VA ðx; tÞ þ ½lm ðcgnd þ cm Þ ls cm 2 VQ ðx; tÞ @t @t

297

ð4:6:11Þ

where VA is the transient voltage along the active interconnection, VQ is the transient voltage along the quiet interconnection, cgnd is the ground capacitance of the interconnection, cm is the mutual (coupling) capacitance between the interconnections, ls is the self-inductance of each interconnection, and lm is the mutual (coupling) inductance between the two interconnections. Both lines A and Q are of ﬁnite length ‘ and are open circuited at the load ends, line A is driven by a voltage source VS having a source resistance RS whereas line Q is not driven by a voltage source though it is connected to a resistance RS at x ¼ 0. The resulting boundary conditions for current and voltage along the lines A and Q are as follows: VA ðx ¼ 0; tÞ ¼ VS ðtÞ RS IA ðx ¼ 0; tÞ

ð4:6:12Þ

VQ ðx ¼ 0; tÞ ¼ RS IQ ðx ¼ 0; tÞ

ð4:6:13Þ

IA ðx ¼ ‘; tÞ ¼ 0

ð4:6:14Þ

IQ ðx ¼ ‘; tÞ ¼ 0

ð4:6:15Þ

Equations (4.6.10) and (4.6.11) can be decoupled in terms of the following voltages Vþ and V deﬁned as V þ ¼ V A þ VQ

V ¼ V A VQ

The resulting set of decoupled partial differential equations is @2 @ @2 V V ðx; tÞ ¼ rc ðx; tÞ þ ðl þ l Þc Vþ ðx; tÞ þ þ s m @x2 @t2 @t @2 @ @2 V ðx; tÞ ¼ rðc þ 2cm Þ V ðx; tÞ þ ðls lm Þðc þ 2cm Þ 2 V ðx; tÞ 2 @x @t @t

ð4:6:16Þ ð4:6:17Þ

The boundary conditions for voltages Vþ and V and for currents Iþ ¼ IA þ IQ and I ¼ IA IQ can be derived from Eqs. (4.6.12) to (4.6.15) as follows: Vþ ðx ¼ 0; tÞ ¼ VS ðtÞ RS Iþ ðx ¼ 0; tÞ

ð4:6:18Þ

V ðx ¼ 0; tÞ ¼ VS ðtÞ RS I ðx ¼ 0; tÞ

ð4:6:19Þ

Iþ ðx ¼ ‘; tÞ ¼ 0

ð4:6:20Þ

I ðx ¼ ‘; tÞ ¼ 0

ð4:6:21Þ

298

CROSSTALK ANALYSIS

Equations (4.6.18)–(4.6.21) indicate that the boundary conditions for ðVþ ; Iþ Þ and ðV ; I Þ are the same as those for an open-circuit single line driven by a voltage source VS with an arbitrary resistance RS . Equation (4.6.16) suggests that Vþ ðx; tÞ is the solution for the voltage along either of the two interconnection lines when both are excited simultaneously. In this case, the mutual capacitance between the lines will be zero and each line will have its ground capacitance only. In this conﬁguration, since the currents in the two lines are in the same direction, the effective inductance of each line will be the sum of its selfinductance and the mutual inductance between the two lines. On the other hand, Eq. (4.6.17) suggests that V ðx; tÞ is the solution for the voltage along the active interconnection line when the adjacent line is switching with opposite polarity. In this case, the mutual capacitance between the lines will be twice its previous value in addition to each line having its ground capacitance. In this conﬁguration, since the currents in the two lines are equal in magnitude but opposite in direction, the effective inductance of the line will be the difference of its self-inductance and the mutual inductance between the two lines. The worst-case crosstalk on the quiet line occurs when both lines are initially uncharged and the active line is connected to the voltage source. In this case, the voltage waveform induced on the quiet line is given by VQ ð‘; tÞ ¼ 1=2½Vfin ð‘; t; l ¼ ls þ lm ; c ¼ cgnd Þ Vfin ð‘; t; l ¼ ls lm ; c ¼ cgnd þ 2cm Þ ð4:6:22Þ In Eq. (4.6.22), Vfin ðx; tÞ represents the voltage waveform along a single interconnection line derived earlier in Chapter 3. It is given by Vfin ð‘; tÞ ¼ 2Vinf ðx ¼ ‘; t; m ¼ 0Þ q X n X 1 X nðn 1 þ jÞ! þ 2er=ð2lÞt ð1Þi ðniþjÞ i!j!ðn iÞ! n¼1 i¼0 j¼0 Vinf ðx ¼ ð2n þ 1Þ‘; t; m ¼ i þ jÞ

ð4:6:23Þ

where Vinf ðx; t; mÞ denotes the voltage waveform along the semi-inﬁnite line given by " Vinf ðx; t; mÞ ¼ VS

Z0 Z0 þ RS

pﬃﬃﬃﬃ!m=2 qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃ t x lc r r=ð2lÞt pﬃﬃﬃﬃ e I0 t2 ðx lcÞ2 2l t þ x lc

pﬃﬃﬃﬃ!ðkþmÞ=2 1 1X t x lc pﬃﬃﬃﬃ þ er=ð21Þt ½4 ð1 þ Þ2 k1 2 k¼1 t þ x lc qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ# pﬃﬃﬃﬃ pﬃﬃﬃﬃ r IðkþmÞ t2 ðx lcÞ2 uðt x lcÞ 2l

ð4:6:24Þ

COMPACT EXPRESSIONS FOR CROSSTALK ANALYSIS

299

FIGURE 4.6.3 Three parallel coupled interconnections, each driven by voltage source VS having internal source resistance RS sandwiched between two virtual ground planes. (From [22]. # 2000 by IEEE.)

4.6.3

Distributed RLC Model for Three Coupled Interconnections

Three parallel coupled interconnections, each driven by a voltage source VS having an internal source resistance RS , sandwiched between two virtual ground planes as shown in Fig. 4.6.3 can be described by the partial differential equations [22] 2 2

V1 ðx; tÞ

3

2

Cgnd þ cm þ c13

@ 6 7 6 4 V2 ðx; tÞ 5 ¼ r 4 @x2 V3 ðx; tÞ 2

cm c13 l11 l12 l13

32

cm

c13

3

2

V1 ðx; tÞ

3

7 7@6 Cgnd þ 2cm cm 5 4 V2 ðx; tÞ 5 @t cm Cgnd þ cm þ c13 V3 ðx; tÞ Cgnd þ cm þ c13

76 6 þ 4 l12 l22 l23 54 l13 l23 l33 2 3 V1 ðx; tÞ @ 6 7 4 V2 ðx; tÞ 5 @t2 V3 ðx; tÞ

cm c13

cm

c13

3

7 Cgnd þ 2cm cm 5 cm Cgnd þ cm þ c13 ð4:6:25Þ

The inductance and capacitance matrices are connected by the following relationship: 2

32 3 2 3 cm c13 Cgnd þ cm þ c13 1 0 0 l11 l12 l13 1 4 l12 l22 l23 54 5 ¼ 40 1 05 cm Cgnd þ 2cm cm v2 c13 cm Cgnd þ cm þ c13 l13 l23 l33 0 0 1 ð4:6:26Þ where v is the speed of propagation of an electromagnetic wave in the dielectric medium where the interconnections are placed. From the symmetry of the interconnections, we will assume that the voltage waveforms on the outer interconnections 1 and 3 are the same and call them Vo ðx; tÞ. For this reason, the coupling capacitance c13 can be taken as effectively zero. On the same lines, we will represent the voltage waveform on the inner interconnection 2 as Vi ðx; tÞ. Then the

300

CROSSTALK ANALYSIS

matrix equation (4.6.25) can be expressed as the following two coupled partial differential equations after setting c13 ¼ 0: @2 @ @ 1 @2 Vo ðx; tÞ ¼ rðcgnd þ cm Þ Vo ðx; tÞ rcm Vi ðx; tÞ þ 2 2 Vo ðx; tÞ 2 @x @t @t v @t

ð4:6:27Þ

@2 @ @ 1 @2 V V V ðx; tÞ ¼ 2rc ðx; tÞ rðc þ 2c Þ ðx; tÞ þ Vi ðx; tÞ ð4:6:28Þ i m o gnd m i @x2 @t @t v2 @t2 Equations (4.6.27) and (4.6.28) can be decoupled in terms of the voltages Vsum and Vdiff deﬁned as Vsum ¼ 2Vo þ Vi

ð4:6:29Þ

Vdiff ¼ Vo Vi

ð4:6:30Þ

The resulting equations are @2 @ 1 @2 Vsum ðx; tÞ ¼ rcgnd Vsum ðx; tÞ þ 2 2 Vsum ðx; tÞ 2 @x @t v @t

ð4:6:31Þ

@2 @ 1 @2 V ðx; tÞ ¼ rðc þ 3c Þ ðx; tÞ þ Vdiff ðx; tÞ V diff gnd m diff @x2 @t v2 @t2

ð4:6:32Þ

The boundary conditions for (Vsum , Isum ) and ðVdiff ; Idiff Þ can be found from those for the inner and outer interconnections to be Vsum ðx ¼ 0Þ ¼ 2VS ðtÞ RS Isum ðx ¼ 0Þ

ð4:6:33Þ

Vdiff ðx ¼ 0Þ ¼ VS ðtÞ RS Idiff ðx ¼ 0Þ

ð4:6:34Þ

Isum ðx ¼ ‘Þ ¼ 0

ð4:6:35Þ

Idiff ðx ¼ ‘Þ ¼ 0

ð4:6:36Þ

According to Eqs. (4.6.31) and (4.6.32), the voltage waveforms for Vsum ðx; tÞ and Vdiff ðx; tÞ are the solutions for a single ﬁnite line though with different capacitance and inductance values. These can be used to ﬁnd the voltage waveforms for the worst-case time delay and crosstalk scenarios. The worst-case crosstalk on the inner interconnection occurs when all three lines are initially uncharged and the two outer interconnections are made simultaneously active by turning on their sources. The resulting load voltage waveform for the inner (quiet) interconnection is then given by 2 1 Vfin ‘; t; l ¼ ; c ¼ 2c VQ ð‘; tÞ ¼ gnd 3 2cgnd v2 1 ð4:6:37Þ Vfin ‘; t; l ¼ ; c ¼ 2c þ 3c gnd m ð2cgnd þ 3cm Þv2

COMPACT EXPRESSIONS FOR CROSSTALK ANALYSIS

301

In Eq. (4.6.37), Vfin ðx; tÞ represents the voltage waveform along a single interconnection line derived earlier in Chapter 3. It is given by Vfin ð‘; tÞ ¼ 2Vinf ðx ¼ ‘; t; m ¼ 0Þ þ 2er=ð2lÞt

q X n X 1 X

ð1Þi ðniþjÞ

n¼1 i¼0 j¼0

Vinf ðx ¼ ð2n þ 1Þ‘; t; m ¼ i þ jÞ

nðn 1 þ jÞ! i!j!ðn iÞ! ð4:6:38Þ

where Vinf ðx; t; mÞ denotes the voltage waveform along the semi-inﬁnite line given by " Vinf ðx; t; mÞ ¼ VS

Z0 Z 0 þ RS

pﬃﬃﬃﬃ!m=2 qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ pﬃﬃﬃﬃ t x lc r r=ð2lÞt pﬃﬃﬃﬃ e I0 t2 ðx lcÞ2 2l t þ x lc

pﬃﬃﬃﬃ!ðkþmÞ=2 1 1X t x lc pﬃﬃﬃﬃ er=ð21Þt ½4 ð1 þ Þ2 k1 þ 2 k¼1 t þ x lc qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ# pﬃﬃﬃﬃ pﬃﬃﬃﬃ r t2 ðx lcÞ2 uðt x lcÞ ð4:6:39Þ IðkþmÞ 2l Comparisons of the normalized load voltages obtained by the compact expressions for the distributed RLC interconnection model with those obtained by HSPICE with 1, 10, 50, and 500 lumped RLC elements are shown in Fig. 4.6.4 [22]. For these comparisons, the interconnection metal is assumed to be copper surrounded by a low-k dielectric. The interconnection parameters are as follows: Interconnection length 3.6 cm Interconnection cross section 2:1 mm 2:1 mm Resistance per unit length 37.86 /cm Driving source resistance 133.3 Lossless characteristic impedance Z0þ ¼ 266:32 Lossless characteristic impedance Z0 ¼ 88:77 Figure 4.6.4 shows that the HPICE waveforms approach the compact expression waveform as the number of RLC elements is increased in the HSPICE simulation. For the typical values of the interconnection and driving source parameters chosen in these comparisons, there is virtually complete agreement between the two waveforms for 500 or more RLC elements, lending excellent support to the compact expressions.

302

CROSSTALK ANALYSIS

0.40

0.40 HSPICE Simulation of 10 RLC Element Compact RLC Expression

HSPICE Simulation of 1 RLC Element Compact RLC Expression 0.30

Vo/Vdd

Vo/Vdd

0.30

0.20

0.10

0.20

0.10

0.00 0.0e+00

5.0e–10

1.0e–09 Time [sec] (a)

1.5e–09

2.0e–00

0.00 0.0e+00

0.40

1.0e–09 Time [sec] (b)

1.5e–09

2.0e–00

0.40 HSPICE Simulation of 50 RLC Element Compact RLC Expression

HSPICE Simulation of 500 RLC Element Compact RLC Expression 0.30

Vo/Vdd

0.30

Vo/Vdd

5.0e–10

0.20

0.10

0.20

0.10

0.00 0.0e+00

5.0e–10

1.0e–09 Time [sec] (c)

1.5e–09

2.0e–00

0.00 0.0e+00

5.0e–10

1.0e–09 Time [sec] (d)

1.5e–09

2.0e–00

FIGURE 4.6.4 Comparison of normalized load voltages obtained by compact expressions for distributed RLC interconnection model with those obtained by HSPICE with 1, 10, 50, and 500 lumped RLC elements. (From [22]. # 2000 by IEEE.)

4.7

MULTICONDUCTOR BUSES IN GaAs HIGH-SPEED LOGIC CIRCUITS

The propagation delays, crosstalk, and pulse distortion associated with multiconductor interconnecting buses are critical issues in the design of large-scale and very large scale high-speed logic ICs on conventional or GaAs substrates. Modeling of these buses has received considerable attention in the literature, and it is widely accepted that the lumped models are inadequate for high-speed ICs. The validity of transmission line models has also been questioned [28] because these do not include either surface wave excitation or free-space line or load radiations. Nevertheless, it can be shown that the quasi-TEM models are satisfactory as long as coupling effects within a multiconductor bus (MBUS) rather than between distant MBUSes are concerned. In this section, a lossy quasi-TEM model of crosstalk for MBUSes on semi-insulating GaAs substrate [15] is presented.

303

MULTICONDUCTOR BUSES IN GAAS HIGH-SPEED LOGIC CIRCUITS

4.7.1

The Model

A schematic of a high-speed VLSI bus made of N (common values of N are powers of 2, e.g., 8, 16, 32, . . .) parallel equispaced metallic strips deposited either on a semi-insulating substrate (GaAs ICs) or on a thin oxide layer placed on a semiconducting substrate (Si ICs) along with the lower conducting ground plane is shown in Fig. 4.7.1. Typical values of widths, thicknesses, and spacings of the conducting strips usually fall into the ranges w ¼ 1–10 mm, t ¼ 0:5–2 mm, and s ¼ 1–10 mm, respectively. Since we are interested in crosstalk between conductors within the same bus and not between distant buses (which are affected by surface wave excitations), we can describe the structure of Fig. 4.7.1 by a quasi-TEM model, that is, as a multiconductor transmission line characterized by the capacitance matrix ½C, inductance matrix ½L, resistance matrix ½R, and conductance matrix ½G whose elements are deﬁned per unit length and, in principle, can depend on frequency. Since the GaAs substrate is almost lossless and the Si substrate can be considered lossless as long as the frequency is such that the onset of slow waves can be avoided, the conductance matrix can be neglected. Then, the signal propagation on the bus can be described by the well-known generalizations of Kirchhoff’s equations [29]: @ @ vðz; tÞ ¼ ½R þ ½L iðz; tÞ @z @t @ @ iðz; tÞ ¼ ½C vðz; tÞ @z @t

ð4:7:1Þ

where vðz; tÞ and iðz; tÞ are the N-component voltage and current vectors. As shown in Fig. 4.7.2, the input signals are fed into the bus by voltage generators having ﬁnite internal impedances (simulating the output of the driving stage) and the bus is loaded on the right side by the input impedances of the next logic stage. For low-speed signals, the MBUS behaves as RC lines resulting in mainly diffusive transients and strong signal distortion. Above a critical frequency which depends on the propagation mode considered, the bus behaves as lossy LC lines and propagation dominates. Therefore, for a wide range of input signal frequencies, simulation of the transient behavior of the bus can be performed by solving

FIGURE 4.7.1

Schematic of structure of MBUS. (From [15]. # 1989 by IEEE.)

304

CROSSTALK ANALYSIS

FIGURE 4.7.2 Termination network for MBUS analyzed in this section. (From [15]. # 1989 by IEEE.)

Eqs. (4.7.1) through standard spectral-domain techniques, that is, Fourier analysis and back transformation. First, the frequency-domain response of the N lines is determined. Using standard multiconductor line analysis [29], we deﬁne the series impedance matrix as ½Zs ¼ ½R þ jo½L and the parallel admittance matrix as ½Yp ¼ jo½C A symmetrical grounded N-conductor line supports N propagation modes which are called even or odd depending on whether their potential distribution is even or odd with respect to the center of the line. The N complex modal propagation constants ki will be a solution of the eigenvalue problem: ðk2 ½U þ ½Zs ½Yp Þ½Mv ¼ 0 where ½Mv is the voltage eigenvector matrix and ½U is the identity matrix. The current eigenvector matrix ½Mi is then given by 1 ½Mi ¼ o½C½Mv diag ki and the characteristic admittance matrix is given by ½Yc ¼ ½Mi ½Mv 1 The characteristic impedance matrix ½Zc is the inverse of ½Yc and the modal impedances are given by the eigenvalues of ½Zc . The voltage and current vectors on

MULTICONDUCTOR BUSES IN GAAS HIGH-SPEED LOGIC CIRCUITS

305

the lines are then given by VðzÞ ¼ ½Mv ½Wþ ðzÞ þ W ðzÞ

ð4:7:2Þ

IðzÞ ¼ ½Yc ½Mv ½Wþ ðzÞ W ðzÞ where W ¼ fWi ðzÞg

ð4:7:3Þ

Wi ðzÞ ¼ Wi ð0Þejki z

Wiþ and Wi are the amplitudes of the progressive and regressive components of the ith mode, and ki is the propagation constant of the ith mode. The presence of generators and loads on the bus leads to the following boundary conditions: Vð0Þ ¼ E ½Zg Ið0Þ

ð4:7:4Þ

Vð‘Þ ¼ ½ZL Ið‘Þ where E ¼ fEi ðoÞg, ½Zg ¼ diagfZgi g, ½ZL ¼ diagfZLi g, Ei is the voltage spectrum of the generator at the input of the ith strip, Zgi is the internal impedance of the ith generator and ZLi is the load impedance on the ith strip. Substituting Eqs. (4.7.2) and (4.7.3) into (4.7.4) leads to the following linear system for W ð‘Þ: "

ð½YL ½Yc Þ½Mv

ð½YL þ ½Yc Þ½Mv

ð½U þ ½Zg ½Yc Þ½Mv ½P1

ð½U ½Zg ½Yc Þ½Mv ½P

#"

Wþ ð‘Þ W ð‘Þ

#

" ¼

O E

# ð4:7:5Þ

where ½P ¼ diagfejki ‘ g After solving Eq. (4.7.5), the voltage and current spectra can be obtained from Eq. (4.7.2). The time-domain response can then be obtained by inverse Fourier transformation. 4.7.2

Lossless MBUS with Cyclic Boundary Conditions

The transient behavior of the MBUS can be analyzed by considering an idealized case of a lossless MBUS with cyclic boundary conditions which can be solved explicitly. If all load and generator impedances are equal and the signal is applied to the kth line only, that is, ZLi ¼ ZL , Zgi ¼ Zg , and Ei ¼ Edik , then the solution of Eq. (4.7.5) can be obtained to be ( ) N 1 1X 2p Vi ðoÞ ¼ exp j nði kÞ gn ðoÞ EðoÞ ð4:7:6Þ N n¼0 N

306

CROSSTALK ANALYSIS

where gn ðoÞ ¼

ð1 rn Þ½1 þ n ðoÞejkn ‘ 2½1 rn n ðoÞe2jkn ‘

where rn and n are the reﬂection coefﬁcients of Zg and ZL with respect to the characteristic impedance Zn of the nth mode. Equation (4.7.6) represents the output voltage spectra as superpositions of N modal line contributions. The time-domain output waveforms can be obtained by the inverse Fourier transformation to be 1 vi ðtÞ ¼ N

( N1 X n¼0

) 2p exp j nði kÞ hn ðtÞ N

ð4:7:7aÞ

where hn ðtÞ is the inverse Fourier transform of gn ðoÞEðoÞ. In the practically important case where the load is capacitive ¼ Cload , the generator impedance is resistive ¼ Rgen , and the driving voltage is a unit step uðtÞ, then the modal line contribution hn ðtÞ is given by hn ðtÞ ¼ ð1 rn Þ

1 X

n n n rm n ½1 m ðtm Þuðtm Þ

ð4:7:7bÞ

m¼0

where tnm ¼ t ð2m þ 1ÞTn

Tn ¼

1 vn

an ¼

1 Zn Cload

and nm ðtÞ ¼ ean t

m k X X m ðan tÞi ð1Þmk ð2Þk i! k i¼0 k¼0

Due to the superposition of echoes, the function hn ðtÞ exhibits a staircase shape, as shown in Fig. 4.7.3.

4.7.3

Simulation Results

First, the quasi-TEM model can be validated by comparison of the computed results with the experimentally measured results. Such a comparison for two coupled lines is shown in Fig. 4.7.4. The experimental results have been obtained from [30, 31]. For these results, the excitation is a tapered unit step with trise ¼ 40 ps and other parameters are w ¼ 1:5 mm, s ¼ 2 mm, t ¼ 0:5 mm, h ¼ 400 mm, b ¼ 0, ‘ ¼ 3 mm, Rin ¼ 2100 , Rout ¼ 380 , er ¼ 12:8, and strip conductivity g ¼ 2:1 106 S=m. Time-domain voltage responses of an eight-conductor MBUS to a unit 1-ns voltage pulse applied to line 4 assuming lossless strips are shown in Fig. 4.7.5a.

MULTICONDUCTOR BUSES IN GAAS HIGH-SPEED LOGIC CIRCUITS

307

FIGURE 4.7.3 For MBUS of Fig. 4.7.1 with lossless strips, typical modal line contribution of zeroth mode (solid line) in response to 1-ns unit square pulse (dashed curve). (From [15]. # 1989 by IEEE.)

Fig. 4.7.5b shows these responses for lossy strips of conductivity g ¼ 4 107 S=m. Values of the other parameters are w ¼ 3 mm, s ¼ 4 mm, t ¼ 0:5 mm, h ¼ 400 mm, b ¼ 0, ‘ ¼ 5 mm, Rg ¼ 2100 , Cload ¼ 20 fF, and er ¼ 12:9. The time-domain responses of the same structure as in Fig. 4.7.5 to a typical high-speed digital signal

FIGURE 4.7.4 Comparison of computed results with experimentally measured results for two coupled lines. Experimental results obtained from [3, 4]. Excitation is a tapered unit step with trise ¼ 40 ps and other parameters are w ¼ 1:5 mm, s ¼ 2 mm, t ¼ 0:5 mm, h ¼ 400 mm, b ¼ 0, ‘ ¼ 3 mm, Rin ¼ 2100 , Rout ¼ 380 , er ¼ 12:8, and strip conductivity g ¼ 2:1 106 S=m. (From [15]. # 1989 by IEEE.)

308

CROSSTALK ANALYSIS

FIGURE 4.7.5 Time-domain voltage responses of eight-conductor MBUS to unit 1-ns voltage pulse applied to line 4 assuming (a) lossless strips and (b) lossy strips of conductivity g ¼ 4 107 S=m. Other parameters: w ¼ 3 mm, s ¼ 4 mm, t ¼ 0:5 mm, h ¼ 400 mm, b ¼ 0, ‘ ¼ 5 mm, Rg ¼ 2100 , Cload ¼ 20 fF, er ¼ 12:9. (From [15]. # 1989 by IEEE.)

represented by a 0.2-ns square pulse applied to line 4 are shown in Fig. 4.7.6. For the MBUS structure of Fig. 4.7.5, the peak voltage couplings are plotted in Fig. 4.7.7. Figure 4.7.7a shows the effect of interconnection length for lossless strips, Fig. 4.7.7b shows the effect of lossy lines for ‘ ¼ 5 mm, and the effect of input signal rise time for lossy lines is shown in Fig. 4.7.7c.

FIGURE 4.7.6 Time-domain responses of structure of Fig. 4.7.1 to typical high-speed digital signal represented by 0.2-ns square pulse applied to line 4. (From [15]. # 1989 by IEEE.)

EXERCISES

309

FIGURE 4.7.7 Peak voltage couplings for MBUS structure of Fig. 4.7.1: (a) effect of interconnection length for lossless strips, (b) effect of lossy lines for ‘ ¼ 5 mm, and (c) effect of input signal rise time for lossy lines. (From [15]. # 1989 by IEEE.)

EXERCISES E4.1 Referring to the lumped-capacitance model of Fig. 4.1.1, show that the amplitude of the crosstalk voltage at time t is given by V2 ðtÞ ¼ 12 ½et=t1 et=t2 where t1 ¼ RðC þ CL Þ and t2 ¼ Rð2Cc þ C þ CL Þ. Further prove that the maximum value of the crosstalk voltage is given by " # 1 nc 1 1 þ nc nc þ 1 1 þ nc ln exp ln V2; max ¼ exp 1 nc 1 nc 2 2nc 2nc

310

CROSSTALK ANALYSIS

where nc ¼

Cc C þ Cc þ CL

E4.2 Referring to Fig. 4.2.2, show that the voltage and current on the kth conductor can be expressed in terms of the normal modes by the equations Vk ðzÞ ¼

X

½Ayf ejðk1Þy ejo½tðz=vy Þ þ Ayr ejðk1Þy ejoðtþz=vy Þ

y

Ik ðzÞ ¼

X Ayf y

Z0y

e

jðk1Þy jo½tðz=vy Þ

e

Ayr jðk1Þy joðtþz=vy Þ e e Z0y

where z denotes the position on the conductor, o is the angular frequency, and Ayf and Ayr are the amplitudes of the forward and backward voltage waves in the y mode. E4.3 The mode wave amplitudes Ayf and Ayr in exercise E4.2 can be determined by using the known terminal conditions at both ends of each strip conductor. Assuming a variety of terminal conditions, ﬁnd these amplitudes. E4.4 Using the modiﬁcations suggested in Section 3.4.2, extend Section 4.5 to carry out a comprehensive analysis of crosstalk in the crossing interconnections shown in Fig. 3.4.7. Comment on the validity of the assumptions and approximations used in your analysis. E4.5 A few methods of reducing crosstalk are discussed in this chapter. Can you think of other methods? Discuss the merits and drawbacks of each method that you propose. E4.6 List and discuss the desirable characteristics of a numerical model that make it more suitable for inclusion in a CAD tool. Review the techniques presented in this chapter from the point of view of their suitability for inclusion in a CAD tool.

REFERENCES 1. J. Chilo and T. Arnaud, ‘‘Coupling Effects in the Time Domain for an Interconnecting Bus in High-Speed GaAs Logic Circuits,’’ IEEE Trans. Electron Devices, vol. ED-31, pp. 347–352, Mar. 1984. 2. M. Riddle, S. Ardalan, and J. Suh, ‘‘Derivation of the Voltage and Current Transfer Functions for Multiconductor Transmission Lines,’’ Proc. IEEE Int. Symp. Circuits Syst., pp. 2219–2222. 3. A. R. Djordjevic and T. K. Sarkar, ‘‘Analysis of Time Response of Lossy Multiconductor Transmission Line Networks,’’ IEEE Trans Microwave Theory Tech., vol. MTT-35, pp. 898–908, Oct. 1987.

REFERENCES

311

4. F. Romeo and M. Santomauro, ‘‘Time Domain Simulation of n Coupled Transmission Lines,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-35, pp. 131–137, Feb. 1987. 5. S. Seki and H. Hasegawa, ‘‘Analysis of Crosstalk in Very High-Speed LSI/VLSI Using a Coupled Multiconductor Stripline Model,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-32, pp. 1715–1720, Dec. 1984. 6. A. R. Djordevic, T. K. Sarkar, and R. F. Harrington, ‘‘Time Domain Response of Multiconductor Transmission Lines,’’ Proc. IEEE, vol. 75, pp. 743–764, June 1987. 7. S. Frankel, Multiconductor Transmission Line Analysis, Norwood, MA: Artech, 1977. 8. A. J. Gruodis and C. S. Chang, ‘‘Coupled Lossy Transmission Line Characterization and Simulation,’’ IBM J. Res. Dev., vol. 25, pp. 25–41, Jan. 1981. 9. A. R. Djordevic, T. K. Sarkar, and R. F. Harrington, ‘‘Analysis of Lossy Transmission Lines with Arbitrary Nonlinear Terminal Networks,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-34, pp. 660–666, June 1986. 10. J. Kim and J. F. McDonald, ‘‘Transient and Crosstalk Analysis of Slightly Lossy Interconnection Lines for Wafer Scale Integration and Wafer Scale Hybrid Packaging— Weak Coupling Case,’’ IEEE Trans. Circuits Syst., vol. CAS-35, pp. 1369–1382, Nov. 1988. 11. S. P. Castillo, C. H. Chan, and R. Mittra, ‘‘Analysis of N-Conductor Transmission Line Systems with Non-Linear Loads with Applications to CAD Design of Digital Circuits,’’ Proc. Int. Symp. Electromagn. Compat., pp. 174–175, San Diego, CA, Sept. 16–18, 1986. 12. C. S. Chang, G. Crowder, and M. F. McAllister, ‘‘Crosstalk in Multilayer Ceramic Packaging,’’ Proc. IEEE Int. Symp. Circuits Syst., pp. 6–11, Chicago, IL, Apr. 1981. 13. H. R. Kaupp, ‘‘Pulse Crosstalk between Microstrip Transmission Lines,’’ Proc. 7th Int. Electron. Packaging Symp., pp. 1–12, Los Angeles, CA, Aug. 22–23, 1966. 14. J. C. Isaacs, Jr., and N. A. Strakhov, ‘‘Crosstalk in Uniformly Coupled Lossy Transmission Lines,’’ Bell Syst. Tech. J., vol. 52, pp. 101–115, Jan. 1973. 15. G. Ghione, I. Maio, and G. Vecchi, ‘‘Modeling of Multiconductor Buses and Analysis of Crosstalk, Propagation Delay and Pulse Distortion in High-Speed GaAs Logic Circuits,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-37, pp. 445–456, Mar. 1989. 16. H. You and M. Soma, ‘‘Crosstalk Analysis of Interconnection Lines and Packages in HighSpeed Integrated Circuits,’’ IEEE Trans. Circuits Syst., vol. 37, no. 8, pp. 1019–1026, Aug. 1990. 17. A. K. Goel and Y. R. Huang, ‘‘Modelling of Crosstalk among the GaAs-Based VLSI Interconnections,’’ IEE Proc., vol. 136, Pt. G, no. 6, pp. 361–368, Dec. 1989. 18. Y. R. Huang, ‘‘Characterization of Multilevel Interconnections on GaAs-Based VLSI,’’ M. S. Thesis, Michigan Technological University, 1988. 19. P. J. Prabhakaran, ‘‘Analysis of Crossing Interconnections on GaAs-Based VLSICs,’’ M. S. Thesis, Michigan Technological University, 1989. 20. M. K. Mathur, ‘‘Workstation and Microcomputer Analyses of Crossing VLSI Interconnections,’’ M. S. Thesis, Michigan Technological University, 1991. 21. J. A. Davis and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Models—Part I: Single Line Transient, Time Delay and Overshoot Expressions,’’ IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2068–2077, Nov. 2000.

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22. J. A. Davis and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Molels—Part II: Coupled Line Transient Expressions and Peak Crosstalk in Multivel Networks,’’ IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2078–2087, Nov. 2000. 23. R. Venkatesaran, J. Davis, and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Molels—Part III: Transients in Single and Coupled Lines with Capacitive Load Termination,’’ IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 1081–1093, Apr. 2003. 24. R. Venkatesan, J. A. Davis, and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Models—Part IV: Uniﬁed Models for Time Delay, Crosstalk and Repeater Insertion,’’ IEEE Trans. Electron Devices, vol. 50, pp. 1094–1102, Apr. 2003. 25. K. S. Crump, ‘‘Numerical Inversion of Laplace Transforms Using a Fourier Series Approximation,’’ J. ACM, vol. 23, pp. 89–96, Jan. 1976. 26. R. M. Simon, M. T. Stroot, and G. H. Weiss, ‘‘Numerical Inversion of Laplace Transforms with Application to Percentage Labeled Mitoses Experiments,’’ Comput. Biomed. Res., vol. 5, pp. 596–607, 1972. 27. T. Sakurai, ‘‘Closed-Form Expressions for Interconnection Delay, Coupling and Crosstalk in VLSI’s,’’ IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 118–124, Jan. 1993. 28. T. K. Sarkar and J. R. Mosig, ‘‘Comparison of Quasi-Static and Exact Electromagnetic Fields from a Horizontal Electric Dipole above a Lossy Dielectric Backed by an Imperfect Ground Plane,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-34, pp. 379–387, Apr. 1986. 29. J. Siegl, V. Tulaja, and R. Hoffman, ‘‘General Analysis of Interdigitated Microstrip Couplers,’’ Siemens Forsch.-u. Entwickl.-Ber., vol. 10, no. 4, pp. 228–236, 1981. 30. N. Moisan, ‘‘Etude Theorique et Experimentale Des Effets de Propagation dans les Circuits Logiques Rapides,’’ Ph.D. Thesis, Institut National des Sciences Appliquees de Rennes, France, Oct. 1986. 31. N. Moisan, J. M. Floc’h, and J. Citerne, ‘‘Efﬁcient Modelling Technique of Lossy Microstrip Line Sections in Digital GaAs Circuits,’’ Proc. 16th European Microwave Conf., pp. 698–704, 1986.

CHAPTER FIVE

Electromigration-Induced Failure Analysis The term electromigration refers to mass transport in metals under high-stress conditions especially under high current densities and high temperatures. This phenomenon has been studied in different metallizations during the last several years [1–61] and presents a key problem in VLSI circuits since it causes open-circuit and short-circuit failures in the VLSI interconnections. Currently, there is a trend to fabricate VLSI circuits on small chip areas to save space and reduce propagation delays. According to scaling theory for both bipolar and FET circuits, if the chip area is decreased by a factor k, the current density increases by at least the same factor in both cases, and this becomes one of the primary reasons for circuit failure. This chapter is organized as follows: Several factors related to electromigration in the VLSI interconnection metallizations are reviewed in Section 5.1. In this section, the basic problems that cause electromigration are outlined, the mechanisms and dependence of electromigration on several factors are discussed, testing and monitoring techniques and guidelines are presented, and the methods of reducing electromigration in VLSI interconnections are brieﬂy discussed. Various models of IC reliability, including the series model of failure mechanism in VLSI interconnections, are presented in Section 5.2. A model of electromigration due to repetitive pulsed currents is developed in Section 5.3. Electromigration in the copper interconnections under direct current (DC) and alternating current (AC) conditions is discussed in Section 5.4.

High-Speed VLSI Interconnections, Second Edition By Ashok K. Goel Copyright # 2007 John Wiley & Sons, Inc.

313

314

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

The series model has been used to analyze electromigration-induced failure in several VLSI interconnection components, including multipath interconnections, in Section 5.5. A few computer programs available for studying electromigration in VLSI interconnections are discussed brieﬂy in Section 5.6.

5.1

5.1.1

ELECTROMIGRATION IN VLSI INTERCONNECTION METALLIZATIONS: OVERVIEW Problems Caused by Electromigration

As mentioned earlier, smaller chip areas are desirable because device miniaturization has become a continuing trend in VLSI. To obtain a better understanding of the problems associated with electromigration, dimensional scaling and its effects on current density should be considered. Since different devices have different operational principles, scaling theories and problems may differ. For example, when the dimension of an FET device is reduced by a factor k, the time delay per circuit decreases while the power dissipation remains constant and the current density increases by a factor k. In bipolar devices, the scaling structure is nonlinear. Therefore, it is difﬁcult to get a generalized picture of how scaling affects current density. Basic scaling theories for both FET and bipolar devices are summarized in Table 5.1.1. Despite this problem, it is possible to classify the problems caused by electromigration into two categories: geometry- and material-related problems [65–71]. 5.1.1.1 Geometry-Related Problems Geometry-related problems arise as a result of the reduction of interconnection dimensions to the micrometer or submicrometer range. In metal ﬁlms, with grain size about the same or even larger than ﬁlm thickness, the ﬂux generated is conﬁned mainly along grain boundaries. As a consequence, the small number of grains across the line increases the importance of each individual inhomogenous site of the grain structure and its effect on the overall mass ﬂow pattern. That makes each individual divergent site potentially more damaging since a line can fail without requiring a TABLE 5.1.1

Scaling of Device Parameters

Device Parameters

FET [69]

Bipolar [70]

Device dimension Voltage Current Delay time/circuit Power density Line resistance Line current density

1/k 1/k 1/k 1/k 1 k k

1/k

1 1/k 1/k

k k

k2

ELECTROMIGRATION IN VLSI INTERCONNECTION METALLIZATIONS: OVERVIEW

315

statistical linkage of several divergent sites. Another problem concerns the device contacts and step coverages. As the dimensions of device contacts decrease, they become comparable to those of the interconnection lines, thus subjecting them to about the same amount of current densities as the conductor lines. In some cases, the stress generated by the abrupt structural variations in contacts and steps can play an important role in causing their failure. 5.1.1.2 Material-Related Problems Material-related problems are basically caused by the high current densities. Three associated problems in electromigration are referred to as joule heating, current crowding, and material reactions. Joule Heating. As the chip size decreases, heat distribution becomes a serious problem. This is especially true in the case of bipolar VLSI because the power density increases by a factor k when the dimensions decrease by the same factor based on the constant-voltage assumption. For a metal wire that can afford a certain current density rate of about 105 A/m2 s before melting, joule heat generated by current density in the interconnection line exceeding half of this limit must be completely removed through the substrate and/or some passivation layer. Cooling rate has to be faster than the heating rate due to the current density to avoid overheating the line. Therefore, at high current density, say, above 106 A/cm2, any imperfection of the substrate may result in thermal runaway and destroy the line because of inadequate space for heat dissipation. This also results in raising the strip temperature, which accelerates the diffusion process, thus reducing the mean time to failure (MTF). Current Crowding. Current crowding refers to uneven distribution of currents along the metallization lines. It occurs especially in metallizations with structural inhomogeneities. It can alter the local electromigration driving force, thus affecting the mass transport pattern. It can also cause the atoms in the metallization lines to migrate with different velocities, resulting in the formation of voids that cause opencircuit failure. Material Reactions. Material reactions are part of the effects caused by electromigration. As signiﬁcant mass accumulation and depletion occur, the amount of mass transport is signiﬁcant enough to generate enough stress to induce extrusion in the passive layer. It can also change the electrical properties of the junction contacts [71]. Furthermore, the joule heat can suppress or promote any unwanted interfacial material reactions. These problems can alter the device and interconnection characteristics and degrade VLSI reliability [68]. 5.1.2

Electromigration Mechanism and Factors

Much research has been carried out to study the electromigration pattern as well as the factors that affect electromigration [1–64, 72–135]. In this section, the basic mechanisms and associated factors affecting electromigration are discussed.

316

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

5.1.2.1 Mechanism In general, a metallization line consists of an aggregate of metallic ions. These ions are held together by a binding force and opposed by a repulsive electrostatic force. At any given temperature, some of these ions may have sufﬁcient energy to escape from the potential well that binds them in the lattice. When they reach the saddle point of the potential well, they are free from the lattice and become ‘‘activated.’’ The energy needed to achieve this is known as the activation energy. Since a metallization line also contains a certain concentration of vacancies, these ions can diffuse out of the lattice into an adjacent vacancy. This process is known as selfdiffusion. In the absence of an electric current, the self-diffusion process is more or less isentropic; that is, the probability for each nearest ion around the vacancy to exchange with the vacancy is equal. Under no concentration gradient or chemical potential [104, 105], a random rearrangement of individual ions takes place resulting in no mass transportation. Once the current is applied, the situation changes. Now, there are two external forces exerted on the metallization, namely the frictional force and the electrostatic force. The frictional force is due to the momentum exchange with the crystal and its magnitude is proportional to the current density. The electrostatic force is due to the interactions between the electric ﬁelds created by the electrons and the positively charged metallic ions. The electric ﬁeld due to the electrons will attract the positively charged metallic ions toward the cathode against the electron wind and its magnitude, denoted by E, is given by E ¼ rJ

ð5:1:1Þ

where r ¼ density of ions J ¼ current density Because of the presence of ‘‘shielding electrons,’’ the frictional force is always greater than the electrostatic force. Consider a metal strip as shown in Fig. 5.1.1. The frictional force and the electrostatic force are denoted by F1 and F2 , respectively. The frictional force is acting in the direction of the current ﬂow and the electrostatic force is acting against the current ﬂow. The electric ﬁeld E also acts against the current ﬂow. Since F1 is

FIGURE 5.1.1 Frictional and electrostatic forces (F1 and F2, respectively) inside currentcarrying metal strip.

ELECTROMIGRATION IN VLSI INTERCONNECTION METALLIZATIONS: OVERVIEW

317

much greater than F2 , the net force, denoted by F, will be in the direction of the current ﬂow. Deﬁning the direction of the net force being positive, we have F ¼ F1 F2 ¼ ðZ eÞE

ð5:1:2Þ

where Z e is the effective charge assigned to the migrated ion with Z given by [22] Z ¼ Z

rd Nm 1 2rNd m

ð5:1:3Þ

where Z ¼ electron-to-atom ratio rd ¼ defect resistivity Nd ¼ density of defects r ¼ resistivity of metal N ¼ density of metal m ¼ effective electron mass m ¼ free-electron mass The ﬁrst and the second terms in Eq. (5.1.3) correspond to the forces F1 and F2 , respectively. According to the Nernst–Einstein equation, the average drift velocity v is given by v ¼ mF ð5:1:4Þ where m ¼ mobility; ¼ D=fkT D ¼ self-diffusion coefﬁcient, ¼ D0 expðEa =kTÞ f ¼ correlation factor depending on lattice structure; in most cases, f ¼ 1 k ¼ Boltzmann’s constant Ea ¼ activation energy T ¼ absolute temperature The induced ﬂux due to the creation of this frictional force is now given by [94] cA ¼ Nv

ð5:1:5Þ

Combining Eqs. (5.1.1), (5.1.2), (5.1.4), and (5.1.5), we get cA ¼

NDrJ ðZ eÞ fkT

ð5:1:6Þ

or ND0 rJ Ea cA ¼ ðZ eÞ exp kT fkT

ð5:1:7Þ

318

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

In general, cA may not be the same throughout the metallization because of structural inhomogeneities. Such a divergence of ﬂux in the metallization is more likely to occur under high-current-density conditions. If the divergence becomes signiﬁcant, the original isentropic self-diffusion is perturbed and the ions moving along the current ﬂow have a higher probability of exchanging positions with the vacancies. As a result, the original random process changes to a directional process in which the metallic ions move opposite to the electron wind direction while the vacancies move in the opposite direction. The metallic ions condense to form whiskers whereas the vacancies condense to form voids [105–108]. This process results in the change in the density of the metal ions with respect to time. The rate of this change, dN=dt, can be expressed as [33] dN ¼ VdivðcA Þ dt

ð5:1:8Þ

where V is volume and divðcA Þ ¼

dcA dcA dcA þ þ dx dy dz

The formation of voids causes some of the metallization lines to fail, forcing the current to go through the rest of the lines and resulting in an increase in the current density and joule heat. This production of joule heat can increase the local temperature and cause more lines to fail [91]. Furthermore, as the whiskers and hilllocks form, a concentration gradient is produced which may create a stressrelated force enhancing the mass transport process and causing more lines to fail [109–111]. All these processes continue as a loop, shown in Fig. 5.1.2, until the circuit fails to work. The MTF, or t50, is deﬁned as the time taken for 50% of the lines to fail and is given by MTF ¼ AJ n exp

Ea kT

ð5:1:9Þ

where Ea ¼ activation energy J ¼ current density T ¼ temperature, K A ¼ constant depending on geometry and material properties k ¼ Boltzmann’s constant n ¼ constant ranging from 1 to 7 The value of n is stated last because of its variance found in different reference texts and research works [112]. Some of the n values reported in different works are listed in Table 5.1.2. The deviation of n values has been explained as due to the overestimation of joule heating resulting in low values of n and the underestimation

319

ELECTROMIGRATION IN VLSI INTERCONNECTION METALLIZATIONS: OVERVIEW

FIGURE 5.1.2 Schematic of various factors that contribute to electromigration in VLSI interconnection metallizations. (Modiﬁed from [91].)

of joule heating resulting in an apparent very large current density dependence and hence high values of n. In general, the correct value of n should lie between 1 and 2 [124]. If the cross-sectional area A is also taken into account [83], then Eq. (5.1.9) is modiﬁed as Ea n ð5:1:10Þ MTF ¼ AJ exp kT It is also interesting to study the speed of the metallic ions and its relationship to MTF. According to Gimpelson [115], the migration velocity vm can be expressed as Ea vm ¼ GJ exp ð5:1:11Þ kT TABLE 5.1.2

Values of the Exponent n from the Literature

Source Huntington and Grone [21] Attardo [114] Black [83] Blair et al. [54] Chhabra and Ainslie [85] Venables and Lye [90] Sigsbee [88, 89] Vaidya et al. [62] Danso and Tullos [51] Chern et al. [41]

Current Density <0.5 MA/cm2 0.5–1 MA/cm2 0.45–2.88 MA/cm2 1–2 MA/cm2 — — &1 MA/cm2 — 0.168–0.704 MA/cm2 —

n 1 1.5 2þ 6–7 1–3 1 1 2 1.7 2.5 0.5

320

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

where G is a proportionality constant. Combining Eqs. (5.1.10) and (5.1.11), MTF can be expressed as A ðn 1ÞEa ð5:1:12Þ exp MTF ¼ Gn kT ðvm Þn

5.1.2.2 Factors Some known factors that induce electromigration can be classiﬁed as follows. Current Density. Current density is the key factor that contributes to the frictional forces as well as to the ﬂux divergence. At a high current density, the momentum exchange between the current carriers and the metallic ions becomes signiﬁcantly large resulting in a very large frictional force and ﬂux divergence along the metallization lines resulting in mass transport that leads to line failure. It is obvious from Table 5.1.3 that the MTF decreases as the current density increases. This result has been veriﬁed by plenty of research work [1–61, 72–103, 116, 117]. Thermal Effects. Thermal gradients and the line temperature are two other important factors that cause electromigration. It has been reported that the electromigration process occurs in the direction from high temperature to low temperature and that thermal gradients are very important in the electromigration process because these can induce a thermal force that enhances further mass transport in the metallization lines [33, 94, 118, 119]. Thermal gradients are dependent on the metallization structure as well as on the processing techniques. Line temperature is also an important factor in the electromigration process [12, 14, 120–124]. According to Eq. (5.1.9), the MTF decreases with the increase in line TABLE 5.1.3 Dependence of MTF on Current Density for Three Aluminum Film Conductors of Cross-Sectional Area 107 cm2 and Temperature 160 C MTF (h) Current Density (MA/cm2) 0.1 0.2 0.4 0.6 0.8 1.0 2.0 4.0 6.0 8.0

Small Crystallite

Large Crystallite

15,500 4,000 960 450 250 155 40 10 — —

120,000 30,000 7,800 3,300 1,900 1,250 300 75 33 18

Source: Data derived from [83].

Glassed Large Crystallite

65,000 29,000 15,000 11,000 2,700 700 370

ELECTROMIGRATION IN VLSI INTERCONNECTION METALLIZATIONS: OVERVIEW

321

TABLE 5.1.4 Dependence of MTF on Temperature for Three Aluminum Film Conductors of Cross-Sectional Area 107 cm2 and Carrying Current Density 1 MA / cm2 MTF (h) Temperature ( C) 40 60 80 100 120 140 160 180 200 220 240 260

Small Crystallite

Large Crystallite

Glassed Large Crystallite

23,000 7,700 3,000 1,280 580 300 155 90 52 32 21 14

47,000 12,500 3,800 1,250 450 180 80 37 18

50,000 11,000 2,800 800 255 90 34

Source: Data derived from [83].

temperature. This conclusion can also be drawn from Table 5.1.4. In general, if the VLSI system is operating at room temperature under normal conditions, thermal effects can be considered insigniﬁcant. Line Length and Line Width. Table 5.1.5 shows the relationship between the MTF and line length. As mentioned earlier, voids, hilllocks, and whiskers are formed along the interconnection line during electromigration, creating a stress-related force that enhances further electromigration. The magnitude of this force is proportional to the concentration gradient. If the lines are long, the concentration gradient will be much larger, resulting in shorter electromigration lifetime as compared to the shorter lines [125]. Much work has been done to study the effects of line width on the electromigration lifetime as well [126–129]. It has been found that the electromigration lifetime is inversely proportional to line width. This is because, for small line widths, the TABLE 5.1.5 Dependence of MTF on Length of Interconnection Line with Width 2 lm and Median Grain Size 1.25 lm Length (mm) 10 20 30 40 Source: Data derived from [93].

MTF (h) 530 380 325 315

322

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

TABLE 5.1.6 Dependence of MTF on Width of Interconnection Line with Length 25 lm and Median Grain Size 0.75 lm Width (mm) 0.5 1.0 1.5 2.0 2.5

MTF (h) 165 220 270 305 335

Source: Data derived from [93].

cross-sectional area will also be small, resulting in higher current density that may degrade the electromigration lifetime. Experimental data on this relationship are shown in Table 5.1.6. Activation Energy and Material Structure. Activation energy of a metallization line depends on its material structure and, therefore, different metallization lines may have different values of activation energy. For VLSI interconnections, metallizations having high activation energy are desirable because they lead to enhanced stability. Material structure also affects the electromigration lifetime in many ways. Known aspects include grain orientation, grain size, and grain boundaries. Reports have shown that electromigration is related to structural inhomogeneity [33, 35, 36, 124]. An ideal metallization line is the one with uniform grain size and regular grain orientation. Unfortunately, this is not possible and there is always some degree of inhomogeneity that induces ﬂux divergence [131, 134, 135]. As the metallization line becomes more inhomogenous in structure, this ﬂux becomes more divergent, resulting in smaller MTF. Based on the previous studies, it is known that electromigration is conﬁned mainly to the grain boundaries [6, 33, 35, 79, 84]. Smaller grain size means that more grain boundaries are available for electromigration. Table 5.1.7 shows the experimental relationship between grain size and MTF. The fact that smaller grain size degrades the electromigration lifetime has been veriﬁed by many researchers [39, 79, 93]. If the grain size is large enough to TABLE 5.1.7 Dependence of MTF on Median Grain Size for Interconnection Line with Width 1 lm and Length 20 lm Median Grain Size (mm) 1.0 1.5 2.0 2.5 3.0 Source: Data derived from [93].

MTF (h) 245 330 405 460 515

ELECTROMIGRATION IN VLSI INTERCONNECTION METALLIZATIONS: OVERVIEW

323

be comparable to the stripe width, then the single grain can act as a barrier to the migrating atoms [35, 130, 133, 135]. 5.1.3

Electromigration under Pulsed DC and AC Conditions

So far, electromigration under steady-state DC conditions has been discussed. However, it is important to understand electromigration under pulsed DC and AC conditions. Based on recent work, it can be stated that under pulsed DC conditions, MTF is inversely proportional to the duty cycle [89, 136–142]. This can be explained as follows: Equation (5.1.9) shows that MTF is a function of the average value of the steady-state current density. For a periodic current pulse with frequency f, pulse height J, and duty cycle D, the average value of the pulse is given by DJ. Therefore, if D is closer to 1, then the pulse will have a higher average value, resulting in lower MTF. Under pulsed DC conditions, the MTF can be written as MTF ¼ AðDJÞn exp

Ea kT

ð5:1:13Þ

Under AC conditions, at a frequency below the kilohertz range, electromigration is not detected [46]. Using a similar approach as before, a possible explanation for this is that the average value of current density under AC conditions is zero. Therefore, electromigration may not be easily detected. However, the actual explanation is still not well known and further investigation is required. Research work is also required under high-frequency AC conditions, especially in the gigahertz range, to ﬁnd out its impact on the electromigration mechanism. 5.1.4

Testing and Monitoring of Electromigration

Many methods can be used for testing and monitoring electromigration [143–151]. Two techniques used frequently employ resistance measurement and noise measurement though the latter is rather difﬁcult in practice. 5.1.4.1 Resistance Measurement In general, when an open-circuit failure occurs, the resistance goes up, whereas when a short-circuit failure occurs, the resistance goes down. Therefore, by measuring the resistance, one can check whether electromigration has taken place. The MTF can be determined by ﬁnding the time during which the ratio of the change of resistance to the original resistance reaches a certain value. Rodbell and Shatynski used the ratio of 0.5 because this value corresponds to the transition from predominantly electromigration to predominantly thermomigration [144]. A standard method of evaluation for VLSI interconnections using this approach is called accelerated testing, in which high current density and high temperature are applied to the metallization lines [144]. The technique results in the reduction of the complicated testing work and it is widely used in studying electromigration.

324

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

5.1.4.2 Noise Measurement Metal thin ﬁlms generate thermal noise and current noise. The noise voltage spectrum Sðf Þ is given by Sðf Þ ¼ 4kTR þ

k1 V b fa

ð5:1:14Þ

where k ¼ Boltzmann’s constant T ¼ temperature of ﬁlm, K R ¼ resistance of ﬁlm, V ¼ DC voltage applied across ﬁlm, ¼ IR f ¼ frequency 0 k ; a; b ¼ constants characterizing current noise spectrum The ﬁrst term corresponds to the thermal noise and the second term corresponds to the current noise. In most cases, the ﬁrst term is negligible because the current noise dominates. In aluminum ﬁlms, the current noise is relatively small. Therefore, the measurement of current noise may need special attention. In general, the current noise spectral density of continuous metal thin ﬁlms at room temperature follows Hooge’s equation, Sc ðf Þ ¼

gV b gðIRÞb ¼ Nc f a Nc f a

ð5:1:15Þ

where Nc is the total number of free charge carriers in the ﬁlm. For a uniform cross section, Nc is proportional to the volume of the ﬁlm. Therefore, Sc ðf Þ is detectable only in small ﬁlms. For nonuniform cross sections, current density distribution should also be taken into account because the current-crowding effect will cause the noise to increase. Electromigration results in the formation of voids and hillocks and this also leads to a change in the noise level. Using a normal line as a reference denoted by a and the line under test denoted by b, the respective noise voltage spectra can be expressed as

Sa ðf Þ ¼ Ka

ðIRa Þb fa

ð5:1:16Þ

Sb ðf Þ ¼ Kb

ðIRb Þb fa

ð5:1:17Þ

Therefore, the ratio Sb ðf Þ=Sa ðf Þ becomes b Sb ðf Þ Kb Rb ¼ Ka Ra Sa ðf Þ

ð5:1:18Þ

ELECTROMIGRATION IN VLSI INTERCONNECTION METALLIZATIONS: OVERVIEW

325

If this ratio is much larger or smaller than 1, then that implies that electromigration may take place [151]. 5.1.5

General Guidelines for Testing Electromigration

In the literature [92], it has been suggested that the guidelines given below should be followed for the testing procedure. 5.1.5.1 Dimensions of Test Line 1. The test line should have the minimum interconnection width used for that set of the IC family. 2. The length of the test line must be greater than 1 mm to obtain accurate results. 5.1.5.2 Test Line Preparation 1. The current to this test line should be fed by a wider lead (between two to ﬁve times the width) and leads must be greater than 0.125 mm on both sides to reach the bond pads. Long bond pads greater than 1 mm should be avoided because it does not represent typical IC interconnections. 2. The test line fabrication process should simulate the practiced interconnection process for the IC family. For example, the test line should share the same parameters and thickness, go through an identical processing as for the other lines in the IC family, and be packaged in a standard IC package very similar to that used for the IC family. 5.1.5.3 Testing Conditions 1. The thickness data (after ﬁlm deposition and/or lead patterning) coupled with the width of the line should be used to calculate the current density. If a multilayer metal such as a barrier layer/conductor is used, then the cross section of the primary conductor system should be used for the current density calculation. 2. Current density between 0.8 and 1 MA/cm2, depending on the structure of the line, is recommended. 3. High temperature is not recommended because the microstructure properties of the ﬁlm may change at high temperature and that will lead to erroneous results. Besides, thermomigration may also take place. Ambient temperature between 125 and 215 C is recommended. 4. The test temperature should be reported. If the resistance of the leads and the temperature coefﬁcient of resistance are accurately determined, the line temperature may be reported as the test temperature. 5. For the sake of accuracy, sample sizes of 15–20 should be used for testing electromigration at a chosen test temperature.

326

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

5.1.5.4

Calculations and Plots

1. Lognormal probability plots are recommended to determine the MTF and standard deviation. 2. Arrhenius plot of MTF versus 1=T (in Kelvin) with at least three or four data points should be used to determine the activation energy. 3. Since electromigration-induced failures are caused by divergences of atomic ﬂuxes and the atomic ﬂux is directly proportional to the current density, use n ¼ 1 in Eq. (5.1.1) for the MTF at low current densities and n ¼ 2 for optimistic estimates of MTF at operating temperatures and at current densities less than 1 MA/cm2. Use n ¼ 1:5 when electromigration test data are collected at 1 MA/cm2 and have to be extrapolated to current densities in the range 0.1–0.6 MA/cm2. Three current densities in the range 0.6–1.2 MA/cm2 may be used to determine the value of the exponent n. 4. Failure times are assumed to obey a lognormal distribution: " # 1 1 lnðtÞ lnðt50 Þ 2 f ðtÞ ¼ exp st 2 s

ð5:1:19Þ

The instantaneous failure, by deﬁnition, corresponds to the decrease in the number of surviving samples at time t and is given by lðtÞ ¼

f ðtÞ 1 FðtÞ

ð5:1:20Þ

where the cumulative failure density function FðtÞ ¼

Z

t

f ðtÞdt

ð5:1:21Þ

0

corresponds to the probability of failure in total time t. From the above equations, it is obvious that the failure rate increases with time and reﬂects the true wear-out mechanism of the interconnection due to electromigrationinduced damage. 5. If the conductor crosses an oxide step, a thinning step for ﬁlm thickness should be determined and the minimum cross section of the conductor at the oxide side should be used to calculate the maximum current density. 6. If a pulsed current is used for testing, then the peak current or the maximum current pulse height in a lead should be used for the current density calculation and to ﬁnd the MTF. If a transient is present, similar corrections are recommended. 7. Since reliability of the ﬁlm interconnection is determined by its microstructure and alloy composition, detailed test procedures should be established

ELECTROMIGRATION IN VLSI INTERCONNECTION METALLIZATIONS: OVERVIEW

327

to characterize the as-deposited and annealed ﬁlms. Routine process control procedures should be followed to verify that the ﬁlm properties are reproduced. 5.1.6

Reduction of Electromigration

There has been much effort in order to achieve the reduction of electromigration in VLSI interconnections [152–170]. The most common solutions are summarized below. 5.1.6.1 Substrate Overcoating The basic reason for overcoating the substrate is to prevent the formation of vacancies needed for diffusion and to presumably ﬁll up the broken bonds on the surface of the metallization [73, 79, 116, 152–159, 170]. This is also called passivation. With the addition of a passivation layer, the joule heat can be dissipated more easily. In order to form a passivation layer, the substrate is basically sealed hermetically by the overcoating layer. The materials mostly used are oxides such as SiO and anodic oxides as well as dielectric layers such as Al2O3–SiO2 and P2O5–SiO2. This technique has proven to be effective in improving electromigration lifetimes [12, 87]. It has been further shown that the increase in thickness of these layers increases the electromigration lifetime as long ˚ [154, 160–162]. as the thickness does not exceed 6000 A 5.1.6.2 Alloying of Metallization Addition of the correct type and concentration of alloys has also been shown to improve the electromigration lifetime [163, 164, 166, 170]. For example, it has been shown that addition of Ti–Si to Al increases the electromigration lifetime by more than an order of magnitude whereas addition of Cr–Si does not show any noticeable improvement [47]. Other reports have shown that addition of 0.4% Cu to Al with or without addition of Si results in better electromigration lifetimes than pure Al [38, 156, 158, 159]. The reason for this is that by adding the proper concentration of correct impurities into the original metallization line, the structure of the line changes substantially and this results in improvement of electromigration lifetimes [156–159]. However, one of the major problems is the increase in resistance after alloying. This has been demonstrated by adding manganese to the aluminum and Al–Cu metallizations [156]. In short, alloying with Cu (typical levels of 0.5, 1, 2, and 4% have been widely used and reported) has been the industry standard for many years. However, Cu is very hard to etch dry for VLSI applications. This has resulted in an interest in Al/Ti and Al/Si/Ti alloys as alternatives. 5.1.6.3 Encapsulated Multilayer Interconnections Encapsulation has the effect of preventing the formation of hillocks. It can be done by using refractory metals and a spacer technology. The refractory metal is deposited by biased sputtering and by anisotropic etching of the material. Several layers of the refractory metal are deposited to ensure reliability. Another way to achieve

328

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

encapsulation is to form a native oxide layer on the interconnection [160]. In order to be effective, the native oxide has to be thick enough compared to the ﬁlm thickness to ensure the removal of hillocks. This approach has also been shown to improve electromigration lifetimes [161, 162]. 5.1.6.4 Gold Metallization It has been shown that a gold-based interconnection system has a much better MTF than aluminum ﬁlms [163]. The key reason for this is that gold has a very high activation energy. In particular, at high current densities and high temperature operations, gold interconnections have shown a better performance. In general, gold can be deposited by vacuum evaporation techniques. However, because of its inert nature, adhesion of gold to the insulating layer by chemical bonding is extremely difﬁcult. Therefore, gold has to be used in a multilayer system where more than one layer of metallization is used to adhere to the insulator as well as to gold. 5.1.6.5 Deposition Techniques It has been shown that the MTF of a VLSI system has a close relationship with the employed deposition technique [164, 167, 168]. For example, it is found that the MTF is smaller for the sputtered ﬁlm technique than the e-beam technique [165]. One possible explanation may be that different deposition techniques may change the defect structure of a metallization and may change the electromigration pattern.

5.2

MODELS OF IC RELIABILITY

Reliability of an IC is a measure of the promise that it will carry out its function correctly during a given time period. Generally, it is expressed graphically by the bathtub curve shown in Fig. 5.2.1. The portion of the curve depicting high failure rates at small times is called the infant mortality phase and accounts for the major built-in ﬂaws in the components. The portion of the curve depicting high failure rates

FIGURE 5.2.1

Bathtub curve showing failure rate as function of time.

MODELS OF IC RELIABILITY

329

at large times is called the wear-out phase and accounts for the actual wear-out of the components. The rest of the curve deﬁnes the operating life of the IC. In general, the reliability of an IC can be enhanced by using better design techniques for its components, employing better manufacturing methods, using more stringent screening procedures, and providing redundancy within the IC so that it will perform its assigned function even if some of its components do actually fail. Several mathematical models to predict the reliability of an IC or components thereof have been proposed in the literature. 5.2.1

Arrhenius Model

Several physical mechanisms which result in device failure can be modeled by the Arrhenius relationship, expressed as lðTÞ ¼ lðT0 Þ exp

Ea 1 1 k T0 T

ð5:2:1Þ

where T ¼ temperature, K T0 ¼ reference temperature, K lðTÞ ¼ failure rate at temperature T Ea ¼ activation energy for failure mechanism, eV k ¼ Boltzmann’s constant, eV/K Relationship (5.2.1) indicates that a physical mechanism having a lower activation energy results in a higher failure rate. The same is true for systems at higher operating temperatures. 5.2.2

Mil-Hdbk-217D Model

This semiempirical model is based on the measured lifetimes of a large number of devices after screening. It states that the failure rate l in units of failures per 106 h can be predicted by the expression [171] l ¼ Q ½C1 T V þ ðC2 þ C3 ÞE L

ð5:2:2Þ

where Q is a quality factor dependent on the burn-in procedure used to remove devices suffering from built-in problems, T is an acceleration factor dependent on the operating temperature, V is a stress factor dependent on the operating voltage, E is a factor dependent on the environment, L is a learning factor, and C1 , C2 , and C3 are failure rates dependent on the complexity of the system expressed by the number of equivalent gates, number of pins, package type, and so on. Values of C1 , C2 , and C3 depend on the devices and their technologies and have been tabulated for several cases in [171]. The Mil-Hdbk-217D model is a widely used model and the data for this model have been constantly under revision to include new devices and technologies.

330

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

5.2.3

Series Model

A series model for calculating the reliability of an IC due to wear-out has been presented by Frost and Poole [172]. It is based on the assumptions that an IC consists of several basic elements that are not necessarily identically distributed, the states of the various elements with respect to their being functional or failed are mutually statistically independent, the failure distribution of each element is known a priori, and the failure of any one element of the series system causes the IC to fail. The failure rate ls of a system of n elements having failure rates li ði ¼ 1; 2; 3; . . . ; nÞ can be found by adding the failure rates of the elements, that is, ls ðtÞ ¼

n X

li ðtÞ

ð5:2:3Þ

i¼1

If the n elements are identical, that is, l1 ðtÞ ¼ l2 ðtÞ ¼ ¼ ln ðtÞ ¼ lðtÞ then Eq. (5.2.3) reduces to ls ðtÞ ¼ nlðtÞ

ð5:2:4Þ

The probability of failure function Fs ðtÞ of a series system can be determined using the formula Fs ðtÞ ¼ 1

n Y ½1 Fi ðtÞ

ð5:2:5Þ

i¼1

where Fi ðtÞ is the probability of the failure function for the ith element. The series model can be used to predict the reliability of a system with respect to any of the physical processes which cause wear-out. These include interconnection metallization failure due to electromigration or corrosion, oxide shorts, threshold voltage shifts in MOS devices, and alpha-particle-induced soft errors. A physical process can cause two types of defects which result in the failure of the system: structural defects and performance defects. A structural defect represents an abrupt change in the circuit topology such as the one caused by open circuiting of a conductor. A performance defect represents a continuous degradation of the system until its operation performance falls below an acceptable level. The series model treats these two defects in the same way. 5.2.4

Series–Parallel Model

As shown in the next section, an interconnection or a component thereof can be modeled as a series–parallel combination of several straight segments. Then, the

MODELING OF ELECTROMIGRATION DUE TO REPETITIVE PULSED CURRENTS

331

probability of failure as a function of time, that is, Fsp ðtÞ, can be determined by the expression Fsp ðtÞ ¼½1 f1 F11 ðtÞgN11s f1 F12 ðtÞgN12s f1 F1n ðtÞgN1ns N1p ½1 f1 F21 ðtÞgN21s f1 F22 ðtÞgN22s f1 F2n ðtÞgN2ns N2p ½1 f1 Fm1 ðtÞgNm1s f1 Fm2 ðtÞgNm2s f1 Fmn ðtÞgNmns Nmp

ð5:2:6Þ

where the total number of parallel units is equal to N1p þ N2p þ þ Nmp , Nmp is the number of identical parallel units in the mth set and the total number of identical series units in the mth set of parallel units is equal to Nm1s þ Nm2s þ þ Nmns . The function Fmn ðtÞ in Eq. (5.2.6) is the probability of the failure function for the nth unit of the mth set. For a series system of Ns identical units, Eq. (5.2.6) reduces to Fs ðtÞ ¼ 1 ½1 FðtÞNs

ð5:2:7Þ

in agreement with Eq. (5.2.5). For a parallel system of Np identical units, it becomes Fp ðtÞ ¼ ½FðtÞNp

5.3

ð5:2:8Þ

MODELING OF ELECTROMIGRATION DUE TO REPETITIVE PULSED CURRENTS

In the past, most of the work on electromigration effects in VLSI interconnections has been limited to steady (direct) currents and the chip design rules have been based on these DC models. However, most VLSI devices are now digital and use unipolar or bipolar pulsed currents throughout the chip. In a few modeling efforts [138, 142] and experimental studies [136–140] concerned with pulsed or alternating currents, the pulsed current guidelines have been developed from the DC design rules by substituting the average current density of the pulsed current for the DC density. In other words, if r denotes the duty factor of the pulsed current of density Jp (assumed constant), then the corresponding DC density Jdc is given by Jdc ¼ rJp

ð5:3:1Þ

In principle, according to Eq. (5.3.1), current density Jp can be increased in direct proportion as the duty factor r is decreased with no effect on the design rules. This is simply not true in all cases. In this section, a simulation model for the major physical processes that inﬂuence electromigration-induced damage in interconnections due to pulsed electric currents [173] is presented. It should be noted that experimental veriﬁcation of the model is required before its predictions can be used in design guidelines.

332

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

5.3.1

Modeling of Physical Processes

An expression that adequately describes the mass ﬂow rate due to an electrical current density is Ja ¼

ND ðZ qÞE kT

ð5:3:2Þ

where Ja ¼ atomic ﬂux, atoms/cm2/s N ¼ number of metallic ions, cm3 D ¼ diffusion coefﬁcient, cm2/s k ¼ Boltzmann’s constant, J/K T ¼ temperature, K Z ¼ effective mobile ion charge number q ¼ electronic charge; ¼ 1:6 1019 C E ¼ electric ﬁeld strength, V/cm In Eq. (5.3.2), the divergence of metallic ion ﬂux due to geometric conditions, microstructural conditions, thermal conditions, or any combination thereof can be expressed in terms of the mass continuity equation @N þ r Ja ¼ 0 @t

ð5:3:3Þ

Further, the effect of local heating on the movement of metal atoms can be included in terms of the temperature dependence of the diffusion coefﬁcient D in Eq. (5.3.2) given by D ¼ D0 eEa =ðkTÞ

ð5:3:4Þ

where D0 is a numerical factor independent of temperature and Ea is the activation energy whose value depends on the predominant manner of diffusion. It should be noted that the rate of electromigration-induced degradation of the interconnection line is also inﬂuenced by the mechanical stress generated by the difference in thermal expansion coefﬁcients and mechanical properties such as elastic moduli of the line and its surrounding material. To account for the physical factors present in a complex system consisting of the interconnection line, its dielectric overcoating, its dielectric undercoating, and the substrate, Eq. (5.3.2) should be modiﬁed to Ja ¼

ND ðrUÞ kT

ð5:3:5Þ

MODELING OF ELECTROMIGRATION DUE TO REPETITIVE PULSED CURRENTS

333

where U is the electrochemical potential which, as a ﬁrst approximation, should be taken as N þ Snm þ m0 ð5:3:6Þ U ¼ Z qV þ kT ln N0 where V ¼ electric potential, V N0 ¼ equilibrium metal ion concentration at reference condition, number/m3 ¼ atomic volume, m3, Snm ¼ mechanical stress, N/m2 m0 ¼ reference chemical potential, J Substituting Eq. (5.3.6) in Eq. (5.3.5), we get ND kT Z qE ðrNÞ rðSnmÞ Ja ¼ kT N

ð5:3:7Þ

Equation (5.3.7) states that the electric force caused by the exchange of momentum between the electrons and the metallic ions is opposed by the diffusion force caused by the nonequilibrium ion concentration differences and the mechanical force caused by the longitudinal pressure differences. Now, as done previously [90], we can deﬁne a term P called Porosity as the local incremental change in metal ion concentration given by the expression @P 1 @N ¼ @t N @t

ð5:3:8Þ

Combining Eqs. (5.3.3) and (5.3.5), dividing the resulting equation on both sides by N, and substituting in Eq. (5.3.8), we obtain @P 1 ND ¼ r ðrUÞ @t N kT

5.3.2

ð5:3:9Þ

First-Order Model Development

First, we assume that the grain sizes in the interconnection line follow a lognormal distribution characterized by a median value D50 and standard deviation s. Next, for an interconnection line of length L, we divide it into Nl segments of equal length D50 , that is, Nl ¼ L=D50 , where Nl is taken as the nearest integer value. Further, if W is the width of the interconnection line, we partition it into Nw parallel strips of width D50 each with some remaining strip of width less than D50 such that Nw ¼ W=D50 , where Nw is taken as the larger nearest integer. For a line of width less than D50 , Nw ¼ 1.

334

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

Thus, each interconnection segment of length D50 has Nw locations or nodes where mass ﬂux divergence is possible. The mass ﬂux divergence factor Df at each node deﬁned by the indices ðk; lÞ with 1 k Nl and 1 l Nw can now be calculated from the relationship

Df ðk; lÞ ¼

X i

X yj yi cosðfi Þ cosðfj Þ sin sin 2 2 j

ð5:3:10Þ

where f is the random grain boundary angle with respect to the longitudinal centerline of the metallization line for each grain boundary on either side of each node and is another random angle selected for each grain boundary on either side of the node used to calculate a mobility factor for mass transfer along the grain boundary [135]. The divergence of the metal ion ﬂux at the node ðk; lÞ can now be calculated from

ND Df ðk; lÞ ðrUÞ r Ja ðk; lÞ ¼ D50 kT

ð5:3:11Þ

where, as a ﬁrst-order approximation, it is assumed that the electric ﬁeld, mobile metallic ion concentration gradient, and longitudinal pressure gradient are appropriately averaged macroscopic quantities and, therefore, the forcing function terms in the factor U can be regarded as constants with respect to the divergence operation. The rate of porosity development at the node ðk; lÞ is then given by @P D0 Df ðk; lÞ ½eEa =ðkTÞ ðrUÞ ¼ D50 kT @t

ð5:3:12Þ

and the increment of porosity ðPÞ developed at node ðk; lÞ over an increment of time ðtÞ can be obtained from

@P t Pðk; lÞ ¼ @t

ð5:3:13Þ

The calculation of P in Eq. (5.3.13) needs an evaluation of every force term in rU. The ﬁrst force term in rU is due to the electric ﬁeld E and is equal to Z qE. Including the effect of local current crowding due to the development of porosity [2] at node ðk; lÞ, the local value of the electric ﬁeld E is given in terms of the local current density J by the expression E ¼Jr¼

J0 r0 ½1 þ afTðkÞ Ta g 1 Pðk; lÞ

ð5:3:14Þ

MODELING OF ELECTROMIGRATION DUE TO REPETITIVE PULSED CURRENTS

335

where J0 ¼ initial current density uniform throughout undamaged interconnection line, A/cm2 r0 ¼ initial electrical resistivity of interconnection metal at temperature Ta ; cm a ¼ temperature coefﬁcient of resistivity TðkÞ ¼ local temperature at boundary of kth segment Ta ¼ ambient temperature It should be noted that the porosity factor 1=½1 Pðk; lÞ in Eq. (5.3.14) is used only for Pðk; lÞ > 0. Further, for a continuous train of unipolar current pulses applied to the interconnection line resulting in local current density pulses of amplitude Jp for a duration of d seconds with a repetition period of seconds, the duty factor r of these pulses is given by r¼

d

ð5:3:15Þ

resulting in a local power dissipation of rrðJp Þ2 . This heat ﬂows away from the interconnection line longitudinally by thermal conduction and transversally through a dielectric layer (such as silicon dioxide) to the substrate (such as silicon) acting as a heat sink assumed to be at the constant ambient temperature Ta . This heat ﬂow is given in terms of the local temperature TðkÞ by the equation rrðJp Þ2 ¼

Km ðD50 Þ

2

½TðkÞ Tðk lÞ þ

K0 Km ½TðkÞ Ta þ ½TðkÞ Tðk þ lÞ d0 dm ðD50 Þ2 ð5:3:16Þ

where Km ¼ thermal conductivity of interconnection metal, W/(cm K) K0 ¼ thermal conductivity of dielectric layer, W/(cm K) d0 ¼ thickness of dielectric layer, cm dm ¼ thickness of interconnection metal, cm. The next force term in rU is due to diffusion and can be considered as equivalent to the force exerted by a threshold electric ﬁeld Eth, that is, Z qEth ¼

kT 1 Fg ln 1 Fl L

ð5:3:17Þ

where L ¼ length of interconnection line, cm Fg ¼ fractional mass gain along line (corresponding to negative porosity) Fl ¼ average fractional mass loss along line (corresponding to positive porosity)

336

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

The last force term in rU is due to a pressure gradient along the length of the line and is caused by the transfer of mass by the electromigration and the tendency to accumulate mass at various places along the line. It can be approximated by dSnm V0 1 1 N ¼ ð5:3:18Þ dx N0 L b N0 which has been obtained by putting the approximate expression for the bulk compressibility 1 dV b¼ ð5:3:19Þ V0 dS into its incremental form S ¼

1 V b V0

ð5:3:20Þ

and combining it with the relation between volume increase and mass increase V N ¼ V0 N0

ð5:3:21Þ

In terms of the average fractional mass gain Fg , Eq. (5.3.18) can be rewritten as

dSnm ¼ dx

V0 N0

Fg bL

ð5:3:22Þ

Substituting the force terms given by Eqs. (5.3.14), (5.3.17), and (5.3.22) into Eqs. (5.3.12) and (5.3.13), the increment of porosity ðPÞ developed over an increment of time ðtÞ can be obtained from

D0 Df ðk; lÞ ½eEa =½kTðkÞ Pðk; lÞ ¼ D50 kTðkÞ "

r 1 Pðk; lÞ # kTðkÞ 1 Fg V0 Fg ln 1 Fl N0 bL L Z qj0 r0 f1 þ a½TðkÞ Ta g

ð5:3:23Þ

It should be noted that a factor r has been inserted in the electric force term because this force is applied for a fraction of the time only whereas the diffusion and pressure gradient force terms are present at all times. Further, the time increment ðtÞ can be larger than or equal to one pulse repetition period .

MODELING OF ELECTROMIGRATION DUE TO REPETITIVE PULSED CURRENTS

337

In general, the failure criterion for the interconnection line can be stated in terms of the attainment of maximum tolerable fractional increase in the line resistance, elevation of the temperature at a node to the melting point of the interconnection metal, or the attainment of pressure level at any point along the line that exceeds the strength of the covering layer, if present. In this section, the results are calculated using the fractional change in the line resistance ðR=R0 Þ as an indicator of the progress of electromigration-induced damage and it is calculated using the expression 2 3 X 7 R 1 6 1 6 7 ð5:3:24Þ ¼ X 4 5 R0 Nl Nw =½1 Pðk; lÞ k l

where only a loss of mass is considered to affect the line resistance, that is, Pðk; lÞ is taken to be zero for those nodes where there is an accumulation of mass. 5.3.3

Modeling Results for Direct Currents

In order to validate the physical factors included in the simulation model presented above, the simulation results obtained using the model can be compared with experimental observations of various workers. In the following results, values of the parameters used in the model are taken as follows: constant factor in diffusion coefﬁcient ðD0 Þ ¼ 104 cm2/s, effective charge on metal ion ðZ Þ ¼ 1, activation energy for diffusion ðEa Þ ¼ 0:67 eV (typical of Al–Cu alloys), bulk compressibility ðbÞ ¼ 1:33 1011 m2/N (for Al), and thermal conductivity of oxide layer ¼ 0.0096 W/cm C. In addition, the Wiedemann–Franz law is used for the thermal conductivity of the interconnection metal and the temperature dependence for the metal resistivity is taken to be given by r ¼ 2:42 106 ½1 þ 0:00475ðT 273Þ cm

ð5:3:25Þ

The effect of an oxide coating in reducing the rate of electromigration in an interconnection line of length L ¼ 50 mm, width W ¼ 2 mm with D50 ¼ 2mm, and s ¼ 0:5 carrying a direct current of density J ¼ 1 MA/cm2 at temperature T ¼ 200 C is shown in Fig. 5.3.1. This ﬁgure shows that time at which the line resistance begins to rise very rapidly increases nearly six times for the coated line (shown by circles) than with the uncoated line (shown by squares). Such a signiﬁcant rise in the time to failure for coated lines has been observed experimentally by many workers. Using a failure criterion of 10% resistance change, the effect of line length on failure time is shown in Fig. 5.3.2. The line parameters are W ¼ 2 mm, D50 ¼ 2 mm, and s ¼ 0:5 subjected to a direct current of J ¼ 1 MA/cm2 at T ¼ 200 C. Squares indicate the results based on the present model while circles indicate those calculated from the statistical model presented in [125]. This ﬁgure shows that lifetime increases rapidly as the line gets shorter, which is in agreement with experimental observations.

338

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

FIGURE 5.3.1 Simulation results showing effect of oxide coating on rate of development of electromigration-induced line failure. (From [172]. # 1988 by IEEE.)

The simulation results showing the dependences of the median failure time on the normalized width ðW=D50 Þ for 20 lines with L ¼ 50 mm subjected to a direct current of J ¼ 1 MA/cm2 at T ¼ 200 C are shown in Fig. 5.3.3. For the upper curve (with squares), D50 ¼ 3 mm and s ¼ 0:5; for the middle curve (with circles), D50 ¼ 2 mm and s ¼ 0:5; and for the lower curve (with triangles), D50 ¼ 1 mm and s ¼ 0:5. All curves indicate a minimum at about W=D50 ¼ 1, which is in agreement with the observations of Kinsbron [126].

FIGURE 5.3.2 Simulation results showing effect of line length on failure time. (From [172]. # 1988 by IEEE.)

MODELING OF ELECTROMIGRATION DUE TO REPETITIVE PULSED CURRENTS

339

FIGURE 5.3.3 Simulation results showing effect of line width on failure time. (From [172]. # 1988 by IEEE.)

The effect of the DC density on the failure time is shown in Fig. 5.3.4. The upper curve (with squares) is for a line of length 50mm and activation energy 0.67 eV (characteristic of Al–Cu alloys) with both ends kept at the ambient test temperature of 200 C and an oxide thickness of 1mm with the substrate held at ambient temperature. The medium curve (with circles) shows the effect of allowing the ends of the line to ﬂoat, that is, adiabatic end conditions. The lower curve (with triangles) is for a 200-mm line having activation energy of 0.55 eV (characteristic of Al–Si lines) with adiabatic

FIGURE 5.3.4 Simulation results showing effect of DC density on failure time. (From [172]. # 1988 by IEEE.)

340

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

end conditions. The upper, middle, and lower curves correspond to 1.2, 1.5, and 1.5 power dependences upon the DC densities, respectively. These values agree very well with experiments. 5.3.4

Modeling Results for Pulsed Currents

For pulsed current following the relation Jp ¼ Jdc =r with Jdc ¼ 1 MA/cm2 (typical of accelerated testing of electromigration), percent changes in line resistance as a function of elapsed stress time for r values of 0.03125, 0.0625, 0.125, 0.25, 0.5, and 1.0 are shown in Fig. 5.3.5. The value of r ¼ 1:0 corresponds to the DC case. For these results, both ends of the lines are kept at the ambient temperature of 200 C and the values of the line and other parameters are L ¼ 50mm, W ¼ 2 mm, D50 ¼ 2 mm, s ¼ 0:5, and T ¼ 200 C. Figure 5.3.5 shows that, for very short duty cycles, there is a signiﬁcant decrease in the time at which the line resistance begins to increase rapidly. Assuming a more general relationship between the DC density and peak current density given by Jp ¼

Jdc rm

ð5:3:26Þ

where m is a constant in the range 0–1, the dependences of the times required to reach 3% change in the line resistance on the duty factor r for values of m ¼ 0:5, 0.666, 0.75, 0.85, 1.0 (for curves from top to bottom) are shown in Fig. 5.3.6. These results assume a 1-mm-thick oxide layer with the surface below the oxide and the

FIGURE 5.3.5 Simulation results showing effect of peak current density on failure time for various values of r. (From [172]. # 1988 by IEEE.)

ELECTROMIGRATION IN COPPER INTERCONNECTIONS

341

FIGURE 5.3.6 Simulation results showing effect of duty factor exponent on failure time. (From [172]. # 1988 by IEEE.)

ends held at the ambient temperature. It should be noted that, for Jp given by Eq. (5.3.26), the local power dissipation is given by rrðJp Þ2 ¼ rr

2 Jdc rðJdc Þ2 ¼ rm r 2m1

ð5:3:27Þ

which shows that, at a 5% duty cycle ðr ¼ 0:05Þ, there is 20 times as much power dissipation as in the DC case ðm ¼ 1:0Þ but only about 11 times as much power dissipation when m ¼ 0:9.

5.4

ELECTROMIGRATION IN COPPER INTERCONNECTIONS

Because of its lower resistivity and potentially superior electromigration properties, copper has emerged as an alternative to aluminum or aluminum-based alloy interconnections particularly for submicrometer IC technologies. Electromigration characteristics of copper interconnections with minimum interlayer barrier metal thickness have been studied by Tao et al. [174]. They have also compared the performance of copper interconnections with those made with Al–4%Cu/TiW and Al–2%Si under DC, high-frequency pulsed DC, and low-frequency bipolar current stressing conditions. 5.4.1

Electromigration under DC Conditions

Figure 5.4.1 shows the Arrhenius plots of the MTF of interconnections made from electroless plated Cu, Al–2%Si, and Al–4%Cu/TiW versus 1000=T under a DC

342

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

105 104

Ea=0.77eV

MTTF (h)

103 Ea=0.57eV

102 101

Ea=0.42eV

100 Al-2%SI Al-4%Cu/TiW Cu

10–1 10–2

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 1000/T (°F)

FIGURE 5.4.1 Arrhenius plots of MTF versus 1000/T for Cu, Al–4%Cu/TiW, and Al–2%Si interconnections under DC density of 1:5 107 A=cm2 . (From [174]. # 1993 by IEEE.)

density of 1:5 107 A/cm2. This ﬁgure shows that the MTF for the electroless plated Cu interconnections is about one and two orders of magnitude longer than those for Al–4%Cu/TiW and Al–2%Si interconnections, respectively. Activation energies of these materials can be derived from the slopes of the Arrhenius plots. These can be determined to be 0.77 eV for electroless plated Cu, 0.42 eV for Al–2%Si, and 0.57 eV for Al–4%Cu/TiW. Using these activation energies, it can be extrapolated that at 75 C the Cu interconnection lifetimes are about three and ﬁve orders of magnitude higher than those of Al–4%Cu/TiW and Al–2%Si interconnections, respectively. 5.4.2

Electromigration under Pulsed DC Conditions

Figure 5.4.2 shows the dependences of the MTF for Cu, Al–2%Si, and Al–4%Cu/ TiW interconnections on the frequency of the pulsed direct current with a peak current density of 1:5 107 A/cm2 at 275 C. This ﬁgure shows that the MTF for the Cu interconnections is about one and two orders of magnitude longer than those for the Al–4%Cu/TiW and Al–2%Si interconnections, respectively, for all frequencies. The MTF values predicted by the vacancy relaxation model [175] are also included in this ﬁgure and are shown by solid lines. Defect relaxation time t is a ﬁtting parameter in this model and its value can be found to be about 0.2 ms for Cu interconnections, about 15 ms for Al–4%Cu/TiW interconnections, and about 20 ms for Al–2%Si interconnections [174]. 5.4.3

Electromigration under Bipolar AC Conditions

A comparison of the change in resistance of the Cu interconnections under a DC density of 1:5 107 A/cm2 with that under a 1-MHz bipolar symmetrical rectangular

ELECTROMIGRATION IN COPPER INTERCONNECTIONS

343

101 τ = 0.2µs

MTFPulse-DS h

100 τ = 15µs 10–1 τ = 20µs

Cu Al-4% Cu/TiW Al-2% Si

10–2

Model 10–3 100

101

102

103 104 105 Frequency(Hz)

106

107

108

FIGURE 5.4.2 Dependences of MTF on frequency for Cu, Al–4%Cu/TiW, and Al–2%Si interconnections under pulsed DC peak current density of 1:5 107 A=cm2 at 275 C. (From [174]. # 1993 by IEEE.)

current waveform with 1:5 107 A/cm2 current density at 275 C is shown in Fig. 5.4.3 [174]. This ﬁgure shows that under DC conditions the interconnection shows an open-circuit failure after about 3.4 h whereas no failure is detected under AC conditions for even up to about 350 h. Similar results indicating no failure under AC conditions have also been shown for the Al–2%Si and Al–4%Cu/TiW interconnections. This has been attributed to the healing effects of electromigration-induced

101

R/R0

DC case

100 Ac case Cu line 275°C, J=1.5×107A/cm2 10–1 –1 10

100

100

102

103

Time (h)

FIGURE 5.4.3 Normalized resistance for Cu interconnections versus time under DC density of 1:5 107 A=cm2 and under 1-MHz bipolar current of peak current density of 1:5 107 A=cm2 at 275 C. (From [174]. # 1993 by IEEE.)

344

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

1.012 Reverse

Forward 1.010

Forward

Reverse

Blpolar Stressing

R/R0

1.008 1.006 1.004 Cu line

1.002

275°C, 9.0×106A/cm2

1.000 0

1

2

3

4

5

Time (h)

FIGURE 5.4.4 Normalized resistance for Cu interconnections versus time under lowfrequency bipolar current of peak current density of 9:0 106 A=cm2 at 275 C. (From [174]. # 1993 by IEEE.)

damage under the two opposite halves of the AC cycle. This assertion has been further veriﬁed under low-frequency AC conditions. The change in resistance versus time for Cu interconnections under a bipolar current waveform with peak current densities of 9:0 106 A/cm2 of nearly a 2-h time period is shown in Fig. 5.4.4. This ﬁgure clearly shows a damage recovery behavior under opposite current cycles though it shows an overall increase in resistance with successive cycles.

5.5

FAILURE ANALYSIS OF VLSI INTERCONNECTION COMPONENTS

In general, an interconnection line on an IC chip consists of several components such as straight segments, bends, steps, plugs, and vias. In addition, there are power and ground buses serving several logic gates on the chip. For submicrometer width lines, there may be sections along the line length suffering from material overﬂows. Recently, a multipath interconnection has been introduced which differs from a standard interconnection in that a driver and its load are connected by more than one path for the current/voltage signal to ﬂow [176]. In this section, electromigrationinduced failure of the various interconnection components is analyzed. 5.5.1

Reduction of Components into Straight Segments

First, a straight interconnection segment, shown in Fig. 5.5.1a, of length L, width W, and thickness T carrying a current I at a given temperature has been analyzed. Then,

345

FAILURE ANALYSIS OF VLSI INTERCONNECTION COMPONENTS

by considering the effects of the average ﬂux density on the grain boundary migration in the other interconnection components, we have reduced them to a series–parallel combination of equivalent straight segments. The average ﬂux density in a component is determined using the interconnection current I and the average cross-sectional area throughout the component. The additional area in an interconnection bend of angle yB , shown shaded in Fig. 5.5.1b, can be found equivalent to a straight segment of length LB and width WB given by the expressions

LB ¼

WB ¼

pWj180 yB j 360 pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ W 2 1 þ tanðyB =2Þ

ð5:5:1Þ

W þ LB

For a bend angle of 90 , expressions (5.5.1) yield values in agreement with those derived by Frost and Poole [172]. An interconnection line of length L, width W, and thickness T having a single step of height H and angle yS , shown in Fig. 5.5.1c, is equivalent to three straight segments each of width W, lengths LS1 , LS2 , and LS3 , and thicknesses TS1 , TS2 , and TS3 , respectively, given by the expressions

LS3 ¼

LS1 ¼ L þ

H tan yS

TS1 ¼ T

LS2 ¼ T cos yS þ

H sin yS

TS2 ¼ T cos yS

pTð180 yS Þð1 cos yS Þ 720

TS3 ¼

ð5:5:2Þ

T 2 ½1 þ cos yS ðcos yS sin yS Þ 2LS3 þ Tð1 cos yS Þ

Two straight sections of an interconnection line of total length L, width W, and thickness T joined by a single plug of length H and square dimension WP , shown in Fig. 5.5.1d, is equivalent to three straight segments of lengths LP1 ; LP2 , and LP3 , widths WP1 , WP2 , and WP3 , and thicknesses TP1 , TP2 , and TP3 , respectively, given by the expressions LP1 ¼ L WP LP2 ¼ H LP3 ¼ 18pðT þ WP Þ

WP1 ¼ W

WP2 ¼ WP WP3 ¼ W

TP1 ¼ T TP2 ¼ WP TP3 ¼

TðW þ LP Þ LP3

ð5:5:3Þ

346

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

FIGURE 5.5.1 Schematic of various interconnection components: (a) straight segment, (b) bend, (c) step, (d) plug, (e) overﬂow, (f) via, (g) vertical multipath interconnection, and (h) power and ground buses.

FAILURE ANALYSIS OF VLSI INTERCONNECTION COMPONENTS

FIGURE 5.5.1

347

(Continued)

An interconnection line of length L, width W, and thickness T having a length LO suffering from overﬂow (top and end views are shown schematically in Fig. 5.5.1e), is equivalent to two straight segments of lengths LO1 , LO2 , widths WO1 , WO2 , and thicknesses TO1 , TO2 given by the expressions LO1 ¼ L LO LO2 ¼ LO

TO2

TO1 ¼ T WO1 ¼ W pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ WT ¼ 12ðW þ W 2 þ 4WT Þ WO2 ¼ TO2

ð5:5:4Þ

Two straight sections of an interconnection line of total length L, width W, and thickness T joined by a via of height H, width WV , and angle yV , shown in Fig. 5.5.1 f, is equivalent to four straight segments each of width W, lengths LV1 , LV2 , LV3 , and LV4 , and thicknesses TV1 , TV2 , TV3 , and TV4 , respectively, given by the

348

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

expressions yV pTð1 þ cos yV Þ 720 2 T ½1 þ cos yV ðcos yV þ sin yV Þ ¼ 2LV1 þ Tð1 þ cos yV Þ H ¼ T sin yV sin yV

LV1 ¼ TV1 LV2

TV2 ¼ T cos yV LV3 ¼

ð5:5:5Þ

T 2 sin½atanðT=WV Þ

T 2 =ð2 tan yV Þ þ T½WV T=ðtan yV Þ LV3 H ¼ L WV tan yV

TV3 ¼ LV4

TV4 ¼ T A schematic of the side view of a multipath interconnection of length L is shown in Fig. 5.5.1g. It consists of a parallel combination of N paths. Each path is of length L, width W, and thickness T. The paths are connected to each other at the ends by conducting plugs each of length LP . As shown in Fig. 5.5.1h, a power or ground bus serving Ng gates on the IC chip can be modeled as a series combination of N straight segments carrying currents equal to I; 2I; 3I; . . . ; Ng I, where I is the current in each gate. 5.5.2

Calculation of MTF and Lognormal Standard Deviation

For a basic conductor element of length 10 mm, the MTF can be found using the expression [172] MTF ¼ 1523:0

WT I 105

n 11:63 10740:74Ea W 3:07 þ 1:7 exp TK W

ð5:5:6Þ

where I is the interconnection current in milliamperes, n is the current density exponent, Ea is the activation energy of the interconnection material in electronvolts, TK is the temperature in Kelvins, W is the interconnection width in micrometers, and T is the interconnection thickness in micrometers. Then, as a ﬁrst approximation, the MTF of a series combination of N elements ðMTFS Þ can be found using the expression 1 1 1 1 ¼ þ þ þ MTFS MTF1 MTF2 MTFN

ð5:5:7Þ

FAILURE ANALYSIS OF VLSI INTERCONNECTION COMPONENTS

349

whereas that of a parallel combination of N elements ðMTFP Þ can be found using the expression MTFP ¼ MTF1 þ MTF2 þ þ MTFN

ð5:5:8Þ

The lognormal standard deviation s of a basic conductor element of width W (in micrometers) is given by [172]

sðWÞ ¼

2:192 þ 0:787 W 2:625

ð5:5:9Þ

Then, for a straight segment of length L, it can be calculated using the expression sn ¼ sn0:304

ð5:5:10Þ

where n¼

5.5.3

L ðmmÞ 10

ð5:5:11Þ

The Program EMVIC

The program EMVIC is provided in Appendix 5.1 on the accompanying ftp site. EMVIC can be used to determine the MTF and lognormal standard deviation of a straight interconnection segment and the values of MTF for the interconnection bend, interconnection step, interconnection plug, interconnection via, interconnection overﬂow, multipath interconnection, and a power/ground bus. For the userdeﬁned values of the parameters of any component, EMVIC calculates the MTF and s (for straight segment only) for it and displays the results on the screen. The user can choose to write the simulation results on an output ﬁle called EMVIC.OUT. A ﬂow chart of the program EMVIC is shown in Fig. 5.5.2. For a straight segment, the parameters include its length, width, thickness, temperature, current, current density exponent, and material activation energy. In addition to these parameters, the other components are deﬁned as follows: Interconnection bend: bend angle Interconnection step: step height, step angle Interconnection plug: plug length, square plug dimension, plug material activation energy, lower level material activation energy Interconnection via: via height, via width, via angle, lower level material activation energy Interconnection overﬂow: overﬂow length

350

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

FIGURE 5.5.2

Flow chart of program EMVIC.

Multipath interconnection: number of sections, plug lengths, plug material activation energy Power or ground bus: number of gates served by the bus, current in each gate

5.5.4

Simulation Results Using EMVIC

The program EMVIC has been used to study the dependence of MTF on the parameters of each interconnection component. In the following results, the current density exponent is set at 1.0. For a straight interconnection segment, the dependences of MTF and log (s) on the segment width in the range 0.5–5 mm are shown in Fig. 5.5.3 and the dependence of MTF on segment length in the range 10–100 mm is shown in Fig. 5.5.4. The relatively sharp increase in MTF and for widths less than nearly 2 mm is due to

FAILURE ANALYSIS OF VLSI INTERCONNECTION COMPONENTS

351

FIGURE 5.5.3 MTF and log(s) as function of interconnection width for straight interconnection segment.

the so-called bamboo effect. The dependence of the MTF on the interconnection current for a 20-mm-long, 2-mm-wide, 0.5-mm-thick straight segment in the range 2– 20 mA at 100 C is shown in Fig. 5.5.5 and the dependence of the MTF on the temperature of a straight segment in the range 20–200 C is shown in Fig. 5.5.6. For an interconnection step, the dependence of MTF on step angle in the range 90.1–160 is shown in Fig. 5.5.7 and that on the step height in the range 1–10 mm is shown in Fig. 5.5.8. Figure 5.5.7 shows that MTF decreases rapidly as the step angle approaches 90 . This is because of the gradual thinning of the material at the step. For an interconnection plug, the dependence of MTF on the plug length in the range 1–10 mm is shown in Fig. 5.5.9 and that on the dimension of its square side in the range 0.5–2.0 mm is shown in Fig. 5.5.10. The dependence of the MTF on via height for an interconnection via is shown in Fig. 5.5.11, that on via angle is shown in Fig. 5.5.12, and that on via width is shown

FIGURE 5.5.4 segment.

MTF as function of interconnection length for straight interconnection

352

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

FIGURE 5.5.5 segment.

MTF as function of interconnection current for straight interconnection

in Fig. 5.5.13. For an interconnection of length 20 mm, the dependence of the MTF on the length of the section of the interconnection suffering from overﬂow in the range 2–20 mm is shown in Fig. 5.5.14. For a multipath interconnection, the dependence of MTF on the number of paths in the range 1–5 is shown in Fig. 5.5.15. This ﬁgure shows that MTF varies nearly as n2 , where n is the number of sections. This is because the current density in each path is nearly 1=n of that in the single-path interconnection and further because all paths must fail before the interconnection fails completely. For a 1000-mm-long power or ground bus serving 100 identical gates, the dependence of MTF on the current in each gate in the range 0.1–1 mA is shown in Fig. 5.5.16. This ﬁgure shows that increasing the gate currents results in lower values

FIGURE 5.5.6 segment.

MTF as function of interconnection temperature for straight interconnection

FAILURE ANALYSIS OF VLSI INTERCONNECTION COMPONENTS

FIGURE 5.5.7

MTF as function of step angle for interconnection step.

FIGURE 5.5.8

MTF as function of step height for interconnection step.

FIGURE 5.5.9

MTF as function of plug length for interconnection plug.

353

354

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

FIGURE 5.5.10 MTF as function of plug dimension for interconnection plug.

FIGURE 5.5.11 MTF as function of via height for interconnection via.

FIGURE 5.5.12 MTF as function of via angle for interconnection via.

FAILURE ANALYSIS OF VLSI INTERCONNECTION COMPONENTS

355

FIGURE 5.5.13 MTF as function of via width for interconnection via.

FIGURE 5.5.14 MTF as function of overﬂow length for interconnection ﬂow.

FIGURE 5.5.15 MTF as function of number of paths (or sections) for vertical multisection (or multipath) interconnection.

356

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

FIGURE 5.5.16 MTF as function of current in each gate for power or ground bus.

FIGURE 5.5.17 MTF as function of number of gates served for power or ground bus.

of MTF for the bus, as expected. Finally, the dependence of MTF on the number of gates served by the bus is shown in Fig. 5.5.17.

5.6

COMPUTER-AIDED FAILURE ANALYSIS

Rapid developments in VLSI over the last decades have resulted in IC chips consisting of millions of devices and interconnections. In addition, the reductions of device and other dimensions have led to ever-increasing complexity of these chips. With the scaling of the device and interconnection dimensions, several factors need to be considered that have important bearings on the reliability of the chip. These include the small geometry effects in MOSFETs and MESFETs such as hot-carrier effects, dielectric breakdown, electromigration effects in the interconnections, and radiation effects. The reliability performance of a VLSI chip is of major concern to a designer. In the past, because of the lack of CAD tools, VLSI reliability tests were limited to the

COMPUTER-AIDED FAILURE ANALYSIS

357

transistor level. In today’s submicrometer age, it is almost impossible to do without CAD tools for designing the IC chips and for predicting their reliability under various operating conditions. In fact, over the past few years, several CAD tools have emerged which address different aspects of reliability of an IC chip. 5.6.1

RELIANT for Reliability of VLSI Interconnections

RELIANT is a CAD tool developed by researchers at Clemson University [177] for the purpose of predicting the reliability of interconnections because of wearout due to electromigration. It predicts the instantaneous failure rate of the interconnection pattern as a function of time. The algorithm used in RELIANT is based on the principle of fracturing the interconnection pattern into a number of interconnection components, including straight segments, bonding pads, contact windows, vias between two metal layers, and steps resulting from discontinuities in the wafer surface. These components are assumed to be statistically independent, which is valid as long as the time of analysis is much smaller than the median time to failure and when the current density is low enough so that any thermal interactions among the components can be considered negligibly small. This latter requirement is usually satisﬁed if the current density is less than 106 A/cm2. A simpliﬁed ﬂow diagram of RELIANT is shown in Fig. 5.6.1. It shows that RELIANT consists of three main modules, called EXTREM, COMBINE, and

FIGURE 5.6.1

Flow diagram of RELIANT. (From [177]. # 1988 by IEEE.)

358

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

SIRPRICE. The function of EXTREM is to fracture the interconnection patterns contained in a Caltech Intermediate Format (CIF) ﬁle into the various components and to produce the database ﬁle DB1 containing the physical description of each component in terms of its type and physical dimensions. EXTREM also identiﬁes the active devices and produces a SPICE-compatible netlist of the RC equivalent network, including all parasitic interconnection resistances and capacitances of each branch of the interconnection pattern. The function of COMBINE is to read the ﬁle SPC containing the user-deﬁned device models, analysis parameters, and external components such as voltage sources and load resistors and then to add this information to the extracted netlist to produce the ﬁle SPR. The function of SIRPRICE is to read the ﬁle SPR and to call a modiﬁed version of SPICE 2G.6 to perform a transient simulation of the extracted circuit and produce ﬁles containing current-time data jðtÞ for each resistor corresponding to each branch of the interconnection pattern. The cross-sectional area of each component is determined from the physical information contained in the ﬁle DB1 and an effective current density in the component is computed using the expression Jeff

1 ¼ t

Z

tfinal

sinh½jðtÞ dt

ð5:6:1Þ

0

where is a constant [177]. The median time to failure ðt50 Þ is then calculated using the equation t50 ¼

G Ea =ðkTÞ e Jeff

ð5:6:2Þ

where k is Boltzmann’s constant, T is the absolute temperature, Ea is the activation energy, and G depends on the physical dimensions of the component contained in the ﬁle DB1. The standard deviation s of the lognormal failure distribution of each component is also calculated from the physical information in the ﬁle DB1. The instantaneous failure rate of the interconnection pattern is then calculated using a suitable failure distribution such as the most commonly and experimentally tested lognormal distribution. SIRPRICE produces several data ﬁles called DAT, LIS, DB2, and DTR containing the failure rates for each component and the entire circuit, the reliability data, and other data used for interfacing to other program modules.

5.6.2

SPIDER for Checking Current Density and Voltage Drops in Interconnection Metallizations

As is well known, high current densities in the interconnection metallizations lead to electromigration of metal atoms and voltage drop and should be properly accounted for in order to avoid any serious reliability problems. SPIDER is a CAD tool developed

COMPUTER-AIDED FAILURE ANALYSIS

FIGURE 5.6.2

359

Flow diagram of SPIDER. (From [178]. # 1986 by IEEE.)

by researchers at Texas Instruments [178] for the purpose of checking current density and voltage drop in VLSI interconnections. In fact, it is a system of programs employing a simpliﬁed hierarchieal approach developed to aid VLSI designers to ensure adequate current-carrying capacity in the metallization patterns on an IC chip. SPIDER includes both the detection and correction algorithms for current density and voltage drop and can be used in the initial design phase as well as for layout veriﬁcation. SPIDER uses a hierarchal approach and can be used at any level of circuit design. The lowest level subcircuits can be analyzed for the current waveforms using SPICE, which can then be used for the design and analysis at the next higher circuit level. An abbreviated form of the ﬂow diagram of SPIDER is shown in Fig. 5.6.2. The various steps can be summarized as follows: 1. The various metallization patterns, which could be power supply lines, ground lines, clock lines, or other signal lines, are represented in terms of equivalent resistive and capacitive elements which are determined by using a parasitic element extraction program. This results in an RC network suitable for analysis by SPICE. The designer also identiﬁes the nodes at which the current enters or leaves the conductor. 2. Transient current waveforms at each identiﬁed node are determined by the designer by analysis of the individual subcircuit.

360

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

3. SPICE is used to determine the current waveform ﬂowing through each resistance. 4. The continuous DC densities equivalent to the current waveforms of step 3 are calculated using the procedure derived by McPherson and Ghate [179]. These current densities are then compared with the desired values speciﬁed by the designer. If, in a given region, the calculated current density exceeds the speciﬁed value, then the width of the metallization is increased; if it is below the speciﬁed value, no change in the width is made. 5. Steps 3 and 4 are then repeated for the revised values of the widths and the process is carried out until the ﬁnal set of line widths are found.

EXERCISES E5.1 According to Eq. (5.3.16), the local power dissipation from the interconnection line is given by rrðJp Þ2 ¼

Km 2

½TðkÞ Tðk lÞ þ

ðD50 Þ Km þ ½TðkÞ Tðk þ lÞ ðD50 Þ2

K0 ½TðkÞ Ta d0 dm

This equation does not account for the details of heat transfer from the substrate to the ambient environment. Comment on the signiﬁcance of this missing factor and modify the equation to include this process. E5.2 Equation (5.3.16) is time independent. This is valid as long as the pulse repetition rate is of the order of megahertz because the thermal time constant for a typical metal line–dielectric layer combination is usually 1 ms or more. Modify the equation so that it is also valid for lower pulse repetition rates. E5.3 By considering the effects of the average ﬂux density on the grain boundary migration in an interconnection bend of angle yB , show that the additional area (shown shaded in Fig. 5.5.1b) is equivalent to a straight segment of length LB and width WB given by the expressions pWj180 yB j LB ¼ 360

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ W 2 ð1 þ tanðyB =2ÞÞ WB ¼ W þ LB

E5.4 Show that an interconnection line of length L, width W, and thickness T having a single step of height H and angle ys , shown in Fig. 5.5.1c, is equivalent to three straight segments each of width W, lengths LS1 , LS2 , and LS3 , and thicknesses

EXERCISES

361

TS1 , TS2 , and TS3 , respectively, given by the expressions LS1 ¼ L þ

H tan yS

TS1 ¼ T

H sin yS pTð180 yS Þð1 cos yS Þ ¼ 720

LS2 ¼ T cos yS þ

TS2 ¼ T cos yS

LS3

TS3 ¼

T 2 ð1 þ cos yS ðcos yS sin yS ÞÞ 2LS3 þ Tð1 cos yS Þ

E5.5 Show that the two straight sections of an interconnection line of total length L, width W, and thickness T joined by a single plug of length H and square dimension WP , shown in Fig. 5.5.1d, is equivalent to three straight segments of lengths LP1 , LP2 , and LP3 , widths WP1 , WP2 , and WP3 , and thicknesses TP1 , TP2 and TP3 respectively, given by the expressions LP1 ¼ L WP

WP1 ¼ W

TP1 ¼ T

LP2 ¼ H

WP2 ¼ WP

LP3 ¼ 18pðT þ WP Þ

WP3 ¼ W

TP2 ¼ WP TðW þ LP Þ TP3 ¼ LP3

E5.6 Show that an interconnection line of length L, width W, and thickness T having a length LO suffering from overﬂow (top and end views are shown schematically in Fig. 5.5.1e) is equivalent to two straight segments of lengths LO1 and LO2 , widths WO1 and WO2 , and thicknesses TO1 , TO2 given by the expressions LO1 ¼ L LO LO2 ¼ LO

TO1 ¼ T TO2

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ¼ 12ðW þ W 2 þ 4WT Þ

WO1 ¼ W WT WO2 ¼ TO2

E5.7 Show that the two straight sections of an interconnection line of total length L, width W, and thickness T joined by a via of height H, width WV , and angle yV , shown in Fig. 5.5.1f, are equivalent to four straight segments each of width W, lengths LV1 , LV2 , LV3 , and LV4 , and thicknesses TV1 , TV2 , TV3 , and TV4 respectively, given by yV pTð1 þ cos yV Þ 720 H ¼ T sin yV sin yV T ¼ 2 sin½actanðT=WV Þ H ¼ L WV tan yV

T 2 ½1 þ cos yV ðcos yV þ sin yV Þ 2LV1 þ Tð1 þ cos yV Þ

LV1 ¼

TV1 ¼

LV2

TV2 ¼ T cos yV

LV3 LV4

TV3 ¼

T 2 =ð2 tan yV Þ þ T½WV T=ðtan yV Þ LV3

TV4 ¼ T

362

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

E5.8 The simulation results using EMVIC presented in Section 5.5.4 are based on the approximate equations (5.5.8) and (5.5.9). More accurate results can be obtained by using the probability-of-failure equations (5.2.6)–(5.2.8). Determine the MTF by ﬁrst plotting the probability of failure as a function of time for each interconnection component described in Section 5.5.

REFERENCES 1. N. V. Doan and G. Boebec, ‘‘Migration Sous L’effect Dun’ Champ Electrique de Ag110 et de Sb124 Dans l’Argent,’’ J. Phys. Chem. Solids, vol. 31, pp. 475–484, 1970. 2. D. F. Kalinovich, I. I. Kovenskii, M. O. Smolin, and V. M. Statsenko, ‘‘Electrotransport of Molybdenum in Ni-18 at % Mo Alloy,’’ Fiz Tverd. Tela (USSR), vol. 12, pp. 3042– 3044, 1970. 3. J. C. Peacock and A. D. Wilson, ‘‘Electrotransport of Tungsten and Life of a Filament,’’ J. Appl. Phys., vol. 39, pp. 6037–6041, 1968. 4. D. L. Kennedy, ‘‘Electrotransport in Thin Indium Films,’’ J. Appl. Phys., pp. 6102–6104, 1968. 5. R. M. Valleta and H. S. Lehman, ‘‘Al-Cu for Semiconductor Metallurgy,’’ Extended Abstracts, The Electrochemical Society Meeting, Atlantic City, NJ, Oct. 1970, p. 474. 6. L. Berenbaum and R. Rosenberg, ‘‘Electromigration Damage in Al-Cu Thin Films,’’ IRPS, 1971. 7. E. Nagapawa and H. Okabayaski, ‘‘Electromigration of Sputtered Al-Si Alloy Films,’’ IRPS, pp. 64–70, 1979. 8. T. Mori, M. Meshii, and J. W. Kaufman, ‘‘Quenching Rate and Quenched-in Lattice in Gold,’’ J. Appl. Phys., vol. 33, pp. 2776–2780, 1962. 9. D. O. Boyle, ‘‘Observations on Electromigration and the Sovet Effect in Tungsten,’’ J. Appl. Phys., vol. 36, pp. 2849–2853, 1965. 10. L. Berenbaum and B. Patnaik, ‘‘Study of Failure Mechanisms in Al-Cu Films by High Voltage Microscopy,’’ Appl. Phys. Lett., vol. 18, pp. 284–286, 1971. 11. P. B. Ghate, ‘‘Some Observations on the Electromigration in Aluminium Films,’’ Appl. Phys. Lett., vol. 11, pp. 14–16, 1967. 12. I. A. Blech, ‘‘Electromigration in Thin Aluminium Films on Titanium Nitride,’’ J. Appl. Phys., vol. 47, pp. 1203–1208, Apr. 1976. 13. J. K. Howard and R. F. Ross, ‘‘Electromigration Effects in Aluminium on Silicon Substrates,’’ Appl. Phys. Lett., vol. 11, pp. 85–87, 1967. 14. R. C. Pitelli, ‘‘Electromigration of TiPdAu Conductors,’’ IRPS, pp. 171–174, 1972. 15. A. Ladding, ‘‘Current-Induced Motion of Lattice Defects in Indium Metal,’’ J. Phys. Chem. Solids, vol. 26, pp. 143–151, 1965. 16. P. S. Ho and H. B. Huntington, ‘‘Electromigration and Void Observation in Silver,’’ J. Phys. Chem. Solids, vol. 27, pp. 1319–1329, 1966. 17. P. S. Ho, ‘‘Electromigration and Soret Effect in Cobalt,’’ J. Phys. Chem. Solids, vol. 27, pp. 1331–1338, 1966.

REFERENCES

363

18. J. F. D’Amico and H. B. Huntington, Electromigration and Thermomigration in GammaUranium, Report, Rensselaer Polytechnic Institute, Department of Physics, Troy, NY, pp. 1044–1048. 19. R. V. Penny, ‘‘Current-Induced Mass Transport in Aluminium,’’ J. Phys. Chem. Solids, vol. 25, pp. 335–345, 1964. 20. A. R. Grone, ‘‘Current-Induced Marker Motion in Copper,’’ J. Phys. Chem. Solids, vol. 20, pp. 88–98, 1961. 21. H. B. Huntington and A. R. Grone, ‘‘Current-Induced Marker Motion in Gold Wires,’’ J. Phys. Chem. Solids, vol. 20, pp. 76–87, 1961. 22. J. R. Black, ‘‘Aluminium Conductor Failure by Mass Transport,’’ Proc. 3rd Int. Congression on Microelectronics, Munich, Germany, pp. 141–162, Nov. 1968. 23. G. M. Newmann, ‘‘On Thermotransport in Tungsten,’’ Z. Naturforsch A., vol. 22, pp. 393–395, 1967. 24. D. Campbell and H. Huntington, ‘‘Thermomigration and Electromigration in Zirconium,’’ Phys. Rev., vol. 179, pp. 601–612, 1969. 25. D. Campbell and H. Huntington, ‘‘Electron Transfer of Silver and Copper Between Crystallites,’’ Phys. Metals Metallogr. (USSR), vol. 16, no. 4, 1964. 26. H. Dubler and H. Wever, ‘‘Thermo- and Electrotransport in b-Titan and b-Zirkonium,’’ Phys. Status Solidi, vol. 25, pp. 109–118, 1968. 27. S. C. Ho, T. Hehenkamp, and H. B. Huntington, ‘‘Thermal Diffusion in Platinum,’’ J. Phys. Chem. Solids, vol. 26, pp. 251–258, 1965. 28. T. Thernquist and A. Lodding, ‘‘Electro- and Thermotransport in Lithium,’’ Proc. Int. Conf. Vacancies and Interstitials in Metals, Kernsfor Schungsanlage Julich, pp. 55–68, Sept. 1968. 29. T. Hehenkamp, ‘‘Diffusion und Elektrotransport von Kohlenstoff in Kobalt,’’ Acta Met., vol. 14, pp. 887–893, 1966. 30. H. Hering and H. Wever, ‘‘Electro- and Thermotransport in Nickel,’’ J. Phys. Chem., vol. 1, pp. 310–325, 1967. 31. G. M. Newmann and W. Hirschwald, ‘‘Electrotransport in Tungsten,’’ Z. Naturforsch A., vol. 22, pp. 388–392, 1967. 32. H. J. Stepper and H. Wever, ‘‘Electrodiffusion in Dilute Copper Alloys,’’ J. Phys. Chem. Solids, vol. 28, pp. 1103–1108, 1967. 33. I. A. Blech and E. S. Meieran, ‘‘Direct Transmission Electron Microscope Observations of Electrotransport in Aluminium Films,’’ Appl. Phys. Lett., vol. 11, pp. 263–266, 1967. 34. K. R. Kodbell and S. R. Shatynski, ‘‘Electromigration in Sputtered Al-Cu Thin Films,’’ Thin Solid Films, vol. 116, pp. 95–102, 1984. 35. M. J. Attardo and R. Rosenberg, ‘‘Electromigration Damage in Aluminium Film Conductors,’’ J. Appl. Phys., vol. 41, pp. 2381–2386, 1970. 36. F. d’Heurle and I. Ames, ‘‘Electromigration in Single Crystal Aluminium Films,’’ Appl. Phys. Lett., vol. 16, pp. 80–81, 1970. 37. T. E. Hartman and J. C. Blair, ‘‘Electromigration in Thin Gold Films,’’ IEEE Trans. Electron Devices, vol. ED-16, no. 4, pp. 407–410, 1969. 38. P. B. Ghate, ‘‘Electromigration Testing of Al-Alloy Films,’’ IRPS, pp. 243–251, 1981.

364

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

39. S. S. Iyer and C. Ting, ‘‘Electromigration Lifetime Studies of Submicrometer Linewidth Al-Cu Conductors,’’ IEEE Trans. Electron Devices, vol. ED-31, no. 10, pp. 1468–1471, Oct. 1984. 40. J. Chern, W. G. Oldham, and N. Cheung, ‘‘Contact Electromigration Induced Leakage Failure in Aluminium-Silicon to Silicon Contacts,’’ IEEE Trans. Electron Devices, vol. ED-32, no. 4, pp. 1341–1346, July 1985. 41. J. Chern, W. G. Oldham, and N. Cheung, ‘‘Electromigration in Al-Si Contacts—Induced Open-Circuit Failure,’’ IEEE Trans. Electron Devices, vol. ED-31, no. 9, pp. 1256–1261, Sept. 1986. 42. S. D. Steenwyk and E. F. Kankowski, ‘‘Electromigration in Aluminium to Tantalum Silicide Contacts,’’ IRPS, pp. 30–37, 1986. 43. G. D. Giacomo, ‘‘Electromigration Depletion in Pb-Sn Films,’’ IRPS, pp. 72–76, 1979. 44. S. S. Iyer and C. Ting, ‘‘Electromigration Study on the Al-Cu/Ti/Al-Cu Systems,’’ IRPS, pp. 273–274, 1981. 45. E. Levine and J. Kitchen, ‘‘Electromigration-Induced Damage and Structural Change in Cr-Al/Cu and Al/Cu Interconnection Lines,’’ IRPS, pp. 242–248, 1984. 46. W. Hasse, J. Schulte, and J. Grawl, ‘‘Electromigration of Silicon and Phosphorous in Tantalum Polycide Interconnections,’’ IEEE Trans. Electron Devices, vol. ED-34, no. 3, pp. 659–663, 1987. 47. D. K. Sadana, J. M. Towner, M. H. Norcott, and R. C. Ellwanger, ‘‘Some TEM Observations on Electromigrated Al and Al-Alloy Interconnects,’’ IRPS, pp. 38–43, 1986. 48. B. Grabe and H. U. Screiber, ‘‘Lifetime and Drift Velocity Analysis for Electromigration in Sputtered Al Films, Multilayers and Alloys,’’ Solid State Electron., vol. 26, pp. 1023– 1032, 1983. 49. J. P. Tardy and K. N. Tu, ‘‘Interdiffusion and Marker Analysis for Electromigration in Aluminium Titanium Thin Film Bilayers,’’ paper presented at the Electronic Materials Conference, June 1984, p. 12. 50. C. F. Dunn, F. R. Brotzen, and J. W. McPherson, ‘‘Electromigration and Microstructural Properties of Al-Si/Ti/Al-Si VLSI Metallization,’’ J. Electron. Mat., vol. 15, no. 8, pp. 273–277, Sept. 1986. 51. K. A. Danso and T. Tullos, ‘‘Thin Film Metallization Studies and Device Lifetime Prediction Using Al-Si, Al-Cu-Si Conductor Test Bars,’’ Microelectron. Reliabil., vol. 21, pp. 513–527, 1981. 52. I. A. Blech and E. Kinsborn, ‘‘Electromigration in Thin Gold Films on Molybdenum Surfaces,’’ Thin Solid Films, vol. 55, pp. 113–123, 1978. 53. P. B. Ghate and J. C. Blair, ‘‘Electromigration Testing of TiW/Al and TiW/ Al-Cu Film Conductors,’’ Thin Solid Films, vol. 25, pp. 327–334, 1971. 54. J. C. Blair, P. B. Ghate, and C. T. Haywood, ‘‘Electromigration-Induced Failure in Aluminium Film Conductors,’’ Appl. Phys. Lett., vol. 17, pp. 281–283, 1970. 55. S. Vaidya and A. K. Sinha, ‘‘Electromigration-Induced Leakage at Shallow Junction Contacts Metallized with Aluminium/Polysilicon,’’ IRPS, pp. 50–54, 1982. 56. S. Vaidya, A. K. Sinha, and J. M. Andrews, ‘‘Contact-Electromigration-Induced Failure Shallow Junction Leakage with Al/Poly Si Metallization,’’ J. Electrochem. Soc., vol. 132, no. 2, pp. 496–501, Feb. 1983.

REFERENCES

365

57. G. S. Prokop and R. R. Joseph, ‘‘Electromigration Failure at Aluminium-Silicon Contacts,’’ J. Appl. Phys., vol. 43, no. 6, pp. 2595–2602, 1972. 58. I. A. Blech and H. Sello, ‘‘The Failure of Thin Aluminium Current-Carrying Strips on Oxidized Silicon,’’ Phys. Failure Electron., vol. 5, pp. 496–505, June 1967. 59. J. Howard and R. F. Ross, ‘‘Electromigration Effects in Aluminium on Silicon Substrates,’’ Appl. Phys. Lett., vol. 11, no. 3, pp. 85–87, Aug. 1967. 60. G. J. VanGurp, ‘‘Electromigration in Aluminium Films Containing Si,’’ Appl. Phys. Lett., vol. 19, pp. 476–479, 1971. 61. A. J. Learn, ‘‘Electromigration Effects in Aluminium Alloy Metallization,’’ J. Electron. Materials, vol. 3, no. 2, pp. 531–552, 1974. 62. S. Vaidya, D. B. Fraser, and W. S. Lindenberger, ‘‘Electromigration in Fine-Line Sputtered Gun Al,’’ J. Appl. Phys., vol. 51, pp. 4475–4482, 1980. 63. J. R. Black, ‘‘Electromigration of Al-Si Alloy Films,’’ IRPS, pp. 233–240, 1978. 64. J. R. Lloyd, M. J. Sullivan, G. S. Hopper, J. T. Cofﬁn, E. T. Severn, and J. L. Jozwiak, ‘‘Electromigration Failure in Thin Film Silicides and Polysilicon/Silicide (Polycide),’’ IRPS, pp. 198–202, 1983. 65. P. S. Ho, ‘‘Basic Problems for Electromigration in VLSI Applications,’’ IRPS, pp. 288– 290, 1982. 66. P. S. Ho, F. M. d’Heurle, and A. Gangulee, in Electro- and Thermotransport in Metals and Alloys, R. E. Hummel and H. B. Huntington, Eds., New York: AIME, 1977, pp. 108– 159. 67. P. S. Ho, ‘‘Motion of Inclusion Induced by a Direct Current and a Temperature Gradient,’’ J. Appl. Phys., vol. 41, pp. 64–68, 1970. 68. J. R. Lloyd, P. M. Smith, and G. S. Prokop, ‘‘The Role of Metal and Passivation Defects in Electromigration-Induced Damage in Thin Film Conductors,’’ Thin Solid Films, vol. 93, pp. 385–396, 1982. 69. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, ‘‘Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions,’’ IEEE J. Solid State Circuits, vol. SC-9, p. 256, 1974. 70. D. D. Tang and P. M. Solomon, ‘‘Bipolar Transistor Design for Optimized Power-Delay Logic Circuits,’’ IEEE J. Solid State Circuits, vol. SC-14, pp. 679–684, 1979. 71. J. R. Lloyd, ‘‘Electromigration-Induced Extrusions in Multi-Level Technologies,’’ IRPS, pp. 208–209, 1983. 72. J. Verhoenen, ‘‘Electrotransport in Metals,’’ Metallurg. Rev., vol. 8, pp. 311–368, 1963. 73. J. R. Black, ‘‘Metallization Failures in Integrated Circuits,’’ RADC Tech. Rept. TR-68243, Oct. 1968. 74. K. E. Schwartz, Electrolytische Wonderung in Flussizen und Festern Metallen, Leipzig, 1940. 75. J. Verhoeven, ‘‘Electrotransport as a Means of Purifying Metals,’’ J. Metals, vol. 18, pp. 26–31, 1966. 76. H. B. Huntington and S. C. Ho, ‘‘Electromigration in Metals,’’ J. Phys. Soc. Japan, vol. 18, Suppl. II, pp. 202–208, 1963. 77. C. Bosvieux and J. Friedel, ‘‘Sur l’electrolyte Des Alliages Metallignes,’’ J. Phys. Chem. Solids, vol. 23, pp. 123–136, 1962. 78. S. M. Klostman, A. N. Timoferv, and I. S. Trakhtenberg, ‘‘On the Mechanism of Lattice Electromigration in Metals,’’ Phys. Status Solidi, vol. 18, pp. 847–852, 1966.

366

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

79. F. M. D’Heurle, ‘‘Electromigration and Failure in Electronics, An Introduction,’’ Proc. IEEE, vol. 59, no. 10, pp. 1409–1418, 1971. 80. N. V. Doan, ‘‘Effect de Valence en Electromigration Dans L’argent,’’ J. Phys. Chem. Solids, vol. 31, pp. 2079–2085, 1970. 81. D. Chhabra, N. Ainslie, and D. Jepsen, ‘‘Theory of Failure in Thin Film Conductors,’’ paper presented at the Electrochemical Society Meeting, Dallas, TX, May 1967. 82. W. Mutter, ‘‘Electromigration in Metal Film Conductors,’’ Abstracts, Electrochemical Society Spring Meeting, Dallas, TX, May 1967, pp. 96–98. 83. J. R. Black, ‘‘Electromigration—A Brief Survey and Some Recent Results,’’ IEEE Trans. Elec. Dev., vol. ED-16, pp. 338–347, Apr. 1967. 84. J. R. Devaney, ‘‘Investigated of Current-Induced Mass Transport in Thin Metal Conducting Stripes,’’ in Proceedings of the Third Scanning Electron Microscope Symposium, O. Johaii, Ed., Chicago, Apr. 1970, pp. 417–424. 85. D. S. Chhabra and N. G. Ainslie, ‘‘Open Circuit Failures in Thin Film Conductors,’’ Tech. Report 22.419, IBM Components Div., E. Fishkill Facility, New York, July 1967. 86. F. M. d’Heurle and R. Rosenberg, ‘‘Electromigration in Thin Films,’’ in Physics of Thin Films, Vol. 7, Haas, Francombe, and Hoffman, Eds., New York: Academic, 1972. 87. F. M. d’Heurle and P. S. Ho, ‘‘Electromigration in Thin Films,’’ in Thin Films Interdiffusion and Reactions, Poate, Tu, and Mayer, Eds., New York: Wiley, 1978, pp. 243–304. 88. R. A. Sigsbee, ‘‘Failure Model for Electromigration,’’ IRPS, pp. 301–305, 1973. 89. R. A. Sigsbee, ‘‘Electromigration and Metallization Lifetime,’’ J. Appl. Phys., vol. 44, pp. 2533–2540, 1973. 90. J. D. Venables and R. G. Lye, ‘‘A Statistical Model for Electromigration Induced Failure in Thin Film Conductors,’’ IRPS, pp. 159–164, 1972. 91. K. Nikawa, ‘‘More Carlo Calculations Based on the Generalized Electromigration Failure Model,’’ IRPS, pp. 175–181, 1981. 92. P. B. Ghate, ‘‘Electromigration-Induced Failures in VLSI Interconnects,’’ IRPS, pp. 292–299, 1982. 93. J. M. Schoen, ‘‘Monte Carlo Calculations of Structure-Induced Electromigration Failure,’’ J. Appl. Phys., vol. 51, pp. 513–517, 1980. 94. J. R. Black, ‘‘Physics of Electromigration,’’ IRPS, pp. 142–145, 1972. 95. C. B. Oliver and D. E. Bowers, ‘‘Theory of the Failure of Semiconductor Contacts by Electromigration,’’ IRPS, pp. 116–120, 1970. 96. R. W. Thomas and D. W. Calabrese, ‘‘Phenomonological Observations on Electromigration,’’ IRPS, pp. 1–4, 1983. 97. S. Luby, ‘‘Electromigration Defect Formation in Thin Films,’’ Thin Solid Films, vol. 116, p. 97, 1984. 98. P. B. Ghate, ‘‘Failure Mechanism Studies in Multilevel Metallization Systems,’’ Final Tech. Report RADC TR-71-186, Rome Air Development Center, Air Force System Command, Grifﬁss Air Force Base, New York, Sept. 1971. 99. H. B. Huntington, ‘‘Electromigration in Metals,’’ in Diffusion in Solids—Recent Developments, A. S. Norwick and J. J. Burton, Eds., New York: Academic, 1975, p. 303. 100. E. J. Goldberg and T. W. Adolphson, ‘‘A Failure Mechanism of Semiconductor Devices and Its Analyses,’’ IRPS, pp. 144–147, 1967.

REFERENCES

367

101. S. K. Ghandi, VLSI Fabrication Principles. New York: Wiley Interscience, 1982. 102. P. P. Metchant, ‘‘Electromigration: An Overview,’’ Hewlett-Packard J., p. 28, Aug. 1982. 103. V. B. Fiks, ‘‘On the Mechanism of the Mobility of Ions in Metals,’’ Solid State Phys. (USSR), vol. 1, no. 2959, pp. 14–27, 1959. 104. P. G. Shewmon, Diffusion in Solids. New York: McGraw-Hill, 1963. 105. Y. Adda and J. Phillibert, La Diffusion dans les Solides. Paris: Presses Universitaites de France, 1966. 106. S. C. Ho and H. B. Huntington, ‘‘Electromigration and Void Observation in Silver,’’ J. Phys. Chem. Solids, vol. 27, pp. 1319–1329, 1966. 107. R. R. Patil and H. B. Huntington, ‘‘Electromigration and Associated Void Formation in Silver,’’ J. Phys. Chem. Solids, vol. 31, pp. 463–474, 1970. 108. R. W. Berry, G. M. Bonton, W. C. Ellis, and D. E. Engling, ‘‘Growth of Whisker Crystals and Related Morphologies by Electrotransport,’’ Appl. Phys. Lett., vol. 9, pp. 263–265, 1966. 109. R. Vanselow, R. Masters, and R. Welnes, ‘‘Crystal Forms of Hillocks and Voids Formed by Electromigration on Ultrapure Gold and Silver Wires,’’ Appl. Phys., vol. 12, pp. 341– 345, 1975. 110. B. Selikson, ‘‘Void Formation Failure Mechanisms in Integrated Circuits,’’ Proc. IEEE, vol. 57, no. 9, pp. 1594–1598, 1969. 111. I. A. Blech and C. Herring, ‘‘Stress Generation by Electromigration,’’ Appl. Phys. Lett., vol. 29, no. 3, pp. 131–133, 1976. 112. I. A. Blech and K. L. Tai, ‘‘Measurement of Stress Gradients Generated by Electromigration,’’ Appl. Phys. Lett., vol. 30, no. 8, pp. 387–389, 1977. 113. J. Partridge and G. Littleﬁeld, ‘‘Aluminium Electromigration Parameters,’’ IRPS, pp. 119–125, 1985. 114. M. J. Attardo, IBM, private communication. 115. G. E. Gimpelson, ‘‘An Elementary Relationship between the Electromigration MeanTime to Failure and the Migration Velocity,’’ VLSI Multilevel Interconnection Conf., 1984, pp. 84–89. 116. R. G. Shepheard and R. P. Sopher, ‘‘Effects of Current Density and Temperature on Lifetime of Aluminium Thin Film Conductors,’’ Abstracts, Electrochemical Society Spring Meeting, Dallas, TX, May 1967. 117. H. C. Schafft, ‘‘Thermal Analysis of Electromigration and the Current Density Dependence,’’ IRPS, pp. 93–99, 1985. 118. H. A. Schafft, ‘‘Thermal Analysis of Electromigration Test Structures,’’ IEEE Trans. Electron Devices, vol. ED-34, no. 3, pp. 664–672, Mar. 1987. 119. A. D. LeClaire, ‘‘Some Predicted Effects of Temperature Gradients on Diffusion in Crystals,’’ Phys. Rev., vol. 93, p. 344, 1954. 120. H. B. Huntington, ‘‘Driving Forces for Thermal Mass Transport,’’ J. Phys. Chem. Solids, vol. 29, pp. 1641–1651, 1968. 121. R. A. Oriani, ‘‘Thermomigration in Solid Metals,’’ J. Phys. Chem. Solids, vol. 30, pp. 339–351, 1969. 122. G. M. Newmann, ‘‘On Thermotransport in Tungsten,’’ Z. Naturforsch A., vol. 22, pp. 393–395, 1967. 123. S. C. Ho, T. Hehenkamp, and H. B. Huntington, ‘‘Thermal Diffusion in Platinum,’’ J. Phys. Chem. Solids, vol. 26, pp. 251–258, 1965.

368

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

124. J. M. Towner, ‘‘Electromigration-Induced Short-Circuit Failure,’’ IRPS, pp. 81–86, 1985. 125. B. Agrawala, M. Attardo, and A. P. Indraham, ‘‘The Dependence of ElectromigrationInduced Failure Time on the Length and Width of Thin Film Conductors,’’ J. Appl. Phys., vol. 41, pp. 3954–3960, 1970. 126. E. Kinsborn, ‘‘A Model for the Width Dependence of Electromigration Lifetimes in Aluminium Thin Film Stripes,’’ Appl. Phys. Lett., vol. 36, pp. 968–970, 1980. 127. S. Vaidya, T. T. Sheng, and A. K. Sinha, ‘‘Linewidth Dependence of Electromigration in Evaporated Al -.5% Cu,’’ Appl. Phys. Lett., vol. 36, pp. 464–466, 1980. 128. J. Arzigian, ‘‘Aluminium Electromigration Lifetime Variations with Linewidth: The Effects of Changing Stress Conditions,’’ IRPS, pp. 32–34, 1983. 129. G. A. Scogan, B. N. Agrawala, P. P. Peressini, and A. Brouillard, ‘‘Width Dependence of Electromigration Life in Al-Cu, Al-Cu-Si, and Ag Conductors,’’ IRPS, pp. 151–155, 1975. 130. M. Saito and S. Mirota, ‘‘Investigation of Grain Boundary and Lifetime in Aluminium Interconnections,’’ Elec. Comm. Lab. Tech. J., vol. 22, pp. 1375–1398, 1973. 131. D. Turnball and R. Z. Hoffman, ‘‘The Effect of Relative Crystal and Boundary Orientation on Grain Boundary Diffusion Rates,’’ Acta Metallurg., vol. 2, pp. 419–426, 1954. 132. N. G. Einspruch and G. B. Larrabee, Eds., VLSI Electronics, Microstructure Science, Vol. 6, New York: Academic, 1983. 133. R. Rosenbert and L. Berenbaum, ‘‘Atomic Transport in Solids and Liquids,’’ Proc. Europhysics Conference, Marstrand Sweden, Ladding and Lagerwall, Eds., Tubingen, Valag der Zeitschrift fur Naturformschung, 1971, p. 113. 134. J. K. Howard and R. F. Ross, ‘‘The Effect of Preferred Orientation on the Rate of Electromigration and Its Implication to the Cracked-Stripe Failure Mode,’’ IBM Tech Rep. 22.601, Mar. 1968. 135. M. J. Attardo, R. Rutledge, and R. C. Jack, ‘‘Statistical Metallurgical Model for Electromigration Failure in Aluminium Thin-Film Conductors,’’ J. Appl. Phys., vol. 42, no. 11, pp. 4343–4349, 1971. 136. E. Kinsborn, C. M. Melliar Smith, and A. T. English, ‘‘Failure of Small Thin-Film Conductors Due to High Current-Density Pulses,’’ IEEE Trans. Electron Devices, vol. ED-26, no. 1, pp. 22–26, 1979. 137. R. J. Miller, ‘‘Electromigration Failure Under Pulsed-Current Conditions,’’ IRPS, vol. 16, pp. 241–247, 1978. 138. J. R. Davis, ‘‘Electromigration in Aluminium Thin Films Under Pulse-Current Conditions,’’ Proc. IEE, pp. 1209–1212, 1976 139. A. T. English, K. L. Tai, and P. A. Turner, ‘‘Electromigration in Conductor Stripes Under Pulsed DC Powering,’’ Appl. Phys. Lett., vol. 21, pp. 397–398, Oct. 1982. 140. J. Towner and E. Van de Ven, ‘‘Aluminium Electromigration Under Pulsed DC Conditions,’’ IRPS, pp. 36–39, 1983. 141. A. T. English and E. Kinsbron, ‘‘Electromigration Transport Mobility Associated with Pulsed Direct Current in Fine-Grained Al-0.5% Cu Thin Films,’’ J. Appl. Phys., vol. 54, no. 1, pp. 275–280, 1983. 142. J. M. Schoen, ‘‘A Model of Electromigration Failure Under Pulsed Condition,’’ J. Appl. Phys., vol. 51, no. 1, pp. 508–512, Jan. 1980.

REFERENCES

369

143. K. P. Rodbell and R. Shatynski, ‘‘A New Method for Detecting Electromigration Failure in VLSI Metallization,’’ IEEE Trans. Electron Devices, vol. ED-31, no. 2, pp. 232–233, 1984. 144. T. A. Burkett and R. L. Miller, ‘‘Electromigration Evaluation—MTF Modeling and Accelerated Testing,’’ IRPS, pp. 264–272, 1984. 145. R. Rosenberg and L. Berenbaum, ‘‘Resistance Monitoring and Effects of Nonadhesion During Electromigration in Aluminium Films,’’ Appl. Phys. Lett., vol. 12, no. 5, pp. 201– 204, 1968. 146. R. E. Hummel, R. T. Deltoff, and H. J. Geier, ‘‘Activation Energy for Electrotransport in Thin Aluminium Film by Resistance Measurements,’’ J. Phys. Chem. Solids, vol. 37, pp. 73–80, 1976. 147. Y. Z. Lu and Y. C. Cheng, ‘‘Measurement Techniques of Electromigration,’’ Microelec. Reliabil., vol. 23, no. 6, pp. 1103–1108, 1983. 148. R. W. Pasco and J. A. Schwartz, ‘‘Temperature-Ramp Resistance Analysis to Characterize Electromigration,’’ Solid State Electron., vol. 26, no. 5, pp. 445–452, 1983. 149. P. M. Austin and A. F. Mayadas, ‘‘Correlation between Resistance Ratios and Electromigration Failure in Thin Films,’’ J. Vac. Sci. Technol., submitted for publication. 150. D. J. LaCombe and E. Parks, ‘‘A Study of Resistance During Electromigration,’’ IRPS, pp. 74–80, 1985. 151. T. M. Chen, T. P. Djen, and R. D. Moore, ‘‘Electromigration and 1/f Noise of Aluminium Thin Films,’’ IRPS, pp. 87–92, 1985. 152. H. Kroemer, Technical Memorandum no. 275, Fairchild Semiconductor, Nov. 1966. 153. I. A. Blech and E. S. Meiein, ‘‘Electromigration in Integrated Circuits,’’ IRPS, pp. 243– 247, 1970. 154. S. M. Spitzer and S. Shwartz, ‘‘The Effects of Dielectric Overcoating on ELectromigration,’’ IEEE Trans. Electron Devices, vol. ED-16, no. 4, pp. 348–350, 1969. 155. D. Whitcomb, ‘‘Advanced Technology of Interconnections in Micro-electronics,’’ Report prepared by Motorola Inc. for NASA/ERC under contract NAS-132, Jan. 1968. 156. G. Schnable, Philco-Ford Corp., Blue Bell, PA, private communication, Mar. 1968. 157. K. G. Kemp and K. F. Poole, ‘‘A Study of Electromigration in Double Level Metal Systems Using Oxide and Polymer Dielectrics,’’ IRPS, pp. 54–57, 1987. 158. T. Wada, H. Higuchi, and T. Ajiki, ‘‘New Phenomena of Electromigration in Double-Layer Metallization,’’ IRPS, pp. 203–207, 1983. 159. H. A. Schafft, C. P. Youngkins, T. C. Grant, C. Y. Kao, and A. N. Saxena, ‘‘Effect of Passivation and Passivation Defects on Electromigration Failure in Aluminium Metallization,’’ IRPS, pp. 250–255, 1984. 160. L. Yau, C. Hong, and D. Crook, ‘‘Passivation Material and Thickness Effects on the MTTF of Al-Si Metallization,’’ IRPS, pp. 115–118, 1985. 161. J. R. Lloyd and P. M. Smith, ‘‘The Effects of Passivation Thickness on the Electromigration Lifetime of Al/Cu Thin Film Conductor,’’ J. Vac. Sci. Tech., vol. Al, no. 3, pp. 455–458, Apr.–June 1985. 162. L. E. Felton, D. H. Norbury, J. A. Schwartz, and R. W. Pasco, ‘‘Composition Grain Size and Passivation Thickness Effects on Electromigration of Al-Alloy Films,’’ ECS Presentation, New Orleans, LA, Oct. 1984. 163. F. M. d’Heurle and A. Gangulee, ‘‘Effects of Complex Alloy Additions on Electromigration in Aluminium Thin Films,’’ IRPS, pp. 165–169, 1972.

370

ELECTROMIGRATION-INDUCED FAILURE ANALYSIS

164. A. Gangulee and F. M. d’Heurle, ‘‘Effect of Alloying Additions on Electromigration Failure in Thin Aluminium Films,’’ Appl. Phys. Lett., vol. 19, pp. 76–77, 1971. 165. I. Ames, F. M. d’Heurle, and R. E. Horstmann, ‘‘Reduction of Electromigration in Aluminium Films by Copper Doping,’’ IBM J. Res. Dev., vol. 14, pp. 461–463, 1970. 166. M. C. Shine and F. M. d’Heurle, ‘‘Activation Energy for Electromigration in Aluminium Films Alloyed with Copper,’’ IBM J. Res. Dev., pp. 378–383, Sept. 1971. 167. H. Harada, S. Harada, Y. Hirate, T. Naguchi, and H. Mochizuki, ‘‘Perfect Hillockless Metallization (PHM) Process for VLSI,’’ IDEM Tech. Dig., pp. 46–49, Dec. 1986. 168. H. J. Bhatt, ‘‘Superior Aluminium for Interconnection of Monolithic Integrated Circuits,’’ IDEM Tech. Dig., pp. 48–50, Oct. 1970. 169. C. J. Delloca and A. J. Learn, ‘‘Anodization of Aluminium to Inhibit Hillock Growth and High Temperature Processing,’’ Thin Solid Films, vol. 8, pp. R47–R50, 1971. 170. L. E. Terry and R. W. Wilson, ‘‘Metallization Systems for Silicon Integrated Circuits,’’ Proc. IEEE, vol. 57, pp. 1580–1586, 1969. 171. Mil-Hdbk-217D, Reliability Prediction of Electronic Equipment, Reliability Analysis Center, RADC, 1982. 172. D. F. Frost and K. F. Poole, ‘‘A Method for Predicting VLSI-Device Reliability Using Series Models for Failure Mechanisms,’’ IEEE Trans. Reliabil., vol. R-36, no. 2, pp. 234– 242, 1987. 173. J. W. Harrison, Jr., ‘‘A Simulation Model for Electromigration in Fine-Line Metallization of Integrated Circuits Due to Repetitive Pulsed Currents,’’ IEEE Trans. Electron Devices, vol. 35, no. 12, pp. 2170–2179, Dec. 1988. 174. J. Tao, N. W. Cheung, and C. Hu, ‘‘Electromigration Characteristics of Copper Interconnects,’’ IEEE Electron Devices Lett., vol. 14, no. 5, pp. 249–251, May 1993. 175. B. K. Liew, N. W. Cheung, and C. Hu, ‘‘Projecting Interconnection Electromigration Lifetime for Arbitrary Current Waveforms,’’ IEEE Trans. Electron Devices, vol. 37, no. 5, p. 1343, 1990. 176. A. K. Goel and M. M. Leipnitz, ‘‘Analysis of the Electromigration Induced Failure in the VLSI Interconnection Components and the Multisection Interconnections,’’ ﬁnal report submitted to the USAF-RDL Faculty Summer Research Program sponsored by the Air Force Ofﬁce of Scientiﬁc Research, July 1991. 177. D. F. Frost, K. F. Poole, and D. A. Haeussler, ‘‘RELIANT: A Reliability Analysis Tool for VLSI Interconnects,’’ Proc. IEEE Custom Integrated Circuits Conf., pp. 27.8.1–27.8.4, 1988. 178. J. E. Hall, D. E. Hocevar, P. Yang, and M. J. McGraw, ‘‘SPIDER—A CAD System for Checking Current Density and Voltage Drop in VLSI Metallization Patterns,’’ Proc. Int. Conf. Comp. Aided Design, pp. 278–281, 1986. 179. J. W. McPherson and P. B. Ghate, ‘‘A Methodology for the Calculation of Continuous DC Electromigration Equivalents from Transient Current Waveforms,’’ J. Electrochem. Soc., vol. 85–6, p. 64, 1985.

CHAPTER SIX

Future Interconnections In this chapter, the interconnection technologies that seem promising for future highspeed ICs are discussed. The chapter is organized as follows: Advantages, issues, and challenges associated with optical interconnections are discussed in Section 6.1. Transmission line models for lossy optical waveguide interconnections are derived in Section 6.2. Propagation characteristics for superconducting interconnections and their comparison with normal metal interconnections are presented in Section 6.3. Several potential interconnection technologies for nanotechnology circuits are outlined in Section 6.4.

6.1

OPTICAL INTERCONNECTIONS

As ICs become larger in size and faster in speed, a large fraction of the available chip area and bandwidth is used by the interconnection system. Pinout and pin capacitance limitations place severe restrictions on the size and speed realizable for the IC. Furthermore, a large amount of power is used in driving the communication lines only. For example, on a typical current-steering Schottky logic chip, 80% of its power is consumed in driving its communication lines [1]. Thus, conventional interconnections are becoming a major problem in the development of nextgeneration VLSI systems. The optical interconnection technology is emerging rapidly to provide relief from the problems associated with conventional interconnections [2]. Techniques have been developed to integrate optical devices and materials with electronic circuits. It High-Speed VLSI Interconnections, Second Edition By Ashok K. Goel Copyright # 2007 John Wiley & Sons, Inc.

371

372

FUTURE INTERCONNECTIONS

is now possible to integrate optoelectronic devices such as photodiodes, lightemitting diodes (LEDs), and laser diodes with high-density silicon-based electronic circuits by depositing GaAs or other heterostructure layers on top of a processed silicon wafer and building the optical devices in the layers [3]. Techniques for constructing optical waveguides and mirrors on a silicon substrate have also been developed [4–6]. In this section, the advantages, challenges, and other issues associated with optical interconnections are addressed [4]. 6.1.1

Advantages of Optical Interconnections

On-chip as well as chip-to-chip optical interconnections offer several advantages over conventional interconnections in that they do not suffer from the drawbacks of the latter. As stated above, the drawbacks of conventional interconnections become more pronounced when the IC becomes more complex either by scaling down the transistor sizes or by scaling up the chip size [7]. The ﬁrst drawback of conventional interconnections results from their capacitive loading effects, which increase as the chip size increases. In fact, in present-day chips, interconnection delays dominate device delays and chip speed is limited primarily by the delays associated with the interconnection capacitances. On the other hand, optical interconnections are free from any capacitive loading effects. The speed of propagation of a signal using an optical interconnection is determined by the speed of light and the refractive index of the optical transmission medium only. Even if the times taken to convert from electrical signal to optical signal and back are taken into consideration, optical interconnections turn out to be as fast as conventional interconnections for distances as small as a millimeter and, for longer distances, an optical interconnection is much faster than a conventional metallic interconnection. The second drawback of conventional interconnections is the crosstalk among the nearby electrical paths which is also caused by stray and other coupling capacitances among the interconnections. This crosstalk increases as the interconnections are brought closer and as the signal bandwidth is increased. Further, as the signal frequency goes up, the self and mutual inductances of the metal interconnections go up, resulting in higher crosstalk. In contrast, optical interconnections do not suffer from the problem of crosstalk. The next drawback of conventional interconnections is the limitation on the number of pinouts available for chip-to-chip connections on a chip. According to a well-known empirical relationship called Rent’s rule, which applies to random logic circuitry, the number of pins required for chip-to-chip interconnections increases approximately as the 0.61th power of the number of devices and other components on the chip whereas the perimeter available for fabricating these pins increases only as the 0.5th power of the number of devices on the chip. (In general, fewer pins are required for memories and more are required for telecommunications circuitry.) This problem can be alleviated with chip-to-chip optical interconnections because they operate at much higher speeds than conventional input/output (I/O) pins, allowing the multiplexing of a large number of I/O signals in a single I/O ﬁber. Furthermore,

OPTICAL INTERCONNECTIONS

373

optical chip-to-chip interconnections can be anchored directly to the interior of a chip rather than to a pin on its perimeter. The next problem faced by conventional metallic interconnections is their failure caused by electromigration. Electromigration-induced failure becomes more pronounced as the interconnections become smaller. Optical interconnections do not suffer from electromigration. However, it is interesting to note that optical interconnections can break down due to optical damage, which occurs only in certain materials at rather high optical power densities. For example, for the optical medium LiNbO3, the threshold for optical damage is of the order of tens of kilowatts per square centimeter and that for other optical dielectric materials such as glass and oxides is an order of magnitude higher. It should be noted that when the limitations of conventional VLSI systems are alleviated by using optical interconnection technologies, several new computing architectures become available allowing much quicker handling of complex problems such as matrix operations, digital ﬁltering, distributed symbolic connections, and other interconnection-intensive algorithms. Furthermore, optical chip-to-chip interconnections offer the promise of signiﬁcantly enhancing the performance of high-throughput performance systems such as supercomputers, ﬁfth-generation computing systems, and massively parallel SIMD and MMID machines [8]. 6.1.2

Systems Issues and Challenges

In order to develop large systems with optical interconnections, several researchers have chosen to employ thin-ﬁlm waveguides rather than free-space, holographic, or optical ﬁber interconnections. This is primarily because the planarity of substrates with thin-ﬁlm waveguides on them allows the use of conventional processing techniques whereas the use of optical ﬁbers for intrachip communication may require specialized equipment and holographic techniques are less mature than thinﬁlm techniques. However, it should be noted that the use of thin-ﬁlm waveguides poses alignment and coupling problems which can be resolved by careful process control. The material chosen for the development of systems with optical interconnections depends on several factors. For constructing optical devices, many researchers have used epitaxial deposition on silicon substrate because silicon offers a stable base for electronic circuitry and because long-wavelength optics requires epitaxial techniques on silicon or gallium arsenide. An additional advantage of silicon-based processing is that, by developing an epitaxial technique for silicon that can yield 3D structures, one can still incorporate a layer of GaAs circuitry where extremely high speed, available only with GaAs, is required. For example, GaAs circuitry may be used to provide multiplexors to achieve speed matching between the electronic circuitry and the optical interconnections. Fault tolerance is a crucial issue in the development of large systems with optical interconnections. We have seen that the greatest advantage of optical interconnections lies in the larger systems employing chip-to-chip, wafer-to-wafer, or board-to-board

374

FUTURE INTERCONNECTIONS

connections rather than in a smaller system employing the on-chip connections, and these are the systems having the greatest need for fault tolerance. 6.1.3

Material Processing Issues and Challenges

The development of optical interconnection systems requires specialized material processing techniques. One of the processing technique that has shown great promise in this ﬁeld is called molecular beam epitaxy (MBE). Currently, MBE is used primarily as a research tool and it is important to make it widely available as a manufacturing process. Molecular beam epitaxy can be used to build 3D structures needed to build optoelectronic systems. For example, it can be used to deposit layers of compound semiconductors such as GaAs, GaInAlAsP, InAlAsP, and so on, to construct superlattices. The techniques to build optoelectronic components such as photodiodes, LEDs, and laser diodes using MBE need to be reﬁned. It is also important to reﬁne the etching and material deposition techniques for constructing optical waveguides, mirrors, etc. Techniques for anchoring optical ﬁbers onto any part of a substrate with great accuracy need to be developed. Reliable connections between the Si and GaAs layers are required. It will be extremely helpful to integrate the processes for Si and GaAs which, at present, are very different [9]. Last but not least, it is obvious that the optical interconnection technology will require many more processing steps than the electronic circuits and it may be necessary to develop techniques to decrease the number of these steps to achieve an acceptable yield. 6.1.4

Design Issues and Challenges

Integrating on-chip and chip-to-chip optical interconnections with the electronic circuitry requires careful designing of the various optical structures such as the optical waveguides, detectors, sources, and so on. A few well-known materials for constructing optical waveguides are glass, zinc oxide, and silicon nitride. Material selection for the optical waveguide depends on several factors, such as the refractive index of the material, attenuation at the wavelength of operation, ease of patterning, and ease of deposition. Channels with very smooth side walls are formed in the substrate, such as silicon, by an etching mechanism so that the light beam does not suffer signiﬁcant loss due to scattering. The channels are tapered down to the size of the optical detector such that the transition from the waveguide to the detector is very gradual and does not cause any serious loss of signal. The material in which the optical detector is fabricated depends on the wavelength of the optical signal. In near-future applications, it is expected that the optical signal will be in the near infrared and optical detectors can be fabricated on the silicon wafer itself because silicon is the best known detector material at these wavelengths. However, silicon cuts off at 1.1 mm and, therefore, for optical signals of wavelength greater than 1.1 mm, the detectors and the sources will have to be fabricated in an InP-type compound semiconductor.

TRANSMISSION LINE MODELS OF LOSSY OPTICAL WAVEGUIDE

375

For fabricating an optical source, silicon is not a suitable substrate because it is an indirect bandgap material. On the other hand, GaAs is an excellent material for fabricating an extremely efﬁcient and reliable light source. The best way of utilizing the silicon-based electronic circuitry with the GaAs source depends on successful heteroepitaxial techniques of depositing GaAs on silicon. This is done by ﬁrst depositing a layer of germanium (Ge) on silicon because Ge and GaAs have closely matching lattice constants. The bandwidth of the structure will depend on the ability of the light source to modulate at high frequencies. Further, the power from the source should be high enough for long-distance communication.

6.2

TRANSMISSION LINE MODELS OF LOSSY OPTICAL WAVEGUIDE INTERCONNECTIONS

In its crudest form, at very low frequencies, the behavior of an interconnection line is determined by its line capacitance, driving source impedance, and load impedance. As the frequency increases, the interconnection can be satisfactorily modeled as a distributed RC transmission line. As the frequency increases further, the line inductance becomes important and the interconnection can be modeled as an RLC transmission line. Further, as is well known, a transmission line is characterized by a series impedance R þ j o L and a shunt admittance G þ j o C, where R, L, G, and C are the resistance, inductance, conductance, and capacitance per unit length and o is the frequency in radians per second. In general, an interconnection line behaves as a waveguide which, in turn, is analyzed by solving Maxwell’s equations for electric and magnetic ﬁelds. However, for the sake of continuity, with RC and RLC transmission line models of an interconnection, it is desirable to derive a transmission line model of a waveguide. It is interesting to note that waveguides and transmission lines are analogous in that waveguides propagate waves of electric and magnetic ﬁelds while transmission lines propagate waves of voltage and current. Further, if z direction is the direction of propagation, then the transverse electric ﬁeld in the waveguide and voltage wave in the corresponding transmission line have the same z dependence. Also, the z dependences of the transverse magnetic ﬁeld in the waveguide and current wave in the corresponding transmission line are the same. In this section, the R, L, G, and C are found for a transmission line that models a lossy waveguide characterized by a complex propagation constant and a complex average power ﬂow [10]. First, these are derived for the simpliﬁed case of a lossy waveguide with only one propagating wave with no reﬂections and then the analysis is carried out starting from Maxwell’s equations for the general case of a lossy waveguide in an inhomogenous medium. Equivalent circuits for the driver and load are also derived. 6.2.1

Lossy Waveguide with Single Propagating Wave

To derive the parameters of the equivalent transmission line in this case, we assume that, either from measurements or by solving Maxwell’s equations, two waveguide

376

FUTURE INTERCONNECTIONS

parameters, that is, the complex propagation constant g and the complex average power (P) traveling down the waveguide, are known. We can write for the propagation constant g ¼ a þ jb

ð6:2:1Þ

where a is the attenuation constant and b is the phase constant. The average power P can be expressed in terms of Poynting’s vector as P¼

1 2

Z

Z dx

ðE H Þz dy

ð6:2:2Þ

where the asterisk denotes the complex conjugate. Assuming propagation of a single wave traveling in the z direction, the electric ﬁeld is given by the real part of Eðx; y; z; tÞ ¼ Eðx; yÞeðgzþjotÞ

ð6:2:3Þ

For the corresponding transmission line, the propagation constant g is given by g2 ¼ ðR þ joLÞðG þ joCÞ

ð6:2:4Þ

and, for the case of a single propagating wave with no reﬂections and a single mode of propagation, the complex average power PðzÞ is given in terms of the voltage VðzÞ and current IðzÞ by the expression 1 1 1 jVðzÞj2 PðzÞ ¼ VðzÞIðzÞ ¼ jIðzÞj2 Z0 ¼ 2 2 2 Z0

ð6:2:5Þ

where Z0 is the complex characteristic impedance. We require that the propagation constant g for the waveguide and the average power P traveling down the waveguide are the same as these quantities for the corresponding transmission line. Writing P and Z0 in terms of their real and imaginary parts as P ¼ Pr þ jPi

ð6:2:6Þ

Z0 ¼ Z0r þ jZ0i

ð6:2:7Þ

we can deﬁne a power quotient Q at any position along the line as Q

Pi Z0i ¼ Pr Z0r

ð6:2:8Þ

It should be noted that Q is independent of position z because both the real and imaginary parts of P attenuate at the same rate expð2azÞ.

TRANSMISSION LINE MODELS OF LOSSY OPTICAL WAVEGUIDE

377

From the transmission line equations, the characteristic impedance Z0 is given by Z02 ¼

R þ joL G þ joC

ð6:2:9Þ

Using Eq. (6.2.4), we can write

R þ joL R þ joL ¼ Z0 ¼ g a þ jb

ð6:2:10Þ

Using Eq. (6.2.10) in Eq. (6.2.8), we can write Q¼

aoL bR aR þ boL

ð6:2:11Þ

Using Eqs. (6.2.4) and (6.2.9), Z0 can also be expressed as Z0 ¼

g a þ jb ¼ G þ joC G þ joC

ð6:2:12Þ

Using Eq. (6.2.12) in Eq. (6.2.8), we can write Q¼

bG aoC boC þ aG

ð6:2:13Þ

From Eqs. (6.2.11) and (6.2.13), we can derive the following equations: oL aQ þ b ¼ R a bQ

ð6:2:14Þ

oC aQ b ¼ G a þ bQ

ð6:2:15Þ

a2 b2 Q2 1 þ Q2

ð6:2:16Þ

GR ¼

o2 LC ¼

a2 Q2 b2 1 þ Q2

ð6:2:17Þ

Equations (6.2.14)–(6.2.17) can be used to ﬁnd the values of R, L, G, and C for the equivalent transmission line in terms of the known values of g and Q for the waveguide. It should be noted that g and Q depend on the mode of propagation in the waveguide and hence the parameters R, L, G, and C will be different for each mode of propagation. Also, note that Eq. (6.2.17) is not independent; it follows from multiplying Eqs. (6.2.14), (6.2.15), and (6.2.16). Therefore, Eqs. (6.2.14)–(6.2.17) can be used to determine three of the four parameters and the fourth parameter is

378

FUTURE INTERCONNECTIONS

arbitrary and can be chosen to obtain agreement with a particular low-frequency equivalent circuit. It can also be chosen to simplify the equivalent transmission line or the equivalent circuit of any driver or termination. It is interesting to note that, for a three-parameter transmission line, the power quotient Q depends on the propagation constant g only. For example, if R ¼ 0 or if L ¼ 0, then Eq. (6.2.11) yields 8 a > > R¼0 ð6:2:18Þ < b for Q¼ > b > : for L ¼ 0 ð6:2:19Þ a and, if G ¼ 0 or C ¼ 0, then Eq. (6.2.13) yields 8 a > > < b for G ¼ 0 Q¼ > b > : for C ¼ 0 a

ð6:2:20Þ ð6:2:21Þ

Conversely, it can be stated that if the power quotient of a waveguide is given approximately by the ratio ða=bÞ or its inverse, then it can be modeled approximately by a three-parameter transmission line. 6.2.2

Equivalent Circuits for Waveguide Drivers and Loads

Now, we need to ﬁnd the transmission line load impedance and the Thevenin voltage source (or Norton current source) equivalent circuit for the waveguide driver in terms of the known waveguide parameters. To accomplish these objectives, we note that z dependences of both the transverse electric ﬁeld in the waveguide and the voltage in the equivalent transmission line are given by the function VðzÞ ¼ Aegz þ Begz

ð6:2:22Þ

where A and B are the forward and reﬂected wave amplitudes determined by the driver and the load. Similarly, the z dependences of both the transverse magnetic ﬁeld in the waveguide and the current in the equivalent transmission line are given by the function IðzÞ ¼

1 ½Aegz Begz Z0

ð6:2:23Þ

Now, the reﬂection coefﬁcient L looking toward the load is the quantity characteristic of the waveguide termination and is deﬁned as L ¼

B A

ð6:2:24Þ

TRANSMISSION LINE MODELS OF LOSSY OPTICAL WAVEGUIDE

379

The load impedance ZL for the equivalent transmission line can now be determined by requiring that it result in the same L as exists in the waveguide. Therefore, if ‘ is the length of the transmission line, then Eqs. (6.2.22) and (6.2.23) yield, at z ¼ ‘, ZL

Vð‘Þ 1 þ L eð2g‘Þ ¼ Z0 Ið‘Þ 1 L eð2g‘Þ

ð6:2:25Þ

Since both L and g are ﬁxed by the wave behavior in the waveguide and Z0 is determined by conditions (6.2.14)–(6.2.17) and the requirement of agreement with a low-frequency circuit, the load ZL can be determined from Eq. (6.2.25). For the waveguide driver, the Thevenin voltage source equivalent circuit (input voltage Vin and impedance Zin ) for the corresponding transmission line can be determined by requiring that the equivalent circuit result in the correct complex input power Pin and the correct reﬂection coefﬁcient from the driver ðD Þ. The input power is given by 1 1 Vin Pin ¼ Vin Ið0Þ ¼ Vin Zin þ Zi 2 2

ð6:2:26Þ

where Zi is the line input impedance, which can be determined from Eqs. (6.2.22) and (6.2.23) to be Vð0Þ 1 þ L ¼ Z0 Zi 1 L Ið0Þ

ð6:2:27Þ

The impedance Zin is given by Zin ¼ Z0

1 þ D 1 D

ð6:2:28Þ

Then, using Eqs. (6.2.27) and (6.2.28), Eq. (6.2.26) becomes 1 2 1 ð1 D Þð1 L Þ Pin ¼ jVin j 4 Z0 1 D L

ð6:2:29Þ

Knowing the power input to the waveguide and the two reﬂection coefﬁcients D and, L , jVin j can be determined. The reﬂection coefﬁcients can be determined from standing-wave measurements in the waveguide or by calculations in certain special cases. 6.2.3

Lossy Waveguide in Inhomogenous Medium

In this section, the transmission line parameters R, L, G, and C for a transmission line equivalent to a lossy waveguide in an inhomogenous medium are derived from

380

FUTURE INTERCONNECTIONS

Maxwell’s equations. In this case, the material parameters of the waveguide medium are taken as complex and dependent on the transverse position. In other words, if the z direction is the direction of propagation, then the dielectric permittivity e and magnetic permeability m are given by sðx; yÞ jo m ¼ m1 ðx; yÞ þ jm2 ðx; yÞ e ¼ e0 kðx; yÞ þ

ð6:2:30Þ ð6:2:31Þ

where k is the dielectric constant and s is the conductivity of the medium. The electric and magnetic ﬁelds at any angular frequency o are also considered to be complex and are given by Eðx; y; zÞ ¼ Et ðx; yÞVðzÞ þ ZEl ðx; yÞIðzÞ 1 Hðx; y; zÞ ¼ Ht ðx; yÞIðzÞ þ Hl ðx; yÞVðzÞ Z

ð6:2:32Þ ð6:2:33Þ

where the subscript t denotes the transverse vector with x and y components, the subscript l denotes a longitudinal component in the z direction, and Z is the intrinsic impedance of empty space given by s ﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ m0 376:7 Z¼ e0

ð6:2:34Þ

It should be noted that the electric and magnetic ﬁelds given by Eqs. (6.2.32) and (6.2.33) represent one mode of propagation only; a general solution of Maxwell’s equations will be given by summations over all propagation modes. 6.2.3.1 Separation of Longitudinal and Transverse Components Assuming a single traveling wave, we will now derive a few basic equations by substituting Eqs. (6.2.32) and (6.2.33) into Maxwell’s equations and separating the longitudinal and transverse components. Substituting Eqs. (6.2.32) and (6.2.33) into the Maxwell equation r E ¼ jomH

ð6:2:35Þ

we get d VðzÞ r Et ðx; yÞ þ VðzÞ^k Et ðx; yÞ þ IðzÞZ r E1 ðx; yÞ dz 1 ¼ jom IðzÞHt ðx; yÞ þ VðzÞ Hl ðx; yÞ Z

ð6:2:36Þ

TRANSMISSION LINE MODELS OF LOSSY OPTICAL WAVEGUIDE

381

where ^k is a unit vector in the z direction. Taking the z components of Eq. (6.2.36), we get jom Hl ðx; yÞ ¼ 0 VðzÞ r Et ðx; yÞ þ Z

ð6:2:37Þ

Since VðzÞ is nonzero, we get r Et ðx; yÞ þ

jom Hl ðx; yÞ ¼ 0 Z

ð6:2:38Þ

Now, taking the transverse components of Eq. (6.2.36), we get Z r El ðx; yÞ þ jomHt ðx; yÞ ¼ ^k Et ðx; yÞ

1 d VðzÞ IðzÞ dz

ð6:2:39Þ

Since the left side of Eq. (6.2.39) is independent of z, it follows that

1 d VðzÞ ¼ const ¼ c1 IðzÞ dz

ð6:2:40Þ

Substituting (6.2.32) and (6.2.33) into the Maxwell equation r H ¼ joeE

ð6:2:41Þ

and following the above steps, we get from the z components IðzÞ½r Ht ðx; yÞ joeZEl ¼ 0

ð6:2:42Þ

and, since IðzÞ is nonzero, we get r Ht joeZEl ¼ 0

ð6:2:43Þ

Taking the transverse components, we get 1 1 d ^ r Hl ðx; yÞ joeEt ðx; yÞ ¼ k Ht ðx; yÞ IðzÞ Z VðzÞ dz

ð6:2:44Þ

Since the left side of Eq. (6.2.44) is independent of z, it follows that

1 d IðzÞ ¼ const ¼ c2 VðzÞ dz

ð6:2:45Þ

382

FUTURE INTERCONNECTIONS

Equations (6.2.40) and (6.2.45) can be written in the form of transmission line equations by choosing the arbitrary constants c1 and c2 as c1 ¼ gZ0 g c2 ¼ Z0

ð6:2:46Þ ð6:2:47Þ

Substituting Eqs. (6.2.32) and (6.2.33) into the Maxwell equation r ½eðx; yÞEðx; y; zÞ ¼ 0

ð6:2:48Þ

we get VðzÞr ½eðx; yÞEt ðx; yÞ þ

d IðzÞeðx; yÞZ^k El ðx; yÞ ¼ 0 dz

ð6:2:49Þ

Using Eqs. (6.2.45) and (6.2.47) in Eq. (6.2.49), we get g VðzÞ r ½eðx; yÞEt ðx; yÞ ½eðx; yÞZ^k El ðx; yÞ ¼ 0 Z0

ð6:2:50Þ

and, since VðzÞ is nonzero, we get r ½eEt

g ðeZ^k El Þ ¼ 0 Z0

ð6:2:51Þ

Substituting Eqs. (6.2.32) and (6.2.33) into the Maxwell equation r ½mðx; yÞHðx; y; zÞ ¼ 0

ð6:2:52Þ

we get IðzÞr ½mðx; yÞHt ðx; yÞ þ

1 d mðx; yÞ^k Hl ðx; yÞ VðzÞ ¼ 0 Z dz

ð6:2:53Þ

which, when combined with Eqs. (6.2.40) and (6.2.46), leads to 1 IðzÞ r ½mðx; yÞHt ðx; yÞ gZ0 mðx; yÞ^k Hl ðx; yÞ ¼ 0 Z

ð6:2:54Þ

and, since IðzÞ is nonzero, we get r ½mHt gZ0

1 ^ mk Hl ¼ 0 Z

ð6:2:55Þ

TRANSMISSION LINE MODELS OF LOSSY OPTICAL WAVEGUIDE

383

Using Eqs. (6.2.46) and (6.2.47) in Eq. (6.2.39), we get gZ0 ^k Et jomHt Zr El ¼ 0

ð6:2:56Þ

and using Eqs. (6.2.46) and (6.2.47) in Eq. (6.2.44), we get g^ 1 k Ht þ joeEt r Hl ¼ 0 Z0 Z

ð6:2:57Þ

In addition, using Eqs. (6.2.46) and (6.2.47) in Eqs. (6.2.40) and (6.2.45), we get the transmission line equations d VðzÞ ¼ gZ0 IðzÞ dz d g IðzÞ ¼ VðzÞ dz Z0

ð6:2:58Þ ð6:2:59Þ

whose general solutions are known to be given by VðzÞ ¼ Aegz þ Begz 1 IðzÞ ¼ ½Aegz Begz Z0

ð6:2:60Þ ð6:2:61Þ

where A and B are the complex amplitudes of the forward and reverse traveling waves whose values can be determined by the characteristics of the driver and load of the line. Eigenvalue Equation for g. Divide Eq. (6.2.38) by m and take the curl of the resulting equation. Next divide Eq. (6.2.51) by e and take the gradient of the resulting equation. Then, subtracting the second equation from the ﬁrst, we get mr

1 1 g g ðr Et Þ r r ðeEt Þ ¼ jom ^k Ht joeEt Z rð^k El Þ m e Z0 Z0 ð6:2:62Þ

Now, taking the cross product of Eq. (6.2.56) with ^k, we get jomð^k Ht Þ ¼ gZ0 Et Z rð^k El Þ

ð6:2:63Þ

Substituting Eq. (6.2.63) in Eq. (6.2.62), we get the eigenvalue equation for g: 1 1 2 2 ð6:2:64Þ m r ðr Et Þ r r ðeEt Þ þ ðg þ o emÞEt ¼ 0 m e The eigenvalues of Eq. (6.2.64) can be discrete, continuous, or a combination of both depending upon the functions e and m.

384

FUTURE INTERCONNECTIONS

6.2.3.2 Power Using Poynting’s vector, the average power at position z in the waveguide is given by 1 PðzÞ ¼ 2

Z

Z dx

dy½Etx Hty Ety Htx VðzÞIðzÞ

ð6:2:65Þ

Since we require that the equivalent transmission line carry the same average as the waveguide, we get PðzÞ ¼ 12 VðzÞIðzÞ

ð6:2:66Þ

Combining Eqs. (6.2.65) and (6.2.66), we get the condition Z

Z dx

dy½Etx Hty Ety Htx ¼ 1

ð6:2:67Þ

Using Eqs. (6.2.62) and (6.2.51), we can eliminate Ht and condition (6.2.67) can be expressed in terms of Et alone as Z

Z

dy Et

dx

Z0 1 r ¼1 r Et o2 eEt jog m

ð6:2:68Þ

Integrating Eq. (6.2.68) by parts and assuming that the ﬁelds vanish at the waveguide boundaries (or at inﬁnity), we get Z

Z dx

1 jog 2 2 dy ðr Et Þ ðr Et Þ o ejEt j ¼ m Z0

ð6:2:69Þ

If we now eliminate Et in Eq. (6.2.67), the condition can be expressed in terms of Ht alone as Z

Z dx

1 2 2 dy ðr Ht Þ ðr Ht Þ o mjHt j ¼ jogZ0 e

ð6:2:70Þ

The conditions (6.2.69) and (6.2.70) normalize the transverse ﬁelds to ensure that both the waveguide power and the transmission line power are given by Eq. (6.2.66). 6.2.3.3 Expressions for R, L, G, and C Using the customary expressions deﬁning g and Z0, that is, g2 ¼ ðR þ joLÞðG þ joCÞ R þ joL Z02 ¼ G þ joC

½Eq:ð6:2:4Þ ½Eq:ð6:2:9Þ

TRANSMISSION LINE MODELS OF LOSSY OPTICAL WAVEGUIDE

385

we can write g Z0 R þ joL ¼ gZ0 G þ joC ¼

ð6:2:71Þ ð6:2:72Þ

Using Eq. (6.2.71) and the normalization condition (6.2.69), we can ﬁnd the following expressions for G and C: # om2 jHl j2 G ¼ dx dy sjEt j Z2 " # Z Z m1 jHl j2 2 C ¼ dx dy ke0 jEt j Z2 Z

Z

"

2

ð6:2:73Þ ð6:2:74Þ

Similarly, using Eq. (6.2.72) and the normalization condition (6.2.70), we can ﬁnd the following expressions for R and L: R¼ L¼

Z

Z dx

Z

Z dx

dy½sZ2 jEl j2 om2 jHt j2

ð6:2:75Þ

dy½m1 jHt j2 ke0 Z2 jEl j2

ð6:2:76Þ

For the case of a homogeneous medium, the corresponding expressions can be found by replacing the transverse and longitudinal ﬁeld quantities with the ﬁeld components in Eqs. (6.2.32) and (6.2.33) to yield G¼ C¼ R¼ L¼

Z

1 jVðzÞj2 1 jVðzÞj jIðzÞj

dx Z

2

1

jIðzÞj2

Z dx

Z

Z dx

2

1

Z

Z

Z dx

dy½sjEn ðx; y; zÞj2 om2 jHz ðx; y; zÞj2

ð6:2:77Þ

dy½ke0 jEn ðx; y; zÞj2 m1 jHz ðx; y; zÞj2

ð6:2:78Þ

dy½sjEz ðx; y; zÞj2 om2 jHn ðx; y; zÞj2

ð6:2:79Þ

dy½m1 jHn ðx; y; zÞj2 ke0 jEz ðx; y; zÞj2

ð6:2:80Þ

where the subscript n denotes the component of the ﬁeld normal to the direction of propagation. After some manipulation, it can be proved that expressions (6.2.73)– (6.2.76) result in the same values of the ratios in Eqs. (6.2.14) and (6.2.15).

386

6.3 6.3.1

FUTURE INTERCONNECTIONS

SUPERCONDUCTING INTERCONNECTIONS Advantages of Superconducting Interconnections

The signal propagation characteristics, including transit delays of the chip-to-chip interconnection lines, have a major effect on the total performance of an electronic system. An attempt to reduce the interconnection delays by scaling down its dimensions results in increased signal losses in the interconnection [11]. This is due to the increased series resistance and higher dispersion of the interconnection. This adverse effect can be almost eliminated by replacing normal metallic interconnections by superconducting interconnections which have very low series resistance at frequencies up to the energy gap frequency of the material [12, 13]. In fact, in recent years, the advent of high-critical-temperature superconductors [14–16] has opened up the possibility of realizing high-density and very fast interconnections on silicon as well as GaAs-based high-performance ICs. The major advantages of superconducting interconnections over normal metal interconnections can be summarized as follows: 1. The signal propagation time on a superconducting interconnection will be much smaller as compared to that on a normal metal interconnection. 2. The packing density of the IC can be increased without suffering from the high losses associated with high-density normal metal interconnections. 3. There is virtually no signal dispersion on superconducting interconnections for frequencies up to several tens of gigahertz. 6.3.2

Propagation Characteristics of Superconducting Interconnections

In this section, an analysis of propagation characteristics [17] on a superconducting microstripline with dielectric thickness td , stripline thickness tc , ground-plane thickness tg , and penetration depth lL shown in Fig. 6.3.1 is presented. In the structure shown in Fig. 6.3.1, material 1 is air with er ¼ 1:0; material 2 is Ba–Y–Cu–O with critical temperature Tc ¼ 92:5 K, normal-state resistivity ðrn Þ ¼ 200 m cm, ˚ material 3 is SiO2 with er ¼ 3:9; material 4 is Ba–Y–Cu–O with and lL ð0Þ ¼ 1400 A; ˚ and material 5 is SiO2 with Tc ¼ 92:5 K, rn ¼ 200 m cm, and lL ð0Þ ¼ 1400 A; er ¼ 3:9. It is assumed that the permeability of each medium is that of free space m0 , the loss tangent of dielectrics is negligible, the fringing ﬁeld effects at the edges of the line can be neglected, and high-Tc superconductors have standard superconducting behavior below Jc, Hc1 , Tc , and energy gap frequency. It can be further assumed that the only nonzero component of magnetic ﬁeld is Hy and that all ﬁelds are independent of y. In other words, in addition to the time dependence given by ejot, the nonzero ﬁeld components in rectangular coordinates are Hy ðxÞegz , Ex ðxÞegz , and Ez ðxÞegz . Using the two-ﬂuid model [18, 19], the total current JT in a superconductor consists of normal current Jn and a supercurrent Js , that is, J T ¼ Jn þ Js

ð6:3:1Þ

SUPERCONDUCTING INTERCONNECTIONS

387

FIGURE 6.3.1 Schematic of superconducting microstrip structure analyzed in this section. (From [17]. # 1987 by IEEE.)

where the supercurrent component obeys London’s equations E ¼ jom0 l2L Js

H ¼ l2L = Js

ð6:3:2Þ

where lL is the penetration depth of the superconductor. The boundary value problem presented in Fig. 6.3.1 can be solved using Eqs. (6.3.1) and (6.3.2) and Maxwell’s equations to obtain the propagation constant g which is valid for frequencies up to several gigahertz (note that the normal-current component is negligible for these frequencies): lL;2 tc lL;4 tg 2 2 þ ð6:3:3Þ coth coth g ¼ m0 e3 o 1 þ td lL;2 td lL;4 According to Eq. (6.3.3), g is purely imaginary, indicating that the propagation characteristics of a superconducting microstripline are lossless and dispersionless. The phase velocity of propagation for the superconducting microstrip is given by o ¼ vp ¼ ImðgÞ

(sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ﬃ)1 lL;2 tc lL;4 tg þ coth coth m0 e3 1 þ td lL;2 td lL;4

ð6:3:4Þ

Equation (6.3.4) indicates that the phase velocity depends strongly on the superconducting layer thickness, penetration depth of the superconducting layers, and dielectric constants of the dielectric layers. Since the penetration depth is a function of temperature given by lL ð0Þ lL ðTÞ ¼ qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 1 ðT=Tc Þ4

ð6:3:5Þ

388

FUTURE INTERCONNECTIONS

the phase velocity also depends on temperature, particularly for temperatures near the critical temperature Tc . It can also be seen from Eq. (6.3.4) that the phase velocity is a function of the dielectric constant only when the dielectric thickness and the superconducting layer thickness are much larger than the penetration depth. Using the two-ﬂuid model, the conductivity of a superconductor is given by [19] " 4 4 # T 1 T j 1 s ¼ snormal 2 Tc Tc m0 o½lL;2 ð0Þ

ð6:3:6Þ

where snormal is the normal-state conductivity of the superconductor at a temperature just above Tc . 6.3.3

Comparison with Normal Metal Interconnections

In this section, a comparison of the propagation characteristics of the superconducting and normal aluminum interconnections at 77 K [17] is presented. The interconnection dimensions and other transmission line parameters for the aluminum line are chosen to be the following: Width of microstrip line ðWÞ 2 mm Thickness of microstrip ðtc Þ 0:5 mm Interdielectric thickness ðtd Þ 1 mm Ground-plane thickness ðtg Þ 1 mm Relative dielectric constant for interdielectric 3.9 Relative dielectric constant for substrate 3.9 Conductivity of 0.5-mm-thick aluminum at 77 K 1:5 106 S/cm Capacitance of line 1.54 pF/cm The inductance of the line for frequencies up to 10 GHz is 2.95 nH/cm (decreasing to 2.25 nH/cm for frequencies above 100 GHz, due to skin effect). The series resistance of the line for frequencies up to 10 GHz is 77.6 /cm (increases as the frequency increases above 10 GHz, due to skin effect) A comparison of the phase velocities at 77 K for the superconducting line and the aluminum line for frequencies up to 1012 Hz is shown in Fig. 6.3.2 and a comparison of the attenuation for the two lines in the frequency range 106–1012 Hz is shown in Fig. 6.3.3. First, for the normal aluminum interconnection line, it can be seen that its phase velocity is much less than that of the superconducting line for frequencies up to 100 MHz. Further, its phase velocity depends very strongly on frequency, indicating that the line is very dispersive. Figure 6.3.3 indicates that, for a normal aluminum line, its maximum useful length (attenuation < 3 dB) is limited by attenuation to be 2 cm at 100 MHz and only 2 mm at 10 GHz. For the superconducting interconnection line, it can be seen from Fig. 6.3.2 that its phase velocity is nearly constant at frequencies up to 1 THz at 77 K; that is, the

SUPERCONDUCTING INTERCONNECTIONS

389

FIGURE 6.3.2 Comparison of phase velocities at 77 K for superconducting and normal aluminum lines. (From [17]. # 1987 by IEEE.)

line is virtually nondispersive. However, as shown in Fig. 6.3.3, the attenuation of the superconducting line is a function of frequency and temperature; it is very small for frequencies up to 10 GHz and increases with increasing frequency. Therefore, superconducting interconnections can operate with negligible dispersion and low loss at frequencies of several gigahertz for lengths exceeding several meters.

FIGURE 6.3.3 Comparison of attenuations at 77 K for superconducting and normal aluminum lines. (From [17]. # 1987 by IEEE.)

390

6.4

FUTURE INTERCONNECTIONS

NANOTECHNOLOGY CIRCUIT INTERCONNECTIONS: POTENTIAL TECHNOLOGIES

As progress along the International Technology Roadmap for Semiconductors (ITRS) continues, physical and electromagnetic limitations make scaling of silicon CMOS FETs increasingly difﬁcult. One long-term solution is to replace Si FETs by completely new structures such as nanoscale molecular, biological, or quantum devices. Before considering this changeover, an interconnection technology must be developed that is suitable for these new device concepts. To connect ultrasmall devices, interconnections must be less than 10 nm in diameter. However, they still must be easy to fabricate, have low resistance and high maximum current-carrying capacity, and be isolated by low-k dielectric materials for applications in nanotechnology circuits requiring ultrahigh density of the devices and interconnections. This implies that, in addition to the development of the various nanodevices, interconnections that will be used to connect these devices in nanotechnology circuits should be given a very special attention. It is extremely important to gain an understanding of the parasitic elements such as capacitances and inductances and interconnection performance parameters such as propagation delays, crosstalk, and current-carrying capacities for almost electromigration-free operation for the various interconnection technologies in the nanoscale regime. In the past, such models have been developed for microscale metallic interconnections [20]. In future development of nanoscale ICs, interconnections will play a crucial role. As the sizes of the active devices approach the nanometer dimensions, the wires that connect them must also be scaled down. Several IC manufacturers are in the process of commercializing 100-nm CMOS-based IC technologies and the research and development work for the 70- and 50-nm devices is well underway. Successful IC development below these feature sizes faces the fundamental challenges imposed by the basic lays of quantum physics. In addition, as the diameters of conventional metallic interconnection wires reach the mean free path for electrons, surface scattering from the boundaries of ultranarrow conductors as well as grain boundary scattering would inhibit electronic conduction in the wires to an unacceptable level. Nanotechnology circuits [21–27] with devices on the sub-100-nm scale will require interconnections with sizes from 50 nm down to molecular and atomic dimensions. If metallic conducting lines such as copper are used for the interconnections, then the miniaturization process will result in a rise in copper resistivity because the dimensions of the conducting lines will be of the same order of magnitude as the mean free path of electrons, which is 39.3 nm in copper at room temperature. This rise in resistivity may dramatically slow the circuit’s functioning and as a result jeopardize the ability to improve the circuit speed expected from miniaturization. Electromigration which is the result of momentum transfer from electrons moving under an applied electric ﬁeld to ions making up the lattice structure of the interconnection material imposes another serious problem. Continuing miniaturization of thin-ﬁlm metallic interconnections results in increasingly high current densities leading to the open- and/or short-circuit electrical failures of interconnections in a relatively short time. The higher the

NANOTECHNOLOGY CIRCUIT INTERCONNECTIONS: POTENTIAL TECHNOLOGIES

391

temperature, the higher the electromigration-induced failure of metallic interconnections. In this context, it is important to note that lots of electrons and electron scattering are required for electromigration to take place. It does not occur in semiconductors unless they are so heavily doped that they exhibit metallic conduction. In this section, the various potential interconnection technologies suitable for nanoscale ICs, including metallic interconnections, nanowires, carbon nanotubes, and quantum wires, are reviewed. 6.4.1

Silicon Nanowires and Metallic Interconnections

A nanowire is simply a solid, cylindrical wire with a diameter on the scale of a few nanometers. These can be fabricated from a variety of materials (silicon, germanium, gallium nitride, metals, oxides, etc.) to a length of several micrometers. Semiconductor nanowires are 1D structures with unique electrical and optical properties that are used as building blocks in nanoscale circuit design. Their low dimensionality means that they exhibit quantum conﬁnement effects. One of the challenges lies in understanding the electron conduction and transport properties of these nanowires and how these can be used as interconnections for integrating various nanoscale devices such as single electron transistors and quantum cellular automata. These issues are relevant to the ultimate design of a nanoscale IC regardless of the nature of the active element. As such these issues represent a fundamental element of the road map leading to nanoscale integration. According to C. M. Lieber of Harvard, nanowires ‘‘represent the smallest dimension for efﬁcient transport of electrons and excitons, and thus will be used as interconnections and critical devices in nanoelectronics and nano-optoelectronics.’’ Silicon nanowires, a class of nanowires, are good candidates for nanoscale interconnections [28]. Metal interconnections which are used to connect transistors on an IC chip have become the major bottleneck in furthering chip miniaturization. On-chip interconnections contribute much more to the chip’s overall delay than that caused by the once dominant gate capacitances in transistors. This delay in interconnections is due to the presence of parasitic impedances characteristically seen in metal lines. These impedances are seen in the form of capacitances between an interconnection line and the substrate as well as between interconnection lines in different levels, line resistances, and inductances, both self and mutual, due to induced magnetic ﬁelds. Over the years, researchers have been trying to reduce this delay by reducing the interconnection’s RC time constant. For the 130-nm technology chips, this has been achieved to some extent with the replacement of aluminum with copper to reduce the line’s resistance and by using low-k dielectric materials in the place of the industry standard silicon dioxide to reduce capacitances. However, with ever-increasing frequencies, scaling of minimum feature sizes, the reduction of resistances and capacitances, as well as larger die sizes have all led to a growing dominance of on-chip inductances. These inductances have been largely ignored in the past. However, this trend cannot continue into the future [29, 30]. Inductance effects include ringing and reﬂections which can distort the signals severely. If not considered, further scaling of devices and the use of higher frequencies will increase

392

FUTURE INTERCONNECTIONS

these effects, leading to false switching in transistors and resulting in the chip’s failure. To sum up, it is crucial to understand the effects of interconnection inductances on various signal and design parameters such as signal rise and fall times, power dissipation, repeater insertion processes, and signal propagation. It is particularly true for nanoscale interconnections which are expected to be used for the 65-nm technology chips and onward. ‘‘Multipath interconnection,’’ a modiﬁed version of the traditional metallic interconnection proposed as a possible solution of the interconnection problem for some nanoscale circuits [31, 32], is discussed in Chapter 1. The modiﬁcation consists of using the concept of parallel processing by providing two or more paths between the driver and the load to carry the signal, as shown in Fig. 1.1.2. These paths are stacked vertically isolated from one another by insulating layers between them, thereby taking the same area on the chip as a standard single-path interconnection. Such a structure can carry much larger currents on the chip, and this interconnection structure can be built by an extension of the existing microelectronics fabrication infrastructure. Computer simulations of the propagation delays expected in a multipath interconnection indicate that the overall interconnection delay would decrease as the number of paths is increased [31]. An analysis of the electromigration-induced failure of a multipath interconnection suggests that the MTF increases as the number of paths is increased [31]. Clearly the multipath interconnection shows great promise for microelectronic circuits or hybrid circuits consisting of both microelectronic and nanotechnology devices. 6.4.2

Nanotube Interconnections

Nanotubes are tiny tubes about 10,000 times thinner than a human hair and consist of rolled-up sheets of carbon hexagons. Discovered in 1991 by researchers at NEC, they have the potential for use as minuscule wires in ultrasmall electronic devices. As shown in Fig. 6.4.1, there are two main types of carbon nanotubes (CNTs) that can have high structural perfection. Single-walled nanotubes (SWNTs) consist of a single graphite sheet seamlessly wrapped into a cylindrical tube. Multiwalled

FIGURE 6.4.1 (a) Single-walled CNT. (b) Multiwalled CNT. (From [39]. # 2004 by IEEE.)

NANOTECHNOLOGY CIRCUIT INTERCONNECTIONS: POTENTIAL TECHNOLOGIES

393

nanotubes (MWNTs) comprise an array of such nanotubes that are concentrically nested like rings of a tree trunk [33]. Multiwall nanotubes are generally in the range of 1–25 nm in diameter while SWNTs have diameters in the range of 1–2 nm. Both SWNTs and MWNTs are usually many micrometers long and hence can ﬁt well as components in sub-micrometer-scale devices and nanocomposite structures that may play an important role in emerging technologies. IBM has recently been able to manipulate the nanotubes in a controlled way. It has developed the capability of changing a nanotube’s position, shape, and orientation as well as cutting it by using an atomic force microscope. NASA researchers have reported a new method for producing ICs using CNTs instead of copper for interconnections. This technology may extend the life of the silicon chip industry by 10 years. The electrical properties of CNTs are fascinating because they can exhibit metallic or semiconducting behavior depending on their structure and dimensions. This has made CNTs a unique candidate material for potential nanotechnology applications as nanoscale electronic devices and interconnections [34–36]. To a large extent, the unique electrical properties of CNTs such as their extremely low electric resistance are derived from their 1D character and the unique electronic structure of graphite. Resistance primarily occurs due to defects in crystal structure, impurity atoms, or an atom vibrating about its position in the crystal. In the case of a CNT, the electrons are not so easily scattered. Due to their small diameter and huge aspect ratio (length to width), nanotubes are essentially 1D systems and therefore electrons have a low chance of scattering, giving rise to very low resistance. The electronic properties of perfect MWNTs are rather similar to those of perfect SWNTs because the coupling between the cylinders is weak in MWNTs. Electrical transport in metallic SWNTs and MWNTs is ballistic, that is, without scattering over long nanotube lengths, enabling them to carry high currents with essentially no heating. In contrast, electrons in copper travel only 40–50 nm before they scatter. Phonons also propagate easily along the nanotube. Superconductivity has also been observed at low temperatures with transition temperatures of nearly 0.55 K for 1.4-nm-diameter SWNTs and nearly 5 K for 0.5-nm SWNTs. The low resistance ensures that the energy dissipated in CNTs is very small, thereby solving the problem of dissipated power density that adversely affects silicon circuits. Current densities of more than 1010 A/cm2 have been reported for the metallic conﬁguration of CNTs. Since CNTs do not have any leftover bonds, there is no need to grow a ﬁlm on the surface in order to tie up the free bonds and there is no need to restrict the gate insulator to silicon dioxide. This fact implies the use of other superior materials to insulate the gate terminal in a transistor which can result in a much faster device. The properties of CNTs can be summarized as follows: 1. The carrier transport is 1D, resulting in ballistic transport with no scattering and much less power dissipation. Scattering-free current transport allows high current densities and improved signal delays.

394

FUTURE INTERCONNECTIONS

2. All chemical bonds of the carbon atoms are satisﬁed and there is no need for chemical passivation of free bonds as in silicon. 3. The strong C–C covalent bonding gives the CNTs high mechanical and thermal stability and resistance to electromigration. Current densities as high as 1010 A/cm2 can be sustained in metallic CNTs. 4. The diameter of a CNT is controlled by chemistry, not by fabrication. 5. Both active devices and interconnections can be made of semiconducting and metallic nanotubes. 6. Thermal conductivity along the axis is roughly twice that of diamond. Carbon nanotubes have shown great promise for use as interconnections in nanotechnology circuit applications. This is particularly because they can conduct large currents of the order of a 106 A/cm2 without any deterioration, thus avoiding the electromigration problems characteristic of metallic interconnections. The scatteringfree transport of electrons possible in defect-free CNTs is a very attractive feature of CNTs for microelectronic applications. The reduction in the thickness of conventional metallic or polycrystalline interconnections leads to additional scattering at the surfaces and grain boundaries, thereby deteriorating the interconnection resistance. Carbon nanotudes provide undistributed quasi-crystalline wirelike structure where pulses can travel uninterrupted by length-dependent ohmic scattering. The approximate estimation of signal delays with a simple model proves that nanotubes would surpass classical wires with respect to signal delays. Plenty of work on using CNTs for building ICs is in progress [37–40]. Researchers are also trying to develop complex gates and circuits by fabricating devices along the length of a single CNT. 6.4.2.1 Nanotube Vias The ability to grow nanotubes at speciﬁc sites has helped researchers to design CNT vias [41]. Vias are deﬁned as interconnections between wiring layers in chips and are prone to deterioration due to current crowding and electromigration. Carbon nanotubes have been proposed as the alternative for metal plugs to overcome these problems. Ultra-large-scale integrated (ULSI) circuits have problems that originate from stress and electromigration of copper interconnections, particularly the vias. One proposed solution for this problem is to use CNTs with large migration tolerance as vias. Bundles of CNTs must be used as vias to get enough current for large-scale integrated (LSI) interconnections. Hot-ﬁlament chemical vapor phase deposition (HF-CVD) can be used to grow CNT bundles in the via holes. Mechanical polishing with diamond slurry can be done to control the length of the CNT vias after their growth. Figure 6.4.2a suggests that the total resistance of the CNT via is about three orders of magnitude lower than that of a single CNT and that there is no visible degradation of the via current with time as shown in Fig. 6.4.2b. Such measurements show that the current ﬂows in parallel through the thousands of nanotubes used in the vias which are end bonded to the upper and lower electrodes [41]. The total resistance of a CNT via with about 5000 nanotubes has been shown to be about 1 , and this resistance can be

(a)

Current (mA)

(b)

Total resistance (Ω)

NANOTECHNOLOGY CIRCUIT INTERCONNECTIONS: POTENTIAL TECHNOLOGIES

108 107 106 105 104 103 102 10 1

395

One CNT bridge Three CNT bridge CNT via

10 102 103 Number of CNTs

1

104

20 15 10 2 × 106 A/cm2 5 0

0

20

40

60

80

100

120

Time (hour) FIGURE 6.4.2 (a) Dependence of resistance of CNT bundle on number of CNTs in bundle. Resistances of one-CNT bridge, three-CNT bridge, and typical CNT via also shown. (b) Dependence of current in CNT via on time. (From [41]. # 2004 by IEEE.)

further reduced by improvements in nanotube quality. The density of CNTs needs to be increased and the diameters of nanotubes need to be decreased for fabricating more effective CNT vias. It is expected that CNT bundle vias will prove to be effective replacements for copper vias for future ULSI interconnections. 6.4.2.2 Comparison of Nanotubes and Copper Interconnections The potential performance of CNT interconnections and their relative comparison to copper interconnections can be studied using physical models [42]. Nanotube bundles offer better performance than single nanotubes in which wave propagation is relatively slower. As the interconnection size decreases, the performance of copper interconnections goes down due to the increased resistivity as well as electromigration problems, and CNTs have been proposed to be effective replacements due to the ballistic ﬂow of electrons with electron mean free path of several micrometers. Latencies of ideal CNT and copper interconnections are plotted in Fig 6.4.3. A singlewall nanotube results in a very high contact resistance and high characteristic impedance, and hence a bundle of closely packed parallel CNTs is preferably used above a ground plane. The properties of the desired nanotube bundle include: 1. Good connections to all nanotubes within the bundle. 2. Distance between nanotubes within the bundle should be as small as possible to have the largest nanotube density. 3. Quantum coupling between the nanotubes should be nearly zero.

396

FUTURE INTERCONNECTIONS

80

W

SWCNTs Above a Ground Plane Copper Wires Bundle of SWCNs

2d0 d0

dg 0

10

20

30

40

50

8

60

0.25

6

Latency, τ (ps)

d0 = Inm, dg = 2d0

0.3

W

0.2 4

40

T

0.15 0.1

2

H

0.05 0 0

2

4

6

8

0 10

W 20

T H W = T = H = 27nm

0

0

20

40

60

80

100

Interconnect Length, L (µm)

FIGURE 6.4.3 Dependence of latency on interconnect length for ideal single-layered carbon nanotubes above ground plane, 22-nm node copper wires (expected in 2016), and bundles of ideal SWCNTs for n > 100. (From [42]. # 2005 by IEEE.)

The ITRS predicts that the latency for carbon nanotube bundles will be given by [42] tbundle ¼ 0:7Rtr ðcbundle L þ CL Þ where Rtr is the driver resistance, CL is the load capacitance, and L is the interconnection length. The diameters of the SWCNs can be less than 1 nm and a bundle of, for instance, 400 SWCNs can be as narrow as 20 nm. Assuming that the SWCNT resistance increases exponentially with length, Fig. 6.4.4 shows the latencies of SWCNT bundles and copper interconnections (implemented at 22-nm node) versus the interconnection length for electron mean free path, for L0 ¼ 5 mm and L0 ¼ 10 mm. This ﬁgure suggests that there is a length beyond which the latency of SWCNT bundles becomes larger than that of copper wires. This critical length is roughly 10 times the electron mean free path in SWCNTs. From Fig. 6.4.4, one can infer that compared to the 22-nm copper node, the bundles are about 30% faster for a mean free path of 5 mm while they can be nearly 80% faster if a mean free path of 10 mm is achieved. Assuming that the SWCNT resistance increases linearly with length, dependences of the latency on the interconnect length for a 22-nm node copper wire and bundles of SWCNTs with electron mean free paths of 0.1, 1, and 10 mm are shown in Fig. 6.4.5.

NANOTECHNOLOGY CIRCUIT INTERCONNECTIONS: POTENTIAL TECHNOLOGIES

397

200 Copper Interconnects SWCT-Bundles, L0=5.0 µm SWCN-Bundles, L0=10 µm

Latency, τ (ps)

150

22nm Node, Year 2016

100

50

0 0

50 100 Interconnect Length, L (µm)

150

FIGURE 6.4.4 Dependence of latency on interconnect length for 22-nm node copper wire and bundles of SWCNTs with electron mean free paths of 5 and 10 mm. It is assumed that SWCNT resistance increases exponentially with length. (From [42]. # 2005 by IEEE.)

6.4.2.3 Carbon Nanotubes for High-Frequency Applications In the near future, CNTs are expected to be used for high-frequency applications. Models of the AC properties of CNTs are still in developing stages. Concepts such as quantum capacitance and AC impedance of 1D quantum systems are discussed only in theory. Little data are available to validate high-frequency device models for nano scale devices [43]. A proposed circuit model for understanding the AC impedance of a single-walled nanotube with DC contacts on both sides is shown in

100 CNT Bundles, L0 = 0.1µm Copper Interconnects CNT Bundles, L0 = 1µm CNT Bundles, L0 = 10µm

Latency, τ (ps)

75

50

25

0

0

20

40 60 80 Interconnect Length, L (µm)

100

FIGURE 6.4.5 Dependence of latency on interconnect length for 22-nm node copper wire and bundles of SWCNTs with electron mean free paths of 0.1, 1, and 10 mm. It is assumed that SWCNT resistance increases linearly with length. (From [42]. # 2005 by IEEE.)

398

FUTURE INTERCONNECTIONS

FIGURE 6.4.6 (a) Proposed RF circuit model for single-wall carbon nanotube with DC electrical contacts at both ends. (b) Simpliﬁed equivalent circuit. (From [43]. # 2002 by IEEE.)

Fig. 6.4.6a and its simpliﬁed equivalent circuit is shown in Fig. 6.4.6b. In this model, Lk is the kinetic inductance per unit length (approximately 10 nH/mm), CQ is the quantum capacitance per unit length, and CES is the electrostatic capacitance per unit length. Other high-frequency applications of CNTs are in the active mode of operation such as in nanotube transistors. While detailed theoretical models for the highfrequency properties of CNT transistors are not available at present, the device performance can be estimated using the following equation for cut-off frequency [44]: fT ¼

gm 2pCgs

where gm is the transconductance and Cgs is the gate–source capacitance. Predictions of the maximum frequency at which current gain can be achieved can be done assuming values of 20 mS for the transconductance. The predictions for fT versus gate length for a nanotube transistor are shown in Fig. 6.4.7. This ﬁgure indicates that nanotubes will surpass existing semiconductor devices and achieve cutoff frequencies in the terahertz range.

NANOTECHNOLOGY CIRCUIT INTERCONNECTIONS: POTENTIAL TECHNOLOGIES

399

FIGURE 6.4.7 Speculative prediction of fT versus gate length for CNT transistor compared to other semiconductor device technologies. (Derived from [44].)

6.4.3

Quantum-Cell-Based Wireless Interconnections

A digital signal can be propagated down a series of quantum cells by using what may be called ‘‘quantum wires.’’ These are wireless interconnections; that is, there is no actual contact between the cells. As shown in Fig. 6.4.8, the coulomb repulsion forces the adjacent cells to align in the same ‘‘1’’ or ‘‘0’’ orientation for the lowenergy state, that is, the ground state [45–49]. Hence, one can achieve wireless logic for propagation of signals. Based on this principle, quantum wires designed as a straight interconnection, to achieve a 90 bend and to obtain a fanout of 2 are shown in Fig. 6.4.9. In addition, quantum wires can be designed to carry crossover signals in the same plane. This kind of wireless connection eliminates the usual electromigration problems associated with metallic interconnections in conventional ICs. This also results in chip area saving and a much higher packing density. Quantum-cell-based interconnections form a part of a quantum cellular automata (QCA), which refers to an array of quantum cells that is fabricated at the nanometer scale and can be used to implement binary logic. These quantum cells can be arranged in principle to get all levels of circuit complexities from the basic logic gates such as inverters and adders to a complete nanocomputer. Though the current QCA-based circuit designs are limited to a single plane, it is possible that bilevel, trilevel, or even higher level circuits and interconnections will be used in future QCA designs.

FIGURE 6.4.8 cells.

Ground state resulting from coulomb interaction between two quantum

400

FUTURE INTERCONNECTIONS

FIGURE 6.4.9 Layouts of quantum cells used to (a) design straight wireless interconnection, (b) achieve a 90 bend, and (c) obtain a fanout of 2.

EXERCISES E6.1 List the problems that need to be solved before optical interconnections can be used for on-chip and chip-to-chip communications. E6.2 List the problems that need to be solved before superconducting interconnections can be used for on-chip and chip-to-chip communications. E6.3 Equation (6.2.29) can be used to determine the magnitude of Vin only and not its phase. Comment on the relative signiﬁcance of the phase of Vin . E6.4 Based on the discussion in Section 6.2, show that VðzÞ and IðzÞ can be expressed as the weighted averages of the transverse electric and magnetic ﬁelds over the cross section of the waveguide. In particular, prove that Z0 1 2 r r Et o eEt VðzÞ ¼ dx dy Eðx; y; zÞ jog m Z Z 1 1 2 r Ht o mHt IðzÞ ¼ dx dy Hðx; y; zÞ r jogZ0 e Z

Z

E6.5 Prove that Eqs. (6.2.73)–(6.2.76) for R, L, G, and C result in the same values of the ratios in Eqs. (6.2.14) and (6.2.15). E6.6 List the problems that need to be solved before nanotube, nanowire, multipath, and quantum-cell-based wireless interconnections can become a reality for nanotechnology circuits.

REFERENCES 1. R. W. Keyes, ‘‘Fundamental Limits in Digital Information Processing,’’ Proc. IEEE, vol. 69, no. 2, Feb. 1981. 2. J. Fried and S. Sriram, ‘‘Optical Interconnect for Wafer-Scale Silicon Systems,’’ Proc. 1984 V-MIC Conf., pp. 159–166, 1984.

REFERENCES

401

3. Y. Omachi, Y. Shinoda, and T. Nishioka, ‘‘GaAs LEDs Fabricated on SiO2-Coated Si Wafers,’’ IEDM Tech. Dig., pp. 315–318, 1983. 4. J. T. Boyd and D. A. Ramey, ‘‘Optical Channel Waveguide Arrays Coupled to Integrated Charge-Coupled Devices and Their Applications,’’ SPIE Guided Wave Opt. Syst. Devices, vol. 176, pp. 141–147, 1979. 5. S. Sriram, ‘‘Fiber-Coupled Multichannel Waveguide Arrays with an Integrated Distributed Feedback Dye Laser Source,’’ Ph.D. Dissertation, University of Cincinnati, Cincinnati, OH, 1980. 6. J. W. Goodman, ‘‘Optical Interconnection in Electronics,’’ Paper presented at the SPIE Technical Symposium, Los Angeles, CA, Jan. 1984. 7. K. C. Saraswat and F. Mohammadi, ‘‘Effect of Scaling of Interconnections on the Time Delay of VLSI Circuits,’’ IEEE Trans. Electron Devices, vol. ED-29, pp. 645–650, 1982. 8. A. Hussain, ‘‘Optical Interconnect of Digital Integrated Circuits and Systems,’’ SPIE Opt. Interf. Dig. Circuits Syst., vol. 466, pp. 10–20, 1984. 9. C. E. Weitzel and J. M. Fray, ‘‘A Comparison of GaAs and Si Processing Technology,’’ Semiconductor International, pp. 73–89, June 1982. 10. J. R. Brews, ‘‘Transmission Line Models for Lossy Waveguide Interconnections in VLSI,’’ IEEE Trans. Electron Devices, vol. ED-33, no. 9, pp. 1356–1365, Sept. 1986. 11. O. K. Kwon and R. F. W. Pease, ‘‘Closely-Packed Microstrip Lines as Very High-Speed Chip-to-Chip Interconnects,’’ Proc. IEEE Int. Electron. Manufacturing Technol. Symp., pp. 34–39, Sept. 1986. 12. R. W. Keyes, E. P. Harris, and K. L. Konnerth, ‘‘The Role of Low Temperature in the Operation of Logic Circuitry,’’ Proc. IEEE, vol. 58, no. 12, pp. 1914–1932, 1970. 13. R. L. Kautz, ‘‘Miniaturization of Normal-State and Superconducting Striplines,’’ J. Res. Natl. Bureau Stand., vol. 84, no. 3, pp. 247–259, 1979. 14. M. K. Wu et al., ‘‘Superconductivity at 93 K in a New Mixed-Phase Y-Ba-Cu-O Compound System at Ambient Pressure,’’ Phys. Rev. Lett., vol. 58, no. 9, pp. 908–910, 1987. 15. J. Z. Sun et al., ‘‘Superconductivity and Magnetism in the High-Tc Superconductor Y-BaCu-O,’’ Phys. Rev. Lett., vol. 58, no. 15, pp. 1574–1576, 1987. 16. R. J. Cava et al., ‘‘Bulk Superconductivity at 91 K in Single Phase Oxygen-Deﬁcient Perovskite Ba2YCu3O9d,’’ Phys. Rev. Lett., vol. 58, no. 16, pp. 1676–1679, 1987. 17. O. K. Kwon, B. W. Langley, R. F. W. Pease, and M. R. Beasely, ‘‘Superconductors as Very High-Speed System Level Interconnects,’’ IEEE Electron Devices Lett., vol. EDL-8, no. 12, pp. 582–585, Dec. 1987. 18. P. London, Superﬂuids, Vol. 1, New York: Wiley, 1950. 19. M. Tinkham, Superconductivity, New York: Gordon and Breach, 1965. 20. A. K. Goel, High Speed VLSI Interconnections, New York: Wiley Interscience, 1994. 21. R. P. Feynman, ‘‘There’s Plenty of Room at the Bottom,’’ paper presented at the annual meeting of the American Physical Society at the California Institute of Technology, December 29, 1959. Available: www.zyvex.com/nanotech/feynman.html. 22. Los Alamos National Laboratory, ‘‘What is Nanotechnology.’’ Available: www.lanl.gov/ mst/nano/deﬁnition.html. 23. IBM Research, ‘‘Nanotechnology.’’ Available: www.research.ibm.com/pics/nanotech/ deﬁned.shtml#timeline.

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24. M. Bohr, ‘‘Intel’s 90 nm Technology: Moore’s Law and More,’’ paper presented at the Intel Developer Forum, 2002. 25. Mitre Corp., The Nanoelectronics and Nanocomputing Home Page, www.mitre.org/tech/ nanotech. 26. M. Ratner and D. Ratner, Nanotechnology—A Gentle Introduction to the Next Big Idea, Prentice-Hall Professional Technical Reference, Prentice-Hall, 2003. 27. M. Motemerlo, J. Love, G. Opiteck, D. Goldhaber-Gordon, and J. Ellenbogen, ‘‘Technologies and Designs for Electronic Nanocomputers,’’ Mitre Corp., 1996. 28. E. J. Hellner, ‘‘Nanowire, 2001. Available: www.rit.edu/ photo/IFS/index-pages/IFS20.html. 29. Y. I. Ismail, E. G. Friedman, and J. L. Neves, ‘‘Exploiting On-Chip Inductance in High Speed Clock Distribution Networks,’’ IEEE Trans. Very Large Scale Integr. Syst., vol. 9, no. 6, pp. 963–973, Dec. 2001. 30. N. D. Arora, ‘‘Challenges of Modeling VLSI Interconnects in the DSM Era,’’ Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems, NanoTech 2002, pp. 645–648, Apr. 22–25, 2002. 31. A. K. Goel, ‘‘Nanotechnology Circuit Design: The Interconnect Problem,’’ Proc. IEEE NANO-2001, Maui, Hawaii, pp. 123–127, Oct. 27–30, 2001. 32. A. K. Goel and N. R. Eady, ‘‘Characterization of Multipath Interconnects for Microelectronic and Nanotechnology Circuits,’’ Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems, Nanotech 2002, pp. 632–635, 2002. 33. R. Baughman, A. Zakhidov, and W. DeHeer, ‘‘Carbon Nanotubes—The Route towards Applications,’’Science, vol. 29, no. 7, Aug. 2002. 34. IBM Research, ‘‘Nanotube Manipulation.’’ Available: www.research.ibm.com/nanoscience/ manipulation.html. 35. ‘‘Reliability and Current Carrying Capacity of Carbon Nanotubes,’’ Appl. Phys. Lett., vol. 79, no. 8, Aug. 2001. 36. P. Singer, ‘‘Carbon Nanotube Interconnects—Untangling the Noodles,’’ Semiconductor International, Sept. 2001. Available: www.reed-electronics.com/semiconductor/article/ CA319168? industryid¼30287. 37. P. Avouris, J. Appenzeller, R. Martel, and S. Wind, ‘‘Carbon Nanotube Electronics,’’ Proc. IEEE, vol. 91, no. 11, pp. 1772–1784, Nov. 2003. 38. S. Wind, J. Appenzeller, R. Martel, M. Radosavljevic, S. Heinze, and P. Avouris, Carbon Nanotube Devices for Future Nano Electronics, IEEE, 2003. 39. W. Hoenlin, F. Kreupl, G. Duesberg, A. Graham, M. Liebau, R. Seidel, and E. Unger, ‘‘Carbon Nanotube Applications in Microelectronics,’’ IEEE Trans. Components Packing Technol., vol. 27, no. 4, Dec. 2004. 40. J. Appenzeller, J. Knoch, R. Martel, V. Derycke, S. Wind, and P. Avouris, ‘‘Carbon Nanotube Electronics,’’ IEEE Trans. Nanotechnol., vol. 1, no. 4, pp.184–189, Dec. 2002. 41. M. Nihei, M. Horibe, A. Kawabata, and Y. Awano, ‘‘Carbon Nanotube Vias for Future LSI Interconnects,’’ Proc. IEEE 2004 International Interconnect Technology Conference, pp. 251–253, June 7–9 2004. 42. A. Naeemi, R. Sarvari, and J. Meindl, ‘‘Performance Comparison between Carbon Nanotube and Copper Interconnects for Giga Scale Integration,’’ IEEE Electron Devices Lett., vol. 26, no. 2, Feb. 2005.

REFERENCES

403

43. P. Burke, ‘‘Luttinger Liquid Theory as a Model of the Gigahertz Electrical Properties of Carbon Nanotubes,’’ IEEE Trans. Nanotechnol., vol. 1, no. 3, pp. 129–144, Sept. 2002. 44. P. Burke, ‘‘Carbon Nanotube Devices for GHz to THz Applications,’’ Proc. International Semiconductor Device Research Symposium, 2003. 45. C. Lent and P. Tougaw, ‘‘A Device Architecture for Computing with Quantum Dots,’’ Proc. IEEE, vol. 85, p. 541, 1997. 46. C. Lent, P. Tougaw, W. Porod, and G. Bernstein, ‘‘Quantum Cellular Automata,’’ Nanotechnology, vol. 4, p. 49, 1993. 47. C. Lent and P. Tougaw, ‘‘Lines of Interacting Quantum Cell Dots: A Binary Wire,’’ J. Appl. Phys., vol. 74, p. 6227, 1993. 48. J. Lusth, ‘‘Symmetric versus Asymmetric Charge Neutralization in Quantum-Dot Cellular Automata,’’ Nanotechnology Proceedings, 2001. 49. G. To´th and C. Lent, ‘‘Quasi-Adiabatic Switching for Metal-Island Quantum-Dot Cellular Automata,’’ J. Appl. Phys., vol. 85, no. 5, pp. 2977–2984, 1999.

Index Activation energy, 318, 322 Active interconnection(s), 230 driven by cascaded repeaters, 234 driven by minimum size repeaters, 231 driven by optimum size repeaters, 232 propagation delays in, 232, 235 Arrhenius plot, 326 Attenuation, 38 Bend, 345 CAD tools, 356 Capacitance(s), 46, 50 approximate formulas for, 57, 109 matrix, 263 parametric dependence of, 77, 99 Carbon nanotubes, 397 Characteristic impedance, 36, 39, 209 Compact expression(s), 216, 292 Copper interconnection(s), 5, 47, 119, 395 advantages, 6 challenges, 6 damascene processing, 9 electromigration, 341 fabrication, 7 resistance modeling, 119 Crossing interconnections, 168, 195, 280 Crosstalk, 242 compact expression(s), 292

dependence on interconnection parameters, 248, 260, 268, 284 reduction of, 251 Current crowding, 315 Current density, 318, 320 Delays, 136, 226, 230 compact expression(s), 216 dependence on interconnection parameters, 150, 158, 178, 214 Delay time, 41 Electromigration, 2, 49, 313 due to repetitive pulsed currents, 331 due to thermal effects, 320 effect of activation energy, 322 effect of current density, 320 effect of line length, 321 effect of line width, 321 in copper interconnections, 341 guidelines for testing, 325 mechanism, 316 problems caused by, 314 reduction of by alloying, 327 by substrate overcoating, 327 under AC conditions, 323 under direct currents, 337 under pulsed DC conditions, 323, 340 Encapsulation, 327

High-Speed VLSI Interconnections, Second Edition By Ashok K. Goel Copyright # 2007 John Wiley & Sons, Inc.

405

406

INDEX

Even-mode capacitances, 17, 73 for three coupled conductors, 19 for two coupled conductors, 17 FastHenry, 114 Fourier integral method, 84 Fourier transformation, 157 Frequency domain modal analysis, 253 GaAs, 2, 109, 302 GaAs-on-Si, 2 Galerkin method, 16 Gold interconnections, 328 Green’s function, 60, 84 matrix, 67 method, 60, 84 Ground bus, 347, 356 High-frequency effect(s), 203, 213 conductor loss, 205 dielectric loss, 206 effective dielectric constant, 204 model of, 203 skin-effect, 205 Hillocks, 2 Inductance(s), 52 matrix, 263 parametric dependence of, 104 simpliﬁed formulas for, 109 Inductance extraction, 55, 114 Interconnection(s), 2 active, 230 between logic gates, 141 copper, 5, 47 crossing, 168, 195 metallic, 391 MIS model of, 138 multilayer, 2 multilevel, 2, 84, 154 multipath, 2, 4, 30 nanotechnology, 390 nanotube, 392 nanowire, 391 optical, 5, 371 semi-inﬁnite, 140, 219 single-level, 145 superconducting, 5 wireless, 399

Interconnection component(s), 344 bend, 345 ground bus, 347, 356 multipath(section) interconnection, 347, 355 overﬂow, 346, 355 plug, 345, 353 power bus, 347, 356 reduction into straight segments, 344 step, 345, 353 straight segment, 351 via, 347, 354 Inverse Laplace transformation, 25, 157 Joule heat, 315 Ladder network, 27 Lognormal distribution, 326 of failure times, 326 standard deviation, 348 Lumped-capacitance approximation, 243 Median-time-to-failure (MTF), 318, 348 effect of current density, 352 effect of line length, 351 effect of line width, 351 effect of temperature, 352 of interconnection components, 34 Metal loss, 40 Method of images, 10, 60, 67 Method of moments, 15 Miller’s theorem, 23 MIS model, 243 Multiconductor bus(es), 302 Multilayer interconnections, 2 Multilevel interconnections, 2, 84, 154, 264 Multipath interconnection(s), 2, 4, 30, 347 Nanotechnology interconnects, 390 Nanotube interconnection, 392, 397 comparison with copper interconnection, 395 Nanotube via, 394 Nanowire, 391 Nernst–Einstein equation, 317 Network analog method, 91 Noise measurement, 324

INDEX

Odd-mode capacitances, 17, 73 Optical waveguide, 375 Optical interconnection(s), 5, 371 advantages, 372 design issues, 374 material issues, 374 system issues, 373 Pade’ approximation, 25 Power bus, 347, 356 Propagation constant, 23, 36 Propagation delays, 41. See also Delays in active interconnections, 235 dependence on driving mechanism, 235 in multilayer IC, 226 Propagation mode(s), 31 quasi-TEM, 32 skin-effect, 32 slow-wave, 32 Propagation time, 41, 235 Quantum cell, 399 Quasi TEM mode, 32 RC models, 217, 294 Reliability, 328 Arrhenius model of, 329 Mil-Hbdk-217D model of, 329

407

series model of, 330 series-parallel model of, 330 RELIANT, 357 RF circuit model, 398 Repeaters, see Inverters Resistance(s), 46, 47 Resistance measurement, 323 Resistivity, 4, 228 Resistivity-frequency mode chart, 32 Rise time, 41 RLC models, 219, 221, 223, 224, 296, 299 Schwarz–Christoffel conformal mapping, 50, 139 Semiconductor loss, 40 Skin-effect, 48, 198 mode, 32, 34 Slow-wave mode, 32, 34 SPIDER, 358 Superconducting interconnections, 5, 386 Thermal effects, 320 Transmission line analysis, 154, 264 Transmission line theory, 21 Via, 347, 354, 394 Voids, 49

WILEY SERIES IN MICROWAVE AND OPTICAL ENGINEERING KAI CHANG, Editor Texas A&M University FIBER-OPTIC COMMUNICATION SYSTEMS, Third Edition 앫 Govind P. Agrawal ASYMMETRIC PASSIVE COMPONENTS IN MICROWAVE INTEGRATED CIRCUITS 앫 Hee-Ran Ahn COHERENT OPTICAL COMMUNICATIONS SYSTEMS 앫 Silvello Betti, Giancarlo De Marchis, and Eugenio Iannone PHASED ARRAY ANTENNAS: FLOQUET ANALYSIS, SYNTHESIS, BFNs, AND ACTIVE ARRAY SYSTEMS 앫 Arun K. Bhattacharyya HIGH-FREQUENCY ELECTROMAGNETIC TECHNIQUES: RECENT ADVANCES AND APPLICATIONS 앫 Asoke K. Bhattacharyya RADIO PROPAGATION AND ADAPTIVE ANTENNAS FOR WIRELESS COMMUNICATION LINKS: TERRESTRIAL, ATMOSPHERIC, AND IONOSPHERIC 앫 Nathan Blaunstein and Christos G. Christodoulou COMPUTATIONAL METHODS FOR ELECTROMAGNETICS AND MICROWAVES 앫 Richard C. Booton, Jr. MICROWAVE RING CIRCUITS AND ANTENNAS 앫 Kai Chang MICROWAVE SOLID-STATE CIRCUITS AND APPLICATIONS 앫 Kai Chang RF AND MICROWAVE WIRELESS SYSTEMS 앫 Kai Chang RF AND MICROWAVE CIRCUIT AND COMPONENT DESIGN FOR WIRELESS SYSTEMS 앫 Kai Chang, Inder Bahl, and Vijay Nair MICROWAVE RING CIRCUITS AND RELATED STRUCTURES, Second Edition 앫 Kai Chang and Lung-Hwa Hsieh MULTIRESOLUTION TIME DOMAIN SCHEME FOR ELECTROMAGNETIC ENGINEERING 앫 Yinchao Chen, Qunsheng Cao, and Raj Mittra DIODE LASERS AND PHOTONIC INTEGRATED CIRCUITS 앫 Larry Coldren and Scott Corzine RADIO FREQUENCY CIRCUIT DESIGN 앫 W. Alan Davis and Krishna Agarwal MULTICONDUCTOR TRANSMISSION-LINE STRUCTURES: MODAL ANALYSIS TECHNIQUES 앫 J. A. Brandão Faria PHASED ARRAY-BASED SYSTEMS AND APPLICATIONS 앫 Nick Fourikis FUNDAMENTALS OF MICROWAVE TRANSMISSION LINES 앫 Jon C. Freeman OPTICAL SEMICONDUCTOR DEVICES 앫 Mitsuo Fukuda MICROSTRIP CIRCUITS 앫 Fred Gardiol HIGH-SPEED VLSI INTERCONNECTIONS, Second Edition 앫 Ashok K. Goel FUNDAMENTALS OF WAVELETS: THEORY, ALGORITHMS, AND APPLICATIONS 앫 Jaideva C. Goswami and Andrew K. Chan HIGH-FREQUENCY ANALOG INTEGRATED CIRCUIT DESIGN 앫 Ravender Goyal (ed.) ANALYSIS AND DESIGN OF INTEGRATED CIRCUIT ANTENNA MODULES 앫 K. C. Gupta and Peter S. Hall PHASED ARRAY ANTENNAS 앫 R. C. Hansen MICROSTRIP FILTERS FOR RF/MICROWAVE APPLICATIONS 앫 Jia-Sheng Hong and M. J. Lancaster

MICROWAVE APPROACH TO HIGHLY IRREGULAR FIBER OPTICS 앫 Huang Hung-Chia NONLINEAR OPTICAL COMMUNICATION NETWORKS 앫 Eugenio Iannone, Francesco Matera, Antonio Mecozzi, and Marina Settembre FINITE ELEMENT SOFTWARE FOR MICROWAVE ENGINEERING 앫 Tatsuo Itoh, Giuseppe Pelosi, and Peter P. Silvester (eds.) INFRARED TECHNOLOGY: APPLICATIONS TO ELECTROOPTICS, PHOTONIC DEVICES, AND SENSORS 앫 A. R. Jha SUPERCONDUCTOR TECHNOLOGY: APPLICATIONS TO MICROWAVE, ELECTRO-OPTICS, ELECTRICAL MACHINES, AND PROPULSION SYSTEMS 앫 A. R. Jha OPTICAL COMPUTING: AN INTRODUCTION 앫 M. A. Karim and A. S. S. Awwal INTRODUCTION TO ELECTROMAGNETIC AND MICROWAVE ENGINEERING 앫 Paul R. Karmel, Gabriel D. Colef, and Raymond L. Camisa MILLIMETER WAVE OPTICAL DIELECTRIC INTEGRATED GUIDES AND CIRCUITS 앫 Shiban K. Koul MICROWAVE DEVICES, CIRCUITS AND THEIR INTERACTION 앫 Charles A. Lee and G. Conrad Dalman ADVANCES IN MICROSTRIP AND PRINTED ANTENNAS 앫 Kai-Fong Lee and Wei Chen (eds.) SPHEROIDAL WAVE FUNCTIONS IN ELECTROMAGNETIC THEORY 앫 Le-Wei Li, Xiao-Kang Kang, and Mook-Seng Leong ARITHMETIC AND LOGIC IN COMPUTER SYSTEMS 앫 Mi Lu OPTICAL FILTER DESIGN AND ANALYSIS: A SIGNAL PROCESSING APPROACH 앫 Christi K. Madsen and Jian H. Zhao THEORY AND PRACTICE OF INFRARED TECHNOLOGY FOR NONDESTRUCTIVE TESTING 앫 Xavier P. V. Maldague OPTOELECTRONIC PACKAGING 앫 A. R. Mickelson, N. R. Basavanhally, and Y. C. Lee (eds.) OPTICAL CHARACTER RECOGNITION 앫 Shunji Mori, Hirobumi Nishida, and Hiromitsu Yamada ANTENNAS FOR RADAR AND COMMUNICATIONS: A POLARIMETRIC APPROACH 앫 Harold Mott INTEGRATED ACTIVE ANTENNAS AND SPATIAL POWER COMBINING 앫 Julio A. Navarro and Kai Chang ANALYSIS METHODS FOR RF, MICROWAVE, AND MILLIMETER-WAVE PLANAR TRANSMISSION LINE STRUCTURES 앫 Cam Nguyen FREQUENCY CONTROL OF SEMICONDUCTOR LASERS 앫 Motoichi Ohtsu (ed.) WAVELETS IN ELECTROMAGNETICS AND DEVICE MODELING 앫 George W. Pan SOLAR CELLS AND THEIR APPLICATIONS 앫 Larry D. Partain (ed.) ANALYSIS OF MULTICONDUCTOR TRANSMISSION LINES 앫 Clayton R. Paul INTRODUCTION TO ELECTROMAGNETIC COMPATIBILITY, Second Edition 앫 Clayton R. Paul ADAPTIVE OPTICS FOR VISION SCIENCE: PRINCIPLES, PRACTICES, DESIGN AND APPLICATIONS 앫 Jason Porter, Hope Queener, Julianna Lin, Karen Thorn, and Abdul Awwal (eds.) ELECTROMAGNETIC OPTIMIZATION BY GENETIC ALGORITHMS 앫 Yahya Rahmat-Samii and Eric Michielssen (eds.) INTRODUCTION TO HIGH-SPEED ELECTRONICS AND OPTOELECTRONICS 앫 Leonard M. Riaziat NEW FRONTIERS IN MEDICAL DEVICE TECHNOLOGY 앫 Arye Rosen and Harel Rosen (eds.) ELECTROMAGNETIC PROPAGATION IN MULTI-MODE RANDOM MEDIA 앫 Harrison E. Rowe ELECTROMAGNETIC PROPAGATION IN ONE-DIMENSIONAL RANDOM MEDIA 앫 Harrison E. Rowe

HISTORY OF WIRELESS 앫 Tapan K. Sarkar, Robert J. Mailloux, Arthur A. Oliner, Magdalena Salazar-Palma, and Dipak L. Sengupta SMART ANTENNAS 앫 Tapan K. Sarkar, Michael C. Wicks, Magdalena Salazar-Palma, and Robert J. Bonneau NONLINEAR OPTICS 앫 E. G. Sauter APPLIED ELECTROMAGNETICS AND ELECTROMAGNETIC COMPATIBILITY 앫 Dipak L. Sengupta and Valdis V. Liepa COPLANAR WAVEGUIDE CIRCUITS, COMPONENTS, AND SYSTEMS 앫 Rainee N. Simons ELECTROMAGNETIC FIELDS IN UNCONVENTIONAL MATERIALS AND STRUCTURES 앫 Onkar N. Singh and Akhlesh Lakhtakia (eds.) ELECTRON BEAMS AND MICROWAVE VACUUM ELECTRONICS 앫 Shulim E. Tsimring FUNDAMENTALS OF GLOBAL POSITIONING SYSTEM RECEIVERS: A SOFTWARE APPROACH, Second Edition 앫 James Bao-yen Tsui RF/MICROWAVE INTERACTION WITH BIOLOGICAL TISSUES 앫 André Vander Vorst, Arye Rosen, and Youji Kotsuka InP-BASED MATERIALS AND DEVICES: PHYSICS AND TECHNOLOGY 앫 Osamu Wada and Hideki Hasegawa (eds.) COMPACT AND BROADBAND MICROSTRIP ANTENNAS 앫 Kin-Lu Wong DESIGN OF NONPLANAR MICROSTRIP ANTENNAS AND TRANSMISSION LINES 앫 Kin-Lu Wong PLANAR ANTENNAS FOR WIRELESS COMMUNICATIONS 앫 Kin-Lu Wong FREQUENCY SELECTIVE SURFACE AND GRID ARRAY 앫 T. K. Wu (ed.) ACTIVE AND QUASI-OPTICAL ARRAYS FOR SOLID-STATE POWER COMBINING 앫 Robert A. York and Zoya B. Popovic´ (eds.) OPTICAL SIGNAL PROCESSING, COMPUTING AND NEURAL NETWORKS 앫 Francis T. S. Yu and Suganda Jutamulia SiGe, GaAs, AND InP HETEROJUNCTION BIPOLAR TRANSISTORS 앫 Jiann Yuan ELECTRODYNAMICS OF SOLIDS AND MICROWAVE SUPERCONDUCTIVITY 앫 Shu-Ang Zhou