Instabilities in Silicon Devices : New Insulators Devices and Radiation Effects

INSTABILITIES IN SILICON DEVICES New Insulators, Devices and Radiation Effects

INSTABILITIES IN SILICON DEVICES New Insulators, Devices and Radiation Effects

This Page Intentionally Left Blank

INSTABILITIES IN SILICON DEVICES New Insulators, Devices and Radiation Effects

Edited by

Gerard BARBOTTIN Aerospatiale Les Mureaux France and

Andre VAPAILLE Universite de Paris 11 Faculte des Sciences d'Orsay Orsay France

VOLUME 3

m 1999

ELSEVIER AMSTERDAM - LAUSANNE - NEW YORK - OXFORD - SHANNON - SINGAPORE - TOKYO

ELSEVIER SCIENCE B.V. Sara Burgerhartstraat 25 P.O. Box 211, 1000 AE Amsterdam, The Netherlands © 1999 Elsevier Science B.V. All rights reserved. This work and the individual contributions contained in it are protected under copyright by Elsevier Science B.V., and the following terms and conditions apply to its use: Photocopying Single photocopies of single chapters may be made for personal use as allowed by national copyright laws. Permission of the publisher and payment of a fee is required for all other photocopying, including multiple or systematic copying, copying for advertising or promotional purposes, resale, and all forms of document delivery. Special rates are available for educational institutions that wish to make photocopies for non-profit educational classroom use. Permissions may be sought directly from Elsevier Science Rights & Permissions Department, PO Box 800, Oxford OX5 IDX, UK; phone: (+44) 1865 843830, fax: (+44) 1865 853333, e-mail: [email protected]. Yott may also contact Rights & Permissions directly through Elsevier's home page (http://www.elsevier.nl), selecting first 'Customer Support', then 'General Information', then 'Permissions Query Form'. In the USA, users may clear permissions and make payments through the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, USA; phone: (978) 7508400, fax: (978) 7504744, and in the UK through the Copyright Licensing Agency Rapid Clearance Service (CLARCS), 90 Tottenham Court Road, London WIP OLP, UK; phone: (+44) 171 436 5931; fax: (+44) 171 436 3986. Other countries may have a local reprographic rights agency for payments. Derivative Works Subscribers may reproduce tables of contents for internal circulation within their institutions. Permission of the publisher is required for resale or distribution of such material outside the institution. Permission of the publisher is required for all other derivative works, including compilations and translations. Electronic Storage or Usage Permission of the publisher is required to store or use electronically any material contained in this work, including any chapter or part of a chapter. Contact the publisher at the address indicated. Except as outlined above, no part of this work may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without prior written permission of the publisher. Address permissions requests to: Elsevier Science Rights & Permissions Department, at the mail, fax and e-mail addresses noted above. Notice No responsibility is assumed by the Publisher for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions or ideas contained in the material herein. Because of rapid advances in the medical sciences, in particular, independent verification of diagnoses and drug dosages should be made.

First edition 1999 Library of Congress Cataloging in Publication Data A catalog record from the Library of Congress has been applied for. ISBN: 0 444 81801 4

@The paper used in this publication meets the requirements of ANSI/NISO Z39.48-1992 (Permanence of Paper). Printed in The Netherlands.

"There are more things on heaven and earth, Horatio, than are dreamt of in your philosophy ". Shakespeare, Hamlet [1, 5]

VI

AEROSPATIALE ESPACE Gi D E F E N S E

This project was made possible thanks, in part, to the Defense and Space division of the Aerospatiale Cie, France.

vn

THE EDITORS

Gerard BARBOTTIN was bom in Orleans (France) in 1946. He obtained his "Ingenieur" degree from the Institut National des Sciences Appliquees of Lyons (Fr.) in 1969, and was awarded an MS degree from the Materials Science department of Northwestern University (111. USA) in 1973 for his work on composition-modulated thin films. He worked for Texas Instruments from 1974 to 1979 (first as a process engineer in the assembly of integrated circuits, then as a failure analysis and reliability specialist). He worked for IBM France from 1979 to 1989 (first as a failure analysis specialist, then as a process engineer for an advanced CMOS process). During his time with IBM he coordinated the writing of Volumes 1 and 2 of this series, and co-edited their content. He joined the Aerospatiale Cie in 1989. He has since that date carried out specific studies related to the use of electronic components in space launchers and strategic missiles. He currently heads a team in charge of drafting "components and technology policies" for military and space programs. He was named "Senior Expert" with Aerospatiale in 1998. He recently co-chaired the program committee of the RADECS 97 international conference on the effects of radiation on components and systems and edited the proceedings of that conference.

Andre VAPAILLE was bom in St-Leu-La-Foret (France) in 1933 and graduated from the Universite de Paris (Fr.) in 1955. He first carried out research work with Fr. Grivet in the Electronics department of the Universite de Paris from 1958 to 1966. He was awarded the degree of "Docteur d'Etat" from the Universite d'Orsay (Fr.) in 1966 for his work on the deep levels in the silicon band gap introduced by irradiation and impurities. From 1966 to 1972 he pursued research work with R. Castagne on the interface states of the Si-Si02 structure and on impurity-related deep levels in silicon. From 1972 to 1982 his research work focused on the metal-semiconductor structure (using Si and 3-5 compounds). Since 1982 he has been working on the epitaxial growth of Si in high vacuum (MBE and CBE). He teaches at the Institut Universitaire de Technologic of the Universite d'Orsay since 1972 and has been head of the Departement de Mesures Physiques of that institute from 1980 to 1986. Besides the co-editing of the three volumes of this series, he has also authored two other books entitled: "Electronique du silicium homogene" (Masson, 1970) and "Dispositifs et circuits semiconducteurs" (Dunod, 1989), the latter with R. Castagne.

This Page Intentionally Left Blank

IX

FOREWORD By the year 2000, sales of semiconductor integrated circuits will reach approximately 150 billion dollars. The most critical technology supporting this industry is control of the SiSi02 interface. Silicon dioxide is used to passivate all of the critical silicon semiconductor regions which form the heart of the devices. It is also universally used in all of the integrated circuits to form insulating layers and the gate insulator in most MOS devices. The use of silicon dioxide as a passivation layer, gate oxide or insulating layer provides a very stable surface with very low surface recombination velocity. No other semiconductors have been able to match silicon because it has not been possible to achieve a surface passivation layer on them which can compete with the silicon dioxide layer over silicon with respect to stability and low surface recombination velocity. Silicon dioxide possesses other unique capabilities including the ease with which it can be photolithographically patterned and its ability to serve as a barrier against unwanted diffusion. This book addresses the instabilities present when silicon dioxide is used to passivate silicon. Even though a properly prepared Si-Si02 interface is very stable, it is essential to understand the instabilities that inevitably remain and to understand the technology used to reduce them to their present very acceptable state. Many integrated circuits are used in satellite systems where they are subject to high energy radiation from the Van Allen belts, from cosmic radiation and from solar flares. They are also used in military equipment where they must withstand specified levels of high energy radiation from nuclear weapons. High energy radiation can severely degrade the electrical properties of the Si-Si02 interface. A properly manufactured SiSi02 interface can be designed to minimize the adverse effects of high energy radiation, and this technology is thoroughly discussed The most serious radiation problem is the permanent degradation produced by ionizing dose in the Si02 and at the Si-Si02 interface. In hardened devices, failure can occur at ionizing dose levels as low as 500 Rads (Si). However, using special device hardening manufacturing processes, threshold failure levels can easily be increased to a minimum of 10^ Rads (Si), and with more attention to special processes, failure level thresholds can be increased to 10^ Rads (Si). The ionizing dose rate ejfects in Si and Si02 have been explained by defining the hole electron pair generation constants and relating the carriers so generated to the transient current which result in the silicon devices. Permanent damage from neutron and proton irradiation have been well characterized by determining the crystalline defects in terms of their density and energy levels and relating them to changes in current gain in bipolar devices and to leakage currents in MOS devices.

X

Foreword

The production of logic upset and, in rare cases, device failure caused by cosmic rays is also reasonably well understood in terms of the charge collected from the ionization at critical device nodes and its consequent effects on currents and voltage in semiconductor devices. Progress in stabilizing the Si'Si02 interface has resulted from two major efforts. It was necessary to process Si and Si02 through very clean steps; free from chemical impurities, especially electrically active impurities. The alkali ions, especially sodium, had to be eliminated from the silicon dioxide. Other ions such as hydrogen and ammonia had to be reduced. The addition of phosphorus glass was found to be helpful in some cases. It was also necessary to reduce the defect density in the silicon dioxide that resulted from thermal stresses. This was particularly important to minimize the degradation that results from high energy radiation. So special manufacturing processes were developed which reduced the temperatures used in the high temperature oxidation and diffusion processes. Understanding of the Si-Si02 interface is in no way complete at this time. The effort to improve the stability of the oxide continues as does the research and development to minimize the effects of high energy radiation. This work goes on in parallel with the continuing effort to reduce the feature size of the individual devices within the integrated circuits. Feature size is now approaching the incredibly small length of 0.1 micron and may even go lower. High energy radiation seems to activate electrically neutral defects in the oxide and at the interface providing damaging shifts in the threshold voltage ofMOS transistors and increases in the surface recombination velocity that degrades the gain of bipolar transistors. The postulated nature of these defects is discussed thoroughly in this book, but what is lacking is a way to quantitatively measure them. Unfortunately, it still remains true at this time that there is no measurement or combination of measurements, electrical, chemical or physical, which can define a device's susceptibility to damage by high energy radiation. It is therefore necessary to evaluate the radiation hardness of an integrated circuit manufacturing process by sample testing the devices thus fabricated in an actual high energy radiation environment and then, by statistical extrapolation, defining the radiation hardness of the rest of the lot. It remains a primary goal of the ongoing research and development activities to discover a test method capable of predicting an integrated circuit's radiation tolerance by direct measurements. This book is the result of cooperation between a group of experts from several countries and is an up-to-date summary of the instabilities present in the Si-Si02 interface which forms the surface of nearly all commercially important integrated circuits. It is a comprehensive summary of the process technologies used to stabilize the interface both for terrestrial and space applications.

George C. MESSENGER

Foreword

xi

George MESSENGER was bom in Bellows Falls, Ver. (USA) in 1930. He obtained a B. S. degree in physics from Worcester Polytechnic University (USA) in 1951, an M. S. degree in electrical engineering from the University of Pensylvania (USA) in 1957, and a Ph. D degree in engineering from California Coast University (USA) in 1986. He has worked as a research scientist for numerous companies (Philco Corp., Hughes Semicond., Transitron Corp., Northrop Corp., etc.) and has made many significant contributions to the fields of radiation effects and nuclear engineering. He, in particular, developed a simplified "neutron energy-versus-displacement" curve which allowed the development of the 1 MeV equivalent standard. He also discovered the Kirk effect in bipolar transistors and co-discovered the Messenger-Spratt equation for damage in bipolar semiconductor devices. During the course of his long carreer, he has contributed numerous articles to technical journals, was granted several patents and has received many awards for his contributions in the fields of radiation effects and device and system hardening. He has co-authored two books entitled: "The Effects of Radiation on Electronic Systems" (Von Nostrand, 1992) and "Single Event Phenomena" (Chapman & Hall, 1997). He has been an IEEE fellow since 1976.

This Page Intentionally Left Blank

Xlll

INTRODUCTION TO VOLUME 3 An ambitious European effort This book is the third of three volumes devoted to silicon passivation and to passivationrelated instability phenomena affecting modem silicon devices. This study, which should be of great interest to circuit manufacturers and circuit users alike, is the result of an ambitious European effort which began in 1981. Twenty five specialists have collaborated on this project, all of them engineers of the semiconductor industry, university professors or research scientists working in fields related to microelectronics. Electrical instabilities, an ever-present problem A device is said to be unstable when its electrical characteristics are modified in a (fully or partially) reversible manner once a stress is applied. The stress may be thermal, electrical or due to radiation. Unlike hard (irreversible) defects, which are usually due to physical modifications of the materials, soft (reversible) defects are due to "charges" moving about in the insulating layers or at the insulator/silicon interface (A more complete definition of instability phenomena can be found in Chap. 14 of Vol. 2). Far from disappearing with progress in process control and materials characterization, the problem of instabilities remains very acute because of three current trends in microelectronics. • Greater device integration subjects insulating layers and gate oxides to ever-increasing thermal and electrical stresses. • Silicon devices are more frequently used in hostile environments (military, nuclear, space). • "Agressive" new fabrication processes (e.g. ion implantation, electrolithography, plasmas, etc.) substitute for traditional ones and introduce new sources of instabilities. There is thus a need for a complete, didactic and up-to-date manual, aimed at specialists and students in the field. This 2200-page study, published in three volumes, should answer this need. Contents of Volume 1 (published in 1986) Part I of Vol. 1 deals with the physics of silicon passivation from the point of view of material science. We describe the various theories which attempt to explain how silica grows on silicon during thermal oxidation. We look at the imperfections of vitreous silica and at the impurities it contains. We also describe some often overlooked side-effects of silicon passivation, namely those taking place in the silicon substrate itself. In part n we look at the electrical properties and characteristics of the MIS structure, in general terms. We oppose ideal and actual MOS structures and show how any deviation from ideality affects the C(V) curve. We examine the complex nature of electronic conduction in thin insulators and see how and why the application of large electric fields leads to oxide breakdown. We finally render the reader familiar with the concept of electrical noise and with its applications to surface noise.

xiv

Introduction to Volume 3

In Part HI, we review the electrical phenomena occurring in the bulk of silicon oxide (Part in is made up of three chapters: Chaps. 8 and 9 belong to Vol. 1 whereas Chap. 10 belongs to Vol. 2). We re-examine the perennial problem associated with mobile ions, which, in spite of process improvements, remains a potential threat to bipolar and MOS processes alike. We then look at the many aspects of hot carrier injection into silicon dioxide, whether this injection is intentional, for study purposes, or takes place while the device operates. Contents of Volume 2 (published in 1989) Part in ends with Chap. 10 in which we describe at length two phenomena associated with carrier injection, namely carrier trapping and detrapping, and in which we review the many electrical techniques used to characterize carrier traps in silica. In Part IV we take a look at the electrical phenomena taking place at the Si-Si02 interface. We show that imperfections give rise to so-called "intrinsic" surface states, whereas the presence of impurities in the interfacial zone generates "extrinsic" surface states. We examine their properties, their impact on electrical characteristics and the models currently proposed to explain their origin. We review in detail the techniques used to measure them and how these can be used for diagnosis purposes. Practical examples of passivation-related instabilities in silicon devices are reviewed in Part V. Since the basic physics of instabilities has been given in the earlier parts, these chapters should give the engineer quick ways of solving practical instability problems encountered in bipolar as well as in MOS devices. The peculiarities of structures possessing a double insulating layer are also examined and their application to MNOS non-volatile memory cells detailed. We end Vol. 2 by surveying in Part VI the effects of radiation on the Si-Si02 structure and how these effects impact the normal functioning of silicon devices. We show that, once again, most effects occur because of the presence of passivation layers and that only in the particular case of large doses and energetic particles do the upper layers of the silicon substrate play a part in instability phenomena. Contents of Volume 3 (to be published in 1998) Volume 3, the present book, comprises two parts. Part I is made up of seven chapters. Each chapter is either an update of a chapter found in Vols. 1 or 2, or an extension of it. These additions proved necessary due to the fast evolution of new fabrication processes, to the emergence of new insulating materials (such as silicon nitrides, silicon oxynitrides and buried oxides) and to the advent of multilayer dielectrics. The race to decrease the feature size of highly integrated circuits has made it necessary to better understand conduction and breakdown in thin silica films as well as injection phenomena in submicrometer devices. It has also furthered the implementation of new and powerful physical and electrical characterization techniques, of which two are thoroughly described: charge pumping and isotopic tracing.

Introduction to Volume 3 Part n contains four chapters and is entirely devoted to instabilities occurring in radiation environments, with special emphasis on space applications. The (natural) radiation environment encountered in space, around the earth is described and the basic terms and definitions used in the field of radiation-matter interactions are introduced. To understand why and how radiation affects the functioning of semiconductor devices, we review the main radiation-matter interactions and their underlying physics. We show how the electrical characteristics of irradiated devices get degraded either by ionization phenomena or by displacement damage or by both. Finally, two effects, most frequently encountered in space, are thoroughly described: the ionizing dose effect and single event phenomena. Scope of this project and intended audience In this study, we look at instability phenomena from the dual point of view of material science and electronics and we examine how these phenomena affect the functioning of practical devices. These three volumes should thus help circuit manufacturers and circuit users to relate unstable parameters and characteristics to the physical defects and impurities which caused them. The topics treated in these volumes are easily accessible provided the reader is familiar with the basics of physics and electronics. It should prove useful to: • Engineers and technicians working in the semiconductor industry in such fields as: circuit design, manufacturing engineering, material and process characterization, quality and reliability assurance, failure analysis, and hardening assurance. • Graduate students and research scientists in material science, electrical engineering and nuclear engineering, interested in insulator physics, semiconductor physics, device physics, radiation-device interactions and electronics. • Application engineers working in the military, nuclear and space industries. How to use this book The entire study is divided into 30 chapters. Although the chapters follow each other in a logical order, they can be read independently. Each one contains an abstract in English, French and German, a table of contents, a list of symbols, units and abbreviations used and a list of references. An Author Index and a Subject Index can be found at the end of each volume and easily refer the reader to the relevant chapter, section or paragraph. Since a great deal of effort has been devoted to unifying not only symbols, units and abbreviations but also styles and approaches, reading should be easier than in usual multi-author books. However, English being the mother tongue of none of the contributors, we ask the reader to show leniency for style and granmiatical errors which might have escaped our editing.

xv

xvi

Introduction to Volume 3

Acknowledgements We would like to thank the 15 authors who have contributed a text to Vol. 3 and who have shown great patience both with our demanding editing rules and with the delayed publication of their work. We are grateful to Dr. George MESSENGER, a pioneer in the field of radiation effects in silicon devices, who volunteered to read all chapters and contributed many useful comments an suggestions. We are glad he agreed to write a foreword to this volume. Special thanks go to the typing pool of the AEROSPATIALE plant in Les Mureaux (France) and to the typists of ART VIDEO in Poissy (France) who handled the typing (or retyping) of the 950 pages of this volume. Finally, we would like to thank the Defense and Space Division of the AEROSPATIALE Cie (France) who gave us logistical support and financial help and who trusted us throughout this six-year-long project.

The editors

CONTENTS OF VOLUME 3 Introduction to Volume 3 List of contributors

xiii xix

PART I - Updates and additions to Volumes 1 and 2 Chapter 1 : Silica, silicon nitride and oxynitride thin films - An overview of fabrication techniques, properties and appKcations 3 by B. Balland and A. Glachant Chapter 2 : A review of buried oxide structures and SOI technologies 145 by J.L. Leray Chapter 3 : Dielectric breakdown in siUca - A survey of test methods 233 by D.R, Walters, J,F. Verwey and T.A. Zegers - Van Duijnhoven Chapter 4 : Hot carrier injections in siUca and related instabilities in submicrometer MOS transistors 265 byD, Vuillaume Chapter 5 : Multilayer dielectrics for memory appUcations 341 by P, Gentil Chapter 6 : Charge pumping techniques - Their use for diagnosis and interface state 405 studies in MOS transistors by J,L. Autran, B. Balland and G, Barbottin Chapter 7 : The study of thermal nitridation and reoxidation mechanisms using isotopic tracing methods 495 by J J. Ganem andLJ,R. Baumvol

PART II - Silicon devices in radiation environments Chapter 8 : The space radiation environment by D. Brdunig Chapter 9 : An overview of radiation-matter interactions by W.R, Fahrner Chapter 10 : Radiation effects in electronic components by D. Brdunig and F. Wulf Chapter 11 : Defects and radiation-induced charge trapping phenomena in sihca by P. Paillet and J.L. Leray Chapter 12 : The effects of cosmic ions on electronic components by O. Musseau Author index Subject index Errata of Vol.1

525 553 639 723 781

891 917 935

This Page Intentionally Left Blank

XIX

LIST OF CONTRIBUTORS Editors G. BARBOTTIN Service YY/ST AEROSPATIALE Route de Vemeuil 78130 Les Mureaux France

Pr.A.VAPAILLE Institut d'Electronique Batiment 220 Universite de Paris Sud 91405 Orsay Cedex France

Authors and co-authors Dr. J.L. AUTRAN LPM Batiment 502 INSA 20, Avenue A. Einstein 69621 Villeurbanne France

Pr. W. FAHRNER Femuniversitat Gesamthochschule Bauelemente der Elektrotechnik Haldener Strasse 182 D-58084 Hagen 1 AUemagne (Germany)

Pr. B. BALLAND LPM Batiment 502 INSA 20, Avenue A. Einstein 69621 Villeurbanne France

Dr.J.J.GANEM Universite de Paris VI GPS Tour 23/3eme etage. 2, Place Jussieu 75251 Paris France

G. BARBOTTIN Service YY/ST AEROSPATIALE Route de Vemeuil 78130 Les Mureaux France

Pr. A. GLACHANT CRMC2 Campus de Luminy Universite de Marseille Case 913 13288 Marseille Cedex 9 France

Pr. I. BAUMVOL Instituto de fisica UFRGS Avenida Bento Gongalves 9500 Porto Alegre - RS 91540-000-Bresil (Brazil)

Pr. P. GENTIL CIUME 46, Avenue Felix Viallet 38031 Grenoble France

Pr.D.BRAUNIG Department AT Hahn Meitner Institut Glienicker Strasse 100 D-14109 Berlin AUemagne (Germany)

Dr.J.L.LERAY CEA-DAM Service Electronique BP12 91680 Bruyeres-Le-Chatel France

XX

List of Contributors

Authors and co-authors (continued)

Foreword by

Dr. O. MUSSEAU CEA-DAM Service Electronique BP12 91680 Bruyeres-Le-Chatel France

Dr. G. MESSENGER Messenger & Associates 3111 Bel Air Drive 7F Las Vegas NV 89114 USA

Dr.P.PAILLET CEA-DAM Service Electronique BP12 91680 Bruyeres-Le-Chatel France

First Printer

Pr.J.F.VERWEY Phloxlaan 8 5582EGWaalre Pays-Bas (The Netherlands)

Larbi KHORDJ APTEL BP513 77304 Fontainebleau France Second Printer ART VIDEO INTERACTIVE 7, boulevard de la Paix 78300 POISSY France

Dr.D.VUILLAUME ffiMN BP69 Avenue Poincare F-59652 Cedex Villeneuve d'Ascq France

Publisher

Dr.D.WOLTERS Philips Research Lab. WAG 1-1-18 5656 AA Eindhoven Pays has (The Netherlands)

Sponsor

Dr. F. WULF Hahn Meitner Institut Abteilung DS Glienicker Strasse 100 D-14109 Berlin AUemagne (Germany) Dr. ZEGERS Van DUYNHOVEN Philips Research Lab. PC Box 80000 5600 JA Eindhoven Pays-Bas (The Netherlands)

Elsevier Publishing Cie PC Box 1991 1000 BZ Amsterdam Pays-Bas (The Netherlands)

AEROSPATIALE Branche Espace et Defense Centre Operationnel Systemes Route de Vemeuil 78130 LesMureaux France

XXI

THE AUTHORS Jean-Luc AUTRAN was bom in Antibes (France) in 1969. He graduated in Materials Science and Engineering from the Institut National des Sciences Appliquees de Lyon (INSA) in Lyons (Fr.) in 1992. He was awarded a Doctorate Degree in 1994 for his study of interface traps by charge pumping techniques, carried out with IBM-Siemens in CorbeilEssonnes (Fr.). From 1994 to 1996, he worked on technology hardening and radiation effects at the Commissariat a l*Energie Atomique (CEA) in Bruyeres-LeChatel (Fr.). In 1996, he joined the Laboratoire de Physique de la Matiere (LPM, laboratory associated with the Centre National de la Recherche Scientifique) at INS A in Lyons (Fr.). He is currently an Assistant Professor of physics at INSA where his research interests include MOS device physics and characterization, advanced dielectrics and defects and reliability in integrated devices. He has authored or co-authored more than 50 publications, has served as guest editor of the Journal of Non-Crystalline Solids, and co-organized the series of symposia on "Si02 and its defects" in Caen (Fr.) in 1995, Agelonde (Fr.) in 1996 and LAquila (It.) in 1998. He is a member of the IEEE. Bernard BALLAND was bom in Nancy (France) in 1939. He studied physics and chemistry at the Universite de Nancy (Fr.) and was named assistant professor at that same university in 1963. In 1969, he joined the Institut National des Sciences Appliquees de Lyon (Fr.) where he carried out research work in the Materials Science department and taught thin film and device physics. He was awarded the degree of "Docteur d'Etat" from the Universite de Lyon (Fr.) in 1975 for his work on the physical mechanisms responsible for the instabilities of MOS devices, and was named university professor in 1980. He presently heads a research group at the Laboratoire de Physique de la Matifere (LPM, laboratory associated with the Centre National de la Recherche Scientifique) at INSA in Lyons (Fr). His research interests include material and device characterization and processing technologies. His current responsabilities include the development and characterization of new dielectric and semiconductor materials for optoelectronics, VLSI and ULSI microelectronics, and microtechnologies. He is a member of the GCIS (Groupement des Circuits Integres sur Silicium), of the SFP (Societe Fran9aise de Physique), of the European and American branches of the MRS (Materials Research Society) and of the EEA (Electronique, Electrotechnique et Automatique) club of France. He has authored or co-authored over 200 publications or review papers on thin films, device characterization techniques and device reliability. Gerard BARBOTTIN (see Editors).

XXll

The Authors Israel J.R. BAUMVOL was bom in Sao Gabriel (Brazil) in 1947. He graduated from the Federal University of Rio Grande do Sul in Porto Alegre (Br.). He received an M. S. degree from the University of Sao Paulo (Br.) in 1974, and a Ph. D degree from the Federal University of Rio Grande do Sul in Porto Alegre (Br.) in 1977, for his work on the submicroscopic structure and local electric field in ferroelectric materials.

From 1979 to 1981, he worked as a postdoctoral fellow at the Atomic Energy Research Establishment, at Hartwell (England) in the field of ion implantation and radiation-enhanced diffusion. From 1984 to 1986 he spent several periods as Visiting Professor at the IBM-Research laboratory in Yorktown Heights (N.Y., USA), working in such different research projects as: multilayers of metallic thin films, the rapid thermal annealing of defects in Si, and the production of thin films of transition metal silicides. He teaches physics at the Federal University of Rio Grande do Sul in Porto Alegre (Br.) since 1985, and conducts research in the field of very thin dielectric films for present and future large scale integrated silicon devices. From 1993 to 1996 he was also a Visiting Professor at the Universite de Paris Vn (Fr.), working in the Groupe de Physique des Solides, in the research team of Professor Serge Rigo. He is a research fellow of the Brazilian National Research Council (CNPq), a member of the Groupement de Recherche-86 (GDR-86) of the Centre National de la Recherche Scientifique (CNRS)- France, and a member of the Scientific Committee of the Groupement Architecture Physique du Silicium (GDR-GAPS) of the CNRS-France. He is also associate editor for the Brazilian Journal of Physics.

Dietrich BRAUNIG was bom in Berlin (Germany) in 1938. He received the degree of "Diplom-Ingenieur" in electrical engineering in 1968 from the Technical University of Berlin (Ger.). He was awarded the degree of "Doktor Ingenieur" in 1974 from the same university for his work on the nonequilibrium behaviour of MOS structures. In 1993, he was appointed to a professorship in the field of semiconductor devices at the Technical University of Berlin (Ger.). He joined the Hahn-Meitner Institut of Berlin (Ger.) in 1968 and has been, since 1976 head of the department of Irradiation Effects on Semiconductor Devices, (now the department of Technology and Reliability). He spent a sabbatical year at IBM East Fishkill/Yorktown Heights (N.Y., USA) from 1983 to 1984. His activities range from basic research to applied physics in the field of semiconductors and semiconductor devices. He lectures on that subject at the Technical University of Berlin and has done so for several years. He is a member of the IEEE.

The Authors

XXlll

Wolfgang R. FAHRNER was bom in Hohenpeissenberg, Bavaria (Germany), in 1945. He studied physics in Darmstadt (Germany) and Montpellier (France) He graduated from the University of Freiburg (Ger.) in 1970 and was awarded a Ph.D. from that same university in 1972. He studied and pursued research work at the Fraunhofer Institute of Applied Solid State Physics in Freiburg (Ger.) from 1968 to 1977 except for a sabbatical year which he spent, in 1973 and 1974, with IBM East Fishkill (N.Y., USA). From 1977 to 1988 he worked at the Hahn-Meitner Institute in Berlin (Ger.) on basic MOS research, radiation assurance, and high-energy ion implantation. This period was interrupted by a second sabbatical year spent at IBM East Fishkill in 1984 and 1985. In 1988, he was appointed professor at the University of Hagen (Ger.) and now holds a chair of electronic devices in the school of electronic engineering. He has authored or co-authored more than 200 papers and holds several patents on power, MOS, and diamond-based electronic devices. He is a member of the Electrochemical Society and of the German Physical Society.

Jean-Jacques GANEM was bom in Tunis (Tunisia) in 1961. He graduated from the Universite de Paris VII (France) in 1988. He joined the Groupe de Physique des Solides (GPS) laboratory of that same university and was awarded a Doctorate Degree in 1992 for his study of the initial stages of silicon oxidation. For this work, he conceived a setup specially designed for Rapid Thermal Treatments in controlled atmospheres and for isotopic tracing experiments. He extended his research to the growth mechanisms of thin nitrogen-based dielectrics required for future Ultra-Large Scale Integrated devices. He is currently an assistant professor in Applied Physics at the Universite de Paris VI (Fr) and his research interests, at the GPS laboratory, include Nuclear Reaction Analyses for physical characterization and the relations between structural film defects and their electrical properties. He has authored or co-authored more than 30 publications and is currently a member of the Electronique, Electrotechnique et Automatique (EEA) club of France.

xxiv

The Authors

Pierre GENTIL was bom in Rouen (France) in 1945. He obtained the degree of "Ingenieur" from the Ecole Nationale Superieure d'Electronique de Grenoble (ENSERG) (Fr) in 1969. He was awarded the degree of "Docteur d'Etat" from the Universite Scientifique et Medicale de Grenoble (Fr.) in 1979 for his work on interface states in MOS devices, carried out at the Institut National Polytechnique de Grenoble (INFO). He performed his first research work at the Laboratoire d'Electronique, de Technologies et d'Instrumentation (LETT) of Grenoble (Fr.) on MOS and MNOS memories, from 1969 to 1972, and then worked on MOS technology in the CIEA del INF, Mexico D.F. (Mex.) from 1972 to 1974. He joined the Laboratory of semiconductor device physics (LPCS-CNRS) of Grenoble (Fr.) in 1974 where he has worked, since then, on MOS noise, SOI devices, MNOS memories and short-channel MOS transistor degradation. He also headed the Centre Inter-universitaire de Micro-Electronique (CIME) of Grenoble (Fr.) from 1981 to 1994. Besides his current interest for the physics of ultra short channel MOS transistors, he teaches microelectronics at the ENSERG in Grenoble (Fr.) and is responsible for the doctorate in microelectronics at the Grenoble universities. He also acts as an expert for the French Ministry in charge of higher education and research, and for the French Ministry in charge of industry. He is vice-president of a national action committee on microelectronics initial training (CNFM) and is in charge, for France, of a European program on ASIC technology transfer. He is a member of the URSI society. Alain GLACHANT was bom in Conakry (Guinee) in 1946. He first studied physics at the Universite de Provence in Marseille (France), where he was awarded a Doctorate Degree in Crystallography in 1973. In 1974, he joined the Universite d*Aix-Marseille in Luminy (Fr.), where he taught as assistant professor and carried out research work in the Centre de Recherche sur les Mecanismes de la Croissance Cristalline (CRMC2). He was awarded the degree of "Docteur d'Etat- Sciences" from the same university in 1981. He then worked as a postdoctoral fellow at the "Istituto di Scienze Fisiche dell'Universita" of Genoa (Italy) on helium diffraction by rare gas monolayers physisorbed on the basal plane of graphite. In 1983, he became "maitre de conferences" and began to study the physics of silicon nitride growth and that of oxynitride thin films on silicon. Since 1991, he is professor at the Institut universitaire de formation des maitres ae Nice - Centre de Toulon (Fr.). His current research focuses on the low-temperature process-assisted formation of insulating thin films (including electron and photon-enhanced growth or deposition), molecular - scale electronics and the development of new techniques to characterize the surfaces and interfaces of ultrathin films. He was a member of the GCIS (Groupement des Circuits Integres sur Silicium) of the SFV (Societe Frangaise du Vide, Fr.) and is currently a member of the SEP (Societe Fran9aise de Physique, Fr.).

The Authors

XXV

Jean-Luc LERAY was bom in Paris (France) in 1955. He graduated in Physics from the Ecole Centrale de Paris (Fr.) in 1978 and was awarded the degree of "Docteur d'Etat es Sciences Physiques" in 1989 from the Universite d'Orsay (Fr.). Dr. Leray has been with the Commissariat a I'Energie Atomique (CEA) in Bruyeres-Le-Chatel (France) since 1978, where he has worked mostly on radiation effects, technology developments, and hardening. Since 1985, he has been heading a "radiation-hardening" group in charge of developing hardened electronic components for military, space, and high-energy physics environments. He was named Senior Expert with the CEA in 1998. Dr. Leray has authored or co-authored over 120 technical publications, and has written an additional 100 technical articles. He has held numerous teaching and lecturing assignments. He is a senior member of the SEE (Societe des Electriciens et des Electroniciens, Paris, Fr.) and received in 1994 the General Ferrie award for "important contributions to the progress of electronics and its applications". Olivier MUSSEAU was bom in Nantes (France) in 1962. He graduated from the Ecole Superieure d'EIectricite in 1985. In 1986, he joined the Commissariat a I'Energie Atomique (CEA) in the Centre d'Etudes de Bruyeres-Le-Chatel (Fr.), and carried out research work on radiation effects on microelectronic devices. He was awarded the degree of "Docteur en Sciences" from the Universite de Paris XI (Fr.) for his work on heavy ion effects in integrated devices. His current research activities include the study of the physical mechanisms which explain the interaction of radiation with insulating and semiconducting materials, and the development of hardened microelectronic technologies. He has authored or co-authored over 30 publications in this field and has lectured on that topic during the short courses of the RADECS conferences of 1991 and 1995. In 1995, he received the General Ferrie award from the SEE (Societe des Electriciens et des Electroniciens, Paris, Fr.) for "important contributions to the progress of electronics and its applications". Philippe PAILLET was bom in Digne (France) in 1966. He obtained his M.S. degree from the Universite de Aix-Marseille (Fr.) in 1989 and was awarded a doctorate degree from the Universite de Montpellier II (Fr.) for his work on radiation-induced ionization effects in insulators used in microelectronic technologies. He currently works for the Commissariat a FEnergie Atomique in Bruyeres-Le-Chatel (Fr.) where he is in charge of radiation studies on new classes of dielectrics. His research interests include the study of physical mechanisms involved in charge-trapping phenomena and the modeling of these effects in MOS devices. He has authored or co-authored over 30 publications and has co-organized the series of symposia on "Si02 and its defects" in Caen (1995), Agelonde (1996) and L'Aquila (1998).

XXVI

The Authors

Dominique VUILLAUME was bom in Paris (France) in 1956. He received the "Ingenieur en electronique" degree in 1981 from the Institut Superieur d*Electronique du Nord (ISEN, Lille, Fr.) and a doctorate degree in Solid State Physics in 1984 from the Universite de Lille (Fr.). His PhD thesis dealt with the DLTS characterization of electrically active defects in MIS devices. Since 1982, he has been with the Solid State Physics research group at the Laboratoire d'Etude des Surfaces et Interfaces (LESI), laboratory associated with the Centre National de la Recherche Scientifique (CNRS) at ISEN. In 1988, he joined the CNRS as "charge de recherche" (research scientist). From 1988 to 1990, he served as scientific advisor at the "Direction des technologies avancees" (Advanced technologies division) of the BULL R&D laboratory (Les Clayes sous Bois, Fr.). In 1991, he joined the newly created Institut d'Electronique et de Microelectronique du Nord (lEMN) in Lille (Fr.) (this institute is associated with the CNRS, the Universite de Lille, the Universite de Valenciennes and ISEN). His research interests include the physics and the characterization of point defects in semiconductors and MIS devices, the physics and the reliability of thin insulating films on semiconductors, and hotcarrier effects in MOSFETs. He presently works in the field of "molecular electronics", on the physical and electrical properties of self-assembled organic monomolecular films, organic materials, and molecular devices. He is the author or co-author of more than 60 technical papers. Dr. Vuillaume is a member of the French Physical Society, the Material Research Society, the IEEE Electron Device Society and the International Society of Molecular Electronics and Biocomputing.

Jan F. VERWEY was bom in Benschop (The Netheriands). He studied solid state chemistry at the University of Utrecht (The Netherlands) where he obtained a PhD in 1967 for his work on photochemical processes in lead halides. From 1967 to 1990 he was with PHILIPS ELECTRONICS (Hoi.) in several functions, firstly in research where he carried out investigations on hot carrier injection into Si02 and on other reliability-related properties of silicon oxide. Lastly, he was heading a department working on the reliability of integrated circuits. Dr. Verwey was extraordinary professor in applied physics at the University of Groningen (Hoi.) from 1976 to 1985, and had a similar position in electronic engineering at Twente University (Hoi.) from 1990 to 1995. He has authored or coauthored more than 80 technical papers.

The Authors

xxvii

Donald K. WOLTERS was bom in Eindhoven (The Netherlands) in 1939 and graduated from the University of Eindhoven (The Netherlands). He joined the technical staff of Philips Research Laboratories (Hoi.) in 1963. His research interests focus on topics as different as: fuel cells, semi-permeable membranes, magnetic tapes, silicon oxidation and the incorporation of water in alkali glasses. Since 1979, he has been particularly active in the field of conduction and breakdown phenomena in thin dielectric films and was awarded a PhD from the University of Eindhoven (Hoi.) in 1985 for his work on breakdown in Si02. He co-edited, in 1983, the book entitled "Insulating films on Semiconductors", published by North Holland. From 1989 to 1993, he developed and published a new purely electrochemical theory on the oxidation of silicon. This theory gives answers to the peculiar 2-D growth at silicon comers, boxes and trenches. Since 1993, he has been working on 1/f noise. He showed that 1/f noise is a phenomenon which can be easily understood by accounting for power dissipation and its effect on electronic transport.

Friedrich WULF, was bom in Leek (Germany) in 1946. He received the degree of "Diplom Ingenieur (FH)" in micro-electronics in 1972 from the Technische Fachhochschule Berlin (Ger.) and the "Diplom Ingenieur (TU)" degree in high frequency engineering from the Technische Universitat Berlin (Ger.) in 1975. He was awarded the degree of "Doktor Ingenieur" from that same university in 1989 for his work entitled" Einheitliches Modell zur Beschreibung der Generations- und Ausheilprozesse von Oxidlagungen Q^^ und Grenzflachenzustanden Dj^ im Siliziumdioxid durch stress". He joined the Hahn-Meitner-Institut Berlin GmbH in 1975. Until 1978, he ' developed electronic equipment for the control system of the heavy ion accelerator VICKSI. Since then, he has been working in the group of semiconductor devices and radiation tests. He spent one year (1990/91) as an adviser at the Inter-university Microelectronics Center (IMEC, Bel.) on the radiation hardening of MOS devices, especially CDD's. He was in the organization team of the European Committee for the Future Accelerators (EFCA) 1990 and in the program committee of RADECS 1993. His activities include basic research on irradiation effects in semiconductor devices, device simulation, hydrogen profiling in thin Si02 layers, and irradiation qualification tests of semiconductor devices for space applications. He heads the Department of experimental systems at the Hahn-Meitner-Institut in Berlin (Ger.), since January 1994.

This Page Intentionally Left Blank

PARTI UPDATES AND ADDITIONS TO VOLUMES 1 AND 2

FOREWORD Part I of this volume contains seven chapters. Each of these chapters is either an update of a chapter found in Vols. 1 and 2 or an extension of it. In Chap. 1, we give an overview of the fabrication techniques, properties and applications of the newest thin dielectric films used in semiconductor devices, namely: silica, silicon nitride and silicon oxynitride. Whereas in the previous volumes, we were mostly interested in the physics of thermal oxidation (Chap. 1 of Vol. 1), we now describe in detail the (thermal or assisted) nitridation of silicon and of silica, and also mention some deposition techniques. In Chap. 2, we review the techniques currently used to fabricate buried oxides. Devices based on buried oxide (BOX) structures possess such advantages as: an increased integration, a reduction in coupling effects, a better radiation hardness and low leakage currents. This gives BOX technologies a promising future, not only in microelectronics but also in buried optics and micromachines. Dielectric breakdown, studied in previous volumes (Chap. 6 of Vol. 1) is reassessed in Chap. 3 by means of the "charge to breakdown" model. The basic principles of hot carrier injection had been given in Chap. 9 of Vol. 1 and its consequences on short-channel devices examined in Chap. 15 of Vol. 2. In Chap. 4 of this volume, we examine in detail the consequences of channel hot electron injection and drain avalanche hot carrier injection in submicrometer devices and we show how these phenomena can be modeled. The physics and the possible applications of two-layer insulators had been explained in Chap. 6 of Vol. 2. In Chap. 5 of this volume, we describe recent improvements brought to MNOS structures for memory applications and show the advantages of introducing a third insulating layer in the structure. In Chap. 6, we detail the two-level and three-level charge pumping (CP) techniques and their many variants (CP techniques had been briefly described in Chap. 12 of Vol. 2). As dimensions of elementary devices keep shrinking, we show why these techniques are virtually unchallenged to study the channel area in small-size transistors. We show in Chap. 7 how the growth of films (oxides, nitrides, oxynitrides) in wellcontrolled ambients (altematively natural and isotopically-enriched) combined with highresolution profiling techniques, enable us to describe, on an atomic scale, the transport and exchange mechanisms taking place during thermal nitridation and reoxidation. (The use of isotopic tracing techniques, to study the physics of thermal oxidation, had been only briefly mentioned in Chap. 1 of Vol. 1). These seven chapters should allow engineers and researchers alike, to understand the latest developments in the physics and characterization of thin dielectric films and how these developments affect current highly integrated devices.

INSTABILITIES IN SILICON DEVICES Silicon Passivation and Related Instabilities G. Barbottin and A. Vapaille (Editors) © 1999 Elsevier Science B.V. All rights reserved.

CHAPTER 1

SILICA, SILICON NITRIDE AND OXYNITRIDE THIN FILMS An overview of fabrication techniques, properties and applications by B. BALLAND (D and A. GLACHANT (2)

Key items Thin dielectric films Thermal oxidation of silicon Thermal nitridation of silicon Self-limited growth of silicon nitride Thermal nitridation of silica Physical properties of oxynitride films Electrical properties of oxynitride films The role of hydrogen Rapid Thermal Processes (RTP) ReOxidized Nitrided Oxide (RONO) films Nitridation in N2O Nitridation in NO Assisted deposition techniques Assisted growth techniques Applications of oxynitride films

(I) Laboratoire de Physique de la Matiere (CNRS-UMR5511) Institut National des Sciences Appliquees de Lyon 20, avenue Albert Einstein 69621 Villeurbanne - France E-mail: bbaland@insa. insa-lyon.fr

(2) Centre de Recherche sur les Mecanismes de la Croissance Cristalline (CNRS - LP 7251) Campus de Luminy - Case 913 12288 Marseille Cedex 09 - France E-mail: glachant@crmc2. univ.mrs.fr

B. Balland and A, Glachant Abstract of Chapter 1 - Silica, silicon nitride and oxynitride thin films - An overview of fabrication techniques, properties and applications. Although thermal oxide remains an insulator of choice for silicon-based microelectronic devices, thin nitride and oxynitride films possess superior qualities for specific applications. In this chapter we describe both the main techniques used to manufacture thin nitrided insulator films and the main physical and electrical properties of the obtained films. The direct nitridation of silicon in ammonia, by thern^al means, is difficult because it requires high temperatures (> 950°C) and the obtained films are very thin (<10 nm) because of the self limiting nature of the growth process. Since the network of amorphous silicon nitride is denser than that of silica, it resists chemical etching (by HF solutions) better and behaves as a better barrier against diffusion. These properties are exploited in the LOCOS process. Unlike the oxide defects, the defects contained in nitrides behave mostly as electron traps. Thin oxynitride films can be fabricated by nitriding thin silica films in ammonia at high temperature (> SOO^C). Nitridation may be performed at low pressure (P(NHs) < 1 mbar) or at "high" pressure (P(NHs) ^ 1 bar). In either case, the ensuing nitrogen concentration below the surface and at the Si02'Si interface is greater than in the bulk. The introduction of nitrogen atoms in silica, their concentration and their distribution modify in a complex fashion the physical and electrical properties of this material. The presence of nitrogen increases the dielectric strength of silica but increases the density of electron traps and introduces a hole conduction mode. It is also possible to fabricate thin oxide or nitride films, or to nitride thin silica films by using Rapid high Temperature Processes (based on the lamp heating of single wafers). The short process times used allow one to fabricate films whose properties are superior to those grown in furnace processes. To minimize the problems associated with the presence of hydrogen atoms introduced in nitrides during processing in ammonia, one can reoxidize these nitrided films. It is also possible to obtain virtually hydrogenfree nitride films by processing silicon surfaces directly in gaseous N2O or NO. The films thus obtained possess electrical properties which are superior to those of usual nitride films, and especially a greater dielectric strength and a better resistance to electrical stresses. It is also possible to fabricate nitride and oxynitride films at lower temperatures (and even at room temperature) by enhancing the reactivity of the species involved, by non-thermal means. These processes, briefly reviewed, use photons, electrons, ions or plasmas as an enhancement method, which allows one to reduce considerably the "thermal budget". Thin nitride and oxynitride films have found numerous applications in microelectronic devices. Resume du chapitre 1 - Les films minces de silice, de nitrure et d*oxynitrure de silicium - Une revue de leurs procedes de fabrication, de leurs proprietes et de leurs applications. Bien que I 'oxyde thermique reste un isolant de choix pour les composants micro-electroniques sur silicium, les nitrures et les oxynitrures minces se montrent superieurs pour certaines applications. Nous decrivons dans ce chapitre les principales techniques utilisees pour fabriquer des isolants nitrures minces ainsi que les principales proprietes physiques et electriques des films obtenus. La nitruration directe du silicium dans I 'ammoniac par voie thermique est difficile car elle necessite de hautes temperatures (> 950 °C) et les films obtenus sont tres minces (< JO nm) du fait que la croissance est auto-limitee. Compte tenu de la compacite de leur reseau, les films de nitrure resistent mieux que les films d'oxyde a la gravure chimique par I 'acide fiuorhydrique, et constituent une barriere a la diffusion, plus efficace. Ces proprietes sont exploitees dans le procede LOCOS. Sur le plan electrique et contrairement aux oxydes, les defauts presents dans les nitrures se comportent principalement comme des pieges a electrons. Des films minces d'oxynitrure peuvent etre obtenus en nitrurant des films minces d'oxyde thermique, dans de I 'ammoniac a haute temperature (> 800 °Q. La nitruration peut s 'effectuer a basse pression (P(NHs) < 1 mbar) ou a haute pression (P(NHs) ^ I bar). Dans tous les cas, la concentration d'azote sous la surface et a I'interface Si02-Si est plus grande que dans le volume. L 'introduction d 'azote dans la silice, sa concentration et sa distribution modifient de maniere complexe les proprietes physiques et electriques de ce materiau. La presence d'azote accroit la rigidite dielectrique. Elle accroit egalement la densite de pieges a electron et introduit un mode de conduction par trous.

Silica, Silicon Nitride and Oxynitride Thin Films II est egalement possible de faire croitre des films minces d'oxyde ou de nitrure ou de nitrurer des fdms d'oxyde en utilisant des precedes rapides a haute temperature (par chauffage unitaire des tranches, par lampe). Les faibles temps de traitement permettent d'obtenir des fdms qui ont des proprietes electriques superieures a celles des films fabriques dans des fours classiques. Pour minimiser les problemes associes a la presence de I 'hydrogene introduit dans les oxydes nitrures par les traitements thermiques dans Vammoniac, on peut reoxyder ces films. On peut egalement obtenir des films d'oxynitrure sans aucun hydrogene en traitant directement le silicium dans N2O ou NO. Les films ainsi obtenus presentent des proprietes electriques superieures a celles des oxydes ou des nitrures classiques; en particulier, ils presentent une meilleure rigidite dielectrique et une tres bonne resistance aux contraintes electriques. II est egalement possible de fabriquer des nitrures classiques et des oxynitrures a plus basse temperature (voire a temperature ambiante) en activant les especes reagissantes par des procedes non thermiques. Ces procedes, passes brievement en revue, utilisent des photons, des electrons, des ions ou des plasmas comme methode deactivation, ce quipermet de reduire considerablement le "budget thermique". Les films minces de nitrure et d'oxynitrure de silicium ont trouve de nombreuses applications dans les composants microelectroniques. Zusammenfassung zu Kapitel 1 - Siliziumoxyd,-nitrid and-oxinitrid Diinnschichten - Ein Uberblick iiber ihre Herstellungsprozesse, ihre Eigenschaften und Anwendungen, Obwohl thermisches Oxyd hervorragende Isolatoren fUr die mikroelektronischen Siliziumbauelemente abgibt, werden Nitride und Oxinitride fUr bestimmte Anwendungen bevorzugt. In diesem Kapitel werden die wichtigsten Herstellungstechniken von isolierenden Nitriddtinnschichten und deren physikalischen und elektrischen Eigenschaften erldutert. Die direkte, thermische Nitridation von Silizium in Ammoniak erweist sich als schwierig, da sie hoher Temperaturen (>950^C) bedarf und die Filmschichten sind diinn ( 800°C) von thermischem Oxyd in Ammoniak hergestellt werden. Die Nitridation kann entweder bei niedrigem (P(NH^ < Imbar) oder hohem Druck (P(NHs) ^ Ibar) erfolgen. In beiden Fallen ist die Stickstofflconzentration hoher unter derfidche und an der Si02'Si Grenzfidche als im Volumen. Das Einbringen von Stickstoff in Siliziumoxyd, seine Konzentration und seine Verteilung dndern die Materialeigenschaften in komplizierter Weise. Das Vorhandensein von Stickstoff verstdrkt die dielektrische Eigenschaften, aber auch die Dichte der Elektronenfallen undfuhrt zu einer Loch-Leitung. Man kann auch durch schnelle Hochtemperaturprozesse (basierend auf dem Aufheitzen durch Lampen von einzelnen Wafern) Oxid- oder Nitridschichten herzustellen oder Oxydschichten zu nitridieren. Durch die kurze Prozefidauer, sind diese Schichten in ihren elektrischen Eigenshaften den in klassischen Ofen erzeugten Schichten Uberlegen. Um die Probleme, die mit dem Vorhandensein von Wasserstoff in nitridierten Oxyden verbunden sind, zu minimieren, kann man die Schichten erneut oxidieren. Oxinitridschichten ohne jeglichen Wasserstoff konnen auch durch unmittelbares Behandeln von Silizium mit N2O oder NO erhalten werden. Die dadurch erzeugten Schichten zeigen bessere elektrische Eigenschaften als klassische Oxyde oder Nitride, insbesondere stdrkere dielektrische Eigenschaften und einen besseren Widerstand zu elektrischen Randbedingungen. Es ist auch moglich Nitride und Oxinitride bei niedrigen Temperaturen (sogar bei Raumtemperatur) herzustellen, indem man die Reaktionspartner durch nicht-thermische Mechanismen aktiviert. Diese Prozesse werden kurz beschrieben; sie verwenden Photonen, Elektronen, lonen oder Plasmen zur Aktivierung, was das thermische "Budget" (thermischen Aufivand) wesentlich reduziert. Siliziumnitrid- und -oxinitriddiinnschichten haben in mikroelektronischen Bauelementen zahlreiche Anwendungen gefunden.

B. Balland and A, Glachant Chapter 1: Silica, silicon nitride and oxynitride thin films - An overview of fabrication techniques, properties and applications. Table of contents List of symbols and abbreviations used 1. Introduction 2. An overview of some thin insulators used in VLSI devices 2.1. Why use thin insulators? 2.2. Some basic requirements 2.2.1. Physical and chemical requirements 2.2.2. Electrical requirements 2.2.3. Application-dependent requirements 2.3. The manufacturing of thin oxide films 2.3.1. The thermal growth of thin oxides 2.3.2. Properties of thin thermal oxides 2.3.3. Limitations of traditional thermal growth for very thin films 2.3.4. Thin oxides obtained by chemical vapor deposition 2.4. The manufacturing of thin silicon nitride films 2.4.1. The advantages of silicon nitride 2.4.2. Direct nitridation 2.4.3. Deposited nitrides 2.5. The use of other dielectric materials 2.5.1. High-permittivity materials 2.5.2. Silicon oxynitrides 3. Thermally-grown silicon nitride thin films 3.1. Low-pressure (LP) thermal nitridation 3.1.1. Principle 3.1.2. Experimental evidence of nitride growth 3.1.3. Some experimental growth curves 3.1.4. Growth modeling 3.1.5. Proposed growth mechanisms 3.1.6. Film structure 3.2. High-pressure (HP) thermal nitridation 3.2.1. Principle of non-assisted thermal HP growth 3.2.2. Principle of plasma-assisted thermal HP growth 3.2.3. The kinetics of HP nitride growth 3.2.4. Growth mechanisms 4. Properties of thin thermal nitride films 4.1. Structure 4.2. Optical refractive index 4.3. Etching characteristics 4.4. Resistance to oxidation 4.4.1. Resistance to dry oxidation 4.4.2. Resistance to wet oxidation 4.4.3. The LOCOS process 4.5. Resistance to irradiation

Silica, Silicon Nitride and Oxynitride Thin Films 4.6. Resistance to impurity diffusion 4.7. The main imperfections of the sihcon nitride-siUcon system 4.7.1. Defects associated with non-stoichiometry 4.7.2. Defects associated with hydrogen 4.7.3. Defects and introduced energy levels 4.7.4. Impact on electrical properties 4.7.5. Defects induced in the silicon substrate 4.8. Electrical properties of nitride films in MNS structures 4.8.1. Dielectric constant 4.8.2. Dielectric charges 4.8.3. Breakdown voltage 4.8.4. Electrical conduction 4.8.5. Characteristics of short-channel MNSFETs 4.9. Conclusion 5. Silicon oxide films thermally nitrided in ammonia 5.1. The nitridation methods 5.2. The high-pressure (HP) nitridation process 5.2.1. A phenomenological description 5.2.2. Main features of the nitridation process 5.2.3 Proposed nitridation mechanisms 5.3. The main physical properties of HP-NO films 5.3.1. Etching characteristics 5.3.2. Resistance to oxidation 5.3.3. Resistance to irradiation 5.3.4. Resistance to impurity diffusion 5.4. The low-pressure (LP) nitridation process 5.4.1. The various LP processes 5.4.2. Composition of LP-NO films 5.4.3. Proposed nitridation mechanisms 5.5. The main physical properties of LP-NO films 5.5.1. Optical refractive index 5.5.2. Etching behavior 5.5.3. Resistance to oxidation 5.5.4. Resistance to irradiation 5.5.5. Resistance to impurity diffusion 5.6. Defects introduced by the nitridation process 5.6.1. Defects induced in the silicon substrate 5.6.2. Defects introduced in the silica film 5.7. The electrical properties of NO films 5.7.1. Dielectric constant. 5.7.2. Flat-band shift 5.7.3. Impact of nitridation on interface states 5.7.4. Impact of nitridation on conduction mechanisms 5.7.5. The trapping and detrapping properties of NO films 5.7.6. Dielectric breakdown in NO films 5.7.7. Enhanced saturation transconductance of p-channel MOSFETs 5.8. Conclusion and application to VLSI circuits

B. Balland and A, Glachant 6. Thermally reoxidized nitrided oxide films 6.1. Processes used 6.2. Film composition 6.2.1. Zones of interest 6.2.2. Nitrogen content 6.2.3. Hydrogen content 6.2.4. Boron diffusion 6.3. The electrical properties of RONO films 6.3.1. Electrical conduction 6.3.2. Interfacial charges 6.4. Instabilities in (RONO) films under stress 6.4.1. Capacitance-voltage curves after stress 6.4.2. Interface state generation under stress 6.4.3. Electron trapping 6.5. Conclusion 7. Thin dielectric films fabricated by rapid thermal processes 7.1. Principle 7.2. Apparatus 7.3. Rapid thermal cleaning 7.4. Rapid thermal oxidation of silicon 7.4.1. Basic process 7.4.2. Thickness uniformity 7.4.3. Growth kinetics 7.5. Compared electrical properties of RT and FG oxide films 7.5.1. Conduction properties 7.5.2. Interface trap density 7.5.3. Dielectric strength 7.5.4. Role of annealings 7.6. Rapid thermal nitridation of thin oxides in ammonia. 7.6.1. Basic process 7.6.2. Composition of RTNO films 7.6.3. Optical refractive index 7.7. Electrical properties of RTNO films 7.7.1. C-V characteristics 7.7.2. Dielectric constant 7.7.3. Fixed charge and interface states 7.7.4. Behavior of RTNO films under electric stress 7.8. Conclusion 8. Thin oxynitride films grown in N2O and NO ambients 8.1. The major processes 8.2. Oxynitridation in N2O 8.2.1. Growth kinetics 8.2.2. Growth mechanisms 8.2.3. Film composition

Silica, Silicon Nitride and Oxynitride Thin Films 8.2.4. Trapping properties 8.2.5. Dielectric breakdown 8.2.6. Reliability 8.3. Tliin oxynitride films grown in NO 8.3.1. Principle and growth kinetics 8.3.2. X-ray assisted growth at room temperature 8.3.3. Electron beam-assisted growth at moderate temperature 8.3.4. Film composition 8.3.5. Electrical properties 8.4. Conclusion 9. A brief review of low-temperature assisted processes 9.1. Photon-enhanced processes 9.1.1. Basic equipment 9.1.2. Photon-enhanced nitride growth 9.1.3. Photon-enhanced nitride deposition 9.1.4. Composition and properties of LT-PE nitride films 9.1.5. Photon-enhanced oxynitridation processes 9.1.6. Composition and properties of LT-PE oxynitride films 9.2. Electron-enhanced processes 9.2.1. Electron-enhanced nitride growth 9.2.2. Electron-enhanced nitridation of silica tilms 9.2.3. Composition and properties of LT-EE oxynitride films 9.3. Ion-enhanced deposition processes 9.3.1. Nitride deposition by RF-sputtering 9.3.2. Composition and properties of deposited nitride films 9.3.3. Oxynitride deposition by RF-sputtering 9.4. Plasma-Enhanced (PE) processes 9.4.1. Principle 9.4.2. Plasma-enhanced nitridation of silicon 9.4.3. Plasma-enhanced nitridation of silica 9.4.4. Plasma-enhanced nitride deposition 9.4.5. Composition and properties of PECVD nitrides 9.4.6. Plasma-enhanced oxynitride deposition 9.4.7. Applications 10. Summary and conclusion Acknowledgements List of References

10

B. Balland and A. Glachant

LIST OF SYMBOLS AND ABBREVIATIONS USED* A Cox Cn(Cp)

Dit

en(ep) E EQX

Ec Ei,bulk EG

f h k Leff NA(ND)

n q

cm2 F.cm-2 m-3.s-^ eV-t.cm-2 s-l

V.cm-i V.cm-i eV eV eV Hz J.s J.K-l cm cm-3 -

C C.cm-2 Qf C.cm-2 Qinj C.cm-2 Qit C.cm-2 Qm C.cm-2 Qot C.cm-2 Qox C.cm-2 QBD s tor s tnit s tBD nm tin, N s tstress T K VpB, A V F B V V Vth V VG V Vox V s,Vs V ^B cm2 On («5p)

Space charge layer (device) area Gate oxide capacitance, expressed per unit area Capture coefficient for electrons (for holes) Density of interface states Emission coefficient for electrons (for holes) Electric field Electric field in the oxide Lower edge of the conduction band (of Si or Si02) Intrinsic Fermi level in the semiconductor bulk Energy band gap Frequency Planck constant (h = 6.62 10-34 J.s = 4.14 10-15 eV.s) Boltzmann constant (k = 1.38 10-23 j.R-l = 8.63 10-5 eV.K-1) Effective channel length Concentration of acceptor (donor) atoms Optical refractive index Absolute value of the electronic charge (q = 1.6 10-1^ C) Density of fixed charge Density of injected charge Density of interface-trapped charge Density of mobile ions Density of oxide-trapped charge Density of oxide charge Charge-to-breakdown, expressed per unit area Time measuring resistance to oxidation Nitridation time Mean time to breakdown Insulator thickness, nitride thickness Stress time Absolute temperature Flat band voltage, flat band voltage shift Threshold voltage Applied gate voltage Voltage drop across the oxide Surface potential in the silicon substrate Barrier height Capture cross section for electrons (for holes)

* Only those symbols which appear more than once in the text have been listed.

Silica, Silicon Nitride and Oxynitride Thin Films 80 ^0X9 ^Si AES APCVD ARXPS at.% a-u CB CMOS C-V CVD DLTS DRAM EAROM EPROM EEPROM FTIR FN FG HF etching HP ... HRTEM HT... IC IR I-V LEED LOCOS LP... LPCVD LT... MIS MNS MOS MOSFET MNSFET NDB NO NO

F.cm-1 F.cm-1

Permittivity of vacuum Permittivity of silica, of silicon Auger Electron Spectroscopy Atmospheric Pressure Chemical Vapor Deposition Angle-Resolved X-Ray Photoelectron Spectroscopy Atomic concentration expressed in % Arbitrary unit Conduction band Complementary MOS device Capacitance-Voltage characteristics (of a MOS structure) Chemical Vapor Deposition Deep Level Transient Spectroscopy Dynamic Random Access Memory Electrically Alterable Read Only Memory Electrically Programmable Read Only Memory. Electrically Erasable Progranmiable Read Only Memory Fourier Transform Infra-Red Spectroscopy Fowler-Nordheim (injection or current) Forming gas (10% H2, 90% N2) Etching using hydrofluoric acid High Pressure (nitridation process) High-Resolution Transmission Electron Microscopy High Temperature (nitridation process) Integrated Circuit Infra-Red Current-Voltage characteristics (of a MOS structure) Low Energy Electron Diffraction Local Oxidation of Silicon Low Pressure (nitridation process) Chemical Vapor Deposition at Low gas Pressure Low Temperature (nitridation process) Metal-Insulator-Semiconductor (structure) Metal-Nitride-Silicon (structure) Metal-Oxide-Semiconductor (structure) MOS Field Effect Transistor MIS Field Effect Transistor using nitride as a gate insulator Nitrogen Dangling Bond (= N*) Nitrided Oxide or nitrided silicon dioxide or NitrOxide Nitric oxide gas molecule

11

12 NRA PE... PECVD PEN QSM RBS REELS RF plasma RONO RS RT... RTA RTP RTN RTO RTON RTONO SDB SHB SMS SSB TDDB IDS TED TEM TZDB UHV ULSI VB VLSI VTGI XPS [N]/([N]+[0]) [ ]

B. Balland and A. Glachant Nuclear Reaction Analysis Photon-Enhanced (process) Plasma-Enhanced Chemical Vapor Deposition Plasma-Enhanced Nitridation Quasi Static Method (or Measurements) Rutherford Backscattering Spectroscopy Reflection Electron Energy Loss Spectroscopy Radio Frequency Plasma Re-Oxidized NitrOxide (film) Raman Spectroscopy Rapid Thermal (process) Rapid Thermal Annealing Rapid Thermal Processing Rapid Thermal Nitridation (RTP of silicon or of Si02 in NH3) Rapid Thermal Oxidation (RTP of silicon in O2) Rapid Thermal OxyNiti-idation (RTP of sihcon in N2O) Rapid Thermal re-Oxidation of (NH3)-Nitrided Oxide Silicon Dangling Bond {= Si») Silicon-Hydrogen Bond (= Si-H) Secondary Ion Mass Spectroscopy Silicon-Silicon bond or group (= Si-Si =) Time-Dependent Dielectric Breakdown at constant field Thermal Desorption Spectroscopy Transmission Electron Diffraction Transmission Electron Microscopy Time-Zero Dielectric Breakdown Ultra-High-Vacuum techniques Ultra Large Scale Integration Valence Band Very Large Scale Integration Very Thin Gate Insulator X-ray Photoelectron Spectroscopy Composition parameter of an oxynitride film Concentration, usually expressed in at.%

Silica, Silicon Nitride and Oxynitride Thin Films

13

1. INTRODUCTION Thin dielectric films play vital roles in modem Integrated Circuit (IC) technologies. They are mostly used in three types of application: as gate insulators, as field insulators, and as tunnel dielectrics. Gate insulators To function properly, field-effect devices manufactured in the MOS technology, such as Field-Effect Transistors (MOSFETs) and Electrically Erasable and Programmable Read Only Memories (EEPROMs), must possess a thin dielectric layer isolating the transistor channel from the gate electrode, as illustrated in Fig. 1.01. Modem Very Large Scale Integrated (VLSI) circuits make an extensive use of short-channel transistors and electrically-erasable non-volatile memories. These two types of device require that the dimensions of the insulator layer be reduced (both vertically and horizontally). Gate insulator thicknesses of less than 15 nm (150 A) are nowadays (1996) routinely required. The defect density of such layers must be extremely small and their quality and reliability, excellent. Field insulators Dielectric layers are also used in ICs to isolate transistors from one another and to isolate connecting lines from other active parts of the circuit as illustrated in Fig. 1.01. The increasing integration of ICs requires that the thickness of these field insulators be reduced, although less so than gate insulators. Word line gate

Tunnel Oxide

Floating Gate N+ doped polyslllcon 1

\^-\^^j^—A:^EJ< Gate Oxide Select transistor

Field Oxide

Control Gate Sense transistor

Fig. 1.01 - Schematic cross section of a dynamic memory structure based on a floating gate and using a very low programming voltage. Typical oxide thicknesses are 30 nm for the regular gate oxide of the Word line transistor, 6 nmfor the tunnel oxide and ~ 400 nmfor the field oxide.

Tunnel oxides Thin tunnel oxides are used in such devices as Dynamic Random Access Memories (DRAMs). The write operation as well as the erase operation are done electrically using electron tunnel emission. A charge, representing an information, is stored on the floating gate. Electrons are injected through the tunnel oxide. Figure 1.01 is a schematic cross section of a DRAM which shows the three types of insulator used in such a device.

14

B, Balland and A, Glachant

Thermal silicon dioxide has been the first insulator used to passivate the silicon surface [1,2] and for a long time has been the only dielectric material usable both for gate and field oxides [3-9]. The physics of its thermal growth has been thoroughly described in Vol. 1 of this book series [10]. Silicon dioxide has remained the dielectric of choice because it has close to ideal properties: its dielectric strength is large and the Si02-Si interface contains very few defects. Thermal oxide does have some drawbacks, however. It is, for example, a poor barrier against atomic diffusion because of its fairly loose network. This explains why silicon nitride, which possesses a tighter network, has been proposed and used as a substitute insulator. However, both the thermal oxidation and the thermal nitridation of silicon require large "thermal budgets". Since the current trend is to reduce these budgets, especially for multi-layer structures, other dielectric materials and other ways of fabricating oxides and nitrides have been developed. This chapter reviews the many ways which now exist to fabricate Very Thin Gate Insulators (VTGI) and the properties required of these films for the current generation of VLSI devices. In Section 2, we give a first overview of the thin insulators used in microelectronics and the reasons behind their use. These films must meet many requirements, which limits the number of available candidates. We recall that thermal oxide remains, in many aspects, the best possible material for thin films but that silicon nitride is preferred in some specific applications. Both silicon oxide and silicon nitride can be either thermally grown or deposited and we quickly review the main features of these fabrication techniques. Oxynitride films combine some advantages of the oxide and nitride films, which explains why they are increasingly used. Both their properties and their fabrication techniques are extensively described in further sections. In Section 3, we review the basic aspects of thermal nitride growth. We show that the growth of a thin thermal nitride layer on top of a silicon surface is only possible at high temperature (T > 950''C) in a pure nitriding gas (N2 or NH3), either at "high" (atmospheric) pressure or at "low" pressure (in an ultra-high-vacuum chamber). Because of the compactness of the nitride network thus formed, the growth process is self-limiting, and the maximum thickness reached never exceeds 10 nm. To grow thicker films, the nitridation gas must be somehow activated (using e.g. a plasma). We indicate some experimentally-found growth laws and we propose a growth model. Some of the chemical reactions and mechanisms thought to be responsible for the nitride formation are also given. The basic physical, chemical and electrical properties of thin thermal silicon nitride films are reviewed in Section 4. We see that the structure (amorphous or polycrystalline) of these films, as well as the optical refractive index, are highly dependent on the fabrication conditions and on the degree of cleanliness (i.e. on the purity of the nitriding gas ambient, and cleanliness of the silicon surface prior to nitridation). We show that thermal nitrides resist chemical etching better than thermal oxides do and also resist dry oxidation well. The latter resistance depends on the fabrication conditions of the nitride film and on its residual nitrogen content once oxidation has started.

Silica, Silicon Nitride and Oxynitride Thin Films

15

The fact that thin nitride films resist oxidation is the basis of the LOCOS process. We also examine the resistance to irradiation and to impurity diffusion of such films. We next review the major electrically active defects encountered in thermal nitrides and the role they play in conduction and trapping mechanisms. We end this section by taking a look at the electrical properties of nitrides, measured by means of MIS structures, namely: dielectric constant, dielectric "charges", dielectric strength and leakage current. Oxynitride films are also widely used in microelectronics. We describe in Section 5 one of the techniques used to produce such films, namely the nitridation of silica in gaseous ammonia (NH3), and we examine the properties of the obtained Nitrided Oxide (NO) films. The basic mechanism behind the nitridation of silica is the substitution of O atoms by N atoms. This exchange is fueled by the diffusion of NHx species ( 0 < x < 3 ) coming from the gaseous ambient through the silica film. The top silica layer gets thoroughly nitrided (even more so using the low-pressure process) but nitrogen piles up also at the Si02-Si interface. Nitrided oxide films possess properties similar to those of nitride films regarding resistance to: dry oxidation, irradiation, and impurity diffusion. They can thus be used to fabricate very stable gate insulators for field-effect transistors. Due to the presence of nitrogen, the electrical properties of NO films differ from those of silica films. Nitridation modifies the flat-band voltage, the fixed oxide charge and the density of interface states in a complex manner which depends on the nitrogen concentration at the Si02-Si interface. Conduction properties are also modified. Nitridation increases the possibilities of electron trapping and can give rise to hole conduction (of the Poole Frenkel type). It also improves the dielectric strength of the film. Oxide films nitrided in NH3 are often reoxidized. We show in Section 6 that this reoxidation yields insulating films whose properties are half-way between those of silica and those of NO films. During reoxidation, the top nitrided layer is quickly reoxidized while a thin oxide layer grows undemeath the interfacial oxynitride layer, and the hydrogen content in the film is much reduced. ReOxidized Nitrided Oxide (RONO) films display less electron trapping than NO films and their main conduction mechanism involves electrons (and not holes). Rapid Thermal Processes (RTP) are promising altematives to furnace processes. They combine lamp heating and reactive processing in a chamber where temperature and gas ambient can be rapidly changed. In Section 7 we examine two particular RT processes, namely: RT Oxidation (RTO) and RT Nitridation (RTN) and we describe some of the properties of the films thus obtained. As measured through I-V and C-V curves, RTO films display electrical characteristics which are better than those of fumace-grown oxide films: higher dielectric strength, lower defect density and lower density of interface states. Oxides nitrided through an RT process possess properties which are similar to those of oxides nitrided in a furnace. However, RT nitridation makes it possible to minimize the duration of the nitridation step and thus permits one to reduce both strain and impurity redistribution at the Si02-Si interface.

16

B, Balland and A. Glachant

One of the drawbacks of nitridation in NH3 is the inevitable formation of hydrogenated species in the film, which leads to high densities of electron traps. We show in Section 8 that oxynitride films can be grown directly by submitting a Si substrate, or a Si02 film, to a gaseous N2O or NO ambient. This process permits a better control of the nitridation step and minimizes the amount of incorporated hydrogenated species. The obtained films display a greater resistance to high-field stresses (especially to carrier injection) and possess a greater resistance to dielectric breakdown. Although data about oxynitrides grown in NO is still scarce, the electrical properties of such films appear to be even better than those of N20-grown films. Moreover, the "thermal budget" required to incorporate the same amount of nitrogen in the film is much lower. Because of their reduced dimensions, current Ultra Large Scale Integration (ULSI) devices require ever-lower process temperatures to minimize parasitic diffusions and the growth of stacking faults. The fabrication of high-quality VTGIs at low temperature will be required to produce the highly integrated devices of the future. In Section 9 we describe this new interest for non-thermal ways of growing thin insulating films (including silicon oxide, nitride, nitroxide and oxynitride) at "low" temperature, i.e. near room temperature. We describe the principle of each method, discuss the growth process and mechanisms, and sununarize the main physical, chemical and electrical properties of the resulting VTGIs. Thin nitride and oxynitride films have found already numerous applications in microelectronic devices and will be increasingly used. 2. AN OVERVIEW OF SOME THIN INSULATORS USED IN VLSI DEVICES Before we describe in detail the processes used to fabricate thin insulator films for VLSI devices, let us first review the general features of these films and the reasons behind their use. 2.1. W H Y USE THIN INSULATORS?

In active NMOS or CMOS devices, the thickness of the gate insulator (tox) has been scaled down from 100 nm (in the early 70's) to less than 10 nm for current (1996) submicrometer devices [11-14]. This thickness will, however, be further reduced. Transistors with an effective channel length (Leff) of 0.25 |im require gate oxide thicknesses ranging from 6 nm to 10 nm while when Leff is reduced to 0.1 |Lim, tox will have to be brought down to 3.5 nm [15-17]. Likewise, in EEPROMs, the reduction in programming voltage requires that thin tunneling insulating (dielectric) films be used and thicknesses as low as 10 nm have become common [12a]. These very thin insulators are either thin thermal oxides or dual structures made up of thermal oxide + silicon nitride [18-21]. The quality and the reliability of these films condition the performances of the ICs which use them [20 b-c, 22-23]. Basically, thin dielectrics can be divided into two groups: "native" dielectrics and "deposited" dielectrics. The term "native" designates films which are formed by means of a chemical reaction (e.g. oxidation, nitridation, etc.) of the semiconductor substrate while "deposited" means that the dielectric has been formed without any chemical reaction with the semiconductor.

Silica, Silicon Nitride and Oxynitride Thin Films

17

2.2. SOME BASIC REQUIREMENTS

To be used effectively as a VTGI, a dielectric material must meet some basic physical, chemical and electrical requirements which we review next. 2.2.1. Physical and chemical requirements • An homogeneous structure To make sure that the fabrication yield of integrated circuits remains high in spite of the ever-increasing chip size, the dielectric films must be homogeneous and uniform and must retain a low defect density throughout the entire fabrication sequence. The as-grown films must be free of localized defects, pin-holes and microcracks and these defects should neither appear during the subsequent manufacturing steps nor appear while the complete device is operating. • An efficient barrier against diffusion and parasitic effects The dielectric films should, ideally, prevent all foreign species from diffusing into active parts of the device since this diffusion can greatly alter the threshold voltage. These foreign species can be: doping atoms (e.g. boron atoms coming from the polysilicon gate electrode), ions introduced during plasma etching or diffusing from a metal gate electrode, or any type of contaminant introduced during the fabrication process. Moreover the films should also minimize other parasitic effects taking place in the substrate such as: - growth-induced crystal defects, due to thermal stresses generated in the semiconductor when the dielectric is fabricated (see e.g. Chap. 3 of Vol. 1, [10 c]). - impurity segregation, - dopant redistribution at the substrate-insulator interface. For the thin films to be homogeneous and constitute an efficient barrier, two more requirements related to the fabrication process must be met. • A well-controlled growth rate The growth rate should be well controlled to minimize interfacial defects and to ensure the desired composition, both of the bulk dielectric and of the transition layer (when such a layer exists). Let us note, however, that after more than 20 years of research, the first stages (< 5 nm) of the thermal growth of silica on silicon are not yet fully understood and the Deal & Grove model is still opposed to the viscous flow model (see e.g. Chap. 1 of Vol. 1, [10 a] and [25]). • A well-controlled surface quality Cleanliness is essential to obtain a well-controlled growth or deposition and to obtain a good step coverage (for deposited layers). For instance, the thermal oxidation of silicon induces the formation of Si+, Si2+ and Si3+ intermediate oxidation states, which extend « 4 nm from the silica film into the underlying silicon substrate and the width of this interfacial layer depends on the oxidation conditions and on the initial quality of the Si surface. The existence of such a transition region can, of course, be critical for ULSI products.

B. Balland and A, Glachant

18

2.2.2. Electrical requirements To produce high-quality and reliable submicrometer VLSI devices, thin dielectrics should have near-ideal electronic properties. • A large band gap A large band gap is desirable since it provides a large energy barrier at the interfaces, which minimizes hot carrier injection (see e.g. Chap. 9 of Vol. 1 of this book series [10 e]). It also ensures a lower sensitivity to radiation (as explained in Part 2 of this volume). The band diagrams of three typical Metal-Insulator-Silicon (MIS) structures are given in Fig. 1.02. Let us note that it is not appropriate to use the values indicated in Fig. 1.02 for very thin films due to the presence of a proportionally larger transition region whose composition and properties differ from those of the bulk. For example, for thin SiOx oxides, the value of x may decrease from 2 to 1 and the band gap decreases accordingly.

r^

k T2.2

i

2.0 1.1

51

L [[2.0

Al

SiOg

Si

Al

AI2O3

Si

Al

Si^N^

Si

Fig. 1.02 - Energy-band diagrams of ideal unbiased MIS structures (energies are expressed in eV). (After [26] slightly modified)

• A suitable dielectric constant A high dielectric constant (or permittivity) is important when a good capacitive coupling is required (which is the case for the gate of MOS devices). On the other hand, the field insulator deposited between the interconnecting layers of an IC must possess a low permittivity to minimize the values of the parasitic capacitor coupling the active zones of the device with these interconnecting lines. • A large breakdown voltage Dielectric layers in modem ICs must sustain large electric fields without displaying sizeable leakage currents. They thus must exhibit a uniform and high dielectric strength (a high breakdown voltage) as well as an extended wear-out time (these concepts have been defined in Chap. 6 of Vol. 1 [10 d] and are again reviewed in Chap. 3 of this volume). The films must also be able to sustain an injection of hot carriers triggered by high fields (which is the case of EEPROMs and short-channel MOSFETs).

Silica, Silicon Nitride and Oxynitride Thin Films

19

• A low dielectric charge To obtain high-performance MOSFETs with fast turn-on characteristics and high carrier mobility, the electrically active defects encountered in the gate insulator and at its interfaces, and the associated charge, must be minimized. Traditionally four basic types of charge are distinguished in dielectrics: • The mobile ionic charge, mostly made up of sodium ions mobile at room temperature or slightly above it (charge Qm, density Nm). • The trapped charge, whose sign depends on the nature of the trapped carriers (mostly holes in the case of silica and mostly electrons in the case of silicon nitride) distributed in the bulk of the insulator (charge Qot, density Not). • The interface-trapped charge, which is made up of carriers trapped on those interface defects which, depending on bias, can exchange carriers with the semiconductor (charge Qjt, density Nit). • The fixed insulator charge which is the sum of all the other charges which are impervious to changes in bias conditions (charge Qf, density Nf). All the electrically active defects which have a significant impact on device performances (i.e. on MOS threshold voltage, carrier mobility, surface leakage, etc.) have been described at length in the previous two volumes of this series. Since the thickness of the gate insulator is much reduced in modem submicrometer devices, the effects of Qm and Qot are also reduced but Qf and Qit still play a major role. 2.2.3. Application-dependent requirements Depending on how the thin dielectric layer will be used and in which type of device, some of the above-mentioned requirements are more important than others. We have listed in Table 1.01 the qualities required from thin dielectric films in four types of application. • For traditional MOSFETs with n-type polysilicon gate electrodes and without buried contacts, silicon dioxide is still an appropriate gate dielectric because of its superior electrical properties [27-28]. • If buried contacts are required or if p-type polysilicon is used as a gate electrode material, nitrided silica is more suitable as a gate dielectric because of its enhanced resistance: to etching and to the diffusion of doping (boron) atoms [28-29]. • If the dielectric film is used to manufacture the storage capacitors of DRAMs, some of its electrical characteristics are not too critical but the films must have a high dielectric constant and a very low leakage current [30-32]. • Finally, in the case of EEPROMs, the most important feature of the thin dielectric is that its trapping properties be low and its resistance to wear-out be high [33-35].

20

B. Balland and A. Glachant

DEVICES

-^

MOSFETwith n+poly and no buried contact

MOSFET with p+poly or with buried contact

DRAM

EEPROM

TYPE OF INSULATOR

~>

Gate insulator

Gate insulator

Storage capacitor

Tunneling dielectric

He He

•p *l* 'P *r

He He He

****

•p n^ 'F •p

He He He He

High sensitivity to HF etching

• «

He He He He

He He

H: He

Good diffusion barrier

• *

^^ ^ ^

He He

He He

1 REQUIRED PROPERTIES ^

High dielectric constant Low defect density

Low leakage current

He

*

^^ ^ ^

He :(c 4 : si:

He He He He

He He He He

He He He He

** *

He He He

He He He He

He He He He

Good resistance to wear-out

He He •

^^ ^

He He He He

****

Very low density of bulk traps

He He He

He He He

He

****

****

He

He He He

****

He

He He He

He He He He

He

He He

High breakdown field

Very low interface charge

^

Very low density of interface traps

m Hn iti

High carrier mobility

He He He He

^ ili ^

j

*

Table 1.01 - Properties required from the dielectric films for various applications: (* (***) very critical (* *) fairly critical f*; not critical (After [18] slightly modified).

•; most important factor,

2.3. THE MANUFACTURING OF THIN OXIDE FILMS

For VLSI devices, silica films with a thickness ranging from 5 to 20 nm must be fabricated in a repeatable manner [36-39]. There basically exist two methods to grow such thin films: - Thermal growth, - Chemical Vapor Deposition (CVD). Let us review in some detail the most important features of these two methods and those of the produced films. 2.3.1. The thermal growth of thin oxides Thermal growth is by far the method most widely used to prepare thin (gate) oxides because the electrical properties of the films thus produced are vastly superior to those of CVD silica films. (The thermal growth of thick oxides has been extensively described in Chap. 1 of Vol. 1 of this series [10 a] and will not be described here). From a practical point of view, the growth rate of thin oxides must be slow enough to obtain a uniform and reproducible thickness [41]. It should not exceed 1 nm/min in the linear region and about 5 nm/min in the parabolic region.

Silica, Silicon Nitride and Oxynitride Thin Films

21

• Dry oxidation versus wet oxidation Dry oxidation is performed in pure O2 with P(02) - 1 bar and 900°C < T < 1150°C. It yields good quality oxides. The experimental data of Fig. 1.03 demonstrate that a set of time and temperature parameters can be chosen to grow thin oxides with a reasonable control of the thickness. In the wet oxidation process, water vapor is introduced in the oxidizing ambient. "Wet" films grow faster than "dry" films and at somewhat lower temperatures (900°C < T< 1000°C) [42-46]. • High-pressure oxidation In the high-pressure (HP) oxidation process, P(02) may vary from 5 to 20 bar with 800 < T < 1000°C. This method can be used to increase the growth rate while using a lower processing temperature to reduce impurity diffusion and to decrease the quantity of oxidation-induced stacking faults. However, due to the faster growth rate, the suitability of this technique to fabricate thin gate dielectrics is questionable [47-50]. 10

1

1

U I

E c <0 (0

1 1 11

1

« '

r

[

fi

u

^

.^

M ^'

1

1 1 11

1 1 11

10°

f""^nr|

\

^ ^ 2 ^'m.''AT'

*

*

*

*

r-n

1

?^

1

*

1

*

*

1 SOCC 2 850°C

0' r ML-' .a » * » ^ ^ / y ' • -' ^ c< ^ ' * '

r

10

'

/' —^' ^'' * '' *^

s

r L \L

' ' 1

.-

M

1

o

'

^'

r\

h —

2 o

i

<100> Silicon Dry Oxygen

1

c o

'1

10^

1

1

L.xJI

J

j 1 \

SOCC 950°C 1000°C •]

3

XI

—4

iJ

1 L.

1

10^ 10^ Oxidation time (min)

Fig. 1.03 - Oxidation rate of a lightly doped <100> silicon substrate in dry oxygen in the 800-1000°C range. (After [44 a] modified).

i_J

10'

• Low-pressure oxidation Low-pressure (LP) oxidation offers an attractive way of growing thin oxides in a controllable manner [25 a]. Oxide thicknesses between 3 nm and 14 nm have been grown this way at temperatures ranging from 900 to 1000°C using an oxygen pressure of 0.2 to 2.0 mbar. With this method, the growdi rate is slower, which makes the method attractive if controlling the oxide thickness is very critical. The observed growth rate is parabolic, and the growth rate constants agree with the values extrapolated from those of atmospheric pressure growth. The LP oxides are very uniform, homogeneous, and similar to thicker oxides prepared at atmospheric pressure [56]. • Two-step process A two-step oxidation process has also been proposed to obtain thin oxides [57-58]: 1/ The first step is carried out at a moderate temperature (T < 1000°C) in a dry 02-HC^ ambient and leads to the formation of a uniform oxide with a small defect density. 2/ The second step consists in a heat treatment in N2, O2 and HC£ at 1150°C to bring the oxide to the desired thickness. ECi (or HF) ambients are typically used to passivate ionic sodium, to improve the breakdown voltage, and to reduce the amount of impurities and defects in silica.

22

B. Balland and A. Glachant

Such a sequence takes advantage of the beneficial effects brought both by the lower and the higher temperatures. • High'pressure and low-temperature steam oxidation A 30-nm-thick oxide can be grown in 30 min using an oxidizing pressure of 5 bar < P < 10 bar and a temperature of TOO^'C < T < lOOO^'C. Pressure, temperature and time can be changed to obtain the desired thickness. Such a technique has been successfully applied to the growth of thin gate oxides for MOS dynamic RAMs. The properties of the obtained thin films depend more on the oxidation temperature than on the oxidation pressure. To reduce the density of electrically active defects in the oxide film, oxidation is often followed by an anneal at oxidation temperature in an inert ambient followed by an anneal in forming gas (FG: 10% H2 and 90% N2 or Ar), at 450°C, once the device has been fabricated. • Others To reduce the oxidation temperature, several beam technologies are also being investigated. For example a scanning CW argon laser beam (488-514 nm) with an incident power of 2.5 W has been used to grow a 5-nm-thick siUca film [20]. 2.3.2. Properties of thin thermal oxides The duration, the temperature and the conditions of oxidation, all influence the structure and the properties of the resulting oxide film. It is therefore important to gain a good insight into this relationship to obtain thin oxides with reproducible parameters [56-60]. • Transition region It has been experimentally shown that thin thermal oxides are strained in a zone which extends 1.5 to 3 nm away from the silicon/oxide interface and which differs from bulk Si02 [58]. It appears also that oxidation processes carried out at high-temperature lead to an increase in thermal stresses in the underlying semiconductor and to a degradation of its properties. • Excellent interface Thermal oxide films exhibit an excellent interface with the Si substrate and a low trap density. The trap density is further reduced by annealing in hydrogenated ambients at low temperature, i.e. in FG at 450°C (hydrogen passivates the traps). At higher temperatures, hydrogen can desorb, which increases the trap density. For this reason, the annealing is performed after all other high-temperature process steps, and is usually the last fabrication step. In spite of this excellent interface, the leakage current in thin oxides increases when the thickness decreases, because of tunneling effects. For a 10-nm-thick oxide, the leakage current is sizeable above five volts due to Fowler-Nordheim tunneling. • Dielectric strength The amount of micro-defects propagating from the Si substrate into silicon dioxide during oxidation decreases for thin oxides. Thus, contrary to earlier predictions, thin oxides display in fact a better reliability than thick oxides and their breakdown field is higher. • Mask against diffusion A thermal oxide can also act as a (more or less efficient) diffusion barrier. The values of the diffusion constants for various dopants in Si02 depend on the density and the structure of Si02. Table 1.02 lists diffusion constants for several common dopants. Not surprisingly, quoted values may vary significantly [23, 59].

Silica, Silicon Nitride and Oxynitride Thin Films

Dopants B Ga P As Sb

Diffusion constants at 1100°C (cmVs) from 3.4x10-17 to 2.0x10-14 5.3x10-11 from 2.9 x 10-16 to 2.0 x 10-13 from 1.2x10-16 to 3.5x10-15 9.9x10-17

23

Table 1.02 - Diffusion constants of various dopants in SiO . (After [60])

• Impurity segregation As thermal oxidation proceeds, the Si02-Si interface moves into the siUcon substrate. A doping atom initially present in silicon will redistribute at the interface until its chemical potential is the same on each side of the interface. This redistribution may result in an abrupt change in doping concentration across the interface. 2.3.3. Limitations of traditional thermal growth for very thin films Very thin thermal oxides can presently be fabricated using a low oxidation temperature, a diluted O2 gas (e.g. diluted in N2) and a reduced gas pressure in the fumace. However, the dielectric properties of the thin films thus prepared often suffer from these oxidation conditions. Moreover, the early stages of oxide growth should not be perturbed if one wants to obtain the desired oxide thickness. Finally, a considerable amount of water vapor is incorporated into the film during the loading and unloading steps. Unless water is fully removed from the silica film, the residual hydrogen atoms form electron trapping centers which degrade the oxide quality. For all these reasons, traditional thermal growth will be increasingly difficult to rely upon, to manufacture very thin oxide films. The important features of thermal oxidation as well as the characteristics of thermal oxides are summarized in Table 1.03 [25]. 2.3.4. Thin oxides obtained by chemical vapor deposition Deposited oxides are also widely used in the IC industry as field oxides [23]. The methods used for their fabrication and the main properties of CVD-oxides are listed in Table 1.03. The most commonly used deposition techniques are based on: - the reaction of silane (SiH4) and oxygen; - the thermal decomposition of tetra-ortho-silicate (TEOS = (C2H20)4 Si); - the reaction of SiCl2H4 and oxygen. Unfortunately not much is known about the reliability of thin silica films grown by techniques other than thermal oxidation. Silica layers enriched in silicon (with 13% excess Si) can be produced by depositing a 10 to 20-nm-thick Si-rich Si02 layer by CVD on top of a 10-nm-thick thermal oxide. Such dual dielectrics have found applications in memory and logic circuits [66].

24

B. Balland and A. Glachant

Fabrication mode

Growth

Deposition

Reacting species

Si + 02

SiH4 + 02

Deposition TEOS*

Pressure Temperature (°C) Deposition rate (nm/min) Composition

Ibar 900-1000 -

Ibar 300-450 43-52

Ibar 500-800 12

Si02

Si02(H)

Si02

Si02(C^)

Thermal stability

very stable

densifies

stable

looses a

Density (g/cm^)

2.2

2.1

2.2

2.2

Refractive index (for X = 546.1 nm) Dielectric constant Residual film stress (109dyne/cm2)

1.46

1.44

1.46

1.46

3.9

3.6 3 (tensile)

3.7 1 (compressive)

3.6 3 (compressive)

Dielectric strength

8-10

8-10

10

10

60

highly process1 dependent

highly processdependent

highly processdependent

Deposition

|

SiC€2H4 + 02** 1 15-60 mbar

850-1000

1

low

1 1

1 (MV/cm) lEtch rate in buffered* 1 HF (10-1 nm/min)

Table 1.03 - Characteristics of the major oxide fabrication techniques and properties of the produced films f* thermal decomposition of tetraethylorthosilicate (C2H20)4Si - ** low partial pressure of reactants • 100:1 = NH4:HF). (After [25] modified). 2.4. THE MANUFACTURING OF THIN SILICON NITRIDE FILMS

Silicon nitride is the second most widely used insulator. 2.4.I. The advantages of silicon nitride Silicon nitride (Si3N4) has distinct advantages over silicon oxide [61-62]. It has a higher dielectric constant (ei. = 7.5) than silica (ei. = 3.9) and has a denser structure. This denser structure makes it a better barrier against the diffusion of various species [63-67]. • Barrier against oxygen The fact that silicon nitride is a good barrier against the diffusion of oxygen has given birth to the LOCOS technique (LOcal Oxidation of Silicon) described in § 4.4.3 [68-70] and to self-aligned processes [70-72]. • Barrier against doping atoms This property is particularly important when boron-doped polysilicon gate electrodes are used, boron having a tendency to migrate through the oxide and contaminate the underlying silicon substrate. • Barrier against mobile ions, moisture and other impurities This property has led to use silicon nitride as a passivation and protection layer [64-65].

Silica, Silicon Nitride and Oxynitride Thin Films

25

• Resistance to etching Silicon nitride resists etching in hydrofluoric acid (HF) better than silicon oxide. A variety of methods may be used to fabricate silicon nitride films either through growth or through deposition [73-78]. These methods can be classified according to the temperature used (i.e. high temperature (HT) versus low temperature (LT)) or depending on whether nitridation takes place directly or is somehow "assisted" or "enhanced". These methods are briefly described next, and will be described in detail in further sections. 2A.2. Direct nitridation • Thermal nitridation Thin silicon nitride films can be grown by exposing a silicon surface to N2 or NH3 at high temperature (950°-1300''C). This method gives a film which is less than 10 nm thick because growth is quickly limited by the difficult diffusion of the reacting species through the formed film. The process will be fully described in Section 3. • Enhanced nitridation Silicon nitride films thicker than 10 nm can be grown at a lower temperature if the nitridation process is "enhanced". The enhancement techniques can rely on plasma or RF glow discharge [79-85], photons [78, 86-87], electrons [88-89] and ions [90-91]. Another enhancement technique is based on the introduction of a variety of components in the nitriding ambient to act as catalysts. This includes fluorinated compounds such as SFg, NF3, CF4, [92-95] or alkali metals [96-97]. • Ion implantation The low-energy implantation of nitrogen ions (N+ or N2'^) has also been investigated [98-101] to produce nitride films on silicon. Nitrogen ions are implanted beneath the surface of the silicon wafer and Si3N4 forms [102-104]. The implantation can be followed by an HT anneal. The thickness of the nitride film is controlled by the implantation voltage, the ion mass, and the ion dose. Since the implantation profile is of the Gaussian type, an abrupt interface with the Si substrate cannot be achieved, which results in poor interfacial properties. 2.4.3. Deposited nitrides In the IC industry, most nitrides are deposited using Chemical Vapor Deposition (CVD) processes [74-77, 105-124]. There exist basically two processes to accomplish deposition: - by letting silane (SiH4) react with anmionia (NH3) at high temperature (700-900°C) and high pressure (P(NH3) > 1 bar), - by letting dichlorosilane (SiCl2H2) react with NH3 at low pressures (P(NH3): 15-60 mbar) and high temperature (700-900''C) and at high pressure (P(NH3) > 1 bar). Chemical vapor deposition may be performed either at Atmospheric Pressure (APCVD), at Low Pressure (LPCVD) or may be Plasma-Enhanced (PECVD). The composition of the deposited films depends to a large extent on the deposition conditions and their electrical behavior can vary from conducting to insulating, depending on the silane-to-ammonia ratio. Let us note that deposited films usually contain a high density of bulk traps, interface states and hydrogen. Silicon nitride films may also be obtained by high-rate reactive sputtering, performed at low temperatures [125-126].

26

5 . Balland and A.

Glachant

2.5. THE USE OF OTHER DIELECTRIC MATERIALS

To substitute for pure silica or pure nitride, other insulating materials have been tried. 2.5.1. High-permittivity materials Several insulator materials with high-permittivity (high dielectric constant) have been envisaged to substitute for thermal oxides. They are listed in Table 1.04. Thermal silica films have a dielectric constant of 3.9. Dielectric constants between 4.5 and 5.5 have been reported for silicon oxynitrides [18, 20, 21, 74], the dielectric constant increasing with the nitrogen content. Silicon nitride has a dielectric constant ranging from 6.0 to 7.5.* Deposited dielectrics possessing a high dielectric constant are interesting to manufacture the storage capacitors of DRAMs. Deposited dielectrics like Ta205, Nb205, Ti02, Zr02, etc. have a high dielectric constant in the 11-100 range. Among the insulators listed in Table 1.04, titanium oxide has the highest dielectric constant, but because of a strong dispersion in the MHz frequency range, it is ruled out for high-speed write-erase devices. Tantalum oxide seems attractive because of its high dielectric constant (22, i.e. 5.6 times larger than £ox) which varies little with frequency. However, the structure of the film deposited by the chemical reaction of tantalum chloride and oxygen does not stay amorphous during subsequent heat treatments and easily changes to polycrystalline. The polycrystalline structure sometimes leads to a non-uniform trap distribution within a film plane, which has a negative effect on the memory performance. A mixture of tantalum oxide and aluminium oxide has been proposed as an insulator for MIOS memory [128]. In a certain range of concentration ratio, the film remains amorphous. A one-transistor one-capacitor DRAM cell structure consisting of a MOSFET with a Ta205 storage capacitor stacked on it has also been described [129-130]. Ta205 is a material of choice for future generations of DRAMs [131]. Si02

Si3N4

M2O3

Ti02

Ta205

Nb205

8.9

5.1

8-9.5

3.0

4.2

3.5

Refractive index (for X = 546.1 nm)

1.5

2.0

1.7

2.0

2-2.3

2.2

Dielectric constant

3.9

6-7.5

8

20-50

19-22

11

3

2

10

100

100

100

8-10

5-10

7-8

0.5

5

5

Insulating material 1 Energy gap (eV)

Loss tangent (at 100 kHz) (lO'"*) Dielectric strength (MV/cm)

Table 1.04 - Properties of some thin dielectric materials. * The 7.5 value corresponds to a silicon-rich CVD nitride film deposited on a 10-nm-thick thermal oxide and is due to the 13% excess Si (8Si« 11.8) existing in that nitride film.

Silica, Silicon Nitride and Oxynitride Thin Films

27

2.S.2. Silicon oxynitrides Because they retain favourable features of both silica and silicon nitride while minimizing their drawbacks, oxynitride films are of great interest. For example, silica deposited on silicon is under compressive stress, while nitride is under (an even greater) tensile stress. It is thus possible to tailor a SiOxNy (x = 1.75, y = 0.25) film, which will leave film and substrate stress free [132]. Likewise, the band gap energy of SiOxNy can be adjusted between 5 eV and 9 eV depending on the [0]/[N] ratio, which gives rise to potential applications for heterostructures. The methods most conmionly used to fabricate oxynitrides are the LPCVD and the PECVD processes. • The LPCVD process is generally performed at 800 < T < 850°C using various gas mixtures (NO-NH3-SiH4, SiH2Cl2-N20-NH3 or ND3, SiH4-C02-NH3-H2) and very low pressures (P = 0. 2 to 0.3 X 10-3 mbar). The composition of the nitride films thus obtained is uniform across their thickness. N-H bonds have been observed with a total concentration of hydrogen atoms of about 5 x 10^^ cm-^. Excellent dielectric breakdown distributions have been found for layer thicknesses as low as 7.5 nm and midgap interface state densities of about 5 x lO^O cm'^ eV-l have been found. For non-volatile memories, most of the experiments performed in the past used an LPCVD nitride. • The PECVD process is generally performed at 300 < T < 430°C using various gas mixtures (SiH4-NH3, SiH4-N20, SiF4-SiH4-N20-NH3-Ar, SiH4-N20-NH3-H2, etc.) and low pressures (P = 2.0-2.6 mbar). The resulting films contain generally up to 10^^ hydrogen atoms per cm^ and have an excellent uniformity. In addition to the homogeneous silicon oxynitride films mentioned above, there exist other nitrogen-rich oxide films which can be produced but whose nitrogen concentration is not homogeneous. The most commonly encountered ones are: - the nitrided silicon dioxide (NO) film, obtained by nitriding a thin silica film in gaseous N2 or NH3 (as explained in Sect. 5), - the re-oxidized nitroxide film (RONO), obtained by oxidizing an NO film (as explained in Sect. 6), - the ultra-thin oxynitride film produced by rapid thermal oxynitridation (RTON) technologies, (as explained in Sect. 8). Compared to oxides, oxynitrides have advantages which are reviewed in the relevant sections. 3. THERMALLY-GROWN SILICON NITRIDE THIN FILMS Since they provide a promising solution to obtain thin gate insulators for VLSIs, silicon nitride films grown directly on silicon substrates have been extensively studied [133-135]. Thermal growth is possible by exposing a silicon surface to a nitriding ambient (i.e. containing highly purified nitrogen (N2) [133] or ammonia (NH3) gases [134]) at high temperature.

28

B. Balland and A. Glachant

Thermal growth can be carried out at High Pressure (typical parameters P > 1 bar, 900 < T < 1300°C) or at Low Pressure (with 10-7 < P < 10-5 mbar and 800 < T < 1050°C) depending on the desired result. We describe these two types of process in the present section. Thermal growth is unfortunately a naturally self-limiting process and the thickness of the obtained films does not exceed 10 nm. Thermal growth is also possible in a highly purified anmionia plasma (plasma generated by RF power) in a lower temperature range (250°C < T < 1200'^C). Films thicker than 10 nm can be produced within a reasonable reaction time only by using plasma-assisted processes. This altemative technique is also briefly described in this section. 3.1. LOW-PRESSURE (LP) THERMAL NITRIDATION

Low-pressure thermal nitridation is not an industrial process but it is a useful tool to study the nitridation process itself. 3.1.1. Principle Nitride films can be grown at high temperature and low pressure. This Low-Pressure (LP) process must be carried out in an Ultra High Vacuum (UHV) chamber where residual pressures as low as 10-^^ mbar can routinely be obtained. Only a UHV apparatus permits excellent control: - of the purity of the reacting gases, - of the cleanliness of the silicon surface. The nitriding species can be atomic nitrogen [136-141], or NH3 [140-141]. The pressure of the reacting gas usually never exceeds lO""^ mbar while the temperature remains below llOOX. The thickness of the nitride film can be monitored in-situ by using Auger Electron Spectroscopy (AES) [136-141], X-ray Photoelectron Spectroscopy (XPS) [132, 140] and Thermal Desorption Spectroscopy (TDS) [141]. It can also be measured ex-situ by means of Nuclear Reaction Analysis techniques (using for instance the I'^N (d, a) ^^C nuclear reaction to measure the amount of ^^N in the film) [141] as explained in Chap. 7 of this volume. The structure of the film can be monitored by means of Low Energy Electron Diffraction (LEED) [136-141]. Compared to the HP process described in § 3.2, the LP process allows a much better control of the growth rate. 3.1.2. Experimental evidence of nitride growth How thermal nitride layers grow is not fully understood yet, especially for the first stages, i.e. for a film thickness tN < 5 nm (see Chap. 7 for more detail). The early stages can however be followed by means of AES. Since the Si(lOO) substrate orientation is the most widely used in microelectronics, we shall next limit our discussion to this case. Figure 1.04 shows the evolution of the Si(L23VV) and N(KLL) Auger transitions of silicon and nitrogen respectively, when a clean Si(lOO) surface is exposed to an anmionia ambient (P(NH3) = 3x10-7 mbar) at T = 950°C.

Silica, Silicon Nitride and Oxynitride Thin Films

Si(L23VV)

29

N(KLL)

x50 42.5

^\.^\

x20 x20 x20 x20 71 I 90 61

82,7

1 . I . I . t • I . I . t • r

40

60

360

80

t J

3 8

100350

Energy

2 J

Fig. 1,04 - Evolution of the Si(L23W) and N(KLL) Auger transitions upon nitridation of a silicon substrate (T = 950°C - P(NH3) = 3x 10'^ mbar): (a) clean Si(100)-2 x 1 substrate (b) t = 0.5 h (one nitride monolayer) (c) t = 2 h (two nitride monolayers) (d) t = 3 h (three nitride monolayers) (e) t = 16 h (five nitride monolayers) (monolayer thickness = 0.35 nm). (After [88] modified).

L_

450

(eV)

The AES spectram (recorded in the derivative mode) of the clean Si(lOO) surface is visible in Fig. L04, curve a, while its LEED pattern, characteristic of a 2 x 1 superstructure, is shown in Fig. 1.08 a. When the nitridation time increases, a new AES peak develops at 82.7 eV. This peak is due to the presence of Si-N bonds. It develops at a much lower kinetic energy than the main Auger transition located at 91.5 eV. The latter is characteristic of Si-Si bonds while the former indicates the presence of Si-N bonds in a Si3N4 matrix. The presence of three peaks (at 61, 71 and 82.7 eV) constitutes the "signature" of Si3N4. Since these transitions are observed only after the first full monolayer has completely grown on the substrate, it has been concluded that the silicon/silicon nitride interface is abrupt [141]. This contradicts, however, previous results indicating the presence of at least two nitride compounds in the layer [140]. By "flashing" (i.e. by quickly heating) the nitride monolayer in vacuum at T = 1215°C in front of a quadrupole mass spectrometer, one [136, 141] is able: to identify the thermal desorption products (H2 and Si2N), and to monitor thickness tN, by using the integrated intensity of the Si2N thermal desorption peak. Thickness t^ can also be deduced from the intensity of the N(KLL) AES peak (e.g. one can find from Fig. 1.04 that after 16 hours, tn = 1.8 nm, assuming a layer-by-layer mode of growth [141]). The residual hydrogen content of the grown film can be measured by means of NRA (using reaction (D(3He, a)p as explained in Chap. 7) whose sensitivity limit is 2 x 10^2 atom/cm^ [141]. In the case illustrated by Fig. 1.04, no trace of hydrogen contamination could be found [88].

B, Balland and A. Glachant

30

3J.3. Some experimental growth curves Several growth curves are illustrated next. The thickness of the nitride film (assessed by means of the AES N-peak or by means of the TDS Si2N-peak) is plotted as a function of nitridation time. Several isothermal growth curves are shown in Figs. 1.05 and 1.06. All growth curves reveal an initially fast regime which is linear with time, until the first monolayer is formed (one nitride monolayer contains « 3 x lO^^ N atoms/cm^ and its thickness is « 0.35 nm [136]). During this first step, the growth rate does not appreciably depend on T (in the temperature range investigated) as visible in Fig. 1.05, but it varies strongly with P(NH3) as shown in Fig. 1.06. The growth rate slows down once the first monolayer is completed. This translates into a sharp break in the growth curves (i.e. an abrupt change in slope) quite visible in Figs. 1.05 and 1.06. Growth slows down further as more monolayers are formed. 3.1.4. Growth modeling These experimental results clearly show, as previously assumed [143, 144], that the thermal growth of silicon nitride is diffusion-limited.The abrupt reduction in growth rate suggests [141] that: 1/ the first monolayer covers entirely the silicon surface, 2/ the reacting species needs to diffuse through the first layer to fuel further nitride growth. This has led to propose a layer-by-layer growth model [141] in which one layer is completed before the next one begins to grow over it. The arrows of Figs. 1.05 and 1.06 indicate the completion of the successive layers according to this model.

1 "ii [-• 3 » 'ayer

3 (0

---r

R-aSlayer

0>

1 KJ-

.--o-

• o

"^

"^

°

•<>•

N

O) 3

i> 1

<

p K

b [• 2^ CO

3 r

Q.

L

o

Q . k-

1

1

1

1

1

1

t

1

1

1

• .-X-""

---'^—

u

,.)c::-5

1

• ---X-

.--x--"

0

r ,^-

1

^"

'^'

^

'>'0 0

•o o 1 •z c

X...950X 1

•

Lb 1

-1

60

1

1

120

I

1

180

1

„ ^,^-7 ^ i

1

240

Nitridation

time

1

1

300 (min)

U

360

Fig. 1.05 - Growth curves of an LP thermal nitride on a Si(lOO) substrate for two growth temperatures (835°C (O) and 950''C (x)) at PiNHs) = i jc 10'^ mbar. The nitride thickness is monitored by AES and TDS. (After [136, 141] slightly modified).

Silica, Silicon Nitride and Oxynitride Thin Films

31

l h

.»--"•*

Fig. 1.06 - Growth curves of an LP thermal nitride on a Si(IOO) substrate at 950°C for four ammonia pressures: P(NH3) = 10-^mbar (X); P(NH3) = 3x 10-^ mbar (m); P(NHs) = 1.3 x 10'^ mbar (o); P(NH3) = 5x 10'^ mbar (A). Nitride thickness is monitored by AES. (After [141] modified).

03 O Q.

<

^A'' JL^-

..*r

4-^

^- - 0 - ' --0" ^'*"

if'

O 3

4H

- A--^

1 t-«h

4 a

••

4—

th .

4 = layer rd .

3 = layer 2 = layer

• ^

-^•x--

0.5

St ,

xy

h' , k^ •

1 = layer

•

•

/.^

_i

L 1 1 1

50

1 11

J

1

L

100 Nitridation

. i . 150

1

time

j_lJ

L_

200 (min)

The growth curves of the LP process can neither be fitted by a logarithmic law [132] nor by a power law [21 a] (unlike the growth curves of the HP process studied in § 3. 2). The best fit of the growth data, in the case illustrated by Fig. 1.05, is obtained if one assumes that: 1/ the nitriding species are ionized and travel across the growing (ultra thin) film in the presence of a high electric field, i.e. that diffusion is opposed by drift (as previously proposed for the initial rapid regime of oxidation [51-56]); 2/ each growing monolayer can start at many points and the total area (or coverage) 0\ of the ith layer is the sum of all patches it occupies over the (i-l)th layer (ai is normalized to the available substrate area, i.e. Oo = 1). The above result means that thermal nitridation obeys in fact a pseudo layer-by-layer mode of growth, illustrated by Fig. 1.07 [141, 147], in which layer i can start even though the completion of layers (i-1), (i-2),..., 1 is not achieved. These conclusions have been confirmed by the NRA analysis of films grown consecutively with I^N and l^N ammonia [148-149]. Such a growth model requires the transport of N ions across the film in the presence of high electric fields, while some re-arrangements of Si atoms may take place [147]. This pseudo layer-by-layer growth mode is however difficult to observe, even with opposing electric forces, when ion transport is too fast (i.e. when higher pressures of reacting gas and higher temperatures are used). This may explain why even careful studies [55] have failed to reveal such a growth mode for higher pressures. 3.1.5. Proposed growth mechanisms Let us now consider the mechanisms at work during the growth, in NH3, of the first nitride layer. Careful XPS studies [150-152] have mainly shown that: - the dangling bonds of the silicon surface are saturated by various nitrogen or hydrogen species; - the nitridation of Si(lOO) is heterogeneous and proceeds via island growth.

32

B. Balland and A. Glachant

^)

|^a3-[..|—[ \A P

L H L

11

n^

H

IA2

1

_L_kl

ll

A

^ "^

\! '® 1 o r ' 5^2 0. . ' o > o 1

w\

(Yi n = 1

,

WA

k

¥\

81(100) F/g. 7.07 - Illustration of the layer-by-layer mode of growth of ultra thin nitride films on a Si(lOO) 2x1 substrate: C) a) Schematic cross section of the growing film; b) Evolution with time of the individual coverage of the first six layers, assuming that ion transport across the film takes place in the presence of a high electric field; c) Theoretical curve (—) deduced from b) and experimental data points (*) (T=950''Q P(NH3) = 3 x W'^ mbarUAfter [141]).

• ^

y^^

\

<^'

/ 1

•! '•• • • ' ~ l " ~Fl

^1 ^^ 0

1.0

b)

|a4|

y

"^

'

f

'

'

®,-''

'

o

^-'

^^

^ ^^ "

^^

^^

^12

16

(0 o ^

A

(0

3 2 L/91** o I f 1 E f«

I

I

\r

hie

8 1 2 16 Nitridation time (h)

Two situations arise depending on whether P(NH3) is greater or smaller than a critical pressure PQ: • if P > Pc, i.e. in the so-called "passivating mode", the growth rate is quite fast. The mean distance between islands is smaller than the diffusion length of the chemisorbed species, thus leading to a rapid incorporation of the chemisorbed atoms in the islands. The resulting coverage increases rapidly. • if P < Pc, i.e. in the so-called "burning mode", the growth rate is slow. The mean distance between islands (whose density is relatively small) is larger than the diffusion length of the chemisorbed species. This leads to a desorption of the nitriding species before reaction can take place along the island edges (where the species could be stabilized). Taking into account the above experimental results, a model explaining how the first reacted nitride layer is formed has recently been proposed [153] based on a thermodynamical and structural approach of the problem. This model proposes five steps: 1/ the chemisorption of NH3 molecules at the surface of Si( 100)2 x 1, which leads to the formation of s Si-NH2 and s Si-H species, 2/ the beginning of H2 desorption, leading to the breaking of = Si-H and = Si-NH2 bonds, 3/ the dimerization of = Si-H and Si-NH2 groups, leading to the formation of = Si-NH-Si = groups, 4/ the total desorption of H2 and the formation of = SisN groups (in which nitrogen has an sp^ hybridation), 5/ the formation of = Si3N2 groups (in which nitrogen has an sp^ hybridation) which is the basis for the formation of Si3N4.

Silica, Silicon Nitride and Oxynitride Thin Films

33

Fig. 1.08 ' LEED patterns corresponding to the LP nitridation of a Si(100) surface (energy of the primary electrons = 80 eV): (left) pattern of a clean Si(lOO) surface, (middle) pattern of a nitride monolayer 50% complete, (right) pattern obtained when close to one monolayer is formed. (After [136]).

3.1.6. Film structure Figure 1.08 shows typical LEED patterns corresponding to various stages of the reaction of NH3 on Si(lOO) at 800°C, leading to the formation of the first reacted monolayer [136]. Once a full monolayer is completed, a very faint 1x1 structure can be observed while the 2 x 1 spots have disappeared (Fig. 1.08 c). The disappearance of the diffraction features corresponds to the abrupt change in slope, observed in the top curve of Fig. 1.05, and which occurs after - 30 min of reaction, the silicon dangling bonds being saturated. Above this coverage, the LEED pattern vanishes showing that a layer with no long-range order has been formed [136, 141]. 3.2. HIGH-PRESSURE (HP) THERMAL NITRIDATION

Thermal silicon nitride films can also be obtained by letting a silicon substrate react at high temperature (T > 900°C) and at high pressure (P « 1 bar) in N2 or NH3 [20, 21, 63, 73]. Since below 1200°C the thermal nitridation process is self-limiting, thick films cannot be obtained unless an "enhancement" method is used. 3.2.1. Principle of non-assisted thermal HP growth Figure 1.09 shows a schematic cross section of a typical HP (High Pressure) reactor used for thermal nitridation. Chemically-cleaned silicon wafers are placed in the reaction chamber and react with highly purified N2 or NH3 or other nitrogen-rich ambients at a pressure of « 1 bar and at temperatures ranging from 900°C to 1300°C [20, 134]. This reaction yields a thin amorphous nitride film (nitride films of about 5 nm can be obtained within 200 min at 1200°C). Due to the self-limiting growth process, the obtained nitride thickness t^ cannot exceed 10 nm unless high temperatures (T > 1200°C), unacceptable for a regular fabrication process, are used [73,142-144]. From Arrhenius plots, the activation energy for the reaction between silicon and ammonia is found to be 0.2 eV. This low value makes it impossible to obtain films much thicker than 5 nm, unless either the substrate temperature is raised much above 1200°C, or the nitridation reaction is "enhanced", as explained next.

34

B. Balland and A. Glachant Quartz Tube

Pressure Vessel

Fig. 1.09 - Schematic cross section of a high-pressure nitridation chamber. (After [154] slightly modified).

Front Door

End Cop I Cooling Jacket

Gas Inlet N 2 NH 3 Main Heater

HP thermal nitrides are amorphous although some researchers have found [155-159] that thermal nitridation may produce crystalline (a-Si3N4 or p-Si3N4) or polycrystalline films. The discontinuous structure of polycrystalline films makes them unsuitable for use in microelectronics. --200 E c d100 Fig. 1.10 - Growth curve of a nitride film grown in a non-actived ammonia gas at 1200°C (A) and in an RF-actived ammonia plasma at lOSO^C (O). (After ho [134] slightly modified).

T

• I » ' "I Activated NH3 1050^CN

o 50 c

NH3 1200^C Deal-Grove Diff. Model

I u.

10

II i I

10

I

I

I I II

50 Nitridation

III

100 time

500 (min)

3.2.2. Principle of plasma-assisted thermal HP growth In this process, chemically-cleaned silicon wafers are mounted on SiC-coated susceptors and loaded inside a horizontal quartz tube. A highly purified NH3 gas is introduced in the tube at a somewhat reduced pressure (10-1
* This plasma nitridation process is much different from that process in which the substrate is biased to collect the plasma (anodic plasma nitridation).

Silica, Silicon Nitride and Oxynitride Thin Films

35

Figure 1.10 shows two growth curves. The lower one corresponds to an unassisted growth in purified NH3 at 1200''C at a background pressure of 1.33 mbar. Thickness i^ has been measured by ellipsometry. The curve shows that tj^ does not exceed 5 nm even after a reaction time of 200 min. The upper curve shows that the use of an RP-activated NH3 plasma clearly enhances the growth rate and makes it possible to decrease the nitridation temperature. Films thicker than 10 nm can be obtained within a reasonable reaction time although the growth rate remains much lower than that of thermal oxide films. This lower growth rate allows, however, a much better control over the nitride thickness (reproducibility is better than ± 0.5 nm). 3.2.3. The kinetics of HP nitride growth Thermodynamic considerations Except for a few reported results, dealing with the direct thermal nitridation of Si in N2 at T > 1150°C, using reaction times ranging from 1 min to 18 h, unassisted thermal nitridation is a self-limiting process which yields a maximum film thickness of « 7 to 10 nm [19, 20, 136-141]. Three reasons explain why it is difficult to cause silicon to thermally react with nitrogen in a direct manner: - the binding energy of nitrogen molecules is fairly high, - the diffusion of nitrogen atoms in silicon or silicon nitride is very slow, - the standard free energy of the reaction between silicon and nitrogen is low. It is worth noting that the thermal nitridation of Si cannot be achieved if the residual oxygen concentration (in the form of water or oxygen) in the nitriding ambient is above 1 ppm or if a native oxide layer remains on top of the substrate [160-163]: traces of oxygen have in fact a strong inhibiting effect on the nitridation reaction. For example. Fig. 1.11 illustrates a case where pure NH3 has been used on a silicon wafer whose natural oxide had not been previously removed. The film obtained is an oxynitride and not a nitride. This is due to the fact that the reaction of silicon oxidation is thermodynamically more favorable than silicon 1 • (N) nitridation, assuming standard equilibrium . / (N) + (O) 60 conditions [138]. 1 '-'•* • •D

50

u 40 F^

1 \

E 3

s

8

1 1

,

^^s

X V

Fig. 1.11 ' In-depth composition profiles of a thin nitride film grown on a wafer, whose natural oxide has not been removed prior to nitridation, in pure NH3 for 40 min at T^llOO^'C. (After [137]).

30 V V

\

s a

o o

20 10 r'

interface

"*.

''-

-^^

3

<

' 0

^^^>>.

1

\

1 u.-4—1 20

40

1

1

U

60 80 Depth (0.1 nm)

The top curve shows the variations of the composition parameter with depth, while the other two curves illustrate the variations of the [N] and [O] concentrations with depth.

36

B, Balland and A. Glachant

Indeed, thermodynamic calculations [19] have shown that the partial pressure of oxygen should not exceed 10-23 atm (i.e. 1 ppm) to let P-Si3N4 form in an otherwise pure ammonia ambient at T = 1200°C. The calculated stability field diagram for the Si-O-N system is shown in Fig. 1.12. Non-assisted thermal growth Unassisted isothermal HP growth curves for T > 1200''C and P(NH3) = 1.01 bar [143] are shown in Fig. 1.13. Large thicknesses (> 10.0 nm) can be obtained using HP and HT conditions. In this case the growth curves, as illustrated in Fig. 1.13, follow a law of the form: tN=107(k/d)log(t+l)

(1.1)

where k is the rate constant of the reaction, in g/(cm2.min), d is the density of silicon nitride (3.18 g/cm3), tN is the layer thickness in nm and t is the nitridation time in min. The k values deduced from the experimental results increase from k (1200°C) = 3.60 x 10-6 g/(cm2.min) up to k (1350°C) = 22.70 x 10-6 g/(cm2.min). To explain such a logarithmic-like growth, a model has been proposed in which the nitriding species are supposed to diffuse through microcracks or faults in the growing film [142]. Finally, a law of the following form, where a and b vary with T, has also been deduced [21]: tM=aJ^

(1.2)

-21.0

160 h E c (/) o c o

120 h

80

40

15

-27.Oh

30

60

Nitridation -6.0

-5.0 -4.0 -3.0 Log Equilibrium P N ^

180 time (min)

-2.0 (atm)

Fig. 1.12 - Calculated stability field diagram for the Si-O-N system. In the diagram P(N2) varies fr-om 10'^ to 10'^ atm while P(02) varies fi-om 10'^'^ atm to 10'^^ atm. (After [24] modified). Fig. 1.13 - The thickness of silicon nitride layers thermally grown (unassisted) in NHs is plotted versus log(t + l)for the following growth conditions: T = 1200 CP, 1250 ®, 1300 (3)orl350°C ®andP(NH3) = 101 bar. (After [143] modified).

Silica, Silicon Nitride and Oxynitride TItin Films

37

Assisted growth During the later stages of plasma-enhanced nitridation in NH3, growth appears to follow a diffusion-limited process in which the active nitrogen from the plasma plays an important role. It seems that a diffusion model of the Deal & Grove type [10a] fits well the experimental results [93, 144]. A characteristic diffusion length L of the nitriding species is defined in order to explain the observed saturation effects. If the film thickness tN is less than L (L « 1.0 nm at 1200''C), a Deal & Grove-like model is valid, whereas saturation occurs if tN exceeds L [144]. In the case of anodic plasma-nitridation, substrate bias plays an important part. In this case the growth rate of nitride films is found to be quite independent of the partial pressure of the nitriding gas. A linear growth model has been proposed for growth in N2 plasma [47] and a diffusion-limited model has been proposed for growth in NH3 plasma [119]. The introduction of a fluorine-based catalyst (e.g. SFg, CF4, NF3) inside the reactor is found to enhance the growth rate [92-95]. Film thicknesses of about 100 nm have thus been grown after 4 h at 600°C (N2 plasma) using such a catalyst [93]. 3.2.4. Growth mechanisms How thin (< 10.0 nm) HP nitride layers grow is not fully understood yet. During the early stages, both for "natural" and plasma-enhanced growth, film growth seems to follow a reaction-limited process up to a thickness of 3 nm, since it is rapid and uncontrollable. During nitridation, nitrogen atoms are thought to saturate the voids in the silicon lattice [173] giving rise to a distortion of the crystalline array of Si (which, in turn, eventually contributes to the diffusion of Si atoms from the substrate up to the nitride layer). Nitride growth in NH3 is observed to be faster and better controlled than when using molecular nitrogen. The hydrogen produced by the reaction is assumed to eliminate oxygen contaminants from the substrate [19] via the following reaction. Si02 + H2 (g) -^ SiO (g) + H2O (g)

(1.3)

Under thermodynamic equilibrium conditions, the most favorable nitridation reaction of Si with NH3 should be [154, 189-190] 3Si + 4NH3(g)'^Si3N4

+ 6H2(g)

(1.4)

the standard free-energy changes for this reaction being given by [132] AGO = -126-3.2

X 10-^ T (in kcal/mole)

(1.5)

More detail about the transport and exchange mechanisms at work during the HP nitridation of Si in gaseous NH3 can be found in Chap. 7 of this volume. Although the nitride films thus produced are thin, isotopic tracing techniques have shown that nitridation proceeds via the transport of NHx species through the growing film. This transport is accompanied by complex exchange mechanisms affecting both N and H atoms. In the case of plasma nitridation studies, the characterization of the plasma itself is practically never reported. How the charged particles from the plasma interact with the growing film has not been (to our knowledge) studied up to now. The saturation effect observed when the plasma-assisted thermal nitridation of silicon is carried out over a long period, is attributed [81] to sputtering artifacts in the growing film.

38

B. Balland and A, Glachant

4. PROPERTIES OF TfflN THERMAL NITRIDE FILMS Thin thermal nitride films possess physical, chemical and electrical properties which are strongly affected by the presence of impurities and defects. We next review some of these properties. 4.1. STRUCTURE

In microelectronics, insulating layers cannot be used unless they are amorphous. Thermal nitride films are amorphous provided: - that the substrate is perfectly clean before growth, - that the growth ambient is perfectly controlled (i.e. that the amount of water vapor and oxygen is extremely reduced), - that the nitridation time is not too long. If all these growth conditions are met, uniform and amorphous films can be obtained by thermal growth [20] with properties which are superior to those of CVD nitrides. Figure 1.14 summarizes the conditions under which either a crystalline or an amorphous thermal nitride film is obtained. Let us note, however, that if the growth process is plasmaassisted, amorphous films can be obtained at much lower temperatures (T<900''C) [99, 153]). 1000

I , *

0)

o

^ L

100

-

s

Smooth

"

flC

1

. S m a l l Spots ^ ^ i ^ ^ ^ * •..

^ 0

°\

1

1

-e 1

1200

1250

1300

^

10

O

—

j ^

Fig, 1.14 - Illustration of the structure of nitride films grown in N2 at different temperatures and for different nitridation times: in a "dry" ambient ([H2O] < I ppm, [O2] < 0,1 ppm). Experimental data points are indicated

[ 0 ^ <0.1 ppm

: 8\i Js^**

S E c o

[H 2O] < 1 ppm

Crystalline

^

1

(0, A, *). The continuous line f—j separates the process conditions which yield amorphous films from those which yield crystalline films, (After 20 b] slightly modified).

Temperature f'C)

If the reaction environment contains substantial concentrations of impurities (e.g. water or oxygen) [20], the obtained thermal films are neither uniform nor amorphous but usually possess the following features [142-143]: - the films appear highly faulted and faceted under the microscope, - their polycrystalline nature is revealed by sharp IR absorption peaks, characteristic of the a and p forms of Si3N4 (as visible in Fig. 1.15), - their physical appearance is dark but transparent with some interference colors, - their optical refractive index exceeds that of amorphous nitride films (i.e. n > 1.9).

Silica, Silicon Nitride and Oxynitride Thin Films

39

60 h

Fig. 1.15 - IR transmission spectra of thermal silicon nitride films prepared under different conditions: P(NH3) = 1.01 bar; (Z t) = (1350''Q 18 min) (Z>, (1350''C, 60 min) ® or (ISSO^'Q 180 min) 0. (After [143] modified).

I 40

20 r 500

1000 \/X (cm-1)

1500

4.2. OPTICAL REFRACTIVE INDEX

The optical refractive index of silicon nitride films depends on the nitrogen content [75a] and index values in the 1.5-1.9 range have been reported [81]. For thermal and for plasmaenhanced nitrides, the index value is unaffected by the anmionia pressure (as illustrated in Fig. 1.16) and depends very little on the nitridation temperature (Fig. 1.17). The index values are very close to that of stoichiometric Si3N4 (i.e. n = 1.9). The highest values have been measured for films formed at the highest temperatures or for the longest nitridation times.

2.0

~*-

..^

*--

C

I

1.5

Fig. 1.16 - Optical refractive index versus pressure for thermal nitridation in NH3 at lOSO^'Cfor 100 minutes. (After [20 b] modified).

NH3

o 2

.1050°C 1n —1 0.1

1—

1.0

1 1

10

Pressure (mbar)

Refractive indexes ranging from 2.0 to 2.3 have also been reported [79, 85, 92], but could be due, as discussed before, to an excess of Si in the film [163]. This is not the case for films thinner than 10 nm. Figure 1.17 b shows how the refractive index, and film structural properties (such as density and [N]/[Si] ratio), typically vary with the substrate temperature and with the RF power density.

40

B, Balland and A, Glachant 2.2

P J-^

n X

2.9

KA,,

2.1

CO

E

c 2.0 o > o 1.9

2.5

/ ^

CO

o Q:

^

1.8

i N/Si

Temp 350°C . 1.

1.7 250

300

Temperature

350

1ii

c o o

J 2.1

i

0.5

1-5 Power

(^'C)

J

(0

(W/cm^)

Fig. 1.17 - The optical refractive index (n), density (p) and composition ([N]/[Si] ratio) of thermal nitride films are plotted: (left), as a function of substrate temperature during growth, (right) as a function of RF power density during growth. (After [163] slightly modified). 4.3. ETCHING CHARACTERISTICS

Nitride films display a better resistance to chemical etching than thermal oxide films do. Using a buffered HF solution (7:1 HFiNH^F at 24°C), the following etch-rates* have been reported: 2.5 nnfi/min for a (microwave) plasma-assisted thermal nitride grown at 800°C [92]), 2-3 nm/min for a "non-assisted" thermal film grown a 1200°C [137] and 1 nm/min for a plasma-assisted (RF) nitride grown at 1050°C [80]). These values should be compared to etch rates of 60 nm/min typically found for thermal silica [164]. As illustrated in Fig. 1.18, resistance to etching increases rapidly when the nitridation temperature exceeds 600°C and becomes then constant for Tnit > 800°C. When nitridation is carried out below 800''C, such films probably consist of oxynitrides, whose oxygen ratio increases as the nitridation temperature falls. 60

E 40

I

h Fig 1.18 ' Etching rates of thermal nitride films (in a solution of 7:1 HF:NH4F at 24''C) are plotted versus nitridation temperature. (After [20 d]).

c

s

20

H

CO

cc JZ

o

ill

*

300 600 900 Nitridation Temperature {°C)

1200

The etch rate was determined by dividing the initial film thickness by the time required to complete etching.

Silica, Silicon Nitride and Oxynitride Tliin Films

41

4.4. RESISTANCE TO OXIDATION

The resistance to oxidation of nitride films has been particularly studied because these films are used as masks to perform local oxidations (see the LOCOS process). Amorphous nitride films exhibit oxidation rates which are generally much less than those reported for thermal silica films [20, 98, 144, 154, 165]. The oxidation of a nitride features an initial stage during which the growth rate of the oxide is very small, followed by a second stage during which the growth rate reaches that of Si02 on Si [137]. When the oxide thickness is plotted versus oxidation time, the duration of the initial stage (tor) serves as a characteristic parameter used to measure how well the nitride film resists oxidation. This resistance depends both on the previous conditions of nitride growth (in pure NH3 ambient or not), on the oxidation conditions (dry or wet) and on the oxidation temperature.

E

1

^'<''

,x y

c 0)

c

I— 100h

1 ^jxr

L

10h u.

^

,-*

.x'-""'

«

®->: ;

i

--140 1 E 1 T = HOO^C / £3 ^ P ! S 100 "

s '

n

i ; i \

1

4)

(

1

c

£ 60

t 1

E

1 1

' /

p

^

20 1 1 10

I 1 100 1000 Oxidation time (min )

r

0.5

1

i

1.5

i

1

2.5

1

1

\

3.5

Oxidation time (h)

Fig. 1.19 - (left) Resistance to oxidation (m) of a film obtained by the nitridation of Si under various NH3 partial pressures (1 to 5.10^ mbar). Oxidation was carried out at 1000°C in an O2 ambient. The reference line (-X-) corresponds to the oxidation of pure silicon. (After [154] slightly modified). Fig. 1.20 - (right) Illustration of the oxidation rate (in dry O2 at llOO^C) of two thermal nitride films: one grown in 5% NHs-95% Ar (a) and one grown in 100% NH^ (m) (in identical nitridation conditions (time, T)). (After [137] slightly modified).

4.4.1. Resistance to dry oxidation Values of 10^ min have been observed for tor before oxidation talces place, as illustrated in Fig. 1.19 [154]. This value has been found to be independent of P(NH3) in the 1 to 5.10^ mbar range. This result does not however confirm a previous analysis [137] showing that resistance to oxidation strongly increases when the thermal nitriding step is achieved using a 100% NH3 ambient father than a 5% NH3 - 95% Ar ambient (Fig. 1.20). Moreover, in this previous work, it was shown that the oxidation resistance increases also with nitridation time (Fig. 1.21 a) and temperature (Fig. 1.21 b).

42

B. Balland and A, Glachant 20

/

10

/

^

virgin Si wafer

16

_/ • /

(0

in

/

^ 1 2u o

4

r"

E iZ

./^ '^ /

8 r/

/ /

/

/

y

/

/

/

/ f

/

/

/

/

/

i

^16

w -. ^

•

/

1

0) 1 2

/

0

c

^

0

'f

•c •' 1 1 1

1 1

E

/

Oxidation in O2 at T = 1100*^0

i

J1 4

], - ^ - ' - ' ' - ' : 1

k: ' ^ ^ 0.4

* - - ^ 1... 1

1.2

/V

I

I

I

2.0

I

^

i

l;

'

/

4

;

^ V

''L^'<^1,'-^

!

2.8

0.4

Oxidation time (h)

1

'

/ /

'

- / "

4

.° '

1

-t^/ /i

;

/ /

//

''^

8

1

1/

^

/ / / / '^ ^ / ^''^ / ^ / ' / ' / / ,/ ' /' /

c

•

/ «

/

virgin ^ Si wafer—^' ^^

,^- /^ 1

^

/ d

A 1

/ /

240

/

''

,0

/

•

-

/

/

10

4,0

/ /

Oxidation in 0 2 at T=1100°C

1.2 2.0 2.8 Oxidation time (h)

Fig. 1.21- (left) Illustration of the resistance to dry oxidation of nitride films grown at the same temperature for various lengths of time, in a 5% NHs-95% Ar ambient, for 10 min (A), for 40 min (O), for 240 min (O). (right) Illustration of the resistance to dry oxidation of nitride films grown at different temperatures for the same time (40 min) in a 5% NHs-95% Ar ambient: at 900°C (m), 1000°C (A), llOO^'C (O), 1190°C. (O). (After [137] slightly modified). 1

1

I

•

1 —

1 Dry O2 Oxidation

1 ^* •

[

iooq;,G--

••

1 4 k [ ,----•

1

^ * **

1

\,

'^ll«.-—""r050°C

2 h

h

1154^0 1

—

.

5

—

—

1

6 Nitride

1

7 thicl
. J

8 (nm)

1

1

9

10

Fig. 1.22 - The resistance to oxidation, measured through tor* of a thermal nitride film is plotted as a function of film thickness for various (dry) oxidation temperatures. (After [144] slightly modified).

The value of tor varies also linearly with the initial thickness of the nitride layer [144] as illustrated in Fig. 1.22. It strongly decreases when the oxidation temperature increases from 1050X to 1154X as illustrated in Fig. 1.23. It has been proposed [144, 164] that the oxidation kinetics of a nitride film obeys a linear parabolic law of the Deal & Grove type [10 a].

Silica, Silicon Nitride and Oxynitride Thin Films

43

\ 40

^

-

30

q

% \

SI

\

t 20 o •^

-

Fig. 1.23 - Dependence of tor ^^ the oxidation temperature The nitride film has originally been obtained by exposure of Si to 100% NH3 for 90 minutes at llOO^'C. (After [137] slightly modified).

\

\

N

\ "o

V

10

"""-^ •

900

1000

^ - T > - 0 |

1100

1200

Temperature of oxidation (^C) Si3N4 + 302 -^ 3 S i 0 2 + 2 N 2

€0 O

>. - 3 0 0 0)

Fig. 1.24 ' Free energy is plotted as a function of temperature for three types of conversion of silicon nitride into silicon dioxide. (After [164] slightly modified).

S i 3 N 4 + 6 H 2 0 - > 3 S i 0 2 + 6 H 2 + 2N2

c

S -200 CO

I -100

Si3N4+6H20->

3Si02+4NH3

CO

JL

1000

1200

1400

1600

1800

Temperature

(K)

Figure 1.24 shows the reactions of conversion which are effective at high temperature. The conversion of silicon nitride into silicon dioxide has been carefully studied [137] and has revealed that: - the film is homogeneously oxidized, although oxidation tends to be more thorough at the surface; - three different modes of oxygen incorporation in the nitride film can be defined before tor is reached, depending on the value of the composition parameter ([N]/ ([N]+[0]) of the film as illustrated in Fig. 1.25: 1/ For a composition parameter greater than or equal to 0.2, a quick substitution of N atoms by O atoms takes place and the nitrogen atoms are removed from the film. This substitution process takes place homogeneously throughout the film thickness and the oxygen is practically completely consumed during this process.

44

B, Balland and A, Glachant

II For a composition parameter below 0.2, the N -> O substitution slows down. Between 0.1 and 0.2, the film composition is modified very slowly and oxide growth begins due to a slow diffusion of oxygen through the film up to the nitride/silicon interface, where oxygen atoms react with the silicon substrate. 3/ A fast oxidation regime appears when the composition parameters is less than 0.1. The lowering of the nitrogen concentration could then be the result of either a loss of nitrogen or a simple dilution. The remaining nitrogen fraction is estimated at less than 0.01 for t = tor-

o

o 4 - 100% NH3, 90 mn (5 nm)

?

60 •4— 100% NH3. 40 mn (4 nm)

X

O 1*

z

^^—

5 % NHo. 60 mn (4 nm)

\ V0J6.I nm) 2 0 - \ ^ ^->~~.^(6.7 nm) X ( 9 nni)

- - Bi-..

^-----.^^ 1

0 0

1

•

40

y

(35 nm) T~ - A

60

1

1

^ - , ( 2 0 nm) 1

1

1

1

80 100 Oxidation time (mn)

Fig, 1.25 - Composition parameter [N]/([N] + [O]) is plotted vs oxidation time for various thermally-grown nitride films when oxidation is carried out in dry O2 at llOO'^C. As discussed in the text, three stages of oxidation are distinguishable. (After [137] slightly modified).

4.4.2. Resistance to wet oxidation As illustrated in Fig. 1.26, the resistance of a nitride to wet oxidation is considerably less than that observed for dry oxidation [137, 164]. At 1050°C or above, the nitrided siHcon wafers do not show any measurable resistance [137]. Even for strongly nitrided films (Fig. 1.26 a), the tor value for wet oxidation is only 0.5 h at lOOOX and about 3 h at 900°C, which is considerably less than for dry oxidation (see Fig. 1.22). 4.4.3. The LOCOS process The LOCOS (LOCal Oxidation of Silicon) process is based on the selective oxidation of silicon using a silicon nitride mask as illustrated in Fig. 1.27 [71]. One of the problems encountered in the selective oxidation of silicon for the production of an embedded field oxide (EFOX), as illustrated in Fig. 1.28, is the unintentional oxidation of silicon under the nitride mask. The transition region from thick to thin oxide (also called bird's beak) consumes about 1 |Lim of space, sideways.

Silica, Silicon Nitride and Oxynitride Thin Films 120

T

T

IT *? 253 nm

I 100

r

r o 11 1190*0 1 ^ 1 1 OO'^C OOO'C I o 10

1 at 5h

^ 80

Fig. 1.26 - Illustration of the resistance to oxidation of thermal nitride films. Comparison of dry and wet oxidation characteristics for nitride films grown in pure NH3. (After [137] slightly modified).

900°C

I 60 40

J !

I

I 20 v> k^^/^rrr-'^r^^'i-

4

6

8

10

12

45

14

16

a) Resistance to dry oxidation at various oxidation temperatures of nitride films grown in pure NHj for 90 min at 1100°C.

Oxidation time (h)

E 120 c 100

1 |224 nm 1 1000°C ] ^ in O2 gas through ' boiling water

(0

o c o

80 -

60

20

'

-2-^-.^-.. 0.4

b) Resistance to wet oxidation at two oxidation temperatures of nitride films grown in pure NHs for 16 h at llOO^'C.

9oo°c ; in O2 gas through-^/ boiling water /'

'

40

1 / <

_-^

1.2

----2.0

^ 2.8

3.6

Oxidation time (h) Si3N4

KOH etch t^WkViiVywWWVVVVWkVaiVW : .

Fig. 1.27 - Illustration of the LOCOS process: (upper) preferential etching of silicon using KOH, (lower) formation of the field oxide. (featuring the bird's beak effect). (After [71] modified).

-^—SiO.

Si Si3N4

SiO.

bird's beak

Figure 1.28 shows the cross-section of an EFOX structure fabricated using a 7-nm-thick thermal silicon nitride as the oxidation mask. The substrate has been oxidized in wet oxygen (H2O; 80°C) at 1000°C to obtain an EFOX thickness of 0.75 |xm.

46

B. Balland and A, Glachant Thermal nitride 7nm Poly-Si Fig. 1.28 - Schematic cross-section of an EFOX pattern fabricated by means of a thermal nitride mask (After [161] slightly modified).

The problems related to the growth of field oxides are lateral oxide encroachment (field oxide loss, stress), the generation of stress-induced defects in silicon (dislocation generated in the substrate under the mask), poorly controlled impurity redistribution, the Kooi-effect and surface planarity [72]. Moreover, it has been shown experimentally that the high level of stress induced during the oxidation process results in a higher defect density and thus in higher leakage current, as well as oxide integrity problems. A good knowledge of the stress level is therefore a prerequisite to the development of a reliable technology. Stresses arise during oxidation because of the volume expansion accompanying the oxidation process. When the nitride layer is placed directly on the silicon substrate the shape of the bird's beak not only depends on the orientation of the wafer, but also on the orientation of the nitride mask. Si02 (field oxide)

Si^Nj

1.2

Lbb tfox

a)

® ® q '\

1.1

b) X'4 Fig. 1.29 - Bird's beak configuration: a) typical cross section of a bird's beak - b) the ratio of removed silicon thickness (tsi) to field oxide thickness (tfox) ^^ plotted as a function ofx c) the ratio of the bird's beak length (Li^ij) to the field oxide thickness (tfox) ^^ plotted as a function of the oxidation temperature for several wafer orientations and oxidation pressures: (DP = lOatm, orientation = (100) c) ®P = 1 atm, orientation = (100) (S)P = lOatm, orientation = (111) ®P = 1 atm, orientation = (111) (After [74] slightly modified).

1.0

0.9 \-

920

960

1000

Temperature (X)

Silica, Silicon Nitride and Oxynitride Thin Films

Al

To releave stress and to prevent the direct contact of Si3N4 with Si, a buffer oxide is used, as illustrated in Fig. 1.30. However this buffer oxide furthers oxide encroachment. In addition, nitrogen species due to the reaction of the top nitride layer with the H2O ambient, diffuse through the buffer oxide to form Si3N4 at the Si02-Si interface (Kooi-effect). Si O 2 (field oxide)

^i 3 N 4 (nitride patcli)

Al

P+

i^^

Bird's beak

^ SI P substrate

Si0 2 (buffer oxide)

Si (field Implant)

Fig. 1.30 - Illustration of how the growth of the field oxide is masked by the nitride patch. The buffer oxide under the nitride helps lower the stress on the silicon surface. The nitride is removed after this step. (After [71] modified).

The ideal buffer dielectric (or masking dielectric) is a material which can prevent the diffusion of NHx species, resist oxidation and can easily be removed to leave a virgin surface. By using nitride films produced by PECVD or by implantation of nitrogen ions, the problem of lateral oxidation has been considerably reduced. A comparison of the local resistance to oxidation of ni{ride films formed by means of LPCVD, PECVD and nitrogen can be found in [166]. 4.5. RESISTANCE TO IRRADIATION

The irradiation of amorphous dielectric materials has two consequences: the creation of structural defects (displacement damage) and ionization phenomena. Numerous studies ([167] and references therein, [162, 168]) have been devoted to the surface damage produced by an ion, or an electron beam, in amorphous thin films. Si02 has been shown to offer a resistance to ion or electron bombardment, which differs from that of Si3N4 or silicon oxynitrides. When the energy of impinging Ar ions increases from 1 to 5 keV, the surface damage of Si02 increases, but that of Si3N4 diminishes. On the other hand, increasing the electron fluence up to 5 x 10^^ cm-^ (electron energy = 2 keV) [167] results in both cases in an increased surface damage. The damage produced is measured by detecting the uptake of the Si(LVV) Auger transition (kinetic energy E = 89 eV) characteristic of the formation of Si-Si bonds in the irradiated insulator. The irradiation of A^/Si3N4/Ti MIS structures with 10-keV electrons [168] has shown that the electron-induced current in the nitride saturates at relatively low electric fields, while similar investigations performed on MOS devices have concluded that the corresponding current in the oxide never completely saturates even at fields of 5 x 10^ V/cm. These results suggest that a strong electron-hole pair recombination mechanism (of the geminate and/or of the columnar type) takes place in silicon nitride [168].

48

B, Balland and A, Glachant

MIS structures using very thin nitride films have also been found to offer a good resistance to high doses of photons and/or heavy ions [169]. The flat band voltage shift remains below 500 mV, for applied electric fields in the -1 to +1 MV/cm range, and, irradiation doses of 2 Mrad. Under irradiation, the C-V curves shift without deforming, thereby indicating that the interface state density does not change appreciably. 4.6. RESISTANCE TO IMPURITY DIFFUSION

Silicon nitride films exhibit a much better resistance to the diffusion of impurities, than thin silica films do. Figure 1.31 shows an example of the masking effect of thermal nitride films. The concentration of phosphorus atoms which have diffused through the thin (< 10 nm) nitride layer is found to be four orders of magnitude smaller than that obtained for silica [20]. A thermal nitride film, only 4 nm-thick, covering the gate insulator of an IGFET is also an effective barrier against the doping impurities diffusing from the gate electrode into the channel region.

Fig. 1.31 - Illustration of the masking properties of silicon nitride films. The concentration profile of phosphorous atoms diffusing from a PSG film (and measured through the concentration of free carriers as a function of depth) is given in four cases: when silicon is not protected, and when silicon is protected either by a thin silica layer (6.6 nm) or by a thin nitride layer (3.4 and 9.2 nm). (After [20 b] slightly modified).

0.2

0.4

0.6

Depth from surface (mm ) 4.7. THE MAIN IMPERFECTIONS OF THE SILICON NITRIDE-SILICON SYSTEM

In a near-perfect stoichiometric amorphous nitride, the Si atoms are linked to four N atoms in a distorted tetrahedral arrangement while the N atoms are linked to three Si atoms in a nearly planar trigonal arrangement. The structure is amorphous when the interatomic distances and the bond angles are randomly distributed around the values encountered for the crystalline structure [170-172]. 4.7.1. Defects associated with non-stoichiometry When silicon nitride is non-stoichiometric, two kinds of dangling bonds appear: the silicon dangling bond (abbr: SDB, symb: =Si*), and the nitrogen dangling bond (abbr: NDB, symb: = N*). Moreover, when Si is in excess, = Si-Si = bonds are also encountered.

Silica, Silicon Nitride and Oxynitride Thin Films

49

4.7.2. Defects associated with hydrogen Just like in amorphous silicon, hydrogen may passivate dangling bond by forming = Si-H and = N-H groups, but an excess of hydrogen can also create defects by distorting existing bonds. The concentration of chemically bonded hydrogen varies, depending on the nitridation process: from 4-10 at. % for HT thermal nitrides to 30 at. % for LT plasma-assisted thermal nitrides. Nitrogen dangling bonds are more readily hydrogenated since the bonding energy of N-H is larger than that of Si-H. The annealing of silicon nitride in N2 at 700°C [124] causes dehydrogenation. This treatment gives birth to dangling bonds (by breaking the H bonds) and induces a densification at the same time. The out-diffusion of hydrogen leads to a degradation of the electrical properties. Conversely, annealing in hydrogen can, to a certain extent, reintroduce hydrogen atoms in the nitride and thus reduce the concentration of SDBs and NDBs. 4.7.3. Defects and introduced energy levels To sunmiarize, the following defects have been identified in silicon nitride: = Si% = N*, = Si-Si =, =Si-H and =N-H. The concentration of these various defects depends, along with stoichiometry, on the growth process used. The presence of these defects influences the electrical properties of the nitride depending on the type of energy level and state they introduce in the gap. If the level is close to a band edge, or to a band edge tail, it contributes to the conduction mechanism. If the level introduced is deep in the gap, the defect contributes to the memory effect. A large concentration (1018 to 1019 cm-3) of carrier traps associated with these defects is usually found distributed throughout the nitride bulk. • SDB The SDB possesses one unpaired electron. It can either lose this electron or capture another one of opposite spin. Therefore it exists under two forms: = Si" and =Si^. The = Sidefect is responsible for a peak in the distribution of states near midgap, at Ey + 3.6 eV. It possesses two possible charge states (0, -) and traps electrons. The = Si^ defect introduces states in the gap at Ey + 3.1 eV. It possesses two possible states of charge (0, +) and acts as a hole trap because it lies energetically close to the valence band tail. The distribution of states introduced by SDB's is illustrated in Fig. 1.32. • NDB Likewise, the NDB exists under two forms labelled: = N~ and = N°. The = N"" defect gives birth to a state located at the top of the valence band. The = N" defect is responsible for a valence band tail about 1.5 eV wide, visible in Fig. 1.32. The =N" defect possesses two possible charge states (-, 0) and acts as a hole trap. It is charged when empty. • = Si-Si = The a bonding state of the = Si-Si = defect is found to lie in the gap, at about Ey + O.l eV while the a* anti-bonding state is in the conduction band. Consequently this defect only gives rise to a narrow valence band tail, about 1.5 eV wide.

B, Balland and A, Glachant

50

The neutral = Si-Si = centers play an important part in the hole conduction mechanisms. • s Si-H The a (bonding) and a* (anti-bonding) Si-H states lie outside the gap, which explains the passivating action of hydrogen. • = N-H The states corresponding to this defect also lie outside the gap. • Si-N bond Due to stresses existing in the random network of silicon nitride, the Si-N bond is strained. It can lead to a more complex situation than the simple creation of a couple of one SDB (= Si*) and one NDB (= N*).

rio^^ E

u « 10^°

-

0) ft

^ 10

.-'

\Si-Si

'

V

A A

'<0

§ 16 Q 1 0

/

1

18

—

' =N-\

1

1

u

1

V 1 2

Ny .\ 3

4

5

i

• Ev

Energy

(eV)

Ec

Fig. 1.32 - Distribution of energy states introduced in the band gap of silicon nitride by bulk defects. (After [170] slightly modified).

AHA. Impact on electrical properties • On electrical conduction Hole conduction dominates in silicon nitride (while electron conduction dominates in silica). For low electric fields, conduction in silicon nitride is due to holes hopping from shallow traps (energetically located in the valence band tail), while electrons are trapped in very deep = Si" centers. (= Si* centers also act as traps in Si02 and should hamper electronic conduction, but their density in silica - typically IQl^ cm-3 - is much smaller than that in silicon nitride - typically 10^9 cm-^). • On memory effects SDBs and NDBs are the defects most likely to contribute to the memory effects, although authors disagree on their respective role (see Chap. 5 of this volume). Because of its amphoteric nature the SDB acts in MNOS devices as a long term (memory) trap. It is located deep in the nitride gap and is energetically aligned with the gap of Si. SDBs trap either electrons or holes during the writing phase and release them during the reading phase [34].

Silica, Silicon Nitride and Oxynitride Thin Films

51

4.7.5. Defects induced in the silicon substrate The concentration of stacking faults in the silicon substrate is found to decrease during the thermal nitridation of silicon [173, 175]. It decreases linearly with nitridation time at a speed which increases with the NH3 pressure in the reactor. This effect could be due to a reduction in the concentration of Si interstitials close to the silicon surface, caused by a diffusion of Si atoms from the Si3N4-Si interface towards the nitride surface. The diffusion of P and B atoms in the bulk of silicon is found to be retarded during the nitridation of Si because of the depletion in Si interstitials which takes place [174, 176] (see § 5.6 and Fig. 1.52). 4.8. ELECTRICAL PROPERTIES OF NITRIDE FILMS IN M N S STRUCTURES

The electrical characteristics of nitride films presented next are derived from studies of the MNS (Metal-Nitride-Silicon) structure. They include the properties of the Si3N4-Si interface, the breakdown voltage, the dielectric constant and the electrical conductance. Correlations between electrical characteristics and growth conditions are also discussed. 4.8.1. Dielectric constant The dielectric constant of Si3N4 usually quoted is £r = 7.5 (see Table 1.04), but this value depends on the preparation conditions (i.e. cleanliness of the Si wafer before nitridation and purity of the nitriding gas, temperature, composition, etc.). The presence of silicon inclusions in the film increases 8r and brings it closer to the dielectric constant of silicon (£51 = 12). 4.8.2. Dielectric charges The C-V characteristics of MNS structures are very stable and show no hysteresis loop even when submitted to voltage stresses of ± 5MV/cm. Dielectric "charges" nethertheless exist in the Si-Sic^N4 system. E 10

\\

12

1

- 1 N = 7.5 nm

® -- - 1 N = 9.4 nm > 0

10

joA

*f/ i Ji h P

11

m

I

10

. *•* • • • • J * ' * ' ' " " •

10 •

•0.2

1

1

0.0

0.2

1

1

0.4

1

I

I

0.6 Surface potential (V)

0.8

Fig. 133 ' The density Dit of interface states in the band gap of silicon nitride is plotted versus surface potential as determined from quasistatic C-V measurements. (After [20 a, 172] slightly modified).

B, Balland and A, Glachant

52

• Interface states caused by the discontinuity of the silicon lattice at the interface have been reported with a density in excess of IQl^ cm^/eV as illustrated in Fig. 1.33 [20, 172]. • Fixed positive charges caused by the non-stoichiometric [Si]/[N] ratio at the interface, have been reported with densities of about 5 x 10^ cm-2 [21, 171]. Although this value is relatively high, its contribution to the threshold voltage is rather small, due to a very large gate capacitance. • Bulk trap densities of about 10^ ^ cm-2 have been measured [21, 171]. • Mobile ions such as Na+, K+ and H+ have little impact [66-67] in a nitride layer because of the blocking effect of the nitride network. 4.8.3. Breakdown voltage The breakdown voltage of the nitride films can be measured by biasing the MNS structure in the accumulation mode. Breakdown occurs when the leakage current reaches an abnormally large value. Breakdown fields ranging from 6.5 MV/cm [85] to 20 MV/cm have thus been measured [27, 146]. The dielectric strength is found to increase with increasing substrate temperature and RF power density during nitride growth. When as-grown films are annealed at 700°C in N2 the dielectric strength decreases and the leakage current increases 50 to 100 times. Before final breakdown to destruction, the film allows a large current, of density 10 mA/cm^, to flow. 4.8.4. Electrical conduction Electrical conduction in thin nitride films has been studied using I-V recordings (see Chap. 5 of Vol. 1 for more details on I-V techniques). Since the gap width of Si3N4 is smaller than that of Si02, one expects and observes higher leakage currents in MNS devices than in MOS devices. Figure 1.34 shows the typical leakage current characteristics of a thin nitride layer [135].

Fig, 1.34 ' Leakage current flowing at room temperature through a IS-nm-thick plasmagrown nitride film. (After [135] slightly modified).

10

11

12

13

14

Applied voltage (V)

Silica, Silicon Nitride and Oxynitride Thin Films

53

The linear parts of the Log J(A/E ) characteristics observed at high electric fields (see Figs. 1.35) shift rightwards for samples produced at increasing substrate temperatures (as shown in Fig. 1.35 a) and RF power densities (Fig. 1.35 b) [124]. The linear relationship observed between Log J and V E in the higher field region suggests that electronic conduction in nitride films is either controlled by Poole-Frenkel emission or by Schottky emission (see Chap. 9 of Vol. 1 [lOe]) whose equations are recalled next: J Pf = CEexp

(Poole-Frenkel emission)

kT

^^o^d 1/2

/ ^ = AT exp

kT [ ^

(Schottky emission)

ne^Sd

where: C is a constant which depends on the trap density, A is the Richardson coefficient, O B is the Poole-Frenkel barrier height (obtained from an Arrhenius plot of the leakage current for a constant electric field strength such as that of Fig. 1.36 a), O'B is the Schottky barrier height, E is the electric field and 8o and £d are respectively the permittivity of free space and the dynamic dielectric constant of the nitride (calculated using I-V characteristics).

E o <

/

F(b)

(a)

-^ -^ Ao 1

;

10

/ ' / ," A A / / /

in

.'^

c o

A

X3

K

/ / / / / /

l

/

J

• Temp. C*C) as-grown/ annealed 250 a 300 ^ 350 o «

•

/

1 1

L

i1 1 1

1

,

I

,

,

,

1

1 I 1

' 1

ni

/ a

L

/1

1 '

f

1

'

0

1

i y» A.'

1

L.

I

t

i 1

3

t

P A% ^

7

[•

L A

.^•°

^

4k

c 10 8 o O

,°AiA^

/ /

' 1

1

1

I 1

'

'

1 1 '

1

M. I 1

•A ^*'Power (W/cm ^ ) ^ * as-grown/annealed

n -A • Q ''^ Jk -J

0.51 0.85 1.19 1

n -^ 0 1

• 1

1

(Fleld)^ ^2 po ^(V/cm) ^ '^ \ Fig. 1.35 ' The current density flowing through thin nitride films is plotted as a fiinction of the electric field strength for several samples: (a) samples grown and annealed at various temperatures and (b) samples grown and annealed at 350°C for various RF power densities. (After [177] slightly modified).

The Arrhenius plot of the leakage current is illustred in Fig. 1.36 a and indicates that electronic conduction in nitride films follows the Poole-Frenkel emission in regions both below and above 80°C. The change in slope, not fully understood, could correspond to a change in material structure. Constant 8^ decreases from 4.5 to 3.6 with increasing measurement temperature.

54

B, Balland and A, Glachant Temperature 150 100 -5

10

h

50 .^''

(""C) 25 H4.5 c ••H4.0 c(0

E o

o o

E -6 o1 0

\

<

\

C

o 35 1 0 c o ^

-8

3

o

-9

10


E

[- Temp = 350°C P = 10 W/cm2

o

C

1 h o

rff2.5

3.0

3.5 0.5

(a)

10 ^ /T (K ^)

( b)

1.0

Power density (W/cm

)

Fig. 1,36 (a) - Arrhenius plot of the leakage current flowing through a thin plasma-grown nitride layer for a constant electric field strength (E = 3.7 x l(PV/cm) (bottom) variation of the dynamic dielectric constant with measurement temperature (top), (b) - The dielectric strength of a thin plasma-grown nitride film is plotted as a function of power density, (after [134] modified).

4.8.5 Characteristics of short-channel MNSFETs • In the example given next, a nitride film with a thickness of 7 nm or 9.5 nm has been used in a "silicon gate" technology to fabricate n-channel MNS field-effect transistors (MNSFET) with higher performances. The resulting structure is shown in Fig. 1.37 a. The poly-Si gate electrode deposited on top of the nitride film can be fully doped since the thin nitride film acts as a perfect mask against diffusion. The channel length and width of the MNSFET are respectively 0.8 and 20 |Lim. The depth of the source and drain junctions is 0.4 |im, (junctions are obtained by a phosphorus diffusion from a PSG film). The resulting ID(VD) characteristics are shown in Fig. 1.37 b. (The negative threshold voltage of - 0.15 V is due to the relatively low acceptor concentration (3 1015 cm-3) of the substrate and to a film thickness of 9.5 nm. However, an enhanced mode of operation could easily be achieved). • A very large transconductance of about 2 |imho (2 juSiemens), calculated for a gate voltage of 1 V, and a drain voltage of 4 V, yields an effective electron mobility above 800 cmW.s. This practical application could be useful as a short-channel FET because a thinner gate insulator film, with a larger dielectric constant, is effective in eliminating the so-called shortchannel effects, and since it is thin, minimizes electron trapping. • The leakage current flowing through the gate insulator may be as small as that of a pn junction (see Fig. 1.38). Such acceptably small values of leakage current make these thin nitride films usable as DRAM capacitors.

Silica, Silicon Nitride and Oxynitride Thin Films

55

poly-Si Gate

Source

y///////A

Thermal Nitride As"*" Implanted p-Si{IOO) Fig. 1.37 - a) Cross-section of an FETwith an effective channel length of 0.8 fjm and using a thin nitride film as gate insulator, b) IDS (^DS) characteristics of the corresporuiing MNSFET (see text). (After [134]). 10

•8

I <

-10

r 10 S 0

10

10

-12

L = 3 |Lim

L W = 20 ^im L tN = 7.3nm r

-14

/•-VG<0

Fig. 1,38 - Typical gate leakage current of an MNSFET (After [134] slightly modified).

VG>0-Hh/^ 1

O

1

\

I

\ Z ±5

\

\ \

\1 ±10

Gate voltage (V) A.9. CONCLUSION

Good quality ultra thin (< 10 nm) nitride films can be thermally grown on silicon using a pure nitriding ambient. These films have a high mass density and display a good uniformity. Although their thickness is limited, their physical, chemical and electrical properties are of great interest. They are moreover free from instabilities caused by carrier trapping at the Si3N4-Si interface which are encountered with other types of nitride. Compared to other thin insulator films, thermal nitrides have attractive properties: • they have a large dielectric constant (which allows for a larger capacitance per unit area), • they behave as electrically stable chemical passivators, • they are good diffusion barriers (which is the basis of the LOCOS process). These unique properties have led to the production of a large variety of new devices of which we list a few below: • capacitors for RAM structures, using 20-nm-thick thermal nitrides [135], • MIS transistors with L^ff values of 0.5 |am, using a 5.3 nm-thick plasma-assisted thermallygrown silicon nitride film [20], • MIS switching devices, using a 3.5-nm-thick thermal nitride [144], • Si-FETs used in the address matrices of liquid-crystal display panels [111].

56

B. Balland and A, Glachant

5. SILICON OXIDE FILMS THERMALLY NITRIDED IN AMMONIA In order to take advantage of the passivating and masking properties of Si3N4, while retaining the excellent electrical properties of the Si-Si02 interface, several ways of nitriding silica have been developed. The idea is to convert the top (surface) layer of the oxide into a nitride-like structure while keeping the almost perfect Si02-Si interface. The obtained films display unique properties which we present next. 5.1. THE NITRIDATION METHODS

Silica layers can be nitrided by direct exposure to gaseous NH3 at high temperature (800X"1200°C) using high or low pressures of anmionia (HP: P(NH3)« 1 bar, [19-21, 152, 178-214], LP: 10-6 mbar < P < 10-1 mbar [215-221, 231-233]). The plasma-assisted nitridation (in N2 or NH3) of thin silica films is also possible [229]; typical process parameters being then: P - 10-2 mbar, RF power ~ 600 W, T - 950°C. By using either process, the top (surface) layer of the oxide turns into a more or less perfect silicon nitride. The film thus obtained is called a nitrided-oxide film (abbr. NO film). Finally, the nitridation of thin silica films is also possible using a Rapid Thermal Nitridation (RTN) process. This technique is described in Sect. 7. 5.2. THE HIGH-PRESSURE (HP) NITRIDATION PROCESS

For all practical purposes, the only ambient that allows the easy and controllable nitridation of an oxide is gaseous NH3. Gaseous N2 does react, to a slight extent, with silicon at the oxide silicon interface, but high temperatures (> 1000°C) and long nitridation times (several days) must be used to obtain a sizeable result. To study nitridation in NH3, long nitridation times associated with high temperature have often been used. For example, Pan [234] and Moshlehi and Saraswat [216] showed the characterization of nitrogen concentration in a 10-nm oxide film after a nitridation time of 2 h at 1200 X . Hayafuji and Kajiwara [85] worked at 1100 °C for 5 h and Chang [180] studied a 17-nm oxide film after a treatment at 1150 °C for 6 h. All these results show that with this Idnd of treatment, the nitrogen concentration is constant throughout the film thickness and ratio [N]/[N + O] is around 40%. From these many results, it is possible to find evidence that such parameters as ammonia pressure, nitridation time, and nitridation temperature have an influence on the nitrogen concentration in the oxide layer, but it is difficult to deduce the quantitative relationship between the preparation conditions and the nitrogen concentration. 5.2.I. A phenomenological description The thermal nitridation of Si02 leads to the substitution of oxygen atoms by nitrogen atoms coming from the nitriding gas. The nitriding species diffuse through and react with the silica film following complex mechanisms which we attempt to clarify below. The obtained results depend on the nitridation time and temperature and on the initial oxide thickness.

Silica, Silicon Nitride and Oxynitride Thin Films

*»

57

O(KLL) Si(LVV) »*

Fig, 1.39 - Auger in-depth profiles (arbitrary units) of NO films fabricated using different experimental conditions (oxide thickness = 20 nm). (After [177]y slightly modified) (1) Illustration of the influence of nitridation time tfor: T = 1000°C, P(NHs) = I bar. (a)t= 10 min, (b) t = 90 min

J=_ Sputter

time

(h)

Si

Si

.-••K

13

(b)

V-

s.-./ Fig. 1.39 (cont'd) (2) Illustration of the influence of nitridation temperature Tfor: t = 60 min, P(NH3)= 1 bar. (a) T = 800°Q (b) T = 7i(50°C

interface—t>l *

interface-

•J/

o

N

T /1\

\

• I•

t

# #

<

:^j^

0 (a)

!k:i 6 Sputter

•^•^*.

0

2

time

(h)

(b)

Figure 1.39 illustrates the influence of nitridation time and temperature. The in-depth concentration profiles of oxygen, nitrogen and siUca have been measured by Auger electron spectroscopy. Figure 1.39 (top) shows that for a short nitridation time (t = 10 min) and a thin oxide (t^x = 20 nm) nitrogen is encountered both at the silica surface and at the Si02-Si interface. As nitridation proceeds, [N] increases not only at the surface but also in the bulk, while [O] decreases accordingly. Figure 1.39 (below) shows that nitridation is more thorough when nitridation is carried out at higher temperature for similar nitridation time (which was to be expected). Figures 1.40 (1) and (2) illustrate the influence of oxide thickness. The in-depth profiles of oxygen, nitrogen and silicon show that the thicker the oxide, the smaller the amount of interfacial nitrogen. Figure 1.40 (3) illustrates that even a prolonged (6.5 days !) nitridation in pure N2 only leads to the incorporation of a small amount of nitrogen at the Si02-Si interface, which explains why, for practical reasons, NH3 is being used instead of N2.

58

5. Balland and A. Glachant

i^^)

^ 0

1 .-^"

interface->

^#-••"1 *'

"^

(3)

•••.^

^

• •

0

^

1

• ^>

3

•

• § • • • • aM •

%

•

1 1

11

.\ % %

SL

•

.- • • • • • •ta• • • # ^ •

1 V,.L?>t4.'-r—r 2 0 .2

8

(2)

,

V'

3

<

10

O Si i:*'

:v..•f--\

12 14 16

• 1 • •• 11 •'

•

,<

X. I \

1

!

interface\-H •*

N

'-•—»^

1 .•

interface«->| •

U«B*a««ai

1 •

1 v/

•1--I 1 J - ..-'ll--.*-1 i-^'*«-i""r' 24 30 Sputter time (h) ^

Fig. 1.40 - Auger in-depth profiles (arbitrary units) of NO films fabricated using different experimental conditions. These profiles reveal the influence of the initial oxide thickness: (1) 45 nm, (2) 119 nm (T= 1160°C, P(NHs) =1 bar); and the influence of the nitriding gas ambient (3): P(N2) = 1 bar (T=1000''Q t = 6.5 days, oxide thickness = 10 nm). (After [177] slightly modified).

5.2.2. Main features of the nitridation process A careful study [198] of how the [N] in-depth profile varies with short nitridation times (0.5-120 min) has yielded (see Fig. 1.41) the following information: (i) At the oxide surface The reaction is very fast leading to values of [N] « 6 x 1015 cm-2 for nitridation times below 15 min and, simultaneously, to a depletion of oxygen. (ii) In the oxide bulk [N] continuously increases with time, while simultaneously [O] decreases (thus confirming that an exchange reaction between O atoms coming from the oxide film and N atoms coming from ammonia indeed takes place [173]). (iii) At the SiOz-Si interface The nitrogen-rich species first react with interfacial silicon and form the nitrogen pile up. This step occurs well before any nitrogen is incorporated in the bulk oxide. The maximum of the nitrogen pile up is observed to shift towards the bulk oxide as nitridation proceeds. This shift has been attributed to a re-oxidation of the silicon surface (Si (100)) in the interfacial region by the oxidizing species produced upon reaction in the oxide bulk. Up to - 30% of these oxygen species could participate in the interfacial reoxidation.The remaining species are thought to diffuse through the insulator up to the surface where they escape in the reactor.

Silica, Silicon Nitride and Oxynitride Thin Films

59

I [N]

[O]

[Si]

0 Depth

Fig. 1.41 - Auger in-depth concentration profiles of [N], [O] and [Si] obtained for various nitridation times. (T= llOO^'C, PiNHs) = 1 bar, oxide thickness = 10-40 nm) (Dt = 30s ®t = 60s (E>t = 15 min ®t = 30min ®t- 60min @t= nOmin (After [198] slightly modified).

-20 (nm)

The nitridation of bulk Si02 is believed to be unaffected by the existence of macroscopic stresses which are intrinsic to the Si02-Si system [202], whereas the nitrogen pile up has been attributed to a preferential reaction of NH3 with the interfacial oxide layer under tensile stress [192]. The fact that [N] at the Si02/Si interface is reduced for thicker oxide layers [177], indicates that the nitridation process in NH3 is limited by the diffusion of the NH^ species through both the oxide layer and the oxynitride layer being formed. Nitrogen in-depth profiles have been fitted using the solution of the classical diffusion equation (erfc) from the surface down to the interface, while taking into account the reflection and back scattering of the nitriding species [189]. The diffusion coefficient has been estimated to be « 10-16 cm2 s-l, regardless of the nitridation temperature and film thickness. 5.2.3. Proposed nitridation mechanisms Nitridation in pure N2 is found to be nearly impossible. This is confirmed by the fact that a direct reaction between Si02 and N2 is not thermodynamically favorable [177, 188] and that an implantation of N atoms into Si02, followed by an annealing at 1100 °C, only leads to the nitridation of the silicon substrate. The fact that nitridation is possible with NH3 while nearly impossible with N2 seems to indicate that hydrogen plays a role in breaking the Si-O bonds.

60

5. Balland and A. Glachant Two models for such a bond-breaking mechanism have been proposed:

First model It has been proposed [20d] that the nitridation of Si02 proceeds via the following reaction: 3 Si02 (s) + 4 NHs (g) - ^ Si3N4 (s) + 6 H2O (g)

(1.6)

More precisely, the following reactions are expected to take place [177]: NHs^NH^ + Hs.x

(l<x<3)

(1.7)

NHjc + ^ Si'O'Si = ^ = Si-NHx - 0-Si = ^ = Si-NHjc-ySi = + HyO

(1 <x <3)

(1.8)

Since water can easily escape into the anmionia ambient, a surface reaction is expected to be more favorable than a bulk reaction. Likewise, at the interface, the oxidizing species resulting from the nitridation reactions may be consumed by the subsequent oxidation of the silicon substrate. Other reasons behind the increased reactivity encountered at the Si02/Si interface may be due to the capture of hydrogen, originating from the decomposition of anmionia, by the SDBs and by the strained Si-Si bonds present in that region [177]. In the 1000-1160°C temperature range, the reaction could be limited by the (difficult) diffusion of NHx species through the top oxynitride layer, while at lower temperature it might be limited by the activation energy necessary to convert oxide into nitride. Figure 1.39 b clearly shows that [N] depends indeed on T. Second model A nitridation mechanism in two steps has also been proposed [20 d, 134, 187]. It includes: (i) the diffusion of NHx species to interstitial sites which are all uniformly occupied, followed by (ii) the migration of the NHx species from interstitial sites to substitutional sites. Nitridation could proceed via the following reaction, more likely to occur than (1.6). 2 Si02 (s) + 2 NH3 (g) - ^ Si2N20 (s) + 3 H2O (g)

(1.9)

5.3. THE MAIN PHYSICAL PROPERTIES OF HP-NO FILMS Let us now review some of the physical properties of the thin NO films produced by the HP process. 5.3.1. Etching characteristics The (chemical) etching rate of NO films is found to depend on the nitrogen content. This rate approaches that of pure silicon nitride when the NO layer contains a large concentration of nitrogen. Figure 1.42 shows the etching characteristics of NO films obtained by reaction at 1000°C of thermal Si02 films with anmionia for respectively 5 h and 17 h. No difference is observed in the slope of the etching characteristics between the two NO samples. This indicates that chemically passive layers of different thickness, but both having a very small etching rate have been formed at the surface [20d, 228].

Silicay Silicon Nitride and Oxynitride Thin Films

61

Using an HF solution, precise chemical etching depth profiles have been recorded [21c]. These profiles have been related to the [N] depth profile of the NO film, in good agreement with the results of classical Auger in-depth profiUng technique. 200 HF/NH4F = 1/10 150 0)

18 100 c

* £

• -

\

\

50 I-

17h \

5h \ 4

\

Fig. 1.42 - Etching characteristics of two NO films in a solution of NH4.HF = 10:1 (a) reference Si02film (b) NO film (lOOO^'C, 5h in NH3) (c)NOfilm(1000°CJ7h in NH3) (After [21 c] slightly modified)

SiO. Nitroxide -J-

200

400 600 Etching time (s)

5.3.2. Resistance to oxidation Thin NO films, just like nitride films, display lower oxidation rates than thermal oxide films do. Resistance to oxidation in dry O2 increases with nitridation time and temperature. Typically, a 1-nm-thick oxide layer is formed when an NO film, resulting from the nitridation of an Si02 film at 1150°C during 1 h in NH3 [235] is re-oxidized in dry O2 at 925°C. The oxidation rate of NO samples whose surface has been partially etched in HF is found to be practically the same as that of the non-etched samples. This shows that the nitrogen-rich interfacial layer is the most likely contributor to the oxidation resistance [185]. Just like nitride films, NO films display a much smaller resistance against wet oxidation, than against dry oxidation [164]. 5.3.3. Resistance to irradiation The irradiation of a MOS structure by y rays, using a 6OC0 source, generally leads to the build-up of a positive space charge at the Si02-Si interface. This phenomenon is due to the generation of electron-hole pairs and to subsequent hole trapping on electrically active defects of the Si02-Si interface. The resistance of NO films to y-in-adiation is observed to be two to three times greater than that of conventional oxides [187]. This could be due to a passivation of the interface defects, existing prior to nitridation in the oxide film, by nitrogen species diffusing during nitridation. The small number of remaining interface traps is thus insufficient to capture the irradiation-induced holes. For MIS transistors using a 10-nm-thick NO film as gate insulator, bombarded by energetic electrons (dose = 1 Mrad), only a small Vx shift (< 0.03V) and a small reduction in carrier mobility (< 16%) have been measured [236].

B, Balland and A, Glachant

62

1—'—m—1—"^^^—'^-—

E o

1.0

1

b'"' /

/'"''^

12fe>^10 To r y^ <^ ^5""*'^ c U ^^r'^ ^-"".^ — • o \/y^yV

X

o O O

o 10

E / K

X

-1

-^--J

•—^-""""^ J

®J 3

^^""^^""^

y

j

-^

0)

0.5-k -30 (a)

^

-20

> L I 1 1 5 10 10 20 40 §10 5 Q. ( b )

-1 0 0 5 Bias (V)

—

I

1

—

100 200

Dose krad(Si)

®^,-^ F

> <

*^

J)

^-^'*•*"

r-"-^' (D

-10 t-

x"

" ^

Q 10

1 •'

5 10 20 40 100 (c)

1000

1000

Dose krads(SI)

1

p-n

(d)

1

L^

1

1

5 10 20 40 100 Dose

1

LJ

1000 krads(Si)

Fig. 1.43 - Illustration of the effects of irradiation (using 1.5 MeV electrons) on 500-nm-thick pure and nitrided oxide films and on their electrical properties: (a) Normalized High-frequency C-V curves (oxide film: —; NO film: —), dose = 10 krad(Si), gate bias during irradiation = +12V, Arrows point from non-irradiated to irradiated curves; (b) Positive fixed oxide charge versus dose; (c) Interface state density measured at mid-gap versus dose (oxide • ,
Moreover, 500-nm-thick NO samples, irradiated by 1.5 MeV electrons [186-187], exhibit Dit values which are two orders of magnitude less than those measured on the reference oxide film, as illustrated in Figs. 1.43a and c. The evolution of the fixed charge density is comparable to that of the oxide (Fig. 1.43 b), while the MISFET with the NO film exhibits a shift in Vth which is smaller than that measured for the reference oxide (see Fig. 1.43 d). The same behaviour has been observed for 10-nm thick NO films exposed to an electron flux depositing a dose of 10 Mrad [236].

Silica, Silicon Nitride and Oxynitride Thin Films

63

5.3.4. Resistance to impurity diffusion Compared to conventional thermal Si02 films, NO films constitute a good barrier against impurity diffusion. For example no boron diffusion can be detected in MISFETs possessing an NO gate insulator after an annealing at 250''C (Ih) of the boron-doped polysilicon gate electrode [235] and even after an annealing at 1100°C (0.5h) [20 f]. 5.4. THE LOW-PRESSURE (LP) NITRIDATION PROCESS

5.4.1. The various LP processes The HP nitridation technique (carried out in NH3 at atmospheric pressure or above, using long nitridation times), which we reviewed in § 5.3, suffers from an inability to control the spatial distribution of nitrogen in the oxides and, consequently, the defect density in the bulk oxide and at the Si02-Si interface. Low pressure (LP) processes have also been studied and used. Although nitridation times are longer, LP processes allow a good control over nitrogen incorporation into silica. There exist basically two processes to accomplish the LP nitridation of silica: in a low-pressure NH3 ambient (abbr. LP) or in a low-pressure NH3 plasma ambient (abbr. LP-PE). • LP thermal nitridation with or without plasma The furnace depicted in Fig. L44 can be used both for nitriding the Si02 films at low pressure (unassisted) and for plasma-enhanced thermal nitridation. Two electrodes are used to capacitively couple the RF power and the plasma discharge, if desired. Quartz

RF generator (13.56 MHz) Heater elements Q Q Q g Q 0 Q

0 0 0 0 0

Heater elements RF Discharge plates

Wafers on quartz boat

¥

Vacuum door

To mechanical vacuum pump

Fig, 1.44 - Schematic cross section of a furnace used for nitriding oxide films: a typical nitridation is carried out at 950°C in NH3 (P(NH^) = 1 mbar) or in a NH3 plasma ambient for 2 hours. (After [22] slightly modified.)

• LP thermal nitridation in a UHV environment Ultra High Vacuum is mostly used to study the nitridation process itself. For example, the nitridation of 13-nm-thick thermal Si02 samples has been studied in an UHV environment as a function of: temperature (850-1 ISO'^C), ammonia pressure (IQ-^-lO-l mbar) and nitridation time (t < 15 h), using AES, XPS, SIMS, Raman and IR spectroscopies [215-220, 223, 237].

64

B, Balland and A. Glachant

• LP plasma-enhanced thermal nitridation The nitridation of thin silica films can be performed in a N2 or NH3 plasma at temperatures ranging from 300 to 700°C [232]. The plasma is ignited by a 90-450 kHz RF generator. The frequency range is chosen well below the ion transit frequency (« 4 MHz [229]), to maximize the ion bombardment of the film. The RF power can be chosen between 400 to 1100 W. The [N] and [O] in-depth profiles measured by AES (as illustrated in Fig. 1.45), reveal: an enhanced nitridation at the surface of the oxide, little nitrogen incorporation in the oxide bulk, and the existence of a small nitrogen pile up at the Si02-Si interface, when NH3 is used, or the formation of a near-homogeneous oxygen-rich oxynitride, when N2 is used [232]. The ion bombardment of the substrate is found to enhance the nitridation process. These profiles have been confirmed by etch rate measurements [232]. 100 ^80 c60 o

1

S 40

u c

o

^20

4 6 Sputter time (min)

0

8 12 16 Sputter time (min)

(b) (a) Fig. 1.45 - In-depth concentration profiles (based on Auger Electron Spectroscopy) of nitrogen and oxygen measured in a 10-nm-thick plasma-enhanced nitrided oxide, (a) For a nitridation performed at 925°C for 2 hours, (b) For different nitridation times (Ih, 3h, 6h). (After [18] and [232] slightly modified).

5.4.2. Composition of LP-NO films In the case of LP and LP-PE thermal nitridation in ammonia, [N] and [O] concentration profiles are shown to be complementary* . This fact could indicate that in the nitridation process nitrogen simply replaces oxygen in the silica matrix. However, all the trends conceming the evolution of the nitrogen concentration which we describe in the following, remain accurate whatever the mechanism involved in LP nitridation may be. In particular, this approach demonstrates that the nitridation of an oxide leads to the formation of three distinct zones: surface, bulk and interface. • Below the oxide surface The composition parameter of the region undemeath the surface of the NO film can be assessed by using the INAIN + lo) ^^^tio of the Auger N and O peaks. This ratio measures the extent of nitridation in this region. For a nitridation at T = 1100°C and * When the ratio of the AES sensitivity factors between O(KLL) and N(KLL) is taken to be 1.6 as in an oxynitride.

Silica, Silicon Nitride and Oxynitride Thin Films

65

P(NH3) =10-1 mbar, it has been observed that the composition parameter first increases rapidly and then saturates, while simultaneously, the main Si(L23VV) Auger transition shifts from the Si02 energy location up to a position which is near that expected of Si3N4 (see Fig. 1.46 a). Hence, the LP nitridation of Si02 in pure ammonia leads to the formation of a nitrogen-rich oxynitride layer in the surface region of the oxide sample. The surface peak is found to be independent of film thickness and increases at a rate which depends on the square root of time. This is characteristic of a process limited by the diffusion of the reactive species. The peak reaches its maximum when nitrogen replaces about 80% of the oxygen atoms. Then, the nitrided surface layer spreads over about 5 nm. The surface reaction is found to be weakly thermally activated. In the case of LP-PE nitridation, the surface reaction is not affected by a further increase in the RF power beyond 600 W. The evolution of the composition parameter with time for different T values at P(NH3) = 10-1 nibar and for different P(NH3) values at T = lOOOX is shown in Figs. 1.46 b, c respectively. For sufficiently large nitridation times, a substantial nitridation of the surface region of the oxide can be achieved for P(NH3) > 10-3 mbar. For T = SSO^'C, the composition parameter remains appreciably smaller than the mean value measured for T > 950°C. The XPS peaks for Si (Si 2pi/2 3/2) reveal that the chemical environment of Si atoms is more varied in the case of oxynitrides than in the case of nitride or oxide [141c, 219].

o ^ ** •

'•'••'

^ .•-' "

40 •

^

\i>

100

(a)

200

•

Nitridation

time

h / 1 /

' 17 a 0 l + ' l ..I

(min)

(b)

•

850°C 950*C

Q

'

A

+ 1024''C 0 X

100

300

•

a'

'

h!/ < 'x

20

"

--•*''

x

^

L_

200 300

1075°C 1110'C _j

1

L

400

Nitridation time

(min)

66

B. Balland and A. Glachant

100

Y L

o

.^-^xs—"5

Y Cf""^ 50 Y / z =-

r i^

2

0 ( c)

1 n*-T

^'''°

^-cr'" . - - " ' . - » - - * ' ; ^ ^ ^^ ^ "*" 1—1—1—1—1—1—1—1—1—1—1—1

5

10

Nitridation

15 time

(h)

Fig. 1.46 - Illustration of the LP-nitridation kinetics of a set of 13-nm-thick Si02 samples placed in a pure NHj ambient: (a) Variation of the composition parameter with nitridation time (top) and shift of the corresponding Auger Si(L23W) energy peak (below) with t for T= 1100''CandP(NHs) = lO-l mbar; (b) Variation of the composition parameter with t for P(NHs) = 10-i mbar and various T>850°C (c) Variation of the composition parameter with t for T=1000°C and P(NH3) = 10-^ (0), 10-3 (o) and lO-i mbar (o). (After [219] slightly modified).

ARXPS (Angle-Resolved X-Ray Photoelectron Spectroscopy) experiments reveal in fact that NH^ species (together with SiN species) exist near the nitrided oxide surface. IR absorption spectra from the same samples confirm the existence of N-H bonds which have been assigned to amine (NH^) groups, as expected [199]. • SIMS analysis of the hydrogen content (not shown in Fig. 1.47 b.) reveals the existence in the surface region of a concentration of ~ 10^1 - 10^^ H atoms/cm^. The in-depth [H] profile is similar to that of [N] but with no evidence of an H pile up at the Si02/Si interface [217-219]. These last results confirm previous NRA measurements [190], showing that the hydrogen content of NO thin films, using the LP process, amounts to 1-3 at. %. • In the bulk In-depth [N] profiles can be measured both by AES in conjunction with Ar+ sputtering (see Fig. 1.47 a) and by SIMS (see Fig. 1.47 b). These profiles reveal a nitrogen enrichment and an oxygen depletion below the surface region of the NO samples, where a thin inhomogeneous oxynitride layer has been formed. The nitrogen content is found to decrease rapidly with depth. • At the interface A very small nitrogen pile-up, concentrated within a few monolayers from the interface is generally found near the Si02-Si interface, as shown in Fig. 1.45. The [N] concentration at the interface is found to be independent of the film thickness and to increase linearly with time. It is smaller than in the case of HP processes. The pile-up is only governed by the interface reaction. The temperature has no influence on the interface reaction. The increase in plasma power induces a linear increase in the nitrogen concentration at the interface. These results are of great interest for technological applications. It is possible to tailor the nitrogen distribution in the oxide layer by varying the experimental conditions. The physical and electrical characteristics strongly depend on the type of nitridation process used. For example, plasma nitridation furthers a surface nitridation with very few nitrogen atoms in the oxide bulk or at the interface. The resulting NO samples thus exhibit minimum interface states.

Silica, Silicon Nitride and Oxynitride Thin Films

67

1.0

l_

0) Q.

o

i

CM

insulator

n\

p-Si(100) c 4

1 0.5

Si

insulator Si-N"^

1 \

interface

interface

1 \ ^'^

o

2 F

<

r#ir*i ^^-O-TS^^S^^

0

0.5

Normalized

(a)

1

1.5

1.0

-"

8 s

depth

(b)

12

16

Depth

(nm)

:^

[N]/(rN] + [0])

1H c o o

Depth

(0

a - 1 monolayer at the interface

c o o

L

urvYinrrruiA'yvYrrau^wyinrm'

(c)

X

1% in the bulk

nil iiiii m i l m i l iiiii i i ^

Depth

(nm)

Fig, 1.47 (a) - AES depth profiles of nitrogen (in arbitrary units) recorded in NO films, obtained in conjunction with Ar'^ sputtering (two sputtering rates have been chosen in order to check for sputtering artifacts (1 nm/min (0) and 0.2 nm/min (O)); nitridation conditions: P(NHs) = 10'^ mbar, T = 1024''C t = 10 h). (b) ' SIMS profiles (in number of counts per second) recorded in NO films, of Si-N and N-O groups (nitridation conditions: P(NH^) = 10-^ mbar, T = 1045''C, t = 4 h). (After [141c] slighty modified), (c) - Auger profiles and simulated nitrogen concentration of an LP-PE nitrided oxide (16 nm thick). It shows that plama nitridation mainly transforms the surface region [219].

B. Balland and A, Glachant

68

5 A3. Proposed nitridation mechanisms The fact that the increase in [N] is accompanied by a simultaneous reduction in [O] in the same probed region, as shown by AES, reveals that during the nitridation process nitrogen atoms replace oxygen atoms. As previously discussed (in § 5.2.1), amine NHx groups are essential in the nitridation of Si02. It has been proposed [238-239] that higher-order amine groups (x < 3), and eventually nitride species form at the expense of amine groups while oxygen is lost in the form of water. ARXPS analyses [141c] confirm this prediction. Experimental results are consistent with a reaction of NHx groups with the oxide film, this reaction being limited by the diffusion of nitriding species through the nitrided layer and by water elimination: water must be eliminated from the system to maximize the amount of nitrogen incorporated in the film. At the surface, the reacting nitrogen species are nitride, amine, and molecularly adsorbed ammonia groups. In the bulk, the concentration of nitride groups vanishes while a relatively larger concentration of amine groups is observed with increasing depth. Compared to the HP process, the LP process clearly leads to an enhanced superficial nitridation of Si02 while the nitrogen pile-up at the Si02-Si interface is very small (very often undetectable (see Fig. 1.47 a)). The enhanced nitridation in the surface region can be attributed to various complementary factors listed below: 1/ Water is more easily eliminated in a particularly dry and low-pressure anmionia ambient than in the bulk of the insulator. This furthers the reaction between NH3 and Si02 (see Fig. 1.48 a). 2/ The diffusion length of the reacting species is smaller at LP than at HP. 60 at(%)

ou 1

^40

o

s

v. 0 40 \ c

0

-- 40 c o o c -

0) 0

§30

c 0

0 0 20

S

0

c 0

8

20 -

0

zlO — 0 (a)

c

0

1

8«

60

\

c

4

at(%)

>* \

10

1

1

20 30 H 2p Percentage

a>

^ 0. 0 (b)

^

^ ^ 1

H 20 •u £ p

"^^v^

:

: ^ J 0 3 4 Depth (nm)

8

Fig. 1.48(a) - Superficial nitrogen concentration vs. H2O percentage in the gas phase for two nitridation times: t = 2h(m)and7h (o) (T = 1050°C, PiNHs) = IQ-^ mbar); (b) Corrected [N] in-depth profile (o) deduced from a measured AES depth profile (*) (T = 1050°C, P(NHs) = IQ-' mbar, f « 7 /i). (After [219]).

Silica, Silicon Nitride and Oxynitride Thin Films

69

3/ The diffusion coefficient of NHx decreases rapidly in the reacted layer due to the N enrichment, as previously proposed [177] (the diffusion coefficient of nitrogen in Si3N4 is only « 10-2^ cm^ s"! at 550°C). This implies that the diffusion coefficient of the observed amine groups, diffusing through the reacted layer, decreases with increasing [N] and consequently decrease with nitridation time. An apparent diffusion coefficient for various [N] values has been roughly estimated using the [N] in-depth profile corrected for experimental artifacts (see Fig. 1.48 b). At 1050°C this coefficient has been found to decrease from « 10"l^ cm^ s'l down to « lO-^^cm^ s"^ when the superficial [N], expressed in atomic concentration, increases from 15 up to 56 at %, i.e. practically the [N] value expected for Si3N4 [141c, 219]. 5.5. T H E MAIN PHYSICAL PROPERTIES OF L P - N O FILMS

No significant difference in physical properties is observed between LP and LP-PE nitrided oxides. The specificity of plasma-enhanced nitridation, is that nitrogen can be incorporated below the oxide surface while minimizing its amount in the oxide bulk and at the interface. This explains the excellent transport properties encountered in both n and p-channel devices using LP-PE nitrided gate oxide films as shown further on. 5.5.1. Optical refractive index The refractive index moves to higher values when nitridation time increases. The mean index values are 1.47, L57, 1.64 and 1.69 for the different treatment times of 0, 1, 3, and 6 h, respectively. The largest part of this modification occurs at the beginning of nitridation [232].

ior

r® 33n

c /

CO CO

0)

r"

\

1

a 6 1

1

\/ \» *

/ •

1

f

J 28.8nm/min

\

^^

m/min®

i

f

A

1

f

1

• / 7.5nm/miri

/ / •i 9.1nm/mini 1 1

1 i 1

E 2

1.0 nm/min ' • > / 0.13 nm/mIn

1^ >

0 1

*

^

J, ^ y

I

:

4 6 8 Etching time (min)

Fig, 1.49 - Effect of nitridation time on the etch rate of lO-nm-thick silicon dioxide films dipped in a buffered HF solution: ® as grown; ® nitrided for I h; d) nitrided for 3 h; ® nitrided for 6 h. (After [232-233] slightly modified).

70

B, Balland and A, Glachant

5.5.2. Etching behavior The etching behavior of LP-NO films dipped in buffered HF solution (100: 1 = NH4 F: HF) agrees with the Auger analysis. Three distinct nitrided zones are observed: the surface, the interface and the bulk. The resistance to etching observed at the surface and at the interface is due to the presence of nitrogen in both regions. The major portion of nitrogen is concentrated at the surface and the nitrogen content, in every region, increases with the nitridation time. A precise determination of the thicknesses of the three zones can be deduced from the large difference in the etch rate observed between the nitrided and the non-nitrided region, as visible on Fig. 1.49. 5.5.3. Resistance to oxidation NO samples grown at low pressure exhibit a good resistance to oxidation. Authors have reported that two 13-nm-thick films: an NO film (nitridation conditions: T = 1075°C, P(NH3) = 10-1 mbar, [N] « 56 at. %) and its SiOi reference were simultaneously oxidized (oxidation conditions: T = 1000°C, P(02) = 10^ mbar, t = 45 min) [240]. The resistance to oxidation was assessed by measuring the increase in film thickness, taking place upon oxidation, using the AES in-depth profiling method. The oxide sample was found to be « 50 nm thicker than the NO sample (in which nitrogen was hardly detectable after oxidation). 5.5.4. Resistance to irradiation The effect of bombarding, with 3-keV electrons (electron flux = 2 x 10^^ cm-^s"!), Si02 films before or after nitridation (T = 1050°C, P(NH3) = 10"! mbar, t = 6 h) has been studied [240], as a function of irradiation time (tin- < 13 h). For the pure Si02 film, a chemical reduction of the surface region of the oxide film (characterized by the breaking of Si-0 bonds followed by the migration and/or the desorption of O atoms) is found to occur for tin- « 1 h, i.e. for an electron fluence of « lO^^ cm"^ (as expected [241]). The reduction rate increases continuously with tin- until saturation is reached, i.e. after tirr - 4 h. The NO films reveals the same behaviour as the oxide film during the first hour of irradiation, but, its reduction rate reaches first a maximum value, which is one order of magnitude less than that of the oxide (1 h < tin- ^ 1-5 h), and then decreases down to zero (tin^ « 3 h). During the same period, [N] in the surface region decreases from « 46 at. % (tin= 0) to a constant value of ~ 15 at. % (for tin= 6 h), while [O] increases first and then saturates (for tin = 6 h). This behaviour has been explained by the electromigration, in a nonuniform electric field [227], of O and N ionized species resulting from the electron-induced breaking of the Si-0 and Si-N bonds. 5.5.5. Resistance to impurity diffusion An LP-NO film, just like a nitride film, constitutes a good barrier against the diffusion of impurity and doping atoms. The ability of NO films to prevent boron diffusion has therefore been investigated.

Silica, Silicon Nitride and Oxynitride Thin Films

71

Boron profiles in the Si substrate, resulting from boron atoms diffusing from a borondoped poly-Si electrode through the gate oxide, can be analyzed by combining a spreading resistance profiling (SRP) technique and SIMS. As illustrated in Fig. 1.50, NO films are effective in slowing down boron diffusion. 0

"iio^^ \ N. >-^ c o

® \

\

Fig. 1.50 - Boron profilesy measured in a p-type substrate, resulting from the diffusion of B atoms through a J-nm-thick film during 6 h at 970°C (D nonnitrided oxide; ® oxide nitrided in an NH^ plasma during 10 min at 900''C. (After [231]).

\^

\

••^^

^^

(0 k.

\\

c^ J 5 01 0

\

y®

\^ x\

V^

N.

^ V w

o c o

11

^^^*-«^

^ ^ ^ ^

J^«-»>^

11

*-—'-^-^^^•""^ ^„—.

O

. J4 10 0

1

1

0.2

0.4

Depth (jim)

In the example illustrated in Fig. 1.51, MOS and MNOS capacitors have been fabricated using either aluminium or boron-doped polysilicon gate electrode material. After an annealing in H2 at 450°C (30 min or 1 h), no boron diffusion can be detected in the MNOS structures, neither through the measurement of AVth nor by measuring the distortion of the C-V curves in the depletion region. The exact nature and location of the diffusion barrier have not been identified. Even if boron atoms have diffused to some extent into the dielectric, their presence has not been reported to degrade the dielectric quality [231]. u.

Q.

>—' .^ 4 0 0) 0

~ ~* -V: ""^"V^ N^'^v

c

r

30

^

20

0 CQ

y^

\

,'x^ / \ \

-''' 1 '•

^ — ®

0

®-H 10

0 . -2.5 (a)

1

1

^^-^^ !

0.0

1

1

J

2.5

Gate voltage (V)

-2.5 (b)

0.0

2.5

Gate voltage (V)

Fig. 1.51 - Quasi-static C-V plots of capacitors fabricated (a) with a pure silica film, (b) with an NO film: curve (D: with an A/gate, curve ® with a P* polysilicon gate [231].

72

B. Balland and A, Glachant 5.6. DEFECTS INTRODUCED BY THE NITRIDATION PROCESS

5.6.1. Defects induced in the silicon substrate During the nitridation of an oxide film, stacking faults of the silicon substrate are found to grow [175]. This phenomenon depends on the partial pressure of anmionia in the reactor. As indicated in Fig. 1.52, the diffusion of phosphorus and boron is accelerated during the nitridation of the oxide, due to the injection of interstitials in Si leading to a distortion of the crystal array [173, 176]. This result is the opposite of what is observed during the direct thermal nitridation of Si (see § 3.2.). Similar results regarding impurity out-diffusion and the growth of stacking faults during the nitridation of Si02 and Si [189] have been mentioned in Chap. 3 of Vol. 1 [10 c].

(a)

(b)

Fig, 1.52 - Illustration of the effect of thermal nitridation on the diffusion of doping atoms (a) Cross section of the test structure used, (b) Cross section after direct exposure to NHj ambient at elevated temperatures showing the diffusion zones: in zone B, B and P atoms have diffused less during nitridation. In zone C, diffusion has been enhanced compared to both zones A and B. (After [173] slightly modified).

A model based on an equilibrium between point defects (vacancies and interstitials) has been proposed [173] in order to describe this phenomenon: 1/ A thermal equilibrium exists between interstitials and vacancies in Si at high temperature. If we call [I] and [V] the concentration of interstitials and vacancies respectively, we can write: [I] + [V] <=> 0. It follows that when [I] increases (resp. decreases) then [V] decreases (resp. increases) while product [I] x [V] remains constant (at a given temperature). 2/ An interstitial supersaturation and a vacancy undersaturation appear simultaneously at the Si02/Si interface during the nitridation process. 3/ The diffusion of B, P, Ai and Ga in Si is associated with a migration of interstitials. Following this model, the enhanced diffusion of B and P, observed during the nitridation of a thermal oxide in NH3 should be due to a supersaturation of interstitials and an undersaturation of vacancies.

Silica, Silicon Nitride and Oxynitride Thin Films

73

5.6.2. Defects introduced in the silica film Nitridation introduces in silica several new defects which are not always easy to tell from regular defects introduced during oxidation. • Intrinsic defects Intrinsic defects, similar to those found in silica, are found in NO films, namely: strained and broken Si-O bonds, oxygen vacancies, non-bridging oxygen atoms, etc. (see Chap. 2 in Vol. 1 [10 b] for a more complete description). Depending on the nitridation process used, the effective density of oxygen-related carrier traps is found to be between lO^ and 1013 cm-3 [173]. • Extrinsic defects The dissociation of ammonia is a source of hydrogen contamination during the nitridation process. Hydrogen atoms and H+ ions are very mobile in an NO film. Various atoms or radicals (especially H, OH, N, N-H...) enter the silica network during the thermal nitridation process, and combine with it. If the = Si-O-Si = bond is broken because of thermal treatments, the non-bridging oxygen atoms thus generated are very mobile and combine with foreign atoms. The O atoms of the network tend to retain these impurities to form complex defects. Just like in regular nitrides, such groups as = N-H, and = N*(Nitrogen Dangling Bond) are encountered in NO films. = Si-N groups are also found (due to the substitution of an O atom by a N atom in the = Si-O bond). The nitridation of Si02 at T > 900°C in an NH3 ambient induces the generation of hole traps at the Si02/Si interface due to the presence of = Si-O groups, resulting from the Si + Si02 reaction (see Chap. 2 of Vol. 1). Power = 600 W I

10 -

s 8

• Ns

^

* Ni

V ^

Nitridation time ^-^

•


s 0 tS «n

3h

- • Ns * Nl

8

T-^

0

6 C O

1 o

4

-

2

/ /•

0 c ^0

6

''S 2 4^

4

C

^


g 2

0

/

0

n- \'-*^''^ 0 (a)

\

\

1

i-^"'"'""^

1 400

Time (h)

(b)

800 Power (W)

Fig. 1.53. - Evolution with time (a) and plasma power (b) of the nitrogen content at the surface (N,) and at the interface Ni), in a 16-nm-thick oxide nitrided in an ammonia plasma at 950°C and P(NHi) = 0.3 mbar (After [232]).

74

B, Balland and A. Glachant 5.1. THE ELECTRICAL PROPERTIES OF NO FILMS

We have seen that the HP nitridation of an oxide leads to the incorporation of nitrogen at the surface (Ng), in the bulk (Nb) and at the Si02-Si interface (Ni) and that the amount of incorporated nitrogen increases with nitridation temperature and time and with plasma power. On the other hand, the LP process leads mostly to the incorporation of nitrogen underneath the top surface of the oxide. The evolution of nitrogen concentrations (Ns and Ni expressed in atoms/cm^) with time and power is shown in Fig. 1.53. The presence of nitrogen in Si02 leads of course to somewhat modified electrical properties, which we review next. Moreover a difference in electrical behavior is expected between HP and LP nitrided oxides. 5.7.1. Dielectric constant High frequency C-V curves reveal that a nitrided film behaves like the original (nonnitrided) oxide film (as can be seen from Fig. 1.54) except for its capacitance value in the accumulation mode (Cacc) and for its flat-band voltage (VFB)- An enhancement of Cacc is systematically observed. This enhancement is explained by the increased (effective) permittivity of the NO film. As nitrogen is incorporated into the oxide, the dielectric constant of the film Er may increase from 3.9 (Er value for Si02) to 7.5 (Ef value for Si3N4).

Fig. 1.54 - High frequency (HF) and Low frequency (LF) quasistatic C(V) curves measured on a MOS structure made up of a IS-nm-thick oxide, pure or nitrided for 3 hours, an n^ polysilicon electrode and a p' doped Si substrate with an electrode area = 0.38 mm^. (After [223] modified).

-3

-2

-1

0 Voltage

+1 (V)

5.7.2. Flat-band shift A correlation between the amount and direction (negative or positive) of the flat-band voltage shift AVpB and the nitrogen distribution has been observed: AVpB depends on the nitridation methods and parameters (nitridation time t^it, T and P(NH3)) [182, 194-195]. In Fig. 1.55 a, AVpB has been plotted as a function of t^^^ (for a continuous HT LP nitridation process). We note that at first VpB decreases (increase in negative flat-band shift), thereby indicating the creation of a positive oxide charge, an effect which has been reported for plasma-enhanced thermal nitridation. The VpB value then stabilizes and finally, during a third period, increases and comes back almost to its original value.

Silica, Silicon Nitride and Oxynitride Thin Films

75

Since AVpB reflects the variations of both the fixed oxide charge and the fixed interface charge during nitridation, the interpretation of the phenomena is not easy at this stage. The complexity of the phenomena involved is further illustrated by Fig. 1.55 b where the VpB measured during a sequential thermal nitridation (i.e. nitridation by cycles of short duration: Atnit = 3 to 4 mn at the same temperature) has been plotted. In this case the final VpB value exceeds that of the original oxide !

1 2

(a)

3

4

5

Net nitridation time (h)

0 (b)

10

20

30

40

Nitridation step duration (min)

Fig. 1.55 (a) - AVfB is plotted as a function of nitridation time for a continuous nitridation mode (T = 1050°C, P = 10'^ mbar); (b) AVf^ is plotted as a function of At for a sequential nitridation mode (t^^^ = 120 min, T = 1050°Q P =10-^ mbar). (After [223]).

In both cases (continuous and sequential nitridation) the AVpB curve displays zones for which various mechanisms have been proposed. • During the first phase (i.e. for t^^^ < 30 min), initial nitridation produces electrically active defects (strained bonds, broken Si-O bonds, possibly accompanied by displaced Si and O atoms and Si-dangling bonds) which are all sources of positive charge, i.e. which all produce a negative VpB shift [177]. These defects are due to the in-diffusion of hydrogen, O-H and N-H radicals, into the oxide. This shift has indeed been correlated with the presence of Si-H and Si-OH groups, observed by analyzing the NO film by means of SIMS and RAMAN spectroscopy [217-219]. • During the second phase t^it increases and Si-N groups form which reduces AVpB by reducing the number of SDBs or by redistributing the existing defects. • During the third phase and after long nitridation times (t^jt > 90 min), the negative voltage shift is greatly reduced, as the amount of incorporated nitrogen keeps increasing. The concentrations of the main defects, namely = Si*, = Ni*, and = Si-H, = N-H, increase. AES analyses show in fact that the amount of incorporated nitrogen increases with time and temperature and that nitrogen is detected at the Si-Si02 interface [212-214].

76

JB. Balland and A, Glachant

Fig, 1.56 - Evolution of the fixed charge and generation of charge and interface traps during the nitridation of a IS-nm-thick oxide [217].

0

2

4

6

Nitridation time (h) 5.7.3. Impact of nitridation on interface states • MOS structure with w^ polysilicon gate electrode and p'Si substrate Nitridation does not significantly degrade the Si02-Si interface when the initial quality of the oxide is good (i.e. typically when Dj^ «10l^ cm-^ eV"l at mid-gap). By optimizing the nitridation conditions [217], Djt values after nitridation remain low (1 - lOxlOl^ cm"2 eV"l) as illustrated in Fig. 1.56. The incorporation of a fraction as low as 4 at.% of nitrogen* at the Si02-Si interface leads to some increase in Djj [205]. The change in material structure from Si02 to nitrided Si02, leads to a different state of bonding, stress, etc. at the interface and may be one of the causes of an increase in Dj^ upon nitridation. It is therefore desirable to keep interfacial [N] well below this value. • MOS structure with p^ (boron-doped) polysilicon gate electrode The measurement of the VpB shift as a function of annealing time, is not sensitive enough to detect any degradation due to boron diffusion but the midgap interface state density (Djt), measured by QSM reveals a strong degradation when boron diffusion occurs. Figure 1.58 illustrates that this is indeed the case for a control oxide (Dit varies from 3 x 10^^ to 6.1011 eV-l cm-2), while Dit for two plasma-nitrided films remains nearly constant (from 2 X 10^^ to 3 X lOlO eV-l cm-2), even for prolonged nitridation. The nitridation of silica is effective in providing a good protection against boron diffusion [233]. 5.7.4. Impact of nitridation on conduction mechanisms Figure 1.59 a shows the I-V curves of MOS and MNOS devices (with an oxide thickness of 10 nm). Each curve is the average representative of several I(V) measurements performed for VG<0.

• For low electric fields (e.g. EQX < 7 MV/cm), as visible in Figs. 1.59 a and b, NO layers display a better conductivity (curve (3) than regular oxide layers (curve 1)). This can be attributed to the presence of the N-rich superficial layer which lowers the effective energy barrier height for electrons (this barrier is smaller for Si3N4 (2.1 eV) than for Si02 (3.2 eV)). •

Nitrogen atomic concentrations are mesured by fitting AES spectra.

Silica, Silicon Nitride and Oxynitride Thin Films

11

•^••1 5 ^ • Oxide (lOnm) K * 3h nitrlded / A 30 min nitrlded^'

'>10-|-

®

T—

o ^ 5 4-

0

1 Annealing time

2 (h)

-0.2

Surface potential (V) Fig. 1.57 (left) - The interface state density of several MOS and MNOS structures is plotted versus surface potential (or energy): (I) Si02film of poor initial quality, (2) and (3) the same film after nitridation at 1050''Q (4) good quality Si02film, (5) the same film after nitridation [223]. Fig. 1.58 (right) - Evolution of the midgap interface state density of MOS capacitors with a /?+ (B-doped) polysilicon gate (D of MNOS capacitors ® as a function of the annealing time at 950°C in N2: [233].

-6 f^

(a)

- 5 -1 0 Gate voltage (V)

Fig. 1.59 (a) - I-V characteristics of MIS devices with a 10-nm-thick oxide and a lO-nm-thick nitrided oxide (nitrided at lOOO^'Cfor 4 hours). (After [223]). Fig. 1.59 (b) - I-V characteristics measured: (D for a MOS structure ® and (3) for an MNOS structure obtained by sequential nitridation (t^if^ 120 min, T = 1050°C, P(NH^) = 10-1 mbar with At =10 min for (2) and with At = 40 min for 3). (After [224]).

(b)

4 8 12 Gate voltage (V)

16

• For higher electric field (EQX > 8 MV/cm), FN tunneling is the prevailing conduction mechanism, both for NO and regular oxide films (in the FN plots of Fig. 1.60, both I(Eox) data fit a straight Une and the strong field dependence of the current is preserved after nitridation).

78

B, Balland and A, Glachant

CM

>

LU

Fig. 1.60 - Current-field plot for as-grown and nitrided Si02 films: (D As-grown 11-nm-thick oxide ® after nitridation at 1000°Q in NH3, 10 min (S) after nitridation at lOOO^'C, in NH3, 120 min (After [223]).

1.0

1.2

1.4 1/Eox

1.6

1.8

(lO^cm/V)

The surface oxynitride layer and the interfacial oxynitride layer (when it exists) of NO films, are both thinner than typical tunneling distances (2 to 3 nm). Therefore, the FN characteristics of NO film are not markedly different from those of regular oxide films. An increase in the nitrogen content of the film causes a parallel rightwards shift of the FN plots as visible in Fig. 1.60, and this shift, which is found to be proportional to the increase in [N], is due to the increase in the positive oxide charge. The non-linear behavior of curve (3) of Fig. 1.60 is due to a change in film composition following a prolonged nitridation: the slope of the FN-plots decreases for long nitridation times at low pressures (10"6 mbar 0). To minimize or avoid trap generation and high-field-assisted detrapping, techniques like UV photo-injection, FN tunneling (Constant Current Stress: CCS) or avalanche injection can also be used.

Silica, Silicon Nitride and Oxynitride Thin Films

79

Carrier trapping can be detected through the shift of the high-frequency C-V curves along the voltage axis (AVQ or AVpe). A positive shift indicates that a negative charge is accumulating, and the measured charge nearly equals (in magnitude) the charge injected into the NO film. • The detrapping properties of NO films Once AVpB has reached saturation and when electron injection is stopped, the C-V curves relax. This relaxation is initially quick and then slows down. Reverse-biasing the device significantly increases the relaxation process. Temperature is shown to have a negligible effect on electron detrapping, which makes a mechanism of thermal emission from shallow traps unlikely. Tunnel emission must be envisaged to explain electron detrapping, and the depth of the dominant deep electron traps has been estimated at 2 eV below the conduction band edge of the oxide [212]. A tunneling hole process may also contribute to the relaxation of the C-V curve. Holes tunnel from the silicon substrate to the oxide valence band and subsequently recombine with the trapped electrons. However no extensive investigation of this phenomenon, in the case of thermally-nitrided oxide, has been carried out. 5.1.6. Dielectric breakdown in NO films The dielectric strength (or destructive breakdown field) of NO films varies from 2 MV/cm to about 30 MV/cm, depending on the nitridation conditions (Fig. 1.61). It is however shown to be on average greater than that of regular (non-nitrided) oxide films. The electrical conduction and charge trapping characteristics of NO films, measured before breakdown, are similar to those of oxide films. The current distribution in NO films is however found to be much more uniform than that found across a regular oxide thus indicating fewer weak spots (these weak spots are thought to cause current instabilities in the high-field regime and to induce breakdown itself). Nitridation removes flaws in the oxide and gives NO films a greater dielectric strength. 12.0 F

?o

1

5 11.5

ll

1 1

5,,.o

1 10.5 1

(a)

1 — 1 —

• 1 2 3 4 Nitridation time 1

L 5 (h)

(b)

1 2 3 4 Nitridation time

5 (h)

Fig. 1.61 a - The maximum field strength of a 10-nm-thick NO film is plotted versus nitridation time (at T=1000''C) Fig. 1.61 b - Breakdown current, defined as the maximum equilibrium current just prior to breakdown, is plotted versus nitridation time (at T = 1000°C) [256].

80

B. Balland and A, Glachant

Another explanation for the improvement in dielectric strength is that the electron traps created by the nitridation process are filled more quickly near weak spots in the oxide (because of enhanced conduction there). The filled traps create a local field which counters the external field and chokes off conduction, allowing a more even current distribution across the film. Consequently the dielectric strength of NO films appears to be a function of the number of electron traps created by the nitridation process [72]. Below a critical number, the traps increase the dielectric strength by reducing the field, and consequently the current at weak spots. Above this critical number, the filled traps appear to cause the intemal field to increase which could result in breaking the Si-0 bonds and trigger breakdown. SJ.l. Enhanced saturation transconductance of p-channel MOSFETs Dual gate C-MOSFETs have been fabricated with thin 8- and 15-nm-thick silica gate films nitrided using LP-PE nitridation. An improvement of both n and p-channel transistors drive characteristics (+ 12% and + 5% respectively) has been obtained [233]. After nitridation, the saturation current of transistors with 15-nm gate oxides improves by 8% and 3%, for n and p-channel devices respectively, when measured at Vc-Vth = Vj = 5 V. The influence of nitridation in the saturation regime is even more effective when the oxides are thinner. In this case, the n and p-channel transistors with 8-nm dielectrics show respectively 12% and 5% higher current values after nitridation, as shown in Figs. 1.62 a andb. The difference observed between the two types of transistors (tox = 8 nm and 15 nm) can be explained by the higher nitrogen contents (N / N + O) incorporated in thinner films. Indeed, Auger analyses have shown that treatment in an anmionia plasma essentially nitridates the outer oxide surface so that the resulting nitrogen fraction is higher when the film is thinner. Moreover, capacitance measurements show that the permittivity increases after nitridation by only 3% for 15-nm oxides and by more than 5% for 8-nm oxides. 1.2

y

VG-Vth PMOS

E 1.0hL.

'—t" -^^

Jo.8 0.6 Jr^r^

0.4

>.--••

.J^fs^^

''

A—

i\i

— ( f - »3V

p-

0.2 0 (b)

'•••^•^5

^A^ 0

. ^V

1

4

5 Vd ( V )

Fig. 1.62 - Saturation Id-Vd characteristics ofn-channel (a) and p-channel (b) MOSFETs featuring 8-nm-thick non-nitrided gate oxides (lower curve) and 8-nm-thick NO films (upper curves) (the oxides have been nitrided in a NHs plasma). (After [233]).

Silica, Silicon Nitride and Oxynitride Thin Films

81

In the case of the p-channel transistors, the higher current drive characteristics quantitatively corresponds to the percentage of capacitance (or permittivity) increase. But, for the n-channel transistor, the capacitance increase is not sufficient to account for the observed 12% enhancement of the saturation drain current. Since the normalized saturation transconductance (Gmsat/Co) with Co = Ci*W*L is known to be the best criterion for speed evaluations, we have plotted in Fig. 1.63 a and b this switching speed parameter as a function of Vc-Vth for n- and p-channel transistors respectively. The magnitude of Gmsat/Cc for the n-channel transistor with the NO gate insulator is comparable at low gate drive to that of the pure oxide, but a striking improvement is obtained at higher-field. The highest switching speed of 2.10^ s"! is obtained at 3.5 V and is 9% higher than that of the control device. The p-channel transistor drive characteristics increases after nitridation. This is due both to a gate capacitance increase and to an absence of degradation of the high-field hole mobility. The preservation of carrier mobilities, especially that of holes, in both the linear and saturation regimes can be related to the very low level of Nit, Nf and traps introduced by the LP plasma nitridation, in contrast with other (thermal) nitridation processes in ammonia.

PMOS K/1

C/5 OS

o

o o

Nitrided Oxide

I

I

o 1 V

o o

r

o

o 0 (a)

3 4 5 VG-Vth(V)

1

- j -

(b)

Oxide

1 ll 3 4 5 VG-Vth(V) L.

Fig. 1.63 - Saturation transconductance normalized by capacitance is plotted versus gate drive (V^ = ± 3.5V) (a) for an n-channel MOS transistor; (b)for a p-channel MOS transistor (After [233]).

This weak degradation of the interface can be explained by the low nitrogen content in the bulk and in the interface region. Furthermore, it has been shown that plasma nitridation leads to a reduction of donor interface states near the valence edge [12]. Because of this reduction of Njt, the contribution of interface states to hole scattering is thought to be reduced and this compensates the contribution of the few fixed charges introduced by nitridation. 5.8. CONCLUSION AND APPLICATION TO VLSI CIRCUITS Many techniques have been proposed to nitridate thin oxides in ammonia.

82

B, Balland and A. Glachant

The HP process results in the incorporation of nitrogen below the surface, in the bulk and at the Si02-Si interface. The amount of nitrogen incorporated increases with nitridation temperature and duration. HP films offer two consecutive barriers against oxidation and impurity diffusion. However, the HP nitridation of thermal oxides is responsible for an increase in the positive fixed charge, a significant increase in the density of electron traps and a reduction of channel mobility. The LP process leads also to the incorporation of nitrogen, but mainly below the surface of the film. The LP films thus offer only one effective barrier against oxidation and impurity diffusion. The drawbacks of conventional thermal nitridations (HP and LP) processes are higher interface states densities, higher fixed positive charge densities, and the incorporation of a large amount of hydrogen atoms in Si02,which leads to an increase in electron traps. Plasma nitridation increases the high-field transconductance of p-channel devices in contrast with other thermal nitridation processes. The specificity of the LP plasma-enhanced nitridation method, is that the reactions take place essentially at the outer oxide surface while the nitrogen content can be maintained very low in the oxide bulk and at the interface. This is thought to explain the excellent transport properties found in n-and p-channel devices featuring an LP-PE NO gate insulator. Let us mention also that NO films display a better stability under high field stress (FN current injection) and a greater dielectric strength, than regular oxide films. Because of their unique properties, NO films have been used to fabricate various MIS devices, such as: • MIS transistors with Leff = 1.5 |Lim (using a 10-nm-thick plasma NO film [120]); • a 16-kb EPROM structure (using a 6.5-nm-thick re-oxidized NO film) having better performances than those built with a conventional oxide [180]; • MIS transistors with Leff = 4.0 |im (using a 10-nm-thick thermal NO film) displaying a high resistance against irradiation [181]. 6. THERMALLY REOXIDIZED NITRIDED OXIDE FILMS We have seen in Section 5 that during the nitridation of silica in NH3 the incorporation of hydrogen atoms, which act as precursors of electron traps, is unavoidable. The reoxidation of nitrided-oxide films has proven effective in reducing the density of incorporated H atoms. It has therefore been investigated [243-259, 281] as a technique to minimize bulk electron trapping and to reduce interface states, without affecting other properties. The obtained films are called ReOxidized Nitrided Oxide (abbr. RONO) films. They still behave as excellent diffusion barriers and display a better endurance under hot-carrier stress. They are also shown to improve the transconductance of n-channel transistors.

Silica, Silicon Nitride and Oxynitride Thin Films

83

6.1. PROCESSES USED

Mostly two methods are being used to obtain RONO films: furnace annealing in dry oxygen and rapid thermal annealing in dry oxygen. • Furnace annealing in dry oxygen Studies on the fumace nitridation of thermal silica layers, at high temperatures, followed by a reoxidation step have shown very promising results. Conventional annealing in dry oxygen in a quartz-tube fumace can be used (as illustrated in Fig. 1.44). Its major drawback is a considerable redistribution of impurities [243249]. Typical reoxidation cycles are 15 min in O2 ambient at 950°C, resulting in a film thickness increase of less than 0.5 nm. Longer reoxidation times are used mostly to understand reaction kinetics, and the evolution with time of the film composition. • Rapid Thermal annealing in dry oxygen An annealing in dry oxygen using the so-called Rapid Thermal Process (RTP) has many advantages because it can be well controlled. This process shall be described in Section 7. 6.2. FILM COMPOSITION

As discussed in § 5.3, NO films resist oxidation. Reaction kinetics and film composition can be studied by using long reoxidation times (e.g. 60 min at T = 950''C) [249] as illustrated in Fig. 1.64 a. Figure 1.64 b shows the etching behavior (in a 100-to-l buffered HF solution) for NO films subjected to various length of reoxidation times. 6.2.1. Zones of interest As illustrated in Fig. 1.65, two zones are of interest: the top (external) surface and the filmsubstrate interface. • At the surface The study, by AES, of the influence of a low-pressure reoxidizing anneal on NO structures shows that only the nitrogen concentration below the surface is substantially reduced (30% to 50%). The top oxynitride layer of the NO film is rapidly converted back into silica. It follows that the surface etch rate of a RONO film approaches that of silica (Fig. 1.64 b). • At the film-substrate interface The oxidizing species diffuse to the film-substrate interface and react with silicon to form a thin silica film undemeath the oxynitride layer whose nitrogen concentration decreases with oxidation time and temperature. However the amount of nitrogen at the interface remains almost unchanged [246]. The RONO structure possesses oxynitride layers near both interfaces with, in addition, nitrogen distributed inside the oxide bulk. The Nitrogen [N] and Hydrogen [H] contents of RONO films have been monitored [246] using AES and SIMS, respectively.

B, Balland and A, Glachant

84 E 30 c

(D

L P-Oxide

®

(2) NO ® NO

20

E 0 c CO CO

c ^ - (D *-

10

0 o > o E C15

-D1 • ^

CO CO

U^-'

c

S

1 ,,. .

1

i

20 40 60 80 Oxidation time (min)

^NO^

~

L ® L P-Oxide ""^-^^ @

(S)

lu^

NO RONO RONO

^

® 1

N

1

L_

100 200 Etch time (s)

Fig, 1.64 - (left) Increase in film thickness during oxidation in O2 at 950^C (A t^ox) versus oxidation time: 0for a low-pressure oxide film; ®) for a nitrided-oxide film; (3) for a nitrided-oxide with surface removed, (right) Etching behavior of various types of films (in 100:1 = NH4: HF solution): (Dfor a low-pressure oxide, ® for a nitrided oxide, ®for an NO film reoxidized at 950^Cfor 15 min; ®for an NO film reoxidized at 950°Cfor 1 h. (After [249-250] slightly modified).

0 0 0 0 0 0 0 0 0

1 SiOy

1®

0 0 0 0 0 0 0 0 0

1

Si O2

00 0 0 0 0 0 0 0 1

te"

w

-w-

w

w

N2

SiwNx Si Oo

Fig. 1.65 - Model for the reoxidation of nitrided-oxide films: (I) at the external surface: 2SiOyN^ + (2-y)02 -^ 2Si02 + zJ^2(2) at the interface: Si + 02^ Si02.

Silicon Substrate 1

6.2.2. Nitrogen content AES analyses reveal that as reoxidation proceeds, [N] at the outer surface decreases quickly, while at the interface, [N] decreases very slowly (see Fig. 1.66). Moreover, the oxynitride layer at the interface moves further into the substrate as reoxidation proceeds. The distance travelled by the oxynitride layer is greater if its nitrogen content is originally smaller or if the reoxidation temperature is higher. This inward motion of the oxynitride layer at the interface is attributed to the diffusion-limited interfacial oxidation (let us note that in contrast, the annealing of NO films in pure N2 leads also to a reduction in the interfacial [N] but causes no motion of the oxynitride layer) [246].

Silica, Silicon Nitride and Oxynitride Thin Films

85

Fig. 1.66 - Nitrogen in-depth profiles measured by AES in 7. J-nm-thick RONO films. (After [245] modified) (a) The oxide samples have been nitrided in pure NH3 at T = 950''Q during t = 15 s and then reoxidized in a dry O2 (T = 950°C )for various times (tfox)trox =0 s (-), trox = ^^ s (---) and

(a)

trox = 60s(

j,

(b)The oxide samples have been nitrided in pure NH3 at T = 1150°C, during t = 60 s and then reoxidized in dry O2 (T = 1150°) for various times (tfox)-' trox =0(-),trox

=15s(---),

trox = 60s( ; a n d 2 0 0 s ( - . - . -). Crosses indicate the positions of the interface between the Si and the N-rich layer near the Si02/Si interface.

10 (b)

Depth

15 (nm)

6,2.3. Hydrogen content Hydrogen introduced during annealing in NH3 is reduced during post-annealing in O2 via the following reactions: 2 (=Si-H) + O-^ = Si-0-Si = + H2

(1.10)

= Si'H + HO-Si = + O ^ = Si-0-Si = + H2O

(1.11)

SIMS analyses reveal that, as the reoxidation of NO film proceeds, [H] decreases and the film thickness increases. Concentration [H] is found to decrease more rapidly if [N] is originally lower or if reoxidation temperature is higher. For example, [H] = 1.8 lO^O/cm^ in a thermal oxide film, [H] = 1.6 lO^Vcm^ in nitrided oxide film and [H] = 1.6 lO^O/cm^ in RONO film [242-246].

86

B, Balland and A, Glachant

6.2A. Boron diffusion Boron diffusion through RONO films has been studied by fabricating 100 |Lim x 100 |Lim boron-doped polysilicon capacitors. The results of quasi-static C-V measurements performed on these capacitors are shown in Fig. 1.67. The threshold voltage of RONO capacitors is 0.14 Volt higher than that of NO capacitors indicating that about 3 x lO^^ boron atoms have diffused per cm^ through the RONO films [18].

1.0

0)

o

0.8 -

o

(0 Q.

©"

CO

O XJ

0.4

75 E 0.0 -2.5

1

1

Fig. 1.67' Quasi-static C-V curves measured on MIS capacitors (with a borondoped polysilicon electrode) fabricated on a: 0) silica film, ® nitrided oxide film, (3) reoxidized nitrided oxide film. (After [18] slightly modified).

2.5

0.0 Gate voltage (V)

6.3. THE ELECTRICAL PROPERTIES OF RONO FILMS

The reoxidation step slightly modifies the electrical properties of the nitrided oxide films (as well as those of the underlying channel if the NO film is used as a gate oxide in a MOSFET) [232-233]. 6.3.1. Electrical conduction Electrical conduction in RONO films has been measured by using a stepped ramp I-V technique [251] on capacitors with a boron-doped polysilicon electrode. The resulting I-V characteristics are shown in Fig. 1.68, for RONO structures of three different thickness, with an increasing negative gate voltage (the silicon surface is in accumulation) applied until the capacitors break down. The low-level leakage current is found to increase with decreasing RONO thickness. The leakage currents measured in RONO films are generally more than one order of magnitude greater than those measured in thermal oxides. Large initial leakage in RONO is attributed to an energy barrier lowering due such causes as: a pile-up of nitrogen in the interfacial region [254], Frenkel-Poole conduction, field ionization from trap-assisted tunneling or a combination of these processes. No clear mechanism for low-field leakage current in thin RONO has been reported so far. The FN tunneling of electrons is still the dominant conduction mechanism encountered in RONO films (Fig. 1.68).

Silica, Silicon Nitride and Oxynitride Thin Films

87

Fig. L68-I-V characteristics of three RONO structures compared to that measured for a 10-nm thermal oxide (after [251] modified]).

8

10

12

14

Gate voltage (V)

63.2. Interfacial charges The mobility of channel electrons has been measured on large geometry (100 |im x 100 |Lim) n-channel MOSFETs fabricated with: regular oxide, NO and RONO films and with a channel doping of about 10^^ cm"^. The mobility of channel electrons is found to be lower for NO films, whereas with RONO films the mobility approaches that of MOSFETs using Si02 films [233]. This observation is consistent with the presence in RONO films of a thin Si02 layer at the dielectric-substrate interface. The fixed oxide charge density of RONO films should thus be similar to that of LP Si02 films («10^ cm-2). 6.4. INSTABILITIES IN (RONO) FILMS UNDER STRESS

6.4.1. Capacitance-voltage curves after stress The C-V curves shown in Fig. 1.69 have been measured before and after FN constantcurrent stress. NMOS capacitors have been stressed by electrons injected by the gate electrode (VQ < 0) or by the silicon substrate (VQ > 0). It is clear from the distortion of the quasi-static curves and the stretch-out of the high-frequency curves, that for equivalent stresses, the RONO dielectric exhibits much less degradation. 6.4.2. Interface state generation under stress C-V curves have been measured before and after FN - CC stress (Fig. 1.69), to determine ADit, the amount of generated interface states (using the high-low frequency method). The resulting distribution of interface states in the bandgap, after stress, is shown in Fig. 1.70. The difference in the shapes of the RONO and Si02 spectra could be attributed to the fact that the damage levels are different. Although the two dielectrics (NO and RONO) have a similar interfacial nitrogen content, they display a significant difference in their ability to suppress the generation of interface states.

88

B. Balland and A, Glachant

^30

0 1 2 Gate voltage (V)

(a)

(b)

0 1 2 Gate voltage (V)

Fig. 1.69 - HF and LF C-V curves of NMOS capacitors measured before (-) and after (—) a 10'"^ Acm'^ constant current stress applied during 5000 s. (a)fora Il-nmSi02 sample, (b) for all-nm NO sample (nitrided at 950°C), (c)for a U-nm RONO sample (reoxidized at 950°C). (After [248] slightly modified). -1 (c)

0 1 2 Gate voltage (V)

• Generation when electrons tunnel from the silicon substrate to the gate contact Figure 1.71 shows the plot of log (ADit) vs log (F), where the fluence (F) is the number of carriers injected per unit area or tunneling through the gate dielectric (F is the current density multiplied by the duration of the stress). By examining the slope of the resulting curve, it is possible to learn about the rate-limiting step of the interface state generation process. Following a positive gate bias stress, the increase in Da measured at midgap on a PMOS capacitor, is found to be linearly dependent on fluence, for low injected fluences: ADit = KA.FlO

(1.12)

where KA is the generation efficiency. As the fluence increases, the rate of interface-state generation decreases and ADit approaches a maximum values Dit,niax» although it never completely saturates. This suggests that ultimately is the number of (interface state) precursors that determines the magnitude of ADit. Fo^* high fluences, the damage is not linear with fluence, but described by: ADit = ^it^m^x

[1 - exp(

-KA.F]

(1.13)

Silica, Silicon Nitride and Oxynitride Thin Films

89

10

\W>

s

^

4

1

(DV^^^^^^

>

It

1

—

e

f-H i-H

o

^

=: 2 o

r-H

HI 1

<S ' L-

-0.4

a)

1

-0.2

1

0.0

_l

1 V il 0.2 0.4

E - E M G (eV)

-0.4

b)

^

-0.2

1

1

0.0

0.2

\ *

Vi 1 0.4

E-EMG(eV)

Fig. 1.70 (a) - Distribution Dn vs energy measured for several NMOS capacitors after a 10-^ A/cvffi CCS applied for 5000 s: (D oxide film, ® NO film (oxide nitrided in NHs at T = 950''C, P = 0.1 atm, for Ih), ® RONO film (NO reoxidized in 02atT= 950°C, P = 0.1 atm, for 3h). (b) Dif vs energy measured: Qfor an oxide film after a 10-"^ A/cm^ CCS applied for 200 s, ©for a RONO film after a 10-^ A/cm^ CCS applied for 20 000 s. (After [248] slightly modified).

Equation (1.13) simplifies into Eq. (1.12) at low fluence. When the change in the number of remaining precursor sites is small, which is the case at low fluence, the generation rate is a constant. KA is the low-fluence interface state generation efficiency, and is dependent on thickness, electric field, temperature and processing history. • Generation when electrons tunnel from the gate contact to the silicon substrate As illustrated in Fig. 1.71, after an NMOS capacitor is submitted to an electron injection from the gate, the increase in interface state density is not linear with fluence, but varies as: ADit^KB.F0 5

(1.14)

Under negative-bias stress, interface states are generated via a different mechanism. This weaker dependence on fluence is explained by considering that these interface states are due to the breaking of strained chemical bonds. When a strained bond is broken, the surrounding lattice relaxes reducing the strain in adjacent bonds. Thus, when one interface state is created, the probability that another defect be created nearby decreases [248]. • Transient response of RONO films For RONO films, ADit is not stable inmiediately following an FN injection. For positive-bias stress, ADit is found to increase once the stress has ceased, while ADit decreases after stress if a negative-bias stress has been applied. Thus, a delay of several hours is necessary after the stress to measure the post-stress C-V curves which allow one to calculate Dit.

B. Balland and A. Glachant

90 1000 1

^

»

•

'

» » 1

1

1

: o ---•

o —•

Q—.a

©--••

^^

1

1

1

•

•

I 1*

-fr^

j

\ T

Q

100

: ® —•

9*

Ao-'

0...O

o

%/y

A

,x

,Q

.

/

/

1 10 7 1

/

1 ' * * ' - ' '

0.001

i^

'

'

/ • / '

. . . . . I

0.01

/^

4

0.1

1

1 1

m / *'

1

10

Fluence (C. cm^)

100

Fig. 1.71 - Interface state generation vs fluence for various MOS structures and various injection densities 0+10'"^ Acw? (2) ©-10-"^ Acm? for U-nm Si02 films, S)+70-^ Acm^ ® -lO-"^ Acm?for 11nm NO (950°C, 10 min) films, ®) +10-"^ Acm^ ® '10-"^ Acrn^ for 11-nm RONO (950''Q 10 min) films, ®+10-^ Acrn^ ®-10'^ Acm^ for 11nm RONO (950''C, 10 min) films. Positive-bias stress data is fitted to Eq. (1.13) (solid line) and negative bias stress data ( ) is fitted to ^^ (L14).(Afier [260] modified).

• Generation mechanisms The formation of interface states can be prevented by blocking one of the steps leading to bond-breaking at the interface, or by simply not having precursor sites at the interface. The reoxidation of NO films improves the dielectric reliability by removing the Pb- centers which are precursor sites initially present at the interface. During the nitridation step, strained Si-Si bonds are broken, and some sites are passivated with nitrogen or hydrogen. Nitrogen may also displace an hydrogen atom on existing Si-H bonds. However, short nitridations result in a large density of Pb- center precursor sites. During the reoxidation step, oxygen permeates the dielectric, replacing the remaining Si-H bonds with a stronger Si-0 configuration, and oxidizing any remaining precursor site. Thus, the RONO process first damages the Si02-Si interface (during nitridation), and then repairs it to create a more stable atomic network (during reoxidation). This explanation of how interface-states are generated in RONO films accounts for the fact that not all oxynitrides inhibit the formation of interface states under electrical stress. While most oxynitride gate dielectrics, including heavily and lightly nitrided oxides, as well as reoxidized nitrided oxides, are resistant to radiation-induced interface state generation, only a subset of these dielectrics can be made "electrically hard". The nitrogen-rich layer at the interface acts as a diffusion barrier for hydrogen and inhibits hydrogenic radiation-induced interface state generation. 6A.3. Electron trapping A quantitative relationship between the electron trap density and the [H] concentration has been established for NO films [242] reoxidized in dry oxygen at temperatures ranging from 1050 to 1150X for 15-200 s (according to process 4a, see Table 1.07 of Sect. 8). In this experiment, the trapping properties have been evaluated by injecting a charge of 0.1 C/cm^ from the substrate (using a constant injection current of 10 mA/cnfi) and by measuring the ensuing flatband voltage shift AVpB induced by the stress. The residual [H] content has been measured by SIMS (see Fig. 1.72).

Silica, Silicon Nitride and Oxynitride Thin Films

91

Figure 1.73 shows the C-V curves recorded, before and after electron injection on various but related MOS samples. One is an oxide nitrided in NH3 at 1150°C for 60 s, and reoxidized either at 1050°C or at 1150°C for 60s. A large positive shift of the C-V curve (AVpB = +1-5 V) is observed for the first sample which indicates a high electron trap density [242]. The reoxidation steps indeed reduces the amount of electron trapping. 1.0 CO

'B

0)

O

o o

o

cd

0.5

o

I

N

§

o

a o U

i 0.01

t

0.0 15

20

Depth (nm) Fig. 1.72 - Hydrogen in-depth profiles measured by SIMS in NO and RONO films. (After [242] slightly modified).

-3

-

1

0

1

2

Gate voltage (V) Fig. 1.73 - C-V curves measured before (D and after @ electron injection (Qi^j = 0.1 C/crr?) on NO and RONO capacitors. (After [242] slightly modified).

Figure 1.74 shows the correlation found between AVpB values by induced by electron injection and concentration [H] for different RONO samples. Regardless of the fabrication conditions one finds: AVFB =

K,[H]

(1.15)

where K is a constant («9.3 lO-^^V/cm^ when a charge of 0.1 C/cm^ is injected into an 8-nm-thick RONO film). The elimination of hydrogenated species by reoxidation reduces indeed electron trapping. The reoxidation step appears also as promising in reducing electrical instabilities due to electron trapping, RONO films appears "superior", (i.e. display lower charge trapping) compared to other insulators, at high fields and for injected fluences > O.lC/cm^. They appear, however, "inferior" (i.e. display higher charge trapping) at low fields. Generally speaking, background electron trapping dominates all observations at lower fields (experimentally, < 7 MV/cm) for any nitrided structure.

B. Balland and A. Glachant

92 1.5

4^A

• RONO(1) A RONO (2)

A

Fig. 1.74 - Correlation observed between the flatband voltage shifts AVpB induced by an electron

• Oxide CO

injection of 0.1 C.cm'^ and the hydrogen concentration [HI measured in various RONO samples.

1.0

u.

.?-;

> 0.5

RONO (1) (oxide nitrided at 950''Cfor 60 s and reoxidized at lOSO^'C, and RONO (2) (oxide nitrided at 1150°C for 60 s and reoxidized at USO^'C). (After [246] slighly modified).

A%

0.5

1.5

1.0 21.

Concentration [H] (1 0 at.cm ^) 6.5. CONCLUSION

The reoxidation of NO films brings other advantages not mentioned above. It reduces the fixed oxide charge and increases the charge to breakdown. However the property most often seeked in RONO films is their ability to improve the stability of insulating films under stress and for many RONO gate dielectrics, their ability to suppress interface-state generation (ADit) under a variety of electrical and radiation stresses. 7. THIN DIELECTRIC FILMS FABRICATED BY RAPID THERMAL PROCESSES The nitridation and reoxidation processes, when carried out in a fumace, suffer from a dual handicap: they require a prolonged treatment at high temperature, and the risk of incorporating unwanted impurities and interfacial stress is high. An alternative technique based on rapid thermal processes has shown great potential, which we explain next. 1.1. PRINCIPLE

As illustrated in Fig. 1.75, the abbreviation RTF refers to the use of a broad range of energy sources to heat rapidly (1-100 s) and isothermally materials used in semiconductor and IC processing. Rapid Thermal Frocessing (RTF), originally introduced to anneal ion implantation defects, has since proved useful for a variety of additional applications [243]. Indeed, as device dimensions decrease (from micrometer to submicrometer devices), low "thermal budgets" are necessary to limit dopant diffusion. There exist then two solutions: • either to use low-temperature processes, enhanced by: photons, plasmas, etc. (see Sect. 9), • or to use RTF processes in which high temperatures are applied for short durations (typically a few seconds). Figure 1.76 shows schematically the time-temperature regime available using RTF.

Silica, Silicon Nitride and Oxynitride Thin Films

Names used Annealing Heating Processing

Time scale

T profile

Fast Rapid Short time Transient

Isothermal

93

Heating devices Flash lamp Heat pulse Incoherent light Infrared lamp Optical furnace Thermal furnace

Fig. 1.75 - An overview of terms used to describe Rapid Thermal Processes.

The RTF processes described next have been used to manufacture thin silica films (RTO), thin nitride films (RTN), thin nitrided oxide films (RTNO) and thin reoxidized nitrided oxide films (RTONO). They can also be used to fabricate composition-tailored insulators [243]. The cleaning (RTC) and the annealing (RTA) of the wafer can usually also be performed in the same apparatus.

^

Fig. 1.76 - Schematic representation of the time-temperature ranges used for Furnace Processing (FP), Rapid Thermal Processing (RTP) and Very Rapid Thermal Processing (VRTP) (after [244]).

1500 VRTP RIP

I-

FURNACE 500

H X -1

1

X

2

3

Log (time) (s)

4

Nota - Annealing for less than 1 second is indicated as a separate regime. Very Rapid Thermal Annealing (VRTP) is not currently accessible in most RT processing modules.

7.2. APPARATUS

Figure 1.77 shows a schematic cross-section of a single-wafer, rapid thermal processing module. In this module, heating is provided by a bank of tungsten-halogen lamps and temperature is monitored using an optical pyrometer for temperature measurement and a feedback system for controlling the power supplied to the lamp bank. The wafer is held by quartz pins and the reactive gas flows from the gas inlet (right) to the exhaust (left). This apparatus allows one to perform several processes sequentially in the same chamber. The small size of the chamber makes possible quick changes in reacting gases, while the substrate temperature, rather than the gas flux, switches on and off the chemical reactions. A computer controls the temperature between 700°C and 1200°C for reaction times between 0 and 300 s, and also selects which gas or combination of gases flows into the quartz chamber, which provides another degree of process control. The wafer is kept at high temperature only during the active chemical reaction and is kept at lower temperature during the gas purges.

94

B, Balland and A. Glachant

.«—

Lamp bank-

Process gases

wafer insertion removal

quartz tray quartz tube

pyrometer

Fig, 1.77- Schematic cross-section of the reaction chamber of an RTF module. (After [245] slightly modified).

Figure 1.78 illustrates typical temperature-time profiles used while, in Table 1.05, the gases used for each step are indicated. Gases most frequently used are ultra pure nitrogen, oxygen, hydrogen chloride, forming gas and ammonia. For example, RTC/RTA or RTO/RTN processes consist of two temperature steps. The first step is used to stabilize the system, typically at 775°C. The chemical process takes place during the second step, at a higher temperature, and lasts between 0 and 300 s. 1200

1

1

ei 1000 llOO^Ci o

1

•

3

1

1

1

1150*Q 1150*0/—I /; I

r

""

loso^Ci

i i 770*c\

I

1

CO

V'

L^

V.

0) Q.

r

RTA time

^

time

E 02-

0)

NH3 or N2.

-^r^

-H

(0

J

24

Wafer loading

Air

48

r

I

72

I

I

96

I

I

120

I

L_i

L

144 168 Time (s)

RT Oxidation

Rapid Thermal Cleaning

Fig. 1.78 - Wafer temperatures and gases used as a function of time for a typical RTC/RTO/RTA process in Ar or N2 (or RTN in NH3) (After [246] modified).

RT Annealing

RT (Oxy)Nitridation

Ar/10% H2

O2

N2

NH3

Ar/10% H2/O.5 -1.0% HC^

O2/I - 4.0% HC^

Ar

(NO)

N2/2% HCm.5% O2

(N2O)

Table 1.05 - Typical gases used for the RTF growth of oxides, nitrides and oxynitrides [246].

Silicay Silicon Nitride and Oxynitride Thin Films

95

13. RAPID THERMAL CLEANING

Native oxides encountered at the surface of silicon usually contain metallic impurities which may contaminate the silicon substrate during further steps. Moreover, the presence of a native oxide renders the manufacturing of very thin oxides difficult to control. Rapid Thermal Cleaning (RTC) allows for the reduction of native oxides and enables some silicon etching prior to growing Si02 film. It is typically performed at a temperature between 1000°C and 1150°C for 2 to 10 s. The gases used for RTC are Usted in Table 1.05. A chemical oxide {- 1-nm-thick) grows during the standard (liquid) cleaning process for which such solutions as ammonium hydroxide/hydrogen peroxide, hydrochloric acid/hydrogen peroxide, and sulfuric acid/hydrogen peroxide are used. By using the RTC process, it is possible to reduce this chemical oxide and thus to obtain, in-situ, an ultra clean silicon surface prior to film growth. It follows that wafers can be transported from the standard cleaning station to the RTP equipment without the need to perform a buffered oxide etch prior to oxidation. During a thermal treatment in an 02-free ambient (less than 100 ppb of oxygen), the thin chemical oxide is reduced by reaction of the Si02 film with the Si of the substrate and the formation of volatile SiO species following: Si + Si02-^2SiOT

(1.15)

SiO is volatile at temperatures above 750''C. When the Si02 film is removed, the silicon wafer starts to etch, in a low O2 partial pressure: Si + 02-^2SiOT

(1.16)

In an Ar/10% H2 ambient, the reduction of chemical oxides proceeds at rates shown in Table 1.06. These data show that RTC can be accomplished in a matter of 2 to 5 s at a steady state temperature (RTC etch rate), while 10 to 40% of etching takes place during the temperature ramp (ramp-up etch). Argon serves as an inert carrier gas, while it is believed that H2 reduces Si to gaseous SiHx and also allows for the formation of O and SiO. This cleaning eliminates also metallic impurities which adhere to the silicon surface, by forming the corresponding metal halides.

1

Temperature (°C)

Etch rate during T ramp (nm/s)

1150

0.4

0.1

1100

0.3

0.04

1050

0.2

0.015

1000

0.05

0.005

950

Etch rate at constant T (nm/s)

0.002

Table 1.06 - Etch rates of chemical oxides during Rapid Thermal Cleaning in Ar/10% H2, as a function of temperature

96

B, Balland and A, Glachant

The kinetics of silicon etch in an H2/HC^ ambient can be represented by a series of adsorption-desorption reactions and the subsequent chemical reaction of the absorbed species. The potential reactions are represented by : nHC/^ + Si —> SiC/n * + nif *

(1.17)

l/2H2(g)-\- *"->if*

(1.18)

(2x-4)m + (4'X)HC/'' + Si (s) —> SiH^Cf'4.^ (g)

(1.19)

SiH^C/^4-x (g) - > SiH^ C/4.X (g)

(1.20)

where * designates a free site on the surface. These kinetics have been studied for conventional FG cleanings and should be the same for RTC because in both cases they are thermally driven. The gas mixture containing HC^ has been found to produce some pitting of the silicon. Thus an optimum cleaning process has been developed whereby any chemical or native oxide is first reduced in Ar/10% H2, followed by a treatment, for 2 to 5 seconds, in Ar/10% H2/0.5% HC^. 7.4. RAPID THERMAL OXIDATION OF SILICON

Using conventional oxidation techniques (i.e. thermal FG-oxidation) silica can be obtained in very thin layers either by lowering the growth temperature or by diluting the oxidizing gas and/or by reducing pressure (see § 2.3.1). However, the oxydation of silicon at temperatures below 900°C generates large compressive stresses and a large fixed oxide charge. Moreover, a considerable amount of moisture is incorporated into the silica film during the boat-loading and unloading steps. Unless water is fully removed from the film, hydrogen forms centers which act as electron traps and degrade the film quality (see Chap. 2 of Vol. 2 of this book series and Chap. 11 of this volume). Traditional FG-oxidation is thus becoming more and more difficult to use, to grow very thin gate insulators (VTGIs). Rapid Thermal Oxidation (RTO) has proved a very attractive and efficient technique to grow device-quality thin Si02. We present next its principle and we compare some physical and electrical properties of oxides obtained by RTO to those of conventional (FG) oxides. 7.4.1. Basic process Nulman et al. succeeded for the first time in 1985 to grow thin Si02 film by RTO [250251]. Since then many publications have dealt with RTO [137, 244-282]. • Apparatus Thin RTO films are grown in a well-controlled oxygen ambient. The gas flow is monitored by computer-controlled mass flow controllers. The RTF chamber (Fig. 1.77) is equipped with tungsten-halogen lamp heaters. The reaction chamber is a quartz tube. The temperature is controlled with an in-situ thermocouple and a microprocessorcontrolled feedback system and/or with a calibrated optical pyrometer. A reflector can be used to provide a uniform heating of the wafer.

Silica, Silicon Nitride and Oxynitride Thin Films

97

• Procedure Silicon wafers are chemically cleaned and then "spun dry" in an N2 ambient. Wafers are introduced in an N2-filled quartz chamber and the oxygen gas flow is switched on. Oxidation is carried out in a pure oxygen ambient or in oxygen with 4% HC^. A first heating step is carried out at 800°C for 30 s in order to stabilize the process conditions (Fig. 1.78). The oxide grows during a second step, set at 1150°C for a duration of 5-30 s. This temperature has been chosen in order to achieve optimum chlorine gettering. This two-step approach lets the wafer reach the oxidation conditions in the shortest possible time (the heating and cooling rates are typically + 100°C/s and -60°C/s respectively). Once the oxidation step is completed, the oxygen flow is discontinued and nitrogen is introduced. After a short purge period, a similar two-step process, but in N2, follows. This last high-temperature post-oxidation annealing step, typically performed at 1050°C, stabilizes the Si02- Si interface and reduces the interface state density. 1A.2. Thickness uniformity The thickness of RTO films, measured by means of either a Nanospec apparatus or an ellipsometer, has been found to be as uniform across the wafer as in the case of conventional FG oxides. This uniformity depends on how the temperature is distributed across the wafer diameter. A fairly uniform thickness can be obtained from center to about 10 mm from the edge regardless of the ramp rate. In the outer ring, the thickness drops significantly (by more than 15%) due to radiative heat loss mechanisms. A good thermal repeatability of the two-step RTO process is ensured by the feedback control system. The "slip results" indicate that slip dislocations are generated more easily at higher temperatures and for faster temperature ramps. RTO can be a slip-free process in a wide range of process temperatures and times, if the transient and steady-state temperature gradients, particularly near the wafer edge, are eliminated. 7.4.3. Growth kinetics Figures 1.79 a and b show how the thickness of an RTO film varies as a function of oxidation time. Figure 1.79 b also shows the growth enhancement resulting from an addition of 4% HC^ to the oxidizing ambient. In the RTO process, oxide growth starts during the temperature ramp-up portion of the RTF cycle resulting in a thickness off-set (- 2.8 nm) at zero RTO time. This initial oxide protects the silicon surface from being etched by chlorine (which would result in pitting of the silicon surface) [246]. •Growth rate Figure 1.80 shows how the oxide thickness typically varies as a function of oxidation time for temperatures between 800''C and 1150°C in a pure dry O2 ambient, obtained from a one-step RTO cycle. Growth data, such as those of Fig. 1.80, shows that the growth rate, initially very fast, decreases with oxidation time (i.e. with oxide thickness). The linear regime is followed by a fast parabolic regime before growth become linear again. The second linear regime corresponds, at high temperatures, to the linear oxidation kinetics described by Deal and Grove. The oxidation models, conceived for oxides grown over long periods (see e.g. Chap. 1 of Vol. 1 [10]) cannot accurately predict the growth kinetics of RTO. This is because transient physical processes, other than simple one-species

98

B. Balland and A. Glachant ^i ,''

E c

,'3''' .--'''I

S 10 S 8 o

'£

^^

6 •

4 0

10

(a)

20 Time

30 (s)

.,

^

•

1

r •

r

•

10

15

1

20 25 30 RTO Time (s)

1150^0

Dry Oxygen One step E S15

1100^C

1050**C

Fig. 1.79 - Typical growth rates of RTO films (a) The thickness of an RTO film is plotted as a function of oxidation time (on a linear scale) during the initial growth regime (T = IISO^'C). (b) The thickness of an RTO film is plotted as a function of RTO time at a temperature of 1150°C in dry O2 (^ and in O2 with 4% HC/ (D). (After [246] slightly modified).

Fig. 1.80 - Typical growth rates of RTO films at temperatures between 800°C and 1150°C, in dry 02.(After [246] slightly modified).

80

100

120

140

RTO Time (s)

diffusion and interface reaction, may play an important role. The results shown in Fig. 1.80 disregard the ramp-up growth and the native oxide.

Silica, Silicon Nitride and Oxynitride Thin Films

99

10 • EA = 1.27 eV

8

• EA = 1.44 eV o EA = 1.71 eV

'co 6 E c 0)

Fig. 1.81 - Arrhenius plot ofRTO growth rates (nm/s) versus 1/kT (eV)'^ for the linear regime (10-sec window), for various RTO apparatus. (After [249] modified).

7.5

8.0 1/kT (eV ')

• Activation energy For RTO temperatures between 900°C and 1150°C and times less than 20 s, the oxidation rate in the linear regime has an activation energy of « 0.9 to 2 eV [246247] as shown by the Arrhenius plot of Fig. 1.81. 7.5. COMPARED ELECTRICAL PROPERTIES OF R T AND F G OXIDE FILMS

7.5.1. Conduction properties To compare the conduction properties of RT and FG oxides, MOS capacitors have been fabricated with both types of thin (8 -10 nm) films. The electrical characteristics of the films have been assessed by I-V and C-V measurements. Typical I(V) and C(V) curves are given in Figs. 1.82 and 1.83. • I(V) curves Three consecutive voltage ramps have been applied to the virgin RTO structure, up to 10 volts. As visible in Fig. 1.82, these ramps cause no visible degradation of the film characteristics. A fourth voltage ramp applied up to 12 volts leads to destructive breakdown. The same four ramps have been also applied to an FG oxide. The I(V) curves shown in Fig. 1.82 are similar but significant consequences of voltage stress are seen both in the base leakage current and in the Fowler-Nordheim region for the FG film. The lack of shift of the I(V) curves for RT oxides is a consequence of the very low trap generation as compared to FG oxides. The parts of the I(V) curves which correspond to FN conduction display indeed two distinct slopes. The last voltages in the curves of Fig. 1.82 correspond to destructive breakdown [245 - 246]. • C(V) curves High-frequency (1 MHz) C(V) measurements yield in both cases (RTO and FGO) a flat-band voltage value of « - 0.9 volt (this VpB value depends on the substrate resistivity) and a total flat-band charge of 2.5 10^ cm-2. An example is shown in Fig. 1.83 (curve 3).

100

B. Balland and A, Glachant

A shift of -0.15 volt in VpB is observed when the sample is stressed under 15 V at 300''C for 15 min. A AVpB of +0.10 volt is observed on a control sample which has been postannealed in N2 in a furnace.

Fig. 1.82 ' I-V curve measured on MOS capacitors: • with 10-nm thick FG oxide (for four consecutive I'V ramps) •with 10-nm thick RT oxide (for four consecutive I-V ramps) (After [243]). The M(RT)OS capacitor is in a virgin condition before the first ramp. The current values for the first four ramps overlap exactly until catastrophic breakdown is allowed to occur (during the fourth ramp only).

9 1 2 Gate voltage (V)

The effects of RTC on the electrical properties of Si02 films have been studied by comparing C-V data for films grown by RTC/RTA with and without RTC. Figure 1.83 shows such curves for a 16-nm Si02 film grown at 1150°C in dry O2 and subsequently annealed at 1050°C in N2 for 31 s. A reduction of interface states is clearly indicated in the C-V curves of Fig. 1.83 (curve 1) by the sharper transition from charge accumulation to inversion for the wafer with RTC compared to that without [243]. From I(V) and C(V) measurements we can conclude that the dielectric strength and the quality of the Si02-Si interface in RT oxides are equal to or better than those of comparable FG oxides.

Fig. 1.83 - C-V curves of MOS structures. (Dforaie.O-nmoxide (RTC-RTORTA). ® for a 16.0-nm oxide (RTORTA). ®for a 10.9-nm RT oxide (grown at 1000°C in a dry O2 ambient for 80 s). Both HF and LF curves are shown. (After [243] slightly modified).

-1

0 1 Gate voltage (V)

Silica, Silicon Nitride and Oxynitride Thin Films

101

7.5.2. Interface trap density The interface trap distributions of FGO and RTO films are compared in Fig. 1.84. Diluted and wet FGO samples have nearly U-shaped Dit distributions. RTO samples have similarly shaped distribution with smaller Dit concentrations than FGO samples. The Dit distributions of FGO and RTO samples become nearly equal as the RTO temperature is decreased and no difference is observed when oxidation takes place at lOOO^'C. RTO films formed at 1200°C show the largest decrease in Dit, in the upper side of the Si02 bandgap (Fig. 1.84). This decrease is however not due to the type of oxidation process but to the oxidation temperature itself.

Fig. 1,84' Distributions of interface traps in FGO and RTO

films: (D Wet FGO (850''C) grown in a 1:1 H2/O2 ambient, ® Dry FGO (800°C) grown in a 2:1 N2/O2 ambient, 0) FGO (950°C) in dry O2, ®RTO (lOOO^'C) in dry O2, ®RTO (llOO'^C) in dry O2. (After [243] slightly modified).

0.4

0.6

0.8

1.0

1.2

Surface potential (V) The Dit values found for p+-polysilicon gate MOS structures are more than one order of magnitude above those of similar n+-polysilicon gate structures. This significant degradation is apparently caused by the penetration of boron atoms into the ultra thin gate oxide. This penetration not only degrades the interfacial properties but also may enhance carrier trapping in the gate insulator and reduce the device lifetime. 7.5.3. Dielectric strength Distributions of breakdown field values measured on FGO films are centered around 11 MV/cm while similar distributions for RTO films are shifted by about + 1 MV/cm. Moreover, some RTO capacitors display breakdown fields above 12 MV/cm and an average charge to breakdown (QBD) value of 50 C/cirfi (at a stress current density of 1 A/cm^).

102

B, Balland and A. Glachant

In time-Zero Dielectric Breakdown (TZDB) tests, a negative voltage ramp is applied to the gate electrode and the breakdown voltage is defined as that voltage reached across the oxide when a leakage current of 1 |iA is measured [243]. In Fig. 1.85 the TZDB characteristics of an FGO film grown at 950°C in dry O2 and an RTO film grown at lOOO^C in dry O2, for two thicknesses (7.5 and 9.8 nm) are compared. The TZDB of RTO films is better than that of FGO films on two counts: (1) low-field (< 1 MV/cm) and medium-voltage breakdown rarely occur in RTO films; (2) the maximum breakdown frequency occurs at higher fields in RTO films [243]. 80 o c

0) 3

RTO - — FGO

60

cr o 40

c o 20 •o

1 1 1 1

1 1

—

1 "-n

CO

o (a)

0 5 Breakdown

10 15 field (MV/cm)

CD

(b)

"%

T _ "

!

1

0 0

5

Breakdown

10 field

LJ

1

15

(MV/cm)

Fig. 1.85 ' Time-zero dielectric breakdown histograms measured on MOS capacitors fabricated with RTO and FGO films. The film thicknesses are (a) 7.5 nm and (b) 9.8 nm, respectively [243].

In Fig. 1.86, the time to breakdown (tBo) data, measured on 9.8-nm-thick oxide films fabricated by different techniques, have been plotted versus Jinj, the density of the injected current. Time tsD is found to vary as l/Jinj^'"^. We note that the values of tsD for RTO films are consistently larger than those of FGO films and that they increase when oxidation temperature increases. These larger tsD values have been explained by a reduction in the amount of defects, especially strained Si-O-Si bonds and Si dangling bonds at the Si02-Si interface, due to the higher oxidation and anneal temperatures used in the RTO process [243]. 7.5.4. Role of annealings As shown in Fig. 1.87, the rapid post-oxidation thermal annealing, in Ar + N2 or Ar + O2 at lOSO'^C, of RT oxides, results in a rapid decrease in VpB whose value approaches the ideal work function value. This decrease is correlated to a decrease in Dit (below 10^^ eV-^cm-^ after 40 s for RTO compared to 5.10^^ eV-^cm-^ for FGO). Similarly, the average breakdown field of annealed RT oxides has been observed to increase to a value of 15 MV/cm, as compared to 13.5 MV/cm for FGO.

Silica, Silicon Nitride and Oxynitride Thin Films

103

Fig. 1.86 - Mean-time-to-breakdown (tQp) values versus injected current density (Jinj)' Oxidation conditions are shown as a parameter: 0FGO (diluted, 800°C), a>FGO(wet,850''C), (3>FGO(dry,1000°C), ®RTO(dry,1000''C) ®RTO(dry, 1200''C). The film thickness is 9.8 nm. (After [243] slightly modified).

10" 10 Injected current density

10

(AcmO

A post-oxidation RTA, as short as 10 s, has been shown to reduce both electron and hole trapping. A low-level nitridation takes place during RTA in nitrogen. RTA in NH3 (as discussed in the following section) results in films with better properties than those annealed in N2. The QBD value measured on 10-nn oxides increases from 20 C/cnfi for FGO films to 80 C/cm^ for RTO/RTA films [246]. Since QBD is directly correlated to electron trapping in Si02, it is concluded that electron trapping on water-related centers occurs at a much smaller rate in RTO films annealed in Ar + N2 and Ar + O2 than in FGO films. By comparison, hole trapping is optimally reduced by RTA in Ar + O2 for (longer) times of 100 s at a (higher) temperature of lOOOX [250].

25.0 E o H 20.0 > Q

15.0 10.0

-0.25 0.0

20.0

40.0 RTA time (s)

Fig. 1.87 - Illustration of the influence of the post-oxidation RTA time on the flat band voltage (upper curve) and on the breakdown field (lower curve) of MOS capacitors annealed in Ar + O2. (After [246] slightly modified).

104

B, Balland and A, Glachant

7.6. RAPID THERMAL NITRIDATION OF THIN OXIDES IN AMMONIA

The incorporation of nitrogen in the Si02 network of an oxide film by Rapid Thermal Nitridation (RTN) yields a nitrogen-rich surface layer, a bulk oxide with a small concentration of nitrogen, and an interface region consisting of an interfacial nitride layer and an oxygenrich layer. RTN gives oxides several advantages such as an increased barrier to dopant diffusion [228, 251], an increased resistance to interface trap generation under electrical stress [106], a reduced sensitivity to radiation, an increased endurance to hot-electron injection [121, 177], and a dielectric constant larger than that of pure oxides. In this sub-section, the rapid thermal nitridation (RTN) of thermal oxides films is described and the main physical, chemical and electrical properties of these films are sunmiarized. In this case, the RTA part of the cycle shown in Fig. 1.78 is replaced by RTN. 7.6.1. Basic process The Rapid Thermal Nitridation of RTO films is performed in a pure anmionia ambient (containing less than 1 ppm H2O, at atmospheric pressure, for typically less than 60 s [243]. NH3 is introduced after a 10 s purge in nitrogen at 770''C. This is followed by two hightemperature pulses [243]. The first temperature pulse is set at about 800''C, i.e. below the threshold temperature for nitridation, in order to quickly reach the actual nitridation temperature and thus reduce the early incorporation of nitrogen to an insignificant amount. The second temperature pulse is chosen between 900 and 12(X)°C with nitridation times between 3 s and 300 s. Finally, ammonia is switched off after this second step and nitrogen is introduced inside the reactor. 7.6.2. Composition of RTNO films Nitrided Oxide films, fabricated by means of the RT process (abbr. RTNO), have been studied using various techniques such as AES [216, 245, 246, 254], XPS [249], RBS, etch rate and TEM [21b] or SIMS [249-254]. Figure 1.88 shows the [H], [O] and/or [N] in-depth profiles, obtained by AES, of RTNO films nitrided at 1150°C for 3 and 300 s. These experimental results show that [N] below the extemal surface tends to increase with RTN time and temperature; [N] saturates at 1.7 x lO^^ cm-^ [20f]. Generally speaking, the largest variations in the amount of nitrogen incorporated into the starting oxide film are observed for the thinnest oxide films. Nitridation is not observed for temperatures below 900°C, whereas above 1050''C, surface nitridation is accomplished in a very short time (3 s at 1150°C). Surface nitridation is essentially a reaction-rate-limited process and the ensuing [N] depends on the RTN temperature and not on the oxide thickness. For prolonged RTN, the nitrogen concentration in the Si02/Si interfacial region increases. In fact, interfacial [N] appears at the early stages of the RT process and even for the least severe nitridation conditions (950''C, 30 s). It increases monotonically with time and slightly with temperature but does not saturate. This observation suggests that the concentration of the nitriding species at the interface is not rate limiting in the process. This interfacial N-rich layer is believed to be between 0.3-0.6 nm thick [247]. Hence the RTNO film appears as a nitride/oxide/nitride (NON) structure.

Silica, Silicon Nitride and Oxynitride Thin Films

105

During nitridation, the thinnest oxides [249] behave with time and temperature just like thicker oxide films, but depending on the values of the RTN parameters, nitridation of the bulk oxide also occurs. During the early stages of RTN, nitrogen piles up at the oxide/silicon interface, and in the final stages it distributes uniformly throughout the film (Fig. 1.88b), until complete saturation (formation of an oxynitride). No increase in oxide thickness due to nitridation is observed. Finally, the hydrogen concentration is found to increase monotonously as nitridation proceeds. The physical, optical, and electrical properties of nitrided oxides are related to the presence and the behavior of the reaction by-products in the oxide. ^ 100

RTN time = 3s

80 h Oxygen

o

100

RTN time = 300s

80

SiliconOxygen

CO

60 0)

o c o o o E o 2.5 (a)

5.0 7.5 10.0 Sputter time (min)

3 (b)

6

9

Sputter

time

12 (min)

Fig. 1.88 ' Auger in-depth profiles of a nitrided oxide, (a) RTN time of 3 s at 1I50°C, (b) RTN time of 300 s at 1150°C. The thickness of the RTOfilm is tox = lUnm. (After [245] slightly modified).

7.6.3. Optical refractive index EUipsometry is used to characterize the RTNO films as a function of RTN time and temperature. Figures 1.89 a and b show how the optical refractive index of an 8-nm-thick RTNO film varies with nitridation time and temperature. Index values are in the 1.45 -1.68 range. These indices depend on the nitrogen content. A longer RTN time results in index values above 1.7 (NON structure). 7.7. ELECTRICAL PROPERTIES OF RTNO 7.7.1. C-V characteristics Rapid thermal nitridation affects the high- and low-frequency C-V characteristics of MOS capacitors in several ways. For nitridation temperatures below 1000°C, a large negative shift is observed. For higher temperatures, the initial negative shift is smaller and tends to disappear as nitridation time increases (Fig. 1.90a). These shifts in VpB values are due to complex variations in Nf and Dit at midgap, with time and temperature, and probably to some variation of the work function difference between the gate electrode material and the Si substrate.

106

B. Balland and A. Glachant

^-''^''"•l ^

X

a> 1.7 c _


•

1.6 k

••'

> ^ • *^ o •^ 5 1.5 - .•^ «0) *« • ^

1.5 tox = 8nm

1.4

Oxide-* NO#-NON-ff-Oxy litride

1.71-

[..•-•-

. 1.

60

1

120

,.,

1

180

tox = 8nm RTN time = 120s

1

I-

RTN time (s)

(a)

1

0

1.4 L

240

' • "

-^"

RTN temp. = 1150^C ,

• •

1

800 / jj ^

I

1

1

J

1000 1200 RTN temperature ("C)

Fig. 1.89 - Optical refractive index ofnitrided oxide films versus RTN time (a) and RTN temperature (b).

4.8 RTN temp. == n50°c -n4--

•£ 4.6

^ ^Jc"^ - ^ - - ^ "

o

.-^ir

M C

'^^'

o

0 4.4

u

i

^ 4.2 a tox = lOnm

-3

-2 -1 0 Gate voltage (V)

-^^-^ ^^' .^"# ..-^r^'

1 1

.^-^

.0--

^^•^ " 960°C 900°C

---•--"••-•'- - — • - - •

r

RTN temp. = n s e c

-4

V

1050°C

vJAiuo^o.y;

3.8

tox = 8nm 1

100

200 300 RTN time (s)

Fig. 1.90 ' (Left) High-frequency C-V curves of MIS capacitors with oxides nitrided by RTN at IISO'^C for several nitridation times. (After [254] slightly modified). Fig. 1.91 - (Right) Dielectric constant Ejsfo versus nitridation time for several nitridation temperatures. (After [245] slightly modified).

7.7.2. Dielectric constant The Cacc value (dynamic capacitance in the accumulation mode) of RTNO capacitors is found to increase with RTN time and temperature. Increases as large as 20% have been observed (as shown in Fig. 1.90 for a 10-nm-thick RTNO film). Sputter Auger profiles show that the thickness of the nitrided oxide does not change. Consequently, the observed increase in Cacc is only due to an increase in dielectric constant.

Silica, Silicon Nitride and Oxynitride Thin Films

107

Figure 1.91 illustrates that £NO increases monotonously with nitridation time and temperature. Compared with the original oxide, nitridation for 5 to 300 s results in increases of 8NO of about 12 and 20 percent respectively. These increases are found to follow increases in [N] at the interface. For similar conditions, £NO increase faster if the oxide film is thinner. 7.7.3. Fixed charge and interface states In thin nitrided oxides, interface traps and fixed charges are found to vary strongly with RTN time and temperature. Variations of Nf and Dit, calculated by combining high-frequency and quasi-static C-V measurements, are plotted versus nitridation time in Fig. 1.92. Two temperature ranges must be distinguished: below and above 950°C.

L

E o ^' 5

Nitridation temp. = 950X

p Cv-•»•"•

7

900'C

T-

^ ^ '**

1050'C ^--t.

1150X A

•A

-1 L

L.

100 (a)

J.J 200 300 Nitridation time (s) i

Nitridation temp. = 950X

0 •

^

•'• 9 ^ ^

5

^ ^

-

-

-

-

-

^

^-^

^'^

^^-*A.

t,'V-^

'

-

(a) Variation in the fixed oxide charge density with RT-nitridation time for several nitridation temperatures. (b) Variation in the midgap density of interface states with RTnitridation time for several nitridation temperatures. (After [249] slightly modified).

1050*C

•"•--—-.-

»^a-^

nl

-

900'C

f 7 X X^^si^;: W

(b)

.

Fig. 1.92 - Illustration of how the electrical properties of the Si02-Si interface are modified by Rapid Thermal Nitridation. (The oxide film is 8-nm-thick).

115o»c

1

1

100

200 Nitridation time

LJ

300 (s)

• Below 950°C, Nf and Dit increase regularly during the early stages and then tend to saturate for longer nitridation times.

108

B, Balland and A, Glachant

• Above 950°C, both Nf and Dit first increase sharply at a rate which depends on the RTN temperature, reach a maximum, and then decrease monotonically at a rate which again depends on RTN temperature [249, 255]. For long nitridation times, Nf and Dit reach values comparable to those of FG oxides. The similarity in the behavior of Nf and Djt suggests that the physical and chemical mechanisms underlying these changes are the same in both cases. Models explaining the role of RTN, on ANf and ADit, based on mechanisms involving nitrogen, hydrogen, and Si-0 bonds, have been proposed by Hori et al [255]. In a first step, defects form due to the incorporation of nitrogen while in a second step these defects are reduced through a process similar to high-temporature annuealing [255]. This reduction could also be due to the fact that at higher temperatures, surface nitridation is enhanced and blocks the subsequent in-diffusion of N-rich species. This blocking action slows down further interfacial nitridation. An alternative explanation is to consider the thermal and chemical changes taking place at the interface and their influence on the partial charge transfer in interface bonds [256]. It is well known that a thermally-grown silica film on silicon is under compressive stress above the Si02-Si interface (due to a mismatch of the two lattices) while a nitride film on Si is under (macroscopic) tensile stress (see Sect. 2). Nitrogen-related defects are formed under the influence of interfacial stress. A sufficiently large incorporation of nitrogen relaxes the initial stress and leads to the healing out of the existing defects and thus to a decrease in Nf and D^. Once interfacial nitridation has reached a certain level, the interface stress disappears and the strain energy is reduced because the Si lattice and the SiOxNy lattices more or less match. Above this level, the further incorporation of nitrogen is hampered by the generation of a counter stress. Whatever the mechanism may be, Nf is shown to increase with increasing [N] and then to decrease, as illustrated in Fig. 1.93. Nitridation temp. T 9 0 0 ' C

6

..;;;;p;;. .•i3:L^^§jij:..

a pso'C Ol050°C

I

e

4 1 , %

o

A.

Fig. 1.93 - Variation in fixed oxide charge density with nitrogen concentration at the interface. (After [242] slightly modified).

•,•• J6

•I:'"^'

>^^.

2 ,••-••,•

n

••• • •

•«,••,••.

1

1

1

LIIILA

8 12 16 [N] at interface (at %)

1

Silica, Silicon Nitride and Oxynitride Thin Films

109

7.7.4. Behavior of RTNO films under electric stress In a study reported in [242], very thin (< 5 nm) RTNO MIS structures have been submitted to electron injection (electrons being injected from the gate electrode into the RTNO film by FN tunneling). The injected current was kept constant (= 10 mA/cm^). The effects of this stress on the leakage current and on Time-Dependant Dielectric Breakdown (TDDB) is reported below. i) Effect on oxide leakage current For all samples, the I-V curves measured before stress are nearly identical as visible in Fig. 1.94 a. After an injection stress (Qinj = 0.1 C/cm^), a sizeable leakage current appears for all samples, below 8 MV/cm, as seen in Fig. 1.94 b. It is observed that the current passing through the oxide increases for electric fields in the 6-8 MV/cm range, with the current increase becoming larger in samples nitrided at higher temperatures. At fields larger than 8 MV/cm, the current through the oxide decreases. This behavior is attributed to the role of nitrogen affecting the tunneling barrier for electrons and holes, the changing interfacial fixed charge density, and the lower conductivity of RTN oxides and their weaker field dependence. This leakage current increases with nitridation time. Although this leakage current is also encountered in thicker (> 10 nm) oxide samples, it plays a more important role when oxide are thinner. The mechanism of this low-field conduction is not fully known yet but it seems to fit an FN type of conduction with a reduced barrier height.

6 (a)

8 10 E (MV/cm)

6 (b)

8 10 E (MV/cm)

Fig. 1,94 ' Leakage current-versus electric field curves measured on MIS samples before (a) and after (b) FN injection. The oxide samples are S-nm-thick and have been nitrided for various lengths of time in NH^ via an RTF process: (a) I-E curves before stress (Dpure Si02, ©after 10 s of nitridation, ® after 20 s of nitridation, ® after 30 s of nitridation, (b) I-E curves obtained after injecting Qinj = 0.1 C/crr?. (After [242] slightly modified).

It is believed that FN electron injection increases the number of electron traps and that this creation is made easier as nitridation time is increased. The leakage current, which results from an increase in the number of electron traps, acts as a trigger for oxide breakdown.

B. Balland and A, Glachant

no

ii) Effect on dielectric strength Figure 1.95 shows the increase in gate voltage (AVQ) necessary to maintain a constant injection of 10 mA/cm^ in the oxide samples. • For pure Si02 film (case ©) AVQ is positive which means that hole generation and trapping dominate during the early stages of injection. • For RTNO films, AVG is negative which means that electron trapping dominates during injection. AVG is found to increase with nitridation time. The ratio AVc/AQinj (i.e. the slope of the AVc-Qinj curve) is proportional to the product of the capture cross-section of the traps and of the trap density (see Chap. 10 of Vol. 2 ) . Figure 1.95 shows that this ratio increases with nitridation time. Figure 1.95 also shows that the charge-to-breakdown value (QBD) decreases with increasing nitridation time. We can thus conclude that in RTNO sample nitrided in NH3, the electron trapping process dominates and that the amount of created electron traps increases with nitridation time. -0.5

0.6 Q

0.8 1.0 • (C cm"2)

Fig. 1.95 - The increase in gate voltage necessary to maintain a constant injection current is plotted versus the injected charge for various silica samples nitrided via an RTN process: (Dpure silica film, ® nitridation for 10 s, (3> nitridation for 20 s, ® nitridation for 30 s, ® nitridation for 60 s. Arrows indicate that the film was destroyed by dielectric breakdown. (After [242] slightly modified).

Dielectric breakdown in very thin Si02 could result from an increase in low-field leakage due to the enlargement of defect-related "weak spots". Another possibility is that tunneling occurs in the regions where conduction relies on the field-assisted hopping of electrons from one trap to another i.e. where Poole-Frenkel conduction dominates. In RTNO samples, a strong correlation is found between QBD» the ratio AVc/AQinj and the nitridation time. Charge QBD is proportional to (AVc/AQinj)"^ with k = 0.56, [242-243]. The charge trapping characteristics of silica film have been explained by means of the broken bond model (see Chap. 2 of Vol. 1) and by the role hydrogen-containing species, such as -H and -OH or -NH bonds play in electron trapping. -H and -OH bonds are created during RTN as a result of the dissociation of NH3 and are responsible for the large number of electron traps in nitrided oxides. Electron trapping in high-field stress is associated with chemical reactions such as: 03=Si'H +e-—> 03=S> -vRo (1.21) or 03=Si^NH + ^ - —> 03=Si- +NHO (1.22)

Silica, Silicon Nitride and Oxynitride Thin Films

111

Fourier Transform InfraRed measurements show that during RT nitridation in NH3 a large number of N-H bonds (« 2.9 10^1 at/cm^) and Si-H bonds (« 3.3 10^0 at/cm^) form in the film. These sites act as electron traps. Thus if the weak s Si-H, = Si-NH and /or = Si-O-Si = bonds encountered in pure silica, are minimized by the formation of more stable bonds, such as SiN bonds (4.6 eV), the electron trapping density can be reduced. This can lead to a larger QBD value. Thus, in ultra thin RTNO films, the density of electron traps must be minimized to reduce the leakage current and increase QBD- The rapid thermal reoxidation of nitrided oxides eliminates these hydrogen-containing species via the reactions: 2 (=Si ^H) + 0 ^ = Si-0-Si

= + H2

(1.23)

and = Si- H +=Si -OH +0-> = Si-0-Si=

+H2O

(1.24)

which results in the reduction of electron traps in nitrided oxides while niaintaining all other advantages of RTN [259 - 261]. 7.8. CONCLUSION

Thermal nitridation was formerly considered as a step difficult to apply to a ULSI process. This difficulty stemmed from the high temperatures and long durations attached to the fumace process. Rapid Thermal Processes (RTO and RTN), using a lamp-heated apparatus have made it possible to minimize the duration of the oxidation and nitridation steps and thus have allowed a reduction of impurity redistribution and stress at the interface. Thin oxides grown at 1150°C show superior electrical characteristics (breakdown fields of 15 MV/cm and interface state densities below 10^^ eV'l cm-^) compared to oxides grown in diffusion furnaces at low temperatures. When an additional RTN step is added, oxides display characteristics similar to those of annealed oxides, while gaining both a superficial nitride layer and a nitrogen-rich interfacial layer. Rapid Thermal Processing is mostly exploratory and developmental in nature but it is slowly being introduced as a manufacturing technique of Si devices. It is an important new direction. The greater use of RTP in routine production will depend on either demonstrated productivity/cost advantages or on some intrinsic advantage of RTP (single wafer processing, possibility of selectively enhancing a desired process over another undesired reaction, etc.). Temperature uniformity and repeatability will also need to be better garanteed. 8. THIN OXYNITRIDE FILMS GROWN IN N2O AND NO AMBIENTS The nitridation of silica in gaseous ammonia introduces a substantial amount of hydrogen in the film which in tum enhances the density of electron traps, results in a fixed-charge buildup, and causes the leakage current to increase. However, the primary purpose of nitridation is usually to introduce a small concentration of nitrogen at the Si02-Si interface to improve the interfacial quality and the charge-to-breakdown.

112

B, Balland and A. Glachant

Nitridations conducted in oxidizing ambients have been found to suppress or reduce some of the disadvantages of nitridation while preserving its advantages. 8.1. THE MAJOR PROCESSES

Alternative nitridation processes, using gaseous nitrous oxide (N2O) or nitric oxide (NO), have been developed [237, 262-294]. The successful oxynitridation of silicon in N2O has been demonstrated by using both Rapid Thermal OxyNitridation (abbr. RTON) and conventional Furnace OxyNitridation (abbr. FON). Several processes have been tested to get the best electrical characteristics for a given application. The four major processes which use N2O are given in Table 1.07. • Process 1

a) Conventionalfiamaceoxynitridation of silicon using [237-280] a pure N2O ambient (typ. T = 900°C, t = 60 min) b) Rapid thermal oxynitridation of silicon using a pure [237, 262-279] N2O ambient (typ. T = 1050°C, t = 100 s)

• Process 2

Rapid sequential thermal processing of silicon at various ambients: N2O followed by O2 and then N2O (typ. T = 1050°C)

• Process 3 (RTON)

Two-step process: (1) treatment in O2 (typ. for FON, T = 900°C, t = 60 [237, 280] min and for RTON, T = 1100°C, t = 20 s), followed by (2) treatment inN20 (typ. for FON, T = 900°C, [263, 271-275] t = 60 min and for RTON, T = 1100°C, t = 30 s)

\» Process 4 • Process 4 a • Process 4 b (RTONO)

[263, 271-275]

In-situ RT-oxidation followed by RT-nitridation: (1) ^ O2 (T = 1100°C, t = 60 s) ^ then (2) -^ NH3 (T = 900°C, t = 60 s) -^ then

a) [242, 253-261]

(a) -> dry O2 (T = 1000°C, t = 30 s)

b)[237, 277-279]

or (b) -» N2O (T = 1100°C, t = 30 s)

Table 1.07 - Characteristics of four oxynitridation processes using N2O.

Although nitridation in N2O can be performed directly on silicon (process 1), it usually follows an oxidation step, because the thickness of films grown directly in N2O can saturate at relatively low values. Two-step oxynitridation allows one to produce any desired thickness and yields superior electrical characteristics. The thin oxynitride films thus produced exhibit interesting electrical properties (QBD > 30 C/cm^ and a smaller change in Dit upon nitridation) which stem from the presence of nitrogen at the interface and from a low concentration of hydrogen-related species in the resulting film. The first three processes are hydrogen-free. The fourth process has been proposed to grow thin films for flash EEPROMs (a most promising device for the next generation of non-volatile memories) [277-279].

1

Silicay Silicon Nitride and Oxynitride Thin Films

113

8.2. OXYNITRIDATION IN N2O 8.2.1. Growth kinetics The growth of an "oxynitride" film in N2O is slower than a regular oxidation in O2 and is easier to control. Growth may be self-limited as nitridation time increases, depending on the amount of incorporated nitrogen [237, 269-270]. The growth rate strongly depends on temperature (T ~ 1000-1200'^C), as illustrated in Fig. 1.96a, on pressure, and on the dimensions of the RTP reactor (which in turn determine the amount of nitriding species). Typical growth curves are shown in Figs. 1.96. As illustrated in Fig. 1.96b, growth in N2O is twice slower than growth in O2. Figure 1.100 c shows the influence of temperature and crystal orientation on the growth rate in N2O. These data show that tox increases as approximately (time)l/^. From the Deal & Grove model [10a], this time dependence implies that the oxidation rate is limited primarily by the diffusion of the oxidizing species through the oxide, rather than by the chemical reaction at the Si-Si02 interface (which would produce a linear time dependence). This conclusion is supported by the data of Fig. 1.96c which shows a relatively small orientation dependance, especially at 1000°C, (on the contrary, reaction rates depend relatively strongly on crystal orientation). Soleimani et al. have reported a linear time-dependent oxidation rate [281]. Others [282285] have reported self-limited growth in N2O [274]. Low N2O flow rates produce a lower nitrogen concentration at the interface, which is a less effective diffusion barrier [285]. Ting [266] and Soleimani [281] have presented a model for growth kinetics of oxynitrides on Si in N2O using a FON process or a RTON process. 8.2.2. Growth mechanisms Studies on the (gas phase) dissociation of N2O near the Si wafer temperature, the dissociation products are NO (gas), O2 and O:

show that at high

• the primary decomposition is: N2O <=> N2+ O

(1.25)

• but the following reactions are expected to take place: N20 + 0<^ N2+O2

(1.26)

N20 + 0^2NO

(1.27)

The incorporation of nitrogen in the film is due to the diffusion of NO [274]. The NO radicals diffuse through the growing film via an interstitial mechanism (as explained in Chap. 7 of this volume). They have a weak probability of reacting with the network atoms but dissociate at the Si02/Si interface to form SiO^Ny. This explains why nitrogen is only encountered at the Si02-Si interface in N20-grown films.

114

B. Balland and A. Glachant

1"

a 900^C

c 30.0 ^-'

o 950^C

o

•g 20.0

.^-''' ..•''"' ,^'-'"' ^«»" ^*"

.^'•'" V - - " • '

o

--:1c-.---?--

2 10.0

o

^-t'" 1

• lOOO^C • 1050^0

W—A

I . I

A

1

1.

1

30

1

'••"' 1

1—1

60

E c m

I.

1

1

I

120

F

^ 02

L

°

[

T-

•-^ f

•

r

t

/

/ ^

y . -a

1

(min)

.4-^ '

^'

1

Oxidation time

/ 1

900*»C

1

I

180

N2O

1 0 h1

I

150

L^

in

c o

1

90

(a) 100

,---'^"

/ X

.'0

b Y

L

T A <111>

" ^ <100>

1

'''°' ^

10"

Oxidation time

1 1 1 1 m 1

L

t

10^ 1 (min)

(c)

X

''

_^

-'

-' A'-'

>i . * . ' 'f '^' ' ^ ' . ' A . r 'f^

.''-•'' .^d \

^ ^ 1

.'

•

X

-y^A

\ ^ •

P

>'6

/

1000»C

r

^

A 1 rf n i i 1

10^ (b)

X

•

''

^

•

'JLX

^'

¥ ' ' .'".^'a' 3 ^ .'^^'

900*'C

-p- a '-^

'V'/d'

L

1

iV

^ ^

1 ^1,1.1

\ 111 i

10

1

1 1 « 1 1k A j j

10^

Oxidation time

10 (min)

Fig. 1.96 - Typical growth data for the furnace oxynitridation of Si: (a) Growth kinetics in N2O at various temperatures, (b) Growth kinetics in O2 and N2O at 900°C; (c) Growth kinetics in N2O for two wafer orientations at 900''C and lOOO^'C (After [280] and [283] modified).

Both molecular and atomic oxygen contribute to the growth of the Si02 film. Molecular oxygen diffuses through the growing film to react with Si at the Si02-Si interface. Atomic oxygen reacts at the surface of the film and/or gets into an exchange mechanism with O atoms of the film. 8.2.3. Film composition The composition of oxynitride films grown in N2O differs slightly depending on whether the film is grown in a furnace or in an RTP apparatus. Extensive chemical analysis data of films grown in N2O have been obtained by AES, XPS and SIMS analysis [262-266]. The maximum [N] concentrations found vary between 1% and 6% as sunmiarized in Fig. 1.97. • Furnace-grown films The distribution of nitrogen in an FON film differs from that of an RTON film. More N is found in the bulk of FG films. SIMS results for O2/N2O processes are shown in Fig. 1.98 a. For the two-step O2/N2O sample, the N profile peaks at the Si-Si02 interface at a concentration of « 0.55 at.%, with a width of «(5 ± 1) nm a t « 0.3 at.%. [N] near the top of the oxide, far from the Si-Si02 interface, is only « 0.03 at.%.

Silica, Silicon Nitride and Oxynitride Thin Films

115

The reoxidation of an O2/N2O oxynitride in O2 causes an unusual behavior. A new Si02 layer grows at the Si02-Si interface under the nitrogen peak, and the existing N-rich layer remains essentially intact (Fig. 1.98 b). This behavior suggests that nitrogen atoms are chemically bonded in the oxide near the interface, rather than bonded exclusively, at the interface, with silicon atoms. 6 ^

f

5

1 1 1 1 1

1

'

'

'

1 ~ ""

• « •

1 1 1

=

1 1 1

"~ 3 IT ~

c a> o c o O

I } \ y-r 1 ( 1 1 j T t 1 1 ,

•i® '

^@ i

~

r

f 1 n

'

r

"-' 4 h c o

1 1 1 1 ^ 1 1 1 1

1 1 1

: ®^i

! ®

2 h

1 I I __!_ I 1 1 I

~

<

1 h

j

1 1

, , , _4 , , ,

J J J J "n J J

I

1

__ '

j

i

•_ 1 1

,

n

4 -

-J I

- J

,

J

^® i

1

Fig. 1.97 -Maximum [N] values found in ETON films (oxynitrides grown in N2O): (D - N2O furnace oxynitridation ® - N2O furnace oxynitridation (D - N2O furnace oxynitridation ® ' N2O furnace oxynitridation ® - N2O furnace oxynitridation ® - N2O furnace oxynitridation ® - N2O RTF oxynitridation ® - N2O RTF oxynitridation ® - N2O RTF oxynitridation © - N2O RTF oxynitridation (li)-N20 RTF oxynitridation Q-N2O RTF oxynitridation (After [292] modified)

T-T-I

i

I I

1 !

id

b j - i ~ i . .4 1 1 1 . 1.-L-1 1 -1—LJ-I-X..I I 1 1 \ 1 1 1 1 1 1 i-,.i 1 t..i... 1J

900°C

lOOO^C

1100°C

1200X

Temperature

(^ C) 1.00

1.00

i

•]

0.75

T 0.75

0—^i^x1

-ll

«

/ -j

0.50 Sl_

r y^M*^

M

0,25

[-1 0.00

1

0 (a)

5

10

15

Depth (nm)

20

1

0 (b)

I

5

I

1

10

1

1

15

1

S

0.25

g

\v 1

..v^V. 1

0.50

iL

1

\

A

0.00 1

20

1

25

Depth (nm)

Fig. 1.98 - SIMS profiles of N, O, and Si (a) for a two-step O2/N2O oxide and (b) for a reoxidized O2/N2O oxide [281].

• RTP'grown films To highlight the difference in the amount of N and H introduced by the various RTON processes, oxide films nitrided in NH3 and N2O have been compared [275]. Figure 1.99 shows the N and H in-depth concentration profiles: of a control oxide obtained by RT oxidation (a), of the same oxide nitrided in NH3 (RTN) (b) and of an RT-oxide treated in N2O (c). The film thickness has been estimated at 5 nm using ellipsometry [275].

116

J5. Balland and A, Glachant

• A^ in-depth concentration We note the presence of nitrogen in the RTO film. This nitrogen comes from the gas ambient which was only 99.9% pure. We note also that, compared with nitridation in N2O, more nitrogen is found in the bulk of the RTN sample and that [N] at the Si02-Si interface is also larger. It is clear from these results that, in both cases, during the nitridation of Si02, the nitriding species diffuses and N piles up at the Si02-Si interface. • H in-depth concentration Identical [H] values are found in the RTO and RTON samples. This has been attributed to the fact that the water concentration [H2O] was about the same in the O2 and N2O gases used [275]. In contrast, [H] is much larger in the RTN film, as expected. InfraRed analyses show the existence of N-H and Si-H bonds with concentrations above 10^^ at/cm^ in the RTN-film, while these concentrations remain below detection limits for the RTON samples [275]. Complementary XPS experiments (as shown in Fig. 1.100) confirm that the only nitride species formed in the RTON films are Si-N species, whereas N-H, Si-H and Si-N species are found in the RTN sample [275]. Typical 0(ls) and N(ls) core level lines recorded at the interface reveal the presence of an N-Si bond peak at 397.8 eV. No peaks originating from N-H bonds and N-O bonds, which are expected to appear in the range of 398.5-400 eV and 400-404 eV, respectively, have been seen in the XPS spectrum [281]. The 0(ls) spectrum, whose main component appears at 532.2 eV, indicates that the SiOxNy structure is essentially the same as that of the tetrahedral Si04 network itself. 1 ^sro2 : Si

^

N\

. H

RTN . . . . 1 5 10

1 * * * ' *J

0 (a)

5 Depth

10 (nm)

0 (b)

Depth

(nm)

0 (c)

5 Depth

1 0 (nm)

Fig. 1,99 - Nitrogen and hydrogen in-depth profiles measured by SIMS in three different 5-nm-thick samples : a) Control oxide grown by RT oxidation (RTO), b) Oxide nitrided in NHj by RT nitridation (RTN), c) Oxynitride first grown in O2 at lOSO^'Cfor 5 s and then in N2O at llOO'^Cfor 30 s (RTON). (After [273, 275] modified).

Silica, Silicon Nitride and Oxynitride Thin Films

536

534

532

530

402 400

117

398 396 394

Binding energy (eV) Fig. 1. 100 - 0(1 s) and N(ls) core level XPS spectra measured at the interface for ETON [250]),

samples. (After

Any reduction in the concentration of hydrogenated species (-H and -OH, Si-H, Si-NH, Si-OH, etc.) in the oxynitride film should minimize the number of electron traps [273, 275] as well as the density of neutral defects by the formation of strong Si-N bonds (see § 4.7). RTON films are thus expected to show lower electron trap density, as confirmed below by electrical measurements. High Resolution Transmission Electron Microscopy has revealed [263, 273] the structure of the Si02-Si interface of RTON samples. Cross-sectional HRTEM images of RTON films, produced using the hydrogen free processes described above, show that process 3 of Table 1.07 gives the best results. In this case, the interface structure seems to be quite uniform, at least ordered within one or two atomic layers. Moreover, no anomalous oxidation behavior, like Si clusters or Si02 epitaxial layers, have been observed [273]. However, a transition layer, one or two atoms thick, has been found between the Si crystal and the amorphous oxide layer. This last result has been confirmed by means of a Transmission Electron Diffraction analysis performed at points A, B, C and D (Fig. 1.101).

Fig. 1.101 - Cross-sectional HRTEM image of the insulator/silicon interface of an RTON film formed (process 3) in O2 (1050°Q 5 s) and then in N2O (llOO^'Q 30 s). (After [273] modified).

• • • . f • • • • » • »j

wnnwiMmwww

mm

118

5. Balland and A, Glachant 8.2.4. Trapping properties

The trapping properties of MOS samples using either an oxide or an oxynitride film have been studied by submitting these samples to an electron FN injection from the gate electrode (at a constant current of: 10 mA/cm^) [275]. • Flat band voltage shift The variations in AVpB as a function of injected charge (Qinj) are represented in Fig. 1.102. Obviously, the oxynitride samples grown in N2O display a smaller AVpB than either the pure oxide film or the reoxidized RTN film. This means that (after pair production) hole trapping is smaller for N2O samples. The tendency of AVpB to saturate in the region of higher injected charge indicates a hole trap filling process and the saturation value is proportional to the trap density. During injection experiments, the gate voltage (VQ) must be readjusted to maintain the injected current constant. This shift in gate voltage has been plotted versus stress time for the above three samples, in Fig. 1.103. We note that AVQIS positive for the oxide samples, while it is negative for the reoxydized RTN oxide and nearly neutral for the oxide nitrided in N2O. The positive V^ shift is attributed to hole generation and trapping (confirmed by theVpB shift). On the contrary, negative VG shifts are attributed to the creation and the filling of new electron traps during the high-field stressing. We note that the creation of new traps occurs mostly in the samples nitrided in NH3. The differences observed between the three kinds of oxide films can be explained in terms of the broken bond model [10b]. 1.5

m 11.

1.0 U A

Fig. 1.102 - The AVfB observed after injection is plotted as a function of Qinj for: pure Si02(A), reoxidized NHs-nitrided Si02 (0) and N2Onitrided Si02 (m) (After [275] modified).

A' /

•0.5 r

:iS

RTO RTO/RTN/RTO RTO/RTON

I

0.0

u

-1

l_l

0.5

U

1

1.0

1

1

1

1

1

1.5

2.0

Injected charge (Ccrrr^)

• Interface trap density The change in interface trap density Dit after an FN injection of ±0.01 C.cm-2 is shown in Fig. 1.105 (right). First, all oxides last exposed to N2O during growth show a smaller D^ increase for positive gate bias during e-injection than those submitted to negative bias, whereas samples last exposed to O2 show the opposite behavior. Second, oxides grown in O2/N2O and (especially) in N2O show less Dit generation than the control oxide. Similar trends are found after irradiation experiments.

Silica, Silicon Nitride and Oxynitride Thin Films

Fig. 1.103 ' The gate voltage adjustment AVQ^ necessary to maintain a constant injection current (linj =0.1 A/cm^) is plotted versus stress time for the same samples as those of Fig. 1.102. (After [275] modified).

0

RTO/RTN/RTO

t'

119

RTO/RTON

RTO

+0.4 h I

10

I

I

20

I

30

-L 40

50

Stress time (s)

8,2.5. Dielectric brealidown • LoW'field leakage Breakdown in ultra thin silica films results from an increasing low-field leakage due to the enlargement of defect-related weak spots. As visible in Fig. 1.104, after stress, this anomalous leakage current is visible at low-field (< 10 MV/cm), whether the structure has been positively or negatively biased. Low-field leakage is thought to be due to the generation of defects or weak spots, located on positive charges and/or trap sites, near the injecting interface. All currents measured after a high-field stress seem to be the sum of two components: a leakage current Idef flowing through the defective area and If, a current flowing through the remaining area [275]. 1 0"

c ^ 10

10

-11

1 0

12

6 8 10 Field (MV.cm^)

6

8

10

Field (MV.cm^)

Fig. 1.104 - Leakage currents measured on the same samples as those of Fig. 1.103 after a negative bias (left) and a positive bias (right). The insulator thickness is 6 nm. (After [275] modified).

120

B, Balland and A. Glachant

• Charge-tO'breakdown In Fig. 1.105, average QBD values obtained for a small constant injection current (Jjnj = ±4.10"^ A.cm-^) are given. First, QBD is higher in the O2/N2O and O2/N2O/O2 samples than in the control oxide. Second, QBD for the N2O oxide is smaller than for the other samples, especially for V Q > 0. Such an asynmietric behavior with bias suggests that the Si02-Si interface (injecting for V Q > 0), is much rougher than the Si02-gate interface. Joshi [290] proposed that the lower QBD values observed for N2O oxides is caused by an increase in roughness at the Si02-Si interface, especially for oxidation temperatures of 1000°C or above. This roughness is thought to enhance locally electron injection, leading locally to higher current density and lower QBD- This hypothesis has been validated by taking TEM pictures of the Si02-Si interface to evaluate the roughness. The interface appears reasonably abrupt, with a roughness of « ± 2 monolayers (± 0.27 nm) encountered over a lateral distance of « 0.1 |im. About the same roughness is obtained for a 10-nm control oxide grown in O2 at 900°C. As illustrated in Fig. 1.105, these data suggest that the two-step O2/N2O oxide is preferable (process c) to oxidation in N2O alone (processes a or b). The corresponding leakage current is smaller, which will result in a better resistance to dielectric wear-out. 100 i

E

o O

10 1

O

0.1

0.01

10 ^H

i

1 • !1 • ' H1 I II I -

J 1ll

+ 0.01 C. cm^ -0.01 C. cm^

J

J 1 1 L

LIJlII • \ a)

b) c) d) Process

a)

b)

c)

I d)

Process

Fig, 1.105 - (Left) Charge-to breakdown (QBD) ^^d (right) change in interface trap density (Dif) measured after FN injection, for gate insulators grown in various conditions: (a) furnace oxidation in O2 at 900°C, (b) two-step oxidation first in O2 and then in N2O (90 0°C, 60 min), (c) like (b) and then reoxidation in O2 (900°C, 60 min), (d) furnace oxidation in N2 O at 1000°C (60 min). For FN injection + (resp -) indicates that a positive (resp. negative) charge ofO.OlC.cm^ has been injected (After [280] modified).

8.2.6. Reliability MOSFETs using RTON films as a gate dielectric display excellent performance and good inraiunity to hot-carriers [282]. Figure 1.106 shows that the degradation in threshold voltage, due to channel hot carrier effects, is indeed less when N20-grown gate dielectrics are used [283]. Moreover, the effective carrier mobility, both in n-MOSFETs and p-MOSFETs is virtually unchanged after hot carrier injection when N2O gate dielectrics are used.

Silica, Silicon Nitride and Oxynitride Thin Films

121

Fig. 1.106 -The degradation in threshold voltage due to channel hot carrier injection is plotted versus gate voltage for p-MOSFETs possessing either an oxide or an N20-grown oxynitride as gate dielectric. (After [292] modified).

- 4

- 6

Gate voltage (V) Oxynitride films grown in N2O display a better resistance to process-induced damage (such as that caused by plasma during the polysilicon etch and resist etch steps) and to dielectric wear-out. They, moreover, display a better immunity to radiation (suppression of both radiation-induced neutral traps and positive charge build-up) [292, 293], It has also been shown that N20-oxides grown on RIE-treated surfaces show higher breakdown fields, lower leakage currents and significantly improved TDDB characteristics. They thus have been used as tunnel dielectrics to manufacture reliable EEPROM devices with slow "window closing" and high endurance. The leakage current induced in oxynitride films by such stresses as: successive voltage ramp stress, constant voltage stress, alternative stresses (unipolar or bipolar) is suppressed when the films are grown in N2O. 8.3, THIN OXYNITRIDE FILMS GROWN IN NO

Unlike growth in N2O, only limited data on growth in NO is available. 8.3.I. Principle and growth kinetics Preliminary results indicate that growth is more "self-limited" in gaseous NO than in N2O. For example, while the exposure of bare silicon to N2O ambient at 1050°C for 100 seconds produces a 5.2-nm-thick layer, exposure to NO, under the same conditions, produces only a 2.5-nm-thick layer [292]. This is probably due to the larger amount of N incorporated in the latter case, the N-rich silicon layer acts then as a barrier blocking the diffusion of the oxidizing species towards the interface. Growth kinetics in NO when the starting materials is Si02 is illustrated in Fig. 1.107. We note that growth is extremely slow. The increase in [N] is probably due to the complete dissociation of the NO molecules and to the subsequent direct reaction of N and O atoms with silicon, whereas in the case of growth in N2O, this direct reaction is less probable [292].

122

B. Balland and A. Glachant

10.0

Fig. 1.107 - Growth curves ofoxynitride films obtained by nitriding Si02 films of various thicknesses in NO at 1000°C. (After [252] modified).

40

60 NO anneal time

80 (s)

8.3.2, X-ray assisted growth at room temperature The formation of an oxynitride film on silicon in NO is possible at room temperature when one operates in Ultra High Vacuum under soft X-ray irradiation. For example, a (111)oriented single Si crystal can be cleaved in an UHV chamber (residual pressure < 5 10" 11 mbar) [301-303]. After exposure to 10"^ mbar of pure NO gas, the NO-covered surface is irradiated at grazing incidence. This leads to the formation of Si-N and Si-O bonds due to the dissociation of NO-molecules by the Si dangling bonds from the Si(lll)-2 x 1 reconstructed surface (an ultrathin, passivating, oxynitride layer forms). The remaining NO molecules, adsorbed at the surface, give rise to further oxynitride growth upon irradiation under X-rays. Thin oxynitride films (0.6 -1.0 nm) can thus be formed. 8.3.3. Electron beam-assisted growth at moderate temperature The exposure of a Si(100)-2xl surface to a low pressure NO gas (< 10-5 mbar) at moderate temperature (from room temperature up to 600°C) leads to the formation of a «0.5- nm-thick amorphous passivating oxynitride layer [294]. The irradiation of the surface with a low energy (100 eV) electron beam (maximum fluence= 1.6 lO^^/cm^), during exposure to the NO gas, induces the growth of an amorphous, thin (> 3 nm), oxynitride film whose composition depends on temperature. At room temperature, oxygen-rich films are formed, whereas at 600°C, nitrogen-rich layer are formed. It has been suggested [294] that the observed electron beam-induced growth at room temperature is the result of both: • the reaction of activated N and O species, produced by the dissociation of NO molecules, with free Si atoms from the substrate, • the electromigration of NO", O^" and/or O" ions through the oxyde layer formed, up to the interface, where they react with the Si atoms of the substrate. An increase in temperature, from room temperature to 600''C, leads to an enhancement of the thermal diffusion, through the oxide film, of the NO species adsorbed on the surface. These diffuse to the insulator-silicon interface, where they react.

Silica, Silicon Nitride and Oxynitride Thin Films

123

8.3.4. Film composition Comparing the N(ls) XPS spectra of oxynitride films grown by annealing silica samples in N2O and NO for identical conditions, shows that the N(ls) signal is much larger for samples grown in NO, thereby indicating a higher [N] concentration. The [N] profiles obtained by SIMS for both types of oxynitride show that N mostly piles up near the Si02-Si interface. The required thermal budget is found to be much lower for the NO-process than for the N20-process. The Composition Parameter (CP), i.e. ratio [0]/([0] + [N]), and the thickness of the obtained oxynitride film, measured by AES can vary between 0.50 (0.5 nm) and 0.83 (3.0 nm) [294]. Moreover, the energy gap, determined using REELS is found to vary between 6.0 eV (CP = 0.59) and 7.7 eV (CP = 0.83). These values are in good agreement with the values expected for such compositions using optical absorption [295]. 8.3.5. Electrical properties Basically, the oxynitride films grown in NO display excellent electrical and reliability properties, even better than those of films grown in N2O. Both n- and p-MOSFETs using NOgrown oxynitrides exhibit excellent performance and a good resistance to hot-carrier effects [286-287]. Less interface states are generated during an electrical stress when an NO oxynitride is used. This improvement is due to the presence of N atoms at the Si02/Si interface which reduce the interfacial strain through the replacement of strained Si-O bonds by Si-N bonds. It is also due to the replacement of weak Si-H bonds by strong Si-N bonds, which renders the generation of interface states by bond breaking under electrical stress less likely.

40 - a Ofe 20 : 0 • •

>

^ 1

NO N20

0 -20 1 •40 1 1 ...

1 1

20

_i

1

1

1—1—1—1—1—1—1—1—1—1—1—1—I

40

60 80 100 Stress time (s)

Fig, 1.108 - Charge trapping characteristics for various MIS insulators. The shift in gate voltage necessary to maintain a constant injection current (Iinj = 200 mA/cm^) has been plotted versus stress (injection) time for a S.l-nm-thick untreated oxide and for a similar film nitrided in N2O and NO. (After [290] modified).

124

B, Balland and A, Glachant

Likewise, due to the absence of hydrogen in the processing ambient, NO-based oxynitrides display negligible charge trapping, as illustrated in Fig. 1.108. A significant improvement in TDDB characteristics is thus obtained in such films. The excellent breakdown properties of NO-based oxynitrides are due to the much reduced charge trapping and to the electrical stability of the Si/oxynitride interface. NO-based oxynitrides can be used as tunnel dielectrics in EEPROM. Figure 1.109 shows that over a wide range of oxide thicknesses, the Stress Induced Leakage Current (SILC) in NO-processed films is always lower than in thermal Si02 films [290]. 8.4. CONCLUSION

The use of oxynitride films grown in N2O and in NO is extremely promising due to the simplicity of their fabrication process, to a good control of their thickness and to the excellent electrical characteristics obtained. Since the thermal budget required to incorporate the same amount of nitrogen in Si02 is much lower for the NO process than for the N2O process, the NO process could become a process of choice. This technology is key to manufacture submicrometer flash-EEPROMs. 10

-5

F L r

E o <

r

^-''' < ' . -

-O"--

^ ^ x

\

10

6

h-

t

H

V

• -

\ 0 SD2 • N O Annealed SiOz

o

o

\N

N

\

\ \ \

\ \

\N \

tr

\

\

\

b

N

Fig. 1.109 - The Stress Induced Leakage Current (SILC) measured for an applied field of 6.2 MV/cm is plotted as a function of oxide thickness. The SILC has been measured both for a regular thermal oxide film and for oxide an film nitrided in NO. An injection stress of 100 mA/crn^ has been applied for 10 seconds. (After [290]).

N

•

I

t_J- 1 11 1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

4.0

5.0

6.0

7.0

Oxide thickness (nm) 9. A BRIEF REVIEW OF LOW-TEMPERATURE ASSISTED PROCESSES Current high-temperature furnace processes, and even RT processes, induce such undesirable effects as the redistribution of doping atoms and the growth of stacking faults. Many attempts are thus under way to grow or deposit dielectric films at room temperature or close to, it through techniques requiring low thermal budgets. Several ways to enhance the reactivity of the active species have been tried. The enhancement techniques make use of photons, electrons, plasmas and reactive RF sputtering. We examine next these techniques as well as the properties of the films thus produced.

Silica, Silicon Nitride and Oxynitride Thin Films

125

9.1. PHOTON-ENHANCED PROCESSES

Both silicon nitride and silicon oxynitride can be obtained at low temperature using photon-enhanced processes. 9.1.1. Basic equipment Thin silicon nitride films may be obtained either through the direct reaction of an activated NHx (x < 3) species with the silicon substrate [296] or by deposition [86, 297-298]. In each case, the Si(lOO) wafer is introduced into a quartz reactor in front of an excitation source. This source may be an ex-situ UV-light source (e.g. a low-pressure mercury lamp with resonance lines at 184.9 and 253.7 nm) [297-298] or an ArF excimer laser [86]). This source may also be an in-situ UV-light source, the gases involved in the chemical reaction being then used as the gases of a pseudo-lamp operating in the normal glow discharge domain of a DC discharge. The wafer is heated from the rear by means of a halogen lamp. The wafer temperature reached varies between 100 and 800''C i.e. well below that of usual pyrolytic processes (for which T < 900°C). 9.1.2. Photon-enhanced nitride growth The reactive NHx species are produced after absorption of an ex-situ UV-light by the NH3 molecules [296]. NH3 is known to absorb wavelengths between 160 nm and 220 nm and to dissociate according to the following three equations: NH3 + /iv -^ NH2 + H

(1.28)

NH3 ^-hv-^NH + 2H

(1.29)

NH3 + hv "-> NH-\-H2

(1.30)

Energy considerations show that if X. < 213 nm, the NH2 radical is in an excited state. At "moderate" temperature (400°C < T < 800°C) a nitride film grows on silicon. Growth is quick during the initial stage but saturates with increasing time, just like in the case of HT thermal nitridation. Thicknesses of 2.7 nm (400°C, 1 h) and 6.2 nm (800°C, 1 h) have been obtained [86, 296], to be compared with 4.6 nm for the standard thermal process (llOO^C, 40 min). 9.1.3. Photon-enhanced nitride deposition Thin silicon nitride films can be deposited at low pressure (< 5 mbar) and low temperature (100-400°C) by the photon-enhanced decomposition of hydrazine (N2H4) and silane (Si H4) or ammonia and silane [297, 298], with Hg vapor being introduced in the reactor. An irradiation with a wavelength of A. = 253.7 nm produces, in the pseudo-lamp, an excitation of the Hg atoms to the 3?^ state. When colliding with silane or hydrazine molecules, the Hg atoms release the absorbed energy, and the silane or hydrazine molecules decompose.

126

B. Balland and A. Glachant

The decomposition products thus form a deposit on the substrate. Growth rates of up to 10 nm/min can be obtained at 200°C, depending on the total pressure and on the distance between the sample and the light source. 9.1.4. Composition and properties of LT- PE nitride films The Auger spectra of the LT-PEnitride films grown on silicon (direct reaction with Si) reveal a small carbon contamination at the nitride surface, and a decreasing oxygen contamination, when T increases from 400 to SOO^'C. Auger spectroscopy yields values of [N] of 50at.% Ih, Hg lamp) [296], of 48at.% (400°C, after 2000 pulses of 15nJ.cm-2, Arf excimer laser [86], and 69% (800°C, Ih, Hg lamp) [296]. Films grown at 400°C are thus nitrogen-rich oxynitride films rather than nitride films. However, the films grown at the highest temperature (T = 800°C) show a composition parameter which is very close to that of LPCVD nitrides. The IR absorption spectra of LT-PE deposited nitride films reveal the presence of Si-N or Si-H bonds [297]. Compared with films deposited using SiH4+NH3 at 900X, LT-deposited films display: a lower dielectric strength (10 MV/cm), a lower dielectric constant (5.5) and a higher etch rate in NH4F-HF (0.1 |im/mn). 9.1.5. Photon-enhanced oxynitridation processes Thin oxynitride films have been deposited [299] or grown [300-304] directly on silicon substrates at temperatures below 500°C, using the same apparatus as that described in § 9.1.1. and a gas mixture containing argon, SiH4 and NH3. Oxygen (O2) (from 0 to 2%) has also been added to the reaction gases. Activation was achieved by a DC electrical discharge in the pseudo-lamp. The deposition of oxynitride films can also be achieved using a pulsed ArF laser beam (K = 193 nm) and two different sets of precursor gases: SiH4 and SiC^2H2 combined with NH3 and N2O. The Si substrate is heated up to 500°C [299]. The residual pressure inside the preparation chamber, prior to processing, is kept below 10-^ mbar. The influence of various parameters such as: the laser pulse energy, the repetition rate, the volumetric ratio of reactive gas and the substrate temperature on the deposition rate, has been investigated [299]. The deposition rate (whose maximum value is « 0.17 nm/J.pulse) is found to increase with the average energy density, the repetition rate and temperature. The SiH4 process exhibits a stronger temperature dependence than that using SiC^2H2. The films deposited with SiH4 are of higher quality than with SiC^2H2. A maximum film thickness of 400 nm has been obtained by optimizing the process parameters [299]. 9.1.6. Composition and properties of LT-PE oxynitride films As-deposited LT-PE oxynitride films have been analyzed by ellipsometry and FTIR spectroscopy. Their optical refractive index n varies between 1.41 and 1.81 (to be compared with 1.46 and 2.05 for stoichiometric Si02 and Si3N4 respectively). The pulse frequency of the laser is found to influence the value of n: an increase in frequency leads to a decrease in n (0.001 per Hz), when all other parameters are kept constant [299].

Silica, Silicon Nitride and Oxynitride Thin Films

127

FTIR spectra reveal the existence of small concentrations of O-H, Si-OH, N-H and Si-H groups in the deposited films, i.e. that the quality of these films is, in this respect, comparable to PECVD films. 9.2. ELECTRON-ENHANCED PROCESSES

9.2.1. Electron-enhanced nitride growth Atomic and ionized nitrogen are effective in nitriding silicon at low-temperature. Uniform ultra thin nitride films can be grown at low temperature (T < 50°C) on Si(100)-2xl surface, in a UHV environment, by exposing the substrate to low anmionia pressures (P(NH3) < 10"6 mbar) and by simultaneously bombarding it with a flux of high-energy electrons (0.3 keV < E < 2.5 keV, flux < l.SxlO^O cm-2 s-l) [88, 141]. The rate of Electron-Enhanced (EE) nitride growth at room temperature for: a partial pressure P(NH3) of 3x10"^ mbar, an electron energy of 1.3 keV, and a flux of 1.3 X 1020 cm-2 s-1, is found to be half the growth rate at 950X (i.e. 0.8 nm/h). The growth rate doubles when the ammonia pressure doubles. This electron-enhanced growth has been attributed to the dissociation of NH3 molecules adsorbed at room temperature on the Si(lOO) surface of the wafer. This dissociation yields nitrogen atoms [136-138] and ions, in an excited state, which readily react with the underlying silicon atoms. Consequently, the local growth of silicon nitride can be obtained by using direct electron beam writing [305, 306]. The Si dangling bonds from the reconstructed silicon surface have been shown to be effective in the dissociation of NH3, forming Si-N and Si-H bonds [308, 309]. The breaking of Si-H bonds by electron beam thus restores the Si dangling bonds and the surface reactivity. 9.2.2. Electron-enhanced nitridation of silica films For temperatures below 800°C, the direct thermal nitridation of silica by NH3 cannot be achieved. The nitridation of silica can however be performed at room temperature using an electron beam [141, 215-227]. The electron energy can be as low as 3 eV (using an inverse photoemission electron gun). The usual process parameters are: 3 eV < E < 300 eV, with an electron flux < 10^6 cm-^ s'l. The use of anmionia is essential in this EE-nitridation process since N2 alone or mixtures of N2 and H2 are shown to be ineffective. The extent of nitridation is found to depend on electron energy and fluence and on P(NH3). The amount of incorporated nitrogen increases as LogP(NH3). The irradiation of Si02 with high-energy electrons induces the breaking of Si-0 bonds [241, 288]. A substantial amount of Si-O bond breaking is obtained for a total electron flux above - 2 x lO^^ cm"^ s-1 [141, 216]. However, lower electron fluxes have been shown to be sufficient to produce a substantial amount of oxide nitridation.

128

B, Balland and A, Glachant

This clearly shows that the dissociation of NH3 and/or the ionization of nitrogen (depending on the energy of the primary electrons) play an important role in inducing the reaction. In fact, the reacting species are NHx amine groups (with 0 < x < 3), which are created by the impact of primary and secondary electrons [141, 219]. 9.2.3. Composition and properties of LT-EE oxynitride films Auger in-depth [N] profiles, measured in LT-EE nitrided silica films show that [N] increases with electron energy. For example, 4-eV electrons induce a superficial reaction at room temperature (limited to a depth of « 1 nm from the oxide surface) [225], while 1.3-keV electrons lead to the formation of an inhomogeneous oxynitride whose N content decreases down to the Si02-Si interface [141, 216]. Compared with the Raman spectra of thermal NO films, those of LT-EE oxynitride films exhibit additional lines attributed to a-Si3N4 and hydrogenated species (Si-H, N-H, 0-H). These results are confirmed by IR analyses showing: a strong absorption due to nitrogenated species (N-H, N-0 and Si-N), the formation of a nitride environment with Si-N local groups and the presence of many N-H and Si-H species [141]. This electron-enhanced nitridation process is shown to produce nitrided oxide films which offer a better resistance to energetic electron bombardment than thermal NO-films [141]. 9.3. ION-ENHANCED DEPOSITION PROCESSES

We limit next our review of Ion-Enhanced (IE) nitridation techniques to reactive RFsputtering [125, 126, 307, 310-314]. Ion-implantation [100-104, 127, 300] cannot be considered as an LT-nitridation process since it generally requires an annealing above 850°C to form the insulating thin film. 9.3.1. Nitride deposition by RF-sputtering Amorphous silicon nitride films can be deposited on Si wafers at a high rate, at a temperature slightly above room temperature, by the DC reactive sputtering of a pure Si target in an (Ar + N2) atmosphere, using a sputtering apparatus of the planar magnetron type [125]. Films as thick as 600 nm can be deposited. The total gas pressure is set a t « 8.10-^ mbar, when the N2 partial pressure is varied from 3 to 8.10-^ mbar [125]. The deposition of nitride films at room temperature is also possible using the interaction of a monoenergetic nitrogen ion beam (generated in a separate duoplasmatron ion source), with a Si target located in the deposition chamber (the chamber pressure is maintained at the required low level i.e. < 8 xlO'^ mbar) [126, 307]. Regardless of the partial pressure of N2 (8 x 10"^ to 10-"^ mbar), the stoichiometry of the films depends on the sputtering yield of Si in the 0.4-20 keV range. Nitride layers can be obtained at low DC-voltage, but only with a low deposition rate («1 nm/min).

Silica, Silicon Nitride and Oxynitride Thin Films

129

The incorporation of nitrogen into the growing layer could be due to any of the following three processes: • Nitrogen ions, first implanted into the target, are then sputtered, bonded or not to Si atoms, by the subsequent ion bombardment. The [N]/[Si] ratio of the deposited layer varies conversely with the sputtering yield of silicon, • N2 molecules could be adsorbed on the target and then sputtered as atomic or bonded N-Si species towards the growing film, • N2 molecules could be adsorbed on the growing film itself during its formation. The additional irradiation of the growing nitride film by an electron beam increases the probability that N2 molecules adhere to the surface and increases the deposition rate. 9.3.2. Composition and properties of deposited nitride films The properties of nitride films deposited by RF-sputtering have been investigated [125]. They are shown to depend on the partial pressure of N2. Films deposited with P(N2)>5x 10"^ mbar exhibit excellent properties: (2.06 < n < 2 . 1 0 , etch rate<7 nm/min, resistivity - 10^^ il.cm, residual film stress ~ 12.3 x 10^ dyn/cm^) even if they have been deposited at an elevated deposition rate (e.g. > 100 nm/min). The [N]/[Si] ratio of these nitride films has been measured using RBS and AES [126, 307]. The sputtering yield of silicon must be reduced to 0.5 atom/ion to get [N]/[Si] = 1.25, i.e. to reach stoichiometry. 9.3.3. Oxynitride deposition by RF-sputtering Amorphous oxynitride thin films can also be prepared by the reactive RF sputtering of a silicon target in a (O2 + N2) gas mixture [310-314]. The [0]/[N] ratio of the deposited film can be adjusted by varying the [02]/[N2] gas ratio in the ambient. The residual pressure in the sputter chamber must be reduced to lO-'^ mbar prior to deposition. The other process parameters have the following typical values: total gas pressure = 8 x 10"^ mbar, RF power = 400 W, DC voltage = 3.6 kV, substrate temperature = 127°C, and deposition rate = 6 nm/min. Film thicknesses can be assessed by interferometry (± 5%) or by stylus profilometry. The refractive index at X, = 589 nm is shown to vary between 1.96 (100% N2) and 1.57 (76% N2; 23% O2). Various composition parameters (0.43 < [0]/([0]+[N] < 0.94) have been obtained and measured (through AES and RBS) [310-314]. 9.4. PLASMA-ENHANCED (PE) PROCESSES

Plasma-assisted processes have been used in order to fabricate, at relatively low temperatures, layers whose thickness is compatible with microelectronics.

B, Balland and A. Glachant

130

9A.\. Principle The experimental plasma-enhanced deposition apparatus operates in the 250-1200°C temperature range, using excitation frequencies between 30 kHz and 2.45 GHz. The basic idea is to introduce energy into a gaseous medium through an RF discharge so that the molecules get "heated". These molecules can then deposit on (or react with) a substrate at low ambient temperatures [105]. Excitation can be generated in the inductive or capacitive mode. In the latter case, ring-shaped electrodes [95], and parallel plates are used. The formation of the plasma between two neighboring Si wafers, as in the case of a multiple electrode holder (illustrated in Fig. 1.110.), can reduce considerably the damage done to the internal wall of the reactor. There also exists plasma systems [79] in which the plasma chamber is separated from the reaction chamber. The defects introduced in the sample by exposure to charged particles are thus eliminated and the reaction conditions are well controlled. In this case, the reactive species are transferred from the plasma to the reaction chamber by means of a differential pumping system [79]. The possible deposition on the samples, of silica sputtered off the plasma chamber walls, can also be minimized by placing the wafers sufficiently far from the RF electrode [79-84]. This results in a redeposition of sputtered silica on that wall, before the sputtered material can reach the wafers. RF power.

Ti rods in ^ quartz tube

Gas inlet (N2, NH3)

Wafers

Fig. 1.110' Schematic view of a plasma-enhanced nitridation reactor (after [229] modified)

Furnace

Quartz tube

Vacuum outlet

The use of a DC bias makes possible either the reactive etching of the Si wafer (cathode biasing eliminates the natural oxide layer [84]) or an enhancement of the nitride growth rate (anodic nitridation [84, 115]). Nitride films can be fabricated by plasma-enhanced CVD on substrates kept at a "moderate" temperature (i.e. between 150 and 500''C). The plasma parameters can vary widely: RF frequency (30 kHz-2.45 GHz), RF power (10-1200 W), gas mixture, total pressure (0.25-7 mbar) [116, 121, 123, 310]. The maximum achievable growth rate can be as large as 600nm/min (for plasma-enhanced CVD deposition) or 0.13nm/min (for direct plasmaenhanced nitridation [162]).

Silica, Silicon Nitride and Oxynitride Thin Films

131

9A.2. Plasma-enhanced nitridation of silicon The maximum thickness of films produced by the direct nitridation of Si in a nitrogen plasma is about 10 nm [85]. The obtained films are indeed silicon nitride but exhibit some oxygen and carbon contamination. A typical dielectric strength of ~ 10 MV/cm has been measured. These nitride films can be considered as potential candidates to fabricate ultra thin gate, tunnel, and DRAM memory insulators for VLSI devices. 9A.3. Plasma-enhanced nitridation of silica The nitridation of thin silica films has been performed in N2 or NH3 plasmas at temperatures ranging from 300 to 700°C. The plasma is ignited by a 90-450 kHz RF generator. The frequency range is chosen well below the ion transit frequency (- 4 MHz), to maximize the ion bombardment of the substrate, (the substrate is a silica film 10 to 20 nm thick, thermally grown on p-type Si(lOO)). The other main process parameters are: pressure (= 0.1-1.0 mbar), RF-power (= up to 50 mW/cm^) and t > 2 h, [229]. The [N], [O] in-depth profiles measured by AES, reveal: an enhanced nitridation at the surface of the oxide, little nitrogen incorporation in the oxide bulk, and the existence of a small nitrogen pile-up at the Si02-Si interface, when NH3 is used, or the formation of a near homogeneous oxygen-rich oxynitride, when N2 is used [229]. These profiles have been confirmed by etch rate measurements. 9.4.4. Plasma-enhanced nitride deposition Several gas mixtures can be used: NH3+SiH4, SiH4+N2+H2, SiH4+N2(+Ar), NH3+SiH4+N2. Let us consider the case of a NH3 + SiH4 gas mixture and a plasma system with two separate regions (one for reaction and one for deposition). A plasma is generated in the N2 (or NH3) inlet tube. The activated nitrogen (N2*) reacts with SiH4 (diluted in a suitable inert gas like Ar) and forms Si3N4 (or more generally SixNy) according to the following reaction [110]. The reaction product deposits then as a thin film on the substrate surface. 2 N2''+ 3 SiH4-^ Si3N4 +6H2

(1.31)

Chemi-luminescence emission measurements performed during PECVD show that in fact Si-H, N-H and Si-N radicals, as well as excited N2* molecules, are present in the reaction zone [110]. It has been inferred that two kinds of reaction take place: homogeneous (in the reaction volume) and heterogeneous (at the substrate surface). 9.4.5. Composition and properties of PECVD nitrides Depending on the preparation conditions, the deposited films display an excess of Si [76] and a substantial [H] content (from 4 to 39 at.% [109]). The etch rate of the films thus produced, measured at 25°C using a 13:2 NH4F/HF solution, is found to decrease with the hydrogen content [109]. Moreover, if the [Si-H]/[N-H] ratio increases, the refractive index increases also [114].

132

B. Balland and A. Glachant

The ammonia-free process (using a N2 + SiH4 mixture) leads to the formation of a nearly stoichiometric nitride film with little N-H bonds and less hydrogen [112]. The resistivity of the films thus produced exceeds lO^^ Q.cm and their dielectric strength is about 6xl06V/cm[lll]. 9A.6. Plasma-enhanced oxynitride deposition Oxynitride films can be deposited by plasma-enhanced CVD for substrate temperatures ranging from room temperature to 430'^C, for a wide range of plasma parameters (RF frequency: 30 kHz-2.45 GHz, RF power: 5-300 W, gas mixtures: NH3 + SiH4 + N2O, SiH4 + N20, SiH4 + N2 + 02, SiH4 + N2 + N20, N2O + NH3 + SiH4 + H2, total pressure: 0.7 X 10-3 mbar-1.2 mbar) [310-315, 317, 318]. Film as thick as 4 |iim can be achieved using the PECVD method [315]. Oxynitride films can also be grown by the direct nitridation of a silicon substrate using the same parameters [237] as above but in a gas mixture of: NH3 + H2. In this case, the film does not exceed 6 nm [110]. After the chemical etching of the sample to eliminate the native oxide layer, a residual oxide film, only 0.3 nm thick remains. An 0/N ratio of 1.5 and a significantly smaller amount of excess Si, compared to ultra thin thermal oxide films, is found using AES. Oxynitride films, only 1.3 nm thick, tum out to be good oxidation barriers up to 980°C and reveal excellent resistance against electron irradiation. Various SiOxNyHz film compositions have been achieved by PECVD, depending on the deposition parameters [315]. An SiO2.06N0.09H0.i8 sample has revealed a refractive index of 1.46 (at X = 632.8 nm), while an SiO0.70N0.24H0.24 sample has exhibited a 1.94 value. The optical forbidden gap EQ has been deduced from Tauc's law [295]. E Q is found to vary between 5.6 ± 0.1 eV (for [0]/([0+N]) = 0.046) and 8.9 ± 0.1 eV (for [0]/([0+N]) = 0.984). 9.4.7. Applications A bilayer made up of SiOxNy and SiNx deposited by PECVD has been used as the gate insulator of an amorphous silicon thin film transistor (TFT) [316]. The presence of this bilayer leads to a decrease in the density of trapped charges, if the thickness of the SiNx layer is reduced. Unlike what happens when the SiNx l^y^r is used alone, the bilayer introduces no deterioration in the switching characteristics. The stability of MIS tunnel diodes, which use ultra thin oxynitride films (1.3 nm) is shown to be better after a "life test" at 250°C than regular MIS tunnel diodes which use an oxide film of the same thickness [ 162]. 10. SUMMARY AND CONCLUSION A continuous research effort is under way to improve the characteristics of dielectrics needed for VLSI and ULSI devices. Among the several materials which have been investigated to replace thin thermal silica, mostly, silicon nitrides and oxynitrides have retained attention.

Silica, Silicon Nitride and Oxynitride Thin Films

133

Silicon nitride is attractive because it is an excellent barrier against the diffusion of doping or metal atoms, because of its radiation hardness and because of its good resistance to oxidation. It is, however, inadequate due to its high hydrogen content, its poor interface with silicon and its large leakage current. Thus silicon nitride alone can only be applied towards local oxidation technology. Thin Si3N4 - Si02 bilayers, used in MNOS structures, have resulted in unsatisfactory threshold voltage stability (due to the high trapping efficiency of both the nitride bulk and the nitride/oxide interface). It was thus challenging to achieve the direct conversion of Si02 thin films into SiOxNy by directly incorporating nitrogen into the film. This can be done using three main processes: the thermal nitridation of Si02 in ammonia (NO thin films), the thermal reoxidation of nitroxide thin films (RONO thin films) or the thermal oxidation of sihcon: in N2O (or NO) or successively in O2 and N2O (or NO) (RTON thin films). • The thermal nitridation in anmionia of thin thermal Si02 films (« 10 nm) has attracted attention for a number of reasons: better resistance to irradiation, greater resistance to impurity diffusion, lower interface and trapping densities than MNOS structures, higher dielectric constant, higher dielectric strength, greater bias and temperature stability and greater stability when submitted to high current density. The nitroxides thus formed exhibit in fact one or two maxima in the nitrogen concentration profile, below the film surface and/or at the insulator/silicon interface). These oxynitride or nitride layers are interesting because they offer two efficient barriers against impurity diffusion (at the gate/insulator and insulator/silicon interfaces) and resistance to oxidation (at the insulator surface). The interfacial nitrogen pile-up can be minimized using Rapid Thermal Nitridation. However, thin oxide films nitrided in NH3 cannot prevent the incorporation of hydrogen at the dielectric/silicon interface, and exhibit a large electron trapping. • An additional reoxidation of nitrided oxides reduces both electron trapping and interfacestate generation remarkably, without affecting other properties. However, under such conditions, it has been observed that the masking effect of the oxynitride layer vanishes as the nitrogen content from the gate-nitroxide film interfacial region decreases due to reoxidation. Hole trapping at the silicon-insulator interface is also expected to occur if the annealing treatments are carried out without the presence of an intentional (i.e. controlled) low partial pressure of oxygen. The RONO layers still possess improved electrical characteristics, enhanced resistance to dopant diffusion and also improved radiation hardness, compared to ultra thin Si02 films. However, this process is not easy to optimize and multi-step HT cycles are not desirable if one wants to manufacture ULSI circuits. • To solve these problems, in recent years. Rapid Thermal Processing (RTP) has been proposed. RTP makes possible: fast changes in process temperature and gases and short processing times. These advantages also enable one to perform multiple processing in a single chamber. However, the formation of high quality RONO films requires a careful optimisation of the RTP sequential process.

134

B, Balland and A. Glachant

An alternative approach is to grow thin oxynitride films in an RTP reactor using nitrous oxide (N2O) or O2 followed by N2O. The RTP method permits one to avoid long HT treatments and to better control the thickness of the oxynitride film. This hydrogen-free process incorporates a low concentration of nitrogen (~ 5 at.%) at the Si02-Si interface and thus, the ultra thin (< 10 nm) oxynitrides formed still offer an interesting barrier to the diffusion of dopant impurity from the substrate. These ultra thin oxynitride layers display: a high charge to breakdown, reduced interface generation and less charge trapping compared to Si02, NO and RONO thin films. However, only the oxynitride films formed via consecutive oxidation in O2 and N2O ambients have a large charge-to-breakdown value (> 90 C.cm-^) and display a quite uniform interface ordered within at least one or two atomic layers. Moreover, the levels of N incorporated in these dielectrics may not be sufficient to prevent boron penetration. Oxynitrides grown in NO retain the excellent endurance properties of oxynitrides grown in N2O and form good diffusion barriers due to the higher level of incorporated nitrogen. The properties of the thin insulators reviewed in this chapter are sunraiarized in Table 1.08. 1

DIELECTRICS -> PROPERTIES i

Thermal Oxidized Therma Nitrided oxide Nitride nitride RTN RONO 1 Si02 *

He

1 (low) defect density

*

He He

^ ^^

1 (good) resistance to HF etching

He

^ ^^

He He

^

1 (good) barrier against diffusion

sH

^ ^^

He He

r^ ^ ^

1 (low) electrical leakage

He 4 e He He

^ ^^^

^

^ ^ r^

1 (high) breakdown field

^ ^^

^ ^^

^

1^ ^

(good) resistance to wear out: tBD

^ ^^

^ ^^

^ ^^

(low) density of bulk traps: Not

^ ^^

^ ^^

^ ^^

(low) density of fixed oxide charge: Nj

r^ r^ 1^ ^

He He

^ ^^

He He

He He

(low) density of interface traps: Njt

^ ^ :^ ^

^ ^^^

:^ ^ ^ ^

He He

He He

(high) carrier mobility

^ ^^

He He

^ ^^

(high) dielectric constant ZoZ{

^ ^^

He

^

He He

He

He He

He

^

He

He

^

He He

He

0

^ ^^

He

0

He

He He

He

He

^

1^

dielectric strength *

He

He He

Table 1.08 - The properties of various thin dielectric films for VLSI applications are compared: ( * * * * * ) excellent, f * * *j good, f * *j average, (*)poor, (0) worst, unknown, ( ).

Silica, Silicon Nitride and Oxynitride Thin Films ACKNOWLEDGEMENTS The authors wish to thank the editors, G. Barbottin and A. Vapaille who reviewed this text and contributed many comments and suggestions. They are grateful to G. Barbottin who rewrote the English version of this text.

REFERENCES [I] [2] [3] [4] [5] [6] [7] [8] [9] [10] [10a] [10b] [10c] [lOd] [lOe] [lOf] [lOg] [II] [12a] [12b] [12c] [13] [14] [15a] [15b] [15c] [16] [17] [18] [19a] [19b]

M. M. Attala, E. Tannenbaum and J.E. Scheibner, Bell syst. /., 38 (1957) 749 A.S. Grove, Physics of Semiconductor devices (John Wiley & Sons, New York, 1967) S.K. Ghandhi, The Theory and Pratice of Microelectronics (John Wiley & Sons, New York, 1968) S.K. Ghandhi, VLSI Fabrication Principles (John Wiley & Sons, New York, 1983) E.H. NicoUian and J.R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology (John Wiley & Sons, New York, 1982) S. M. Sze, Physics of Semiconductor devices (John Wiley & Sons, New York, 1981) S. M. Sze, VLSI Technology (McGraw-Hill, New York, 1983) S. M. Sze, Semiconductor devices - Physics and Technology (John Wiley & Sons, New York, 1985) C.Y. Chang and S. M. Sze, ULSI Technology (McGraw-Hill International Editions, New York, 1996) Instabilities in Silicon Devices, eds. : G. Barbottin and A. Vapaille (Elsevier Science Publishers B.V. (North-Holland) - Vols. 1 and 2 S.Rigo, «Silica Films on silicon: Techniques and mechanisms of growth. The theories of silicon oxidation», in: [10], Vol. 1, Chap. 1, (1986) p. 5-100 B. Balland, «Defects in Silica Films» in: [10], Vol. 1, Chap. 2, (1986) p. 101-153 B. Leroy, «Passivation-induced phenomena in silicon substrates» in: [10], Vol. 1, Chap. 3, (1986) p. 155-210 J. Wolters, J.F. Verwey, «Breakdown and wear-out phenomena in Si02» in: [10], Vol. 1, Chap. 6 (1986) p. 315-362 M. Garrigues and B. Balland, «Hot carrier injection into Si02» in: [10], Vol.1, Chap. 9, (1986) p. 441-501 B. Balland and G. Barbottin «Carrier trapping and detrapping», in: [10], Vol. 2, Chap. 10, (1989) p. 84-166 E. Klausmann, W.R. Fahrner and D. Braunig «Intrinsic states and fixed charges of the Si-Si02 interface» in: [10], Vol. 2, Chap. 11-12, (1989) p. 171-248 E. Arai, ffiDM 83 Technical Digest, Abs. 2.1. (1983) 19 R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bassous and A.R. Leblanc, IEEE J. Sol State Circuits, SC-9 (1978) 256 R.H. Dennard, IEEE Trans, on Electron Dev. ED-31 (1984) 1549 R.H. Dennard and M.R. Wordeman, Physica 129B (1985) 3 G. Baccarani, M.R. Wordeman and R.H. Dennard, IEEE Trans, on Electron Dev, ED-31 (1984) 452 G.D. Hutchinson, Sol State Technology, Vol. 40, N°5 (1997) 67 S.K. Lai, Ext. Abstracts of the Electrochemical Society Meeting, Abs. 214 (1981) 541 S.K. Lai, in: Semiconductor Silicon, eds. H.R. Huff, R.J. Kriegler and Y. Takeishi (The Electrochemical Society, 1981) p. 135-210 S.K. Lai, J.Lee and V.K. Dhamer, lEDM Tech. Dig., (1983) 190 P.K. Chatterjee, W.R. Hunter, T.C. HoUoway and Y.T. Lin, IEEE Trans, on Electron Dev. Lett. 1 (1980) 220 P.L. Shah and R.H. Havemann, in : VLSI Electronics Microstructure Science, ed. N.G. Einspruch, (Academic Press, London, 1983), Vol 7, Chap. 2, p. 39 S.S. Wong, Ph.D thesis, Univ. of California, Berkeley, 1983 J.A.A. Nemetz, R.E. Tressler, Sol. State Technol. February 83 (1983) 79 J.A.A. Nemetz, R.E. Tressler, Sol. State Technol. September 83 (1983) 209

135

136

[20a] [20b] [20c] [20d] [20e] [20f| [20g] [20h] [21a] [21b] [21c] [21d]

[22] [23] [24] [25a] [25b] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43a] [43b] [44] [44a]

B. Balland and A. Glachant

T. Ito, T. Nozaki, H. Arakawa, M. Shinoda, Appl Phys. Lett, 32 (1978) 330 T. Ito, S, Hijiha, T. Nozaki, H. Arakawa, M. Shinoda, Y. Fukukawa, J. of Electrochem. Soc, 125, (1978)448 T. Ito, H. Arakawa, T. Nozaki, H. Ishikawa, /. of Electrochem. Soc, 111 (1980) 2248 T. Ito, T. Nozaki and H. Ishikawa, J, Electrochem. Soc, 127 (1980) 2053 T. Ito, H. Ishikawa,.and Y. Fukukawa, Jap. J. Appl. Phys,. 20 (1981) 33 T Ito, T. Nakamura and H. Ishikawa, IEEE Trans. Electron. Dev., ED-29 (1982) 498 T. Ito, in : Jap. Annual Reviews in Electron. Comput. & Telecom. (Semiconductor Technologies), ed. J. Nishizawa (North Holland, Tokyo, 1982), Chap. 6, p. 69-81 T. Ito, I. Kato, T. Nozaki, T. Nakamura, H. Ishkawa, Appl. Phys. Lett., Vol. 3 (1981) 370 M.M. Moslehi and K.C. Saraswat, 4th Symp. on VLSI technology, Abs. 7.4. (1983) 92 M.M. Moslehi and K.C. Saraswat, Proceedings of the IEEE international Electron Devices Meeting, lEDM 84 (1984) 165 M.M. Moslehi and K.C. Saraswat, IEEE Trans. Electron Dev. ED-32 (1985) 106 M.M. Moslehi, S.C. Shatas and K.C. Saraswat, Proceedings of the Fifth International Symposium on Silicon Materials Science Technology (eds.: H.R. Hube and B. Kolbesen) Electrochemical Soc. (1986) 379 E. Harari, J. Appl. Phys., 49 (1978) 2478 M.S. Liang, Y.T. Yeow, C. Chang, C. Hu and R.W. Brodersen, lEDM 82 - Technical Digest Abs. 3.3. (1982) 50 R.F. de Keersmaecker, Physical Problems in Microelectronics, (World Scientific Publishing Co Pte Ltd, Singapore, 1985), 81 E.H. NicoUian and A. Reisman, J Electron. Mater. 17 (1987) 4 A. Reisman, E.H. Nicollian, C.K. Williams, Merz, J. Electron. Mater. 26 (1987) 45 P. Balk, DJFOS 83, eds.: J.F. Verweij and D.P. Wolters, publis. by Elsevier Sc. (North-Holland-1983) R.D. Rung, H. Momose and Y. Nagakubo, Technical Digest IEEE International Electronic Device Meeting 82 (19S2) 237 R. Szeto, H. Fu, K. Chiu, J. Manoliu, ECS Fall Meeting extended Abstracts, 82-2 (1982) 277 T. Morimoto, H.S. Momose, K. Yamabe and H. Iwai, ESSDERC 90 (Nottingham, September, 1990) M. Ishara, T. Matsumoto, S. Shimizu, K. Mitsuada and K. Shimohigashi, ISSCC Digest of technical Papers (19S2) 74 C.A. Benevit J.M. Cassard, K.L. Dinmiler, A.C. Dumbri, M.G. Mound and F.J. Procyk, ISSCC Digest of technical Papers (1982) 76 G. Verma and M. Mielke, Proc of the 1988 International. Reliability Phys. Symp., (1988) 158 H.C. Kirsch, Digest of the IEEE International Solid State Circuits Conference (1985) 256 W. S. Johnson, G. Perlegos, A. Renninger, G. Kuhn and T. R. Ranganath, ISSCC Digest of Technical Papers (1980) 152 H. Fukuda, M. Yasuda, T. Iwabuchi and S. Ohno, IEEE Electron Device Lett, Vol. 12, N° 11, (1991) 587 T.S. Chao, C.L. Lei, J. Electrochem. Soc, 138 (1991) 1756 I.W. Boyd, J.B. Wilson, Appl. Phys. Lett., 50 (1987) 320 LP. Lisvovskii, V.G. Litovchenko, V.V. Khatko, Microel. Eng., 22 (1993) 39 C.P. Ho, J.D. Plummer, J.D. Meindl, B.E. Deal, J. Electrochem. Soc, 125 (1978) 665 D.W. Hess, B.E. Deal, / Electrochem. Soc, 126 (1979) 1523 G. Camera Roda, F. Santarelli, G.C. Sarti, / Electrochem. Soc, 122 (1985) 1910 F.P. Fehlner, /. Electrochem. Soc, 119 (1972) 1723 B.E. Deal, A.S. Grove, J. Appl. Phys., 36 (1965) 3770 B.E. Deal, J. Electrochem. Soc, 111 (1980) 979 A.C. Adams, T.E. Smith, C.C. Chang, J. Electrochem. Soc, 111 (1980) 1787 P.J. Caplan, E.H. Poindexter, B.E. Deal, R.R. Razouk, J. Appl. phys., 50 (1979) 5847

Silica, Silicon Nitride and Oxynitride Thin Films [44b] [44c] [45a] [45b] [45c] [46] [47] [48] [49] [50a] [50b] [51] [52] [53] [54] [55] [56] [57] [58] [59] [60] [61] [62] [63] [64] [65] [66] [67] [68] [69] [70a] [70b] [71] [72] [73] [74a] [74b] [75a] [75b] [76] [77] [78] [79] [80] [81] [82] [83]

137

E.H. Poindexter, PJ. Caplan and R.R. Razouk, J. Appl Phys., 52 (1981) 879 E.H. Poindexter and P.J. Caplan, Insulating Films on Semiconductors, eds.: M. Schultz and G. Pensel, (Springer, Beriin, 1981) 150 H.Z. IVlassoud, J.D. Plummer, E.A. Irene, J. Electrochem. Soc, 132 (1985) 1745 H.Z. Massoud, J.D. Plummer, E.A. Irene, J. Electrochem. Soc, 132 (1985) 2685 H.Z. Massoud, J.D. Plunmier, E.A. Irene, J. Electrochem. Soc, 132 (1985) 2693 L.N. Lie, R.R. Razouk, B.E. Deal, J. Electrochem. Soc, 129 (1982) 2828 M. Hirayama, H. Miyoshi, N. Tsubouchi, H. Abe, IEEE Trans. Electron Dev., ED-2$ (1982) 503 E.A. Irene, E. Tiemey, J. Angilello, J. Electrochem. Soc, 129 (1982) 2594 D.A. Baglee, Proc. 22nd IEEE Rel Phys. Symp. (1984) 152 C. Hu, J. Appl. Phys., 55 (1984) 368 C. Hu, Proc. Int. Electron Devices Meeting, (1985) 368 N. Cabrera and N.F. Mott, Kept. Prog. Phys., 12 (1948) 163 I.W. Boyd, Appl Phys. Lett., 42 (1983) 728 C. Hashimoto, S. Muramoto, N. Shiomo, O. Nakajima, J. Electrochem. Soc, 127 (1982) 129 J. Krauser, F. Wulf, M.A. Briere, J. Steiger, D. Braunig, Microel. Eng., 22 (1993) 65 J. Derrien, M. Commandre, Surf. Set., 36 (1982) 32 E.A. Irene, /. Appl. Phys., 54 (1983) 5416 A. Fargeix, G. Ghibaudo, G. Kamarinos, J. Appl. Phys., 54 (1983) 2878 A. Fargeix. G. Ghibaudo, /. Appl. Phys., 54 (1983) 2878 F.J. Himpsel, F.R. Mc Feely, A. Taleb-Ibrahimi, J.A. Yarmoff and G. HoUinger, Phys. Rev., B38 (1988) 6084 A. Ishizaka and S. Iwata, Appl. Phys Lett., 36 (1980) 71 R. Szeto, H. Fu, K. Chiu, J. Manoliu, ECS Fall Meeting extended Abstracts, 82-2 (1982) 277 T. Ohmi, Proceedings of the 14th Symposium on «Advanced Science and Technology of Silicon Materials» (Hawaii, 1991) 264 V. Murali, / Electron. Mater., 18 (1989) 731 V.Y. Doo, IEEE Trans. Electron Dev., ED-13 (1966) 560 F.K. Ueumann, D.M. Brown and E. Metz, J. Electrochem. Soc, 115 (1968) 99 J.V. Dalton and J. Drobek, /. Electrochem. Soc, 115 (1968) 865 B. Balland, M. Lemiti, S. Audisio, J.C. Bureau, J.of Electrochem. Soc, 137 (1990) 2845 J.A. Appels, E. Kooi and M. M. Paffen, Philips Research Report, IS (1970) 118 E. Kooi, J.G. van Lierop and J. A. Appels, J. Electrochem. Soc, 123 (1976) 1117 C.Y. Wu, C.W. King, M.K. Lee, C.T. Chen, C.T. Shih, J. of Electrochem. Soc, 130 (1983) 458 C.Y. Wu, Y.T. Huang, Solid State Electronics, 27 (1984) 203 J.H. Neave, B.A. Joyce, P.J. Dobson and N. Norton, Appl. Phys., A3 (1983) 11 J.M. van Hove, C.S. Lent, P.R. Pukite and P.I. Cohen, J. Vac Sci. Technol., B l (1983) 741 R.G. Frieser, J. Electrochem. Soc, 115 (1968) 1092 W.G. Oldham, IEEE International Electron Device Meeting, (San Francisco, 1982) 216 W.G. Oldham, Y. Shacham-Diamand, P.L. Pai, K. Young, P. Sutardja, Physica, 129B (1985) 53 C.E. Morosanu, Thin Sol. Films, 65 (1980) 171 (and references therein) C.E. Morosanu and E. Segal, Thin Sol. Films, 91 (1982) 251 F. Sequeda and R.E. Richardson, J. Vac Sci. Technol, 18 (1981) 362 M. Lemiti, Ph. D. thesis, I.N.S.A. - University of Lyons, Fr. (1983) R. Botton, Ph. D thesis, I.N.S.A. - University of Lyons, Fr. (1991) R.P.H. Chang, J. Vac ScL Technol, 14 (1977) 278 T.Ito, I. Kato, T. Nozaki, T. Nakamura, H. Ishkawa, Appl Phys. Lett., 3 (1981) 370 H. Nakamura, M. Kaneko, S. Matsumoto, Appl Phys. Lett., 43 (1983) 691 M. Hirayama, T. Matsikawa, H. Arima, Y. Ohmo, N. Tsobuchi, H. Nakata, J. of Electrochem. Soc, 131 (1984) 6563 D. Henry, Y. Pauleau, A. Straboni, Ecole d'ete, Aussois 1983 (les Editions de Physique/CNRS, 1984)

138

[84] [85a] [85b] [86a] [86b] [87] [88] [89] [90] [91] [92] [93] [94] [95] [96] [97] [98] [99] [100] [101] [102] [103] [104] [105] [106] [107] [108] [109] [110] [111] [112] [113] [114] [115] [116a] [116b] [117] [118] [119] [120] [121] [122]

B, Balland and A, Glachant

B. Vuillermoz, A. Straboni, R. Pantel Ext. Abstracts of the Electrochem. Society meeting, 85/1, Abs. 48, (1985) 359 M. Hirayama, T. Matsikawa, H. Arima, Y. Ohmo, N. Tsobuchi and H. Nakata, /. Electrochem, Soc, 131 (1984) 6563 M. Hirayama, T. Matsikawa, H. Arima, H. Nakata, Ext. Abstracts of the Electrochem. Society meeting, 85/1, Abs. 59 (1985) 81 T. Sugii, T. Ito, H. Ishikawa, Appl. Phys. Lett., 45 (1984) 966 T. Sugii, T. Ito, H. Ishikawa, Ext. Abstrats of the 16th Intern. Conf on Solid state Devices and Materials, Kobe, (1984) 433 HJ. Stein, P.S. Peercy and RJ. Sokel, Thin Sol Films, 101 (1983) 291 A. Glachant, D. Saidi, /. Vac. Sci. Technol., B3 (1985) 985 A. Ronda, A. Glachant, B. Balland, J. Phys. supp. E-MRS, 13 (1986), 239 A.I. Kingon, L.J. Lutz and R.F. Davis, / Amer. Ceram. Soc, 66 (1983) 551 J.R. Troxell, D.G. Moss, J. of Electrochem. Soc, 131 (1984) 2353 R.V. Giridhar, K. Rose, Appl. Phys. Lett., 45 (1984) 578 R.P.H. Chang, C.C. Chang, S. Darack, Appl. Phys. Lett., 36 (1980) 999 F.P. Mc Cluskey and R.J. Jaccodine, J. Electrochem. Soc, 136 (1989) 2328 M. Morita, T. Ishihara and M. Hirose, J. Appl. Phys., 56 (1984) 342 A. Shintani, T. Kusaka, S. Mizuo, K. Hayashi, H. Okuhira, 4 th Symposium on VLSI technology, Abs. 7.3., (1983) 90 P. Soukiassian, M.H. Bakshi, H.I. Starnberg, Z. Hurich, T.M. Gentle and K.P. Schuette, Phys. Rev. Lett., 59 (1987) 1488 T.Y. Chin, H. Bemt, I. Ruge, J. of Electrochem. Soc, 129 (1982) 408 R. Hezel, N. Lieske, J. of Electrochem. Soc, 129 (1982) 379 G.E. Thomas, L.J. Beckers, F.H.P. Habraken and A.E.T. Kuiper, Appl. Phys. Lett., 41 (1982) 56 T.Y. Chiu, W.G. Oldham and C. Hovland, J. Electrochem. Soc, 131 (1984) 2110 T. Tsujide, M. Nojiri and H. Kitagawa, J. Appl. Phys., 51 (1980) 1605 M.J. Kim, M. Chezzo, J. of Electrochem. Soc, 131 (1984) 1934 J. Petruzzello, T.F. McGee, M.H. Frommer, V. Rumennik, P.A. Walters and C.J. Chou, J. Appl. Phys., 58(1985)4605 H.F. Sterling and R.C. Swann, Sol. State Electron., 8 (1965) 653 H. Watanabe, K. Katoh and M. Yasui, Jap. J. Appl. Phys., 21 (1982) L341 R.S. Rosier, Sol. State Technol., April 1977 (1977) 63 A.S. Korhonen and E.H. Sirvio, Thin Sol. Films, 96 (1982) 103 R. Chow, W. A. Landford, W.Ke-Ming and R.S. Rosier, J. Appl. Phys. 53 (1982) 5630 L. Bardos, J. Musil and P. Taras, Thin Sol. Films 102 (1983) 107 K. Katoh, M. Yasui and H. Watanabe, Jap. J Appl. Phys., 22 (1983) L231 S. Fujita, N. Zhou and A. Sasaki, Jap. J Appl. Phys., 22 (1983) LlOO H. Watanabe, K. Katoh and M. Yasui, Thin. Sol. Films, 106 (1983) 263 W.A.P. Claassen, W.G.J.N. Valkenburg, F.H.P. Habraken and Y. Tamminga, J. Electrochem. Soc, 130(1983)2419 S.S. Wong and W.G. Oldham, 4th symposium on VLSI Technol. Abs. 7.2. (1983) 88 M. Maeda and H. Nakamura, J. Appl. Phys., 55 (1984) 3068 M. Maeda and H. Nakamura, Thin Sol. Films, 111 (1984) 279 S. Fujita, H. Toyoshima, T. Ohishi and Sasaki, Jap. J. Appl. Phys, 23 (1984) L144 S. Fujita, H. Toyoshima, T. Ohishi and Sasaki, Jap. J. Appl. Phys, 23 (1984) L268 S.S. Wong and W.G. Oldham, IEEE Electron Dev. Lett., EDL-5 (1984) 175 C. Blauw, J. Electrochem. Soc, 131 (1984) 1114 M.M. Moslehi, C.Y. Fu, T.W. Sigmon and K.C. Saraswat, J. Appl. Phys., 58 (1985) 2416 M. Hirayama, T. Matsukawa, H. Arima and H. Nakata, Ext. Abstracts of the Electrochemical Society Meeting, 85/1 Abs. 59 (1985) 81

Silica, Silicon Nitride and Oxynitride Thin Films [123] [124] [125] [126] [127] [128] [129] [130] [131] [133] [134] [135] [136a] [136b] [136c] [137] [138] [139] [140] [141a] [141b] [141c] [142] [143] [144] [145] [146] [147] [148] [149] [150] [151] [152] [153] [154] [155] [156] [157] [158] [159]

139

H.H. Madden, J. Electrochem, Soc, 128 (1981) 625 M. Maeda and Y. Arita, /. Appl Phys., 53 (1982) 6852 Y. Hoshi, M. Naoe and S. Yamanaka, Jap. J. Appl Phys,, 19 (1980) 71 D. Bouchier, G. Gautherin, C. Schwebel, A. Bosseboeuf, B. Agius and S. Rigo, /. Electrochem. Soc, 130 (1983)638 K. Ohta, in : Semiconductor Technologies (ed.: J. Nishizawa) Japan Annual Reviews in Electronics, Computers & Telecommunication (North Holland Publishing Company, 1982) p.280 Y. Takaishi, M. Sakao, S. Kamiyama, H. Suzuki and H. Watanabe, lEDM Tech. Dig., (1994) 839 J.L. Autran, R.A.B. Devine, C. Chaneliere, B. Balland, IEEE Electron Dev. Lett., 18 (9) (1997) 447 C. Chaneliere, J.L. Autran, B. Balland, Materials Science and Enginering R., 22 (6), (1998) p 269-322 (and references therein) T. Kaga, M. Ohfkura, F. Murai, N. Yokoyama, E. Takeda, J. Vac. Sci. Technol. B, 13 (1995) 2329 [132] M.D. Wiggins, R.J. Baird and P. Wynblatt, /. Vac. Sci. Technol., 18 (1981) 965 R.B. Fair, in : Silicon Integrated Circuits, Applied Solid State Science (Supp. B), (Academic Press, New York, 1981)79 Y. Hayafuji and K. Kajiwara, J. Electrochem. Soc, 129 (1982) 2102 M. Taguchi, T. Ito, T. Fukano, T. Nakamura, H. Ishikawa, lEDM 81, Technical digest, Abs. 16.8 (1981)400 A.G. Schrott, S.C. Fain, Surface Science, 111 (1981) 39 A.G. Schrott and S.C. Fain, Surface Science, 123 (1982) 204 A.G. Schrott, Q.X. Su, S.C. Fain, Surface Science, 123 (1982) 223 S.P. Murarka, C.C. Chang and A.C. Adams, J. Electrochem. Soc, 126 (1979) 996 T.N. Wittberg, J.R. Hoenigman, W.E. Moddeman, C.R. Cothern and M.R. Gulett, J. Vac Sci. Technol, 15 (1978) 348 J.F. Delord, A.G. Schrott and S.C. Fain, J. Vac Sci. Technol, 17 (1980) 517 C. Maillot, H. Roulet and G.Dufour, J. Vac Sci. Technol, B2 (1984) 316 A. Glachant, D. Saidi, J.F. Delord, in: Insulating Films on Semiconductor 85, eds. J. J. Simonne and J. Buxo (Elsevier Science Publishers B. V., North Holland, 1986) 29 A. Glachant, D. Saidi, J.F. Delord, Surface Science, 168 (1986) 672 A. Glachant, in: Trends in Vacuum Science & Technology, Vol. 1, ed.: J. Menon (council of Research Integration, Trivandrum, 1993), p. 13-56 J.W. Evans and S.K. Chatterji, J. Phys. Chem., 62 (1958) 1064 M.I. Kamtchatka and B.F. Ormont, Rus. J. Phys. Chem., 45 (1971) 1246 C.Y. Wu, C.W. King, M.K. Lee, C.T. Chen, J. of Electrochem. Soc, 129 (1982) 1559 J.R. Monkowski, S.Y. Perng, J.A. Nemetz and R.E. Tressler, Ext. Abstracts of the Electrochem. Soc Meeting, S3/2Abs.310 (1983) 488 M.M. Moslehi and K.C. Saraswat, Ext. Abstracts of the Electrochem. Soc. Meeting, 32 Abs. 126 (1983) 199 J.F. Delord, Surface Science, 162 (1985) 717 S. Rigo, Nucl Instr. and Meth., B64 (1992) 1 C. Maillot, H. Roulet, G. Dufour, F. Rochet and S. Rigo, Appl Surf. Sci., 26 (1986) 326 J.L. Bischoff, L. Kubler and D. Bolmont, Surf. Sci., 209 (1989) 115 J.L. Bischoff, L. Kubler and D. Bolmont, J. Non Cryst. Sol, 97/98 (1987) 1407 J.L. Bischoff, L. Kubler and D. Bolmont, Phys. Rev., B 39 (1989) 3653 J.C. Bureau, K. Chafik, Z. Sassi, B. Balland and A. Glachant, Adv. Mater. Research, 142 (1994) 601 Y. Hayafuji and K. Kajiwara, J. Electrochem. Soc, 129 (1982) 2102 D. Hardy and K.H. Jack, Nature 180 (1957) 332 L. Niihara and T. Hirai, J. Mater. Sci.,12 (1977) 1233 R. Marchand, Y. Laurent and J. Lang, Acta Crystallographica, B 25 (1969) 2157 H.M. Jennings, J.O. Edwards and M.H. Richman, Inorganica Chimica Acta 20 (1976) 167 S. Ren and W.Y Ching, Phys. Rev., B 23 (1981) 5454

140

[160] [161a] [161b] [162] [163] [164] [165] [166] [167] [168] [169] [170] [171] [172] [173] [174] [175] [176] [177] [178] [179] [180] [181] [182] [183] [184] [185] [186] [187] [188] [189] [190] [191] [192] [193] [194] [195] [196] [197] [198]

B. Balland and A. Glachant

P.H. Holloway and HJ. Stein, J Electrochem, Soc, 123 (1976) 723 M.N. Rahaman and AJ. Moulson, J. Mater. ScL Lett, 16 (1981) 2319 M.N. Rahaman and A.J. Moulson, J, Mater, ScL, 19 (1984) 189 R. Hezel, T. Meisel and W. Streb, J. Appl Phys., 56 (1984) 1756 E.A. Taft, J. Electrochem. Soc, 118 (1971) 1341 J. Franz and W. Langheirich, Sol. Stat. Electron., 14 (1971) 499 S.I. Raider, R. Flitsch, J.A. Aboaf and W.A. Pliskin, J. Electrochem. Soc, 123 (1976) 560 J. Hui, T.Y. Chiu, S. Wong and W.G. Oldham, IEEE Electron Dev. Lett., 2 (1981) 14 S.S Chao, J.E. Tyler, D.V. Tsu, G. Lucovsky and M.J. Mantini, /. Vac Sci. Technol, A 5 (1987) 1283 G. Gunkel, D. Schalch and A. Scharmann, Phys. Stat. Sol. (a), 69 (1982) Kl 31 P. Hesto, C. Pellet, C. Schwebel, A. Bosseboeuf, D. Bouchier, E. Dupont-Nivet, J.L. Leray and M. Raffaelli, Annales de Physique 14 (1989) 557 S. Fujita, N. Zhou and A. Sasaki, Jap. Appl. Phys., 22 (1983) LlOO O.C. Arnett and B.H. Yun, Appl Phys. A3 (1975) 11 S. Luby, R.N. Lujagin, N. Doshikova, L.N. Alexandrov and J. Cervenak, Sol. State Electron., 13 (1970) 1097 P. Fahey, R.W. Dutton and M.M. Moslehi, Appl. Phys. Lett., 43 (1983) 683 P. Fahey, G. Barbuscia, M.M. Moslehi and R.W. Dutton, Appl. Phys. Lett., 46 (1985) 784 Y. Hayafuji, K. Kajiwara and S. Usui, J. Appl. Phys., 53 (1982) 863 A. Shintani, T. Kusaka, S. Mizuo, K. Hayashi and H. Okuhira, 4th Symposium on VLSI Technology Abs. 7.3 (1983) 90 F.H.P.M. Habraken, A.E.T. Kuiper, Y. Tamminga and J.B. Theeten, /. Appl. Phys., 53 (1982) 6996 S.I. Raider, R.A. Gdula and J.R. Petrak, Appl. Phys. Lett., 27 (1975) 150 R.J. Aucoin, M.L. Naiman, F.L. Terry and R. Reif, J. Electrochem. Soc: Reviews and News, Abs. 377 (1981)913 T.T.L. Chang, H.S. Jones, C.S. Jeng, W.S. Lee, S.K. Lai and V. Dham, IDEM 82 Technical Digest, Abs. 30.8. (1982) 810 H.R. Grinolds, S.S. Wong, J.W. Ekstedt, C.G. Sodini, S.H. Kwan, K.H. Jackson and L. Martinez, lEDM, Technical Digest, Abs. 3.1. (1982) 42 T. Ito, T. Nakamura and H. Ishikawa, / Electrochem. Soc, 129 (1982) 184 J. Amano and T. Ekstedt, Apll. Phys. Lett., 41 (1982) 816 M. Saitoh, M. Sakamoto, K. Hamano, K. Kobayashi and M. Hagiwara, Ext. Abs. of the Electrochem. Soc Meeting 82-1, Abs. 200 (1982) 320 S.S. Wong, S.K. Kwan and H.R. Grinolds, Proc of the Symposium on silicon nitride thin insulating films of the Electrochemical Society (1983) 346 F.L. Terry, R.J. Aucoin, M.L. Naiman and S.D. Senturia, IEEE Electron Dev. Lett., 4 (1983) 191 R. K. Pancholy and F. M. Edermann, IEEE Trans. Nucl. ScL, NS-SO (1983) 4141 Y. Yoriume, J. Vac ScL Technol, Bl (1983) 67 S. Mizuo, T. Kusaka, A. Shintani, M. Nanba and H. Higuchi, J. Appl Phys., 54 (1983) 3860 F.H.P.M. Habraken, E.J. Evers and A.E.T. Kuiper, Appl Phys. Lett., 44 (1984) 62 S. Tung, N.M. Johnson and S.A. Lyon, Appl Phys. Lett., 44 (1984) 316 R.P. Vasquez, M.H. Hecht, F.J. Grunthaner and M.L. Naiman, Appl Phys. Lett., 4 (1984) 969 M.L. Naiman, C.T. Kirk, R.J. Aucoin, F.L. Terry and P.W. Wyatt, J. Electrochem. Soc, 131 (1984) 637 Y. Yoriume, Thin Sol Films, 115 (1984) 135 C.T. Chen, F.C. Tseng, C.Y. Chang and M.K. Lee, J. Electrochem. Soc, 131 (1984) 875 P. Pan and C. Paquette, Appl Phys. Lett., 47 (1985) 473 M.M Moslehi, C.J. Han, K.C. Saraswat, C.R. Helms and S.C. Shatas, J. Electrochem. Soc, 132 (1985) 2189 C.J. Han, M.M. Moslehi, C.R. Helms and K.C. Saraswat, Appl Phys. Lett., 46 (1985) 641

Silica, Silicon Nitride and Oxynitride Thin Films

[199] [200] [201] [202] [203] [204] [205] [206] [207] [208] [209] [210] [211] [212] [213] [214] [215] [216] [217] [218] [219] [220] [221] [222] [223] [224] [225] [226] [227] [228] [229] [230] [231] [232] [233] [234] [235] [236] [237]

141

A.K. Ray, C.J. Merz and T.N. Nguyen, Proceedings of the 3rd international Symposium on VLSI Science & Technology, (The Electrochem. Soc, (1985), 85-5, p. 339 F.L. Terry, Jr, P.W. Wyatt, M.L. Naiman, B.P. Mathur, C.T. Kirk and S.D. Senturia, J. Appl Phys., 57 (1985) 2036 R.P. Vasquez, A. Madhukar, F.J. Grunthaner and M.L. Naiman, Appl, Phys, Lett,, 44 (1985) 361 V.M. Efimov, D.G. Esaev, E.E. Meerson, L.M. Logvinskii and G.N. Perov, Phys. Stat. Sol. (a), 98 (1986)319 C.F. Chen and C.Y. Wu, Appl Phys. Lett., 48 (1986) 165 A.E.T. Kuiper, M.F.C. Willemsen, A.M.L. Theunissen, W.M. van de Wijgert, F.H.P.M. Habraken, R.H.G. Tijhaar, W.F. van der Weg and T. Chen, J. Appl. Phys., 59 (1986) 2765 D.J. DiMaria and J.R. Abemathey, J, Appl, Phys,, 60 (1986) 1727 P.Pan, /. Appl, Phys,, 61 (1987) 284 F.H.P.M. Habraken, E.L.J. Geerlings, R.H.G. Tijhaar, A. Slomp and W.F. van der Weg, J, Appl, Phys,, 62 (1987) 2573 H.H. Tsai, L.C. Wu, C.Y. Wu, and C. Hu, IEEE Electron Dev. Lett,, 8 (1987) 143 M. Severi and M. Impronta, Appl, Phys, Lett,, 51 (1987) 1702 R. Koba and R.E. Tressler, J, Electrochem, Soc, 135 (1988) 144 G.J. Dunn, Appl, Phys, Lett,, 53 (1988) 1650 K. Ramesh, A.N. Chandorkar and J. Vasi J. Appl, Phys,, 65 (1989) 3958 H. Wong and Y.C. Cheng, J. Appl. Phys., 70 (1991) 1078 LA. Chaiyasena, P.M. Lenahan and G.J. Dunn, Appl. Phys. Lett., 58 (1991) 2141 A. Ronda, A. Glachant, C. Plossu and B. Balland, C.R. EMRS XIIIMeeting - Strasbourg (1986), publ. Les Editions de Physique, p. 239 A. Ronda, A. Glachant, C. Plossu and B. Balland, Appl. Phys. Lett., 50 (1987) 171 B. Balland, J.C. Dupuy, A. Glachant and A. Ronda, Phys. Stat. Sol. (a), 100 (1987) 187 A. Benamar, J.C. Bureau, B. Balland, A. Ronda and A. Glachant, Appl. Surf. ScL, 30 (1987) 216 A. Glachant, B. Balland, A. Ronda, J.C. Bureau and C. Plossu, Surf, Sci„ 205 (1988) 287 A. Glachant, B. Balland, A. Ronda, J.C. Bureau and C. Plossu, Le Journal de Physique, 49 (1988) 413 B. Balland, J.C. Bureau, A. Benamar, J.J. Dubray and A. Glachant, Appl, Surf, ScL, 39 (1989) 210 A. Glachant, J.J. Dubray, B. Balland, A. Benamar and J.C. Bureau, Annales de Phys,, C2 6-14 (1989) 85 B. Balland, A. Glachant, J.C. Bureau and C. Plossu, Thin Sol. Films, 190 (1990) 103 J.C. Bureau, A. Glachant and B. Balland, Phys. Stat. Sol. (a) 120 (1990) 507 V. Garcia, A. Glachant, J.C. Bureau, B. Balland, C. Plossu, J.C. Dupuy and A. Straboni, Microelectronic Engineering, 22 (1993) 73 A. Glachant, V. Garcia, B. Balland, J.C. Bureau, C. Plossu, J.C. Dupuy and A. Straboni, Thin Sol. F//m5, 238(1994)31 V. Garcia, A. Glachant, R. Pantel and A. Straboni, Appl, Surf. Sci., 74 (1994) 165 L Kato, T. Ito, T. Nakamura and H. Ishikawa, J. Electron. Mater., 13 (1984) 913 P. Fazan, M. Dutoit and M. Ilegems, Appl. Surf. ScL, 30 (1987) 224 M. El-Sayed and J. Camargo Da Costa, Appl Surf. ScL, 30 (1987) 229 P. Debenest, K. Barla, A. Straboni and B. Vuillermoz, Appl Surf, ScL, 36 (1989) 196 K. Barla, D. Nicolas, R. Pantel, B. Vuillermoz, A. Straboni and Y. Caratini, J, Appl Phys,, 68 (1990) 3635 A. Straboni, B. Vuillermoz and M. Berenguer, Le Vide - Les Couches Minces, n° 255 (1991) 55 P. Pan, J, Appl Phys., 61 (1984) 284 S.S. Wong, C.G. Sodini, T.W. Ekstedt, H.R. Grinolds, K.H. Jackson and S.H. Ewan, J, Electrochem, 5^^130(1983)1139 F.L. Terry, M.L. Naiman and R.J. Aucoin, IEEE Trans, on Nucl ScL, NS. 28 (1981) 4389 Y. Okada, P.J. Tobin, V. Lakhotia, W.A. Feil, S.A. Ajuria and R.L Hegde, Appl Phys, Lett., 63 (1993) 194

142

[238] [239] [240] [241] [242] [243] [244] [245a] [245b] [246] [247] [248] [249] [250] [251] [252a] [252b] [253] [254a] [254b] [255] [256] [257] [258] [259] [260] [261] [262] [263] [264] [265] [266a] [266b] [267] [268] [269] [270a] [270b] [271] [272] [273] [274]

JB. Balland and A , Glachant

R.K. Brow and C.G. Pantano, J. Amer, Ceram, Soc, 70 (1987) 9 F.H.P.M. Habraken and A.E.T. Kuiper, Thin Sol. Films, 193/194 (1990) 665 A. Ronda, Ph, D. Thesis - CRMC2 - University of Aix-Marseille II - Fr. (1987) B. Carriere and B. Lang, Surf. Sci., 64 (1977) 209 H. Fukuda, M. Yasuda and T. Iwabuchi, Electronics Lett., 28 (1992) 796 H. Fukuda, T. Arakawa and S. Ohno, IEEE Trans. Electron Dev., 39 (1992) 127 T.O. Sedgwick, Mat. Res. Soc. Symp. Proc, 92 (1987) 3 J. Nulman and J.P. Knisius, Appl Phys. Lett., 47 (1985) 148 J. Nulman and J.P. Krusius, P. Pente, Mat. Res. Soc. Symp. Proc, 52 (1985) 341 M.M. Moslehi, K.C. Saraswat and S.C. Shatas, Appl. Phys. Lett., 47 (1985) 1113 C.C.Chang, A. Kamgar and D. Kahng, IEEE Electron. Dev. Lett., 6 (1985) 476 Y. Naito, T. Hori, H. Iwasaki and H. Esaki, J. Vac. Sci. Technol, BS (1987) 633 H. Fukuda, T. Iwabuchi and S. Ohno, Sol. State Electron., 33 (1990) 123 F.H.P.M. Habraken, A.E.T. Kuiper, Y. Tamminga and J.B. Theeten, / Appl. Phys., 53 (1982) 6996 M.L. Naiman, C.T. Kirk, B.L. Emerson, J.B. Taitel and S.D. Senturia, J. Appl. Phys., 58 (1985) 779 J.B. Oude Elferink, U.A. van der Heide, W.M.A. Bik, F.H.P.M. Habraken and W.F. van der Weg, Appl. Surf. Sci., 30 (1987) 197 J.B. Oude Elferink, F.H.P.M. Habraken, W.F. van der Weg and A.E.T. Kuiper, Appl. Surf. Sci., 33/34 (1988) 765 T. Hori and H. Iwasaki, Proc. lEDM-International Electron Devices Meeting IEDM-87 (1987) 570 T. Hori, H. Iwasaki and H. Esaki, IEEE Trans. Electron Dev., 34 (1987) 2238 T. Hori, H. Iwasaki, Y. Yoshioka and M. Sato, Appl. Phys. Lett., 52 (1988) 736 T. Hori, H. Iwasaki, T. Ohmura, A. Samizo, M. Sato and Y. Yoshioka, J. Appl. Phys., 65 (1989) 629 H. Hwang, W. Ting, D.L. Kwong, J. Lee, L. Buhrow and R.A. Bowling, Appl. Phys. Lett, 55 (1989) 755 G.Q. Lo, W.C. Ting, D.K. Shih and D.L. Kwong, Appl. Phys. Lett, 56 (1990) 979 D.J. DiMaria and J.H. Stathis, J. Appl. Phys., 70 (1991) 1500 LA. Chaiyasena, P.M. Lenahan and G.J. Dunn, J. Appl. Phys., 72 (1992) 820 N. Novkovski, I. Aizenberg, E. Coin, E. Fullin and M. Dutoit, Appl. Phys. Lett., 54 (1989) 2408 N. Novkovski, M. Dutoit and J. Solo de Zaldivar, Appl. Phys. Lett., 56 (1990) 2120 A. Uchiyama, H. Fukuda, T. Hayashi, T. Iwabuchi and S. Ohno, lEDM Technical Digest International Electron Devices Meeting, IEDM-90 (1990) 425 H. Fukuda, T. Arakawa and S. Ohno, Jap. Appl. Phys., 29 (1990) L2333 H. Hwang, W. Ting, B. Maiti, D.L. Kwong and J. Lee, Appl. Phys. Lett., 57 (1990) 1010 H. Hwang, W. Ting, B. Maiti, D.L. Kwong and J. Lee, lEDM Technical Digest- international Electron Devices Meeting, lEDM 90 (1190) 421 W. Ting, H. Hwang, J. Lee and D.L. Kwong, Appl. Phys. Lett., SI (1990) 2808 W. Ting, H. Hwang, J. Lee and D.L. Kwong, J. Appl Phys. 70 (1991) 1072 H. Fukuda, M. Yasuda and S. Ohno, Electron. Lett., 27 (1991) 440 H. Hwang, W. Ting, D.L. Kwong and J. Lee, Materials Research Society Symposium Proceedings, 224(1991)379 T.Y. Chu, W. Ting and D.L. Kwong, Materials Research Society Symposium Proceedings, 224 (1991) 415 T.Y. Chu, W. Ting, J.H. Ahn, S. Lin and D.L. Kwong, J. Electrochem. Soc, 138 (1991) L13 T.Y. Chu, W. Ting, J.H. Ahn, S, Lin and D.L. Kwong, Appl. Phys. Lett., 59 (1991) 1412 M. Yasuda, H. Fukuda, T. Iwabuchi and S. Ohno, Jap. /. Appl. Phys., 30 (1991) 3597 H. Hwang, W. Ting, D.L. Kwong and J. Lee, Appl. Phys. Lett, 59 (1991) 1581 H. Fukuda, M. Yasuda, T. Iwabuchi and S. Ohno, Appl. Surf. Sci., 60/61 (1992) 359 A.E.T. Kuiper, H.G. Pomp, P.M. Asveld, W.A. Bik and F.H.P. Habraken, Appl. Phys. Lett, 61 (1992) 1031

Silica, Silicon Nitride and Oxynitride Thin Films [275] [276] [277] [278] [279] [280] [281] [282] [283] [284] [285a] [285b] [286] [287] [288] [289] [290] [291] [292] [293a] [293b] [294] [295] [296] [297] [298] [299] [300] [301] [302] [303] [304] [305] [306] [307] [308] [309] [310] [311] [312] [313] [314] [315]

143

H. Fukuda, lEICE Trans. Electron., E76-C (1993) 511 T. Arakawa, Y. Yamashita, H. Hoga, S. Noda and H. Fukuda, Appl. Phys. Lett, 63 (1993) 3364 H. Fukuda, A. Uchiyama, T. Kuramochi, T. Hayashi, T. Iwabuchi, T. Ono and T. Takayashiki, lEDM Technical Digest - International Electron Devices Meeting, IEDM-92 (1992) 465 T. Hayashi, Y. Kawazu, H. Fukuda and T. Iwabuchi, Electron. Lett., 29 (1993) 2178 H. Fukuda, T. Hayashi, A. Uchiyama and T. Iwabuchi, Electron. Lett., 29 (1993) 947 N.S. Saks, D.I. Maria, D.M. Feetwood and M.E. Twigg, lEDM Technical Digest - international Electron Devices Meeting, IEDM-94 (1994) 23 H.R. Soleimani, A. Philipossian, B. Doyle, IDEM Technical Digest-International Electron Devices Meeting, IEDM-92 (1992) 629 H. Hwarig, W. Ting, D.L. Kwong, and J. Lac, lEDM Technical Digest-International Electron Devices Meeting, IEDM-90 (1990) 629 Z.H. Liu, J.T. Kuck, H.J. Wann, P.K. Ko, C.Hu, and Y.C. Cheng, lEDM Technical DigestInternational Electron Devices Meeting, IEDM-92 (1992) 625 S. Dimitrijev, D. Sweatman, H.B. Harrison, Appl. Phys. Lett., (1993) 1539 P.J. Tobin., Technical Dig. Symp. VLSI Tech., (1993) 51 P.J. Tobin, U. Okada, S.A. Ajuria, V. Lakhotia, W.A. Fait, R.I. Hedge, J. Appl. Phys., 75 (1994) 1811 Y. Okada, P.J. Tobin, V. Lakhotia, S.A. Ajuria, R.I. Hegde, J.C. Lido, P.P. Rushbrook, L.J. Arras, Electrochem. Soc, 140 (1993) L87 Y. Okada, P.J. Tobin, P. Rushbrook, and W.A. Dopant, IEEE Trans. Elect. Dev., 41 (1994) 191 J.T. Young and P.M. Lcnahan, J. Non-Cryst. Solids, 164-166 (1994) 1069 G.W. Yoon, A.B. Joshi, G.Q. Lo and D.L. Kwong, IEEE Electron Dev. Lett., 13 (1992) 606 A.B. Joshi, G. W. Yoon, J Kim, G.Q.- Lo, D.L. Kwong, IEEE Trans. Electron Dev. 40 (1993) 1437 J.H. Han, S. Lin, J. Electrochem. Soc, 138 (1991) L39 L.K. Han, M. Bhat, D. Wristers, H.H. Wang, D.L. Kwong, Microelectronic Engineering, 28 (1995) 89 G.Q. Lo, A.B. Joshi, and D.L. Kwong, IEEE Trans. Electron Dev. Letts., 13 (1992) 111 G.Q. Lo, A.B. Joshi, and D.L. Kwong, IEEE Trans. Electron Dev., 40 (1993) 1565 P.Poveda and A. Glachant, Surf. Sci.., 323 (1995) 258 C. Ance, F. de Chelle, J.P. Ferraton, G. Leveque, P. OrdejOn and F. Yndurain, Appl. Phys. Lett., 60 (1992) 1399 Y. Ishikawa, I. Kobayashi and I. Nakamichi, Jpn. J. Appl. Phys., 31 (1992) L443 M.G. Collet, J. Electrochem. Soc, 116 (1969) 110 C.H.J, van der Brekel and P.J. Severin, J. Electrochem. Soc, 119 (1972) 372 A. Loffler-Peters, J. Miiller and T. Ebert, Appl. Surf. Sci., 54 (1992) 121 W. Streb and R. Hezel, J. Vac Sci. Technol, B 2 (1984) 626 A. Glachant, P. Soukiassian, S.T. Kim, S. Kapoor, A. Papageorgopoulos and Y. Baros, J. Appl. Phys., 70 (1991) 2387 A. Glachant, P. Soukiassian, P.S. Mangat, J.Peng and S.T. Kim, Appl. Surf. Sci., 56-58 (1991) 802 A. Glachant and P. Soukiassian, Appl. Surf. Sci., 65-66 (1993) 654 A. Glachant and P. Soukiassian, S.T. Kim, and Z. Hurych, Appl. Surf. Sci.., 65-66 (1993) 847 B.H. Chin and G. Erlich, Appl. Phys. Lett., 38 (1981) 253 M.L. Knotec and J.E. Houston, J. Vac Sci. Technol, 20 (1982) 544 A. Bosseboeuf and D. Bouchier, Surf. Sci., 162 (1985) 695 F. Bozso and Ph. Avouris, Phys. Rev. Lett., 57 (1986) 1185 F. Bozso and Ph. Avouris, Appl. Phys. Lett., 53 (1988) 1095 K. Hiranaka and T. Yamaguchi, /. Appl. Phys., 67 (1990) 1088 D. Schalch, A. Scharmann and R. Wolfrat, Thin Sol. Films, 124 (1985) 301 D. Schalch, A. Scharmann and R. Wolfrat, Phys. Stat. Sol. (a), 105 (1988) K81 H. Reinhardt, D. Schalch and A. Scharmann, Thin Sol. Films, 167 (1988) LI G.A. Niklasson, T.S. Eriksson and K. Brantervik, Appl. Phys. Lett., 54 (1989) 965 Y. Cros, J.C. Rostaing, J. Peisner, G. Leveque and C. Ance, J. Appl. Phys., 62 (1987) 4538

144 [316] [317] [318]

B, Balland and A, Glachant K. Hiranaka and T. Yamaguchi, Jap. J. Appl Phys., 29 (1990) 229 T. Kamada, T. Kitagawa, K. Setsune, K. Wasa and T. Izurni, Appl. Surface Science 33/34 (1988) 1094 F.H.P.M. Habraken Appl. Surface Science 30 (1987) 186

145

INSTABILITIES IN SILICON DEVICES Silicon Passivation and Related Instabilities G. Barbottin and A. Vapaille (Editors) © 1999 Elsevier Science B.V. Allrightsreserved.

CHAPTER 2

A REVIEW OF BURIED OXIDE STRUCTURES AND SOI TECHNOLOGIES byJ.-L.LERAYO)

Key items Silicon-On-Insulator (SOI) technologies Buried Oxide (BOX) structures Silicon-On-Sapphire (SOS) Zone Melt Recrystallisation (ZMR) Wafer bonding Bond and Etch-back (BESOI) process Separation by Implantation of Oxygen (SIMOX) process Radiation Hardening Smart devices Buried optics Micromachining Sensors

(I) CEA'DAM, Commissariat a VEnergie Atomique Direction des Recherches en Ile-de-France B.P. 12, 91680, BruyereS'Le-Chatel, France E-mail: [email protected]

146

7.L. Leray

Abstract of Chapter 2: A review of buried oxide structures and SOI technologies Various techniques have been tried to fabricate buried oxide (BOX) structures and Silicon-On-Insulator (SOI) devices. The advantages associated with such structures are many: an increased integration, a reduction in coupling effects, a better radiation hardness and low leakage currents. Most currently used techniques are reviewed in this chapter. To obtain a SOI structure, silicon can be deposited on an amorphous (or polycrystalline) insulator, or on a crystallized insulator. Although many insulator substrates have been tried, the best results have been obtained by epitaxial deposition of silicon on sapphire (A 120^. The obstacles which the CMOS/SOS process had to overcome to become a reliable process are reviewed along with other techniques which permit growing a layer of crystalline silicon on an amorphous substrate (the ZMR and ISE process). A buried oxide can also be manufactured by implanting oxygen ions at a given depth in a silicon wafer. The SIMOXprocess is based on this principle. Other techniques (the FIFOS, SOOZ, GAA and EFIC processes) make it possible to grow an oxide layer underneath the device one wants to isolate. It is also possible to obtain a buried oxide by bonding two wafers, one of which has been oxidized. The BESOI process enables not only to obtain silicon-on-silica structures but also to associate other semiconductor materials with an oxide. Whatever the method used, BOX structures have found applications not only in microelectronics but also in micro-optics, sensors and micro-machines. When BOX structures are irradiated, the presence of an additional oxide layer and of an additional siliconinsulator interface gives birth to new effects (charge build-up, creation of new interface and bulk traps). These effects must be taken into account when a SOI device is designed to operate in a radiation environment Technologies based on buried oxides have a promising future. Resume du chapitre 2 : Les structures a oxyde enterre et les technologies SOI Diverses techniques ont ^te explorees pour fabriquer des structures a oxyde enterre et des dispositifs en silicium-sur-isolant (SOI). Les avantages que procurent de telles structures sont nombreux : une integration plus poussee, une reduction des effets de couplage, une meilleure tenue aux radiations et de faibles courants defuite. Laplupart des techniques actuellement utiUsees sont passees en revue dans ce chapitre. Four obtenir une structure SOI, le silicium peut etre depose sur un isolant amorphe (ou polycristallin) ou sur un isolant cristallise. Bien que de nombreux substrats isolants aient et^ essayes, les meilleurs resultats ont ete obtenuspar croissance epitaxique du silicium sur le saphir (Al20^. Les obstacles que le precede CMOS/SOS a du surmonter pour devenir un precede fiable, sont passes en revue. De meme, sont presentees d'autres techniques qui permettent defaire croitre du silicium monocristallin sur un substrat amorphe (notamment les procedes ZMR et ISE). On peut egalement fabriquer un oxyde enterre en implantant des ions oxygene dans une tranche de silicium. Le precede SIMOX est base sur ce principe. D'autres techniques permettent defaire croitre une couche d'oxyde sous le dispositif que Ton veut isoler (les procedes FIFOS, SOOZ, GAA et EFIC). II est egalement possible d'obtenir une couche d'oxyde enterre en soudant deux tranches dont Tune est oxydee. Le precede BESOI permet ainsi non seulement d'obtenir des structures silicium-sur-silice mais aussi d'associer d'autres materiaux semiconducteurs a des oxydes. Quelle que soit la methode utilisee, les structures a oxyde enterre ont trouve des applications non seulement en micro-electronique mais egalement en micro-optique, dans les micromachines et pour fabriquer des capteurs. Quand des structures SOI sont irradiees, la presence d'une couche d'oxyde et d'un interface silicium-isolant supplementaires donne naissance a de nouveaux effets (accumulation de charge, generation de nouveaux pieges de volume et d'interface). Ces effets doivent etre pris en compte quand un dispositif SOI est appele a fonctionner dans un environnement radiatif Les technologies utilisant les oxydes enterres ont un avenir prometteur.

A Review of Buried Oxide Structures and SOI Technologies

147

Zusammenfassung zu Kapitel 2: Eine Ubersicht ilber vergrabene Oxidstrukturen und SOI-Technologien. Verschiedene Verfahren zur herstellung vergrabener oxide (buried oxide: BOX) und Silizium-auf-Isolator (Silicon-On-Insulator: SOI) sind entwickelt worden. Die mit solchen Strukturen verbundenen Vorteile sind manigfaltig: eine hOhere Integrationsdichte, geringere Ubersprechneigung, erhohte Strahlungshdrte und geringere Leckstrome. Die gegenwdrtig genutzten Varianten werden in diesem Kapitel dargestellt Um eine SOI-Struktur herzustellen, kann Silizium entweder aufeinen amorphen (oder polykristallinen) oder kristallinen Isolator aufgebracht werden. Obwohl eine grosse Anzahl von Isolatorsub straten untersucht wurde, sind die besten Resultate durch epitaktisches Aujwachsen von Silizium aufSaphir (Al20^ erzielt worden. Die Schwierigkeiten, die der CMOS/SOS-Prozess zu uberwinden hatte, um ein zuverldssiger Prozess zu werden, werden ebenso dargestellt wie andere Verfahren, die es gestatten, kristallines Silizium auf einem amorphen Substrat aufzuwachsen (ZMR- und EPIC- Verfahren). Vergrabene Oxide vorgegebener Tiefe konnen auch durch lonenimplantation in einem Silizium-Wafer erzeugt werden. Der SIMOX-Prozess basiert auf diesem Verfahren. Andere Verfahren (die FIPOS-, SOOZ-, GAA- und EPIC-Prozesse) machen es moglich, eine Oxidschicht unterhalb eines zu isolierenden Bauteils zu erzeugen. Es besteht ebenfalls die Moglichkeit, durch Verbindung zweier Wafer, von denen einer oxidiert ist, eine vergrabene Oxidschicht zu erhalten. Der BESOI-Prozess gestattet nicht nur, Silizium-auf OxidStrukturen zu erhalten, sondern auch solche anderer Halbleiter-Materialien auf einem Oxid. Welches Verfahren auch immer gewdhlt wird, BOX-Strukturen werden nicht nur in der Mikro-elektronik, sondern auch in der Mikrooptik, Sensoren and Mikromechanik eingesetzt. Bei Bestrahlung treten bei BOX-Strukturen aufgrund der zusdtzlichen Oxidschicht und der zusdtzlichen Phasengrenze neue Schddigungsmechanismen auf (Ladungsaufbau, Erzeugung neuer Phasengrenz- und Volumenzustdnde). Diese Effekte mtissen beim Einsatz von SOI-Bauelementen in strahlungsbelasteter Umgebung berucksichtigt werden. Die aufvergrabenen Oxiden basierenden Technologien haben eine vielversprechende Zukunft.

148

y.L. Leray

Chapter 2: A review of buried oxide structures and SOI technologies Table of contents List of symbols and abbreviations used 1. An introduction to SOI structures and buried oxides 2. A historical perspective 2.1. The early works 2.2. How the concepts evolved 3. The many advantages of SOI structures 3.1. Improvements in packing density and process simplifications 3.2. Advantages of device downscaling 3.2.1. Reduction of junction dimensions 3.2.2. The electric breakdown of silicon 3.2.3. Reliability of junctions 3.2.4. Doping fluctuations 3.2.5. Sensitivity to the ionizing particles of the natural environment 3.3. Improvements in hardness against radiation-induced transient effects 3.4. Improvements in high-temperature performance 3.5. Advantages of dielectric insulation in high-firequency devices 3.5.1. Minimizing cross-coupling between elements 3.5.2. Minimizing high-fi-emiency losses 3.5.3. Increase in the maximum operationalfi-equencyof transistors 4. SOI manufacturing: processe/s based on the deposition of silicon on insulator 4.1. Deposition of silicon on/an insulator substrate 4.1.1. Thin-Film Transistirs (TFT) 4.1.2. Epitaxial Lateral Overgrowth (ELO) 4.2. Deposition of crystalling silicon on a crystalline bulk insulator 4.2.1. Origins of the SOS; process and early achievements 4.2.2. Carrier mobility and properties of the silicon-sapphire interface 4.2.3. Bulk minority-carrier lifetime and surface recombination velocity in the silicon film 4.2.4. Morphology and elebtrical properties of deposited silicon 4.2.5. The aluminum autodoping problem 4.2.6. Major improvements contributed by the Solid-Phase Epitaxy methods 4.2.7. Conclusions for the SOS process 4.3. Dual epitaxial deposition 4.4. Deposition of amorphous or polycrystalline silicon followed by recrystallization 4.4.1. The Zone Melting Recrystallization (ZMR) process 4.4.2. The Isolated Silicon Epitaxy (ISE) technique 4.4.3. Examples of other ZMR applications

A Review of Buried Oxide Structures and SOI Technologies SOI manufacturing: processes based on oxygen implantation 5.1. The high-fluence SIMOX process 5.1.1. Early developments 5.1.2. Oxygen and damage profiles 5.1.3. The Ultra-High Temperature Annealing (UHTA) step 5.1.4. Standard temperature conditions used during implantation to obtain a monocrystalline silicon layer 5.1.5. Standard dose conditions used to obtain a thick SIMOX buried oxide 5.1.6. Standard conditions used to obtain a thin SIMOX oxide 5.1.7. The InTernal OXidation (ITOX) process 5.1.8. Adjustments by supplemental implantation 5.1.9. Multiple implantation 5.1.10. Other insulators obtained by ion implantation 5.2. Major defects encountered in SIMOX structures 5.2.1. Fixed charge and interface traps 5.2.2. Silicon islands in the buried oxide 5.2.3. "Pipes" and nano-clusters in the buried oxide 5.2.4. Leakage currents induced by defects in SIMOX structures 5.2.5. Defects in silicon 5.3. Quality and variety of SIMOX substrates 5.3.1. First-order progress 5.3.2. Currently available processes Processes based on directed thermal oxidation (FIPOS, SOOZ and GAA methods) 6.1. The FIFOS process 6.1.1. Selective anodization 6.1.2. Selective oxidation 6.1.3. Densification 6.1.4. Obtained results 6.1.5. Peculiarities of FIFO S oxides 6.1.6. The advantages of using n-doped substrates 6.2. The SOZ and SOOZ processes 6.3. The Gate All Around process 6.4. The EPIC epitaxial and chemical thinning process SOI manufacturing processes based on the bonding of two materials (BESOI) 7.1. Principles of the BESOI techniques 7.2. Wafer bonding 7.3. Thinning of the top layer 7.4. The hydrogen cleavage process (Smart-Cut®) 7.5. Defects and properties of BESOI materials 7.6. Characteristics of current BESOI wafers 7.7. Other bonded materials (SICOI) 7.8. Novel structures permitted by wafer bonding

149

150

y.L. Leray

8. Applications of SOI structures to novel smart structures 8.1. Application to buried optics 8.2. Application to micromachines 9. Radiation effects in buried oxide structures 9.1. Charge trapping in dielectrics after ionization 9.2. Parasitic transistors due to charge trapping 9.2.1. Case of SOI structures 9.2.2. Case of SOS structures 9.3. Specific radiation effects in SOS structures 9.4. Specific radiation effects in SIMOX, BESOI and FIFOS structures 9.5. Additional comments on radiation effects in SOI materials 9.5.1. SIMOX buried oxides 9.5.2. BESOI buried thermal oxides 10. Conclusion 10.1. The fast evolution of BOX technologies 10.2. Perspectives Acknowledgements List of References

A Review of Buried Oxide Structures and SOI Technologies

List of symbols and abbreviations used Cox

F.cin-2

imax

NA

s-l s-l cm cm-3

ND,5ND

cm-3

Concentration of donor-type doping atoms, variation thereof

Qe

C.cm-2

Charge stored under the gate (of a MOS transistor)

Qsi

C.cm-2

Space charge of the silicon film of thickness tg^ when the film

ft L

Oxide capacitance per unit area Maximum (operational) frequency Transition frequency Transistor channel length (distance between source and drain) Concentration of acceptor-type doping atoms

is fully depleted q Mep

C cm

Elementary charge (q = 1.6 10"!^ C)

W

cm

Thickness of the oxide film

tsi

cm

Thickness of the silicon film

VT, 6VT

V

Threshold voltage, variation thereof

W

Transistor width

esi,Sox

cm F.cm'

Permittivity of silicon, resp. of silica

(|)F, 5<j)F

eV

Fermi energy, variation thereof

<|)MS

eV cm^

Metal-Silicon work function difference

CT

3D BESOI BOX C CMOS CVD DI DRAM ELO EPIC FET FIFOS GR GAA

Thickness of the depleted zone

Trap capture cross section Three-Dimensional Bond and Etch-back SOI Buried OXide (structure) Carbon. Stands here for technology using diamond Complementary Metal Oxide Semiconductor Chemical Vapor Deposition Dielectric Isolation Dynamic Random Access Memory Epitaxial Layer Overgrowth Epitaxial Process for Insulated Circuits Field Effect Transistor Full Isolation by oxidation of POrous Silicon Generation-Recombination Gate All Around

151

152 HEMT HTA IC ISE ITOX MBE PD PSG RMS SCR SEU SICOI SIMNI SIMOX SOD SOI SOS SOZ SRAM TFT UHTA VLSI ULSI

vuv XTEM YSZ Yttria Zirconia ZMR

J.L. Leray High Electron Mobility Transistor High Temperature Annealing Integrated Circuit Isolated Silicon Epitaxy InTemal OXidation Molecular Beam Epitaxy Partially Depleted Phosphorous Silicate Glass Root Mean Square Silicon Controlled Rectifier (or Thyristor) Single Event Upset Silicon Carbide On Insulator Separation by IMplantation of Nitrogen Separation by IMplantation of OXygen Silicon On Diamond Silicon On Insulator Silicon On Sapphire Silicon on Zirconium Oxide Static Random Access Memory Thin-Film Transistor Ultra-High-Temperature Annealing Very Large Scale Integration Ultra Large Scale Integration Vacuum Ultra-Violet High-Contrast Transmission Electron Microscopy Yttria-Stabilized Zirconia Y2O3 Zr02 Zone-Melting Recrystallization

A Review of Buried Oxide Structures and SOI Technologies

153

1. AN INTRODUCTION TO SOI STRUCTURES AND BURIED OXIDES To design and fabricate high performance integrated devices, one fruitful solution is to isolate electrically the semiconductor layer, in which the active elements are made, from the substrate. This can be accomplished: • either by depositing the "active layer" on an isolating substrate, • or, by somehow introducing a dielectric layer between the active layer and the substrate. A lot of effort has been devoted in the past twenty years to produce such structures for which two acronyms are currently being used: SOI: which can be understood as "Silicon On Insulator" or "Semiconductor On Insulator" and which usually refers to (SOI) devices. BOX: which stands for "Buried OXide" and which usually refers to the (BOX) structure itself This chapter reviews the many techniques used to fabricate BOX structures and SOI devices and their physical and electrical characteristics. In Section 2 we recall that in the early days of field-effect transistors, one already used a buried oxide structure and we show how the concept evolved over the years. When a SOI technology is used to manufacture analog and digital circuits, these circuits display several advantages, namely: an improvement in packing density, an improvement in radiation hardness, and the possibility of operating at higher temperatures, (the last two improvements being partly due to smaller leakage currents). These advantages are reviewed in Section 3. The isolation of individual (elementary) devices on a chip, using insulating layers (instead of pn junctions), makes it also possible to reduce cross-coupling effects and dielectric losses. We also show in this section that BOX structures are well suited to increase integration and reduce dimensions because of the sharp discontinuity the Si/Si02 interface provides. Problems usually encountered when dimensions are reduced (e.g. increase in electric field, electromigration, sensitivity to ionizing particles, ...) are more easily solved using a BOX structure than using bulk substrates. In Section 4, we review SOI processes based on the deposition of silicon on an insulator substrate, the latter being amorphous or crystallized. When the substrate is amorphous, the deposited silicon film remains amorphous or polycrystalline (case of thin-film transistors) unless crystallization seeds are introduced (the ELO process). The use of a crystallized insulator substrate such as sapphire has given birth to the Silicon On Sapphire (SOS) process in which silicon is deposited and grows epitaxially. We review the many problems which had to be overcome to make the CMOS/SOS process a commercially successful one, namely: an improvement of the Si/Sapphire interface, an improvement of the crystalline quality of the deposited silicon layer (using e.g. Solid Phase Epitaxy methods) and a reduction in aluminum contamination.

154

J,L,Leray

Other techniques used to produce a crystallized silicon layer are also reviewed: the dual epitaxial deposition, the Zone Melting Recrystallization (ZMR) process, and the Isolated Silicon Epitaxy (ISE) technique. Some of these techniques have made it possible to build several active layers on the same wafer. A buried oxide can also be manufactured by somehow introducing oxygen undemeath the silicon surface. In the SIMOX process (separation by Implantation of Oxygen), oxyden is introduced by implantation and the crystalline structure of silicon is restored by a suitable ultra-high temperature anneal. We review the currently available SIMOX processes in Section 5 and show that both thin and thick silicon layers can be obtained, depending on the implantation conditions (energy, fluence, multiple implants) and on the subsequent annealing conditions (temperature, annealing ambients). We also review the various process-induced defects (pipes, nanoclusters, silicon islands, fixed interface charge, interface states) and show that SIMOX structures have greatly improved due to a drastic reduction in contaminants during oxygen implantation. Another way of fabricating a silicon layer on an insulator is to somehow manage a local thermal oxidation of the silicon substrate undemeath the device to be isolated. We review four such processes in Section 6. In the FIFOS process (Full Isolation by Oxidation of Porous Silicon), the silicon substrate is oxidized through microchannels or pipes previously manufactured by means of anodic etching in HF acid. In the SOOZ process (Silicon Oxidation On Zirconia), one takes advantage of the fact that oxygen ions diffuse across zirconia. In the GAA (Gate All Around) process, one starts first from a SIMOX substrate and the buried oxide is etched undemeath a silicon island, which in a later step is reoxidized to obtain a thin gate oxide. Finally, in the EPIC process (Epitaxial Process for Insulated Circuits) the active devices are manufactured inside "tubs" of silicon dioxide. Another way of producing a buried oxide structure is described in Section 7. It consists in forcing an oxidized wafer to bond with an unoxidized wafer and subsequently to thin one of the two bonded wafers to obtain the desired thickness of active semiconductor material. The BESOI process (Bond and Etch-back Silicon-On-Insulator) is currently widely used to produce Silicon-Oxide-Silicon structures but can also be applied to manufacture new structures in which the active semiconductor can be SiC, GaAs, and InP. The thinning of the active silicon layer can be greatly simplified by using the Smart-Cut® technique in which hydrogen ions are implanted at a given depth to facilitate wafer splitting. Wafer bonding is also shown to render possible the 3D integration of active layers. The advantages brought about by SOI structures have made possible the design of novel structures. In Section 8, we show that the buried oxide may be used as a waveguide, which should enable the design of silicon-based opto-electronic devices. The SOI structure is also shown to offer many advantages in the fast-expanding field of micromachining and should give birth to new "smart" devices such as sensors and micro-actuators. Radiation effects in buried-oxide structures are reviewed in Section 9. Ionizing radiation generates electron-hole pairs in buried oxides just like in any other insulator. This gives birth to another parasitic structure called the back-gate FET transistor, and to leakage currents, due

A Review of Buried Oxide Structures and SOI Technologies

155

to the charge build-up in the buried oxide. Specific effects are also shown to exist in most CMOS/SOS structures due to the large build-up of states at the silicon-sapphire interface. Both electron and hole traps are generated during irradiation. Their main characteristics are shown to depend on the radiation used, and on the process conditions used during fabrication of the buried oxide, while their density is shown to depend on the biasing conditions during irradiation. Oxygen vacancies are thought to act as trap precursors, not only in SIMOX oxides but also in BESOI buried oxides. Carrier trapping occurs in the buried oxide during irradiation. Either electron or hole trapping prevails, depending on bias and dose. Buried oxide technologies have made tremendous progress in the last 40 years. This evolution and the benefits it brought are summarized in Section 10. These technologies provide new ways to further integrate electronic circuits and find new applications in the fastexpanding field of sensors and micromachines. 2. A HISTORICAL PERSPECTIVE Let us quickly review the evolution of BOX structures from a chronological point of view. 2.1. THE EARLY WORKS

The early works on BOX structures dealt with the fabrication of Field-Effect Transistors (FETs). Indeed, the most natural way to make a field-effect transistor is to use a semiconductor film on an insulator. These works began in the late 20's and dealt with what would nowadays be identified as Semiconductor-On-Insulator thin films [1, 2, 3]. The early patents filed by Lilienfeld and described in 1926 and 1928 (Fig. 2.1) showed how to control the value of a thin-film resistor (copper sulfide) through a spacer insulator (which at the time was proposed to be aluminum oxide). Heil [3] in the UK suggested in 1935 that the conductivity of a "thin gap" semiconductor could be modulated by an extemal field through mica (Fig. 2.2). March 7, 1933.

j . E. LILIENFELCT

1,900,018

Hl!li|lh;-|[

CeVICB fOR COriTROLLIKG ELECTRIC CURRENT F i l e d March 2 8 . 1928

3 Sbavts-Sbcii

I

Fig. 2.1 - The first Field-Effect Structure (US Patents claimed in 1926 and 1928). The proposed structure used a groove to recess the resistor film and make control easier [1, 2].

J.L. Leray

156

a) Fig. 2.2 - The original MIS patent: a thin film of semiconductor material is placed on or between insulators [3]. a) Single gate Metal-Insulator-Semiconductor Transistor b) Double gate Metal-InsulatorSemiconductor Transistor. (1), (2) contacts - (3) semiconductor gap - (6) plate electrodes - (8) upper and buried insulator.

Shockley rediscovered the structure (illustrated in Fig. 2.3 a) and finally demonstrated in 1948 the feasibility of such a field-effect device by using silicon and quartz (Fig. 2.3 b) [5]. He showed that the conductivity of evaporated layers of Ge (p-type), Si (n-type) or CU2O, with thicknesses ranging from 20 to 50 |Lim could indeed be modulated by a metal plate placed undemeath. An insulated plate of fused quartz (70-|Lim thick) was used both as a mechanical holder, as a substrate for deposition and as a gate insulator. The modulation of the conductivity was as "high" as 11% and the best results were obtained with CU2O and a 3 kV voltage. Gold electrodes

70 mn

7K

Deposited semi conductor

\

THIN LAYER OF / SEMICONDUCTOR

Fig. 2.3 - First evidence of a field-effect transistor using a MOS technology, a) Principle [4] b) Representation of the first manufactured prototype [5].

A Review of Buried Oxide Structures and SOI Technologies

157

2.2, H o w THE CONCEPTS EVOLVED

To be able to manufacture SOI devices, various solutions have been attempted, each solution featuring advantages and limitations: 1. One can deposit the Semiconductor (SC) material on an amorphous insulator. Devices thus produced have poor performances but can be used to command flat screens. 2. One can deposit the semiconductor material on a monocrystalline insulator. The difficulty of such a process has been to find a suitable insulator. The solution which has been the most successfiil one, from an industrial point of view, has been Silicon-On-Sapphire (SOS) which started in the 60's and had its heyday in the 80*s. 3. One can deposit the semiconductor material on an amorphous insulator (which is itself on top of a monocrystalline semiconductor) and then find a way to restore the crystalline structure of the top SC layer (e.g. using "seeds"). This concept gave birth to the Zone Melting Recrystallization (ZMR) process around 1975 and to the Isolated Silicon Epitaxy (ISE) technique around 1985. Because of the need to open "windows", the ZMR process has, however, many limitations. 4. One can implant oxygen atoms in a crystalline silicon substrate undemeath the surface and then, by annealing, create a buried oxide layer while restoring the crystalline structure of the top layer. This gave birth around 1980 to the widely successful Separation-by-Implantationof-OXygen (SIMOX) process. 5. Finally, one can bond two oxidized silicon wafers together (silica layer against silica layer) and thin one of the silicon wafers to the desired thickness: This gave birth, circa 1985, to the process called "Bond and Etch-back Silicon On Insulator" (BESOI). All these processes and their many variants have made it possible to manufacture products which feature many advantages (reviewed in Section 3) over their counterparts built on bulk silicon. Figure 2.4 illustrates how elementary devices manufactured on bulk material have been adapted to the SOI technology.

3. THE MANY ADVANTAGES OF SOI STRUCTURES When a SOI technology is used to manufacture analog and digital circuits, these circuits gain two unique advantages: an improvement in radiation hardness (i.e. a better resistance against radiation effects), and the possibility to operate at higher temperatures [6]. Moreover, the SOI technology enables an even higher degree of integration of the devices. Let us describe these advantages in some detail. 3.1. IMPROVEMENTS IN PACKING DENSITY AND PROCESS SIMPLIFICATIONS

The next figures illustrate how the distance between two neighboring transistors can be reduced in CMOS/SOI devices compared to bulk counterparts. This reduction comes first from the fact that anti-latch-up design rules are no more necessary. Second, well contacts, necessary in the bulk technology, can be optionally avoided in SOI devices. Third, a direct contact between the n^ and p"^ drain areas of neighboring n and p-MOS transistors can be obtained without having to define a metal shunt line and p" or n" wells vmdemeath the field oxide (Figs. 2.5 a and b).

158

J,L. Leray fGitel

FielcLOxide

p G ^

Gate I

WT] i

p

I

I I

Gate!

mr

PTT

p

N

rrr

0.05 to 1 |xm

N

'

0.05 to 2 Mm

Buried Oxide

Buried PN Junction

I

i

f

Silicon Bulk Substrate

Silicon Bulk Substrate I ••

CMOS/SOI

CMOS/Bulk

B

E



Gate

Gate|

TT N+

pTT N+ TP+

|B L _ ^

1 to 5 Mm P N+

C

I

N+

Silicon Bulk Substrate

N+ i

1

1

1

:

1

H .J

Bipolar/Bulk

N+

C

1 1 1

Buried Oxide

0.05 to 2 Hm

iJ

— Silicon Bulk Substrate

L

JFET/Bulk

Bipolar/SOI

JFET/SOI

Fig. 2.4 - Illustration of how elementary devices, manufactured with a conventional have been adapted to the SOI technology (right).

"bulk'* technology (left)

The SOI technology brings an improved flexibility in design (Fig. 2.5 c) since transistors can be made independent. Mixed designs which include CMOS transistors for logic and JFET, or bipolar transistors, for analog parts of the device [7] (and even both types: complementary types of JFETs and bipolars: C-JFET and C-Bipolar) are straightforwardly introduced [8]. SMART^'> architectures comprising high-voltage MOS transistors and diodes, and low-voltage logic (npn, pnp and CMOS along with signal photodiode), are also made easier by using dielectric isolation [9]. 3.2. ADVANTAGES OF DEVICE DOWNSCALING

Beyond the present state of the art, buried oxides will have to take into account the general trends of silicon technology. As lateral dimensions continue to shrink in VLSI circuits, vertical dimensions must also be reduced, thus requiring that the depth of the source and drain junctions be no deeper than 0.1 |Lim. Thanks to the Buried OXide (BOX) under-layer, thin SOI devices do not need such shallow junctions, and hence, do not pose such problems. This advantage and its consequences are described next.

(1) In SMART devices, additional circuits are introduced to process information, on technologies not originally suited for that purpose (e.g. smart sensors, smart power devices).

A Review of Buried Oxide Structures and SOI Technologies distance N' P

159

distance N* P*

a)

c)

Buried Oxide

Bulk S i l i c o n

Fig. 2.5 - Illustration of progress made in integration due to transposing bulk devices onto SOI substrates, a) CMOS/bulk. The anti-latch-up rules require a guard distance of 5-8 pim. b) On CMOS/SOI, the guard distance is reduced to 2.5 ixm in a 1.2 fim technology such as HSOI3 (circa 1990, [10]). c) On 0.8 fim SOI with trench isolation, such as in the DMILL technology, the guard distance can be further reduced [11].

3.2.1. Reduction of junction dimensions A shallow junction is difficult to manufacture, whereas the thickness of an insulating layer is very easy to control. Therefore, in SOL devices, transistors characteristics are more uniform and bi-dimensional effects, such as: (i) short channel effect affecting the threshold voltage, (ii) drain barrier lowering effects due the accumulation of carriers generated in the substrate close to the drain/substrate junctions, are easier to overcome. The evolution of Integrated Circuits (ICs) requires using ever lower supply voltages to reduce power consumption (from 10 V to 5, 3.3, 2.5, 1.8, 1.5 ...). Although the supply voltage of a device can be scaled down, two parameters hamper this reduction: the threshold voltage and the jimction capacitance. The threshold voltage cannot be reduced below a fraction of one volt, whereas junction capacitance increases when the reverse bias voltage drops (thus causing a loss in speed improvements). BOX isolation and very thin SOI layers render integration easier by: • offering the sharp potential barrier of the silicon/insulator band discontinuity, • yielding much smaller parasitic capacitances than their bulk counterparts (for equal oxide or junction depleted thicknesses), since the dielectric constant of Si02 is lower than that of Si.

160

J,L. Leray

Basic device parameters and speed are less sensitive to a reduction in supply voltage in the case of SOI devices than for similar bulk CMOS devices [12], [13, page 161]. 3.2.2. The electric breakdown of silicon In the current race to increase device integration, the dimensions are reduced even faster than the supply voltage. Therefore, the electric fields in the semiconductor increase. Electric breakdown or other phenomena associated with carrier multiplication in silicon must be avoided by carefully controlling the maximum value of the electric field and by properly designing the doping profiles. Some analyses [13] prove that very thin films on insulators are superior in this field-and-doping optimization, by exploiting the deep depletion mode, which is a unique feature of the SOI technology. An increase in the electric field displaces the distribution of electron and hole kinetic energies in the range of one electron-volt, thus increasing the ratio of electrons able to pass through the insulator barrier. Although some authors [14, 15] have reported^^^ that certain types of BOX layers do trap electrons injected from silicon, which could be a major drawback, hot electrons are not a specific reliability concem in the BOX technology, at least up to now [6, 16]. However, in the near future, for technologies with feature sizes of 0.2 micron and below, the energy of hot electrons will reach 1 to 1.5 eV [17, 18], thus increasing the probability that electrons be injected into the BOX and get trapped. This is another strong reason to measure and control the electron trap density in advanced SOI technologies. 3.2.3. Reliability of junctions As junctions become shallower, electromigration requirements become more stringent [19]. Indeed, any metal spike, or even a dislocation can short-circuit the junction as illustrated in Fig. 2.6 a. The use of a very thin silicon layer on an insulator minimizes the junction area since the junction becomes controlled by its peripheral surface rather than by its projected surface, as illustrated in Fig. 2.6 b. In this special case, electromigration may cause a metal pile-up reaching down to the underlaying insulator but consequences such as drain-channel short-circuit are avoided [20 a]. This makes very thin SOI devices extremely interesting. The maximum required thickness is of the order of 100 to 200 nm in this case. 3.2.4. Doping fluctuations Another serious problem encountered when reducing channel lengths down to 0.1 |Lim, or below, is due to fluctuations in the number of doping atoms located in the depleted zone below the channel [19]. Let us recall the equation relating the threshold voltage (Vj) to the substrate doping concentration (N/^) for a bulk NMOS transistor:

Vr- ^^^2^.^ ^ / 5 ^ ^

(2.1)

(2) The magnitude of the electric field in the substrate used for that particular experiment was 1 MV/cm, which far exceeds the magnitude of fields encountered in current BOX structures (< 100 kV/cm).

A Review of Buried Oxide Structures and SOI Technologies

161

where Oj^s is for the difference in electron work functions between gate and source. In transistors whose channel length is reduced to 0.1 |Lim, the volume of active silicon becomes of the order of lO'^^cm^. For a doping concentration N^ of S.lO^'^cm-^, the nimiber of doping atoms in the channel under the gate is as low as N j = 500. This number is small and any deviation from it causes fluctuations in the electrical characteristics from one transistor to another (with standard deviation a = yN^ = 22 and 3a = 66). Metal y Line ^ ^ ^ m LOCOS-^

Gate

r x _ W ^ ^ H , y^

brain \ Metal spite I Source and drain and dislocation^ I J""^('ons ^ short-circuiting, 1 Silicon substrate the drain junction Source

^^^^^Dislocation^^^^^^m Gate

Insulator pv-_W_ -, -_^^, - , 1/^

Source /

Source an^ drainjunctions I I

Drain' \ ' Metal spik and dislocations reaching the bimedl^er

b) a) Fig. 2.6 - Illustration of linear defects affecting junctions in a) bulk and b) SOI MOS transistors (after [13] and [20 a]). The threshold voltage fluctuation can be estimated by modifying (2.1) to introduce Q^gp the space charge encountered in the depleted zone of thickness tjep: Qdep VT = ^ms+'^F+ CoxWL

(2.2)

with W and L being the width and length of the transistor respectively. We can therefore write: q SNd SVf = 25F + Cox WL

(2.3)

If we neglect 5(|)p, since it only varies logarithmically with N^, we get, for SNj = ± 3 a = 66andW = L = 0.1 ^m: 5VT=+160mV

(2.4)

Therefore, the threshold voltage of the transistors could fluctuate substantially. In very large-scale integrated (VLSI) circuits containing 10^-10^ transistors, circuit failvires could arise due to leakage currents statistically likely to occur (some transistors may, statistically, be "on" when all others are "off).

J.L. Leray

162

P4

Fig. 2.7 - Illustration of a fully-depleted n-channel transistor with a p^-doped polysilicon gate (only possible with the SOI technology).

I N+ j N-! N+ \

The situation is very different when one considers a transistor, manufactured in the SOI technology, whose thin siUcon film is fully depleted (Fig. 2.7). The threshold voltage is then given by: ([20 b], or [21, p. 242, adapted]): VT =^msl+ 2^F+

Qsi

(2.5)

with Qsi^'^^AfSi Here, suffix 1 refers to thefi-ontgate device. Qsi is the space charge of the silicon film, of thickness tsi, when the film is completely depleted. Let us note that the factor 2 which appears in the denominator comes fi-om the fact that the image charge of the fiiUy depleted silicon layer is shared equally by the two symmetrical electrodes:fi-ontgate and back-gate. It must be noted also that the condition of complete depletion imposes 2 t^ep > tsiTherefore, an upper value for N^ is given by: \4s <.,<]>

^dep ~-

^'''^ > t,.' qN

or N^tsi'

< 10'cm-'

(2.6)

For tsi = 0.1 nm, it gives an upper admissible value of lO^^ cm-3 for NA- The number of doping atoms encountered in the film for a transistor of dimensions W = L = 0.1 ^im is only: Nd = N^.W.L.tsi = 100. Consequently, the statistical variation in the number of doping atoms isonly5Nd = ± 3 V N 7 = ±30. The correspondingfluctuationin V j is now: q SNd = ±36mV (2.7) 2Coxi WL In this unique type of SOI structure, threshold voltage fluctuations due to fluctuations in channel doping are therefore much less stringent than in bulk devices [22]. For this application, a silicon thickness of less than 100 nm is required and the method used to 5VT =

A Review of Buried Oxide Structures and SOI Technologies

163

fabricate the silicon film depends on the nature of the buried insulator. To date, the SIMOX process (see Sect. 5) is the only process that can provide such a structure with a good interface smoothness, although the BESOI process is making rapid progress. 3.2.5. Sensitivity to the ionizing particles of the natural environment Another source of instability in VLSI devices is the presence of high-energy particles in the natural radiation environment. At ground level, muons, neutrons, and pions resulting from the decay of cosmic rays, can pass through any device (as described in Chap. 12 of this volume). Alpha particles are also encountered. They are usually generated by the fission of the radioactive species contained in the ceramic package or in the device itself (especially in the metal layers).

vpjj

#r

L H^•W\

Fig, 2.8 - Track of an ionizing particle passing through the thin silicon film of a SOI transistor.

N+ \

Along their track, these particles generate electrons and holes in the active silicon layers as illustrated in Fig. 2.8. For the muons conmionly encountered at ground level (their flux is about one particle per cm^ per hour), a charge of 1 to 10 femtocoulomb is generated per micron of path length. This must be compared with the charge Qe stored under the gate of a transistor possessing the following characteristics: W.L = 0.01 [iim^, with V D S = 1 . 5 V; Vx = 0.5 V and a gate oxide thickness t^^ = 5 nm. This stored charge amounts to: Q, = C^^. W.L (VDS ' VT) = 0.067fC

(2.8)

which corresponds to 420 electrons. This rough evaluation shows that the stored charge will be altered when a device is struck by a particle of the natural environment, unless the "collection length" in the silicon substrate (defined in § 3.3 and Chap. 12) is reduced to somewhere between 50 and 100 nm. This is another advantage of using very thin SOI films for VLSI devices. 3.3. IMPROVEMENTS IN HARDNESS AGAINST RADIATION-INDUCED TRANSIENT EFFECTS

A good radiation hardness is historically the main advantage attributed to devices manufactured with SOI technologies. Radiation encountered in space consists mainly of cosmic rays, which are high-energy ions and protons, and of electrons trapped in the Van Allen belts (a simple description of the space radiation environment can be found in Chap. 8). Ground level radiation results from fusion or fission nuclear reactions (due to weapons or

164

7.L. Leray

nuclear reactors), and consists of gamma rays and neutrons. Any of these particles causes (directly or indirectly) ionization phenomena, which generate electron-hole pairs in and around the junctions. The generated carriers are swept away by the applied electric field, or by the doping gradients, and diffuse towards pn jimctions. As a result, the collected "photocurrents" can cause "upsets" in circuit nodes, as described at length in Chap. 12. These phenomena are called "transient" since they are related to the ionization rates, and their effects disappear when ionization ceases. Unlike what happens in silicon, ionization charges generated in insulating layers can be permanently trapped, and in this case, permanent effects survive the transient cause. This aspect is discussed in Chap. 11 and later on in this chapter in the case of buried oxides. The magnitude of these photocurrents is roughly proportional to the junction areas and to a lateral dimension called "collection length". The collection length consists of two parts: i) the depletion width of the junction and ii) the lateral diffusion length. As explained in Chap. 12, when a device is struck by an energetic particle, ionization and carrier drift and diffusion take place throughout the silicon layers, along the particle track. The nearest biased pn junction collects the carriers, generated along a distance called the "collection length". The harmful consequence of this diffusion is the creation of minority-carrier leakage currents, which can flow between neighboring transistors and temporarily connect them. In the early 60*s, Complementary Metal-Oxide-Semiconductor (CMOS) devices were already being reliably fabricated but subsequently the increase in transistor density caused interactions between transistors to increase also. Photocurrent paths may also cormect parasitic bipolar transistors of two types (npn and pnp) and cause the latch-up phenomenon. If the product of the transistor gains satisfies the condition p^pn Ppnp ^^^ ^^^r, a positive feedback loop is triggered and the device latches. The current flows then directly from the supply lines, and is only limited by the low series resistances of the conducting bipolar transistors. The creation of such a "latch-up" circuit is illustrated in Fig. 2.9. If the supply line is not quickly shut down, thermal runaway may destroy the device. The latch-up effect is mostly encountered when the radiation flux is delivered in short or very short pulses, e.g. fluxes of high-energy photons produced by nuclear weapons (pulses lasting from 10 ns to 10 ms), or when the device is struck by cosmic rays, a frequent occurrence in satellites (cosmic rays may strike asfrequentlyas once per second for a l-cm^ chip, while the cosmic rays transit in less than a picosecond). Such a Dirac-shaped excitation causes various electrical interferences (described in Chap. 12 of this volume). By using a SOI technology, most of the pn junctions used for isolation are replaced by a dielectric isolation and bulk leakage paths are automatically avoided. Moreover, the lateral etching of the silicon surroimding the transistors allows a full isolation (as illustrated in Fig. 2.5 c) and shuts off surface leakage paths, reducing the photocurrents by two to three orders of magnitude. Therefore, a substantial gain is obtained since transistors can be made simpler and closer to one another. Most important of all, any latch phenomenon between transistors is inherently avoided. This specific resistance to radiation is called radiation

A Review of Buried Oxide Structures and SOI Technologies

165

"hardness" and the action of improving a given structure or process is called "hardening". NMOS

Fig. 2.9 - Illustration of a parasitic Silicon" Controlled'Rectifier structure (SCR) in the set of transistors encountered in a CMOS structure.

The SOI technology also reduces the sensitivity of a device to particle fluxes. In a regular CMOS/bulk device, the collection length extends into the silicon substrate as represented in Fig. 2.10 a. In similar CMOS/SOI devices, the collection length is reduced to the thickness of the (thin) upper silicon layer, as illustrated in Fig. 2.10 b. The charge thus collected is much reduced and may be unable to cause any disturbance. Moreover, the active area surroimding the transistor is also much reduced in SOI devices, further reducing the charge collection due to carrier diffusion. Overall, compared with its CMOS/bulk counterpart, the CMOS/SOI technology makes it possible to decrease the sensitivity of a device to a given particle flux by several orders of magnitude, depending mostly on silicon thickness. A thorough analysis of this decrease can be found in Chap. 12. COSMIC RAY FLUX

Drain Junction Cross-Section

N-Well Cross-Section

^ N Transistor

f Transistor

rTFn

rm

a

s

N

ITT

Buried Oxid

I

f a)

\\ 7

\

\\"

\

\\

\

W

\

Silicon Bulk SJibstrate

\

b)

\ \

Generation of photocurrent at the crossing of each pn junction

Fig. 2.10 ' Illustration of the reduction in collection length when going from a conventional structure a) to a SOI structure b).

166

yx. Leray

3.4. IMPROVEMENTS IN HIGH-TEMPERATURE PERFORMANCE

Another advantage of full isolation and of a reduction in junction area is clearly found at high temperatures. Many pieces of equipment must function at elevated temperatures in such applications as: i) under-the-hood electronics and anti-lock braking systems in the automotive industry, ii) deep earth drilling for the petroleum industry and the monitoring of geothermal reservoirs iii) aircraft and spacecraft systems, which require functioning at 250°C. The area of the source-substrate and drain-substrate junction is much smaller in thin-film silicon devices than in bulk silicon MOSFETs. In addition, the total volume of silicon in SOI devices is also very small. These two factors explain why in SOI devices, the diffusion currents can be reduced by several orders of magnitude. It follows that the leakage current across the jimctions can also be reduced, especially at high temperature, as first pointed out in 1988 [23]. This was clearly demonstrated in 1989 [24] when a 16-kbit SRAM memory in SOI technology withstood temperatures of 300°C, with leakage currents 2 or 3 orders of magnitude lower than those of bulk CMOS counterparts. High-temperature testing was successfully performed up to 400°C [25] and even at 425°C with devices featuring an ultrathin silicon layer (23.5 nm) [26]. In these two cases, correct transfer characteristics were found up to 400°C and fully usable characteristics were found for circuits up to 250°C, whereas standard bulk devices usually fail above 150°C. Such experiments suggest that, when operating in the 300-400°C range, the limitations will not come from silicon but fi'om aluminum interconnections (the aluminum alloys currently used melt around 600°C and the interdiffusion of Ai into silicon takes place at a much lower temperature). Other metallizations such as tungsten will have to be used in the CMOS process. Thus, it is clearly advantageous to use mature and up-to-date SOI technologies in these temperature domains, instead of costly and not yet reliable SiC or C (diamond) technologies. 3.5. ADVANTAGES OF DIELECTMC INSULATION IN HIGH-FREQUENCY DEVICES

3.5.1. Minimizing cross-coupling between elements A reduction in cross-coupling obviously stems from the isolation of individual transistors by means of "dielectric isolation". It is obtained in any SOI technology, such as those represented in Figs. 2.5 b and 2.5 c. The isolation of transistors by using lateral and buried oxides has the advantage of not only preventing their cross-coupling by leakage currents, but also of reducing their cross-coupling by capacitances. For instance, when replacing a junction isolation by a buried or lateral silicon dioxide layer, the parasitic junction capacitances decrease first because of a favorable dielectric constant ratio (Sox/^si =3.9/11.9). This is especially true for source-substrate or drain-substrate junctions (n"^p or p^n). Due to the decrease in parasitic capacitance values, the operating speed of the ICs is expected to increase by a factor as large as 2, depending on transistor size and circuit layout.

A Review of Buried Oxide Structures and SOI Technologies

167

In the 80's, this enhancement factor ranged from 30% to 50% for transistors with 1 to 2-micron channel lengths ([27-29], [30, p. 196]). For 0.5 |am transistors, the speed has been found to increase by a factor of two, and this factor is expected to increase even more for deep submicrometer technology and lower power supplies (2.5, 1.5 Volts and below) [31]. Figure 2.11 depicts quantitatively the gain in isolation obtained by going from a bulk technology (illustrated in Fig. 2.5 a) to a trench-SOI technology (such as that illustrated in Fig. 2.5 c). It has been also observed that the suppression of the collector-substrate diode and its replacement by a dielectric layer decreases capacitance and improves operatingfrequency.For instance, the transition frequency of an npn transistor transferred into a dielectric isolation technology was found to increase from 0.5 to 3 GHz. This conversion improved also the noise figure by a factor of 10, since an important source of 1/f noise, i.e. the collector-substrate diode, disappeared (ACUTE technology [32]). 0 -20

1 CO

P+ & N-Well P+ & trench P+ (back tied to grd)

-40 -60

P+, SOI & trench (handle floating)

-80 -

110

P+, SOI & trench (handle grounded)

_ 120

140 I I I M i n i — I I I mill

10'

I I III

10'

10

F r e q u e n c y (Hz) Fig. 2.11 - Cross-talk versus frequency in typical structures (after [33], modified).

3.5.2. Minimizing high-frequency losses Another advantage of dielectric isolation is that it reduces losses in the microwave frequency domain. For microwave applications, surface inductors or transmission lines are needed. These elements are usually not manufactured in a silicon technology because of the dielectric losses that take place in the isolation junctions. These losses prevent the use of microwave circuits, made on silicon substrates, above a few hundred megahertz, as opposed to circuits on gallium arsenide substrates for which such losses do not exist. Using a SOI technology of the type illustrated in Fig. 2.5 b can be a way to overcome this difficulty. Figure 2.12 a illustrates the parasitic elements found in a simple spiral inductor consisting of a metal line deposited on an insulating layer, itself grown or deposited on a substrate.

168

7.L. Leray

The elementary cell includes a distributed inductance L, a coupling capacitance C (coupling with the substrate), and dissipation resistances Rg^b (substrate) and Rj^ (metal). At a given frequency, the quality factor Q is improved by maximizing R^ub or minimizing C^ubThis was first obtained in the 70's by using silicon-on-sapphire (SOS) technology (for which Rsub =00). Possible applications include low-cost cellular telephone networks [35]. 3.5.3. Increase in the maximum operational frequency of transistors An increase in the maximum operational frequency (fmax) ^^ MOS transistors has been obtained by using SOI technologies of the type described in Fig. 2.5 b. Gigahertz applications were first demonstrated, and in the late 80*s a 6.2 GHz prescaler divider, fabricated in SOI on silicon dioxide, exhibited a 50% improvement over its silicon counterpart [34]. In the 90's, MOS/SOI transistors demonstrated power gains of 9 dB at 10 GHz and made it possible to integrate the CMOS digital command of microwave transistors operating in the L and X band. This technique (called the MICROX process [36]) used a special high-resistivity silicon substrate (4.10"* Q.cm) obtained by multiple-refining float-zone (FZ) to minimize silicon losses. The possibility of manufacturing high-frequency MOS transistors in silicon has been thus demonstrated, e.g. through the samples made by Westinghouse with transition frequencies f^ of 14 GHz in 1991 and 23 GHz in 1993 ([37]). Using a smaller gate linewidth of 0.2 |im, frequency values of f^ = 51 GHz and f^^x ^ 28 GHz have been obtained with a drain voltage of 1.5 V, even with standard SIMOX wafers with a silicon resistivity of 20 Q.cm [38]. Using SOS with Solid Phase Epitaxy (see § 4.2.6), values of f^^^x "^ 50 GHz have been obtained for transistors with a gate length of 0.5 |im [39-41]. With a fiirther optimization of SOS or SOI processes, one can expect transition frequencies to reach 100 GHz, thus allowing significant power gains in the high-frequency bands currently used for domestic communications (1 to 20 GHz), with a minimum of power loss (thanks to the use of dielectric isolation).

L

Rm C^Cox+Csub

ir=Cox+Csub

—v\^

substrate

a)

ub

b)

Fig. 2.12 - Simple generic SOI microwave structure: a) surface inductor b) equivalent circuit.

A Review of Buried Oxide Structures and SOI Technologies

169

4. SOI MANUFACTURING: PROCESSES BASED ON THE DEPOSITION OF SILICON ON INSULATOR The simplest way to obtain a SOI structure is, at least in theory, to deposit a thin silicon film on an insulating layer. If the insulator is amorphous, the resulting silicon film will be either amorphous or polycrystalline, unless a recrystallization process can be somehow triggered. If the insulator is crystallized, the silicon film may grow epitaxially if conditions are right. We review next these various processes and their peculiarities. 4.1. DEPOSITION OF SILICON ON AN INSULATOR SUBSTRATE

This deposition process is the most straightforward way of manufacturing a SOI structure. Silicon can be deposited on top of a pre-existing insulator, as illustrated in Fig. 2.13. Indeed, Shockley and Pearson gave the first evidence of a field-effect modulation in the late 40's using this process [5], as mentioned in Sect. 2. amorphous or polycristalline silicon layer y^

Fig. 2.13 - Basic features of a Thin-FilmTransistor (TFT) manufactured by depositing silicon on an insulator layer.

4.1.1. Thin-Film Transistors (TFT) In the 60's, this deposition technique gave birth to the Thin-Film Transistor (TFT) technology [42]. In this structure, the gate electrode is first deposited on the substrate insulator (quartz or glass). The gate insulator (glass) and finally the active semiconductor (made up of hydrogenated amorphous silicon) are deposited. The structure is therefore the reverse of a normal transistor. The semiconductor is amorphous, giving mostly poor electrical performances but the technique enables the manufacturing of large areas at low-cost and is increasingly used for large arrays of transistors, e.g. for the growing market of flat panel displays [43-45]. .INSULATING SUBSTRATE

Fig. 2.14-Various forms of TFT manufactured around 1962 (after [45]).

S.C.

INS.

PERFORATED GATE

170

y.L. Leray 4.1.2. Epitaxial Lateral Overgrowth (ELO)

The ELO technique was developed in the 70's to overcome the poor electrical performances obtained with amorphous semiconductors and to enable the growth of a monocrystal over the insulator. In this epitaxial technique, silicon is deposited after patteming windows have been etched in the insulator. Epitaxial growth proceeds both vertically and laterally from the seeding windows. Seeds coming from the etched pits grow and meet to form continuous films [13, 46], as illustrated in Fig. 2.15. The technique is limited by the recrystallisation rates in the horizontal and vertical directions, which requires one to build films as thick as 10 |Lim to cover insulator films with seed window pattems as close as 20 |am.

Fig. 2.15 - Principle of Epitaxial Lateral Overgrowth (ELO). 4.2. DEPOSITION OF CRYSTALLINE SILICON ON A CRYSTALLINE BULK INSULATOR

To overcome the problems associated with deposition on glass, one can attempt to obtain an epitaxial growth on another crystal. The most straightforward technique would be to deposit silicon on a crystalline form of Si02. However, in a-quartz, a phase transition, which takes place at 573°C, causes changes in substrate dimensions. This phase transition thus induces considerable stresses in any siUcon film deposited on top of a-quartz, and consequently, high-temperature treatments are incompatible with good properties of the silicon layer. This precludes any MOS-compatible process. For this reason at least, silicon must be deposited on amorphous Si02, which, consequently yields polycrystalline or amorphous films. 4.2.1. Origins of the SOS process and early achievements In the early 60's, due to advances in the manufacturing of monocrystalline sapphire (A^203)' i^ slicing and polishing techniques and in surface preparation techniques (such as prefiring in hydrogen), crystalline Silicon-On-Sapphire structures were successfully produced at RCA Labs and reported in 1964 by Manasevits and Simpson [47]. In an altemative technique, spinel, a crystalline mixture of A.^203 ^ ^ M%0 was used as the insulator substrate. The first device produced on sapphire (1966) resulted from the works of Heiman and consisted of p- MOS transistors connected in arrays of 16 transistors [48].

A Review of Buried Oxide Structures and SOI Technologies

171

These two techniques were called Complementary MOS On Sapphire or Spinel (CMOS/SOS), and were sufficiently mature to allow the first commercial offer by a company called Inselek in 1971. A thorough review of accomplishments in the area of SOS materials and circuits can be found in [49]. The 70's saw the triumph of this heteroepitaxy technique [50]. Union Carbide and Kyocera became the main wafer suppliers, thereby manufacturing SOS substrates for radiation hardened circuits. Advanced applications took advantage of the low-capacitance, highvoltage, and simpler processes. Toshiba buih the first 16-bit microprocessor on a SOS substrate in 1977, along with the first 16-bit microprocessor on bulk silicon (SBP9900 in PL technology). At the same time, Hewlett Packard proposed SOS devices for pocket calculators. In Europe, works were undertaken on high-voltage applications and on low-power circuits to be used in wristwatches. The quality of the silicon layer and silicon/sapphire interface remained the main concern. Because of the commercial success of this process, numerous studies were carried out to assess and improve the quality of the silicon-sapphire interface. This characterization effort, as explained next, was applied mainly to four areas: -

electrical characterization of the interface, electrical characterization of the deposited Si layer, X-ray study of the interface morphology, study of the aluminum autodoping effect. 4.2.2. Carrier mobility and properties of the silicon-sapphire interface

Figure 2.16 a illustrates the specific "back-gate" structure which can be built with any device containing a buried oxide. For a bulky buried oxide, such as sapphire, kilovolts must

source

back gate G2 I a)

-200

'G2

b)

-100

0

TOO

200

back-gate voltage VQ2 (V)

Fig, 2.16- Electrical characterization of the silicon-sapphire interface using the back-gate biasing technique (after [51]). a) Description of the test structure b) Current-Voltage characteristics of a back NMOS transistor with W/L=100 jum/100 fim andx^^ — 80 jum using a drain voltage V^y^ of 100 mV.

172

y.L. Leray

be applied to the back gate in order to accumulate or invert the silicon-sapphire interface and thus be able to characterize it. This voltage can be reduced by locally thinning the sapphire (e.g. jfrom 300 |im to 70 or even 50 |im) before depositing the back (A-^) gate. By using this technique, some authors have deduced the field-effect mobility, by measuring the IDCVQ) characteristics firom the back-gate as illustrated in Fig. 2.16 b. Mobility values range from: ^e = 40 cm2 V ^ s"! [51], with a n+/p/n+ enhancement-type MOS, to 2 to 10 cm^ V^ s"! with a n"*"/n"/n'^ deep-depleted type relevant to another process. Er

Fig. 2.17 - Profile of the density of states at the silicon-sapphire interface (after [52]).

10

II

12

13 14

Density of interface states (lO^^.cm'^.eV"*)

B'^DOPED; 4 x 10®/cm^ SOS CAPACITORS O 960°C • 975^C

<

O QIO^'C

m 975«'C

3

2

5

1

«^

0

%^-

1

l-^r^\^vW\^ POSITIVE CHARGE | NEGATIVE CHARGE

--

O fM — 2

13

<

CC

o

3

I.

I..6

J

1

1.0 2.0 SILICON EPITAXIAL GROWTH RATE (p<m/IVllN}-

u

3.0

Fig. 2.18 - The density of the fixed interface charge at the silicon/sapphire interface, is plotted as a function of epitaxial growth conditions (after [54]).

A Review of Buried Oxide Structures and SOI Technologies

173

The interface state density appears high (>10l2 cm-2 eV-l) and rather symmetrical in the band-gap [52], except in the upper quarter of the band-gap where it peaks at 8 10^2 cm-^ eV-l, 255 meV below the conduction band as illustrated in Fig. 2.17. The fixed interface charge, as assessed by C-V measurements, is shown to strongly depend on process conditions, as illustrated in Fig. 2.18 [54]. A small process window exists which makes it possible to obtain an interface charge nearly nil. 4.2.3. Bulk minority-carrier lifetime and surface recombination velocity in the silicon film Minority-carrier lifetime measurements have been performed using lateral bipolar transistors and gated diodes on SOS structures [53, 55]. The authors have shown that the effective carrier lifetime x^ff is best expressed by the following expression: T^ff-1 = T^'^ + S2/b

(2.9)

where Xy is the average (bulk) minority-carrier lifetime, S2 is the surface recombination velocity at the Si/A^203 i^^terface and b is the distance to the interface. Parameters Xy and S2 have been found experimentally to be best fitted with the values given in Tab. 2.1. S2

Device used and reference

10 ns

1.8 104cm/s

magnetodiode [56], [57]

50 ns

10^ cm/s

gated diode [58]

100 ns

10^ cm/s

gated diode [55]

^v

Table 2.1 - Electrical recombination parameters of standard silicon-on-sapphire structures.

4.2.4. Morphology and electrical properties of deposited silicon Figure 2.19 shows a TEM cross section of a silicon layer deposited on sapphire. It confirms the existence of an increasing disorder as we get closer to the interface. This is mostly due to the intemal stresses induced by the epitaxial process that takes place between 900 and 1000°C, and by the cooling-down step.

Fig. 2.19 - TEM cross section of a siliconon-sapphire structure showing the morphology of the silicon layer (CEA-LETI, circa 1972).

174

J,L, Leray

Since the average linear expansion coefficient of A£203 is twice that of Si (9.1 vs. 4.5 10-6 °C-1), shear stresses are generated that cannot be relaxed by viscous flow, unlike what happens in amorphous thermal Si02 abundantly used in other parts of the structures [53, 59]. Consequently, residual stresses are of the order of lO^-lQl^dynes.cm-^ [60a]. The disorder encountered in the silicon layer has been confirmed by plotting the number of faults per cm, measured by decoration, as a function of distance away from the interface (Fig. 2.20 a). Likewise, in Fig. 2.20 b, minority carrier lifetime, measured in an n-type silicon film deposited on sapphire, using a gradual etching, has been plotted as a function of distance [60b, 60c]. Both curves confirm that disorder decreases as we move away from the interface. Due to these interface defects, SOS devices can display large excess noise, especially if the deserted zone below the MOS device extends and includes the volume near the interface. The noise spectral density at 1 kHz can be two orders of magnitude larger for MOS/SOS transistor than for MOS/bulk-silicon ones [61, 62]. The spectral analysis of the GenerationRecombination (GR) noise shows the existence of several GR centers [53].

S

1

10'

a)

10''

10"

Distance from interface (A)

10"

b)

Distance from Si surface (^im)

Fig. 2.20 - Comparison of material and electrical characterizations of silicon-on-sapphire structures: a) The number offaults/cm in silicon is plotted as a function of distance from the silicon-sapphire interface (after [60 b]). b) The minority carrier lifetime in an n-type silicon film on sapphire has been measured as a function of distance by gradual etching (after [60 cj).

4.2.5. The aluminum autodoping problem Another detrimental effect, characteristic of SOS substrates, is the aluminum autodoping phenomenon, which is closely associated with the epitaxial process. Early epitaxial deposition processes, which used the cracking of silicon tetrachloride (SiC^4) or trichlorosilane (SiHC>^3) produced heavily p-doped silicon layers.

A Review of Buried Oxide Structures and SOI Technologies

175

The process presently used begins by annealing a well-polished (1102) crystalline sapphire wafer in hydrogen at 1000°C or above (pre-firing step). Epitaxial growth takes place by cracking silane (SiH4) in hydrogen at temperatures ranging from 900°C to 1100°C [54, 60a]. Doping gases, either arsine (ASH3) or phosphine (PH3), or diborane (B2H5) are classically added into the gas stream to obtain the required doping and type. The cracking of silane is symbolized by: SiH4^Si

+ 2H2 f

At the cracking temperature, MjOi, does not react with Si, but reacts with IA2, which produces AiO according to the following reactions: A/2O3 + 2H2 <^A/20 T+ 2 H2O f A/203+H2<^2A£0

f+H20

f

At higher temperature, SiO can be produced following: 2 Si + A/2OS ^2

SiO T+A/2O

f

These reactions lead to a partial etching of the alumina and silicon films. The presence of all these aluminum-rich gases in layers near the interface leads to the incorporation of Al in the form of oxygenated complexes with silicon. Repace and Goodman also suggested that a reaction of reduction of aluminum takes place: A/20 + H2<^2A/+H20

f

which leads directly to the incorporation of aluminum in the silicon network. Silicate A^SiO"^ and Ai2^ signals have indeed been observed by SIMS in a 500-A-thick transition layer [60 a]. SIH4

Fig. 2.21' Illustration of the reactions taking place during the epitaxial growth of silicon-on-sapphire [60 a].

Concentrations of aluminimi contaminants as high as 10^^ cm^^ have been reported, without apparently affecting the functioning of MOS devices. However, under some circimistances, e.g. if the temperature of epitaxial growth or of another step during the MOS process exceeds lOOO^C, aluminum exodiffuses deeper into the silicon layer and reacts with silicon. This can lead to a p-type autodoping by activation of aluminum as ionized species.

176

J,L,

Leray

This exodiffusion phenomenon is particularly harmful, since aluminum is a known contaminant in microelectronics laboratories and fabrication units. This explains why SOS process lines are usually isolated from other silicon manufacturing lines. 4.2.6. Major improvements contributed by the Solid-Phase Epitaxy methods In this method, created by Golecki, an elaborate process takes place after the epitaxial growth of silicon [46]. Let us first describe the SPE (Solid-Phase Epitaxy) illustrated in the left column of Fig. 2.22. First, a deep silicon implant renders amorphous the lower part of the silicon film above the A^203/Si02 interface. Then, a fiimace annealing at 550-600°C restores crystallinity to this damaged area. Crystal regrowth proceeds fi-om the upper part of the film (used as a seed) down (Solid-Phase Epitaxy). As a consequence, the quality is much improved in the active upper part of the film. Sometimes, an additional 900-1000°C anneal is performed [66 a]. A second (shallow) silicon implant is performed and regrowth takes place in the Double Solid-Phase Epitaxy process. In this case (right column), the upper part is amorphized and regrowth proceedsfi*omthe bottom to the top. At the expense of complex processes, these methods have given excellent films that have been thinned by thermal oxidation down to 500 A. Transistors have been made in the early 80's with gate lengths of 0.5 ^m and excellent high-fi'equency characteristics. AlaOs

Si X X X X X X X X X

AlaOs

Si •tarting film

depoilted

twins •t. faulU

^

•

SI implant (mmorphiz.)

solid phase' epitaxial regrowth (550' C)

I

Fig. 2.22 - Illustration of the Single Solid Phase Epitaxy (left) and of the Double Solid Phase Epitaxy methods (right) (after [63]).

regrowth complete SPE-SOS

DSPE-SOS

In the late 90's, a new process named UTSi^ was marketed by the Peregrine Corporation [41]. This technology is based on an efficient method of sapphire crystal growth named Ribbon Growth followed by the Single Solid Phase Epitaxy regrowth process described above. Excellent HF characteristics are obtained and the possibility of designing inductors and antennas directly on wafers without substrate losses makes it appealing for millimeter-wave applications [40].

A Review of Buried Oxide Structures and SOI Technologies 4.2.7. Conclusions for the SOS process The conclusions of the many observations made in the 70's and 80's in laboratories and at the manufacturers' [50], are as follows: • A transition layer, from 100 to 150-A thick, seems to exist at the Si/A^203 interface. It is responsible for the generation of large electrical noise and for some components of the leakage current in MOS diodes and transistors. • The non-uniformity of the deposited silicon film, associated with an increased density of defects near the Si/A^203 interface results in a catastrophic degradation of carrier mobility and minority carrier lifetime. • Mechanical stresses exist at the film/substrate interface [53, 60 a]. • Under some circumstances, aluminum exodiffuses into the silicon layer, which can lead to the phenomenon of p-type autodoping. The quality of the Si/A^203 interface has therefore been the major concem of SOS technologies, although specific treatments have been introduced to improve the quality of wafers, such as: • The prefiring of sapphire in H2 before epitaxial deposition. • The optimization of the growth rate. • The amorphization of the silicon layer by silicon implantation followed by recrystallization by electron beam or laser [64]. These techniques, developed in the 80's, have produced high-quality wafers and 6-inch wafers have been available in the 90's. SOS techniques might gain new interest due to the advantages which full dielectric substrates bring for very high-frequency applications. 4.3. DUAL EPITAXIAL DEPOSITION

Another method used to manufacture a SOI structure is to first deposit epitaxially the insulator layer on a "mechanical" monocrystalline silicon substrate, and then in a second step, to deposit epitaxially the active silicon layer. In a review performed in the 80's, Golecki mentions the following insulating materials on which silicon films have been epitaxially grown [46]: BeO (1966), a-Si02 (quartz), a-SiC (1963), CaF2 (1963), and Yttria-Stabilized Zirconia (YSZ) or (Y203)in-(Zr02)i.in with m = 0.3, the so-called Silicon-On-Zirconia (SOZ) [65]. Several other attempts have also been reported, such as: silicon on chrysoberyl (BeOA^203) [66 b], Th02, ZrSi04, LaA£03 [46], NaC>^ [67]. Early attempts to deposit monocrystalline silicon on CaF2 tried to take full advantage of the small mismatch existing between the two cubic crystals. Interest in this technique has recently been renewed with the intent to match III-V and II-VI devices with a silicon technology and to build stacked silicon devices [68].

177

178

/.L. Leray

The epitaxial deposition of a semiconductor (or a metal) on an insulator was found to be much more difficult to accomplish than the epitaxial deposition of a dielectric on a semiconductor. This is attributed to the large difference in surface energies which prevents a smooth layer-by-layer growth. For instance in the case of Si(lll) deposited on CaF2, it has been shown that the Fermi level is pinned at the silicon valence-band maximum [68] and that the interface charge density is as high as 10^^ cm'^. This has been attributed to ionic effects, such as the reduction of the Ca^^ interface ions to Ca^, by silicon, and the removal of a fluorine layer. In spite of these difficulties, two attempts have been reported regarding the dual epitaxial deposition of thin films of crystalline dielectrics and silicon using yttria and spinel (Fig. 2.23). The zirconia-yttria process, whose result is illustrated in Fig. 2.23 a, consists in a double epitaxial growth: of cubic TxO^-^-^i and of a thin silicon film, using an ion sputtering technique. A MOS transistor effect has been demonstrated with such a structure [69]. In the spinel process (Fig. 2.23 b), tubs are first etched in the silicon substrate. The spinel (MgO-A^203) IS then deposited up to a thickness of 1 (im by open-tube vapor transport epitaxy, and finally silicon is epitaxially deposited. For a silicon thickness of 42 |im, TTL NOR gates driving a high-voltage transistor have been built (gain of 25, breakdown voltage exceeding 260V), suitable for the direct driving of plasma display panels [70]. E

HI

^^raQ

B

N--silicon 35 Hm. 5 10^^ cm-^

C

^ H ^ H

^ ^ Q ^ ^ N + - s i l i c o n Turn, 5 1 0 1 8 c n n - ^ ^ H Q ^ ^ |

silicon Substrate

silicon substrate

Fig. 2.23 - Example of structures obtained by the subsequent epitaxial deposition of a crystalline dielectric and silicon. Left) Cross section of a thin-film MOS transistors [69] Right) Cross section of a structure containing a high-voltage NMOS and a bipolar transistor [70]. 4.4. DEPOSITION OF AMORPHOUS OR POLYCRYSTALLINE SILICON FOLLOWED BY RECRYSTALLIZATION

Another way of obtaining a crystalline silicon layer on an insulator is, to first, deposit a layer of amorphous silicon and then, somehow, find a way to recrystallize it. 4.4.1. The Zone Melting Recrystallization (ZMR) process In 1963, Maserjian first had the idea of using a scanning electron beam to melt a small zone of polycrystalline germanium crystal deposited on a supporting dielectric [71], to obtain a monocrystalline material, as illustrated in Fig. 2.24. Due to the availability of lasers, this technique was reconsidered eleven years later to fabricate device-quality silicon films through Zone Melting Recrystallization (ZMR) [72, 73] as illustrated in Fig. 2.25.

A Review of Buried Oxide Structures and SOI Technologies

179

Fig. 2.24 - Maserjfan's patent describing recrystallization using electron beam (60's), [71].

Because of the limited dimensions of the molten zone, the recrystallization techniques cannot work unless there exists local contacts between the underlying monocrystalline silicon substrate and the deposited poly crystalline silicon layer. For that reason, holes [71 a] or stripes [71 b] must first be etched through the oxide film, to be used as recrystallization seeds (for practical reasons, the distance between the seeds is about 100 |Lim). This constitutes a considerable constraint for circuit designers, since transistors cannot be located on seeds. The seed pattern results therefore from the transistor layout, or vice-versa, and the recrystallization step is part of the MOS process. The integration of this material preparation in the process line is also a major disadvantage, as it widely complicates the design and processing steps. Focused laser beam

Molten zone Silicon Substrate

olycristalline deposited silicon Si02 buried oxide Recrystallized silicon

Fig. 2.25 - Illustration of the scanned laser recrystallization method (75*s), after [71 a]. 4.4.2. The Isolated Silicon Epitaxy (ISE) technique An altemative method has been developed circa 1985, in which a wafer-wide heating strip is used to trigger the recrystallization process, as illustrated in Fig. 2.26, instead of using a local (spot) heating. The process has been named ISE^M for Isolated Silicon Epitaxy(3)-

(3) ISE is a trademark of the Kopin Corporation, 695 Myles Standish Blvd, Taunton, MA 02780 USA.

180

J.L. Leray

Wire

"^ Wafer

Scan Direction/

^

^

pp,

MELT ZONE

Platen

a) b) Fig. 2.26 - Illustration of the scanned strip heater method (85 's), after [75]. a) Principle of the scanning system showing the upper wire heater. The wafer sits on a heated platen, b) Cross sectional view of the wafer showing the peripheral contact of the polysilicon layer with the monocrystalline silicon substrate.

In this method, the buried oxide is grown on the entire wafer surface, except for a small circular zone at the periphery of the wafer. A polysilicon layer is then deposited on the wafer and the recrystallization process is performed using the seeds of the periphery [74]. Consequently, the cumbersome seed array is no more necessary. The major consequence of this process has been to give a new life to the ZMR technique by simply procuring especially prepared wafers before the MOS process. Several manufacturers in the USA and in Japan presently propose good quality wafers for this process. 4.4.3. Examples of other ZMR applications Besides numerous demonstrations of the ZMR of silicon on Si02 or Si3N4 (a review can be found in [13], pp 13-35), other applications have been demonstrated, such as SiC on oxide, and Silicon-On-Diamond (SOD). SiC on silicon dioxide has been obtained by using, as a starting material, a (100) SOI substrate with a 1000-A-thick silicon layer on top of a 2-|im-thick Si02 [76]. Prior to the growth of SIC, a layer of carbon is deposited by propane carbonization which takes place at 1300°C with a dilution of 5% in H2. The deposition of SiC occurs by cracking silacyclobutane (SiC3H8) at 900°C until a thickness of 4500 A is reached. The crystalline type 3C-SiC (polytope) is obtained with a (100) orientation. This technique makes it possible to produce wafers that are larger than with the epitaxial technique, the latter being limited to 2 or 3 inches in diameter. The SOD structure is manufactured like the SOI structure, but the buried oxide is replaced by polycrystalline CVD-deposited diamond acting as an insulator. In the case described in [26], the deposition of silicon takes place on a very thin adhesion barrier (a 30-nm-thick Si02 layer), and the silicon film is recrystallized by ZMR. Transistors have been fabricated with such a technology, but their performances are, up-to-now, modest due to the presence of surface defects that affect carrier mobility (e.g. roughness, graphitization due to the hightemperature melting process, etc.). The ZMR method can be repeated several times: a new insulator, and a new silicon layer can be deposited on top of the recrystallized structure, and the seeding technique can be used

A Review of Buried Oxide Structures and SOI Technologies

recrystallized epitaxial source silicon

recrystallized epitaxial I silicon

deposited insulator

%^&T^

181

metal 2

n

silicon substrate

Fig. 2.27 - Illustration of a 3D structure which could be obtained by the ZMR technique (adaptedfrom [77]).

again, as illustrated in Fig. 2.27. A number of structures using several silicon layers have thus been fabricated around 1985. The carrier mobility (a parameter sensitive to the crystalline quality) was found to decrease when going from lower layers to upper layers, but was sufficiently good to yield three stacked circuits (an image processor), comprising: photodiode arrays on the top layer, AID converters in the intermediate SOI layer, and arithmetic units in the bulk-Si layer. The structure allowed parallel processing and a 64-pixel image was treated within 3 |as. However, the maximum number of layers could not exceed 3 or 4, and no significant circuit fabrication has been achieved beyond that nixmber. Figure 2.27, featuring three levels, including the bulk one, illustrates this possibility of 3D integration (after [77]). 5. SOI MANUFACTURING: PROCESSES BASED ON OXYGEN IMPLANTATION A buried oxide can also be manufactured by introducing oxygen undemeath the silicon surface, provided the crystalline structure of silicon is preserved (or restored) over a sufficiently thick surface layer. Two methods have been used: • implantation of oxygen at a given depth, described in this section, • selective thermal oxidation in channels deep under the surface, detailed in Section 6. 5.1. THE HIGH-FLUENCE S I M O X PROCESS

5.1.1. Early developments The idea of producing Si02 by ion implantation was first reported in 1966 at the dawn of the ion implantation technique [78], but the first successfiil production of a buried Si02 layer was only carried out in 1977. The thickness of the top silicon layer and that of the buried oxide were shown to depend respectively on the ion energy (which determines the implantation peak and range in silicon), and on the oxygen fluence [79].

J,L, Leray

182

This gave birth to the SIMOX process (Separation by IMplantation of Oxygen), as proposed by Izumi in 1978 [80]). The two parameters, energy and fluence, can be adjusted to some extent [88]. It was shown in the late 70's that the best results are obtained with high fluences^^^ (1.5 to 1.8 lO^^ cm"^) of oxygen ions implanted at 200 keV [81]. These conditions are called the "standard SIMOX" conditions. In the early years (1980-87), implantations lasted long (24 hours) due to the limited flux of oxygen then available from the high-flux implanters. Since 1 mA is equivalent to only 6.25 10^^ OVcm^/s, it used to take more than one hour to process a single 4-inch wafer. After 1987 one vendor introduced a very-high-flux implanter capable of delivering 80 mA. This enabled the production of wafer batches in a shorter time and at a reasonable cost. 5.1.2. Oxygen and damage profiles The implantation depth in silica depends on the amount of energy the O ion deposits while passing through the substrate. As an example, for an oxygen ion implant of 150 keV, the deposited energy is 5 eV/A/ion at the silicon surface, but peaks at 15 eV/A/ion at a depth of 0.3 i^im. Below this depth, the ion slows down even more and finally stops [82]. Figure 2,28 shows the oxygen profiles and the implantation-induced damage profiles obtained for implantation energies of 120 and 190 keV.

3000 DEPTH (A)

4000

5000

Fig. 2.28 - Concentration profiles of implantation-induced damage (curves without symbols) and of implanted oxygen (squares and diamonds) for two implantation energies (after [83 a]). Curves ECOIL have been obtained using code TRIM. 92.

The consequences of such an implantation is the creation of defects in silicon. These defects may be point defects or extended defects (dislocations, stacking faults, multiple stacking faults), and their density is highest where the energy loss of the implanted atoms is maximum [83 a]. In Fig. 2.28, the curves called "ECOIL" correspond to the energy transferred to the recoil Si atoms after the knock-on processes. We note on this figure that the implantation peak of oxygen, where the buried layer will form, is deeper than the "defect peak", which is indeed confirmed by XTEM observations. The presence of defects above the buried oxide layer is undesirable and their generation may be avoided by performing implantation at high temperature. (4) In the field of ion implantation, the term "dose" is often used instead of "fluence".

A Review of Buried Oxide Structures and SOI Technologies

183

In general, the damage profile and the implantation profile yield separate peaks. If the substrate temperature is maintained between 500 and 700°C during implantation, it aimeals out the damage produced diiring implantation [84 a] and the profiles obtained look like that of Fig. 2.29 a. At lower implantation temperatures (400°C), the damage remains. CFS

^•rfs»j+$i A o

I Oxygen

I C/3

O

Q5

I.O

0

Depth (|a.m) a)

b)

1.0 0.5 Depth (|im)

Fig. 2.29 - Oxygen profiles obtained for two substrate temperatures during implantation, and for the same energy of 150 keV (after [84 bj). a) Standard conditions for implantation at 500°C. b) EFS special implantation at 350°C.

A technique called EFS (Electric Field Shielding) takes advantage of this remaining damage [82]. Oxygen atoms can be selectively trapped in the defect zone, producing a substoichiometric oxide layer, (SiO^ with x = 0.2 to 0.6 over a 800-A depth) distinct from the thick buried oxide, as illustrated in Fig. 2.29 b. As a result, deep bulk electric states are introduced in the silicon band-gap. A model derived from the CFO band-gap model (CohenFritsche-Ovshinsky, [83 b]) yields trap densities of 1 to 3 10^^ cm"3.eV"^ This buried amorphous layer acts as an electric shield against field effects resulting firom the buried oxide. It brings various advantages for high-voltage devices [84 b], or for hardening against total dose effects [82]. 5.1.3. The Ultra-High Temperature Annealing (UHTA) step To the implantation step, first developed in the late 70's [80], an Ultra-High-Temperature Anneal (UHTA) step was added in the early 80*s. This process aims at defining sharp Si02/Si interfaces by redistributing the implanted oxygen. It also produces oxygen-fi-ee silicon edges and a stoichiometric buried silicon dioxide. This step can be viewed as an "intemal oxidation" in the sense that the oxygen source is buried and confined. The first attempts used standard anneal furnaces with N2 or Ar ambients up to 1200°C, but the resulting oxide and silicon quality was poor, due to a large amount of: dislocations and stacking faults (10'^ to 10^ cm-^), and interface states (10l2cm"2.eV"l).

184

J.L. Leray

• S a m>t iiintalact Fig. 2.30 - a) XTEM micrographs showing (from right to left) how an Ultra-High-Temperature Anneal improves the quality of a SIMOX layer (reprintedfrom [86 a]) Right) as-implantedSIMOXat 200 keV, JOO^'C, L6I0^^OVcml Left) usable SIMOX sample. Notice the typical silicon islands just above the lower SiO/Si interfrice.

Fig. 2.30 — b) Interpretation of Ultra-High Temperature Anneal according to Jablonski & al [86 b]. From left to right, the influence of anneal temperature and anneal time is illustrated (SFT: Stacking Fault Tetrahedron MFD: Multiple Faulted Defect).

A Review of Buried Oxide Structures and SOI Technologies

185

Improvements resulted from the use of specific fiimaces with refractory SiC walls and oxidizing ambient. In 1985, the SOI team in Grenoble (Fr) noticed that very abrupt interfaces and high-quality silicon could be obtained by a high-temperature post-implantation anneal (6 hours at 1300°C in argon + 1% oxygen ambient, with a deposited Si02 capping layer) [85-86 a]. Figure 2.30 illustrates how the quality of the buried layer gradually improves during annealing.

Fig. 2.31' XTEM micrograph of a low-dose SIMOX sample showing the sharp interface between the buried oxide and the silicon substrate [87].

5.1.4. standard temperature conditions used during implantation to obtain a monocrystalline silicon layer Usually, the presence of a non-stoichiometric and amorphous layer between oxide and silicon must be avoided. To obtain a monocrystalline silicon layer and a sharp interface between silicon and oxide, as illustrated in Fig. 2.31, the damaged zone must be recrystallized. This can be obtained if the wafer temperature can be kept high (500-700°C) and well controlled during ion implantation [85, 89]. Damage due to the slowing down of the oxygen ions in the silicon layer can thus be continuously annealed during implantation. This range of temperature is a basic feature of the SIMOX process. 5.1.5. Standard dose conditions used to obtain a thick SIMOX buried oxide The standard oxygen fluence (dose) used to obtain a 3800-A-thick oxide is 1.8 10^^ cm-2 at 190 keV. Smaller fluences have been tried. Aspar [89] noted that for a 190 keV energy, oxygen doses below 3.5 lO^'^ cm-2 produce lamellar Si02 precipitates after UHTA whereas for doses centered around 4 lO^'^cm-^, a continuous layer is obtained, although some Si02 precipitates still remain above this layer [83 a]. For higher doses up to 1.8 lO^^ cm-2, only one buried oxide layer is observed, but silicon islands appear at its lower side. However, these silicon islands never exceed 100 A in thickness, and thus do not interfere with the isolating quality of the thick SIMOX oxide.

y.L. Leray

186

5.1.6. Standard conditions used to obtain a thin SIMOX oxide In the late 80's, other implantation conditions were found and excellent ultra-thin buried oxides (between 47 and 90 nm) and silicon layers were also obtained by using either 120 keV or 80 keV O"^ implantations [88]. There exists "magic" sets of parameters, often called the "Izumi conditions" [96], which permit one to manufacture thin SIMOX substrates reliably. These "process windows", determined for the purpose of improving stoichiometry and reducing the density of defects, are also clearly visible when measuring electrical parameters such as the oxide breakdown voltage, as illustrated in Fig. 2.32 [90]. 500

rs

Fig. 2.32 - Illustration of an "oxygen dose window" for a 180 keV-implantation as measured through oxide breakdown voltage [90].

lOOh

%

2 CQ

160+dose (1018 cm-2) Compared with the standard thick-oxide SIMOX process, the quaUty obtained by the lowdose process remains excellent, as summarized in Table 2.2 (giving data published by the SOITECCieinl995)[91]: Wafer diameter (inches) 4 5 Type of process Standard single implant process

Low-dose process

Implantation conditions 190 keV

120 keV

1.8 lOl^ 0"^.cm-2

4 10l'7 0+.cm-2

Layer thickness Top Silicon

500 to 2050 A

6

Thickness uniformity across the wafer on wafer: 80 A wafer to wafer: 160

100 A 200 A

160 A 240 A

A Buried Oxide

4000 A

±200 A

±200 A

±200A

Top Silicon

500 to 1800 A

on wafer: 50 A wafer to wafer: 50 A

50 A 50 A

50 A 50A

Buried Oxide

800 A

±50A

±60 A

±80 A

Table 2.2 - Variations of the SIMOX dimensional specifications depending on the wafer diameter and type of process used [91].

A Review of Buried Oxide Structures and SOI Technologies

187

5.1.7. The InTernal OXidation (ITOX) process The thickness of the siUcon layer can be adjusted by using an additional thermal oxidation step. It has been found that oxygen can diffuse across the thin-silicon layer and internally segregate at the Si-Si02 interface where the stable silicon dioxide acts as a sink. The superficial silica layer is then etched off This technique provides thinner silicon films with an excellent thickness uniformity (< 80 A across the wafer, < 50 A from wafer to wafer). This process called ITOX (InTemal OXidation), is illustrated in Fig. 2.33. Thickness ftiorbmeht

JiPiHi^l^^

Fig. 2.33 - Illustration of the morphological changes induced by internal oxidation (ITOX) [92]. XTEM photomicrographs of SIMOX wafers, a) before oxidation. b) after oxidation. (a)

0J/4m

(b)

5.1.8. Adjustments by supplemental implantation An additional oxygen implantation makes it possible to increase the buried oxide thickness (but a second UHTA is then necessary), and to obtain an intermediate ("medium") oxide thickness (see Table 2.3). This provides a great flexibility in thickness adjustment. 5.1.9. Multiple implantation To obtain a better oxide quality and reduce the density of silicon islands, a two or threestep technique is used. It consists of a partial implantation followed by a UHTA step in order to obtain a cumulated oxygen dose of 1.8 10^^ cm"^. This technique yields the best quality in terms of breakdown voltage, and minimizes the defect densities both of the oxide layer and of the silicon film (see below). In the case of the "triple implant", the oxygen dose of 1.8 lO^^cm'^ is split in three implantation steps of 0.6 10^^ O+.cm-^ each. A UHTA step takes place after each implantation. It leads to a considerable improvement of all quality indicators (interface state density, density of pipes, etc.), at the price of a tedious processing. 5.1.10. Other insulators obtained by ion implantation Altemative techniques have been proposed in which nitrogen, nitrogen and oxygen, or even carbon are implanted. Nitrogen implants had some success and oscillators using this technology were manufactured in 1983, using the "Separation by IMplantation of Nitrogen" (SIMNI) process [93].

188

/.L. Leray

Nitrogen has also been implanted before or after oxygen, to obtain a buried oxynitride. It was found that silicon nitride easily forms a polycrystalline state during high-temperature annealing, whereas silicon oxynitride remains amorphous [94] (an amorphous state is preferred because it offers a better resistance against mechanical stress and impurity diffiision). By using a beam of NO"^ ions, a co-implantation of oxygen and nitrogen has been performed, and the results compared to the separate implantation of O followed by N and N followed by O. It was found that the nitrogen co-implantation or the implantation of oxygen prior to nitrogen gives the best results (in terms of crystallinity of the top Si layer), probably due to the very different diffiision constants of N and O during the high-temperature annealing sequence [95]. When oxygen is implanted prior to nitrogen, N atoms segregate to the wings of the oxygen distribution, and form two interfacial oxynitride layers. These layers act as barriers against the diffiision of impurities into silicon. Attempts to form SiC, by using carbon implantation have met with difficulties due to graphitization phenomena, apparently unsolved up to now. This can be related to low diffiisivities in SiC itself, as long as it forms, hindering carbon redistribution during annealing and therefore making it impossible to attain stoichiometry. 5.2. MAJOR DEFECTS ENCOUNTERED IN S I M O X STRUCTURES

Devices using BOX structures of the SIMOX type face specific problems and feature defects which we review next. These defects affect the quality of the top silicon layer, the top silicon/oxide interface and the buried oxide layer. 5.2.1. Fixed charge and interface traps In the case of the single-implant SIMOX, the low dose process greatly improves the interface quality, as illustrated in Fig. 2.34 [87]. In particular, the density of interface states of the low-dose SIMOX becomes comparable with that of a thermal oxide. The same observation can be made in the case of the multiple implant SIMOX. 10^^

Substrate/ Oxide Interface Trap Density [eV-i*cm-2]

10'2

1\

\w

10^0

1X ^

-^ ^

^

^

^

Substrate/ ^ '10^1 Oxide Interface Fixed Charge ^\Q^o Density [cm-2]

10»

10» 1330oC 1330oC 1350oC 1350oC 1300oC 4 hrs 6 hrs 4 hrs 6 hrs 6 hrs I I High Low Dose Dose

a1 11 1 0 0 . 7 9 (mms) ' • 0 . 4 4 (mrn^) AO.20 (mm2)

S

c!)

baaa—p^

'

\I

n(—'

E

1330oC 1330oC 1350oC 1350oC 1300oC 4 hrs 6 hrs 4 hrs 6 hrs 6 hrs I 1 High Low Dose Dose

Fig, 2.34 - Dependence of the density of interface traps a) and of the density of fixed oxide charge b) on process conditions (after [87]),

A Review of Buried Oxide Structures and SOI Technologies

189

5.2.2. Silicon islands in the buried oxide The following XTEM micrographs (Fig. 2.35) show a silicon island and its crystalline structure. Although impressive in size, these particles are not harmful, for at least two reasons: 1/ they are much thinner than the buried oxide thickness and have therefore no impact on the breakdown properties, 2/ they are always located close to the lower Si/Si02 interface, which gives their global state of charge a negligible influence on the upper silicon layer. 5.2.3. *Tipes** and nano-clusters in the buried oxide Two other classes of defect exist in SIMOX oxides: pipes and nano-clusters. Pipes are one-dimensional columns of silicon which form when foreign particles, present at the silicon surface, act as screens during ion implantation, and leave columns of unoxidized silicon in the oxide layer [97-98]. The presence of these defects is the source of local leakage currents across the oxide (in the nanoampere range per "pipe") which can lead to a premature breakdown [99 a]. This defect is known to have a major impact on the circuit manufacturing process yield.

a)

b) Fig. 2.35' Microscopic view of a silicon island encountered with the standard or low-dose SIMOX process: a) cross section of a standard SIMOX buried oxide with an unusually high density of silicon islands (reprinted with permission from [101J. b) magnified view of a silicon island in a standard SIMOX oxide [102]. c) cross section of a thin low-dose SIMOX oxide (reprinted with permission from [89]).

c)

190

J.L. Leray

Linked silicon atoms can form nano-clusters ranging in size from a few atoms to a few tens of atoms. This type of defect occurs mainly in single-implant materials. Nano-clusters result from an incomplete oxidation [100]. Their effect is subtler since they are too far from each other to influence either electrical conduction or electrical breakdown. These clusters can provide trapping sites, of large capture cross-section, which could play an active role during exposure to ionizing radiation. The use of multiple implantation (i.e. of implanting the same ion dose in multiple steps, each step being subsequently annealed), drastically reduces the presence of this type of defect. Techniques allowing the measurement of these minute defects are beyond the scope of this infroduction to SOI technologies, but can be found in the general references quoted at the end of the chapter (see "Conference Proceedings and review books"). 5.2.4. Leakage currents induced by defects in SIMOX structures These localized or chained defects cause a decrease in the value of the oxide breakdown field, or allow leakage currents to occur. The type of defects and the typical current-voltage behaviours have been careftiUy studied since they largely impact the manufacturing process yield for large circuits [99 a, 99 b]. Figure 2.36 shows leakage current densities typical of SIMOX annealed as in the standard process (curve 3), or un-annealed (curve 2). In the latter case, the behaviour is similar to silicon-rich deposited Si02. For annealed standard SIMOX (4000 A), and below 80 V (2MV/cm), the I(V) characteristic is quasi-ohmic and temperatiire-dependent, with a low activation energy (0.3 eV). This conduction mode has been attributed to trapping on localized defects and thermal detrapping [103,104 a]. (N

ao

^

•02 •04

>^

-*-»

•1-H CO

a

•06

(L>

n3

^

•00

U

•10

(D

o

F-H

O

•12

HJ

4 6 Electric field (MV/cm)

10

Fig. 2.36- Typical leakage current densities are plotted vs. applied field for several types of oxide (after [104 aj). (1) Si-rich SiO2 (2) un-annealed SIMOX (3) annealed (standard) SIMOX (4) thermal oxide.

A Review of Buried Oxide Structures and SOI Technologies

191

Beyond 80 V (2 MV/cm), the conduction is weakly dependent on temperature and, therefore, a second mechanism has been proposed involving tunneling between silicon clusters. Through modeling [104 a] an effective barrier height of 1.4 ± 0.1 eV has been attributed and the number of defects, supposed to be uniformly distributed, has been estimated at 2.101^ cm-^. The average size of the defects should be 5 A, which corresponds to three atoms of silicon. For the un-annealed implanted silicon, the values are respectively: 0.4 eV and 10^1 cm"3. In the 4 to 6 MV/cm range, for standard SIMOX, a Fowler-Nordheim injection regime from the interfaces takes place. According to this model, injection barrier heights are asymmetrical (1.39 and 1.77 eV, i.e. one half the 3.2 eV value for thermal Si02). This can be attributed to the presence of specific electronic levels in the oxide, which reveals again defects lying in the buried oxide [104 b]. The interpretation of this clustering can be found in [105]. Due to the solubility of oxygen in silicon at high temperature, during the HTA step carried out at 1300°C for 6 hours, a small amount of oxygen migrates from the silicon dioxide layer into silicon and the two Si/Si02 interfaces act as oxygen sinks. Due to the high temperature, the out-diffusion of oxygen takes place throughout the oxide, leaving isolated clusters behind. Consequently, this feature is inherent to the SIMOX structure and process. Other types of defect may also be encountered in the oxide such as metallic contamination coming from the implantation column, or pipes of silicon more or less connecting the two Si/Si02 interfaces. The electrical consequences of these defects have been reviewed in [104 a].

Fig. 2.37-TEM micrograph of a typical stacking fault tetrahedron (SFT) featuring an average length of 0.1 fjm (reprinted with permission from [106]).

5.2.5 Defects in silicon In advanced MOS or bipolar transistors, improvements in the quality of the top silicon film can only be obtained by drastically reducing the density of such structural defects as dislocations and micro-stacking faults (Fig. 2.37), which affect the minority carrier lifetime [106, 107].

192

J,L, Leray

Let us note that significant reductions in dislocation density have been obtained by optimizing the implantation and anneal procedures. Dislocation densities ranging from - 10^ cm-2 (for a low dose SIMOX material) to - 10^ cm'^ (for a standard one), are typically measured on commercial substrates [108]. Minority carrier lifetimes above 10 ms have been measured in the top silicon layer of standard SIMOX wafers. Conversely, the surface recombination velocity at the buried Si02-Si interface has been found to be in the 10-100 cm.s"! range. These values make it possible to process bipolar transistors on SIMOX and obtain excellent characteristics. 5.3.

QUALITY AND VARIETY OF SIMOX SUBSTRATES

The quality of SIMOX substrates has been constantly improved since the 80*s and several companies presently propose a wide array of such substrates. 5.3.1. First-order progress The quality of SIMOX materials has greatly improved over the years, as illustrated in Fig. 2.38, which shows the defect density measured in the thin silicon films. The latter has improved at the constant rate of one decade per year from 1985 to 1992 (10^ defects/cm^ in 85, mostly threading dislocations, to 10^ defects/cm^ in 92, including pairs of dislocation half-loops [109] and narrow or pyramidal stacking faults pinned on residual precipitates [100]). The defect density of these films has become comparable to that of bulk silicon [12]. This decrease is due to a number of factors, but mainly to improvement in the cleanliness of the implanter column. Contaminants coming from: dust particles projected and stuck against the wafer during implantation, silicon diaphragms, iron and chromium from column walls, have been greatly reduced. Improvements in the annealing conditions have also played a role. Another factor has been the discovery of the fractional (so-called "multiple") implant. The use of split implantations and UHTA has reduced the density of silicon dislocations by a factor often and has eliminated the presence of silicon islands in the oxide. 10 10 I

S

10 8 J

.^

10

g

10'

O

^

10^ 4 10-

#

Q

10^

• Single implant

10 3

O Multiple implant ~n— 85 86 87

10-^ 84

R8

year

Fig. 2.38 - Illustration of yearly improvements in dislocation density in SIMOX silicon films, (after [108]).

89

90

91

A Review of Buried Oxide Structures and SOI Technologies

193

5.3.2. Currently available processes The following table, made up of data coming from companies, or from laboratories (Fraimhofer Institute [110]), reviews the practical implantation conditions and the state of the art as of mid-1995 (maximum values obtained with production wafers from 4 to 6 inches in diameter). In the ITOX process of Nippon Steel, the initial BOX thickness is increased from 85 nm to 105 nm by an additional thermal oxidation. An advantage of this technique is the improvement of the silicon film and a reduction in the roughness of the Si/BOX interface (interface roughness is usually expressed as the Root Mean Square of thickness fluctuations). The very thin silicon layers (30 to 50 nanometers) are obtained by an additional thermal oxidation. They open the way to CMOS/SOI structures with gate lengths of 0.1-0.2 i^m. Type of process used (data valid year 1995)

Oxygen implantation energy (keV)

Oxygen fluence

Single implant 4-8 inches (S)

190

Single implant 4-8 inches (I) Multiple Implant

Dislocation density in silicon

|Al

(A|

and local roughness (RMS in A)

and local roughness (RMS in A)

[cm-^l

1.8 10^^

500 to 2050

4000

< 5 10^

<0.2

190

1.8 10^^

500 to 2050

3550-4100

190

0.6 + 0.6 +

Buried oxide thickness

Breakdown Voltage [V] and /or breakdown field ([MV/cml) 190 V (F)

<0.1

4000

290 V

0.6 10^^

4 inches (F) Low dose ITOX 4-8 inches (I) Low dose Medium

Silicon thickness

Pipe density in oxide Icm-2]

[0'*".cm"^l

120

4 10^'^+

500 to 2400

2000

500 to 1500

1500

<0.2

<1104

<2

3 10l'7

> 100 V (>8)

ITOX (S) 1750

1050

(2.4)

(4.5)

Low dose ITOX 5 inches (K-NTT)

1700

Low dose (NS)

Low dose ITOX (NS)

Low dose 4-8 inches (S)

120

4 10^'^

< 3 . 10^

<5

1000

<100

<0.2

3200

850

< 1 10^

(4)

(10)

500 to 1800

800

55 V (5.5)

35 V (4)

<1104

<2

40 V (5)

Low dose + epitaxial Si (4nm)(S)

120

4 10l7

4 ^m

800

2 10^

<2

Table 2.3 - Review of process parameters and of physical and electrical parameters of the BOX structures obtained by current (1995) manufacturing processes. Data has been obtained from technical documentation of several companies (SOITEC (S), Ibis (I), NIPPON STEEL (NS), KOMATSU-NTT (K-NTT) and from the Fraunhofer Institute (F)) [110].

/.L. Leray

194

6. PROCESSES BASED ON DIRECTED THERMAL OXIDATION (FIFOS, SOOZ AND GAA METHODS) Another way of fabricating a silicon layer on an insulator is to somehow manage a local thermal oxidation of the silicon substrate undemeath the element (device) to be isolated. At least three techniques make this possible: FIFOS, SOOZ and GAA. 6.1. THE FIFOS PROCESS The purpose of the FIFOS process (FIFOS: Full Isolation by Oxidation of Forous Silicon) is to oxidize the silicon substrate through microchannels or pipes previously manufactured by means of anodic etching in hydrofluoric acid. Invented in 1981 [111], this technique has been reviewed in 1987 [28] and updates can be found in [112]. A pipe or pore pattem is obtained on a depth which depends on the etching time (a depth of one micron is easily obtained). 6.1.1. Selective anodization The electrochemistry of anodic etching is such that etching takes place whether the material is p doped or n"^ doped [113]. There thus exists two possibilities to perform selective anodic etching: (1) use a p substrate and implant n regions (in this case, the substrate is etched and the n zones remain untouched), (2) use an n-doped substrate and fabricate a buried n+ doped layer (by high-energy implantation). Holes are then etched through the upper n layer to reach the buried layer. T

=r P-Si 3SS5C

(a)

Starting structure

JV:^A':L

^l^'^r^t^'^ ®i

Formation of porous silicon ^in the p-type region by anodic dissolution of silicon

anodic reaction

/g\

Complete insulation of islands by porous silicon

/gN Final structure after fiiU oxidation of porous silicon

Fig. 2.39 - Illustration of the various FIFOS process steps [115].

A Review of Buried Oxide Structures and SOI Technologies

195

For low-doped p substrates (p"), the distribution of pore radii depends little on the density of the anodic current and is centered around 20 A. The porosity ratio (percentage of voids in the layer), depends on the p-type doping concentration and is usually close to 60% for lightly doped substrates [113, 114]. The internal surface can thus reach several hundred (200-400) square meters per cubic centimeter of silicon. Figure 2.39 describes the process used for a p-type silicon substrate [115]. This process has produced the first ever FIFOS CMOS devices [116]. 6.1.2. Selective oxidation Once porous silicon is obtained, oxidation through the pores is carried out in dry O2. Oxidation temperature is kept very low (300°C-1 hour) to avoid both the collapse of the network and explosive reactions due to the high specific surface of this highly reactive material. In the first oxidation step, the surface of the pores is covered with one monolayer within one hour, which corresponds to an oxidation of 15% of the volume. The second oxidation step takes place between 700 and 900°C in steam. After oxidation, TEM micrographs reveal the presence of closed cavities, a few nanometers long, showing that the oxide is porous (5-20% depending on the oxidation temperature). An oxide densification step is therefore necessary. 6.1.3. Densification Densification is obtained in an oxidizing ambient (dry O2 or steam), between 1000 and 1100°C. Due to the activation energy (3 eV) of the process, and to its sensitivity to the ambient, a viscous flow of silica is proposed to explain densification [114]. 6.1.4. Obtained results The best oxides made from a p" substrate have been obtained for the following sequence: pre-oxidation in dry O2 at 300°C-lh, followed by oxidation at 900°C-lh30 in wet O2, densification at 1090°C for 4 minutes in wet O2 and then for 30 minutes in dry O25 followed by an anneal 1090°C-30 minutes in N2 [114]. The breakdown field has been found to be 6.4 MV/cm and the fixed charge density +10^1 cm"^ for a 0.6-|am-thick plane oxide. These good values are attributed to the presence of a thin high-quality oxide grown in the substrate during the first oxidation of the porous layer, prior to densification. 6.1.5. Peculiarities of FIFOS oxides The role of the interfacial layer, in series with the reacted porous layer, has been confirmed by nitridation studies (carried out after the low-temperature oxidation) [117]. Oxynitride (22 at% N, 40 at% O) is produced instead of oxide by performing a thermal treatment in ammonia at 1000°C. The nitridation of oxidized porous silicon differs from the nitridation of thermal oxide, in that it incorporates -- 40 at% of nitrogen instead of ~ 5 - 10 at% in thermal oxides.

196

7.L. Leray

Unlike ammonia-nitrided thermal oxides, which exhibit a nitrogen build-up at the oxide/silicon interface (as described in Chap. 1 of this volume), porous silicon displays a fairly uniform nitrogen concentration throughout the thickness. When a high-temperature oxidation takes place after nitridation, a loss of nitrogen is reported as well as a build-up of nitrogen at the interface and an improvement in dielectric breakdown. Another reported feature of FIFOS buried oxides is the presence of fluorine (a few at. %) and hydrogen [117], probably left-overs from the anodic dissolution in HF. 6.1.6. The advantages of using n-doped substrates To obtain device quality silicon, an epitaxial growth is generally performed on the lowdoped (n") silicon islands. However, this approach, based on p-type substrates has the drawback that a large silicon island is needed to form a sufficiently thick, uniform and continuous buried porous silicon. After a fiiU oxidation, the thick oxide layer induces a large mechanical stress, which provokes a warpage of the silicon wafer, not compatible with VLSI processing. To overcome this difficulty, the FIFOS process can be applied to n-type substrates, {\Q^^ cm'^) containing an implanted buried n"^ layer (10^^ cm"^). Freferential anodization takes place in the buried n^ layer (10^^ cm"^), [115, 118, 119]. Then, a 1 jim-thick silicon layer is epitaxially deposited by CVD and vias are etched by RIE to allow a contact between the n^ layer and the hydrofluoric acid. The buried n+ layer becomes then the porous layer. All these characteristics: (1) compound oxide layers with the first one similar to a thin thermal oxide (2) presence of fiuorine (3) possible presence of nitrogen if nitrided, explain the good quality of the FIFOS buried oxide layer, obtained rather straightforwardly from the beginning, and at a much lower cost than the other competing processes (ZMR and SIMOX). Historically, the FIFOS process has greatly helped to demonstrate the validity of the SOI concept by allowing the production of 64-kilobit SRAMs on 4-inch wafers, 5 years before the SIMOX process did. However, this process suffered from two difficulties: (1) the necessity to implant islands of n"^ or p"^ zones at pre-determined locations depending on the design of circuits, and (2) wafer warpage due to differential stresses appearing after the second oxidation step and incompletely relieved by densification. 6.2. THE S O Z AND S O O Z PROCESSES

SOZ simply means Silicon On Zirconia (Zr02). This technique is basically a variant of the SOS process, in which the hexagonal crystal of M2O2, is replaced by a cubic alloy of YttriaStabilized Zirconia (Zr02,Y203). The yttrium content is chosen at about 10% to enable the cubic networks of Si and Zirconia to match.

A Review of Buried Oxide Structures and SOI Technologies

197

In the SOOZ process, one takes advantage of the fact that oxygen ions diffuse across zirconia. This allows an "internal oxidation" of the interfacial silicon through Zr02 [65]. This type of process dramatically improves the underlying interface by producing a compound Si/Si02/YSZ/Si structure. N" channel and p- channel transistors have been successfully produced and evaluated in terms of radiation effects [69, 120, 121]. 6.3. T H E GATE A L L AROUND PROCESS

Another technique uses a localized oxidation undemeath the transistor channel. It is known as the "Gate All Around" (GAA) Silicon On Insulator process [30, 122, 189 b]. Fabrication is straightforward in principle. A SIMOX substrate is used as a starting material and by means of a single supplementary mask, the buried oxide is etched undemeath a well defined silicon island as illustrated in Fig. 2.40. The silicon bridge can then be thermally oxidized to obtain the gate oxide and a polysilicon gate electrode is deposited by CVD, all around the bridge. Cavity

Source

Fig. 2.40 - Illustration of the Gate All Around fabrication process ISO]. a) A cavity is first etched underneath the silicon island. b) Aspect of the complete Gate All Around device after deposition of the gate electrode.

This method takes advantage of the selectivity in etching that exists between the silicon layer and the BOX. The advantages of such a device are: a better control of the transistor, giving a higher transconductance and the absence of back-gate effects coming from the buried oxide. To date, transistors, ring oscillators and a 1-kilobit SRAM have been manufactured with this technique and display a good radiation hardening level [123, 124]. A major drawback is the large capacitance of the gate, since the gate electrode overlaps a significant part of the source and drain areas. Multiplied by the Miller effect, the gate-to-drain capacitance is especially detrimental to the speed and power consumption of the circuits. 6.4. T H E EPIC EPITAXIAL AND CHEMICAL THINNING PROCESS The EPIC process (Epitaxial Process for Insulated Circuits), first reported in 1964 [125], was first designed to render components less sensitive to photocurrents caused by ionizing radiation. For that purpose, one replaces the usual isolation based on the use of pn junctions with isolation by a "tub" of silicon dioxide [126]. The final structure features a silicon monocrystal surrounded by a silicon dioxide layer, itself immersed in a polysilicon wafer as illustrated in Fig. 2.41.

J.L, Leray

198

To obtain this structure, its designers started from the idea that the epitaxial growth of silicon on silicon dioxide could only lead to polysilicon. Therefore, the polysilicon film is deposited on the silicon dioxide until it is thick enough to mechanically sustain itself like a monocrystalline wafer does. The wafer is then tumed upside down, and the polysilicon layer becomes the handling part of the wafer. The previously oxidized monocrystalline wafer is then mechanically and chemically reduced to a thickness of 5 to 20 ^im, as illustrated in Fig. 2.42. The classical process used to produce diodes and transistors is carried out, with a buried insulator inserted between silicon and polysilicon. Various techniques are used to obtain a lateral isolation, using mostly chemical etching and oxidation before polysilicon deposition.

SBlliccMn!

Polycristalline Si

^.

^

«: -» ^

>flftWAW«X!

^

n

l=N»Jy»l«k30«-»

P^^tv^lfloon

Fig. 2.41 - Basic steps of the EPIC process [126].

Fig. 2.42 - 3D view of the basic EPIC process steps [127 a]

This complex method has benefited from progress in mecanochemical polishing (CMP) techniques. It has been used for more than 30 years, on a small scale, to build radiation-hard simple circuits and on a larger scale to build analog circuits: electronic switches and multiplexers (Harris Corporation and subsidiaries) [127 b]. 7. SOI MANUFACTUMNG PROCESSES BASED ON THE BONDING OF TWO MATERIALS (BESOI) Another way of producing a buried oxide structure is to somehow force an oxidized wafer to bond with an unoxidized one and subsequently to thin one of the two (bonded) wafers to obtain the desired thickness of active semiconductor substrate.

A Review of Buried Oxide Structures and SOI Technologies

199

7.1. PRINCIPLES OF THE B E S O I TECHNIQUES

The generic name of the techniques based on this concpet and developed in the 80*s is "BESOI" which stands for "Bond and Etch-Back Silicon On Insulator". In a BESOI process, the layers of interest are prepared separately in the best possible conditions and may consist of Si, Si02, Si3N4, SiC, BaO-A>^203-Si02 etc., [128]. They are then brought together. The phenomenological aspects of bonding monocrystals, monocrystals to polycrystals, monocrystals to amorphous substrates, or polycrystalline materials to polycrystalline substrates are discussed in [129]. Generally, surface uniformity (e.g. 2nm) is an essential criterion to achieve bonding, unless "distributed" bonding occurs on asperities or at the surface of grains. Table 2.4 lists the types of material which can be bonded to silica, according to [129]. Si, Ge Elemental material

Mo, Ta, Ti, W B, C (diamond) GaAs, ZnSe B4C, BaF2

Inorganic compounds

Si02 (glass)

Table 2.4 - Elements and compounds that bond to oxidized silicon, spontaneously or with application of pressure, according to [129].

SrTi03, LiNb03 Organic polymeric compounds

Polyimide, polymethylmethacrylate Polycarbonate, polyarylate

To be of practical interest for isolated microelectronic devices, the silicon layer must not exceed a few microns. Therefore, one of the two wafers must be thinned afterwards, in order to meet the thickness requirements needed for fiirther processing. Figure 2.43 illustrates how SOI substrates can be manufactured by bonding a silicon wafer onto an oxidized silicon wafer. 7.2. W A F E R BONDING

Bonding occurs through the formation of: hydrogen bonds between silanol groups Si-OH...HO-Si (weak bonding) or the merging of covalent siloxane Si-O-Si bonds (strong bonding). Bonding could not be achieved without applying an extemal force until 1985 [131] (mechanical [126] or electrical forces [131, 132]). The surfaces, which must display a very small microroughness (less than 10 nm), must be cleaned to avoid contaminants (such as metallic particles, alkali ions...) and are generally prepared before contact (e.g., by hydrophilization in NH4OH+H2O2+H2O and rinsing in deionized water [133]).

200

J.L. Leray base wafer

top wafer

precise dimensions TTV (< 1 ^m) LTV (< 0.5 jum)

2/xmq

oxidation

Si02 Si

[sOI structure

Fig. 2.43 - Illustration of the typical steps necessary to obtain a Silicon-On-Insulator thin film using the wafer bonding method (after [130] slightly modified).

Current processes differ depending on the bonding temperature, the ambient, and the subsequent treatments [134]. Below 130°C, fragile hydrogen bonding dominates but is weak. • For hydrophilic surfaces, the surface energy(5) of bonding (and also the adhesion force) is approximately insensitive to annealing temperatures, between 200°C and 800°C, due to the predominant silanol condensation allowing the transformation of hydrogen bonds into siloxane bonds. This bond formation is accompanied by an elastic deformation of the wafers [134]. • For hydrophobic surfaces, bonding becomes efficient only above 600°C [135]. Beyond 800°C, the formation of Si-O-Si bonds is easier and is reinforced by a plastic flow of the oxide, which relaxes the internal stresses and causes the atoms of the two oxide layers to mix. However, most of the problems come from the formation of voids or from the incorporation of particles or contaminating adsorbates. 7.3. THINNING OF THE TOP LAYER

After bonding the two silicon wafers, one of the two wafers must be thinned down to the appropriate thickness required for the further manufacturing of devices. Different methods have been proposed, mainly grinding followed by polishing or etching. (5) Surface energy can be defined as the work of the adhesion forces per unit area when the plates are brought together from infinity to contact.

A Review of Buried Oxide Structures and SOI Technologies

201

10 m i n anneal in nitrogen

"a o—w^et oxides a — d r y oxides •-BPSC

lO m i n anneal o—in oxygen •—in nitrogen

A—PSG d)

CO

CO

Bond temperature (C°)

Bond temperature (C°) a)

b)

Fig. 2.44- Illustration of the dependence of the bond strength on the nature of oxides and on bonding and annealing conditions (after [136]). a) Surface energy is plotted vs. bonding temperature for bonds between wet oxides (300 nm, 3" Si wafers). Also shown are dry oxides (3" wafers), BPSG (4"), PSG (4").

b) Surface energy is plotted vs. bonding temperature for annealing in an N2 and O2 ambient (4" wafers covered with 300 nm wet oxides).

In the first method, most of the "seed" wafer is removed by grinding (which is a timeconsuming operation). The surface quality is then improved by a final polishing. The surface roughness obtained with this method is typically ±300 nm. When etching is used to thin the wafer down, an etch-stop layer (obtained by implantation or epitaxy) is often used to control the efficiency of the chemical etching solution, which dissolves the top silicon wafer. A second etching solution is then employed to dissolve the etch-stop. Surface roughness is much better in this case, typically below ±10 nm. 7.4. T H E HYDROGEN CLEAVAGE PROCESS (SMART-CUT^)

In the mid-90's, a new process, combining proton implantation and polishing, was proposed and is now referred^^^ to as Smart-cut® [137 a, 137 b]. The process, illustrated in Fig. 2.45, first consists in implanting hydrogen ions (with a dose ranging from 2.10^^ to 10^'^ ions/cm^) into the oxidized wafer below the oxide layer, before the bonding operation. The stopping range of the implanted protons defines a buried plane of microcavities. After performing a hydrophilic bonding at room temperature, the structure is submitted to a two-phase heat treatment. During the first phase (400-600°C), leading to blistering and flaking, the implanted wafer splits in two parts and a thin layer of monocrystalline silicon remains bonded to the second wafer. ^^^ Smart-cut is a trademark of the CEA-LETI (France).

202

J.L. Leray

HJW

jdLfi

wafer B

-<pr w a f e r

"Hoiev ^

A

h e a t treatment step 3

H* i m p l a n t a t i o n step 1

\No.^eT B wafer

A

|

cleaning • bonding step 2

wafer B

polishing step ^

Fig. 2.45 - Principle of the smart-cut process [137 bj.

It must be noted that the implantation depth is nearly linearly related to the implantation energy (100 keV gives 0.9 [im), so that the silicon thickness can be precisely and easily tailored [138]. The second phase (1100°C) aims at strengthening the chemical bonds. Finally, performing a fine polishing reduces the roughness of the top silicon layer. Compared with SIMOX, a significant reduction in processing time is obtained with the Smartcut® process, because the hydrogen implant operation takes much less time (by one or two orders of magnitude) than the oxygen implantation (of the SIMOX process). An additional advantage over the classical BESOI technique is that the complete thinning operation of the top silicon layer (usually a time consuming step) is now reduced to a single fine polishing. Moreover, one of the two initial wafers remains and can be re-used, which means that the Smart-cut® process, overall, only uses a single wafer for each produced SOI substrate. The Smart-cut® technique, marketed under the name Unibond™, is credited with a high throughput and is well suited for low-cost, high-volume productions. 7.5, DEFECTS AND PROPERTIES OF BESOI MATERIALS Basically, the defects encountered in the top silicon layer are the same as those of the starting bulk silicon. However, several additional types of defect can be introduced during the bonding operation (voids, mechanical strains, contamination of the BOX) and/or during the thinning process (dislocations, roughness, contamination of the top silicon) [101,139 a]. Voids in the BOX layer can be generated by particles present on the surface of one of the wafers before the two wafers are bonded (extrinsic voids), or induced during this operation by the out-gassing of surface contaminants (like hydrocarbons) and/or gas accumulation probably around small structural defects at the wafer surface (intrinsic voids). In any case, the size of the voids (from 10"^ to several millimeters in diameter in the most extreme cases) is strongly affected by the bonding conditions and by the temperature and ambient of the annealing process. Specific annealing procedures have been proposed to try to reduce the void density in BOX layers.

A Review of Buried Oxide Structures and SOI Technologies

203

It has been found that a high temperature annealing (900-1100°C) can eliminate intrinsic voids whereas only the smallest extrinsic voids decrease in size after an extensive aimealing at 1150°C[139a]. Another type of defect found in the BESOI material is due to the presence of foreign atoms that can induce trapped charges and defect precursors (later revealed by irradiation) at the internal bonding interface, or in the depth of the BOX film. Species such as carbon, oxygen, chlorine and fluorine have thus been measured in significant concentrations. Carbon and boron contaminations have also been frequently reported and can lead to a catastrophic degradation of the BOX insulating properties [139 b]. 7.6.

CHARACTERISTICS OF CURRENT BESOI WAFERS

BESOI substrates currently available (1996) exhibit characteristics which can be found in Table 2.5. 7.7.

OTHER BONDED MATERIALS

(SICOI)

Wafer bonding makes it possible to combine monocrystalline materials which in most cases could not be obtained by epitaxial growth or which could not be obtained in crystalline form by deposition. SiC on Si02 on Si structures have been obtained by wafer bonding, as reported in [140]. In this bonding approach, SiC is epitaxially grown or deposited on Si and the SiC layer is then oxidized before the bonding and the thinning operations. The advantages of SiC-based devices over silicon are due to a wider bandgap, a higher avalanche voltage, and a better thermal conductivity. These properties should allow device applications at high temperature and high power. Up to 1996, SiC wafers were limited to 2 inches in diameter due to the extreme difficulties of SiC ingot crystallization. With the bonding technique, SiC can be epitaxially deposited on 4-inch Si wafers [140]. Thus, the limitations in size due to the ingot process can now be overcome, opening the way to the mass production of SiC components. The SmartCut process, originally invented for silicon has also been applied to SiC, leading to the SICTRANSIT structure, comparable to UNIBOND but with SiC instead of Si giving birth to the SICOI structure, (i.e. "Silicon Carbide On Insulator" [141,142]). Gallium Arsenide has also been bonded to silicon by depositing a thin phosphosilicate glass (PSG) layer at 400°C using a CVD technique on the surface of a polished GaAs wafer [143]. Bonding occurs at 300-600°C under an applied voltage of 10-30 V across the 1-3 |im oxide layer. The phosphorous content in the PSG is adjusted to match the combined thermal expansion of GaAs and Si. The GaAs layer is then back-etched. This method tries to circumvent the difficulty of a direct epitaxial deposition of GaAs on silicon, which is possible but leads to a strained interface. In? has also been bonded to Si by using a similarly deposited Si02 bonding layer. After a back-etch and after etching a stress relief grid in InP, heterostructure InGaAs/InA^As has been deposited by Molecular Beam Epitaxy leading to the fabrication of HEMTs [144].

204

J.L. Leray

Type

Silicon thickness [A] (local roughness) RMS [A]

Buried oxide thickness [A]

Density of stacking faults in silicon [cm-2]

SOI Unibond 4 to 8 inches (S)

2050

Density of Density of dislocations pinholes in silicon in oxide [cm-2]

[cm-2]

Breakdown voltage [V] Breakdown field [MV/cm]

<0.1

4000

(100)

Crystalline Silicon On Glass (S)

1000-2000

SOI 4 to 8 inches (SB)

0.1 to 100 ^im (10 A)


(100) 0.0 to 3 ^im

<0.1

<1

<1

8 MV/cm

Table 2.5 - Comparison of commercial BESOI wafers (circa 1996): (S):from the SOITEC Company (FRANCE), (SB) .from the SiBOND Company (USA).

Recently, the idea of combining the ease of depositing Si02 on InP and the ease of making MESFETs in GaAs has been developed by using a thin buffer layer of intrinsic InP betwen GaAs and the deposited Si02 [145]. This has allowed the fabrication of GaAs MESFETs on Si02 (LOXI or "Layered-OXide-Isolation" technology), used as switches in the 19-GHz band. Excellent high-frequency characteristics have been obtained because the off-state capacitance is 5 times less than that of classical MESFETs on bulk GaAs. This is because the dielectric constant of Si02 (3.8) is lower than that of GaAs (13.1). In addition to III-V semiconductors, Ge has also been bonded to Si, and Si to fused quartz, using a buffer Si02 layer [144]. Generally speaking, bonding must take into account the thermal expansion of the bonded wafers. After high-temperature annealing, stresses are generated by the cooling-down step, which can at least induce defects and dislocations in the materials. Figure 2.46 shows the thermal expansion coefficients of some materials around 1000°C. A good fit is obtained between silicon (used as a supporting medium) and materials such as SiC and A ^ , while a reasonable fit is possible with GaAs. On the vertical axis, one can see the superior thermal conductivity of SiC and BeO, making these materials interesting for applications where thermal power must be extracted, such as in power devices. Interestingly, with this concem in mind, the properties of silicon-on-diamond structures have also been investigated using wafer bonding [146]. The authors tried to solve the problem of transistor self-heating (caused by the poor conductivity of Si02) by using deposited polycrystalline diamond, whose thermal conductivity is ten times larger. The temperature increase measured with test diodes was found to be 3 to 4 times less with this SOD ("Silicon on Diamond") structure.

A Review of Buried Oxide Structures and SOI Technologies K Thermal Conductivity (W/m.^C)

300 750

BeO •

SiC •

200

205

AIN Si

150 100 50 L B N a.Si02:K#lW/m.*^C ^

MgO GaAs

Si3N4 • I

a-A1203 YSZ

I

2

3

4

5

6

7

8

9

a-quartz : K # 7 W/m.^C J

I

I

10

I

1 ^ li

15

Thermal expansion (lOV^^C) Fig. 2.46 - Thermal properties of basic materials suited for bonding (for crystalline materials values have been averaged) x axis: thermal expansion coefficient at 1000°C. y axis: thermal conductivity at room temperature. 7.8. NOVEL STRUCTURES PERMITTED BY WAFER BONDING

Wafer bonding should also make the 3D integration of active layers possible [147, 148]. Since 1986, some CMOS circuits have been designed using inverters obtained from stacked PMOS and NMOS transistors, each of them manufactured separately on two different wafers (ELVIC method: Elementary Level Vertically Integrated Circuit [149]). In this new approach illustrated in Fig. 2.47, the two wafers, capped with a polyimide layer, are bonded together and the transistors are wired by means of A^/Au vias. The wafer bonding method can be generalized to circuit bonding, thus allowing to double the integration density or to combine two different types of circuit. Recently, this approach has been successfully used to design and fabricate 64-Mbit Dynamic Random Access Memories (DRAM's) [150]. Further improvements in integration density could come from the development of such multiplestacking processes. UPPER UYER

IJDWERUYER

OPTICAL INPUT

t)

OCH LOWERI UYER

0 a)

b)

(KOELECTRONICLSI

OPTICAL OUTPUT SI DIGITAL SIGNAL PROCESSOR LSI

C)

Fig. 2.47 - Fabrication of 3D structures using bonded wafers (after [151]): a) Principle, b) Cross section of a structure after wafer bonding showing the 3D integration of active layers. c) A typical 3D association of functions.

/.L. Leray

206

This process differs strongly from the ZMR 3D process, in that here, each layer is fabricated and tested independently, whereas ZMR imposes the processing of each new layer on top of the previous one, including the delicate recrystallization step. The overall process yield should thus be better here than with ZMR. Further improvements in integration should come from repeating the process after thinning the upper layer, and bonding again a third active layer, and so forth. 8. APPLICATIONS OF SOI STRUCTURES TO NOVEL SMART STRUCTURES It becomes clear from the previous sections that SOI structures offer many advantages, not only during the fabrication process but also after fabrication, when the device is operated. The advantages introduced during the manufacturing process come from the etching selectivity that exists between semiconductors and insulators, and from the ability to bond hydrated surfaces. Novel structures can thus be produced more easily (e.g. optical and mechanical devices, sensors). Some of them are reviewed in this section. Merging these devices with integrated electronics can greatly improve the performance of the hybrid components thus obtained. In this case, the term "smart" device is used. The SOI structure makes it possible to separate the various processing steps and to isolate the fimctions for a better performance when noise interference must be reduced or breakdown voltage improved. A few examples are given in this section. 8.1. APPLICATION TO BURIED OPTICS

The integration of optical and electronic components, including signal treatment for integrated optoelectronics, requires optical waveguiding. For that purpose, the large difference in refractive index between Si (n = 3.5) and Si02 (n = 1.5) can befixUyexploited. Glass with n> 1.5 Si02 n=1.5

SiGe (n=4-4.3

Bulk Silicon n=3.5 b)

a) Optical loss demonstrated atA,=1.3 |Lim :


c)

<1 db/cm (with optional Si02caping)

2 to 5 db/cm

0.5 to 2 db/cm (with SOI, SIMOX type)

Fig. 2.48 - Illustration of some silicon-based optical waveguides working with different contrasts of refractive index (after [152], modified).

A Review of Buried Oxide Structures and SOI Technologies

207

The simplest waveguiding structure consists of a silicon layer confined between two silica layers (or between air and silica) as illustrated in Fig. 2.48. In this case, the photon energy must be less than the silicon energy band gap (1.12 eV). The SOI structure is well suited for that purpose, since the BOX can act as a spacer plane between the active silicon guide and the mechanical holder (silicon substrate) [152]. The BOX layer must be sufficiently thick (X/2 to A./3) to minimize the losses due to the evanescent coupling of light through the oxide into the silicon substrate, as illustrated in Fig. 2.49. The minimum thickness of the silicon waveguide is given by the coupling conditions at the exit plane of the guide [152], and is of the order of the photon wavelength (X). Another important parameter is the roughness of the Si-Si02 interface: a mean roughness amplitude of 30 nm can lead to an additional optical loss of about 1 db/cm at A, = 1.3 |am [154]. The guiding of optical waves, with X = 1.3 |Lim, can be exploited in SIMOX wafers. This makes it possible to envisage the integration of silicon-based optoelectronic devices or the design of an optical network on a chip allowing signal treatment over a wide bandwidth, (similar to what is being done on GaAs/GaA^As or InGaAsP/InP). Applications based on Si02-Si take advantage of the excellent interface uniformity, and of the presence of a natural oxide thickness of 0.4 |j,m which provides a single-mode waveguide propagation at A. = 1.3 |uim. In this range of silicon thickness, the attenuation of the first mode has been found to be 4.7 db.cm"!, making this structure attractive for further applications [154]. Loss (dB/cm) tOQQOO

Fig. 2.49 - Optical Loss due to leakage into the substrate for the simplest SOI waveguide (after calculation of [154]), for a wavelength of 1.3 jum.

Buried oxide thickness (^im)

Active optical structures have been discussed in [152] along with the possibility of creating an electro-optic light modulator based on the Mach-Zehnder principle (Fig. 2.50) and using the dependence of the silicon refractive index on the electron carrier density. This carrier density is in tum determined by the current injected by the nearest pn junction. Another optical modulator, based on a Fabry-Perot resonant cavity, has been described in the literature [155] and also uses a diode phase modulator placed inside the cavity. For this application, the buried Si-Si02 interface acts as a cavity mirror and the BOX thickness is chosen equal to 0.2 |j,m to optimize the reflectance at X = 1.3 |Lim.

208

7.L. Leray

Modulator side A

OV

I input light

^ Modulator side B

output light

I

:

\ 3J

••taHP

OV

^•••••"Tn—^

Or) I

*Si02 -X-

(»>.

a^

AD dimeasioBt in ion

F/g. 2.5(? - Mach'Zehnder modulator consisting of two pn junctions on a BOX structure. The carrier density is modulated by the forward bias and influences the silicon refractive index (Kerr effect). The two beams interfere at the output (after [153]). a) Top view of the Si-based Mach-Zehnder modulator, b) Cross section of the Ml modulator. 8.2. APPLICATIONS TO MICROMACHINES

Since the early 90's, the field of micromachining has been in full expansion. This field is based on the application of etching and epitaxy techniques, used in microelectronics, to fabricate mechanical or mixed mechanical/electrical microstructures. The concept has been applied to actuators and sensors (mostly motors and accelerometers), although pressure gauges, pumps, magnetometer, and chemical sensors have also been considered [156]). The dual aspect of Buried Oxides and SOI layers can be efficiently exploited due to: • the high etching selectivity between silicon and silicon dioxide (e.g. 500:1 for SIMOX in KOH), • the monocrystalline structure of silicon in most of the SOI structures, allowing specific electric properties, compared to polycrystalline silicon, and specific etching profiles (especially in wet etching). Figure 2.51 illustrates the structures obtained with a SIMOX wafer after etching off the buried oxide under silicon cantilevers. In this structure, cantilevers are the seismic mass used in the accelerometer. The advantages of using silicon cantilevers come from the possible control of the temperature dependence, and the possibility of integrating both a silicon amplifier and a seismic device on the same chip, which results in a smart sensor. The etching selectivity between silicon and silicon dioxide is essential in this process. 9. RADIATION EFFECTS IN BURIED OXIDE STRUCTURES When SOI devices are irradiated, the buried oxide contributes to radiation effects. Radiation not only generates electron-hole pairs but also generates bulk and interface traps in this additional oxide layer. However, these radiation effects can be minimized as explained next and overall, SOI devices display excellent radiation hardness.

A Review of Buried Oxide Structures and SOI Technologies

209

^t J¥^

Fig. 2.51 - Example of structures used in microaccelerometers consisting of monocrystalline silicon cantilevers (courtesy ofLETI). 9.1. CHARGE TRAPPING IN DIELECTRICS AFTER IONIZATION

The irradiation of an insulating layer generates electron-hole pairs in the material. If no electric field is applied, the pairs recombine and no current flowsf^). If an electric field is applied, some pairs are separated and the carriers can be collected at either electrode unless they get trapped during their drift and diffusion. When a positive bias is applied to the gate of a MOS structure being irradiated, some of the generated holes are driven to the Si-Si02 interface, while electrons are swept toward the gate [157 a, 157 b]. During their drift toward the electrodes, the holes can get trapped on centers (supposed to be electrically neutral before irradiation), which leads to the buildup of a positive charge in the oxide [158]. Carriers, which have not been trapped, reach the oxide interfaces and can be swept away at the collecting electrodes. The presence of holes at the Si-Si02 interface has been extensively studied and their roles invoked in the formation of interface traps [159]. 9.2. PARASITIC TRANSISTORS DUE TO CHARGE TRAPPING

9.2.1. Case of SOI structures To remain general, let us take the case of a MOS transistor in a SOI technology. Once a SOI structure is irradiated, charge trapping in the buried oxide gives birth to a parasitic effect, called "back parasitic transistor" as represented in Fig. 2.52. A leakage current is usually observed in n-type MOS transistors, due to an electron conduction channel, which shows that the trapped charge is overall positive [160].

(7) If we disregard carrier trapping.

7.L. Leray

210

Polysilicon gate Gate oxide

N+ diffusion

Back conduction

^ S ^ i ^ # ' - 't:'^'"^ '*^V' ^' "^'-" ^ +

+ ^

Silicon substrate

Fig. 2.52- Illustration of a radiation-induced back transistor in a SOI structure (after [11]).

J

Charge trapping not only generates a back-gate FET effect but also a lateral FET effect and often also a parasitic bipolar transistor effect (Fig. 2.53). The improvement brought about by the SOI technology over bulk CMOS technology is that these parasitic structures are located in the silicon island instead of being distributed in the bulk or at the surface of the silicon chip. On the other hand, as noted above, a new parasitic FET transistor appears due to the buried oxide, the underlying substrate acting as a back gate [161]. UOS/S0\ Lateral Cross Section

G

GaU gate oxide \ ^ active silicon %

Equivalent Circuit : Lateral MOS

/:te

Main MOS

LATERAL UOS

buried oxide Silicon Substrate

Substrate

D

Buried UOS (back-gate)

Fig. 2.53 -Illustration of parasitic elements encountered in a MOS/SOI or MOS/SOS transistor, a) The five regions of the transistor, b) The corresponding parasitic elements [161].

9.2.2. Case of SOS structures In SOS devices, due to the sizeable thickness of the alumina substrate, the back gate can be considered as being at an infinite distance. However, the electrostatic influence of the trapped charges does not vanish, when these are located close to the silicon/alumina interface and a leakage current is observed due to a back-gate MOS transistor. Since leakage after irradiation is only observed in n-type transistors, one is led to assume that the trapped charges are positive. 9.3. SPECIFIC RADIATION EFFECTS IN SOS

STRUCTURES

In § 4.2.2, we mentioned the existence of a sharp peak in the interface state density at the Si/sapphire interface (culminating at S.IO^^ cm-^ eV"l at E^ - 255 meV). This peak tends to pin the Fermi level at this interface and, because of that, some authors have suggested that the 500-A-thick disordered layer behaves as an n-doped layer whatever the type of the upper silicon film may be.

A Review of Buried Oxide Structures and SOI Technologies

211

+4

b

+3

It

GROWTH RATE 0.3Mni/MIN. 0.6 Mm/MIN. l.Ojum/MIIM.

H-2

if

PRERAD POSTRAD IRRADIATION: O • 1 Mrad (AI2O3) ^ A Co^y-RAYS D m UNDER 10*V/cm

IS +1 s

o II

0

\ \

POSITIVE CHARGE NEGATIVE CHARGE

-1 h

Fig. 2.54' Illustration of the dependence of the radiation-induced trapped charge, encountered at the silicon-sapphire interface (measured before and after a l-megarad(Si) irradiation), on the growth temperature and the growth rate of the epitaxial silicon layer (after [54]).

£ z -2

960°C 970°C 980°C SILICON GROWTH TEMPERATURE-

However, the low mobility of the carriers in this layer renders negligible their contribution to the electron current flow of n-type MOS transistors. This could also explain why one never observes radiation-induced leakage currents in p-type MOSFETs, since this peak in interface states acts as a screen for any negative trapped charge located in the sapphire. In a specific study [54], the density of charges trapped in the sapphire after irradiation was shown to closely depend on two simple process parameters: the silicon growth temperature and the growth rate itself. The results of this important study, displayed in Fig. 2.54, show that a deposition at 975°C with a growth rate of 0.3 |xm/min in silane, minimizes the trap density. 9.4. SPECIFIC RADIATION EFFECTS IN S I M O X , B E S O I AND FIFOS STRUCTURES The radiation-induced charge trapping properties of the oxides described in the previous sections have also been investigated. The goal of such an investigation is of course to compare the different oxides and, as we did for SOS, try to find a common trend. The method used to extract the trap densities and capture cross sections reported in Table 2.6, has been described elsewhere [162-164]. It basically consists in fitting a theoretical model for the variation AV^^ of the threshold voltage of the MOS device, caused by the presence of the oxide-trapped charge, to experimental data obtained in the limiting cases of strong positive (hole trap parameters) or negative (electron trap parameters) bias applied during irradiation.

212

J,L, Leray

It has been shown, theoretically, that AV^^ saturates exponentially with irradiation dose [this volume, Chap. 11]. The saturation values of AV^^ yield the equivalent trap density at the Si-Si02 interface, while the slopes of the curves yield the capture cross section of the trap. Due to large differences in the capture cross sections for holes and electrons, hole trapping dominates at low dose (typically below 1 Mrad(Si02)), whereas electron trapping dominates at high dose (above 1 Mrad(Si02)). Electron trapping is only revealed when irradiation takes place while a large negative applied bias is applied to the substrate (back-gate), i.e. when the generated electrons, separated by the high electric field, are driven to the Si02-Si interface. In this case, electrons trapped in the vicinity of the interface induce a measurable image charge in the silicon substrate. When irradiation is performed while a positive field is applied to the back-gate, the electrons, which escape initial recombination, are swept toward the gate. Even if they are trapped there, the electrostatic influence of this negative trapped charge may not be large enough to induce a measurable threshold voltage shift. The behavious of various types of oxides are compared in Fig. 2.55. Table 2.6 summarizes the data obtained with the method explained in Chap. 11. Data originate either fi-om a literature survey (in this case, raw data have been reinterpreted in accordance with the definition of parameters and method used), or come from original studies [165 a &b]. A correlation clearly exists between the trapping efficiency and the "annealing" temperature, which, depending on the process, can be that of the: • Ultra-High-Temperature Anneal necessary to ensure the uniformity of the SIMOX oxide, • complete oxidation and densification anneal necessary to ensure the stoichiometry and the uniformity of the FIFOS oxide, • silicon recrystallization step for the ZMR process, • bonding and densification steps of the oxides for the BESOI process. The higher the "annealing temperature", the higher the trapping efficiency. Up to 1100°C, the hole trap density increases with temperature, which is consistent with the mechanisms proposed for the general case of thermal oxides (see Chap. 11). Above 1100°C, appears in some cases a large electron trap density, whose origin is still not fiiUy understood. The amount of trapped charge and its influence on the device depend not only on the trap density, but also on the electric field existing in the oxide, on the location of the traps, and on the values of the various trapping and recombination cross sections (a review of trapping mechanisms can be found in Chap. 11). The large values of trapping efficiency given in Table 2.6 have been obtained for very severe substrate biasing conditions which are never encountered in practice. Under normal biasing conditions, the radiation hardness of SIMOX structures may be excellent [10] since there exists a compensation mechanisms between the electron traps and the hole traps (the generated electrons neutralize the trapped holes and vice versa [157 b]. This may not be the case for technologies which do not give birth to electron traps.

213

A Review of Buried Oxide Structures and SOI Technologies Hole Traps

1 BOX type

Oxide Thick ness T ox

Standard SIMOX (C) [166]

3800

Standard SIMOX (C)

3800

A

A

Electron Traps

Trapping cross section

Density of traps

Trapping efficiency

Trapping cross section

Density of traps

^h

%

""k^th

^e

N,e

_2

Oxide process Trapping efficiency

Highest Temperature

Comments

""e-^te

2

.2

cm''

cm-^

0.2

5 xlO-'"

Ixl0l2

0.025

1300°C

Prototype

1.4xl0l2

0.24

2 xlO-"*

I.lxl0l2

0.022

1300°C

Prototype

Manufactured by SOITEC

cm^

cm''

10x10-1"^

2xl0l2

17x10-1"^

[167] Standard SIMOX (C) [164]

4000

5.2 ±1.3 10-14

1.3 ±0.4 10l3

0.68

5.4 ±3.3 10-15

2.5 ±0.3 10l2

0.013

1320°C

A

ITOX SIMOX (C)[164]

1215

3.7 ±1.7

6.6 ±2.2 10^2

0.63

7.9 ± 3.3 10-15

2.4 ± 0.3 1012

0.02

1320°C

ITOX SIMOX (C)[164]

950 A

2.8 ± 0.2 10-13

4.3 ± 0.2 10l2

1.2

15 ± 1 0 10-15

2 ±0.2 1012

0.03

1320°C

Low Dose SIMOX (C) [164]

800 A

2.9 ±0.3 10-13

2.7 ±0.3 10l2

0.78

28 ± 1 6 10-15

7.1 ±0.1 1012

0.02

1320°C

3.10^2

0.36

5.10-1"

1.1012

0.05

1100°C

Densification atllOO°C [119]

5 xl0l2

0.025

(0)

(0)

(0)

900°C

"rad-hard dielectric"

FIFOS (C) CNET samples [166)] BESOI [168]

A

1.2 12.10-1^ nm i 4000

A

0.5 xlO-14

J

bonded at 900°C BESOI UNIBOND [169]

4000

A

ZMR(C) CNET Samples [165 a &b]

1.5 fim

Gate oxide (C) (thermal, wet) [162]

175 A

Gate oxide (C) (thermal, dry) [160]

450 A

6.3 ± 0.2 10-14

1.5 ±0.2 10l3

0.09

35 ± 1 10-15

0.03

9.2 ±0.3 loii

1420°C

10l2

1.3 10-13

3.3 lOll

0.04

(0)

(0)

Thermal oxide bonded at llOO^C

(0)

900°C

For comparison purpose

Thermal 1000°C, dry [15]

4000

lOSO^C, dry [15, 170]

4000

0.5 10-13

5 1012

0.25

(0)

(0)

(0)

1000°C

For comparison purpose

5 10-14

5 1012

0.25

(0)

(0)

(0)

1000°C

For comparison purpose

14.10-14

5.1012

0.60

(0)

(0)

(0)

1050°C

For comparison purpose

A

A

1

214

J.L. Leray Hole Traps

1050°C, dry +UHTA 1320°C [15, 170]

4000

Field oxide (thermal, wet) [157 b]

4000

Electron Traps

36.10-14

1.6.1012

0.57

2.8.10-1'^

1.2.1012

0.035

1320°C

For comparison purpose

1.8 10-1^

8.4 10l2

1,5

(0)

(0)

(0)

950°C

For comparison purpose

A

A

Oxide process

Table 2.6 - Collected data of electron and hole traps encountered in the main varieties of buried oxides and revealed by X- or gamma-rays irradiation. Letter (C) means that the data has been obtained experimentally by the author or his colleagues. vsrsustiasdiiing racfaticn RPOS 2I\/R

OETSarpleB CTETSanples

AUbiiiedM36 f450V,

BESaV\fergB]L0ct93 NRL Hardened Rooess Steam850PQ Bonded at goCfC

BE9aQ4iin

a) ACfcx = -OoxAVt

AQQK

RPOScrersenrte Z^/R

+2id^

OCTSBopleB

Tterrel oxide

^

09 NET m S T I VE ai^«GE HpJETR^^PRNG

BggQjWhnoaroctgs NRL HwdBOBd RooBBS Steem86(rC, BmdBdatgocrc

BE9a0.4 3IVOK 0.38 tiTi -1.5l\Mcm

t

-1l\/M'cm

-f500kV7cm +1 IVK/7cm

Sib^trstetia RPOS 2NR

r^ET NEQOJIVECH^VFGE aHIHFCNTFyvPRNG

b) Fig. 2.55 - Dependence of the radiation-induced trapped charge encountered at the silicon/BOX interface, after a 1 Mrad(Si) irradiation, for several types of oxides, on the field applied during irradiation: a) expressed in voltage, b) converted into charge density.

A Review of Buried Oxide Structures and SOI Technologies 9.5. ADDITIONAL COMMENTS ON RADIATION EFFECTS IN SOI MATERIALS

9.5.1. SIMOX buried oxides At first, the improvements of the SIMOX technology were limited to improving the quality of the top silicon film. Little attention was paid to the quality of the buried oxide until device performances were sufficiently enhanced. It then became clear that the properties of a buried oxide are very different from those of thermal oxides, and can greatly influence the device manufacturing yield, as well as the radiation-induced behavior. The nature of the charge build-up in SIMOX buried oxides has thus been extensively studied, and different characterization techniques have been reported in the literature: X-irradiation [171] or yirradiation[172]; ultra-violet illumination (UV or VUV at 10.2 eV) [173]; and charge injection (holes injected by corona discharge) [174]. Recent studies have confirmed differences between the radiation-induced trapping behavior of thermal oxides and that of the SIMOX buried oxide [171, 172, 175-177]: • In thermal oxides, hole trapping at the interface seems to dominate, whereas in buried SIMOX oxides, results can be interpreted in terms of large bulk trapping. Additionally, it has been widely shown that large electron trapping can also occur in X-ray irradiated SIMOX oxides [14, 157 a]. • Furthermore, SIMOX buried oxides show no sign that interface states are created during irradiation unless very high ionizing doses are used [169, 179]. • Electron paramagnetic resonance measurements reveal an important creation of paramagnetic defects in SIMOX oxides submitted to UV, X-or y-irradiation [171-173, 180]. The density of E ^ centers grows linearly with irradiation dose, and does not exhibit any saturation, at least up to a dose of 200 Mrad (Si02). This result suggests the presence of a large quantity of (defect) precursors (estimated at around 10^^ cm"^) [171, 173]. Moreover, the creation of paramagnetic defects is greatly enhanced by applying an electric field across the oxide during irradiation, whatever the sign of the applied field [178]. Etchback measurements of irradiated samples reveal that the E' centers are generated uniformly in the bulk of the SIMOX oxide [173,181]. Charge injection also generates EL centers, as well as a new type of paramagnetic defect, called the E*5 center [174, 182]. This center differs from the classical E' center, since the spin (unpaired electron) is delocalized in this case. The model proposed to explain its microscopic structure is based on the existence of clusters of five silicon atoms in the oxide, sharing the same unpaired electron. E'5 defects seem to be only observable after a selective hole injection in the oxide, and not after X-irradiation, nor after UV or VUV-illumination. These two types of E' centers, created by hole injection, become diamagnetic after electron injection. Both centers (E*5 and E y) seem to be positively charged when paramagnetic.

215

y.L. Leray

216

The E'5 center is presently believed to have an electron capture cross-section larger than that of the E' center, which would explain why it is not observed after irradiation. In this case, electrons and holes are created simultaneously, and the E'5 readily captures an electron, and thus becomes again neutral and diamagnetic. Electrical measurements of the net trapped charge in the buried oxide do not agree with EPR measurements [171, 183]. The net trapped charge saturates with the irradiation dose, and even in some cases (negative bias during irradiation) reveals the buildup of a net negative trapped charge at high doses. Nevertheless, some characteristics are common between the trapped charge and E' signal measurements: i) both the magnitude of the trapped charge and the EPR signal increase when the appUed electric field increases, whatever its sign; ii) the evolution of the E'y signal and that of the midgap voltage shift are similar during an isochronal anneal at zero bias. A correlation is found between the calculated surface densities of hole traps and the BOX thickness, as illustrated in Fig. 2.56. On the other hand, the density of electron traps does not depend on the oxide thickness, down to a thickness of 100 nm. Below this value, the density decreases noticeably. The simplest interpretation is to suppose that the electron traps are located in the interfacial areas (less than 100 nm away from the silicon interfaces), as opposed to the hole traps which are distributed in the bulk. This result agrees well with recent observations and with a model linking the origin of electron traps to the ultra-high temperature treatment used in SIMOX oxides [105, 181]. The high temperature anneal of an oxide film confined between two silicon layers is shown to result in the degradation of the sandwiched oxide, due to the creation of oxygen-vacancy defects. The physical mechanism producing these defects is related to the out-difiusion of oxygen from the oxide, caused by the oxygen solubility in the silicon layers at this temperature [105, 181]. The density of O interstitials in Si is far from its solubility limit at the anneal temperature, and represents the driving mechanism for this diffusion (see Chap. 11, in this volume). 14 T

10

Electron Traps 10

13 Fig. 2.56-Correlation found between the density of trapped charges at 1 Mrad (SiO^ and the SIMOX oxide thickness [184].

12 10 11 10 10

10 Tox (Angstroem)

10

A Review of Buried Oxide Structures and SOI Technologies

111

This depletion should occur at each interface of the buried oxide. The authors calculated the distance from the interface at which oxygen is gettered during the ultra-high temperature anneal, and found it to be 120 nm. This distance is comparable to the distance at which the electron trap density is found to be lowered, which leads us to propose that the interfacial locations of electron traps could likely be correlated to this oxygen depletion. On one hand, the exact nature of the defect responsible for this negative charge trapping and its relation with the oxygen out-diffusion still remains unclear, although we note that the oxygen vacancy itself has been proposed as an electron trap [185]. On the other hand, the areal density of hole traps is shown to be proportional to the oxide thickness, which confirms the existence of a uniform bulk distribution of hole traps. For standard SIMOX oxides this was confirmed by the study of AV^^ using etch-back experiments applied to the oxide trapped charge as well as to E' defects [157 b]. Modifying the oxygen implantation conditions (oxygen fluence and energy) had no major effect on the trapping properties of the material. In all these SIMOX materials, the electron traps are present in each type of SIMOX. Properties related to holes are independent of the oxide thickness, in the sense that the bulk hole trap density seems to be constant for the material. It confirms that the most damaging factor of the process is the annealing step (temperature and gas ambient) performed on a confined oxide layer. It is the only step that the various SIMOX processes have in common, and it degrades any confined oxide structure (even a thermal oxide, [167]) in a similar way, i.e. by the out-diffusion of oxygen atoms from the oxide, and the generation of oxygen-vacancy related defects. 9.5.2. BESOI buried thermal oxides The behavior of BESOI buried oxides under irradiation is also reported in the literature. Since these insulators are at the origin thermal oxides, one would expect them to exhibit exactly the same charge transport and trapping properties as the original layers. Results, however, show that this is not always the case. It is true that some properties of standard thermal oxides, such as charge transport properties, are still found in BESOI materials. However, the presence of the bonding interface in the oxide greatly modifies the charge trapping properties. Moreover, the use of a high temperature bonding or post-bonding anneal step also contributes to the observed differences. The presence of the intemal bonding interface and its location in the oxide is the key parameter influencing the radiation-induced properties of the BESOI structure. This bonding interface is usually of a relatively poor quality, (e.g. a process-induced fixed negative charge has been found at this interface before irradiation [134, 186]). After irradiation, this interface can efficiently trap both types of carriers [176, 157 a, 188]. Depending on the position of this interface within the buried oxide, the electrostatic influence of its trapped charge can have different effects on the transistor located above. These trap densities at the bonding interface are specific of the BESOI buried oxide, and superimpose on the "natural" trap densities

218

7.L. Leray

located at each Si-Si02 interface (at the top silicon film/oxide and oxide/bulk-silicon interfaces). This material, made from thermal oxide, can thus exhibit deep trapping of both holes and electrons, while typical soft thermal oxides only display hole trapping. The presence of water due to hydrophilic bonding could explain the water-related deep electron traps found in the BESOI buried oxide at the bonding interface [187] both, with and without post-bonding anneal. High temperature anneals on such Si-Si02-Si sandwich structures have been shown to induce a chemical reduction of the buried oxide [105, 167, 176]. This is of course the case in BESOI materials as well, and such annealed structures, while having less macroscopic defects (such as voids at the bonding interface), then display an enhanced quantity of oxygenvacancy-related defects. Their radiation-induced behavior tends to look like that of SIMOX buried oxides [167, 176]. The same types of defect precursor (oxygen vacancies) are induced in the material, and the same defects are encountered, regardless of the method used initially to fabricate the oxide. 10. CONCLUSION 10.1. THE FAST EVOLUTION OF BOX TECHNOLOGIES

Table 2.7 summarizes the fast evolution of BOX technologies and illustrates the impact that progress in materials has had on this evolution. At the end of the 70's, the SOS technology dominated the market due to well-established positions gained in the late 60*s. Although many new technologies have emerged since then, and although SOS structures still feature a large density of defects, the SOS technology is still used to manufacture components for satellites. This is due to the high degree of skill of existing manufacturing lines and to the fact that SOS devices meet strict reliability standards. SOS technologies may generate new interest for very high frequency applications [41]. In the early 80*s, the SIMOX technology emerged due to the excellent physical and electrical properties of this material and to the wider availability of industrial ion implant machines [189]. Between 1985 and 1992, the defect density in the top silicon surface was reduced at the constant rate of one decade per year and has now become comparable to that of bulk silicon [12]. SIMOX is widely used for advanced applications making use of very thin (30-50 nm) silicon films. Wafer bonding emerged also in the 80's and is currently fast developing. It will allow the production of large-size wafers, provided the difficulties encountered with the thinning techniques and the interface roughness can be overcome. New wafer manufacturing companies keep appearing on the market. Wafer bonding, already being used for commercial devices [127 b, 190, 191], also offers excellent possibilities for the production of 3D structures.

A Review of Buried Oxide Structures and SOI Technologies

1 DATE

219

MAIN ACHIEVEMENTS

COMMENTS

30's

The MIS transistor (historical patent)

Semiconductor processing is not mature enough: purity of materials is the most serious handicap

40's-50's

The Shockley MOS device

Oxide processing is not mature enough: oxides are contaminated and electrically unstable

60's

Monocrystalline Silicon On Sapphire

Heteroepitaxy. Demonstration of the Silicon On Insulator Concept

Amorphous Si on glass

Thin-Film Transistor

ZMR by laser beam

Recrystallization of silicon on Si02

ELO

Seeded lateral growth of Si on Si02

SIMOX

Si02 is produced by implantation of oxygen

1

FIFOS

Si02 is produced by directed selective oxidation

1

85

ZMR by Strip Heater BESOI

| 1 |

90's

Ultra-thin SIMOX

Recrystallisation of Si across the full wafer Surface bonding of wafers by hydrophilization Applications to sensors and micromachines Silicon layers as thin as 50 nm can be produced with small roughness on 80-nm buried oxide Vertical bonding and interconnects Generalization of SOI for 0.1 micron transistors?

70's

80's

95 2005's

3D? BESOI

| | 1

Table 2.7 - Evolution and main achievements in the field of SOI structures.

In the domain of micromachines and sensors, wafer bonding offers a unique way of making hollow or sealed cavities [192], with or without added diaphragms. Applications include pressure transducers, microvalves, liquid shear-stress sensors, resonant load cells and accelerometers [193]. Figure 2.57 illustrates progress made by the various BOX technologies using "circuit complexity" as a performance criterion. Other criteria such as radiation hardness, temperature resistance, and 3D packing density could also be used. (Similar criteria in the field of micromachines are not easy to define). Figure 2.57 clearly shows that CMOS/SOI will become a mature technology in the late 90's and will make it possible to solve the problems associated with the manufacturing of 64-, 256- megabit and 1-gigabit DRAMs [194] at the tum of the century. 10.2. PERSPECTIVES

The versatility of BOX structures allows applications in many innovative devices such as: • mixed-mode analog-digital circuits making use of bipolar, junction field-effect (JFET), and CMOS transistors merged on the same chip, • "smart-power" circuits, i.e. circuits associating medium voltage transistors and integrated CMOS drivers, • high temperature circuits, • sensors, actuators and micro-machines.

220

/.L. Leray

1993-95

Fig. 2.57 'Learning curves of the main SOI technologies. The number of transistors per chip is used as an indicator of how mature the technology is [195].

i BESa

Sum 4um Sum 2um

t I I I I

1000A 2000 3000 isOGA 3800i

300 um..

.MiJCi3BiJl.i

Fig. 2.58 - Illustration of the ranges of application of the SOI technologies, obtained by plotting the buried oxide thickness and the silicon film thickness on the X and Y axis, respectively. The mapping lets us clearly identify which structure is best suitedfor a given application [195].

A Review of Buried Oxide Structures and SOI Technologies

221

Figure 2.58 illustrates a two-dimensional classification of SOI technologies based on two criteria: thickness of the buried oxide and thickness of the silicon film. This classification should enable designers to select a SOI technology for a given application. It shows that there is no unique answer regarding the future of BOX and SOI technologies [195]. Although the major trend in microelectronics today is to go toward submicron technologies, other integration techniques are currently emerging. Most of them use the buried insulator concept, either for process simplification, or for electrical insulation or as an active layer contributing to the transistor field-effect. Examples are: integrated micro-machines and sensors with built-in electronics as well as mixed electronic and optical devices on silicon wafers. Generalized multilevel wafer bonding could also substitute for the current technologies used for Multi-Chip Modules (MCM). Potential applications of BOX technologies are numerous and depend primarily on the properties of the starting material. The use of buried insulators could open the era of "Anything On Anything". 11. ACKNOWLEDGEMENTS The author would like to thank Dr. Roderick A. B. Devine for his early encouragement to write this paper, and Dr. Gerard Barbottin for his help in reviewing this text and improving its clarity and coherence. Drs. Akos Revesz and William L. Warren contributed also many useful comments on many subjects. The matter treated in this chapter results also in a large part from the good work done with experts of the Grenoble Area in FRANCE these last twenty years: Yvon Gris, Michel Montier, Joseph Borel, Gerard Borel, Guillermo Bomchill and Michel Haond, Jean-Pierre Joly, Michel Bruel, Claude Jaussaud, Pierre Felix, Andre-Jacques Auberton-Herve, Jean-Michel Lamure, Jacques Margail, Bemard Aspar. My colleagues JeanMarie Chariot, Eric Dupont-Nivet, Olivier Flament, Veronique Ferlet, Philippe Paillet also contributed as colleagues to the data given in this work. Their help is sincerely acknowledged. Special thanks are due to the editors G. Barbottin and A. Vapaille, who carefully reviewed this chapter and suggested many improvements in presentation. I would like also to apologize to those workers in the SOS-SOI field whose publications or work I have inadvertently missed. So many stars in the Sky, so many SOI processes in this World, so few days on Earth!

222

7.L. Leray

12. REFERENCES [I] [2] [3] [4] [5] [6]

[7] [8]

[9] [10]

[II]

[12] [13] [14] [15]

[16] [17] [18] [19]

[20 a]

J.E. Lilienfeld, US Patent 1,745,175 "Method and apparatus for controlling electric current" (filed in 1926, issued in 1930) J.E. Lilienfeld, US Patent 1,900,018 "Device for controlling electric current" (filed in 1928, issued in 1933), US Patent 1,877,140 "Amplifier for electric current" (filed in 1928, issued in 1932) O. Heil, German Patent 439,457 March 2, 1934 W. Shockley: Electrons and Holes in Semiconductors (Van Nostrand, 1950) W. Shockley and G.L. Pearson, "Modulation of conductance of thin fihns of semiconductors by surface charges" Phys. Rev, 74 (1948) 232 J.L. Leray, E. Dupont-Nivet, P. Lalande, O. Musseau, Y.M. Coic, A.J. Auberton-Herv6, M. Bruel, C. Jaussaud, J. Margail, "From substrate to VLSI: investigations of hardened SIMOX without epitaxy for dose, dose rate and SEU", IEEE Trans, on Nucl ScL, 35, n°6, 1355, December 1988, following the International Conference on Nuclear and Space Radiation Effects on Electronics, Portland, Oregon, July 1988 D. G. Platteter, T.F. Cheek, "The use of multiple oxygen implants for fabrication of bipolar Silicon-OnInsulator Integrated Circuits", IEEE Trans, on Nucl. ScL, 35, n%, 1350 (Dec. 1988) E. Dupont-Nivet, E. Delagnes, J.L. Leray, J.L. Martin, J. Montaron, J.P. Blanc, E. Delevoye, J. Gauthier, J. de Pontcharra, R. Truche, E. Beuville, M. Dentan, N. Fourches, "A Hardened Technology on SOI for Analog devices", IEEE Trans, on Nucl. ScL, 39 n°3, June 1992 M.N. Darwish, M.C. Dolly and C.A. Goodwin "Radiation Effects on Power Integrated Cu-cuits", IEEE Trans, on Nucl. ScL, 35, n°6, 1547 (Dec. 1988) J.L. Leray, E. Dupont-Nivet, J.F. P6r6, Y.M. Coic, M. Raffaelli, A.J. Auberton-Herv6, M. Bruel, B. Giffard, J. Margail, "CMOS/SOI Hardening above 100 Megarad(Si02): Limits and Liabilities", IEEE Trans, on Nucl. ScL, 37, n°6, Dec. 1990, following the IEEE International Conference on Nuclear Science and Radiation Effects, Reno, Nevada 17-20 July 1990 O. Flament, J.L. Leray, O. Musseau, "Radiation Effects on ICs and a Mixed Analog CMOS-NPNPJFET on Insulator Technology", in [197] Low-power HF Microelectronics, edited by Gerson A. Machado, the IEEE Circuits and Systems Series 8, ISBN 0 85296 874 4, pp. 185-207 (1996) B. Davari, H.J. Hovel, G.G. Shahidi, "SOI technology Outlook for Sub-0.25 micron CMOS, Challenge and Opportunities" Proc. of the 1993 IEEE SOI Conference J.-P. Colinge, Silicon-On-Insulator Technology: Material to VLSI, Kluwer Academic Publishers, Boston, (2nd edition, 1997) ISBN 0-7923-8007-X T. Ouisse, S. Cristoloveanu and G. Borel, "Electron Trapping in Irradiated SIMOX Buried Oxides" IEEE Electron Dev. Letters, 12, n°6 (1991) 312 P. Paillet , P. Gonon , C. Schwebel , J. L. Leray, "Comparison of X-Ray-Induced Electron and Hole Trapping in Various Materials (YSZ, SIMOX, thermal Si02)", Journal of Non-Crystalline Solids 187 (1995) pp. 170-174, L. Cohn, H.H. Hosak, R. Cheme, P. Fechner, "SIMOX circuits reliability" Proc. of the 1993 SOI Conference, ISBN 0-7803-1348-8 (1993) 158 C. Brisset, "Etudes Th^oriques par Simulation Monte-Carlo 3D de la Sensibility aux Irradiations des technologies CMOS/SOI" Thdse de Doctorat, University d'Orsay-Paris 11, Orsay, France, 1994 A. Abramo, C. Fiegna, "Electron energy distributions in silicon structures at low applied voltage and high electric fields" J. Appl. Phys., 80 (2), 15 July 1996, 889 Y. Takeishi, K. Natori, S. Iwabuchi, "Challenge in semiconductor technologies in the 1990's. A view from Japan" 20th International Conference on the Physics of Semiconductors, Thessaloniki, Greece, Aug. 6-10 (1990) J.P. Colinge, "SOI Technology", in [197] Low-power HF Microelectronics, edited by Gerson A. Machado, the lEE Cu-cuits and Systems Series 8, ISBN 0 85296 874 4, pp. 185-207 (1996)

A Review of Buried Oxide Structures and SOI Technologies [20 b] [21] [22] [23] [24]

[25] [26] [27] [28] [29]

[30] [31]

[32] [33] [34] [35]

[36]

[37]

[38]

223

H.K. Lim and J.G. Fossum, "Threshold voltage of thin-fihn silicon-on-insulator (SOI) MOSFETs", IEEE Trans. On Electron Devices, 30, p. 1244 (1983) S. Christoloveanu, S.S.Li, Electrical characterization of Silicon-On-Insulator materials and devices, Kluwer Academic Publishers (1995), ISBN 0-7923-9548-4 K. Suzuki, A. Satoh, T. Sugii, "Counter doping into uniformly and heavily doped channel region of sub 0.1 ^m SOI MOSFETs", IEEE Electron. Dev. Letter 17, 1 Jan. 1996, 1 W. A. Krull and J.C. Lee, "Demonstration of the Benefits of SOI for High Temperature Operation" Proc. of the 1988 IEEE SOS/SOI Workshop, IEEE (1988) 69 D.P. Vu, M.J. Boden, W.R. Henderson, N.K. Cheong, P.M. Zavracky, D.A. Adams and M.M. Austin, "High Temperature Operation of ISE devices and Circuits" Proc. of the 1989 IEEE SOI Conference, IEEE catalog n°89CH2796-l (1989) 165 R.R. Grzybowski, S.M. Tyson, "High Temperature Testing of SOI Devices to 400°C" Proc. of the 1993 SOI Conference, ISBN 0-7803-1346-1/93 (1993) 176 P.C. Karulkar, "Ultra-thin SOI MOSFETs at High Temperature" Proc. of the 1993 SOI Conference, ISBN 0-7803-1346-1/93 (1993) 136 L.K. Wang, "0.5 \xm gate CMOS/SOI technology using optical mix lithography" Proc. of the 1986 Symposium on VLSI Technology (1986) 359 S.S. Tsao,"Porous Silicon Techniques for SOI Structures" IEEE Circuits and device Magazine, 3, n°6 pp. 3-7 (1987) A.J. Auberton-Herve, M. Bruel, C. Jaussaud, J. Margail, W. d'Hespel, J.F. Pere, A. Vitez, A. Tissot, "A CMOS 1.4 jLim Technology on 1300°C Annealed SIMOX Substrate without epitaxy" Proc. of the VLSI Symposium, San Diego, CA (1988) J.P. Colinge, M.H. Gao, A. Romano-Rodriguez, H. Maes and C. Claes, Proc. of the 1990 IEEE lEDM, p. 595 (1990) S.R. Wilson, B.-Y. Hwang, J. Foerstner, T. Wetteroth, M. Racanelli, J. Tsao and M. Huang, "SiliconOn-Insulator Technology and Devices" Proc. of the 6th international Symp. "Silicon-On-Insulator Technology and devices" edited by S. Cristoloveanu, (The Electrochemical Society, 1994) pp. 413-424 A.H. Pawlikiewicz, "High-tolerance to radiation effects and low noise performance of ACUTE-a complementary bipolar SOI IC technology", IEEE Trans, on Nucl Sci. 43, n° 2, 761, April 1996 K. Joardar, "A simple approach to modeling cross-talk in integrated circuits" IEEE J. Solid State Circuits, p. 1212, Oct. 1994 A. Kamgar, S.J. Hillenius, H.I. Cong, R.L. Field and J.C. Sturm, "Ultra-high speed CMOS circuits m thin SIMOX fihns". Technical Digest ofIEDM(thQ IEEE, 1989) p. 829 P.A. Tove, K.F. Bohlin, F. Masszi, H. Norde, J. Nylander, M. Rosling, J. Tiren, A. Soderbarg and N. Masszi (Uppsala University, Sweden), "Complementary silicon Mesfets (CMES) using Silicon-OnSapphire technology, presented at COMP-EURO (1987) A.K. Agrawal, M.C. Driver, M.H. Hanes, H.M. Hobgood, P.O. McMuUin, H.C. Nathanson, T.W. O'Keffe, T.J. Smith, J.R. Szedon, R.N. Thomas, "MICROX - An Advanced Silicon Technology for Microwave Circuits up to X-Band" Techn. Digest oflEDM, p. 687 (1991) M.H. Hanes, A.K. Agrawal, T.W. O'Keffe, H.M. Hobgood, J.R. Szedon, T.J. Smith, R.R. Siergiej, P.O. McMullin, H.C. Nathanson, M.C. Driver, R.N. Thomas, "MICROX™ - An All Silicon Technology for Monolithic Microwave Integrated Circuits", Techn. Digest oflEDM, (1993) p. 182, IBSN 0-7803-1346-1 (1993) 4 and IEEE Electron Devices Letters, 14, n°5 (1993) 219-221 V. Ferlet-Cavrois, C. Marcandella, J. L. Pelloie, C.Raynaud, O. Faynot, "High Frequency Performances of a SOI Technology for Low-Power, Low-Voltage Applications", 1997 SOI Symposium, Electrochemical Society (1997) th

[39] [40]

P. Sian "Advanced SOI process boost performance". Electronic design, Aug. 4 , 1997, p. 25. I. Lagnado, P. de la Houssaye, "TFSOS: Quo vadis ?" 1997 Joint International ECS-ISE Meeting", Paris, (The Electrochemical Society, 1997)

224

[41] [42] [43]

[44]

[45] [46] [47] [48] [49] [50] [51] [52] [53] [54]

[55] [56] [57] [58] [59]

[60 a] [60 b]

[60 c] [61]

y.L. Leray

Peregrine Semiconductors Corporations, San Diego, Ca, USA, "An ultra-thin silicon technology that provides integration solutions on standard CMOS", Microwave journal, January 1998, p. 198 J.M. Carroll, "Microelectronics circuits and applications, McGraw-Hill Book Company, Library of Congress Catalog Card Number 64-8615 (1965), especially pp. 137-153 H.C. Tuan, "Amorphous Silicon Thin Fihn Transistor and its Applications to Large-Area Electronics" Material Research Society Proceedings, Vol. 33, ed. H.W. Lam and M.J. Thompson (North Holland, 1984) pp. 247-257 G. M. Dohiy, A.C. Ipry, G.E. Nostrand, C.F. Wheatley and P.J. Wodarczyck, "Silicon on Insulator Approach for Power IC's integrating vertical DMOD and polycristalline Silicon CMOS thintransistors", IEEE Electron Devices Letters, 13, n° 10, 516-518 (Oct. 1992) P. K. Weuner, "The TFT - A new Thin-Fihn Transistor", Proc. of the IRE, p. 1462-1469 (1962) I. Golecki, "The Current Status of Silicon on Sapphire and other heteroepitaxial Technologies" Material Research Society Proceedings, Vol. 33, ed. H.W. Lam and M.J. Thompson, (North Holland, 1984) p. 3 H.M. Manasevit and W.I. Simpson, "Single-crystal silicon on a sapphire substrate" J. Appl Phys. 35 (1964)1349 F.P. Heiman,"Thin fihn Silicon On Sapphire Deep depletion MOS Transistor" IEEE-ED 13, n°12 (1966)855 T. Sato, J. Iwamura, H. Tango and K. Doi, "CMOS/SOS VLSI Technology", Material research Society Proceedings, Vol. 33, ed. H.W. Lam and M.J. Thompson, (North Holland, 1984) p. 3 J. E.A. Maurits, "SOS Wafers - Some Comparison to Silicon Wafers", IEEE Trans on ED., 25, n°8, 859-863 (Aug. 1978) P. Gentil, "Simple method for evaluating electronic properties at the silicon-sapphire interface". Electronic letters, 16, n°16, pp. 617-618, (1980) A.M. Goodman, "An investigation of the silicon-sapphire interface using the MIS capacitance method" IEEE Trans. Electron Devices, ED-22, 63 (1975) S. Cristoloveanu, G. Ghibaudo, G. Kamarinos, "Le mat^riau silicium sur saphir en FRANCE. Revue des propri^t^s physico-chimiques et ^lectriques", Revue Phys. Appl. 19, pp. 161-185 (1984) J.L. Repace, "Radiation and negative charge in SOS capacitors", IEEE Trans. Nucl. Sci., 6 (Dec. 1978) and J.L. Repace, A.M. Goodman, "The effect of process variations on interfacial and radiation-induced charge in silicon on sapphire capacitors", IEEE Trans, on Electron Devices, Special issue "SOS", Aug. 1978 J. Tihanyi, "Measurement of the profiles of electrical properties in epitaxial silicon fihns on insulating substrates", European Solid State device Research Conference, paper A 4.2, Mtinchen (1974) S. Cristoloveanu, S. Chovet, G. Kamarinos, "Non-uniform recombination on thin Silicon-On-Sapphire fihns" Solid State Electronics, 21, 1563 (1978) S. Cristoloveanu, Thdse d'Etat de doctorat ^s Sciences Physiques, Institut National Polytechnique, Grenoble, 1981 P. Senn, Thdse de Docteur-Ing^nieur, Institut National Polytechnique, Grenoble, 1988 A. C. Ipri, "The properties of Silicon-On-Sapphire substrates, devices and integrated circuits", in Silicon Integrated Circuits, Part A, edited by D. Kahng, Applied Solid States Supplements, Vol. 2, Academic Press (1981), pp.253-395 H. Schl5terer, "Interface properties of Si on sapphire and spinel", J. Vac. Sci. TechnoL, 13, n° 1, pp. 2936 (1976) M.S. Abrahams, J. Blanc, C.J. Buiocchi, W.E. Ham, "Shear strain at comers and edges of epitaxial Silicon On Sapphire" J. Appl. Phys. 49, (1978) p. 652 and M.S. Abrahams and C.J. Buiocchi, Appl Phys. Lett. 27, (1975) p. 325 E. Preuss and H. Schlotterer, "Silicon-On-Sapphire devices: realisation, properties and applications", Inst. Phys. Conf. Ser. N° 40, (1978) pp. 7-31 (esp. p. 14). P. Gentil, S. Chausse, Solid State Electronics, 20, 935 (1977)

A Review of Buried Oxide Structures and SOI Technologies

[62] [63] [64]

[65] [66a]

[66b] [67] [68] [69]

[70]

[71] [71a] [71b] [72] [73]

[74] [75]

[76]

[77]

[78]

225

A. Touboul, G. Pelloux, G. Lecoy, A. Chouajaa, P. Gentil, Revue de Physique Appliquee, 13, 227 (1974) M.E. Roulet, P. Schwob and I. Golecki, Electron. Lett,, 15, 527 (1979) D.J. Smith, L.A. Freman, R.A. McMahon, H. Amed, M.G. Pitt, T.B. Peters, "Characterization of Siimplanted and electron-beam-annealed silicon-on-sapphire using high-resolution electron microscopy", J. Appl Phys., 56, (8), pp. 2207-2211 (1984) D. Pribat, L.M. Mercandalli, J. Siejka, J. Perriere, "Interface oxidation of epitaxial silicon deposits on (100) yttria stabilized cubic zh-conia", J. Appl Phys., 58, p. 313, (1985) P.K. Vasudev and D.C. Mayer, "Characterization of CMOS devices in 0.5 |im Silicon-On-Sapphire films modified by solid phase epitaxy and regrowth (spear)", Mat. Res. Soc. Symp. Proc. Vol. 33, pp. 35-39 (1984) H.M. Manasevit and D.H. Forbes, J. Appl Phys. 37 (1966) 734 G. Shimoka and S.C. Chang, J. Vac. Sci. Technology, 6,235, (1972) F.J. Himpsel, U.O. Karlsson, F.R. McFeely, J.F. Morar, D. Rieger, A. Taleb-Ibrahimi and J.A. Yarmoff, Material Science and Engineering, Bl, pp. 25-39, (1988) P. Hesto, C. Pellet, C. Schwebel, A. Bosseboeuf, D. Bouchier, E. Dupont-Nivet, J.L. Leray, M. Raffaelli; "Durcissement du transistor MIS a canal superdope en silicium epitaxie sur zircone". Annates de Physique, ANPHAJ 14 (6), p. 557, Dec. 1989 M. Ihara, Y. Arimoto, M. Jifuku, T. Yamaoka, K. Kurokawa, "Spinel-isolated High-Voltage ICs", IEEE 28* Int. Conf on Solid-State Circuits, pp. 210-211 (1981) and High Voltage Integrated Circuits, ed. B.J. Baliga, IEEE Press, PC0232-9, 1988 J. Maserjian, "Single-crystal germanium fihns by micro-zone melting", Solid-State Electronics 6, pp. 477-484 (1963) A.J. Auberton-Herv^, J.P. Joly, P. Jeuch, J. Gautier, J.M. Hode, "Device performance of a submicron SOI technology", IEEE Proceedings of the International Electron Devices Meeting (lEDM, 1984) M. Haond, D. Bensahel and D. Dutartre, "Fabrication of thick films of Silicon-On-Insulator substrates by using a scanning halogen lamp system". Electronic Letters, 20, n° 24, 22"^ Oct. 1984 G.L. Hutchins and R.A. Laff, "Fabricating isolated device-quality semiconductor fibn areas on a foreign substrate using laser melting" IBM Technical Disclosure Bulletin, 16, n° 10 (1974) J.M. Hode, "Silicium sur isolant par microfusion de zone laser. Optimisation du materiau analyse des m^canismes". These de Doctorat en Sciences physiques, Institut National polytechnique de Grenoble, France (1989) B.-Y. Tsaur, "Zone-Melting Techniques for SOI Structures", IEEE Circuit and Devices Magazine, pp. 12-16, 1987 P.M. Zavracky, "ISE technology: a flexible SOI solution", Proc. of the 4th international symposium on Silicon-On-Insulator technology and Devices, Vol. 90-6, The Electrochemical Society, pp.49-60, (1990) A.J. Steckl, C. Yuan, Q.Y. Tong, U. G5sele, M.J. Loboda, "SiC SOI structures by direct carbonization conversion and post growth from silacyclobutane", in: Silicon-On-Insulator Technology and Devices, Proc. of the 6th international Symp. On Silicon-On-Insulator Technology and devices, edited by S. Cristoloveanu, (The Electrochemical Society, 1994) T. Nishimura, Y. Inoue, K. Sugahara, S. Kusonoki, T. Kumamoto, S. Nakagawa, M. Nakaya, Y. Horiba, and Y. Akasaka, "Three-dunensional ICs for high performance image signal processor", Proc. of the 1987 lEDM Conference, p.l 11 (1987) M.W. Watanabe, A. Tool, "Formation of SiOj fihns by oxygen-ion bombardment", Japan J. Appl Phys, 5, 737, (1966)

226

[79]

[80] [81] [82] [83 a]

[83 b] [84 a]

[84 b] [85] [86 a] [86 b] [87]

[88] [89]

[90] [91] [92] [93] [94]

[95]

[96] [97]

J,L,

Leray

V.M. Gusev, M.I. Guseva, V.I. Kurinnyy, V.V. Titov, V.S. Tsyplenkov, E.K. Baranova, L.P. Strel'tsov, "An investigation of the properties of the oxide fibn produced by atomic oxygen ion bombardment of silicon, and its use as protection for p-n junctions", Radio Eng. & Electron Phys., 16, pp. 1357-1361,(1971) K. Izumi, M. Doken and H. Ariyoshi, "CMOS devices fabricated on buried SiOj layers formed by oxygen implantation into silicon". Electron. Lett., 14, pp. 593-594, 1978 P.L.F. Hemment, "Silicon On Insulator by High Dose Implantation" Proc. of the Material Research Society, Vol. 33 (H.W. Lam, M.J. Thompson Editors, North Holland 1984) pp. 41-51 S. Nakashima, M. Akiya, K. Kato, "Electric-Field-Shielding layers formed by oxygen implantation into silicon". Electron. Lett., 19, pp. 568-570, (1983) B. Aspar, C. Pudda, A.M. Papon, A.J. Auberton-Herv6, J.M. Lamure, "Ultra-thin buried oxide layers formed by low dose SIMOX processes", in: Silicon-On-Insulator Technology and Devices, Proc. of the 6th international Symp. On Silicon-On-Insulator Technology and devices, edited by S. Cristoloveanu, (The Electrochemical Society, 1994) M.H. Cohen, H. Fritzche, S.R. Ovshinsky, "Simple band model for amorphous semiconducting alloys", Phys. Rev. Lett. 22, pp. 1065-1068, (1969) C O . Tuppen, M.R. Taylor, P.L. Hemment, R.P. Arrowsmith, "Effects of implantation temperature on the purpose of buried oxides layers in silicon formed by oxygen ion implantation", Appl. Phys. Lett., 45, pp. 57-59, (1984) S. Nakashima, Y. Madea, M. Akiya, "High-Voltage CMOS SIMOX technology and its applications to a BSH-LSI", IEEE Transaction on Electron Devices, ED-33, pp. 126-132, (1986) J. Stoemenos, C. Jaussaud, M. Bruel, J. Margail, "New Conditions for Synthesizing SOI Structures by High Dose Oxygen Implantation" Journal ofCryst. Growth 73, pp. 546-550 (1985) M. Bruel, J. Margail, C. Jaussaud, A.J. Auberton-Herv^, J. Stoemenos, "Silicon-On-Insulator by oxygen hnplantation: an advanced technology" Microelectronic Engineering 8, pp. 149-161, (1988) J. Jablonski, M. Saito, M. Imai and S. Nakashima, "Gettering layer in low-dose SIMOX wafers", Proc. of the 1995 IEEE International SOI Conference, pp. 34-35, ISBN 0-7803-2549-4 (1995) S. Masui, T. Nakajima, K. Kawamura, T. Yano, I. Hamagushi, K. Kajiyama and M. Tashimori, "Evaluation of fixed oxide charge and oxide-silicon interface trap densities in low-dose and high-dose SIMOX wafers", 1994 IEEE International SOI Conference, and: Nippon Steel documentation (1995) available at Advanced Technology Materials, 7 Commerce Drive, Danbury CT 06810, USA F. Namavar, E. Cortesi, B. Buchanan and P. Sioshansi, "Low Energy SIMOX (LES)" Proc. of the 1989 SOI Conference, IEEE catalog number 89CH2796-1, p. 117, (1989) B. Aspar, C. Pudda, A. Garcia, C. Guilhamenc, A.J. Auberton-Herv^, J.M. Lamure, "Buried oxides formed by low dose SIMOX processes", presented at the Insulating Fihns on Semiconductors (INFOS) Conference 1995 and Microelectron. Eng 28, p 411 (1995) NTT documentation, Nippon Telegraph and Telephone, 1995 (Japan) SOITEC documentation, 1995 available at 1, Place Firmin Gautier, 38000 Grenoble, France KOMATSU documentation, n° 95061000, (1995), 2612 Shinomiya, Hiratsuka City, Kanagawa 254, Japan G. Zimmer and H. Vogt, IEEE Trans, on Electron Devices, 30 (1983) 1515 W. Skorupa, K. Wollschlager, R. Grotzschel, J. Sch5neich, E. Hentschel, K. Kotte, F. Stary, "Properties of buried insulating layers in silicon formed by high dose implantation at 60 keV", Nuclear Instruments and Methods, B32, pp. 440-445, (1988) K.J. Reeson, P.F.L. Hemment, CD. Meekison, CD. Marsh, G.R. Brooker, R.J. Chater, J.A. Kibier, J. Davis, "Buried layers of silicon oxynitride fabricated using ion beam synthesis". Nuclear Instruments and Methods, B32, pp. 427-432, (1988) A. Revesz and A.J. Auberton-Herv^, private communications P. Roitman and M. Edelstein, Proc. 1990 IEEE SOS/SOI Tech. Conf., Key West, Florida, October 2-4, 1990, ISBN 0-87942-573-3, p. 154, (1990)

A Review of Buried Oxide Structures and SOI Technologies

[98] [99 a] [99 b] [100]

[101] [102] [103] [104 a]

[104 b] [105]

[106] [107] [108] [109] [110]

[111] [112] [113] [114] [115] [116] [117] [118] [119]

227

M J . Anc and W.A. Krull, "Sources of SIMOX buried oxide leakage" Microelectron. Eng. 28, p. 407, (1995) G.A. Brown and A.G. Revesz, Proc. of the 1991 IEEE Int. SOI Conf, Vail Valley, Colorado, October 1-3, 1991, ISBN 0-7803-0184-6, p. 174, (1991) G.A. Brown, A.G. Revesz, "Defect electrical conduction in SIMOX buried oxides" IEEE Trans, on Electron devices, 40, n°9, pp. 1700-1705 (1993) D. Venables, S.J. Krause, J.C. Park, J.D. Lee and P. Roitman, "Effect of Single vs. Multiple Implant Processing on Defect Types and Densities in SIMOX" Proc. of the 1993 IEEE Int. SOI Conf., Pabn Springs, (Ca) USA, October 5-7, 1993, ISBN 0-7803-1346-1, p. 48, (1993) U. Gosele, M. Reiche and Q.Y. Tong, "Properties of SIMOX and bonded SOI material" Microelectron, ^«g. 28, p. 391, (1995) G. Brebeck, R. Seguin, C. Stella, J. Benevot, C. Martin, Acta Metallica 28, p. 327 (1980) A.G. Revesz, G.A. Brown and H.L. Hughes, "Bulk electrical condition in buried oxide of SIMOX structures", J. Electrochem. Soc, 140, pp. 3222-3229 (1993) A.G. Revesz and H.L. Hughes, "The defect structure of buried oxide layers in SIMOX and BESOI structures", in [196] NATO ASI series, 3. High technologies - Vol. 4 (1995), Kluwer, ISBN 0-79233600-3, pp. 133-156 J.H. Yap, T. Maung, J. Nee, E. Simic and J.E. Chung, "Conduction mechanisms through SIMOX buried oxide", Proc. of the IEEE SOI Conference, IEEE catalog. 0-7803-1346-1 (1993) 32 R.A.B. Devine, D. Mathiot, W.L. Warren, P. Paillet, J.L. Leray, "Processing-Induced Degradation in SiSi02 Systems", in "Le Vide : science, technique et applications" supplement n° 275, Mars 1995 following the 2nd International Conference on Space Charge in Solid Dielectrics, 2-7 April 1995, Antibes-Juan-les-pins, France L.F. Giles, A. Nejim, C D . Marsh, P.L.F. Hemment and G.R. Booker, Proc. of the 1993 IEEE Int. SOI Conf., Pabn Springs, (Ca) USA, October 5-7, 1993, ISBN 0-7803-1346-1 (1993), p. 48 C. Tsamis, D. Tsoukalas, N. Guillemot, J. Stoemenos and J. Margail. Proc. of the Insulat. Fihns Int. SOI Conf., Pahn Springs, (Ca) USA, October 5-7, 1993, ISBN 0-7803-1346-1 (1993), p. 54 G.K. Celler, "Future prospects for SIMOX technology" Proc. of the 6* Int. Symp. on Silicon Mat. Sci. and Tech. (The Electrochemical Society, 1990), Vol. 90-7, p. 472 J.M. Lamure, B. Biasse, C. Jaussaud, A.M. Papon, J.F. Michaud, F. Gusella, C. Pudda, A.M. Cartier, A. Soubie and J. Margail, Proc. of the 1990 IEEE SOI Conference, ISBN 0-87942-573-3 (1990) p. 45 H. Gassel, H. Vogt, "Improvements of SIMOX buried oxide breakdown voltage by multistep and multiple energy implantation", in: Silicon-On-Insulator Technology and Devices, Proc. of the 6th Inter. Symp. On Silicon-On-Insulator Technology and devices, edited by S. Cristoloveanu, (The Electrochemical Society, 1994) pp. 357-366 K. Imai, Solid-State Electronics, 24, p. 59, (1981) Morrazzani, These de I'Universit^ Paris VII, February 20**^, 1996 R.L. Smith, S.D. Collins, "Porous silicon formation mechanisms", J. Appl Phys. 71 (8), April 92 J.J. Yon, K. Barla, R. Herino, G. Bomchil, "The kinetics and mechanism of oxide layer formation from porous silicon formed on p-Si substrates", J. Appl Phys., 62 (3), Aug. 1987, pp. 1042-1044 G. Bomchill, R. Herino and K. Barla, "Porous silicon for Silicon-On-Insulator technologies" Proc. MRS Europe (Strasbourg, 1985), Editions de Physique, France, pp. 463-474 (1985) K. Anzai, F. Otoi, M. Ohnishi, H. Kitabayashi, "Fabrication of high speed 1 micron FIPOS/CMOS", lEEEIEDM, pp. 796-799, (1984) S.S. Tsao, T.R. Guilinger, M.J. Kelly, J.A. Knapp, H.J. Stein, J.C. Barbour, "Oxides and oxynitrides of porous silicon", Proc. of the Material Society Fall Meeting, Boston, Vol. 107, p. 429 (Nov. 1988) K. Barla, G. Bomchil, R. Hermo, A. Monroy, Y. Gris, "Characteristics of SOI CMOS circuits made in N/N^/N oxidized porous silicon structures". Electronics Letters, 22, n°24, 20 Nov. 1986, pp. 1291-1293 K. Barla, G. Bomchil, R. Herino, A. Monroy "SOI technology using buried layers of oxidized porous Si", IEEE Circuits and Devices Magazine, Nov. 1987, pp. 11-14

228

[120]

[121]

[122] [123] [124] [125] [126] [127 a] [127 b] [128]

[129] [130]

[131] [132] [133] [134] [135] [136] [137 a]

[137 b] [138] [139 a]

y.L. Leray

L.M. Mercandalli, D. Dieumegard, S. Cristoloveanu, J.L. Leray, A. Umbert, J.J. Aubert, "CMOS/SOZ and CMOS/SOOZ: A device-quality MOS on Insulator made on Zirconia substrates", Proc. of the IEEE Silicon On Sapphire and Silicon on Insulator Workshop, Florida-USA (1984) E. Dupont-Nivet, A. Umbert, J.L. Leray, L.M. Mercandalli, B. Dessertenne, D. Dieumegard, J. Siejka, "MOS/SOI (Sapphire, Yttrya-Stabilized Zirconia) Technology for Radiation-Hardened Devices and Comparative Study of Photocurrent Generation", Proc. of the Electrochemical Society, Electrochemical Society Meeting, Session Electronics-Dielectrics and Insulation, Atlanta, Georgia-USA, 15-20 May 1985 J.P. Colinge, "An SOI voltage-controlled bipolar MOS device", IEEE Trans, on Electron Devices, 34 n°4, 845, (1987) P. Francis, C. Michel, D. Flandre and J.P. Colinge, IEEE Trans, on Nuclear Science, 41, n°2, pp. 402407, (1994) P. Francis, J.P. Colinge and G. Berger, "Temporal analysis of SEU in SOI/GAA SRAMs" IEEE Trans. on Nuclear Science, 42, n°6, pp. 2127-2137, (1995) B.L. Kravitz, "Radiation-Hardened IC's", Solid State Technology, Jan. 1970, pp. 57-60 A. Berezine, O. Motchalkma, "Technologic et construction des circuits int^gr^s" (Technologia i konstructovanie integralnik mikroskem). Edition MIR, 1983, Moscou, p. 104-105 ATT documentation "High performance silicon wafers - dielectric isolation", ATT Microelectronics, 2525 North 12th street, POB 13396, Reading, PA, 19612, USA. "Features of On-Chip Ringmg Relay type HC5506 for Telephone Subscriber Line", Harris Semiconductors Technical Documents (1995) N.I. Koshelev, A.I. Ermolaeva, V.Z. Petrova, "SOI fabrication by silicon wafer bonding with the help of glass-layer fusion", in [196] NATO ASI series, 3. High technologies - Vol. 4 (1995), Kluwer, ISBN 0-7923-3600-3, pp. 87-92 J. Haishma, G.A.C.M. Spierings and T.M. Michielsen, "Framework for direct bonding". Philips. J. Res. 49, \\-\2 {1995) T. Abe, M. Nakano and T. Itoh, "Silicon wafer-bonding process technology for SOI structures", Proc. of the 4th international symposium on Silicon-On-Insulator technology and Devices, Vol. 90-6, The Electrochemical Society (1990), pp.61-71 J.B. Lasky, S.R. Stiffer, F.R. White and J.R. Abemathey, lEDMtech. Digest (1985) p. 684 J.B. Lasky, "Wafer Bonding for Silicon-On-Insulator technologies" Appl. Phys. Lett., 48 (1), p. 78 (1986) M.Mishima, T. Yasui, T. Mizuniwa, M. Abe and T. Ohmi, IEEE Trans, on Semiconductor Manufacturing, 2, n°3, p. 69, (1989) W.P. Maszara, G. Goetz, A. Caviglia and J.B. McKitterick, "Bonding of silicon wafers for Silicon-OnInsulator", J. Appl. Phys. 64, n°10, pp. 4943-4950, (1988) Q.Y. Tong, G. Cha, R. Gafiteanu and U. G5sele, "Low temperature wafer direct bonding" IEEE Journal of Microelectromechanical Systems, 3, n°l, pp. 29-35, (1994) W.P. Maszara, "SOI by Wafer Bonding: a review", Proc. of the 4th international symposium on SiliconOn-Insulator technology and Devices, Vol. 90-6, The Electrochemical Society (1990), pp.l99-212A M. Bruel, B. Aspar, B. Charlet, C. Maleville, T. Poumeyrol, A. Soubie, A.J. Auberton-Herve, J.M. Lamure, T. Barge, F. Metral, S. Trucchi, "Smart cut: a promising new SOI material technology" Proc. of the 1995 IEEE Int. SOI Conf., Tucson, Arizona-USA, October 3-5, 1995, ISBN 0-7803-2547-8 (1995), p. 178 M. Bruel, "Silicon On Insulator material technology". Electronics letters, 31, n°14, July 1995, pp. 1201-1202 M. Bruel, "Application of hydrogen ion beams to Silicon On Insulator material technology", Nucl. Inst. and Methods B 108, pp. 313-319 (1996) W.P. Maszara, "Wafer Bonding SOI, generalized bonding and new structures" Microelectron. Eng. 22, p. 299 (1993). See also references therein

A Review of Buried Oxide Structures and SOI Technologies

229

[139 b] R.K. Lawrence, J.P. Colinge and H.L. Hughes, Proc. of the 1990 IEEE SOI Conference, IBSN 0-78030184-6/91 (1990), p. 80 [140] Q.Y. Tong, U. G5sele, C. Yuan and AJ. Steckl, Proc. of the 1993 IEEE Int. SOI Conf., Palm Springs (Ca) USA, October 5-7, 1993, ISBN 0-7803-1346-1 (1993), p. 60 [141] L. Di Ciocio, Y. Le Tiec, F. Letertre, C. Jaussaud and M. Bruel, "Silicon Carbide On Insulator using the Smart-Cut process" (SICOI) Electronics Lett., 32, (12), pp. 1144-1145 (1996) [142] L. Di Ciocio, Y. Le Tiec, F. Letertre, A.M. Papon, C. Jaussaud and M. Bruel, "Silicon Carbide On Insulator formation by the Smart-Cut^ process". Mat, Sci. Eng. B46, pp. 349-356 (1997) [143] Q.A. Huang, S.J. Lu, Q.Y. Tong, Proc. of the 1989 IEEE SOS/SOI Tech. Conf, Stateline, NevadaUSA, October 3-5 1989, IEEE catalog number 89CH2796-1 (1989), p. 62 [144] G.G. Goetz and A.M. Fathimulla, Proc. of the 1989 SOI Conference, IEEE Catalog number 89CH27961 (1989) p. 125 and A.M. Fathimulla, H. Hier and J. Abrahams, Proc. of the GaAs and Related Compounds Conference, Atlanta, (1988) [145] X. Kanda, "High-performance 19 GHz-band GaAs FET switches using LOXI (Layered-OxideIsolation) MESFETs", Proc. of the 1997 GaAs IC Symposium, the IEEE, p. 62, ISBN 0-7803-40833/97 [146] A. SOderbag, B. Edhohn, J. Olsson, S. Tiensuu, E. Johansson, Proc. of the 1993 IEEE SOI Conference, ISBN 0-7803-1348 (1993) p. 58 [147] A.J. Auberton-Herve, "Special SOI-based devices" Microelectron Eng. 22, p. 339, (1993) [148] D. Bursky, "Single chip performs both audio and video recording" Electronic Design 43, p. 77, (1995) [149] T. Enomoto, "Fabrication process, experimental results and application for an elemental level vertically integrated circuit (ELVIC)" J. Mater. Res. 1, p. 552, (1986) [150] S. Nakamura, H. Horie, K. Asano, Y. Nara, T. Fukano and N. Sasaki, "Giga-bit DRAM cells with low capacitance and low resistance bit-lines on buried MOSFET's and capacitors by using bonded SOI Technology-Reversed Stacked Capacitor (RSTC) cell" lEDMTech. Dig., p. 889, (1995) [151] T. Enomoto, "Fabrication process, application and future for an elemental level vertically integrated circuit (ELVIC)", Mat. Res. Soc. Symp. Proc, Vol. 53, pp. 383-389, (1986) [152] D.G. Hall, "The role of silicon m optoelectronics" Mat. Res. Soc. Symp. Proc, Vol 298, Material Research Society (1993) 367-378 [153] C.K. Tang, G.T. Reed, A.J. Walton and A.G. Rickman, "Simulation of a low loss optical modulator for fabrication in a SIMOX material". Mat. Res. Soc. Symp. Proc. Vol. 298, pp. 247-252 (1993) [154] N.M. Kassim, T.M. Benson, D.E. Davies and A. McManus, INF0S'91 Conference Proceedings (published by the Institute of Physics, U.K., 1992) p. 319 [155] X. Xiao, J.C. Sturm, P.V. Schwartz and K.K. Goel, Proc. of the IEEE SOI Conference, ISBN 0-87942573-3 (1990) p. 171 [156] P.W. Barth," Silicon fusion bonding for fabrication of sensors, actuators and microstructures" Sensors Actuators, A21-A23, pp. 919-926, (1990) [157 a] H.E. Boesch, Jr. and T.L. Taylor, "Time dependent hole and electron trapping effects in SIMOX buried oxides" IEEE Trans. Nucl. Sci. NS-39, p. 2103, (1992) [157 b] D. Herve, Ph. Paillet, J.L. Leray, "Space-charge effects m x-ray irradiated SIMOX oxides", IEEE Trans, on Nucl. Sci., T-NS 41 Vol. 4, pp. 466, June 1994 and IEEE Conference Records, Catalog Number 93TH0616-3, ISBN 0-7803-1793-9, RADECS 1993 International Conference, St Malo, 13-16 September 1993 [158] F.B. McLean, H.E. Boesch and T.R. Oldham in: Ionizing radiation effects in MOS devices and circuits, edited by T.P. Ma and P.V. Dressendorfer, John Wiley & Sons, New-York (1989), Chapter 3 [159] P.S. Winokur in: "Ionizing radiation effects in MOS devices and circuits", edited by T.P. Ma and P.V. Dressendorfer, John Wiley & Sons, New-York (1989), Chapter 4 [160] J.L. Leray, O. Musseau, P. Lalande, R. Gaillard, "Effets des Rayonnements sur les Mat^riaux et Dispositifs Semiconducteurs", L'onde Electrique, 75 n°3, mai-juin 1995, pp. 13-19 [161] J.L. Leray, "Assessments of SOI technologies for hardening". Microelectronic Engineering, 8, n°3-4, p. 187, Dec. 88 , 1st European SOI workshop, Meylan, FRANCE, 1988

230

[162]

/ . L . Leray

J.L. Leray, "Contribution a I'etude des ph^nomenes induits par les rayonnements ionisants dans les structures a effet de champ au silicium et k I'arseniure de gallium utilis^es en micro^lectronique", These de doctorat d'etat es Sciences Physiques, University de Paris XI, U.E.R. Scientifique d'Orsay, n°3576, 8 D6cembre 1989 [163] Ph. Paillet, "Effet du Proc6d6 de Fabrication des Isolants sur la Charge d'Espace Cr^ee par Rayonnement X. Application aux Technologies Silicium sur Isolant", Th^se de I'Universit^ de Montpellier II, 1995 [164] Ph. Paillet, P. Gonon, C. Schwebel, J.L. Leray, "Comparison of X-Ray-Induced Electron and Hole Trapping in Various Materials (YSZ, SIMOX, Thermal Si02)", Journal of Non-Crystalline Solids 187, pp. 170-174 (1995), E-MRS Sprmg Meeting, May 24-27 1994, Strasbourg (France) [165 a] J.L. Leray, P. Paillet, J.L. Autran, "State of the Art Types of Buried Oxides on Silicon, Radiation Effects and Electron and Hole Traps Herein Involved", Revue de Physique Appliquee, 1996 [165 b] J.L. Leray, M. Haond, G. Bomchil, CNET-CEA data on FIPOS and ZMR, unpublished [166] J.L. Leray, E. Dupont-Nivet, P. Lalande, O. Musseau, "Les technologies de circuits int^gr^s silicium sur isolants SOI : ^tat de I'art et perspectives", Annales de Physique, ANPHAJ 14 (6), Dec. 1989. Editions de Physique, following the RADECS 1989 Conference, University des sciences et techniques du Languedoc, Montpellier, 11-14 Sept. 1989 [167] Ph. Paillet, D. Herv^, J.L. Leray and R.A.B. Devine, "Evidence of negative charge trapping in high temperature annealed thermal oxides", IEEE Trans, on Nuclear Science, 4, June 1994, 473 and IEEE Conference Records Catalog Number 93TH0616-3, ISBN 0-7803-1793-9, RADECS 1993 International Conference, St Malo, 13-16 Septembre 1993 [168] X. Wang, E.E. King, P. Leonov, D.H. Huang, P.T. Thompson and D. Godbey, "Bonded substrates for integrated detector arrays", IEEE Trans on Nucl Sci, 40, n°5, pp. 1342-1346 (1993) [169] Ph. Paillet, J.L. Autran, O. Flament, J.L. Leray, B. Aspar, A.J. Auberton-Herv6, "X-radiation Response of Simox Buried Oxides: Influence of the Fabrication Process", IEEE Transaction on Nuclear Science, 43 n°3, Apr. 1996 and IEEE Proceedings, RADECS 95, Arcachon, France [170] Ph. Paillet, D. Herv^, J.L. Leray, R. Devine, "Effect of high temperature processing of Si/Si02/Si structures on theh* response to x-ray irradiation", Appl Phys. Lett.^ 63 (15), pp. 2088-2090, October 11 1993 [171] J.L. Leray, Y.M. Coic, R.A.B. Devine, J. Margail, "Ionizing Effects m Vitreous Silica and S.O.I. SIMOX Buried Oxide by Study of Trapped Charges and Paramagnetic Defect Creation", IEEE Conference Records, Catalog Number 91TH0400-2, RADECS Conference (RADiation Effects on Components and Systems, Montpellier, Sept. 1991) [172] A. Stesman, R.A.B. Devine, A. Revesz, H. Hughes, "Irradiation-induced ESR active defects in SIMOX structures" IEEE Trans. Nucl. Sci., NS-37, p. 2008 (1990) [173] R. Devine, J.L. Leray, J. Margail, "Ultraviolet radiation induced defect creation in buried Si02 layers", Appl. Phys Lett. 59 (18), p. 2275, 28 Oct. 1991 [174] W.L. Warren, M.R. Shaneyfelt, J.R. Schwank, D.M. Fleetwood, P.S. Winokur, R.A.B. Devine, W.P. Maszara and J.B. McKitterick, IEEE Trans. Nucl. Sci NS-40, p. 1755 (1993) [175] J. F. Conley, P. M. Lenahan, P. M. Roitman, "Electron spin resonance of E' trapping centers in SIMOX buried oxides" IEEE Trans. Nucl. Sci., NS-38, p. 1247 (1991) [176] R. E. Stahlbush, G. J. Campisi, J. B. McKitterick, W. P. Maszara, P. Roitman and G. A. Brown, "Electron and hole trapping in irradiated SIMOX, ZMR, and buried oxides" IEEE Trans. Nucl. Sci,, NS-39,p.2086(1992) [177] F. T. Brady, W.A. KruU, S.S. Li "Total dose radiation effects for implanted buried oxides" IEEE Trans. Nucl. Sci. NS- 36, n°6, pp. 2187-2191 (1989) [178] J.L. Leray, J. Margail, R. Devine, "Electric field dependent paramagnetic defect creation in single-step high dose oxygen implanted SIMOX films". Material Science and Engineering, B12, pp. 153-156 (1992)

A Review of Buried Oxide Structures and SOI Technologies [179]

[180] [181] [182] [183] [184]

[185] [186] [187] [188] [189] [190] [191] [192]

[193] [194] [195]

231

O. Flament, O. Musseau, D. Herve, V. Ferlet, J.L. Leray, M. Raffaelli, A.J. Auberton-Herve, J. Margail, B. Giffard, "Field dependent charge trapping effects in SIMOX buried oxide at very high dose", IEEE Transactions on Nuclear Science, 39, n°6, December 1992, following the IEEE International Conference on Nuclear Science and Radiation Effects, New Orleans-USA, July 1992 M. E. Zvanut, R. E. Stahlbush and W. E. Carlos, Appl Phys. Lett 60, p. 2989 (1992) R.A.B. Devine, W.L. Warren, J.B. Xu, I.H. Wilson, P. Paillet and J.L. Leray, "Oxygen gettering and oxide degradation during annealing of Si-Si02-Si structures", J. Appl Phys. 11, p. 175 (1995) K.H. Vanheusden and A. Stesmans, J. Appl Phys. 74, p. 275 (1993) D. Herve, J. L. Leray and R. A. B. Devine, "Comparative study of radiation-induced electrical and spin active defects in buried Si02 layers", J. Appl. Phys. 72, p. 3634 (1992) Ph. Paillet, J.L. Autran, J.L. Leray, B. Aspar, A.J. Auberton-Herve, "Trapping-Detrapping Properties of Irradiated Ultra-Thin SIMOX Buried Oxides", IEEE Trans, on Nucl Sci., 42 n°6, Dec. 1995, pp. 21082113 J. K. Rudra and W. Beall Fowler, Phys. Rev. B-35, p. 8223 (1987) S. Bengtsson and O. Engstrom, "Interface charge control of directly bonded silicon structure" J. Appl. Phys. 66, p. 1231 (1989) C.A. Pennise, H.E. Boesch, Jr., G. Goetz and J.B. McKitterick, "Radiation-induced charge effects in buried oxides with different processing treatments" IEEE Trans. Nucl Sci. NS-40, p. 1765 (1993) H.E. Boesch, Jr. and C.A. Pennise, IEEE Trans. Nucl. Sci. NS-41, p. 2322 (1994) R.K. Lawrence, J.P. Colinge and H.L. Hughes, Proc. of the 1990 IEEE SOI Conference, IBSN 0-78030184-6191 (1990), p. 80 D. Maliniak, International Rectifier Company, "Commercially available optoisolator proves bondedprocess viable". Electronic Design, July 22, p. 38 (1996) "Single Channel Protector ADG465", Analog Devices Company, Data Sheet, p. 6 (1997) L. Parameswaran, V.M. McNeil, M.A. Huff and M.A. Schmidt, "Sealed-cavity microstructures using Wafer Bonding" Tech. Dig. Transducers'93, following the 7th Int. Conf. Solid-State Sensors and Actuators, Yokohama, Japan, (1993) pp. 274-277 M.A. Huff, A.D. Nikolich and M.A. Schmidt, "Design of sealed cavity microstructures formed by silicon Wafer Bonding" Journal of Microelectromechanical Systems, 2, pp. 74-81 (1993) Hyun et al "Presentation of a 1-gigabit dynamic RAM in a 0.17 ^m CMOS/SOI process". International Electron Device Meetmg (lEEE-IEDM), Washington, USA (1997) J.L. Leray, Buried Oxides: "Where we've been and where we're going", Journal of Non-Crystalline Solids 187, pp. 10-22 (1995), E-MRS Spring Meeting, May 24-27, Strasbourg (France)

REFERENCE BOOKS Single - author book [13]

J.P. Colinge, Silicon-On-Insulator Technology: Material to VLSI, Kluwer Academic Publishers, Boston, (2nd edition, 1997) ISBN 0-7923-8007-X

Multi-author books [21]

S. Cristoloveanu, S.S.Li, Electrical characterization of Silicon-On-Insulator materials and devices, Kluwer Academic PubUshers (1995), ISBN 0-7923-9548-4

[196] J.P. Colinge, V.S. Lysenko and A.N. Nazarov, "Physical and technical problems of SOI structures and devices", NATO ASI series, 3. High technologies - Vol. 4 (1995), Kluwer, ISBN 0-7923-3600-3 [197] G.A. Machado, "Low-Power HF Microelectronics", in lEE Ch-cuits and Systems Series 8, Laventham press, Laventham, UK ISBN 0-85296-874-4 (1995),

This Page Intentionally Left Blank

INSTABILITIES IN SILICON DEVICES Silicon Passivation and Related Instabilities G. Barbottin and A. Vapaille (Editors) © 1999 Elsevier Science B.V. All rights reserved.

233

CHAPTER 3

DIELECTRIC BREAKDOWN IN Si02 A survey of test methods by D.R. WOLTERS(i), J.F. VERWEW), and A.T.A. ZEGERS-VAN DUIJNHOVEN(i)

Key items Dielectric strength Pre-breakdown Degradation Breakdown fields Charge to breakdown Breakdown models Test methods

(1) Philips Research Laboratories Prof. Holstlaan 4 5656AA Eindhoven Pays-Bas (The Netherlands)

(2) Twente University Fac. El. Engineering P.O. Box 217 7500AE Enschede Pays-Bas (The Netherlands)

234

D,R, Walters et al.

Abstract of Chapter 3. Dielectric breakdown in Si02- A survey of test methods This chapter updates Chapter 6 of Volume 1 and reviews the testing methods used for characterizing the breakdown of capacitors with special emphasis on MOS capacitors. The mechanism of breakdown is described by the "Q^,^ model" or "charge-to-breakdown model", based on the continuous degradation and eventual breakdown caused by charge leaking through the capacitor This is explained briefly and the degradation of the stressed capacitors is discussed in more detail. The main proof of the Q^^ model is found by comparing the different testing methods and showing that all the statistical results merge into the same Q^^ distribution law. Apparent differences in various test results are caused by obvious effects such as current confinement and local breakdown. The impact of this unifying model, the physical meaning ofQ^^ and £,^^ and the correlation of the two are studied. Recent literature on other models is briefly discussed. Resume du chapitre 3. Le claquage des oxydes de siliciunL Une revue des methodes de test Dans ce complement au chapitre 6 du volume 7, nous passons en revue les methodes utiUsees pour mesurer la tenue au claquage des capacites MOS. Le mecanisme du claquage peut etre explique par un modele qui prend en compte la charge qui circule dans Voxyde avant claquage (le "Qfj^ model"). Nous expliquons brievement pourquoi, et comment, cette charge provoque une degradation progressive du materiau dielectrique et peut conduire a sa destruction. La validite de ce modele est confirmee en comparant les techniques de test et en montrant que tous les resultats statistiques se fondent dans une seule et meme loi de distribution. Les ecarts observes entre les resultats obtenus avec differentes methodes de test sont dus a des effets evidents tels que le confinement du courant et le claquage premature dufait des conditions locales. Nous etudions Timpact de ce modele unificateur ainsi que la signification physique de Q^^ et de ^^^ et de leur correlation. D'autres mode les, recemment publics sont egalement discutes brievement. Zusammenfassung zu Kapitel 3. Der Dielektrische Durchbruch in Si02' Ein Uberblick iiber die Testmethoden Dieser Artikel bringt eine Ubersicht der Testmethoden fiir die Charakterisierung des Durchbruchs von Kondensatoren mit spezieller Betonung der MOS-Kondensatoren. Der Mechanismus des Durchbruchs wird durch das "Q^^^Modell" oder "Ladung-bis-Durchbruch-Modell" beschrieben, dem eine kontinuierliche Degradation und eventueller Durchbruch zugrunde liegt, die durch Leckladungstransport durch den Kondensator verursacht werden. Dieses wird kurz erkldrt und die Degradation der belasteten Kondensator in genaueren Einzelheiten erkldrt Der Hauptbeweis fiir das Qf^^Modell wird aus dem Vergleich der verschiedenen Testmethoden gefiihrt und aus der Tatsache, dass alle statistischen Ergebnisse in dasselbe Q^^^ Verteilungsgesetz mitnden. Scheinbare Unterschiede bei den verschiedenartigen Testergebnissen sind durch augenscheinliche Effekte wie Stromverengung oder lokaler Durchbruch erkldrbar. Die Auswirkung dieses einheitlichen Modells, die Physikalische Bedeutung von Q^^ - und ^^^ und die Korrelation der beiden werden untersucht. Diejungste Literatur Uber andere Mode He wird kurzfristig diskutiert.

Dielectric Breakdown in Silica Chapter 3 : Dielectric breakdown in Si02 Table of contents List of symbols used 1. Introduction 2. The Qbd model 2.1 Energy dissipation in the pre-breakdown stage 2.2 The charge needed for a breakdown, Q^^j 2.3 Energy dissipation during breakdown 3. The degradation of the capacitor 3.1 Lowering of the effective barrier height 3.2 The space charge evolution 3.3 Inhomogeneous injection 4. A review of recent literature 4.1 The impact ionization breakdown model 4.2 The hole-trapping breakdown model 4.3 Discussion of the hole-trapping model 4.4 Discussion of the Q^d breakdown model 5. The testing methods 5.1 The ramped-voltage test 5.2 The constant-voltage test 5.3 The ramped-current test 5.4 The constant-current test 6. A comparison of the test methods 7. Correlation of Q^^ and ^^d values 8. 4bd and Q^^ values are material properties 9. Conclusions 10. List of References Errata of Chapter 6 of Vol. 1

235

236

D,R, Walters et aL

List of symbols used A C E

cm2

4bd I

F/cm2 J J/cm2 J/cm2 J/cm2 V/cm V/cm V/cm A

Ilimit

A

Etotal Edisp Eieak

^

Sox

Icrit J Jcrit

Q Qbd Qdisp

tbd V

AJcnfi A/cm2 C/cm2 C/cm2 C/cm2 s V

^ox

cm F/cm

Y

-

1/X

1/s

Xox

Capacitor area Capacitance per unit area Energy Total energy dissipated per cm^ of the capacitor Displacement energy stored per cm^ of the capacitor Total energy dissipated per cm^ of the capacitor before breakdown Electric field Electric field in the oxide Value of ^ x at breakdown Current Preset current level above which a capacitor is considered as having broken down Injected current limit above which Q^j drops over several orders of magnitude Current density Injected current limit above which Q^^ drops over several orders of magnitude Charge fluence flowing through the capacitor Charge fluence leading to breakdown for a capacitor Charge density stored on the electrodes of a capacitor Duration of stress until breakdown Voltage applied to the capacitor Oxide thickness Dielectric constant of the oxide Field acceleration factor Instantaneous breakdown rate

Dielectric Breakdown in Silica

Til

1. INTRODUCTION Silicon oxide layers, under bias, display the phenomenon of dielectric breakdown. In the first volume in this series [1], breakdown and wearout phenomena in Si02 films have been described in Chap. 6. These phenomena are studied in capacitors with the aid of different test methods. The basic principles underlying these test methods have already been given in that chapter. However, since Chap. 6 was published (1986), more data have been obtained and more papers have been published in this area, making an update indeed necessary. This update is given in this chapter, with emphasis on the different test methods and their relative advantages and disadvantages. Although in the different test methods the capacitors are stressed under different conditions, the mechanism causing breakdown is the same. The driving force behind this mechanism is the energy dissipated during the stress which degrades the dielectric. We show in Section 2 that the pre-breakdown degradation is intimately related to the dissipation of the electronic charges in the dielectric and at its interface with the electrodes. The more electronic charge the more degradation. Breakdown is then the event following protracted degradation when the energy still stored in the capacitor is released. The total amount of charge to breakdown or Q^j is essential for breakdown. The breakdown model based on accumulative degradation has been called the "Qbd" model or "charge-tobreakdown" model. In Section 3 we show that the pre-breakdown degradation can be explained in terms of several stress-induced phenomena namely: the evolution of the space charge, the generation of interface states and current confinements effects. Other breakdown models exist. Two of them are reviewed in Section 4: the impactionization model and the hole-trapping model. The latter explains just like the Q^j model that pre-breakdown damage is due to a critical chargefluencebut assumes also a large amount of hole trapping rarely observed. We show that the Q^^^j model does indeed seem to better explain experimental data than do other models. Four methods used to measure breakdown in capacitors are reviewed in Section 5: The ramped-voltage test, the constant-voltage test, the ramped-current test and the constant-current test. The relative advantages and disadvantages of these methods are compared. We show in Section 6 that the distributions of Q^^ values obtained with the different testing methods can be readily compared, when the conditions at breakdown i.e. current and voltage at breakdown are not completely different. The reason for this, as explained in Section 7, is that the sets of experimental Q^^ and ^bd values, depend on the confinement and hence on the final current densities at breakdown. We finally emphasize in Section 8 that Q^^^ and ^^d values are both material properties. Material properties such as maximum strain and stress are important factors in mechanical breakdown. We show that Q^^ is analogous to the maximum strain at breakdown whereas, ^^d is analogous to the mechanical stress at breakdown.

238

D,R. Walters et al.

2. THE Q B D M O D E L

Several models have been proposed in the last years to explain the characteristic features of oxide breakdown. Since Vol. 1 of this series was published, the Q^j or charge-to-breakdown model has proven, in our opinion, to be the most successful. Therefore we will describe it in some detail while the other major models will be shortly discussed in Section 4. To cause a breakdown in a capacitor a combination of stress conditions is needed. This means that there is no such thing as a critical field or a critical current below which no breakdown will occur. In most cases, capacitors will breakdown at any voltage or current as long as the stress is sustained long enough. On the other hand, capacitors can withstand extremely high fields or very large currents for a short time [2]. This is due to the fact that a breakdown in a capacitor occurs only after dissipation of a minimum amount of energy [3]. This energy dissipation which occurs in the pre-breakdown stage degrades the dielectric material and forms a low-resistance path between the electrodes. When the low-resistance path connects the electrodes, the breakdown event itself takes place and the residue of the stored energy is then dissipated. The latter energy explosion generates the microscopically visible damage [4] [5] [6]. 2.1 ENERGY DISSIPATION IN THE PRE-BREAKDOWN STAGE

The energy stored and dissipated in the capacitor before breakdown can best be illustrated by a plot of the total charge density, Q, needed to apply a voltage, V, across the capacitor. This is depicted in Figs. 3.1.a and 3.1.b\ At low voltages, Q, is practically equal to the displacement charge density, Qdisph stored at the electrodes of the capacitor. Qdispi varies linearly with V, as visible in Fig. 3.1.a. At high voltages, however, Q > Qdispi since charges leak through the capacitor. The V vs Q curve becomes non-linear, as visible in Fig. 3.Lb. The total area under the V - Q curve, (= J VdQ), is proportional to the total energy consumed by the capacitor. In the linear part, the energy, 1/2 CV^ , is stored by the displacement charge, hence in a completely reversible way. (This is equivalent to the mechanical energy stored in a strained spring.) In the non-linear part, the energy is dissipated by charge leakage through the dielectric and by the irreversible process of charge recombination at the opposite electrode. (This is analogous to the plastic deformation of a spring.) When the stress is performed in the non-linear part of the charging curve and then released, only the energy which is stored reversibly in the capacitor can be recuperated. After the release, a certain amount of charge is lost and the corresponding amount of energy, Eie^k' has been irreversibly dissipated in the capacitor. The dissipated energy, indicated by the nonshaded area, at the left, under the curve in Fig. 3.1.b, can be expressed as: ^ Thesefigurescan be compared with a stress-strain plot obtained for mechanical breakdown [5].

Dielectric

Breakdown

rV Eleak = Etotal " ^disp = J^ ^^Q-

239

in Silica

(3.1)

VQ^isp

where Q is the charge per unit area which has been suppUed by the external circuit to the capacitor and Q^jsp is that fraction of Q which has been stored on the electrodes. The last term of Eq. (3.1), i.e. the displacement energy per unit area, will not be dissipated as long as the capacitor has not experienced a breakdown.

conserved energy

dissipated energy

0) O) CD

o

1/2 CV2

>

dissipated at breakdown a)

total charge

b)

total charge

Fig. 3.1 Stress versus charge plot depicting the energy dissipation during stress and breakdown, a) In the low voltage regime almost all energy can be recovered, b) After substantial charge injection a lot of energy has been dissipated. The stored energy 1/2 CV^ will be dissipated when breakdown occurs. The energy is indicated by the area under the curve. (See text)

The energy lost by leakage, Ei^ak' partly vanishes in the form of heat and is partly stored in the dielectric in the form of degradation energy. The degradation is revealed by the presence of an increased number of interface states and traps. Under stress Ej^ak increases continuously, depending on the rate of charge leakage through the capacitor. The degradation generates a conducting path which grows between the electrodes. The growth continues until the two electrodes are connected and breakdown occurs [5]. 2.2 THE CHARGE NEEDED FOR A BREAKDOWN, Qg^

To degrade a dielectric, energy is needed but there is no energy dissipation without charge flow. When a dielectric is in a degraded state it contains broken bonds and a certain amount of disorder. Therefore a certain amount of energy has to be supplied to bring the dielectric into this disordered state which corresponds to a higher energy content^. ^ To generate a path of atomic dimensions through a dielectric, a large amount of energy is needed. For a single path of 100 X 100 X 1000 A^ = 10"^'^ cm^ about 33.10-1^ Joule = 2.10^ eV is needed, since the formation energy of Si02 is 33 KJ/cm^. The energy dissipation of the total charge Q^^j is, however, orders of magnitude larger.

240

D.R. Walters et al.

The energy of the charge carriers is dissipated in the bulk of the dielectric and at the interface where the charge leaves the dielectric: • In the bulk of the dielectric, electrons can dissipate their energy in two ways: by breaking bonds (and then creating defects) and through phonon interaction. However, the energy required to break a bond is > 4 eV and the electron free path is only about 30 A. Thus for moderate applied fields only a few electrons will gain enough energy to break bonds and most of the electronic energy will be lost through phonon interaction. For a review of the charge transport in Si02, see references [7] [8], and also Chap. 5 of Vol. 1. • At the interface where the injected charges leave the dielectric, the energy is dissipated over a relatively short distance. Electrons which leave the conduction band at the anode have an energy of at least 3 eV. Thus relatively low fields are sufficient to increase their energy to 4 eV or more. Hence, in contrast with the dissipation in the bulk, all charge carriers dissipate at this interface an energy quantum sufficiently large to break bonds. The dissipation of energy is illustrated in Fig. 3.2. A breakdown will occur when a sufficient amount of charge has dissipated its energy. It has been shown experimentally that breakdown will occur at all fields as long as a sufficient charge transport takes place [9]. On the other hand, high fields alone are not sufficient for a breakdown to occur, since the breakdown process needs a certain amount of dissipated energy and hence charge transport. In other words, the value of Q^^ (i.e. the charge fluence that has flowed through the capacitor until breakdown) plays a more critical role for breakdown to occur than does ^b^ (i.e. the value of the oxide field at breakdown).

Si(-)

SiOc

M(+)

Fig. 3.2 Electrons tunnel through the barrier into the conduction band of the oxide. When they drop to the Fermi level of the anode they release an energy > 3.1 eVy which is sufficient to break Si-0 bonds. The dissipation causes a degradation which eventually forms a low-resistance path.

Dielectric Breakdown in Silica

241

2.3 ENERGY DISSIPATION DURING BREAKDOWN

When, by degradation of the dielectric, a low-resistance path is formed, this path will eventually interconnect the two electrodes. The positive and negative displacement charges recombine then and Edjsp, still stored in the capacitor (shadowed area in Fig. 3.1.b), is released in a very fast energy explosion. The displacement energy per area, expressed in [J/cm2], is given by:

/r

- L ^YL _ ^

^disp - 2

^

.2

- 2 ^(^^^bd ^ox

(3.2)

where A is the area of the capacitor, ^bd the applied field at breakdown, Xox the oxide thickness, and e^^ the dielectric constant of the oxide film. It is this energy, E^isp, which causes the visible damage after breakdown. The energy dissipation is so fast that the capacitor partly melts and evaporates and a sort of crater is formed by which the capacitor can be shorted.

Fig. 3.3 The final breakdown of a capacitor leaves a crater, whose dimensions can be calculated fi-om the energy, 1/2 CV^, stored in the capacitor just before breakdown.

For a field of 10 MV/cm and Xox = 300 A and a capacitor with an area of 1 mm^ Edisp is equal to 5.1 x 10-7 joule. When this is used to evaporate silicon, a sphere with a radius of 1 [im can be evaporated, since the heat required to warm up and evaporate silicon is 4.2 105 Joule/cm3. This value of 1 |im is about the diameter of the craters which are observed after a breakdown in MOS capacitors [4]. (See Fig. 3.3.)

242

D.R, Walters et al.

3. THE DEGRADATION OF THE CAPACITOR The degradation during the stress period and the evolution of the low-resistance path through the dielectric are important. This degradation is very fast for high fluxes of electronic charges and slow for very low current densities. Hence, at low applied fields (currents) it can take a very long time, whereas for very high fields (currents) breakdown can occur almost instantaneously. The magnitude of the field and of the current determine the total stress time needed to reach breakdown. Their value can change depending on the stress applied and on three stressinduced effects which change the properties of the dielectric. These effects are: • the modification of the effective barrier height at the interface, • the generation of a space charge in the dielectric, • the confinement of the current caused by inhomogeneous space charge effects. These effects will be discussed briefly below. 3.1 LOWERING OF THE EFFECTIVE BARRIER HEIGHT

By injecting a charge, in excess of 10-5 C/cm^, the effective barrier height can be significantly lowered[10]. This change in the effective barrier height is caused by the generation of interface states. This in turn causes the current to increase with time when a constant voltage measurement is performed, or causes the voltage needed to sustain a constant current to decrease with time. Interface states which are located in the bandgap of Si02, at a small distance from the interface, enhance tunneling into the conduction band of the oxide, as illustrated in Fig. 3.4. This affects the "effective" energy barrier and enhances the injection currents by orders of magnitude. The "lowering" of the barrier by stress is heavily field-dependent.

trap assisted tunneling

Fig. 3.4: Interface states cause enhanced tunneling. Due to the location of the states in the forbidden gap in the oxide, electrons tunnel over a smaller distance into the conduction band. Hence, the effective barrier height is lowered.

Dielectric Breakdown in Silica

243

3.2 T H E SPACE CHARGE EVOLUTION

When dielectrics are stressed, charge trapping or, more generally, an evolution of the space charge in the dielectric can occur. If the space charge is distributed homogeneously over the volume and is of the same type as the charge carriers being injected, it may lower the "effective" field at the interface and hence the current density^. In Fig. 3.5 the broadening of the barrier by trapped electrons and the subsequent longer tunneling path are depicted. For constant-voltage stress conditions, the current decreases and the stress time must be longer for a breakdown to take place. The evolution of the space charge is easier to model if the time evolution of trapping is known. The injection current for fixed voltage conditions often decreases according to the following power-of-time law:

J^Jo{tltof

(3.3)

where J^ is a constant and a can take any real value. The total amount of charge flowing through the capacitor up to time t is then given by"^:

Q=\ljo{t'ltofdt'

(3.4)

Fig. 3.5 Trapping causes a lowering of the field at the interface and hence the electrons have to tunnel over a longer distance. It thus causes the injection current to decrease.

0 space charge

iiiiiiiiiiiiiiiiiitiiiiiiiiiii

Depending on the magnitude of a, Q in Eq. (3.4) saturates to a value Q^^t or increases infinitely. For a < -1 the injection current rapidly decreases and Q{t) for a value of a > - 1 the decrease is much slower and Q{t)

r--^oo

> Q^^f, while

->oo.

' A discussion of how the space charge affects the injection barrier can be found in Chap. 10 A of Vol. 2. ^ It should be noted that only a small fraction of this charge is actually trapped inside the dielectric.

244

D.R. Walters et aL

This means that if a < - 1, the total charge flow may saturate at a value Q^^t < Qbd ^^^ never show a breakdown at all. If a > - 1 a breakdown is, however, bound to occur. Exponent a reflects the efficiency of trapping. Trapping induces a counterfield which reduces the field at the interface. If severe trapping occurs the counterfield becomes so large that the injection drops to zero. 3.3 INHOMOGENEOUS INJECTION

Another effect of the space charge evolution is that it may confine the current flow to a small area of the dielectric. When, for instance, trapping occurs only in one part of the capacitor, the current is forced through the remaining part. If the space charge is of the other sign, an inraiediate confinement of the current to that region will occur. In the case of a confinement of the current, breakdown occurs earlier than for homogeneous injection due to the higher local current density. This relation between the decrease in Q^d and inhomogeneous current injection has been deduced not only from the deviations in the current voltage curves [4], but also from light-emission experiments [11]. Inhomogeneous trapping thus causes breakdown to occur for lower Q^d values.

10'^ b

I = ramped

CO

E o O 10 1

-r-N

JQ

O

V = ramped

10^

I / I I I I ml

-2

10

10"

I

I I I I ml

10"

10^

J [A/cm^] Fig. 3.6 Experimental (2^^ values, from constant current tests, denoted by open squares, are plotted against the injection current density. Lines with arrows in the figure depict how charge and current change during the different test methods. To get similar Q^^^ values for different tests the test conditions should be adjusted in order to let the lines intersect the Q^^ (J) line at approximately the same point.

Inhomogeneous injection is predominantly determined by space charge and hence by the ratio of trapping and detrapping in the dielectric. At low current densities the trapping rate is slow due to the small fluence of electrons and most of the traps are not occupied. In this case the current density will be homogeneous. At large current densities the trapping rates are fast due to the highfluenceof electrons and most of the traps are occupied.

Dielectric Breakdown in Silica

245

In that case, the current will find a region where space charge density is relatively low. This causes a confinement of the current and a breakdown occurs at a small overall Q^j. This decrease of Q^j at high injection current densities is shown in Fig. 3.6. The data points (squares) have been obtained experimentally by stressing capacitors at different current densities, J. At higher current densities, the value of Q^^ tends to decrease. This decrease can also occur when the injection current at edges and comers increases due to field enhancement effects. It will be clear that different test methods e.g. ramped or constant voltage stress or ramped or constant-current stress do not yield similar values of Q^^^ since they all cross the Q^j line of Fig. 3.6 at a different location. This makes it difficult to compare such results. We shall see below that the discrepancies in Q^j values can be avoided by choosing the ramping rates and stress currents (or stress voltages) in such a way that the arrowed lines cross at the same point. The fact that different testing methods give similar results is a strong argument for the idea that a continuous degradation by the charge flow through the dielectric causes its breakdown. Before discussing the different test methods and showing that these indeed coincide let us give a short review of other models proposed in the field. 4. A REVIEW OF RECENT LITERATURE At this point it seems appropriate to review some recent literature on oxide breakdown mechanisms. We make a distinction between a modeling in terms of parameters on the one hand and the underlying mechanism on the other hand. Modeling as such is important for translating oxide stress results into practical use conditions. However, there is as yet no general consensus on how the scaling factors are related to the actual physical mechanisms of degradation, which means that extreme care must be taken in drawing firm conclusions with regard to the scaling factors. At the 1991 Intemational Reliability Physics Symposium two tutorials were given on the mechanisms and modeling of breakdown in Si02 [12] [13]. It is remarkable that each tutorial showed a different opinion about the physical mechanism of breakdown. Therefore we will treat this in the following two sections. 4.1 THE IMPACT IONIZATION BREAKDOWN MODEL

In the work of Shatzkes and Av-Ron the model assumes a stochastic process in which the survival probability is a key element. The latter probability is an exponential function of the instantaneous breakdown rate, l/x [14]. An important part of the mechanism is thought to be impact ionization. However, the charge-transport experiments, also carried out at IBM, clearly indicate that this is an unlikely process [15] [16] [17]. This has been corroborated by the calculations of the ionization coefficient by Ferry [18] and by the injection experiments of Weinberg [19]. Moreover, the work of Shatzkes and Av-Ron assumes that the instantaneous breakdown rate, 1/T, is proportional to the current.

246

D,R, Walters et al.

The survival probability which is a function of j l/xdt, is then itself a function of the charge-to-breakdown, Q^^. This means, in our opinion, that the model of Shatzkes and AvRon and the Q^j model merge; the former is derived from a statistical viewpoint and the latter from a mechanistic viewpoint. 4.2 T H E HOLE-TRAPPING BREAKDOWN MODEL

The modeling of the Berkeley school [13] is based on an earlier publication by McPherson and Baglee [20]. These authors found that: 1) the field acceleration factor, y, is a function of temperature and 2) that the activation energy of breakdown is a function of the field during stress. This needs a few words of explanation. The time-dependent breakdown of oxides is a logarithmic function of time and is also strongly dependent on the applied electric field. The field acceleration factor, y, i.e. the increase of log (t^d), with applied field, where t^j is the time for breakdown, is expressed in decades per MV/cm. The knowledge of this field acceleration and the use of a proper model would facilitate the extrapolation to practical use conditions. Breakdown is also temperaturedependent which is expressed through a simple Arrhenius factor with an activation energy. The researchers of the Berkeley school modeled breakdown in terms of thermodynamic relations between parameters. The model is quite successful in describing the results of different authors with a single set of parameters. The proposed mechanism is still debatable since it assumes that breakdown is induced by trapped holes. There is, at breakdown, a critical charge density in the Si02 which is proportional to the number of electrons injected into the oxide, and to the probability of holes being generated. The current is the Fowler-Nordheim tunneling current Jp^ «= exp(- B/^) and the hole generation has the same type of field dependence: ©c exp (- H/^). The time to breakdown, t^j then becomes tbd = ^o

MG/^)

(3.5)

with G = B + H. Figure 3.7 shows how the model was applied to explain the variations of the field acceleration factor, y, as a function of the electric field, ^. The solid line is fitted to the experimental points by selecting a suitable value for G. The modeling of time-dependent breakdown as a function of temperature needs two more steps. First, it is assumed that all defects can be modeled as an oxide thinning. Second, it is assumed that G and TQ are temperature-dependent, x^ is expressed in an Arrhenius form with an activation energy E^ and G is assumed to have a temperature-independent part, so it is expressed in a Taylor series expansion. The result is a proper description of the temperature dependence of a number of experiments on time-dependent breakdown. It is seen [21] that the activation energy increases with increasing time-to-breakdown.

Dielectric Breakdown in Silica '?

T

I'

I

I

247

I

Crook

'

u o

VO^O-IIOOA)

Bermon

^7

§ E o

I-

6

O

u

2

. \

"* I

Hiroyomo ,^^^

I

(200-400A)

Boglee (100A) *"

^

0)

(>400A)

Abe (110A)

2

Nishioko (75A) \

Yomobe (100-500A)

u

Chen (IIOA)

Yomodo (200A)

0)

4

6 8 10 12 Electric Field [MV/cm]

14

16

Fig. 3,7 The electric field acceleration of the time-to-breakdown, after Moazzami [13] and Lee [25]

From the curve fitting, one finds the temperature dependence of parameter G in Eq. (3.5). It appears that the contribution of parameter H (hole generation parameter) to G is about 5 times that of parameter B (Fowler-Nordheim parameter determined in separate current measurements). This means that hole-trapping contributes substantially to the temperature dependence. 4.3 DISCUSSION OF THE HOLE-TRAPPING MODEL

The model based on hole-trapping and field enhancement, until a critical field is obtained, assumes that a critical amount of charge must be injected. It is therefore comparable to the Qbd model based on the generation of damage and on a critical charge, Q^^j, needed for a breakdown. One of the problems of the hole trapping mechanism is that such high densities of charge should be trapped. This can be elucidated in the following way. In Fig. 3.8 we can see that the time-to-breakdown, %^, decreases with increasing field. If the increase of %^ below ^ ^ = 19 MV/cm is due to the fact that the dielectric must first trap holes, until the field at which breakdown occurs is reached, we can estimate how many holes are to be trapped under an applied field of l^^ = 9 MV/cm. Let us assume that the critical field for breakdown, ^ ^ t ' which is, according to the model, the local field in the dielectric at which the oxide fails, is reached at ^ ^ t ^ 19 MV/cm. Then, it follows that the sample breaking down at 9 MV/cm, must trap at least 2.10^^ charges/cm^ which means that when spread over an oxide layer of 100 A thickness, a volume density of 2.101^ charges/cm^ [22] is needed. This means that holes are packed with a mean distance of 36 A. This is not very realistic since often capacitors on 100 A oxide show no sign of charging at all before breakdown occurs. Moreover, the fact that the damage generated by injection cannot be restored at temperatures up to 400''C (at which holes are easily detrapped) does not support the critical hole-trapping model.

D,R, Walters et al.

248

Another argument against the breakdown model based on hole-trapping is that the activation of hole-trapping [23] [24] with temperature is opposite to the activation of breakdown with temperature. While breakdown is facilitated at higher temperatures (Qbd ^ when T t), positive charges in contrast detrap at higher temperatures. Hence, the injected charge needed for a breakdown by a high field caused by trapped holes should increase with temperature, which is the opposite of what is observed. eox [MV/cm] 12 14 16

.06

.08

20

.1

.12

1/f^ox [cm/MV] Fig. 3.8 The time-to-breakdown r^^ is plotted as a function of the applied electric field, after Moazzami [26]. 4.4 DISCUSSION OF THE QB^ BREAKDOW^N MODEL

The results of Fig. 3.8 can be explained in terms of the Q^d model as well. When charge injection occurs by the Fowler-Nordheim mechanism, it does so according to the equation JpN "^ ^^ ^xp(- B/^). The Qbd model assumes: In QIJJ^ = In (Jpj^ ti^j) = constant

(3.6)

Inthj oc-ln7^^< | - 2 1 n < ^

(3.7)

and thus

where B -- 265 MV/cm can be calculated solving the Fowler-Nordheim equation and assuming an effective barrier height of 3.1 eV. This B value is indeed much less than the value of 350 MV/cm calculated from the slope of Fig. 3.8. This mismatch can be caused by the fact that at high current densities Q^j is substantially less than at low current densities due to local field differences.

Dielectric Breakdown in Silica

249

These can be caused by field enhancement at edges and comers of the capacitors [11]. The higher fields at the comers increase the local injection and lower the overall Q^jHence, instead of an additional mechanism of hole-trapping, the decreasing Q^^ due to field enhancement directly explains Fig. 3.8 and the slope of 350 MV/cm. Some more information on the field acceleration factor of the time-to-breakdown is given in Fig. 3.8. It shows indeed that the field acceleration factor itself is a function of field, ^Qx- This can have several causes. The first one is that the enhancement at comers and edges plays a dominant role. The second obvious reason is that the experimental data included "defective" capacitors, at least at low fields^. This is certainly the case for fields below 5-6 MV/cm for which the measurement of an "intrinsic " breakdown takes an extremely long stress time ( » 10^ s) per capacitor. Therefore the field acceleration factor has to be handled with great care when t^d values at low fields are to be calculated from measurements performed at high fields. The use of Q^d measurements for predicting the end of life of capacitors is also debatable. An easy way might be to divide the measured value of Q^^ ^Y the injection current at the operational field. This method would presume, however, that the injection current stays the same over the whole operational period. The acceleration factors for injection and breakdown are not stable upon degradation and therefore can easily lead to totally wrong predictions. This limits the usefulness of Q^d measurements for lifetime predictions. The distribution of Q^d values does teach us, however, something about the quality of the oxides and/or of the homogeneity of the current injection. High Q^d values often coincide with high quality oxides but the value of the intrinsic Q^d is no guarantee at all for long capacitor life. One must see Q^d values as representative of material properties. (We will elucidate this point in Sect. 8). Low quality material, contamination, local defects, stractural injection points can all be revealed by the measurement of the Q^d value. Predicting the lifetime of a capacitor is, however, a hazardous exercise. 5. THE TESTING METHODS The methods used most often to test breakdown in capacitors are based on: • • • •

increasing the voltage (rather the applied field) in steps until the current suddenly increases, keeping the voltage at a fixed value until the current suddenly increases, increasing the current in steps or by a ramp until the voltage suddenly drops, sustaining a current at a constant value until the voltage suddenly drops. These methods and their relative advantages and disadvantages will be discussed next.

The distinction between "defective" and "intrinsic" failures can be made only after a proper statistical analysis. Plotting distributions on probability paper often reveals the bimodal character of the distributions. We will show distributions for different test methods in Fig. 3.13.

250

D,R. Walters et aL

> limit

t [sec] Fig. 3.9 Voltage and current are plotted versus stress time during a ramped-voltage test. The voltage ramp (dV/dt) and the current limit ln^if should be adapted when comparing different dielectrics. See text. 5.1 THE RAMPED-VOLTAGE TEST

In the classical tests used to measure the dielectric strength, the conditions for breakdown are obtained by increasing the voltage stepwise and by measuring the current at each step until the leakage current exceeds a certain preset value (Iiim)- Instead of steps, a continuously increasing voltage can also be used, which, however, may be rather inconvenient, since the displacement current, CdV/dt can then become significant^ . The test conditions are depicted in Fig. 3.9. When comparing different oxide films, one should adapt the ramp rate of the voltage, so that an identical field ramp is applied to films having different thicknesses. When comparing capacitors with different areas one should adapt the current limit so that the current density levels are the same for all different areas (e.g. 0.01 A/cm^). Very often a capacitor conducts the preset current density without experiencing a breakdown. This is understandable since at high fields the current tunneling through the barrier can be substantial^. This tunneling current is then mistaken as the breakdown current and all non-defective capacitors seem to "fail" at the same "intrinsic" value of the field. Remeasuring shows, however, that the capacitor can be stressed a second time to the same level. Increasing the current limit to higher levels may have the effect that these capacitors really fail and are recorded in the proper way. However, at these high currents, broken down capacitors often cannot reach the high current level when they possess a high series resistance. In such a case a failure is not recorded at all. Therefore it is better not to choose the current limit too high.

^ For instance for a capacitor of 1 nF and a ramp rate of 100 V/s the displacement current is 10'^ A. ^ In an "intrinsic" MOS capacitor a tunneling current of 0.01 A/cm^ flows at a field of about 10 MV/cm.

Dielectric Breakdown in Silica

251

Re-measuring unfailed capacitors can be repeated a number of times. When a capacitor needs a certain charge, Q^^^ to breakdown, and this charge is of the order of 10 C/cm^ this can require a great number of times. When the stress across the capacitor is each time interrupted after a period of 10 ms at 0.01 AJcirfi, less than 10"^ C/cirfi has flowed through the capacitor, which is 10"^ times less than the required Q^^j value. Remeasuring the capacitor 10^ times until a "real" breakdown occurs can be a little cumbersome. The advantages(+)/disadvantages(-) of the field ramp method are sunmiarized in the following: • (+) this method is the conventional way of testing the dielectric strength and it gives information about the number of "defective" capacitors, • (+) it is a fast method. Capacitors take only a few tenths of a second to be measured. It is so fast that a very large array of capacitors can be tested in a reasonable amount of time (e.g. 100 X 100 capacitors within 1.5 hrs at a ramp rate of 20 MV/cm/s), • (-) when capacitors are tested with this method, very often no real breakdown takes place and the tunneling field is mistaken for a dielectric strength. In a distribution it gives the wrong impression that all capacitors fail at the same field, • (-) only the breakdown voltage or the ^\^^ value of the failures are obtained. Unlike other methods which also give information on Q^j the ramped-voltage method is too fast to give a reliable current measurement. Integrating the current through the capacitor at high ramp rates is impractical, if not impossible, and no reliable value of Q^^ can be obtained. 5.2 T H E CONSTANT-VOLTAGE TEST

The constant-voltage test is widely applied for reliability testing. In most cases the voltage is chosen such that testing is performed for applied fields in the range of 4-7 MV/cm. The detection of breakdown occurs by measuring the current flowing through the capacitor. Whenever the current exceeds a certain preset value, Iiimit? the capacitor is considered as having experienced a breakdown. The constant-voltage test is depicted in Fig. 3.10. The tunneling current density J^unn i^ roughly lO-'^ AJcrrfi for a capacitor stressed at 7 MV/cm. The critical current Ij^jj^t must be chosen substantially higher than Area x J^unn- F^^ higher applied fields the value of Iiimit? i^^st be chosen even higher, in order to account for the higher tunneling current. The problem with this method is that, when the stressing field is chosen too low, the "intrinsic" capacitors seldom fail within an acceptable time. For an "intrinsic" capacitor with a Qbd of 10 C/cm^ and a stressing field of 7 MV/cm, which causes a current density of « 10"^ A/cm^, a stress period of 10^ seconds « 3 years would be required. Thus in most cases only the "defective" capacitors will fail. These, indeed, have Q^j values which are orders of magnitude smaller.

D,R, Walters et aL

252

V >

i break down

t [sec] Fig. 3.10 Voltage and current are plotted versus stress time during a constant-voltage test. The current limit should be adapted to give the same density level for capacitors with different areas.

Increasing the field and the temperature can shorten the stress period considerably but even then capacitors may display no breakdown, for instance when, because of severe trapping, the injected current decreases with time. The advantages(+)/disadvantages(-) of the constant-voltage test are: • (+) this method is the conventional way of testing the reliability of capacitors, • (+) the stressing fields used are close to the practical operating conditions. The test can thus often be combined with bum-in tests, • (+) when they are stressed in parallel, a large number of capacitors can be tested simultaneously. This may reduce the total time consumed for the test, • (-) low Qbd or low breakdown voltage values cannot easily be measured, • (-) "intrinsic" capacitors can take an unacceptably long time to reach a breakdown, • (-) when trapping is sufficiently fast and homogeneous, the injected current decreases very rapidly and there may be no breakdown at all. 5.3 THE RAMPED-CURRENT TEST

In this method the current is increased step-by-step in logarithmic increments until breakdown occurs. The breakdown is observed when the voltage, needed to sustain the current, drops suddenly to a lower value. The test signal and the monitor signal are depicted in Fig. 3.11. The method is very similar to the ramped-voltage method but does not have some of its drawbacks. For instance, in the ramped-voltage method the tunneling current is often mistaken for a breakdown current. This is not the case in the ramped-current method. A substantial drop in voltage indicates that a real breakdown has occurred.

Dielectric Breakdown in Silica

1

V

253

^^^J""^"^ break ^ down

>

E^

t[sec]

o

•

Fig, 3.11 Voltage and current are plotted versus time in a ramped-current test. The current is ramped in steps.

Furthermore, it is very easy to integrate the current steps in order to find the value of Q^j. This is almost impossible to acquire in a fast voltage ramp method. The ramped-current method is or can be just as fast as the ramped-voltage method. It yields both the values of ^^j and of Qbj for every capacitor. One advantage is that values of ^^d ^^^ Q^^ can be compared. The correlation of these two parameters can reveal the origin of the statistical spread (See Section 7). Compared to the constant-current method (see next), the ramped-current technique has the drawback that, when the currents are very rapidly ramped, breakdown then occurs above J^nt, and the measured Q^^ values are mostly smaller than those obtained for lower currents. (J^nt has been defined in Chap. 6 of Vol. 1 as the current density above which the value of Q^d decreases substantially). The drop of Q^j at high currents has been discussed in SubSection 3.3 and is illustrated in Fig. 3.6. Another drawback can be that the currents become so high that a capacitor is rapidly recharged after a breakdown, when the breakdown is self-healing^. If the recharge time is shorter than the sampling time of the voltage monitor, the testing system may overlook a breakdown or even a number of breakdowns. This yields exorbitant values of Q^^j. At very high currents a substantial part of the voltage drop may take place over the contact resistances or the series resistance in the substrate. In that case, the voltage drop at breakdown can be overlooked, since it is smaller than expected. The advantages(+)/disadvantages(-) of the ramped-current test are: • (+) this method is very fast and can be as fast as a ramped-voltage method, • (+) at breakdown, both a ^^^ and a Q^d values are measured. Correlations can reveal the origin of the spread. ^ Self-healing occurs when the electrode material is removed at the breakdown spot by the capacitor discharge which consequently removes the electrical short in the capacitor.

254

D,R. Wolters et al.

• (+) the test can measure "defects" and "intrinsic" failures over a very large range of Q^d values, • (+) every breakdown is real and the Q^^ values are measured with a relative precision, • (-) for too fast ramp rates and high Q^d values, the current can increase above 1^^^ and relatively low Q^d values are then measured, • (-) for too high current densities and with self-healing capacitors, a breakdown can be overlooked if the sampling time of the voltage monitor is not very short, • (-) for too high current densities, the series resistance may cause a voltage drop over the test sample, which leads to an overestimation of ^^d5.4 THE CONSTANT-CURRENT TEST

In the constant-current test a constant current is forced through the capacitor, and one records the voltage needed to sustain the current. If the voltage suddenly drops below, for instance, 80% of its value, the capacitor is considered to have had a breakdown [27]. Measurements should be performed in a fast sampling mode since capacitors can restore themselves rapidly after a breakdown. When breakdown occurs at high currents, then the capacitor can be recharged within the sampling time, and the breakdown is then overlooked. The stress current and the monitoring of the voltage are illustrated in Fig. 3.12.

V >

^ ^ ^ break ' down

1 ^

t [sec] Fig. 3.12 Voltage and current are plotted versus stress time in a constant-current test.

This method is the quickest way of forcing a capacitor to breakdown. It is a very convenient test method if, for instance, the quality of a known dielectric has to be monitored on a regular basis. However, for a completely unknown dielectric there are some problems in choosing the correct current density.

Dielectric Breakdown in Silica

255

• If the current density, J, is too high, the value of the intrinsic Q^^j will be small due to the fact that J > J^^i-if This then mostly causes the Q^j values to have a large spread. It could give the wrong suggestion that the overall quality and reproducibility are low. • If J is too small, a single measurement can take a very long time due to the high value of Qbd The best thing to do is to measure first Q^j values at different current densities for a small number of capacitors over a wide range of currents. The result will be as shown in Fig. 3.6. From this result one can take the value of J just at or below J^j-jt- The measurement is then relatively quick, avoiding too small Q^j values. As in the case of the ramped-current test, values of ^5^ and Q^^j can be compared. The correlation of these two parameters can reveal the origin of the statistical spread. A disadvantage of the constant-current method, is that small values of Q^^ are difficult to measure. At relatively high currents they cannot be measured due to the very short time needed for a breakdown. For instance, a current density of 0.1 A/cm^ and a short integration time of 1 msec yield a minimum value of 10~4 C/cm^. "Defective" capacitors often have Qbd values which are below 10"6 C/cm^. The advantages and disadvantages of the constant-current test can be summarized as follows: • (+) this method can be the quickest way to force a capacitor to breakdown, • (+) both Q^^ and ^^^j values are obtained. Correlations can reveal the origin of the spread, • (-) a preliminary knowledge of J^nt is necessary. This is obtained by measuring similar capacitors over a wide range of injection currents, • (-) very small values of Q^d (as occurs for "defective" capacitors) cannot be measured, unless the current density is chosen very low. Then, however, testing "intrinsic " capacitors takes an extremely long measuring time. 6. A COMPARISON OF THE TEST METHODS Historically, the different stress tests have been introduced to measure properties which were assumed to be descriptive for the dielectric. For instance, the dielectric strength in a ramped-voltage test or the lifetime in a fixed-voltage test. Only recently has one reached the conclusion that there are no real differences between the tests [3]. This might sound unrealistic since defects often show up in one test and not in another. This is, for instance, the case when distributions of constant-current tests are compared with a fast ramped-voltage test. In the latter case the ramp is often so fast that "defective" devices do not break down fast enough and are considered as "intrinsic". This effect can also occur for current tests with different currents values. For instance, Olivo et al. [28] have observed a higher defect density for lower current stresses, which suggests that the number of defects is stress-dependent.

D.R. Walters etal

256

Hence, to interpret breakdown results, a "sound" distinction must first be made between intrinsic and defective breakdown. The presence of a defect often confines the current to a local spot and gives rise: to a strong local wearout and, thus, to an early breakdown. This reduces Qbd by orders of magnitude and also reduces ^bj . To make this distinction the fraction of "defective" capacitors must either be known or be reduced to an insignificant level. A statistical approach shows the fraction of "defective" capacitors, while the use of small-area capacitors reduces this fraction. We shall next compare whole distributions and thus account for the difference between the intrinsic values and those of defective capacitors. This is illustrated in Fig. 3.13, which shows the distribution of Qbd values obtained by the four test methods. The figure is a probability plot according to an extreme value distribution where the cumulative probability for failures, F, is a double exponential function of the value of Qbd/Qbd ^^®^® Qbd is the modal value of Qbd- Taking twice the logarithm shows that In [- ln(l - F)] oc Qbd- The probability plots have been discussed in Chap. 6 of Vol. 1. As can be seen, all the different test methods yield the same "intrinsic" Qbd value. Furthermore, approximately the same percentage of "defective" capacitors are observed for the different test methods.

1 2 3 4

= = = =

const, current const, voltage ramped voltage ramped current

0 .I

^

-2h poly-Si 110 Ang oxide p-substrate Si

-4

I lllllJ

10*

10"

10>o

Qbd [C/cm2]

I I IIIM

10 ^

Fig, 3,13 Ramped and constant-voltage and current-test results are compared Note that the intrinsic values and defect values match in the four test methods.

Dielectric Breakdown in Silica

257

7. CORRELATION OF QBD AND ^BD VALUES The intrinsic values of ^^d ^^ Qbd obtained from measured distributions may deviate from the expected normal. They can be too small or too large or have a large spread. Some of the possible deviations will now be discussed. • The ^b^i values are too small: this is possibly caused by a substantial density of positive charges or interface states which are homogeneously distributed over the area. Likewise surface roughening or a very large number of defects, which also lower the "effective" barrier height, yield ^^d values which are too small. In the latter case, Qt,^ values are small too, and both are widely distributed. • The Qi,^ values are too small: this is often caused by structural defects or by a local thinning of the gate oxide at edges (e.g. "bird beaks"). Field enhancement at gate edges or asperities on the injecting interface may cause inhomogeneous injection and small Q^d values. Inhomogeneously distributed traps may also result in current confinement. Note that the inhomogeneity lowers the value of Q^j. When, in contrast, the amount of asperities is very large and homogeneously distributed over the gate area, the injection is fairly spread out, causing relative high values of Q^^. • The ^bd values are too large: this may be due to severe trapping. For instance if M atoms diffuse into Si02 and form electron traps close to the gate, this causes an increase of the barrier width. In that case, the applied field has to be increased to obtain a certain current density. This results in higher ^^d values. Often in these cases the Q^^j values are smaller than without trapping, due to inhomogeneous injection. • The Qb^ values are too large: at very high current densities, the rate of charging of a capacitor is very high. If after a fast charging, a self-healing breakdown takes place, the capacitor may restore before the drop of the voltage has been monitored. In this case exorbitant Q^j values may be observed. It is often useful to draw a plot of Q^^^ versus ^i^^j values for a certain distribution. The possible shapes of such plots are depicted in Fig. 3.14. The correlations between ^^^ and Qbd values are described for the four numbered correlations (1-4). These are discussed below. Differences in the shapes of the Q^d versus ^^^ pl^^s may in the first place be due to the different test techniques used. • When a ramping test technique is used, there is a certain probability that the current will increase above J^nt' ^^ which point the Q^j value decreases due to current confinement effects. • When a constant-current or constant-voltage technique is used, this probability is less. Above J^j-it, the Q^^j distribution will tend to spread out, while the ^^j distribution tends to narrow. Below J^nt the reverse happens: the Q^d distribution is narrow while the ^bd distribution is wide. An example of Qbd(^bd) P^^^s obtained by constant-current and ramped-current measurements is given in Figs. 3.15 and 3.16.

258

D,R, Wolters et aL

C\J

E o

x> JD

o O

^bd [MV/cm]

•

Fig. 3.14 The Qi^^ versus t^i^^ plots can have different shapes. The meaning of the four numbers is discussed in the text.

There are also influences of the manufacturing processing which explain the shape of the Q^^ versus ^^d plots. The shapes of the plots, as depicted in Fig.3.14 and numbered 1-4, are explained next: 1. A spread in Q^^j but not in ^^^ values. The absence of spread in ^^d values reveals that the injecting interfaces of all capacitors have similar properties. It can be concluded from the spread of Q^j values that the growth of the low-resistance path varies. Most probably, the dielectric contains a large density of traps or interface states. 2. A spread in ^^^ but not in Q^^ values. This often occurs for irregular surfaces (e.g. "sacrificially oxidized" surfaces) or surfaces with an irregular distribution of interface-states or traps close to the injecting interface. HCI treatments often reduce a large spread in ^^d [29]. 3. A positive correlation of ^^d ^^th Q^^ values. In this case large Q^j values correlate with large ^^d values. This often indicates that the weakness of the capacitors is due to inhomogeneous injection. Single defects with smaller barrier heights in the capacitor area will confine all the current to one spot. The trapping of carriers may cause the same correlation: for the same current a higher voltage is needed if the stress before breakdown takes longer; i.e. if Qj^^ is larger. 4. A negative correlation of ^^d with Q^j values. Small ^bd values correlate with large Q^^j values and vice-versa. This indicates an evolution of the opposite charge during stress. For instance, the injection of electrons becomes easier through the evolution of the positive space charge during the stress. By this effect the voltage decreases for longer stress; i.e. when Q^j is larger. This effect occurs when A£ electrodes are biased positively [5].

259

Dielectric Breakdown in Silica 14 12 \

10

O c

8

J

•o

o o

6 4

poly-Si 175 Ang oxide \ p-substrate

2 0

0

2

4

6

8

10

12

^bd [MV/cm]

14 ^

Fig. 5.75 GM V5 ^i,ci plot for ramped-current test results

14 12 K

E 10 o O 8 c •o

O O)

o

poly-Si 175 Ang oxide _| p-substrate 0

0

6

8

10

12

14

^bd [MV/cm] Fig. 3.16 Qi,j vs ^i,j plot for constant-current test results

260 8. ^BD AND Q B D

D,R, Wolters et aL VALUES

ARE MATERIAL PROPERTIES

The four stress methods: constant-voltage or current and ramped-voltage or current can all be used to describe the quality of oxide layers. The extracted parameters, Q^d and ^ ^ j , are of practical value, since both can be considered to be material properties. Both can be monitored to check when the quality of the dielectric deviates from its normal value. The values of these two parameters can also give a rough estimate of the expected reliability hazard. However, one must be very careful in using them to calculate a realistic lifetime. A high Q^j, for instance, is not necessarily a guarantee of a long life for a MOS capacitor. Although the injection current may be small in the beginning, the degradation of the dielectric during stress may cause the current to increase by several orders of magnitude. Likewise the reverse situation of a current decreasing by several orders of magnitude may occur. Such extrapolations should therefore be handled with great care. Furthermore, the lifetime depends on the application of the dielectric and its specifications. For instance, for an AC coupler a dielectric needs to have a combination of properties which is different from that needed for a damping device. This can best be understood by considering Q^j and ^5^ as pure material properties. They have their analogs in the maximum strain and yield values for mechanical breakdown. (See intermezzo^*^ below).

^*^ Intermezzo Electrical breakdown has its analog in mechanical breakdown [4], The conservative energy storage occurs in the linear or elastic strain region while the dissipative energy storage is found in the plastic deformation region. Young's modulus is comparable to the reciprocal dielectric constant. The maximum mechanical stress at breakdown (yield) is very comparable to the value of <^^^ and the maximum strain at mechanical breakdown is comparable to Qi^^, The well-known stress-strain plot in mechanics has a shape similar to that of an <^^j - QbdP^ot. For a mechanical structure used in "risky'* conditions, it is very useful to know the strength and the maximum deformation required by the application. For instance, glass has an attractively high strength for static compressive forces but fails very easily under dynamic stress. Rubber has a very attractive maximum strain but can hardly be used under static load when a large creep must be avoided. Each application thus requires a specific combination of material properties. Similar considerations might be important in designing electrical circuits.

Dielectric Breakdown in Silica

KJ

C

r\

261

R

R

o

o

Fig. 3.17 a) An AC coupler needs a very low leakage current, so the |^^ value should be high but the G^^ value is not so important, b) A damping device does not need a very low leakage current but therefore does need a very large Qi,j to be sure of a long life.

In electrical insulation a "brittle" (high ^bd' low Qbd) material and a "tough" material (highQbd, low ^bd) will have different applications. By way of an example, the possible applications for differentiating and integrating RC-networks will be discussed. AC-coupler: for a differentiating RC-device (an AC-coupler), as shown in Fig. 3.17a, a very low leakage current is required. A designer would be better off choosing a capacitor with a dielectric having a large barrier height at its interfaces, since this would suppress the leakage current. He could also consider incorporating a large number of deep traps in the dielectric, since permanent trapping reduces current leakage through the capacitor. Such permanent trapping occurs in A£-gated capacitors which have considerably higher ^bd values than poly-Si capacitors due to Af-related electron traps in the dielectric. An A^-gated capacitor is the best choice for an AC-coupler. The small Qbd value is not a serious handicap since the leakage current is small. Damping device: the capacitor in an integrating RC network, (a damping device) as shown in Fig.3.17b, must be as large as possible. A dielectric with a high dielectric constant or a very thin dielectric layer is therefore the best choice. A thin dielectric means a relatively high leakage current at low voltages. This can be tolerated for a damping device as long as there is no breakdown. A poly-Si-gated capacitor is the best choice for a damping device since it has a very large Qbd value. It is usually orders of magnitude larger than an A£-gated capacitor [5]. The polysilicon gated capacitor is also the best choice for an EEPROM-device since transport through the dielectric to the floating gate is part of the operation of the device. The A^-gated capacitor can be compared with a spring made up of a hard brittle material, and the polysilicon-gated capacitor with one made up of a tough material.

262

D,R. Wolters et aL

9. CONCLUSIONS It makes no difference how capacitors are characterized for breakdown. Any test is as good as another, but it is advisable to choose a method which enables the measurement of both the applied field at breakdown, ^^j and the total fluence of charge at breakdown, Q^^ The most convenient method for a fast monitoring is the ramped-current technique since it yields the values of both Q^j and ^^d ^^ ^ simple way. 10. REFERENCES [I]

D. R. Wolters and J. F. Verweij. Instabilities in Silicon Devices, eds. G. Barbottin and A. Vapaille, North Holland, Amsterdam:315 (1986).

[2]

K. Hamano. Jap. J. ofAppL Phys., 13: 1085 (1974).

[3]

D. R. Wolters. Springer series in Electrophysics. eds. M. Schulz and G. Pensl, 7:180 (1981).

[4]

D. R. Wolters and J. J. Van der Schoot. Philips Journ. of Research, 40:115 (1985).

[5]

D. R. Wolters and J. J. Van der Schoot Philips Journ. of Research, 40:137 (1985).

[6]

D. R. Wolters and J. J. Van der Schoot. Philips Journ. of Research, 40: 164 (1985).

[7]

J. F. Verwey, E. A. Amerasekera, and J. Bisschop. Rep. Progr. Phys., 53:297 (1990).

[8]

D. R. Wolters and A. T. A. Zegers van Duijnhoven. Proc. ofSymp. on Silicon nitride and Silicon dioxide of the Electrochem. Soc. eds. V. Kapoor and K T. Hankins, 87-10:277 (1987).

[9]

T. Poorter and D. R. Wolters. Insulating films on Semiconductors, eds. J. F. Verwey and D. Wolters North Holland, 3 :266 (1983).

[10]

D. R. Wolters and A. T. A. Zegers van Duynhoven. The Physics and Technology of Amorphous Si02; ed. R. A. B. Devine. Plenum Press 1988, p. 391(1988).

[II]

Y. Uraoka, N. Tsutsu, T. Morii, Y. Nakata, and H. Esaki. Private Communication (1989).

[12]

M. Shatzkes and M. Av-ron. I.RP.S. (1992).

[13]

R. Moazzami and C. Hu. I.RP.S. (1992).

[14]

M. Shatzkes and M. Av-ron. Proc. IEEE Int. Reliability Symp., 1984:137 (1984)

[15]

E. Cartier and P. R. McFeely. Proc. Int. Conf Infos 1991. ed. W. Eccleston, :43().

[16]

M. V. Fisschetti and D. J. DiMaria. Appl. Surf. Science, 31:377 (1988).

[17]

D. J. DiMaria and M. V. Fisschetti. Appl. Surf. Science, 30:278 (1987).

[18]

D. K. Ferry. Appl. Surf. Science, 31:37 (1988).

[19]

Z. A. Weinberg. Appl. Surf. Science, 31:427 (1988).

[20]

J. W. McPherson and D. A. Baglee. Proc. IEEE Int. Reliability Physics Symp.'.l (1985).

[21]

R. Moazzami, J. Lee, and C. Hu. IEEE Trans ED-37, 37:1643 (1990).

[22]

N. Klein. Appl. Surf. Science, 31 (1988).

[23]

M. V. Fisschetti, R. Gatstaldi, F. Maggioni, and A. Modelli. J Appl. Phys., 53:3129 (1982).

Dielectric Breakdown in Silica

263

[24]

K. R. Farmer, M. O. Andersson, and O. Engstrom. Appl Phys. Lett, 58:2666 (1991).

[25]

J. Lee, I. Chen, and C. Hu. IEEE Trans ED-35, 35:2268 (1988).

[26]

R. Moazzami, J. Lee, L Chen, and C. Hu. lEDM Techn Dig.

[27]

E. Harari. 7. Appl Phys., 49\2A1% (1978).

[28]

P. Olivo, T. N. Nguyen, and B. Ricco. Appl. Surf. Science, 31:449 (1988).

[29]

F. Vollebregt, J. F. Verwey, and D. R. Wolters. Insulating Films on Semiconductors, eds. J. J. Simonne and J. Buxo, North Holland, Amsterdam, :137, (1986).

This Page Intentionally Left Blank

265

INSTABILITIES IN SILICON DEVICES Silicon Passivation and Related Instabilities G. Barbottin and A. Vapaille (Editors) 1999 Elsevier Science B.V.

CHAPTER 4

HOT CARRIER INJECTIONS IN SIO2 AND RELATED INSTABILITIES IN SUBMICROMETER MOSFETS byD. VUILLAUME(i)

Key items Hot carrier effects Substrate and gate currents Lucky electron model Static and dynamic injections Carrier trapping in Si02 Interface state and defect creation models Impact ionization Diffusion of hydrogen-related species Device engineering Ultra-small (< 0.1 |im) MOSFETs Floating gate technique Electrically detected magnetic resonance

(1) Institut dElectronique et de Microelectronique du Nord (lEMN), UMR 9929, CNRS Institut Superieur d'Electronique du Nord (ISEN) Departement de Physique 41 Boulevard Vauban 59046 Lille cedex, France

266

D. Vuillaume

Abstract of Chapter 4: Hot carrier injections in Si02 and related instabilities in submicrometer MOSFETs, This chapter aims at reviewing recent results on hot carrier injections, interface state creation, charge trapping and related phenomena in submicrometer MOSFETs. Starting from a phenomenological description of hot carrier injections in MOSFETs, the modeling of hot carrier injection is then discussed, from simple analytical models to more sophisticated ones. Typical examples of simulated substrate and gate currents are given. The damage to electrical performances of MOSFETs, induced by hot carrier injection, is described as a function of the operating voltage conditions. A comparison of damage induced by dynamic (DC) and static (AC) injections is included in this chapter. Accelerated aging experiments are described in order to determine the lifetime of devices. Recent results regarding the microscopic nature of damage induced by hot carrier injection and the physical mechanisms by which these defects are created are reviewed. Ways of reducing instabilities due to hot carrier injections, using device engineering, are presented. Finally, recent results regarding deep submicrometer devices (< 0.1 fxm) are briefly discussed and future trends are sketched. Resume du chapitre 4 : Injections deporteurs chauds dans Si02 et instabilites connexes dans les MOSFET submicroniques. Ce chapitre a pour objectifde presenter une synthese de resultats re cents sur les phenomenes d'injection de porteurs chauds, de creation d'etats d'interface et de piegeage de charges dans les MOSFET submicroniques. On debute par une presentation phenomenologique des injections de porteurs chauds dans les MOSFET. On presente ensuite la modelisation de ces injections en partant de mode les analytiques simples jusqu'a des mode les plus sophistiques. On donne des exemples typiques de simulation des courants de substrat et de grille. On decrit les degradations des performances electriques des MOSFET, induites par les injections de porteurs chauds, en fonction des tensions de fonctionnement. Une comparaison des degradations induites par des injections dynamiques et statiques est incluse dans ce chapitre. On decrit des experiences de vieillissement accelere dans I 'optique de determiner la duree de vie des composants. On passe en revue des resultats recents concernant la nature microscopique des degradations induites par les injections de porteurs chauds, et les mecanismes physiques par lesquels ces defauts sont generes. On presente comment reduire les instabilites dues aux porteurs chauds par Vingenierie des composants. Enfin, on expose brievement des resultats recents sur les transistors fortement submicroniques (< 0. Ijum), et des pistes futures sont esquissees. Zusammenfassung zu Kapitel 4 : Injektion von heissen Elektronen in das Si02 und damit verbundene Unstabilitdten in sub-mikrometer MOSFETs. Das Ziel dieses Kapitels ist es einen Uberblick fiber neuerer Resultate betrefjlich Injektion von heissen Ladungstragern, Schajfung von Grenzfldchenzustdnden, Einfaug von Ladungstrdgern und damit verbundenen Erscheinungen in sub-mikrometer MOSFETs zu geben. Nach einer phdnomelogischen Beschreibung der Injektionen von heissen Ladungstrdgern in MOSFETs, wird die Modellierung dieser Injektionen beschrieben, von einfachen analytischen bis zu hochkomplizierten Modellen. Typische Beispiele von Simulationen der Substrats- und Gitterstrome werden beschrieben und erldutert. Esfolgt eine Beschreibung der Verdnderungen der elektrischen Eigenschaften der MOSFETs, die durch die Injektion von heissen Ladungstrdgern hervorgerufen werden, in Abhdngigkeit von den angelegten Versorgungsspannungen, als auch ein Vergleich der durch statische und dynamische Injektionen hervorgerufenen Verdnderungen. Anschliessend werden die beschleunigten Alterungsexperimente beschrieben, anhand derer man versucht die Lebensdauer eines Bausteins genau zu bestimmen. Es folgt eine Aufstellung der neueren Erkenntnisse bezUglich der mikroskopischen Natur der durch Injektion von heissen Ladungstrdgern hervorgerufenen Verdnderungen, und eine Beschreibung der physikalischen Vorgdnge die zu diesen Strukturfehlern fuhren. Die Moglichkeiten die durch Injektion von heissen Ladungstrdgern hervorgerufenen Unstabilitdten durch Bausteinoptimisierung zu veringern werden detailliert dargestellt. Schliesslich wird ein Ausblick aufdas Verhalten von MOSFETs mit Kanalldngen im tiefen Submikrometerbereich (Kanalldnge unter 0,1 Mikrometer) gegeben.

Hot Carrier Injections in Silica

267

Chapter 4: Hot carrier injections in SIO2 and related instabilities in submicrometer MOSFETs Table of contents List of symbols and abbreviations used 1. Introduction 2. Phenomenological description of hot carrier injection in n-channel MOSFETs 3. Modeling hot carrier injection (HCI) in n-channel MOSFETs 3.1. The importance of injection modeling 3.2. Expression of the substrate current 3.2.1. An analytical approach 3.2.2. An approach based on 2-D simulations 3.3. Expression of the gate current 3.3.1. Typical behavior of the gate current 3.3.2. Models using the "lucky electron" concept 3.3.3. Models using the "effective electron temperature" concept 3.3.4. Advantages and limitations of 2-D simulations 3.3.5. Discussion and more sophisticated approaches 3.4. Relationship between gate and substrate currents 4. Damage induced in n-channel MOSFETs by hot carrier injection (HCI) at low and medium gate voltages (VQ ^ VD/2) 4.1. The main features of HCI-induced degradation 4.2. Damage due to post-aging injection 4.3. Some models proposed to explain HCI-induced degradation 4.3.1. Models based on the generation of interface states 4.3.2. Model including interface states and donor-like oxide traps 4.3.3. Other models 5. Damage induced in n-channel MOSFETs by hot electron injection (HEI) at high gate voltages (VQ « VQ) 5.1. Evidence of HEI-induced damage 5.2. Effect of HEI on the transistor parameters 5.3. Effect of HEI on the gate current 6. Injections and related damage in p-channel MOSFETs 6.1. Effects of HCI on the substrate and gate currents 6.2. Degradation of p-channel MOSFETs stressed at low gate voltages 6.3. Degradation of p-channel MOSFETs stressed at high gate voltages 6.4. Surface channel versus buried channel devices

268

D, Vuillaume

7. Dynamic (AC) versus static (DC) injections 7.1. A brief survey of the literature 7.2. The physical effects involved during AC injections 7.2.1. Hole transport properties in Si02 7.2.2. Detrapping effects 7.2.3. The effects of alternating injections (hole/electron) 7.2.4. Relevance for circuit operation 8. The microscopic nature of the damage induced by hot carrier injection (HCI) 8.1. Nature of the defects created at the Si-Si02 interface 8.1.1. Basic experimental results on fast interface states 8.1.2. Other interface defects (slow interface states) 8.1.3. The creation mechanisms 8.2. Nature of the defects created in the bulk oxide 9. Technology and device engineering 10. Future trends and conclusion Acknow^ledgements Appendix 1: Basic principle of the floating gate technique Appendix 2: The electrically detected magnetic resonance technique List of references

Hot Carrier Injections in Silica

269

LIST OF SYMBOLS AND ABBREVIATIONS USED a ai

(V.cm)l/2

a2

Vl/3.cm2/3

A

-

Ai Bi C

cm-1 V.cm-1 -

CG

pF nm cm-^.eV^ eV eV V.cm-l

d Dit E Ep F(x) '• m

^ ox fREDF

g Git,e Git,h

Sm Agm h H ID

AID IG

lG,e lG,h IQR

linj.e Iiiij,h

ISUB Jinj(x) k

V.cm-1 V.cm-1 A.V-1 A.V-1 J.s mTorG A A A A A A A A A A.cm-2 J.K-l

Fitting parameter in Eq. (4.15) Coefficient associated with the barrier lowering due to the imagepotential at the Si-Si02 interface Coefficient associated with the barrier lowering due to carrier tunneling at the Si-Si02 interface Parameter of the time-power law encountered during accelerated test Pre-exponential factor of the impact ionization coefficient Exponential factor of the impact ionization coefficient. Proportionality factor between gate and substrate current in Eq. (4.17) Capacitance of the gate node Distance of a free flight of carriers without any collision Interface states density Energy Fermi energy Longitudinal electric field in the channel, at a distance x from the source Maximum longitudinal electric field Perpendicular electric field across the gate oxide High energy distribution function Lande factor or g-factor (strictly speaking, g is a tensor) Generation rate of interface states for electron injection Generation rate of interface states for hole injection Transconductance Shift in transconductance Planck constant (6.626x10-34 j.s) Magnetic field Drain current Shift in drain current Gate current Gate current due to electrons Gate current due to holes Generation-recombination current Injected current at the Si-Si02 interface due to electrons Injected current at the Si-Si02 interface due to holes Substrate Current Density of the injected current at the Si-Si02 interface Boltzmann constant (1.38x10-23 j.K-1)

270

£). Vuillaume

L AL

[xm

Leff

|Lim

M n

cm-2

nc(x,y)

|im

N No P

cm"2 cm"2

Pb,PbO,Pbl

-

p

-

-

^Si

-

P
C

AQG

R AR s

c c

s-1 s-1 -

Drawn channel length Length of the degraded portion of the channel Effective channel length Multiplication factor Exponent of the time-power law Bi-dimensional carrier concentration at location (x,y) in the device Concentration of trapped electrons Pre-existing electron trap concentration Probability Symbols representing the various trivalent silicon dangling bonds at the Si-Si02 interface Probability that a carrier overcomes the scattering phenomena caused by the repulsive oxide field at the Si-Si02 interface Probability of a collision-free travel in the silicon from the channel to the interface Probability that a carrier overcomes the Si-Si02 energy barrier Charge of the electron (1.6x10-19 C) Charge stored on the gate Change in gate charge Recombination rate Change in recombination rate Quantum number for the spin momentum of electrons (s = +?/2 or -Vi)

t At T ^ox u VB VD VDfg ^Dsat VQ AVG Vs VT

AVj W X

s s K nm ^im V V V V V V cm/s V V |im ^m

Time Time interval Effective electron temperature Oxide thickness Distance. Also dumb variable in Eq. (4.14) Substrate voltage Drain voltage Drain voltage used during the measurement of the gate current by means of the floating gate technique Saturation drain voltage Gate voltage Shift in gate voltage Saturation velocity (« 10^ cm/s) Threshold gate voltage Shift in threshold voltage Channel width Longitudinal distance along the channel

Hot Carrier Injections in Silica

xo

|am

Xe

|im

^j

|am

y Yo

|im

a

P

cm-1 J/T

^m

eV eV

Oi

X

|im

eV eV nm

X*

|im

K

nm nm nm nm nm cm2 s s GHz

\

a T

AC BC CB CHE CMOS CP C-V CVD DAHC DC DLC DLTS DRAM EDMR EPROM

111

Parameter in Eq. (4.20) Critical distance for electron trapping in p-MOSFETs (Eq. (4.21)) Drain and source junction depth Distance in a direction perpendicular to the channel Depth of the region of repulsive oxide field at the Si-Si02 interface Impact ionization coefficient Bohr magneton (9.274xl0"21 J/T) Relative permittivity (dielectric constant) of the oxide (EQX = 3.9) Effective energy barrier at the Si-Si02 interface Energy barrier at the Si-Si02 interface without electric field in the oxide Impact ionization energy Impact ionization energy for holes Scattering mean free path Effective length of the velocity saturation region Scattering mean free path for electrons in silicon Scattering mean free path for holes in silicon Scattering mean free path in the oxide Mean free path for scattering by optical phonons Re-direction scattering mean free path Capture cross-section Time needed to reach a pre-defined amount of device degradation Energy relaxation time Microwave frequency Alternating Current Buried Channel Conduction Band Channel Hot Electron Complementary Metal Oxide Semiconductor Charge Pumping Capacitance-Voltage Chemical Vapor Deposition Drain Avalanche Hot carrier Direct Current Double LDD Concave Deep Level Transient Spectroscopy Dynamic Random Access Memory Electrically Detected Magnetic Resonance Erasable Programmable Read Only Memory

272

ESR FG GOLD HCI HEDF HEI HRS

n I-V LDD MOS MOSFET RONO RTF RTS SC SCHE SDR SED SEI SHE Si

Si02 SRAM TOPS TTL VB

D. Vuillaume Electron Spin Resonance Floating Gate Gate Overlapped LDD device Hot Carrier Injection High Energy Distribution Function Hot Electron Injection Hydrogen-Related Species Impact Ionization Current-Voltage Lightly Doped Drain Metal Oxide Semiconductor Metal Oxide Semiconductor Field Effect Transistor ReOxidized Nitrided Oxide Rapid Thermal Process Random Telegraph Signal Surface Channel Substrate Current Hot Electron Spin-Dependent Recombination Single Electron Device Short Electron Injection Substrate Hot Electron Silicon Silicon Dioxide Static Random Access Memory Total Overlap LDD with Polysilicon Spacer Transistor Transistor Logic Valence band

Hot Carrier Injections in Silica

273

1. INTRODUCTION In 4-Mbit dynamic RAMs (DRAMs) in use today (1994), the channel length of the MOS transistors (MOSFETs) has typically been reduced to 0.8 |im. For a number of reasons, the nominal supply voltage has been kept at 5 V, in particular to ensure a full compatibility with TTL circuits and/or to avoid a reduction in delay time propagation. In shorter devices (e.g. in 16-Mbit and 64-Mbit DRAMs), the channel length is further reduced (typically down to 0.5 and 0.3 |im), but the voltage is not reduced accordingly (for the same reasons as above and also to preserve a sufficient noise margin in these circuits). This means that the electric fields are increased and that special care must be taken to reduce the hot carrier effects. Because of the need to design reliable technologies which can minimize these effects, the study of hot carrier-induced degradations has become an important topic. This chapter aims at describing the recent understanding of hot carrier injection phenomena in silicon MOSFETs, and the injection-induced instabilities which can disturb a circuit or even lead to its failure. We have based this review on the results published for micrometer and submicrometer devices and technologies in order to present the most relevant features of modern and emerging silicon processes. The basic principles of Hot Carrier Injection (HCI) into silicon dioxide have been given in Chapter 9 of Volume 1 of this book series [200], and we refer the reader to this chapter for a description of the fundamental mechanisms. Chapter 9 dealt mainly with the physics of impact ionization and of hot carrier injection and described how to use and study homogeneous injections throughout the active area of the devices. However, in real working conditions, the MOS transistors are submitted to localized injections near the drain, which turns injection into a two-dimensional problem. When a short-channel MOSFET operates in the saturation regime, hot carriers are injected near the drain which eventually leads to a degradation of the device characteristics, i.e. to an "aging" of the device. We recall in Section 2 that there exist several modes of hot carrier injection, already described in Chap. 15 of vol. 2 of this book series [201]. However, in the remainder of this chapter we shall restrict our study to the two modes which are most important for submicrometer devices, namely CHE (Channel Hot Electron) injection and DAHC (Drain Avalanche Hot Carrier) injection. The modeling of these two injection modes requires, that first the substrate current, then the gate current be modeled. We show in Section 3 that the substrate current can be modeled either by using an analytical expression of the impact ionization phenomenon, or by using 2D simulation softwares. The modeling of the gate current is more complex because all injected electrons do not necessarily reach the gate electrode. The "lucky electron" concept enables one to establish an analytical expression of the gate current (IG) based on the device characteristics and on the mean free path of the injected carrier. The concept of "effective electron temperature" can also be used to derive an expression for IQ.

274

D. Vuillaume

These two approaches, developed in Section 3, show that both electrons and holes may be injected, even for low values of gate voltage VG, and that the nature of the injected carriers varies with the location in the channel. More sophisticated approaches have been developed based on Monte-Carlo techniques used alone, or associated with 2D simulations. We examine in Section 4 how the characteristics of n-channel MOSFETs get degraded by Hot Carrier Injection (HCI) at low and moderate gate voltages (VG < V D / 2 ) . With these bias conditions, electrons and/or holes may be injected. The ensuing changes in device characteristics (AVj, Agm/gm? AID/ID) are shown to follow a time-power law (©« At^) in which t is the stress duration, A depends on V D and n depends on ratio VGA^DWe also show that a short electron injection, following a prolonged HCI carried out at low VG, generates more degradation than if performed alone. To explain HCI-induced degradations, models have been developed. Some models assume that injected carriers generate interface states only. Others assume that, in addition, the injected carriers may get trapped on donor-like oxide traps. Finally, some models even assume that acceptor-like oxide traps are generated by the injection of hot holes at low YQ, When n-channel MOSFETs are stressed for higher gate voltages (VG r VD), hot electrons are injected. We show in Section 5 that Hot Electron Injection (HEI) produces degradations of the device characteristics which are of the same magnitude as those caused by HCI and which follow similar time-power laws (oc At^). In this case, the degradation is mostly due to the creation (by the injected electrons) of acceptor-like oxide traps and to electron trapping in the oxide bulk, which leads to a decrease in IG during stress. Less interface states are generated by HEI than by HCI. The case of stressed p-channel MOSFETs is examined in Section 6. Substrate and gate currents tend to be smaller than in n-MOSFETs because the mean free path of holes (in Si and Si02) and their efficiency in producing electron-hole pairs through impact ionization are smaller than those of electrons. For stress at low VG, an electron injection is observed close to the drain, followed by electron trapping. The ensuing negative space charge may invert the n-substrate and shorten the effective channel length. Just like for n-channel MOSFETs, such parameter modifications as AVT, Agm/gm ai^d AID/ID ^ ^ shown to follow time-power laws or logarithmic power laws. For stress at higher VG, a hole injection is observed (although with difficulty) as well as an increase in interface states. Surface channel p-MOSFETs (obtained by using p+- doped polysilicon gate electrodes) prove to be less sensitive to stress than buried channel p-MOSFETs (which use n"*"- doped polysilicon gate electrodes), although precautions must be taken to avoid the migration of boron atoms.

Hot Carrier Injections in Silica

275

In real working conditions, MOSFETs are submitted to dynamic stresses (rather than to static stresses). The question than arises as to whether it is possible to extrapolate AC stress results from DC stress results. In Section 7 we compare degradations obtained by static and dynamic stresses. Depending on the applied gate and drain voltage waveforms, degradations observed for AC stresses may be more or less important than those observed for DC stresses. The degradation mechanisms are complex since they may include, depending on the respective VQA^D ratio, electron or hole injection, carrier trapping and detrapping, and the generation of interface and bulk Si02 traps. The technology used to manufacture the gate oxide plays also a part in the observed results (nitrided oxide versus pure oxide). In Section 8 we examine the defects created at the Si-Si02 interface, and in the bulk, by HCI. Recently developed techniques such as Spin Dependent Re-combination (SDR) and Electrically Detected Magnetic Resonance (EDMR) show that HCI generates fast and slow interface states. Two models have been proposed. In the first one, injected carriers release hydrogenated species while passing through the oxide. These species diffuse to the Si-Si02 interface and recombine with those hydrogen atoms which passivate the dangling bonds. Socalled Pb centers are thus created. In the second model, holes, generated by impact ionization, get trapped in the oxide and generate interface states. The first model seems to apply for lower electrical fields and larger fluences of injected carriers while the second model seems to apply for higher fields and smaller fluences. Technology plays also a part. The exact nature of bulk traps is difficult to assess experimentally. It is possible to reduce the consequences of HCI-induced aging in short-channel MOSFETs by improving the resistance of the oxides and by decreasing, by design, the injection probability near the drain. In Section 9, we review some LDD (Low Doped Drain) structures which make possible such a decrease. A further reduction in device dimensions (e.g. an effective channel length L^ff below 0.2 micron) and the lowering of drain voltage (down to 3 volts) could lead to believe that channel carriers can no longer gain enough kinetic energy to be injected. We show in Section 10 that this is not true. Deep submicrometer devices (with L^ff - 0.1 micron) not only experience HCI but also display some new phenomena: non-stationary and quantum transport. Coulomb blockade, Random Telegraph Signal, etc.). These phenomena, briefly described, either can be obstacles to further integration or, on the contrary, may give birth to new devices possessing interesting properties. The Floating Gate (FG) technique is very useful to study HCI-induced degradations. We review the basic principles of this technique in Appendix 1. Finally, in Appendix 2 we describe a variant of the Electron Spin Resonance technique called: the Electrically Detected Magnetic Resonance (EDMR) technique. We show that it is a powerful tool to determine the configuration of defects at the Si-Si02 interface directly in small-size MOSFETs.

276

D, Vuillaume

2. PHENOMENOLOGICAL DESCRIPTION OF HOT CARRIER INJECTION IN N-CHANNEL MOSFETS The hot carrier injection which takes place near the drain of a MOS transistor is one of the major problems which must be solved in order to develop a reliable submicrometer technology. This injection, which arises when the MOSFET operates normally in the saturation mode, induces long-term instabilities, also called device "aging". The HCI generates electrically active charges and defects in the MOSFET, mostly in the gate oxide and at the Si-Si02 interface. This leads to a degradation of the main electrical parameters of the transistors, and eventually to a failure of the devices and circuits which use them. A brief description of the injection of channel hot carriers has been given in § 3.3.1 of [200]. Many injection modes have been described in [201]. Figure 4.1 describes these various phenomena. The simplest mode is the substrate hot electron (SHE) injection (Fig.4.1-a) which takes place when electrons are heated by a large electric field in the space charge region undemeath the gate (see also § 3.3 in [200]). The injection is mostly uniform when drain and source biases are equal. This SHE injection dominates when a large bias is applied between gate and substrate (with substrate bias more negative than gate bias in the case of an n-channel MOSFET). Another type of substrate injection is the substrate current-induced hot electron injection (SCHE), which occurs when the substrate bias is strongly negative (for an n-channel MOSFET) and the gate voltage lower than the drain voltage (Fig. 4.1-b). These two injection modes are no longer a problem in the normal operation of a MOSFET, and they will not be discussed in this chapter (for more details see [200] and [201]). In today's MOSFETs, the main source of degradation is due to channel hot carrier injection phenomena: the so-called channel hot electron (CHE) and the drain avalanche hot carrier (DAHC) injections (Figs. 4.1-c and 4.1-d). When the drain voltage is large enough, electrons in the channel are heated by the longitudinal electric field, and electron-hole pairs can be generated by impact ionization near the drain. Depending on the gate voltage, electrons and/or holes with enough energy can overcome the energy barrier at the interface and be injected into the gate oxide. These two phenomena will be discussed more extensively in this chapter. 3. MODELING HOT CARRIER INJECTION (HCI) IN N-CHANNEL MOSFETS 3J. T H E IMPORTANCE OF INJECTION MODELING

The ultimate goal of hot carrier modeling is three-fold: • gain new insights into the injection phenomena to be able to interpret correctly the results of the accelerated aging experiments used to test the reliability of a given technology, • reduce hot carrier damage by choosing an optimal device structure, • optimize EEPROM cells, since HCI is sometimes used in the operation of such devices.

Hot Carrier Injections in Silica

111

VG>0 (b) SCHE

VG>0 D^

VG

VB<0 (a) SHE

HighVB < 0

VG>0 VD«VG

VB<0 (c)GHE

(d) DAHC

VB<0

Fig. 4.1 Illustration of several operating modes leading to hot carrier injection in an n-channel MOSFET. (a) Substrate hot electron (SHE) injection. Electrons coming from the substrate are accelerated by the high electric field prevailing in the space charge region and are injected in the oxide, (b) Substrate current-induced hot electron (SCHE) injection. Holes produced by impact ionization near the drain are accelerated by the electric field in the depleted region and can produce electron-hole pairs by impact ionization. Electrons^ accelerated by the electric fields are injected in the oxide, (c) Channel hot electron (CHE) injection. Some electrons coming from the inversion layer can gain enough energy to be injected in the oxide, (d) Drain avalanche hot carrier (DAHC). Electrons in the channel, accelerated by the longitudinal electric field, can produce electron-hole pairs by impact ionization near the drain. Both electrons and holes can be injected in the oxide depending on the prevailing oxide field.

278

D, Vuillaume

The theoretical analysis and the modeling of hot carrier injections are not straightforward because of the strong two-dimensional nature of such injections. To model HCI, two currents must be taken into account: the substrate current and the gate current. The substrate current is directly related to the impact ionization phenomenon which takes place in the channel and which produces the hot electrons and the hot holes. The gate current is related to the injection of these carriers into the gate oxide. The following sub-sections introduce the basic theories and give the basic equations currently used by engineers in the field of device modeling. 3.2. EXPRESSION OF THE SUBSTRATE CURRENT

In the channel and when the transistor is operating in the saturation mode, the electrons are accelerated by the longitudinal electric field of the space charge region near the drain (Fig. 4.2). They can gain energies larger than the silicon band-gap and generate electron-hole pairs by impact ionization (see [200]). The electrons are mainly collected at the drain, and the holes in the substrate. Thus, the existence of a substrate current IsuB indicates that impact ionization indeed occurs. Figure 4.3 shows that impact-ionization is maximum when the device operates for V Q values between V^/B and VD/2 [1]. 3.2.1. An analytical approach An empirical approach is often used to derive an analytical relationship linking IsuB and ID [2-4]. The substrate current can be analytically expressed as : IsuB=JDJo'^cc(FM)dx

(4.1)

where Leff is the effective channel length, and a(F(x)) is the impact ionization coefficient which depends on the value of the longitudinal electric field F(x) in the channel at a distance x from the source. For the sake of simplicity, one takes a(F )= Ai exp \ \

F)

(4.2-a)

with Bi^^i/qXp (see the Shockley model, in § 2.4.2 of [200]).

(4.2-b)

Hot Carrier Injections in Silica

279

Gate current Drain current ~ Electron O Hole

Substrate current Fig. 4,2 Schematic illustration of electron-hole pairs production by the impact ionization occuring near the drain when electrons coming from the inversion layer are accelerated by the longitudinal electric field in the space charge region.

§10-4t 10"''° E 10-^^ to O

2

4

6

8

10

12

Gate voltage (V) Fig. 4.3 Substrate (ISUB) ^^d gate (IQ) currents due to HCI are plotted as a function of gate voltage (VQ). The curves show experimental values (—) and results given by l-D simulations (—). The biasing conditions are: Vo = 8 V, VB = '2.5 V. The device characteristics are : n-MOSFET, Leff = L8 jum, W = 100 jum, and tox = 42 nm. (After [14], slightly modified).

280

D, Vuillaume

In Eq. (4.2-b), Oj is the impact ionization energy (i.e. about 1.6 eV for electrons and 2.5 to 2.7 eV for holes, as explained in § 3.3 and § 6.1, respectively) and Ap is the mean free path for scattering by optical phonons (i.e. 6.2 ± 0.5 nm for electrons and 4.5 ± 0.5 nm for holes [5]). These values are commonly accepted today for silicon technology. Using Eqs. (4.1) and (4.2), the multiplication factor M can be expressed by ,^ huB A" z7 '1 * I M =— = V" ^m ^ ^^P\ ^D Br^ V

Bi

(4.3)

^mj

The maximum longitudinal electric field Fm in the channel should be calculated from the voltage drop Vo-Vosat over an effective length X* of the velocity saturation region [6] and length A.* is a function both of oxide thickness tox and of junction depth Xj [6]. We can write: F

=

A*

(4.4)

This model is valid for channel lengths down to 0.5 |LLm. An extension of this model (used for the determination of Fm and A*) has been proposed for LDD (Lightly Doped Drain) devices [7]. 3.2.2. An approach based on 2-D simulations The second approach used to calculate the substrate current is carried out in two steps and uses two-dimensional simulations. In the first step one calculates IsuB- This requires an accurate knowledge of the twodimensional (2-D) distribution: of the electric fields, of the carrier concentrations, and of the current densities. This can be obtained using 2-D device simulators (e.g. MINIMOS [8], IMPACT [91 or PISCES [10]). The simulation softwares used should be appropriate for the device technology being considered. This requires that source/drain and channel doping profiles be accurately known. 2-D process simulators, combined with experimental techniques [11] to verify the doping profiles, are available to provide such data (e.g. SUPREM [12] or IMPACT [9]). The 2-D field and carrier distributions are then obtained by solving the Poisson equation, the continuity equations and the drift-diffusion current equations given by the Boltzmann transport equation [13]. The second step is to choose an impact ionization model. The main models are described in § 2.4 of [200]. The Baraff relationship is the most useful one to get the impact ionization coefficient. Typical 2-D simulation results of IguB ^ ^ ^^^ shown in Fig. 4.3 [14].

Hot Carrier Injections in Silica

281

3.3. EXPRESSION OF THE GATE CURRENT

Compared to the substrate current simulation described above, the simulation of the gate current is a more difficult and tedious task. This is because several physical events (described in the following sub-sections) must occur before carriers coming from the silicon substrate can be injected into the gate insulator, and then reach the gate electrode. Therefore, many approaches have been proposed to obtain both a valuable analysis and a simulation of the gate current. 3.3.1. Typical behavior of the gate current The carriers generated by impact ionization near the drain can be injected into the oxide layer if their kinetic energy exceeds the height of the energy barrier at the interface (see [200]). Depending on the vertical component of the oxide field, electrons or holes may reach the gate electrode giving rise to a gate current IQ. Figure 4.4 shows a typical IQ-VQ characteristic. Such an IQ-VG curve reveals that the gate current is predominantly: an electron current for VG larger than VD/2, and a hole current for lower VG- The peak of the electron gate current is obtained when VG - VD- The reason is two-fold: • for V G larger than Vj), the longitudinal electric field decreases (the MOSFET is in the linear mode), and thus less hot electrons can be generated in the channel and then injected towards the gate. It follows that the electron gate current decreases when VG increases, even if the longitudinal field across the gate oxide favors electron injection (Fig. 4.5-a), • for V G lower than V D , the vertical component of the oxide field repels the injected electrons, and less electrons are able to pass through the gate oxide when VG decreases, even if more electrons are generated in the pinch-off region near the drain (Fig. 4.5-b), • for very low VQ values (close to Vj), the oxide field near the drain is strongly favourable to hole injection (Fig. 4.5-b), and a very small hole gate current is indeed measured (Fig. 4.4). The maximum level of the hole gate current is always smaller than that of the electron gate current. This is obviously because the barrier height that the carriers must overcome at the interface is higher for holes than for electrons. Moreover, hole trapping in the oxide is much more effective than electron trapping, and many injected holes cannot reach the gate without undergoing a trapping event. Because these electron and hole gate currents are often lower than 1 pA (Fig. 4.4) in submicrometer technologies, and thus cannot be measured with standard pico-ampmeters, their accurate measurement requires specific measurement techniques based on the so-called "floating gate" method [15,16] (see Appendix 1). These electron and hole gate currents are the main causes of device degradation and instabilities since carrier injection is followed by carrier trapping and charge build-up in the oxide. Moreover, these currents generate new traps in the oxide and at the Si-Si02 interface. The modeling of localized electron and hole injections in submicrometer MOSFETs plays an important role in the understanding of the hot carrier effects, and in minimizing the resulting degradations and instabilities.

D. Vuillaume

282

10"'2 10''

3 E

Vd =7V

NM05

i4

10"' CE

cn

10"'15

Vd =BV

10"'IG

10"17 10"IB 10"'19

Electrons

Holes

0

I

4

5 G Vg (V)

7

8

9

10

Fig. 4.4 Typical gate current measured by the floating gate technique in a 2/uni/50ijm n-channel MOSFET (oxide thickness: 20 nm). The current measured at low gate voltages is due to holes flowing through the oxide from the substrate to the gate electrode. The current measured at higher gate voltages is due to electrons flowing through the oxide ft-om the substrate to the gate electrode. The hole gate current is measured at V^/g = 8 V and the electron current at V^fg = 7V.

Electron Electron

Gate Gate

Silicon

Silicon

(a)

Oxide

(b)

Fig. 4.5 Energy band diagrams near the drain for two biasing situations in an n-channel MOSFET. (a) VG > VD and (b) VQ < VD-

283

Hot Carrier Injections in Silica 3.3.2. Models using the "lucky electron" concept

The most important insights gained about hot carrier injection come from the 2-D simulation of IQ. This simulation is usually based on the "lucky electron" concept (see § 4.4 in [200]). Basically, the lucky electron concept has been introduced to describe the nonequilibrium transport of carriers. It is based on the assumption that the probability that an electron gain a kinetic energy along a single free flight (d) is given by: P oc exp(-d/>.). In this expression, X is the mean free path which accounts for the main energy loss mechanisms. Applied to the case of localized injections near the drain of a MOSFET, the model describes [17] the probability that a carrier reaches the gate as the product of three probabilities illustrated in Fig. 4.6, namely: POB. Psi ^ d Fox-

•>

X

rain

Fig. 4,6 Schematic description of the three probabilities used in the "lucky electron model" to calculate the gate current.

• FOB is the probability that a carrier, located at a distance x from the source, possesses both enough kinetic energy to overcome the Si-Si02 barrier, and a momentum directed towards the interface. This probability can be written [17]:

=1

\

dE F(x)X)F{x)X E

•exp\ -

(4.5)

which is also expressed as Prfi_

=0.25-——exp\ 0B

OB

Fix)X

(4.6)

where E is the kinetic energy of the carrier, F(x) is the longitudinal electric field at a distance X from the source, O B is the effective energy barrier height and X is the scattering mean free path (see typical X values at the end of this sub-section). Equation (4.5) is a generalization of the simple lucky electron probability, P 0= exp(-d/X.), by taking into account that only electrons with a momentum directed towards the Si-Si02 interface can be injected, and integrated over all energies which exceed the barrier height [17]. The effective barrier height has been found to be correctly described by [17]:

284

D, Vuillaume

^=^0

-^l^'^2Fo/^

(4.7)

where FQX is the oxide field, OBO is 3.2 eV for electrons and 3.8 eV for holes, ai = 2.6 X 10"4 (V.cm)^^^ for Si02, and a2 is determined by comparison with experimental results: a2 = 4 x l 0 " ^ Vl/3cm^''^ [17]. The second term on the right hand side of (4.7) represents the barrier lowering effect due to the image-potential, and the third term accounts for the carrier tunneling which takes place through the (almost triangular) barrier at the top of the potential barrier (see Chap. 5 of Vol. 1 of this series). • Psi is the probability that a carrier travels in the silicon, from the channel to the interface, along distance y, in a direction perpendicular to the interface without undergoing any collision (Fig. 4.6). After Ning et al., we have [18]: (4.8)

• Pox is the probability that a carrier overcomes the scattering caused by the repulsive oxide field FQX at the interface. This field corresponds to the potential gradient caused by the oxide image-potential well for the carriers injected with a field attracting them to the gate (Fig. 4.5-a), or to the overall oxide field when the latter is repulsive for the carriers (Fig. 4.5-b). This probability can be expressed as: Pox=exp(-yo/Kx)

(4.9)

where

The first yo expression corresponds to Fig. 4.5-a while the second expression corresponds to Fig. 4.5-b. Parameter e^^ is the oxide permittivity, and XQ^ is the mean free path in the oxide. All these probabilities can be evaluated at each (x,y) location in the device (see Fig. 4.6). The density of the current injected at the interface, Jinj(x), is then calculated by integrating product POBPSI over the depth y of the device. It yields : JinjM = jnJx^y)P^^ y

Psi f-

(4.11)

^

where nc(x,y) is the 2-D distribution of the carrier concentration calculated by a 2-D device simulator, and ^ is the mean free path for elastic momentum scattering (see the end of this sub-section).

Hot Carrier Injections in Silica

285

The gate current can now be expressed in terms of the probability described above, and by taking into account those carriers which are scattered at the interface in the repulsive oxide field. It yields : (x)Po^dx Moh mjy-^^^ ox

(4.12)

where L is the channel length and W is the channel width. In the case most favourable to electron injection (i.e. around V Q = Vp), this integral can be analytically expressed by [17]: In ^0.5

^D^ox

m

P(F^^(L))exp-(^/Fj,)

(4.13)

J where Fm is the maximum longitudinal electric field at the drain, and probability P(Fox(L)) is calculated for the value of FQX at the drain (i.e. at distance L from the source). In this equation, P(Fox) is product PIPQX where Pi is similar to probability Psi weighted by the density of carriers in the inversion layer. In the case of electron injection, this product depends mainly on the oxide field FoxTypical simulations of IG are shown and compared with experimental results in Fig. 4.3. The mean free path X values used in these equations take into account both the optical phonon scattering mean free path and the impact ionization mean free path (see [200]). A typical X value of 9-9.5 nm is used for electrons and a X value of about 4.5-5 nm is used for holes [4]. The re-distribution mean free path A^ is the mean free path for which momentum relaxation takes place without significant energy exchange (elastic collision). A typical X^ value of 60 nm is commonly used for electrons and holes [17,19]. Finally, in the oxide, XQX is in the 3.2 to 3.4 nm range [14,17,20]. 3 3 J . Models using the "effective electron temperature" concept Another approach used to calculate the gate current, is based on the concept of "effective electron temperature" [14] (see § 4.3. in [200]). The electric field distribution near the drain is now used directly to evaluate an "effective electron temperature" distribution Tg(x,y) [21]. It yields: 2q foo c^ _. ( zq 7;W = —J^ E(x-u)exp

3u ^ ^^eVsy

du

(4.14)

where Vg = 107 cm/s is the saturated electron velocity, and T^ = 8 x 10-14 s is the energy relaxation time [14]. In this equation, u is a dumb variable used to calculate the integral. This "electron temperature" is used to calculate the hot-electron distribution. Probability POB is then given by:

286

Z). Vuillaume

P0s=^[kT,f^^w\-^\

(4.15)

where parameter a, determined from IG measurements, is the only fitting parameter. The rest of the model is strictly analogous to the lucky electron model. The above model is more correct than the "lucky electron" model in the case of high fields and strong field gradients, i.e. in the case of submicrometer MOSFETs. Typical Te distribution are shown in Fig. 4.7. 3.3.4. Advantages and limitations of 2-D simulations The above 2-D simulations emphasize the important difference between the current injected at the Si-Si02 interface and the current collected at the gate electrode. The former is made up of all the carriers injected into the oxide at the interface, even if the electric field is directed against injection (see e.g. Fig. 4.5-b for electrons), while the latter is made up of all the carriers that can flow through the oxide layer and reach the gate electrode. Figure 4.8 clearly demonstrates this important understanding of localized HCI in a MOSFET. We note in this figure that for medium and low gate voltages (i.e. V G ^ VD/2), a large density of electrons is injected through the Si-Si02 interface. These electrons, however, cannot reach the gate, due to the presence of a repulsive electric field in the oxide near the drain (Fig. 4.5-b), and are repelled in the channel. Nevertheless, this electron injection plays a key part in the degradation mechanisms induced in a MOSFET when the latter is aged at a low gate voltage (see Sect. 4). The 2-D simulations enable one also to calculate the longitudinal distribution of the injected carriers along the channel length (Eq. (4.11)). Several examples of simulation results are shown in Fig. 4.9 for conventional (Fig. 4.9-a) and LDD (Ligthly Doped Drain) 1 structures (Fig. 4.9-b) [19,22,23]. It is also clearly shown that electrons are injected at low VQ. In these two approaches (lucky electron or electron temperature models), IG is simply the integral of the injected carrier density along that part of the interface where the electric field in the oxide is favourable for carriers reaching the gate. However, a more rigorous approach should take into account the transport of carrier through Si02, and their possible trapping. This latter phenomenon should reduce the estimated IG- Moreover, the feedback effects between the trapped charges and the electric field in the oxide and the silicon should also be accounted for. In fact, any change in the electric field resulting from charge trapping will lead to changes in the number of injected carriers, and in tum lead to changes in IG- Several attempts to include, in 2-D simulations, the kinetics of trapping and defect creation during injection experiments can be found in the literature [14,22,24], but none of them include such feedback effects.

1 In order to reduce the longitudinal electric field near the drain, a smooth junction transition with a reduced doping concentration (n") between the channel and the drain is obtained in the LDD structures (see Sect. 9).

Hot Carrier Injections in Silica

287

Fig, 4.7 Effective electron temperature distribution in an n-channel MOSFET. Biasing conditions are: Vj^ = 5 V;y(j = 5 y, V^ = - 2.5 V. Device characteristics are: L = 1.3 jum, tox = 42 nm. (After [14], reprinted with permission, © 1985 IEEE).

1010-9 10-^ <:^

'c 10-^^

p k. 3

o

10-^2 10-^^ 10-^4

4

6

8

10

12

Gate voltage (V) Fig. 4.8 Results of a 2-D simulation showing the electron (I^e) ^^d hole (Ich) currents at the gate electrode ( ), and the injected electron (Iinj,e) ^^d hole (Iinj,h) currents at the Si-Si02 interface (—). The characteristics of the n-channel MOSFET are: L = 1.8 pm, W = 100 pm, t^x = 42 nm. Bias conditions are: VJ^ = 8V,VB = -2.5 V. (After [14], slightly modified).

D. Vuillaume

288 CM

E o

5

'(0

•o

O (a)

CM

-5

ioi h

Channel

io'a r 12 10-13 10 14 10 15 10 16 10 17

10-18 U Hole 10 19 10 20 10

-0.4

10 18

fe •

-0.2 0.0 0.2 Position (|Lim)

I

'

I

'

I

'

I

'

0.4

I

•

i

Channel Drain

E

lectron 1

0) 0)

-o 0)

1016 t

Hole

8 1 1

I

i'

I

I

1* I

1^ I

10^5 1 . / . -0.12-0.08-0.04 0.00 0.04 0.08 0.12

(b)

Position (urn)

Fig. 4.9 Results of 2-D simulations showing the localized distributions of electron and hole injections in an n-channel MOSFET. Case (a) corresponds to a conventional device, case (b) to an LDD one. Biasing conditions are : (a) VD=7V,VC = 2 V; (b) Vj) = 10.5 V, Vg = 5.25 V, VB = - 3 V. Device characteristics are: (a) L = 1.3 jLim, W = 50 iim, tox = 25 nm; (b) L = 2 /urn, W = 5 /jm, t^x = 20 nm. (After [19] and [22], slightly modified). The zero of the x-axis corresponds to the metallurgical junction of the drain.

Hot Carrier Injections in Silica

289

3.3.5. Discussion and more sophisticated approaches The lucky electron model is based on Shockley's model [25] (described in [200]). It uses a ballistic approach in which the electrons follow the electric field lines, and it assumes that these electrons have reached high energies during one ballistic flight before experiencing a collision. This approach supposes that scattering is weak. This, however, has been contradicted by Monte-Carlo simulations [26]. Several more sophisticated approaches have been developed in order to describe more accurately all the encountered physical phenomena. These models can be discussed and compared, and one convenient way to do so is to compare the energy dependence of the HighEnergy Distribution Function (HEDF) of the electrons generated in the channel by impact ionization. A correct description of the HEDF is key for a careful modeling of the substrate and gate currents. The conventional device simulators (which are based on the resolution of the conventional semiconductor equations) only give information on the spatial distribution of the electric fields and carriers. On the contrary, Monte-Carlo techniques directly provide the HEDF. However, Monte-Carlo simulations are very time-consuming, and analytical solutions are often more suitable in an engineering environment. The lucky electron model leads to a purely exponential dependence of the HEDF with energy E, which can be written:

r fHEDF(E)^^m

qFX

(4.16)

where F is the longitudinal electric field. Compared to the Monte-Carlo simulations, the high energy tail of the HEDF is not correctly reproduced by the lucky electron model nor by a Maxwellian distribution [27] corresponding to an average electronic temperature greater than the lattice temperature. This latter result has often been observed [28-30], and has been experimentally confirmed [31,32]. In fact, one has been able to probe the HEDF by analyzing the spectrum of the light emitted by an n-MOSFET [31,32] biased at elevated drain voltage. Photons in a large energy range (1 to 3 eV) are produced by hot electrons in the channel, and data obtained with these experiments can be used to study the HEDF, even though the interpretation of the data is not straightforward. These photons are produced by the recombination of electrons and holes in the channel, and by the Bremstrahlung of hot electrons interacting with charged centers. The former mechanism accounts for the low energy part (below 1.5 eV) of the photon distribution, and the latter for the high energy part (above 1.5 eV) [32]. Let us note that these photons can be reabsorbed elsewhere in the circuit where they are able to trigger some parasitic effects (such as for instance, a "refresh" degradation of DRAMs).

D. Vuillaume

290

25 E^ 20 c

1 \

1

(0

a. © 10

g 5

L [

1.0

^••••••••••J ^

1

1.5

1

1

1

2.0

1

2.5

1

J

3.0

Energy (eV) Fig. 4.10 The energy-dependent "mean free path" is plotted versus energy. It is used in the lucky electron model to closely match the more accurate Monte-Carlo study describing the high-energy distribution function of hot electrons in the conduction band near the drain ofn-channel MOSFETs. (After [30], slightly modified).

Nevertheless, the lucky electron model is probably the best known analytical model used for hot carrier phenomena, even if it is not devoid of drawbacks. It was recently shown that it can give a closed form of the high energy tail of the Monte-Carlo HEDF using an energydependent "mean free path" [30]. This "mean free path" is plotted versus energy in Fig. 4.10. It should be noted that the commonly used X value, i.e. X - 7.5 nm, occurs near 1.7 eV, and this value is indeed suitable to model phenomena related to impact ionization (such as substrate current). However, electrons participating in gate currents possess an energy near 3 eV and a X value of about 5 nm seems to be more suitable in that case. No physical meaning is given to this energy-dependent "mean free path", but it reconciles the lucky electron model with more sophisticated approaches in an engineering environment. When channel lengths come close to 0.25 |Lim, which is the case of devices now (1994) under development, these improvements of the analytical models reach their limits, and the use of the Monte-Carlo technique to solve the Boltzmann transport equation has gained much more attention [31-36]. It is not the aim of this section to give an extensive review of MonteCarlo simulations, and the reader can find a state-of-the-art review in refs. [35,36] with several applications to the case of Si MOSFET as well as to GaAs devices. However, an appealing approach (from an engineering point of view) is to couple a conventional 2-D device modeling (drift-diffusion formalism) with a Monte-Carlo simulation in order to obtain more accurate information about hot carrier phenomena [37-40]. One method is to develop the Monte-Carlo simulation as a post-processor of the 2-D device simulator, with or without iteration between the two techniques.

Hot Carrier Injections in Silica

291

In the former case, for instance, the electron-hole pairs generated by impact ionization (and calculated by the Monte-Carlo method) can be coupled back with the generation term in the continuity equation. In the latter case (as for instance in ref. [40]), it is assumed that electric fields and carrier densities, calculated by the conventional 2-D simulator, are not drastically perturbed by the hot carrier effects. Another method, proposed by Bandyopadhyay [38], is based on a drift-diffusion formalism in which several parameters (such as diffusion coefficient and mobility) have been computed by a Monte-Carlo technique [41]. 3A. RELATIONSHIP BETWEEN GATE AND SUBSTRATE CURRENTS

In the framework of the analytical model, a relationship between IG and IsuB can be obtained from Eqs. (4.3) and (4.13), namely :

(4.17) ID

where C is a parameter weakly dependent on the oxide field. Figure 4.11 shows plots of such relationships. Using (4.7) to calculate O B , the impact ionization energy 4>i is deduced from the slope of these curves. Typical i values for electrons are commonly found in the 1.3-1.6 eV range by this method.

10-

T—I

I 11 i

m

I

I I i 11

10-

10 •10

10 •11

10-

—•—Device 1 —A— Device 2 3 J

i

i i i i ill

10-

i

i i i I ii

10-2

'SUB^'D Fig. 4.11 Typical relationship found between gate and substrate currents in n-channel MOSFETs (for two different technologies). Measurements have been performed at several VD values between 5.5 and 7.5 V and at constant Vj) - VQ = 1 y. Device characteristics are: L = 0.8 jum, W= lOOjum, tox = 15nm (for both technologies). (After A. Bravaix and D. Vuillaume, unpublished).

292

D, Vuillaume

4. DAMAGE INDUCED IN N-CHANNEL MOSFETS BY HOT CARRIER INJECTION (HCI) AT LOW AND MEDIUM GATE VOLTAGES (VG < VD/2) From Fig. 15.44 in [201], and from Figs. 4.4 and 4.8 in this chapter, it is clear that different carriers (electrons alone, or holes and electrons) are injected into the oxide depending on the value of ratio VQA^D- These different injection conditions lead to different degradation effects which will be described and discussed separately in the following two sections (4 and 5). 4.1. THE MAIN FEATURES OF HCI-INDUCED DEGRADATION

The damage produced by HCI in n-channel MOSFETs is maximum when the biasing conditions are such that the substrate current is maximum [42-45]. This corresponds to V Q values ranging between low (VQ = VD/4) and medium (VQ = VD/2) voltages, (typically to V G = V D / 3 ) . TO be able to observe this degradation within a reasonable time, the HCI must be performed at V D values relatively larger than the nominal value (accelerated lifetime experiments). In this gate voltage range, both hot electrons and hot holes are injected together into the oxide (see Fig. 4.8, § 3.3.4). This makes the interpretation of the experimental results much more difficult than when only one type of carrier is injected. These biasing conditions correspond to the "so-called" DAHC injection phenomena described in Fig. 15.44 of ref. [201] and briefly recalled in Fig. 4.1-d, in Sect. 2 of this chapter. The basic and conmionly observed features of HCI-induced degradations, are described next. i) The degradation (induced by HCI) leads to several changes in the linear-mode ID - VG characteristics: an increase in V T (a Vx-shift), a decrease in ID and in the maximum transconductance gm (see § 9.4.2 in [201], and more details in refs. [42-45]). Figure 4.12 illustrates a good correlation observed between the degradation of Vx and the value of IsuB [50]. These changes in the transistor parameters are mainly due to charge trapping in the oxide and to the creation of interface states. For instance, a net negative charge trapping in the oxide and/or at the interface leads to a shift of the I D - V G curves towards more positive gate voltages and thus to a shift of V^ towards more positive values. This also induces a coulombic repulsive effect on the electrons in the channel, and leads to a decrease in the drain current and in the transconductance. Opposite effects are observed for a net positive charge trapping. Consequently, one could conclude that the study of the degradation, viewed through the sole degradation of the transistor parameters, is a route to determining the physical mechanisms responsible for the aging of MOSFETs. However, reaching this goal is not so obvious. For instance, it has been demonstrated that identical degradations of the I-V curves may be due either to the creation of interface states located above the channel or to the creation of fixed negative charges located above the drain [45]. Therefore, more sophisticated characterization techniques are required to fully determine the nature and the mechanisms of the degradation. These techniques include: charge pumping (CP), described in Chap. 6 of this volume), gate current measurement by the floating gate (FG) technique (described in Appendix 1), structural determination of HCI-induced defects by spin-dependent recombination (SDR) or electrically detected magnetic resonance (EDMR), described in Appendix 2.

Hot Carrier Injections in Silica

100

9

80

E

60

• M l

293

900

T-»-T

^

- • - V T Shift dSOO

1

700 r

600 S 500 I 400 JJ

40 20 0

'

'

'

'

•

'

'

I

1 2 3 4 5 6 7 8 9

300 ro 200 ^ 100^ 0 ^ 10

Stress gate voltage (V) Fig. 4.12 Typical relationship observed between the amount of degradation (as measured by the shift in threshold voltage) and the substrate current in an n-channel MOSFET. Stress conditions are : Vp = 8V during 120 min. Device characteristics are: L:=1.8inm, W = 100 jum, and tox - 35.8 nm. (After [42], slightly modified).

10^

I

B i l l !

i I I I

10^ t I Technology 1 > Technology 2 A Technology 3

O 10^ ^ H

10^ ELifetlme to reach AVy=1 Om>

10^ 10"

10-

10-1

'sUB^b Fig. 4.14 Typical plot of xlj) versus IsuB^ofar different CMOS technologies (n-MOSFET) with gate lengths below 1 fim and oxide thicknesses below 20 nm. (Parameter x is defined in the text). The slope of such log-log plots is typically of the order of 3. (After A. BravaixandD. Vuillaume, unpublished).

294

D. Vuillaume

ii) After HCI, the current characteristics, measured in the saturation mode, are usually not much degraded. This is because that portion of the Si-Si02 interface which is degraded during HCI is located near the drain. This part of the channel is in depletion, and the current is less affected by the defects and the trapped charges located in this damaged region. If after aging, we invert the roles of source and drain for the measurement of the ID - VQ characteristics, a large effect is revealed in the saturation-mode (decrease in ID). iii) The V T shifts and the relative degradations of gm and ID (i.e. Agm/gm^ AID/ID) usually follow a time-power law Atn (Fig 4.13-a), where t is the stress duration and A is a parameter which depends on VD and on the technology [42]. The values of n are of the order of 0.5-0.7 for aging at medium V Q (i.e. for V Q - VD/2) [42,43,46] and 0.2-0.3 for aging at low V G [43,45] (Fig. 4.13-b). Let us note that for LDD devices (see Sect. 9 for a definition of the LDD structure), this time-power law is only found at the beginning of HCI, and that the degradation saturates afterwards [47,48]. This is probably due to electron trapping and to interface state generation above the n- region, leading to an increase in the parasitic series resistance. iv) The extrapolation techniques used to assess the aging lifetime of a device make use of these time-dependent behaviors [42]. One often introduces a time parameter t which is the time needed to reach a pre-defined amount of degradation (e.g.: 10 or 100 mV of AVx or 10% of Agm/gm)- The values of t are extrapolated from curves such as those of Fig. 4.13-a [42]. These accelerated lifetime measurements can be used to compare the hot carrier sensitivity of different technologies. Figure 4.14 shows a log-log plot of T I D versus ISUB/ID for AVx =10 mV. Expression x ID thus represents a charge, expressed in Coulomb, which flows through the channel and triggers a certain amount of degradation. Let us note that the degradation observed during this static (DC) aging may not be fully meaningful for the real operation of transistors in an integrated circuit. For instance, in a real digital circuit, transistors operate under dynamic (AC) conditions (see a detailed discussion of a comparison between DC and AC degradations in Sect. 7). Nevertheless, lifetime extrapolation techniques are often performed under DC injections and under the worst biasing conditions (typically at the maximum of the substrate current in n-channel MOSFETs and at the maximum of the gate current in p-channel MOSFETs, (see Sect. 6 in this latter case). 4.2. DAMAGE DUE TO POST-AGING INJECTION

It is generally observed that a short electron injection (SEI) (typically 100 sec at VQ = VD, see Fig. 4.15) performed after a prolonged HCI is sufficient to induce a significant new degradation of V^ or gj^^ [42,45,49]. Let us note that the same SEI performed on an unstressed MOSFET would be unable to produce the same shift. Thus, this post-aging effect is clearly related to the damage already induced in the MOSFET by the previously performed prolonged aging.

Hot Carrier Injections in Silica

10

9

295

I I iiiiiH| I 111111^—rrnm^j—nrnnii—rmni

10^ 10^

(0

10^

10"-1

I—I IIIIIMI

10^

(a)

•

stress at VQ=VD/4 3

•

Stress at VQ=Vj3/2-i

A Stress at VQ=VP | I iiiiiiJ t iiiiiiil I 11 mill {.Luuii

10^

10^

10"^ 10^ 10®

stress time (s)

I 0.8 I 0.6 R 0.4 E 0.2 0

—A— AIQP from Ref. 43

0.0

—•— AVy from Ref. 43

o -0.2

• 1.

55

0.0

0.2

J

\

0.4

AVy from Fig. 13-a t

\

0.6

t

\

0.8

t

\

1.0

(b) Fig. 4.13 (a) Time-dependent evolution of the threshold voltage shift as a function of stress time for various (stress) gate voltages during HCI (performed at V^^ 8.5 V). The characteristics of the n-channel MOSFET are: L = 1 jjim, W = 100 jum, and t^x = 20 nm. (b) Typical values for slope n, describing the time dependence of the degradation (time-power law, At^) are plotted on a log-log scale as a function of the gate voltage during HCI, and for damage measured by the threshold voltage shift (M and # j , and by the charge pumping technique (A), ((a): after [49], (M) and (A) in (b): after [43], slightly modified, (^)from Fig. 4.13-a).

D. Vuillaume

296

400

9

T—'—r

T—^—I—r

—•— HCI —•— HCI + SEI

300 h

E 200 ^H- 100

0

2

4

6

8

10

Stress gate voltage (V) Fig, 4.15 The threshold voltage shifts, measured immediately after HCI and after a subsequent brief electron injection (SEI), are compared for various gate (stress) voltages. HCI conditions are: Vjy = S.5 V, during 4x10^ s. SEI conditions are: Vg = V^ = 8.5 V, during 100 s. Device characteristics are: n-MOSFET, L = 1 jum, W = 100 /um, and t^x = 20 nm. (After A. Bravaix and D. Vuillaume, unpublished).

CO

Techno. 1 Techno. 21

(0

O

o

2 h 1 Lh Techno. 3

O 10-'' 10° 10^ 10^ 10^ 10"^ 10^ 10^ stress tinfie (s) Fig. 4.16 Time-dependent degradation of n-MOSFETs for three different CMOS technologies stressed by HCI at (a) VQ = V/y2 and (b) Vg = Vj). The relative positions of the curves along the y-axis have been changed for the sake of clarity. (After [55], slightly modified).

Hot Carrier Injections in Silica

297

The additional degradation due to SEI can be erased by various means. A short hole injection (SHI) (e.g. at VQ = Viy4) returns the Ij^ - VQ curve to its post-aging value. Likewise, we have shown [50] that if the MOSFET is turned off (VQ = 0), and if a monochromatic light, with a wavelength corresponding to a photon energy greater than about 3 eV, is focused on the damaged region near the drain side, or if a sufficiently high drain voltage is applied (in the dark), the post-aging situation is restored. Figure 4.15 shows that this SEI effect is only observed if HCI has been performed at low V Q [45]. The amplitude of this additional degradation increases with the value of Vj) used during the HCI and with injection time. It is thus clearly linked to the amount of degradation induced by the HCI. This SEI effect exists for low V Q aging because with these aging conditions both hot holes and hot electrons are injected together in the oxide (see § 3.3.3), and because these hot carriers either create or get trapped by different types of defects in the MOSFET. These defects can be: • interface states, • donor-like oxide traps (positively charged after capturing a hole), also called hole traps, • acceptor-like oxide traps (negatively charged after capturing an electron), also called electron traps. The short injections performed after a prolonged aging can change the charge state of the above-mentioned oxide traps and thus lead to drastic changes in the MOSFET characteristics. The reversibility of these changes in charge state is obtained by injecting carriers of opposite polarity, by detrapping the carriers by means of an illumination (photodepopulation) or by applying a large electric field (field-enhanced emission). The models used to explain (HCI induced) degradation in MOSFETs, at low VQ are detailed next. 4.3. SOME MODELS PROPOSED TO EXPLAIN HCI-INDUCED DEGRADATION

4.3.1. Models based on the generation of interface states For HCI performed at maximum IsuB' the slope n « 0.5-0.7 shown'by the time-dependent degradation behavior (see Fig. 4.13b) has been ascribed to the creation of fast interface states by electrons having energies of 3.7 eV and above [42]. This threshold energy and the observed time dependence could be explained by a physical model involving the breaking of Si-H bonds by hot carriers [42]. Another approach [14,44] suggests a process whereby holes and electrons are both involved, via a so-called "two-step process" [51]. In this model, the holes are trapped very close to the interface (typically within less than 3 nm), and the subsequent electron trapping on trapped holes triggers the generation of interface states (see Sect. 8.). However, this "twostep" model was neither clearly confirmed nor clearly invalidated from hot carrier experiments in MOSFETs.

298

D. Vuillaume

The generation of interface states has been clearly revealed by charge pumping measurements [43] (more detail on charge pumping techniques can be found in Chap. 6 of this volume, and in ref. [52]). The creation of interface states has been shown to follow a timepower law with an exponent n « 0 . 5 [43], similar to that observed for the time-dependent behavior of the MOSFET parameters (§ 4.1). Charge pumping measurements, performed on gate-controlled diodes, have yielded the generation "rates" of interface states (i.e. the number of interface states generated per number of injected carriers) due to the injection of hot electrons and hot holes: G-^^^^ « 10-7-10-6 and Git,h "^ 10-3-10-2, respectively [43]. This shows that hole injections are important features to understand hot carrier degradation, and that they are very efficient in generating interface states. 4.3.2. Model including interface states and donor-like oxide traps At low VQ, hot holes are injected into the oxide, leading to hole trapping on the preexisting donor-like oxide traps. The resulting positive charge reduces the effective V-^ shift induced by the interface states. On the other hand, the formation of interface states is masked by the trapped positive charges. According to this model [43], the positive V^ shift observed after a subsequent SEI (Fig. 4.15) is only due to the interface states because the positive charge has been neutralized by the injected electrons. However, this model is not sufficient to explain the large positive V j shifts often observed after SEI following an HCI performed during a long period (more than 10^ sec) or performed at the highest VQ value [45,49]. The hole trapping probabilities have been estimated from charge pumping measurements on gate-controlled diodes [43]. A crude estimate gives a probability value of 0.1-0.5 for hole trapping, which shows the great efficiency of hole trapping on pre-existing deep hole traps (these traps are probably related to the non-bridging oxygen defect, as explained in Chaps. 2 and 10 of Vols. 1 and 2 and in Chap. 11 of this volume). 4.3.3. Other models In a recent work, it was shown, using two-dimensional (2-D) simulations, that a large density of interface states, of about 10^^ cm-^eV-l, induces, at best, a V^-shift of the order of a few tens of mV [49]. It has therefore been suggested that the largest positive V'p-shifts measured after the SEI could be mainly due to the trapping of electrons on the acceptor-like oxide traps generated during the previous hot hole injection at low VQ [45,53]. These traps are neutral after the HCI and negatively charged after the SEI. The creation of such oxide traps by HCI at low VQ has been revealed by a careful analysis of charge pumping measurements [54]. Two-D simulations (using code IMPACT [9]) including the measured concentrations of these traps, further validate this model [49]. For some technologies, it has been observed that the generation rate of these traps under hot hole injection is as high as 10"^-10"^, i.e. of the same order of magnitude as for interface states (see above) [49]. Moreover, it has been also shown that these acceptor-like oxide traps are essential in explaining the difference between AC and DC stress experiments (described in Sect. 6), and that they must be taken into consideration in the lifetime extrapolation techniques [45].

Hot Carrier Injections in Silica

299

To conclude, the model which includes interface states and donor-like oxide traps may be viewed as the most general model to understand degradation mechanisms in n-channel transistors. But, for some technologies (as for instance for some LDD devices and/or for technologies which are not well-controlled), additional effects such as those due to the creation of acceptor-like oxide traps are of great interest. 5. DAMAGE INDUCED IN N-CHANNEL MOSFETS BY HOT INJECTION (HEI) AT HIGH GATE VOLTAGES (VG « Vj))

ELECTRON

As shown in Fig. 4.12, degradation by hot carrier-injection is maximum when V Q is chosen between VjyS and VD/2 [42-45]. However, some work has also recently reported a large degradation induced by hot electron injection (HEI) which is maximum when the device is working at V Q = Vj) [49,55-58]. This biasing condition corresponds to the so-called CHE effect described in [201], and illustrated in Fig. 4.1-c of Sect. 2. 5-1. EVIDENCE OF HEI-INDUCED DAMAGE

Evidence of HEI-induced damage is clearly visible in Fig. 4.16 [55]. The VT shift observed after HEI is of the same order of magnitude (or even larger for some technologies) than after an aging performed at a medium VG range. This degradation comes from electron trapping on oxide defects which either pre-existed or which are created by the HEI itself. These defects have been observed less frequently than those induced by aging at medium and low V Q range. This is because they are often located deeper above the drain of the MOSFET and therefore are less easily detectable through the measurements of the V j , gjj^ or ID degradations. More sophisticated techniques based e.g. on the measurement of changes in IQ using the Floating Gate (FG) technique are very helpful in this case [49,61] (see Appendix 1 and Sect. 5.3). It has also been shown that these negative charges located above the drain can lead to a negative differential charge pumping (CP) characteristic, i.e. that the difference between the CP curves measured after and before stress is negative [54]. 5.2. EFFECT OF HEI ON THE TRANSISTOR PARAMETERS

The HEI-induced degradation is also characterized by a typical time-power law A=At^ where A can be either the V T shift, or the relative drift of g^ or that of ID- Parameter A depends both on the technology and on VD (see Eq. (15.110) in [201]). In the case of HEI, n is typically equal to 0.2-0.3 (Figs. 4.13-b and 4.16), while it is conmionly equal to about 0.5-0.7 for aging at a medium V Q range (i.e. for VD/3 < VG < VD/2) (Sect. 4). This difference in n values has been attributed to a difference in the nature of the defects generated at the Si-Si02 interface or in the gate oxide. The damage induced by HCI for medium V Q is mainly attributed to the creation of interface states [42-44] (Sect. 4), while the damage induced by HEI is thought to be mainly caused by the negatively charged defects in the oxide [55-58].

D, Vuillaume

300

On the other hand, the oxide traps induced by HEI have also been characterized by the CP technique [49,54] (but generally less easily so than the interface states, due to their being located deeper above the drain side). Nevertheless, the appearance of this negative oxide charge has been clearly correlated, using 2-D simulations, with the large VT shift observed in some technologies [49]. The generation "rate" of these acceptor-like oxide traps by hot-electron injection at VG = VD was found to be of the order of 10-9-10-8 [49]. This means that a prolonged aging is needed to observe a significant creation (typically about lO^^-lO^ s). 5.3. EFFECT OF HEI ON THE GATE CURRENT

The gate current observed during an electron injection into the oxide can be directly measured in a wide-channel MOSFET operating with VD values larger than the nominal value (VD > 5 V) (see Fig. 15.36 in [201]). The observed decrease in IQ with stress time is typical of electron trapping occuring on pre-existing traps or on oxide traps newly created by the HEI itself. For submicrometer MOSFETs, it is also possible to measure the entire I Q - V G characteristic using a very sensitive "floating gate" technique [15,16]. In fact, in submicrometer MOSFETs, IG is always below 1 pA (see Appendix 1). (b)

o

u u

i 6

a)

7

10

8

Gate voltage (V)

b)

20

30

40

50

Stress time (xlO^ s)

Fig. 4.17 (a) Behavior of the I^ - Vg curve, measured at Vo = 6 V by the floating mte technique for different HEI stress times (0, 100, 215, 464, lo\ 2154, 4640, lO"^, 2.154x10^ and 4x10 s). HEI is performed at Vp = VG = 8.5 V. Device characteristics are: n-MOSFET, L = 1 /jm, W = 100 jum, tox = 20 nm. (b) Corresponding evolution of the substrate to drain current ratio. (After [6, 59]).

Hot Carrier Injections in Silica

301

It was recently shown that the advantage of measuring the entire IG - VG curve is that the evolution of its form with aging time (aging due to HEI) can be related to the kind of damage induced by the injections [59,60]. Figure. 4.17 shows a typical behavior of the I Q - V G characteristics after various durations of HEI. The main deformation is a decrease of the whole IG - V G curve with a maximum gate current always peaking at the same VG value [61]. This kind of behavior has been ascribed to an increase in the amount of negative charges in the oxide, acting as a repulsive barrier against a further injection of electrons^. Simple 1-D simulations show that 1012 negative charges/cm2 located within 5 nm from the interface can indeed induce a 3-decade decrease in IG [49]. According to 2-D simulations of the injected current (see § 3.3.3.), the measurement of IG is, in fact, a way of probing locally the damaged region of the MOSFET. Figure 4.9 shows that HEI takes place mostly above the drain in the drain-gate overlap region (especially for LDD devices). In this case, electron trapping is limited to that area and only induces a slight VT shift, since Vx measurements are mainly sensitive to charges located above the channel. On the contrary, since electrons which contribute to the gate current are mainly injected in the drain-gate overlap region, the largest decrease in IG is observed for HEI at WQ = V D [49].

10-8 <

I

Vn=-8V. -7.5V, -7V. -6.5V I

10-^ t

-1

-2

-3

-4

-5

-6

Gate voltage (V) Fig. 4,18 Behavior of the IQ - VQ curve measured in a p-channel MOSFET for various VD values. Device characteristics are: L = 1.3 /jm, W = 100 fim, t^x = 26 nm. (After [78], slightly modified).

2 When only interface states are created, it was shown that the deformation of the IQ-VQ curve is limited to a decrease in IQ in the saturation part of the curve (VQ>V|3), while the linear part is unaffected. This corresponds to a shift of the peak current VQ value, and it is explained by the variation of the charge stored on the interface states as a function of the Fermi level movement during the FG measurement [59,60].

302

D. Vuillaume

6. INJECTIONS AND RELATED DAMAGE IN P-CHANNEL MOSFETS In the past, attention was paid mostly to the degradation of n-channel MOSFETs. Although several results had been reported on the effect of hot carriers in p-channel MOSFETs [62,63], the phenomenon was considered as being less acute than in n-channel MOSFETs. This difference is simply due to the smaller mean free path of holes, and consequently to the higher energy (see Sect. 3) required to induce impact ionization in p-channel devices. This is revealed by the largest peak in substrate current observed in n-channel MOSFETs. As a consequence, LDD n-channel MOSFETs are usually used together with conventional p-channel devices in the 1-1.5 |im CMOS technologies. However, it was clearly reported that p-channel MOSFETs can exhibit degradations which are up to two orders of magnitude larger than those of the corresponding n-channel MOSFETs [64]. Moreover, for submicrometer or deep-submicrometer CMOS technologies, the hot carrier reliability of p-channel MOSFETs becomes increasingly questionable, and has drawn considerable attention these last few years [43,44,65-76]. 6.1. EFFECTS OF HCI ON THE SUBSTRATE AND GATE CURRENTS

In p-channel MOSFETs operating in the saturation mode, substrate current IsuB is made up of the electrons generated by impact ionization near the drain. As in n-channel MOSFETs, IsUB is maximum when VQ«V]y3. Moreover, it is clearly shown that, for the same geometry, the same technology and the same drain and gate voltages, IsuB is smaller in the case of p-channel devices. This is because the generation of electron-hole pairs by hot hole impact ionization is less effective. The mean free path of holes is much smaller than that of electrons (see [200], and § 3.2.), and therefore the energy gained during a ballistic flight is also much lower. The gate current in a p-channel MOSFET behaves in a fashion opposed to that of an nchannel MOSFET. The electron gate current is maximum at low VQ, around VQ = Vjy4 (Fig. 4.18), for which the vertical oxide field favors electron injection. In principle, the injection of holes should be maximized at higher V Q values (for V Q > Vj)). However, a gate current has never been measured for this range of gate bias in devices with channel lengths down to 0.5 |Lim, even when using the very sensitive floating gate technique. Recently, in far shorter devices, and for high Vj) values, a hole gate current of about 10 pA has been detected [67]. This could be linked to the specific degradation behavior observed in ultra-short p-channel devices stressed at high gate voltages (see Sect. 6.2.2. below). As in the case of n-channel MOSFETs (see (4.17)), a relationship exists between IguB ^^^ IQ, but it is slightly modified to take into account the difference in electron and hole mean free paths. It yields:

Hot Carrier Injections in Silica

303

+1

(4.18) K 'D where Ojj^ is now the impact ionization energy for holes, which has been determined to be between 2.5 and 2.7 eV (Fig. 4.8) [77,78] using a ratio V ^ e = 0.724. Zone of trapped electrons Drain implantation (p-type) Channel shortening

Fig. 4.19 Schematic representation of the channel shortening effect due to the trapping of electrons in the oxide near the drain. A sufficiently large negative charge trapped in the oxide may invert the silicon underneath this region regardless of the gate voltage. CD

100

I ' I • i

I ' I ' I ' I ' I «

1.0

C/3

80 h

9 •••••

60 h

—•— Al

40 h

CO

20 0

I I t I I I t ( I I I I I I I

-9 -8 -7 -6 -5 -4 -3 -2 -1 Stress gate voltage (V)

o z

Fig. 4.20 Illustration of the correlation observed between the amount of degradation induced by HCI in a pchannel MOSFET and the stress gate voltage (—). The degradation has been recorded through (M) threshold voltage shift, (^) interface state increase, this latter quantity being measured by charge pumping. Device characteristics are: L = 0.85 pm, W = 100 pm, tox = 20 nm. The samples are stressed at VD = -9 V during 1000 s. (After [78], slightly modified).

304

Z). Vuillaume

0.15

BC p-M05FET's

Vd=-BV

O.l

-G . 5V

o e

0.05 -5.5V

D O

0

i RiRiSmiA aioiiPiPiff ° i ° i iiiiiil

100

10

10^

I iiiriiil

s3

10^

S t r e s s Time

10 4

I I I mill

105

in

10^

(s)

Fig. 4.21 Typical time-dependent behavior for the degradation induced by HCI in a p-channel MOSFET and measured through the shift in transconductance HCI stresses have been performed at VQ = Vr/5for various Vj) values between -7.5 and -5.5 V. Device characteristics are: L = 0.85 /um, W = 20 /jm and tox = 20 nm. (After A. BravaixandD. Vuillaume, unpublished). 6.2. DEGRADATION OF P-CHANNEL MOSFETS STRESSED AT LOW GATE VOLTAGES

For p-channel MOSFETs stressed at low gate voltages and with \VQ\ < |V£)|(around the peak gate current visible on Fig. 4.18), a large amount of electrons is injected in the oxide which mostly results in electron trapping in the oxide [43,63,65,72]. This results in the creation of a net negative charge which induces an increase in drain current and an increase in transconductance, as illustrated in Fig. 4.21. The extrapolated V^ value is only slightly modified. This is explained by the channel shortening effect due to the presence of negative charges in the oxide which increase the hole concentration near the drain. In this region, accumulated holes are no longer dependent on applied gate voltages, and this region may be viewed as an extension of the drain as illustrated in Fig. 4.19. However, interface states are also formed, as revealed by CP measurements, but they are masked by the large amount of trapped electrons.

Hot Carrier Injections in Silica

305

Consequently, the time-dependent laws for AV-^, AIQ/IJ) or Is^g^lg^ never match the law of interface state creation [43]. For all gate voltage stresses, IQ decreases due to electron trapping and the multiplication factor, M = ISUB/IJ)^ decreases due to the reduction in longitudinal electric field. Figure 4.20 shows that all the degradations are correlated with the peak gate current instead of being correlated with the substrate current as is the case of n-channel MOSFETs [64,68,72,78]. This feature has led to define several new techniques to extrapolate the device aging lifetime based on a correlation with the gate current [68,70,72], or with the injected charge [68-70]. It is often observed that a large amount of degradation is reached immediately after the first seconds of electron injection as visible in Fig. 4.21. Then, the degradation proceeds slowly in time and even saturates for long stress time (this saturation is not visible in Fig. 4.21). This behavior has been fitted (at least for the beginning of the stress) by a time-power law (At^) with an exponent n « 0.1-0.2 [43,63]. However, several recent results have shown that a logarithmic time-dependent law enables a better fit of the observed degradation (Fig. 4.21) for a large number of parameters (AVj, AID/ID, etc.) and for several stress conditions [74-76]. A simple model has been suggested to explain this logarithmic time-dependent law. It is based on the fact that the degraded portion AL of the channel extends logarithmically in time towards the source [74]. This results from the filling of pre-existing electron traps following a first-order-rate equation such as: dN

Jini(^^t)

dt

(4.19)

T{NO - N)

where NQ, N , a, and Jjnj are respectively the pre-existing concentration of electron traps, the concentration of trapped electrons, the capture cross-section and the injection current density. The solution of this equation yields N(x, t), the density of trapped electrons at distance x from the drain and at time t: Jinj(^ = 0) N(xj)=No

1 - exp\

(

X

\

a exp\ K

(4.20)

^0 J

Figure 4.22 shows a typical time evolution of N(x,t). In expression (4.20), XQ is a parameter associated with Oi, X^e, A^h and VD - Vosat [74]. The logarithmic time dependence for the growth of the edge of the filled traps is obvious from (4.19) by calculating location x^ at which a fraction 1/e of the traps remain empty: (Jinj(x = 0) X^(t)= XQM

—

\ Ct

«

J

which is valid as long as t remains larger than (JjnjCx = 0)a/q)-^.

(4.21)

D. Vuillaume

306

-0.20 -0.16 -0.12 -0.08 -0.04 0.00 Distance from the drain (^m) Fig. 4.22 Evolution of the occupancy function (for electron trapping in the oxide) as a function of the HCI duration in a p-channel MOSFET (W to lu s, step 1 decade, from right to left). (After [74], slightly modified).

0.15

3

P-MOS W/L-20/lyum Vg/Vd-8.H A Vd^-B V o Vd—7.5V V Vd—7V

P-MOS W/L»l0B/lnm

.5

Vd=-8V

Vg(V)-

E

3

_

2

0.1

t-4xl0

E

X

.5

\

E

C3.

u

LIP

-a

I [

X

0.05

Q)

.5

0.

0 tuitftfi iri>Aitii^iiiiii''i irriirf i nmd, i mitJ si 10" 10' 10' 10" 10' 10' 10"

a)

STRESS TIME ( s )

v^

0 0,5

b)

1 1.5

2 2.5

3 3.5

4

dVcpmax (V)

Fig. 4.23 (a) Time-dependent evolution of the total electron trapping in a p-channel MOSFET, measured through the voltage shift of the charge pumping characteristics, as a function of gate voltage during HCI (b) Correlation between electron trapping and the extension of the degraded portion of the channel, as measured through the change in transconductance. (After [75]).

Hot Carrier Injections in Silica

'iOl

Since the increases in drain current and/or in gj^^ are directly linked to the damaged portion of the channel, this last equation describes the logarithmic time-dependence of the degradation. Further evidence of this model has been obtained from charge pumping measurements [75]. It is shown that the shift of the CP curves, which measures the density of trapped electron, increases logarithmically with time, and that this trapped charge is linearly correlated with the growth of the damaged region (Fig. 4.23) [75]. Typical values of NQ and a are -lO^^cm-^ and ~ IQ-^^cm^, respectively [74-76]. 6.3. DEGRADATION OF P-CHANNEL MOSFETS STRESSED AT HIGH GATE VOLTAGES

For p-channel MOSFETs stressed at V Q - V^, hole injection should, in principle, be favoured, even though no hole gate current has ever been measured for transistors down to 0.5 |Lim. For these stress conditions, only a weak creation of interface states has been observed by CP measurements [78]. This leaves the static parameters of the device unaltered after the stress. It is only very recently that both a significant creation of interface states and a build-up of trapped holes due to hot hole injections, have been revealed in deep-submicrometer devices (of channel length: 0.25 - 0.4 |xm) with very thin gate oxides [67,73]. This causes a decrease in gjjj. This degradation mode could become important for future advanced p-channel devices in CMOS technologies. 6.4. SURFACE CHANNEL VERSUS BURIED CHANNEL DEVICES Usually, p-channel MOSFETs use n+ polysilicon gates and the threshold voltage is adjusted to the desired value by means of a boron implantation. This implantation creates a p-n junction in the surface region and turns the device into a buried-channel (BC) transistor thus called because the current flows at a certain distance from the interface as illustrated in Fig. 4.24 (left). To circumvent the need for a threshold implantation, surface-channel (SC) MOSFETs using a p+ polysilicon gate have been introduced [79]. In this case, the difference in work functions between the p+ gate and the n-type substrate imposes the correct order of magnitude for the threshold voltage. In this SC device, the current is flowing near the interface as illustrated in Fig. 4.24 (right). In general, surface-channel devices are more resistant to hot carrier-induced degradation than buried-channel devices [71,72]. Three reasons can explain this behavior. • The gate current (made up of electrons injected at low VQ) is larger in BC devices than in SC devices, while IsuB' ^^^ therefore, impact ionization is larger in SC p-MOSFETs [71,72]. This smaller IQ value in SC devices is due to the lower vertical electric field which exists across the gate oxide near the drain, which results from the difference in work functions of the gate materials as illustrated in Fig 4.24 (right). Consequently less electrons are trapped in the oxide of SC devices. • Moreover, the I-V characteristics of the SC p-MOSFETs are less sensitive to the negative charges contained in the oxide. In fact, 2-D simulations have shown that the potential distributions in SC devices are quite insensitive to the presence of these charges, while significant changes have been observed in BC p-MOSFETs [71].

308

D. Vuillaume P^ poly gate

IvT poly gate

II

''^^^0^0^y^v^^^vi!^0iwy:

£^^ 1

J

qFoxto

qFoxtox

1

I 4.3 eV

J—

3.2 eV

EF

VG-VD EF

—

>rpoly gate

P^poly gate

P silicon

P silicon

Fig. 4.24 Schematic cross-sections of a buried channel (left) and of a surface channel p-MOSFET (right) showing the current flow as determined by a 2D simulation on a 0.6 fim transistor biased at Vc = - IV and VD = - 6V. The corresponding energy band diagrams at the drain junction are also shown (After [71] slightly modified).

T — » — I — « — r


With nitride passivation

£1

S'

^

a> O) (0

o E CD

J

I

Without passivation I I I I

Fig. 4.25 Examples of behavior under DC (—) and AC (- - -) stresses encountered in n-channel MOSFETs for two different passivation techniques (After [80], slightly modified).

L

8 Stress gate voltage (V) • Finally, a peculiar mode of degradation has been observed in the case of SC p-MOSFETs [71]. It was shown that a hole injection (at low VQ) occurs simultaneously with the electron injection. This hole injection induces a build-up of trapped holes which compensates the effect of the trapped electrons, and hence reduces the degradation of the I-V curve.

Hot Carrier Injections in Silica

309

In conclusion, SC p-channel MOSFETs are probably better candidates for future deepsubmicrometer CMOS technologies. However, p+ gates require the use of boron doping, but boron atoms can easily diffuse across the thin gate oxide especially for gates less than - 10 nm thick, such as those used in advanced CMOS devices. This problem has stimulated a very intense research to develop other suitable insulating thin films such as nitrided oxyde, reoxidized nitrided oxide, and so forth (see Sect. 9 and also Chap. 1 of this volume). These gate insulators act as better barriers against boron diffusion. 7. DYNAMIC (AC) VERSUS STATIC (DC) INJECTIONS In real digital circuits, the MOSFETs operate dynamically. Therefore, the effects caused by dynamic hot carrier injection have generated a greater interest these last few years. The main question is whether the AC degradation can or cannot be predicted from DC experiments. If the answer were yes (quasi-static case) the reliability of a given technology could be correctly analyzed by a set of DC experiments. Giving an answer is not straightforward because in an AC operation, the gate bias continuously switches the transistor (let us consider first the case of n-channel transistors) between configurations in which hot-hole injection (at low gate voltage) or hot-electron injection (at high gate voltage) or both hot-electron and hot-hole injections (at medium gate voltage) are the prevailing mechanisms. We must therefore analyze a large number of DC stress configurations to be able to correctly predict the AC degradation. Moreover, we cannot ignore several specific questions such as: what happens when holes have been injected and get trapped in the oxide, and when electrons are then injected and can recombine with the trapped holes? From ealier studies of MOS capacitors, we know that this can lead to the creation of additional interface states, or that it can leave the Si-Si02 interface unchanged depending on the location of the trapped holes (see Sect. 8). 7.1. A BRIEF SURVEY OF THE LITERATURE

In the literature, several results have been reported which have led to several controversies (see a review in [801). Typically, it has often been observed that AC injection induces a more pronounced degradation than DC injection [81-881. However, some of these highly enhanced degradations have been attributed to measurement difficulties [80,89]. Indeed, several precautions must be taken for the measurement set-up in order to avoid an abnormally enhanced degradation resulting from increased voltages, due themselves to capacitive and inductive overshoots [89]. These precautions are mainly to use extemal capacitors and extra grounding as close as possible to the device under test. On the other hand, some research groups have found that AC injection does not in fact induce a more pronounced degradation (e.g. for cases where the drain voltage is pulsed while the gate voltage remains constant, or when a high drain voltage is only present during the rising front of the gate signal) [81,83,90]. Some authors have even found that AC injections causes less degradation than DC injections [91]. However, in some cases, the time-dependent behavior was found to display a steeper slope under AC stress than during DC injection [92].

310

D. Vuillaume

1 0 fa I iiiiii^ I iiiiii|—rrmni—i iiiiii^ i

IIIIIB

10-^ <

10-2 t

10-3

J-LUilMl—UUilllil

10°

10^

•*

10^

' "•••••!

10^

> « . . UHl

10"*

10^

stress time (s) Fig. 4.26 The degradations produced by DC stress (—) and AC stress (- -) under inverter condition (see Fig. 4.27) are compared. Device characteristics are: n-channel MOSFET, L = 0.9 fim, tox = 20 nm. (After [80], slightly modified).

(a) Inverter

B

T

VG

(b)SRAM

VD

_ /

I

A B

Fig. 4.27 Illustration of the drain and gate voltage waveforms used during an AC stress to replicate the biasing conditions encountered by n-channel MOSFETs in inverter and SRAM circuits. Areas A and B refer to the text.

Hot Carrier Injections in Silica

311

Figure 4.25 illustrates a case where the degradation (measured through Agj^^) is more pronounced for an AC stress than for a DC stress, when applied to a nitride-passivated MOSFET [80]. On the other hand, other technologies do not display this enhanced degradation, for instance, for unpassivated MOSFETs as illustrated also in Figure 4.25 [80]. The role played by the technology is obvious, and part of the above controversies can probably be ascribed to differences in process. For instance, the amount of hydrogen species and/or the amount of mechanical stress at the interface, resulting from the passivation step, must be taken into account. Figure 4.26, illustrates that an n-channel MOSFET, dynamically stressed under invertertype conditions (as illustrated in Fig. 4.27-b), exhibits a time-dependent behavior (AID/ID VS stress time) slightly steeper than the corresponding DC stress at the same drain voltage and at a stress gate voltage adjusted to yield the maximum substrate current (worst case described in Sect. 4) [92]. In p-channel MOSFETs, DC injection often leads to a reduced degradation [80] and thus to an enhanced device lifetime. 7.2. THE PHYSICAL EFFECTS INVOLVED DURING AC INJECTIONS

At first, it was shown by means of 2-D simulations and experiments [93] that nonstationary effects (i.e. intrinsic transient effects due to the fast changes of gate or drain voltages) are not relevant to explain the fact that a more pronounced AC degradation is found for rising and falling edges of the gate signal greater than 10-20 ps [80]. It follows that the intrinsic transient effects are not responsible for the enhanced degradation found when stateof-the-art CMOS technologies are submitted to AC stressing. The physical properties of the gate oxide and of the Si-Si02 interface, have been identified as being responsible for some of the observed transient effects, even if some controversies are not yet resolved [80,94]. These transient effects are briefly outlined next. 7.2.1. Hole transport properties in Si02 Once holes have been injected into the oxide layer during the low gate voltage part of the AC stress waveforms (see in Fig. 4.27, part A of the inverter-like or of the SRAM-like waveforms), they move slowly by hopping between neighbouring oxygen atoms, with a mobility of the order of 2xlO"5 cm^V-ls"! [95]. Thus, for a field of 0.5 MV/cm across the oxide, holes require 10 ns to drift over 1 nm. In the inverter-like case, if the frequency is high and if the holes do not have enough time to drift and get trapped by deep hole traps in the oxide, they are repelled to the interface during the period corresponding to the high gate voltage and low drain voltages (part B of the waveform in Fig. 4.27-a), and they no longer contribute to the device degradation.

312

D. Vuillaume

On the contrary, during SRAM-like conditions, the positive Vj) value (part B of Fig. 4.27b) pushes the holes towards the gate. The holes could be efficiently trapped into the oxide leading thus to an enhanced degradation. 7.2.2. Detrapping effects After being injected and trapped in the oxide, carriers can be detrapped either by tunneling back into the silicon [84] or by field-enhanced emission [50]. This occurs when a gate voltage is applied while the drain voltage is nil (Part B of the inverter-like waveform provides a typical example). Such detrapping effects have been clearly demonstrated in the case of hole injection/trapping in n-channel MOSFETs and electron injection/trapping in p-channel MOSFETs at low gate voltages [92]. The detrapping of trapped electrons seems a very efficient mechanism in prolonging the lifetime of p-MOSFETs under AC stress. 7.2.3. The effects of alternating injections (hole/electron) In n-channel MOSFETs, it has often been observed that if a brief electron injection follows a period of hole injection, it results in an increased degradation (see § 4.2) [43,45,49]. Such a typical situation is often encountered during the AC stress (see the inverter-like and SRAMlike waveforms in Fig. 4.27). Two models have been proposed to explain this behavior but both are still a matter of controversy. In the first model [92], the injected electrons neutralize the previously trapped holes. We know that in n-channel MOSFETs the positive charges in the oxide reduce the longitudinal electric field and slow down further hole injection. When the trapped holes are neutralized by electron injection during the AC stress, the longitudinal field is restored, and an additional hole injection at low gate voltage is again possible during the next period. Compared to the case of DC stress conditions at low gate voltage, for which this neutralization does not occur, this effect leads to an increased degradation. The second model states that neutral electron traps are created by hole injection [45,49,53,86] (see § 4.3.3). These neutral traps are then filled during electron injection at high gate voltages. They could explain the observed enhanced degradation. Let us note that the degradation induced by AC stress for various waveforms (SRAM, inverter) has been recently fully predicted from DC stress experiments (quasi-static approach) by incorporating three mechanisms: • the creation of interface states at low and medium gate voltages (see Sect. 3), • the creation of oxide electron traps at high gate voltages (see Sect. 4) and, • the creation of oxide electron traps at low gate voltages (see Sect. 3) [96]. The altemating injection effect seems very efficient in explaining the enhanced degradation observed in AC stressed n-channel MOSFETs.

Hot Carrier Injections in Silica

313

7.2.4. Relevance for circuit operation From an engineering point of view, we should bear in mind the envisaged circuit applications before performing AC experiments to test the reliability of a given technology. In fact, in many cases, the behaviors of the n-channel and the p-channel MOSFETs compensate one another. The drain current usually decreases in the n-channel device and increases in the p-channel device. The AC injections enhance the degradation in the n-channel device and reduce it in the p-channel device. It follows that the degradation of a ring oscillator is less than the corresponding degradation of the individual n- and p-channel MOSFETs which make up an inverter in the chain, even for working conditions at very high drain voltages [97,98]. For the engineers in charge of technology and of circuit reliability, and considering the inverter operation mode, the main transient effects involved during AC stress experiments are [80]: • the altemating injections of holes and electrons in n-channel MOSFETs, which can lead to a reduction in device lifetime of about one order of magnitude (for a reasonably good technology), • the detrapping of holes in p-channel MOSFETs, which prolongs the device lifetime. If we want to assess the final reliability of the circuits fabricated with a given technology, it is necessary to take into account several well-defined operating conditions (waveforms, rise and fall times) and to define the suitable technique to estimate the product lifetime (duty cycle weighting, for instance) [80,96,97]. 8. THE MICROSCOPIC NATURE OF THE DAMAGE INDUCED BY HOT CARRIER INJECTION (HCI) During the injection of hot carriers into Si02, two basic phenomena can occur. The first one is the trapping of the injected carriers by the pre-existing traps in the oxide. These traps are related to the intrinsic defects of the material or to the process-induced defects. The second one is the creation, by the injected hot carriers, of new defects at the Si-Si02 interface and in the oxide. The traps pre-existing in Si02 have been widely studied and an overview has been given in Chaps. 2 and 10 (Vols. 1 and 2 of this series). This review is updated in Chap. 11 of this volume. The intrinsic defects at the Si-Si02 interface, which are characterized by the socalled interface state density, are also well known (see Chap. 11 of Vol. 2). On the contrary, the exact nature of hot carrier-induced defects is still a subject of controversy. This section aims at reviewing some basic results on this topic.

314

D, Vuillaume

8,1. NATURE OF THE DEFECTS CREATED AT THE S1-S1O2 INTERFACE 8.I.I. Basic experimental results on fast interface states The most important intrinsic defect encountered at the Si-Si02 interface is the so-called P^^ center, i.e. a three-fold coordinated Si dangling bond defect symbolized by: 813 = Si* (see [99] and also Chap. 11 of Vol. 2). Substrate

oxide

gate

neg. stress

pos. stress

Ref.

<100>

wet

poly-Si

n.m.

YES

[104]

<100>

ultra-dry

poly-Si

n.m.

NO

[104]

<111>

CVD

Al

NO

n.m.

[105]

1

<111>

wet

no gate

n.m.

YES

[106]

1

<100>

(not given)

poly-Si

YES

n.m.

<111>

dry

no gate

NO

n.m.

[101] [125]

<111>

wet

no gate

NO

n.m.

[125]

<111>

damp [H2O] = 0.1% [H2O] > 1%

no gate no gate

YES NO

NO n.m.

[125] [125]

dry

Al

n.m.

NO, but " Pb-like "

[102]

<100>

1

Table 4.1 Observation, by means ofESR, of the P^ centers generated by high electric field stresses for various oxides and as a function of the sign of the stress bias applied to the oxide, (n.m. means "not measured").

^10" •E

fc

III mm

I I I iiiiii

t

2 nm from interface

I I I imu

•(0

c

1.5 nm from H interface

•D

B (0

• "•'

10

17

'

10,20 Slow state density (cm"^eV^)

Fig. 4.28 Correlation observed between the densities of fast and slow interface states created at the Si-Si02 interface during HCI in the oxide by homogeneous Fowler-Nordheim tunneling injection. Fast states have been measured by DLTS and slow states by Tunnel-DLTS. The fluence of injected electrons is: 1.6x10' C/cm , tox = 75 nm. (After [118]).

Hot Carrier Injections in Silica

315

This representation is well established for the <111> surface, but the situation at the <100> interface is complicated by the existence of, at least, two P^ centers which are physically and chemically different [100]. The microscopic model for the so-called P^Q center is Si3=Si*, while the Poindexter model ascribed to the P^i center is Si20=Si* [100]. This identification of the Pb centers at <100> interfaces is still a subject of controversy [101], and it is beyond the scope of this chapter to discuss this topic. In state-of-the-art devices, these defects are mainly passivated by hydrogen, yielding a residual interface state density Dj^ ranging from 10^ to 10^^ cm'^eV-l. These states are called fast interface states because the defects are located at the interface (typically within one atomic distance) and because their charge state depends on the position of the Fermi level at the interface. Typically, the exchange of carriers between the defects and the valence or conduction bands take place in less than a few ms. The main question about the nature of HCI-induced defects is: "does the injection of hot carriers de-passivate the P^ centers or does it create new types of defects?". Table 4.1 summarizes extended results [102, 103]. It shows that no clear and final picture can be drawn at the present time. Most of these results have been obtained using homogeneous HCI in large size MOS capacitors or transistors (through avalanche injection, Fowler-Nordheim injection, etc., [201, 202]). This is because the most accurate technique which allows one to determine unambiguously the microscopic nature of the defect, namely the electron spin resonance (ESR) technique3, needs large area devices. Besides, the determination of the nature of the created defects by a single electrical technique is a very difficult task [103]. Only recently, has a new variation of this ESR technique been successfully applied to small geometry MOSFETs [107-110]. This technique named Spin-Dependent Recombination (SDR) or Electrically Detected Magnetic Resonance (EDMR) (and described in Appendix 2), has shown that P^ centers have indeed been created in small transistors by HCI at low V^ [108] and in some cases by homogeneous electron injections, depending on the mechanisms of interface state creation [109, 110] (see § 8.1.3). 8.I.2. Other interface defects (slow interface states) It has been shown that positive charges appear in the bulk of the oxide upon hole injection (due to hole trapping in pre-existing traps [43]). However, positive charges may also appear at the Si-Si02 interface upon electron injection when the oxide field is sufficiently large (over 7 MV/cm) [112,113]. This is especially visible for small fluences of injected charges in the oxide (typically less than 0.001 C/cm^). At higher injected fluences, these positive charges are masked by electron trapping. Profiling techniques have shown that these positive charges are mainly located within 3 nm from the Si-Si02 interface [114].

3 For the readers not familiar with the microscopic identification of defects in semiconductors, see a brief description of the basic principles of ESR in the first Refs. quoted in [99] and in [111]. See [181] for a detailed description.

316

D, Vuillaume a)

Interface trap creation by depassivation of a P^ center

Interface states Substrate

^N(E)

Hydrogen-related species b) Interface trap creation by impact ionization

Interface states Substrate

^N(E)

Fig, 4.29 Schematic description of the two main degradation mechanisms in Si02 and at its interface with Si. (a) Trap creation by the release of hydrogen-related species at the anode (here, the gate), and diffusion across the oxide, (b) Hole generation by impact ionization at the anode, and trapping near the cathode-Si02 interface. Trapped holes lead to the formation of a positive charge and to the generation of interface states (After [112], slightly modified).

Hot Carrier Injections in Silica

317

These positive charges have been related to donor-like defects located in the oxide close to the Si-Si02 interface. They are also called slow interface states (or border traps [115]) since they can exchange carriers with the Si substrate via a tunneling mechanism, with a capture and an emission time constant ranging from a few milliseconds to a few hundred seconds. These slow interface states can also be accurately characterized by Tunnel-Deep Level Transient Spectroscopy (Tunnel-DLTS) [116]. This technique, which is a variant of the standard DLTS technique described in Chap. 12 of Vol. 2, takes into account the tunnel interaction between slow states and carriers from the substrate. It allows one to characterize separately the properties of the fast and the slow interface states (density, capture crosssection). Recently, the charge pumping technique has also been used to characterize these slow states [117]. Figure 4.28 shows that a linear correlation is found between the concentration of slow and fast interface states created by HCI [118]. This result suggests that there exists a similarity in the physico-chemical nature of these defects and in their creation mechanisms. 8.I.3. The creation mechanisms Two basic models have been proposed to explain the creation of defects at the Si-Si02 interface upon carrier injection. They are hereafter called the hydrogen-related species diffusion model and the impact ionization model. The role of hydrogen species in the creation of interface state has been clearly established by several research groups [118-123]. The basic mechanism is described in Fig. 4.29-a. The hot electrons entering the oxide can gain enough energy to cut loose some hydrogenated species in the oxide or at the anode-oxide interface. These species diffuse across the oxide and pile up at the Si-Si02 interface where they are able to create interface defects. One possible explanation is that the incoming species de-passivate the Pb centers according to the following type of chemical reaction : / ^ i / + [ / / ] ^ / ^ + //*

(4.22)

where PbH represents a hydrogen-passivated Pb center, [H] stands for any form of hydrogenated species (H, H+, OH, etc.), and [H*] is any form of combination of [H] with the atomic hydrogen released from the Pb center [124]. This model could also explain the creation of interface states by X-ray and g-ray irradiations (see Chap. 11 of this volume). Chemical reactions more complex than (4.22) have also been suggested [125], but (4.22) should be considered as the simplest specific case. This model has been found to apply whenever the oxide field Fox exceeds about 1.5-2 MV/cm [121]. In the second model, historically the oldest one, the degradation is related to the generation of holes by impact ionization across the 9 eV of the Si02 band gap [126] (see also Sect. 8.5 in [201]). The impact ionization model was first ruled out when it was discovered that the average energy of hot electrons in Si02 never exceeds 5-6 eV [127].

318

D, Vuillaume

However, a high energy tail (in the 9-12 eV range) was later observed in the energy distribution of the hot electrons in thick oxide (tox > 20 nm) at high field (above 7 MV/cm) [112]. Recently, the relationship between defect creation and impact ionization has been reexamined both theoretically and experimentally [112,128], and it has been proved that this model fully accounts for the formation of positive charges and the creation of interface states [112,113]. In this model, the holes generated by impact ionization in the oxide can get trapped Si-Si02 interface as illustrated in Fig. 4.29-b. Several results have shown that interface can be created when the injected electrons recombine with the trapped holes located to the interface (< 3nm) [51,129]. The exact nature of this transformation mechanism clear yet.

at the states close is not

This second model requires a high electric field in the oxide because hole generation is only possible when the injected carriers have reached the threshold energy for intra-band impact ionization. On the contrary, in the first model, the energy required to de-passivate the P^ center is almost the binding energy of the Si-H bond. This energy varies from « 0.8 eV to 3.1 eV [130,131], depending on the oxide process, the lowest value accounting for possible weaknesses induced by local disorder at the interface. Many experiments have been performed in order to check the respective role of these two mechanisms on the degradation of MOSFETs. These experiments deal with the effects of injected fluences, oxide fields, oxide thicknesses and temperature at which injections have been performed [112,113,118,121,122,128]. Table 4.2 sunmiarizes the basic behaviors observed for the hydrogen-related species (HRS) model and for the impact ionization (II) model. The HRS mechanism is active whatever the oxide thickness may be, whereas the n mechanism requires a thicker oxide to let the electrons gain enough energy (E > 9 Ev) to generate electron-hole pairs [112,113,128]. The n mechanism also requires a large oxide field (Fox ^ 7.5 MV/cm), while the HRS mechanism occurs as soon as the oxide field is larger than about 1.5 MV/cm, leading to electrons with energy larger than about 2 eV at the anode [112,121]. It has also been observed that trap creation by the HRS mechanism is strongly temperaturedependent while trap creation by the n mechanism is either weakly temperature dependent or independent of temperature [112,113,118,122]. Activation energies for trap creation by the HRS mechanism in the 50meV to 0.2 eV range have been reported [113,118,121,122]. By studying the trap creation kinetics, it was found that the n mechanism dominates at lower injected fluences (typically for less than 10'^ - 10'^ C/cm^) and that the HRS mechanism appears to be the prevailing mechanism responsible for trap creation at higher injected fluences [112,113]. However, this critical injected fluence depends on the technology, and a lower value is expected for devices with an aluminium gate (as compared to devices with a polysilicon gate) since the A/-gate process is known to introduce much more hydrogen into the gate oxide. Table 4.2 should be viewed as a "road map" helping one to recognize a degradation mechanism when studying the reliability of oxide films on silicon.

Hot Carrier Injections in Silica

319

1013 M 1

c

10^2

E o

"^^mm^

Q. b.

10^^

•o

*^ •o

3

B 10^0

"5. E

(0 0)

O

(0

10^

10-® 10-^ 10"^ 10-^ 10-2 10"'' 10° 10^

Q LU

Injected fluence (C/cm^) Fi'^. 4.30 Generation kinetics of interface states (—) as measured by an electrical technique (CV technique) and of Pho centers ( ) as measured by EDMR on the same device. The stress has been performed by FowlerNordheim injection at 9 MV/cm, with t(,x = 67 nm. (After [109], slightly modified).

CB

1 eV C

B1

D1

D2

2 eV 82

3 eV A Fig. 4.31 Energy levels in the forbidden gap ofSi02 for the 0/- transition of several defects : O^^i^ (levels A, Bl and B2, O vacancy in bulk Si02 (level C) and near the Si-Si02 interface (levels Dl and D2). Level E is from HCI experiments described in [50,133]. Different levels for the same defect correspond to different theoretical studies (see detail in [133]).

320

D. Vuillaume

By using EDMR to analyze the nature of the defects created by the homogeneous injection of electrons in the gate oxide of small-size transistors fabricated on <100> oriented surface, it has recently been shown that only the P^Q center is created when the prevailing trap creation mechanism is the release and diffusion of hydrogen species [109]. However, it was also observed (Fig. 4.30) that the number of created P^o centers was too low to account for the whole interface state density as measured by electrical means (C-V or charge pumping techniques). At fluences below 10" C/cm (Fig. 4.30), for which the creation of traps is dominated by holes generated by impact ionization, no paramagnetic signal has been observed while electrical techniques show the efficient creation of interface states (see Appendix 2 for a discussion of the sensitivity of the EDMR technique). Presently (1994), the creation of the other defect, the Pj^j center, has not yet been observed, even when performing the EDMR measurements in a large range of temperatures [110] in an attempt to take into account the difference in the carrier capture properties of the two defects, P^O ^^d Pbl [132]. However, it is not completely clear at the moment, whether the P^j center is not created or whether it is simply not observable through the EDMR technique. Hydrogen-related species (HRS) mechanism

Impact ionization (n) mechanism

Oxide thickness

No

Yes (larger than « 20 nm)

Temperature

Strong

Weak or independent

Injected fluence('^)

>10"^-10'^C/cm^

< 10"^ - 10"^ C/cm^

Oxide field

> 1.5 MV/cm (or energy larger than « 2 eV)

> 7.5 MV/cm (or energy larger than - 9 eV)

Table 4.2 Dependence of the two main degradation mechanisms on oxide thickness, oxide field, injected fluence and on that temperature at which the carrier injections are performed. This table should be viewed as a "road map" to recognize a degradation mechanism when studying the reliability of oxide films. %.2. NATURE OF THE DEFECTS CREATED IN THE BULK OXIDE

In § 3.2, we showed that the injected electrons can be captured by the oxide traps created by HCI during the long-time aging of MOSFETs. This capture event occurs very rapidly (typically in less than 100 sec) compared with the time needed (up to 10"^ sec) to create a significant concentration (i.e. a few lO^^ cm-^) of these oxide traps [49]. Several results have recently been obtained which allow one to determine the electronic properties of these HCIrelated oxide defects [133].

(4) Should depend on the process, especially on the gate (aluminum or polysilicon) process. See text for details.

Hot Carrier Injections in Silica

321

In the case of HCI at low VQ, the defects exhibit large capture cross-sections, ranging from 10-14 to 10-1^ cm^ [133]. Combining photodepopulation spectroscopy and field-enhanced emission time constant measurements, one has been able to determine that the energy levels of these defects lie between 1.7 and 3 eV. Moreover, it was also found that the oxide traps created by HCI at high VQ (see Sect. 5) exhibit the same electrical properties, thus suggesting a similar nature [50,133]. In the absence of any ESR data (absence due to the preferential localization of these defects near the drain side of the submicrometer MOSFETs), speculations on the nature of HCIinduced defects can only come from a comparison with theoretical results [133]. Figure 4.31 sunmiarizes the most likely energy levels for these HCI-induced defects. These levels are mainly related to the several possible forms of Si dangling bond defects which have been identified in the oxide bulk or near the interface. Recently, EDMR measurements have shown that an E' center, i.e. an oxygen vacancy, 03=Si* •Si=03, with two silicon dangling bonds, should be created by HCI at low gate voltage [108], in agreement with the conclusions of the electrical experiments. However, more complete EDMR experiments are required to confirm this creation. 9. TECHNOLOGY AND DEVICE ENGINEERING In order to reduce the instabilities induced by hot carrier injection, researchers and engineers can try to further improve the quality of the materials (for instance the gate oxide) to make them more resistant against defect creation. They can also improve the design of the devices to reduce the electric field in the channel or to obtain a better control of the parasitic effects (especially in the case of the LDD structures). Concerning the gate material, it was recently demonstrated that reoxidized nitrided oxides (abbr. RONO), described in Chap. 1 are more resistant than both nitrided oxides and standard thermal oxides [91,134]. Some reports have also mentioned the better quality of the fluorinated oxides [135], of the RTP (rapid thermal process) oxides [136], or the benefits of the "irradiation then anneal" cycles [137]. The role of the passivation layer has also been pointed out. Passivation with plasmadeposited nitride was shown to degrade the reliability performances of the gate oxide [138]. It is also known to induce mechanical stresses or to indroduce a large amount of hydrogen. Both effects are detrimental since they increase the generation rate of the interface defects under hot carrier injection(^). However, a double layer (oxide at the bottom and nitride at the top) has been proposed as an efficient passivation layer which combines the good barrier properties of the nitride and the good hot carrier reliability of the oxide [139].

(5) See also the detrimental effect of nitride passivation on the AC enhanced degradation (Sect. 7, Fig. 4.25).

322

D, Vuillaume

Poly-Si Spacers a)

Oxide Silicide

b)

Poly Si

P" substrate Fig, 4.32 Cross-sections illustrating four advanced transistor structures proposed to improve device performances: (a) The inverse T-gate to make a gate-overlapped LDD (GOLD) structure, (b) The total overlapped LDD with polysilicon spacer (TOPS), (c) The biased-spacer LDD structure, (d) The double LDD concave (DLC) structure. (After [146-150], slightly modified).

Low Doped Drain (LDD) structures have been designed to reduce the magnitude of the longitudinal electric field near the drain, by introducing a smooth junction transition with a reduced doping concentration (n") between the channel and the drain [140]. However, this n" region lies underneath a spacer oxide, and the gate-control of the field and carrier concentrations in this region in order to avoid specific parasitic effects (such as charge trapping in the spacer oxide) is difficult to obtain. For instance, a careful optimization is required for the n' implantation dose [141], for the tilt angle during the n" implantation [142], for the shape and the nature of the spacer (oxide, nitride, polysilicon) [143,144]. Consequently, LDD MOSFETs are not suitable for deep submicrometer technologies below 0.35 |Lim [145].

Hot Carrier Injections in Silica

323

To overcome these difficulties, several new structures have been investigated in order to build reliable(6) devices operating at 5 and 3.3 V with channel lengths in the 0.5-0.6 and 0.20.3 |Lim ranges, respectively. It was demonstrated that a precise gate control of the field over the n' region is crucial to achieve both good performance and reliable LDD devices. Four such structures are shown in Fig. 4.32. • The inverse T-gate shape has been proposed to obtain a gate-overlapped LDD structure (GOLD) as illustrated in Fig. 4.32a [146,147]. • The total overlap with polysilicon spacer (TOPS) structure has also been suggested to make sure that the gate fully overlaps the Ughtly doped region [148], (Fig. 4.32b). • The longitudinal electric field can be reduced when polysilicon LDD spacers are independently biased with respect to the gate electrode. Such a structure has been manufactured with polysilicon LDD spacers connected to the source and drain electrodes by titanium silicide [149], as illustrated in Fig. 4.32c. • Three-dimensional structures, such as the double LDD concave (DLC) MOSFETs have also been proposed. There, the silicon substrate is etched to form U-shaped grooves with the source and drain junction depths shallower than the depth of the grooves, and with an impurity profile of n+-n"-p"-p+ along the sidewall of the grooves [150] as illustrated in Fig. 4.32d. For p-channel MOSFETs the gate material (i.e. n+ versus p+ polysilicon) also plays a part. It has been outlined in § 6.3.

10. FUTURE TRENDS AND CONCLUSION The basic features and the degradation mechanisms reported in this chapter have been well established for state-of-the-art devices with a channel length in the 0.5-1 |Lim range. However, in laboratories, the research programs aim at fabricating even shorter devices. Although several reports have demonstrated the feasibility of 0.1 |im MOSFETs [151-155], the hot carrier reliability of these deep-submicrometer devices is questionable and is therefore a subject of interest. As device dimensions shrink below the half-micrometer range, the drain voltages must be reduced. In the case of deep-submicrometer MOSFETs (0.1-0.2 |Lim), operating at drain voltage Vj) lower than 3 V, one would expect (based on the lucky electron model, for which carriers gain all their kinetic energy from the applied extemal potential, i.e. a maximum kinetic energy qV^ without any scattering phenomena) that the carriers in the channel cannot gain an energy larger than the potential barrier, which should turn off the hot carrier injections.

(6) For instance a lifetime greater than 10 years at voltage 10 % greater than the nominal voltage.

324

D. Vuillaume

,21

10^' i

T

1 I I I I I

T

1

1

1 I I I

i

t

I

I

l|

CM

i

\

102° I

\

t

(0

I

19

2 10'^ fc-

\

\

\

11 © 10^^ k-

I

Z 10^5

10'

t

I

J

i i t i i I

10^

i I

10^

Oxide thickness (nm) Fig. 4.33 The number of injected electrons, needed to create the same amount of interface defects (see the text for details), is plotted as a function of the oxide thickness. Measurements have been performed at various oxide fields (8 -12 MV/cm). (After [157], slightly modified).

Moreover, when the oxide thickness reaches the 5 nm range and below (which is the case in 0.1 |im devices), electron fluences greater than 10^ C/cirfi have been shown to flow through the gate oxide without significant defect creation, or destructive breakdown [156]. This is also illustrated by the fact that a roughly linear relationship (using a log-log plot) has been observed between the decrease in oxide thickness and the increase in the number of injected electrons needed to create a given concentration of defectsC^) as illustrated in Fig. 4.33 [157]. This is mainly due to the fact that in such thin oxides, carrier transport is mostly ballistic. Thus one could conclude that deep-submicrometer MOSFETs should be free of phenomena associated with hot carrier injection. However, and unfortunately, the real situation appears less simple. It has been shown that the carrier energy may significantly exceed qVj), allowing hot carriers to be injected in ultra-small MOSFETs.

(7) In the present case, for interface states and for a creation following a first order kinetic, this quantity is defined as the number of injected electrons needed to reach a level of defects of 1/e (with e the Neperian) below the number of defects at saturation.

Hot Carrier Injections in Silica

325

For L = 0.15 |im, one has observed that a substrate current is generated when Vj) exceeds 0.7 V, and that a gate current is measurable for V^ values as low as 1.8 V [155]. It was also shown that a 10^ to 10^ % relative increase in the interface state density is observed after stressing a 0.15 |iim transistor with Vj) values comprised between 2.2 and 2.7 V (VQ = IV) during about 10^-10^ min. From the first experimental reports [153,155], it seems that the behaviors of the substrate and gate currents in deep sub-micrometer MOSFETs, as well as the degradation behaviors look like those of longer channel devices. The longitudinal electric field is still determined by Vj) - V^sat, as in (4.4), and the substrate current is still exponentially dependent on this field, as in (4.3), even if this relationship is no longer independent of the channel length [153]. The gate current is still correlated with the substrate current, as in (4.17). Moreover, the degradation is shown to depend on the gate voltage in a manner identical to that of micrometer MOSFETs [155], i.e. with a maximum degradation obtained for a stress (gate) voltage which corresponds also to the maximum of the substrate current (as illustrated in Fig. 4.12). Several mechanisms have been suggested to explain that the carriers can acquire an energy larger than qV^ in the case of low drain voltages [155]. • Due to the heating from frequent electron-electron and/or electron-phonon collisions, a hotelectron gas could exist at an elevated electron temperature. • Heating due to thermionic emission over the barrier in the presence of a vertical electric field can explain the injection of carriers in the gate [158]. • Auger recombination where an electron-hole pair recombines, transferring its energy to another electron closer to the top of the potential barrier, can also lead to an efficient injection in the gate oxide [159,160]. In conclusion, it seems that the basic hot carrier concepts can continue to be used in lowvoltage deep-submicrometer MOSFETs, even if the physical mechanisms responsible for the hot carrier generation are not clearly established in that case, and need to be further investigated. Futhermore, for MOSFETs in the 0.1 |Lim range, new and interesting physical studies become possible. First of all, since the channel length becomes comparable with the mean free path of carriers (at liquid helium temperature), non-stationary and quantum transport can be studied in these devices. Typical examples are : i) velocity overshoot [161,162], ii) reduction of the electron temperature due to near ballistic transport [163], iii) observation of Shubnikov de Haas oscillations [161]. The reduction in electron temperature should be favorable to a reduction of degradation induced by hot carriers. However, many of these studies need to be carried out at helium temperature and it is difficult to extend their conclusions to room temperature. For instance, the degradation of 0.1 |Lim MOSFETs has been investigated at room temperature with injections performed at maximum substrate current, and it was demonstrated that a significant interface state generation had taken place. Moreover, it was shown that this degradation tends to be uniform, namely that the degraded zone tends to extend over the entire channel length instead of being mostly located near the drain as in larger devices [162].

326

Z). Vuillaume

Reducing both the size of the active gate area and the gate dielectric thickness also leads to opportunities for new devices as pioneered by works on single electron devices (SED) [163166]. These devices are based on the effect known as Coulomb blockade. In devices with gate area less than 0.1x0.1 \ivcfi and gate dielectrics thinner than 5 nm, the gate capacitance is so large that the Coulomb energy associated with the transfer of an elementary carrier charge through the capacitance is of the order of a few tens of millivolt. At low temperature (down to a few Kelvin) this energy is sufficient to prevent the transfer of further charges, thus leading to the concept of SED. On the other hand, deep-submicrometer MOSFETs (e.g. with a gate area smaller than 1 iim^) open the door to studying Si-Si02 interface defects at their ultimate level: capture and emission of a single carrier by a single trap [167]. In such devices with a state-of-the-art quality of interface (e.g. a state density of 10^^ cm-^eV-^), less than 100 traps are present under the gate and only a few of them are active because they have an energy level located near the Fermi level at given bias conditions. Any fluctuation in the occupancy of an individual defect generates a discrete switching in the drain current [168, 169]. This peculiar instability is known as random telegraph signal (RTS) and its amplitude (easily observable) is typically of the order of 0.1% of the channel current. Models explaining the relative amplitude of RTS have been proposed, mainly based on fluctuations in carrier number and mobility [170-172]. Typical time constants of RTS range from a few milliseconds to thousands of seconds, and have been attributed to an exchange of carriers between the traps located in the oxide (a few A from the interface, i.e. within a tunneling distance) [167]. RTS is observable over a large temperature range (from liquid helium temperature to room temperature). The study of RTS due to carrier trapping and detrapping on single defects in small size MOSFETs offers the possibility to analyze and reveal some unexplored aspects of the Si-Si02 interface defects. Some important clues are briefly outlined in the following. • An entropy change associated with the change in the charge state, and the corresponding change in the trap energy level has been analyzed [173,174]. • Complex dependences (which do not follow the Shockley-Read-Hall theory) of the capture and emission time of individual defects with respect to carrier density in the channel have been ascribed to the Coulomb blockade effect with large (a few hundred millivolts) Coulomb energy [175]. • Anomalous (for instance three-level fluctuations) RTS have been observed and explained by the possible existence of two (or more) charge-equivalent metastable states for the same individual trap as a result of the inherently amorphous character of the Si02 [176]. • Effects of electron heating on the capture time of a single trap have been investigated and well described by the general formalism of "carrier capture by multiphonon emission" [111] for the capture of carriers by traps [177, 178].

Hot Carrier Injections in Silica

Zll

• Finally, RTS measurements have been used to analyze single traps induced by hot carrier injections [179]. It was found that HCI-related traps are located closer to the interface, and the traps near the conduction band edge have been identified as acceptor-like for n-channel MOSFETs and donor-like for p-channel MOSFETs [179]. In conclusion, deep submicrometer MOSFETs with a channel length close to the mean free path of carriers, display new and interesting physical features, which can be bothersome for future advanced devices, or on the contrary, which may offer opportunities for new concepts and devices. ACKNOWLEDGEMENTS I wish to thank A. Bravaix and D. Goguenheim for fruitful collaborations and discussions. I am grateful to A. Boudou, J.C. Marchetaux and A. Zylbersztejn for the 2 years of fruitful collaboration we had at the BULL S.A. R&D research center, and to B.S. Doyle (INTEL) for helpful comments and collaborations in this research topic. Special thanks are due to E. Litton and G. Barbottin who have carefully read and improved the English manuscript, and to A. Kaiser who has provided the German translation of the abstract. Note: This chapter was written in 1994, and additional results and data have been published since then, especially on dynamic stress, stress-induced leakage currents in very thin oxides, etc. Some of these new results can be found in [203].

328

D. Vuillaume APPENDIX 1 BASIC PRINCIPLE OF THE FLOATING GATE TECHNIQUE

The basis of the FG technique is described in refs. [15] and [16]. In what follows we point out how we have used this technique (first at BULL S.A. and later at lEMN-ISEN) to characterize damage created by HCI in MOSFETs (i.e. interface states and oxide traps) [49,59,60,61]. Let us first recall the basic principle of the technique. The potential of an isolated gate is modified by the injected carriers which reach it by following the oxide field lines. If we call CQ the capacitance of the gate node (including the constant capacitance of the probe pad), AQQ the electronic charge collected by the gate electrode during time interval At and IQ the corresponding gate current, we can write: ^^-

^

"^^

At

^^^-^^

However, any variation in gate voltage (AVQ) induces in turn a variation in drain current AIj) given by: ^D = gm^yG

(A1.2)

where g^ is the transconductance of the transistor. It follows that the collected gate current can be expressed as :

' - = 1 ^

(A..3)

Moreover, gate voltage V Q is given directly by : VQ^-^

+ VJ

(A1.4)

Sm The transconductance g^^ and the gate capacitance CQ are easily measured at all gate and drain voltages applied to the device during the FG measurement, and the threshold voltage Vx is measured by recording the I^ - VQ curve in the linear mode. The measurements are performed on a single isolated MOSFET (no common source pad nor common gate pad). Let us now consider an n-channel MOSFET (the same applies to a p-channel device with the usual changes in notation and polarity). Before the FG measurement itself, we measure the Ij) - VQ characteristic in the linear regime (Vj) = 50 niV) and the I^ - V Q characteristic in the saturated regime for the drain voltage used during the FG measurement (here V^fg = 6 V) and for the range of gate voltage probed during the FG measurement. The gate is then biased at the upper gate voltage (here 9 V) during 30 sec, after which the gate probe is lifted (the micro manipulator is mounted on an automated step motor). The time variation of the drain current (l£)(t)) is monitored until Ij) reaches a lower value corresponding to the chosen lowest gate voltage (here 5 V) according to the saturated Ij) - V Q characteristic.

Hot Carrier Injections in Silica

329

Since the gate has been positively charged, each injected electron reaching the gate decreases the charge stored in the isolated gate, which corresponds to a decrease in gate voltage and a decrease in drain current (Fig. Al-1). From the l£)(t) characteristic, we calculate the gate current IQ by using the time derivative of the curve according to Eq. (A 1.3) and we deduce the corresponding gate voltage from the ID - VQ curve according to Eq. (A 1.4). Typical IQ - VQ characteristics are given in Fig. A1-2. We must make sure that the drain voltage applied during the FG measurement is sufficiently low to avoid self-degradation during the measurement. This can be verified if after performing repetitive FG measurements, no significant change in the successive I Q - V Q characteristics is noted. Moreover, charge pumping measurements recorded before and after the FG measurement should be strictly similar [59]. For the MOSFET under test (in Figs. Al-1 and A1-2), the typical values of CQ, g^^ and AIjyAt are 0.6 pF, 10 mA.V-1 and 0.1-1 ILIA.S"!, respectively, leading to a minimal detectable gate current of about 6x10"^^ - 6xlO"l'7 A. In order to verify that no oxide leakage current perturbs the gate current measurement, an FG measurement is systematically performed at a low drain voltage (for instance 2-3 V) for which no sizeable hot carrier injection is expected. For instance, we have observed (on a large number of samples) only a very weak change in the drain current after the gate probe has been lifted. This drain current variation has been estimated to correspond to a resistance as high as lO^^-lO^^ Q. This has no influence on the gate current measurement. Moreover, in order to reduce the surface leakage current, the probe station is placed under a flow of dry nitrogen gas. The FG technique has been used to monitor the evolution of \Q induced by HCI [49,59,60,61]. Because the FG technique uses the "source" of the degradation (i.e. the hot carrier injection itself) to probe the IQ - VQ characteristics, this technique can, in fact, be used as a local probe to monitor the effects of localized oxide charges on the behavior of IQ. Figure 4.17 (Sect. 5) shows a typical example of this behavior during a hot carrier stress at VQ = Vj) = 8.5 V. In this case, the aging has been periodically interrupted to perform the FG measurement at V^fg = 6 V. Thus, the FG technique is a direct method to probe localized defects around the site of the electron injection point near the drain or in the gate-drain overlap region of the MOSFET. The creation of acceptor-like oxide traps has been deduced from the study of the evolution of IQ during aging when measured by the FG technique [49, 60, 61]. According to the lucky electron model (see § 3.3), the parameters which can effectively modify IQ are: the maximum longitudinal electric field ¥^ and the effective barrier potential Og which electrons must overcome to be injected into the oxide and collected at the gate. In this model, a simple expression of the gate current is given by Eq. (4.13). From this equation, we see that IQ decreases when Og increases or when Fj^^ decreases. The evolution of Fj^ is experimentally probed by multiplication factor M = IsuB^D- We have shown that M increases with stress time [60, 61], which means that Fj^ increases. This increase is due to a generation of negative charges in the oxide, which induces an increase in the effective barrier potentialO B along the channel as shown by 2-D simulations [24].

330

D. Vuillaume GO

_

50

Ou

—'

Fig. Al-1 Evolution of the drain current with time when the gate is floating. The device characteristics are: n-MOSFET, L = I fim, W = 100 /urn, tox = 20 nm. Drain voltage is 6V during the measurement.

1— 2: UJ

r) 0

10

2: 1—1

cc Vd C3

30

20 BO

100 120 140 IBO IBO 200

TIME ( s e c )

10-12

-13

10 CE

Fig. Al-2 Typical IQ (VQ) curve measured by the FQ technique and deduced from the measurement shown in Figure Al-L

Ld DC

10"

o

cc

-IB

10

G

7

B

GRTE VOLTRGE ( V )

This F^ increase should in turn induce an increase in IQ, in disagreement with our results. We therefore conclude that the observed decrease in IQ is dominated by an increase in the effective barrier potential Og induced by these oxide negative charges. One-D numerical simulations using the lucky electron model have shown that IQl^ negative charge/cm^ over 5 nm from the Si-Si02 interface could induce a decrease of a factor of 102-10^ in the gate current [180] (see also Chap. 10 of Vol. 2). However, a careful 2-D simulation of the hot carrier gate current is required to go further in the quantitative evaluation of the amount of defects linked with the observed decrease in gate current.

Hot Carrier Injections in Silica

331

APPENDIX 2 THE ELECTRICALLY DETECTED MAGNETIC RESONANCE TECHNIQUE

For the fundamental understanding of the physical nature (at a microscopic level) of defects generated during hot carrier injection, the electron spin resonance (ESR) technique is the best tool available to date. A detailed description of the ESR technique can be found in [181]. Basically, one considers an unpaired electron (paramagnetic) trapped on a defect. An electron has a magnetic momentum of rotation (spin) represented by a quantum number s which can be equal to +Vi or -Vi, This means that the energy level of the trap with an unpaired electron is two-fold degenerate. When one applies a static magnetic field H, the energy level is split by the Zeeman effect as shown in Fig. A2-1. Without further perturbation, all paramagnetic electrons have their spins aligned with the magnetic field and they occupy the lowest energy level. If, in addition, a microwave radiation of suitable frequency is applied, some spins of electrons can be flipped, allowing these electrons to occupy the highest energy level (Fig. A2-1). In standard ESR detection, this resonance condition is given by h\) = gPH (see Fig. A21) where \) is the microwave frequency, h is the Planck constant, and p is the Bohr magneton. The g-factor is a tensor which depends on the orientation of the magnetic field with respect to the defect orientation in the material. In well characterized materials, its value and anisotropy can be viewed as a "signature" allowing one to identify the atomic structure of the defect. In the standard ESR technique, this resonance is detected by measuring the absorption of the incident microwave power by the sample under test. Unfortunately, the sensitivity of such a technique is limited to the detection of about lO^^ spins in the sample, and in the peculiar case of defects at the Si-Si02 interface, this requires very large sample areas (typically - 1 cm^). Thus, this technique does not permit the identification of the atomic configuration of defects induced by hot carrier injections in modem MOSFETs whose typical gate areas vary from a few tens to a few hundreds jiim^. However, a variant of this ESR technique has been developed. This variant, the electrically detected magnetic resonance (EDMR) technique, has attracted a great deal of interest for the study of the microscopic nature of defects in small-size devices [107-110,182-197]. EDMR corresponds to a measurement of the change in the carrier recombination rate in semiconductors under the condition of spin resonance. It is analogous to electron spin resonance (ESR) except for the fact that the electrical detection leads to an enhanced sensitivity which makes this technique suitable for the study of defects in small-size devices. It can be applied to defects for which the recombination happens to be spin-dependent. The spin-dependent recombination (SDR) of carrier in semiconductor was first discovered by Lepine in 1970 [182]. It was then applied to the study of defects in bare silicon materials [182,184], amorphous silicon [185], commercial p-n junctions [183,186-190], irradiated p-n junctions [110,191], and irradiated or electrically stressed Si-Si02 MOSFETs [107-110,192195]. The great sensitivity of the EDMR technique was demonstrated through the observation of the 29si hyperfine interactions in MOSFETs of 10-5 cm^ [196] and 4x10-6 cm^ areas [197]. This means that EDMR is up to lO^-lO^ times more sensitive than standard ESR technique.

332

D. Vuillaume

hu = gpHc

^0

Fig. A2-1 Energy level splitting of an unpaired electron (Zeeman effect) as a function of the applied magnetic field. For a given energy hv, spin flipping is allowed for a specific value of the magnetic field.

Magnetic field

ki

CB

m4

•4

A

I I

VB-

o o

Recombination forbidden

o

o

Recombination allowed

Fig. A2-2 Simplified illustration of the principle of the spin-dependent recombination of electron-hole pairs through an energy level in the band-gap.

The basic principle of SDR can be easily understood from the typical situation described in Fig. A2-2. This description is Lepine's original explanation of the SDR effect [182], and although it is an oversimplified one, it is suitable for a didactic purpose. A clear understanding of SDR phenomena is not yet (1994) established, but more elaborate theories and discussions can be found elsewhere [187,198,199]. Let us now assume (Fig. A2-2) that electrons of the Conduction Band (CB) and holes of the Valence Band (VB) recombine through a trap level (recombination center) located in the band-gap and possessing an unpaired electron (paramagnetic defect). As in a standard ESR technique, when a static magnetic field H is applied, the spins of electrons in the CB, the spins of unpaired electrons of the recombination center and the spins of holes in the VB are aligned with the magnetic field. Thus, the capture of electrons coming from the CB by the trap is forbidden.

Hot Carrier Injections in Silica

333

Again, applying a microwave radiation at a suitable frequency allows some spins to be flipped in the opposite orientation, and the trap can now capture electrons from the CB whose spin is the opposite of those of the trapped and unpaired electrons. Then, one of these two electrons can now recombine with a hole from the VB through a spin-independent mechanism since electrons with both spins are available on the recombination center. So, applying this microwave radiation at the resonance condition (i.e. with hx) = gpH as in a classical ESR technique) leads to strengthen the recombination process. This change in the recombination rate AR (where AR is defined as the difference between the recombination rate R with the microwave "on" and the recombination rate with the microwave "off) can easily be measured by electrical means. Likewise, the change in the photoconductivity of the sample, or the change in the current of a p-n junction when this junction is biased under conditions for which the generation-recombination current dominates (e.g. at weak forward bias) can be detected. In the case of interest in this chapter, namely the study of Si-Si02 defects in MOSFETs, the transistor is used as a gate-controlled p-n junction (Fig. A2-3). A slight forward bias is applied to the source-substrate and drain-substrate junctions so that the current measured through the junctions is dominated by a generation-recombination phenomenon. We then apply an appropriate voltage on the gate in order to deplete the channel. Thus, the interface states located near the source and drain junctions and acting as recombination centers dominate the recombination process. This corresponds to the peak observed in the generationrecombination current, IQR, versus gate voltage.

iDetector I iKlvstron K ESP 300 spectrometer

iLock-in

X

Field modulation

PC Field sweep*

'

Voltage amplifier (a)

(b)

Fig. A2'3 Basic principle of the EDMR technique, (a): The MOSFETis used as a gate-controlled p-n junction to study spin-dependent recombination through the Si-Si02 interface states (b): Block diagram of the EDMR apparatus.

D. Vuillaume

334

A typical example of such a current peak is shown in Fig. A2-4(a) for a <100> p-channel MOSFET (with a 20-nm-thick oxide) stressed by homogeneous electron injections from the substrate (5x10"^ cm^) under Fowler-Nordheim conditions at an oxide field of 9 MV/cm, and an injected electron fluence of 1.6x10-2 C/cm^ [HO]. Under these conditions, about 2xl0ll interface states/cm^/eV, as measured by charge pumping, are generated. With the transistor biased at the maximum of IGR (i.e. V Q ==^ -0.4 V), and now placed in a modified ESR apparatus (see a schematic block diagram of an EDMR, spectrometer in Fig. A2-3), one can easily obtain the EDMR spectra shown in Fig. A2-4(b). In the present case, an accurate analysis of the g-factor and of its anisotropy measured by EDMR, reveals that interface defects created by the electrical stress are the so-called Pbo center, previously identified by standard ESR as a trivalent silicon dangling bond Si3=Si* [99,100] (see also Chap. 11 in Vol. 2, and Chap. 11 in this volume). Similar observations (the creation of Pbo center at the <100> interface) have been obtained by different research groups, using similar stress conditions [109,110], but also under irradiation [107,193-195] and hot carrier injections [108]. All these results clearly prove that EDMR is a powerful technique to determine the atomic configuration of defects at the semiconductor-insulator interface in small-size MOSFETs. Moreover, the possibility to perform, on the same MOSFET sample, EDMR measurements and more classical electrical measurements of defects (such as charge pumping, CV techniques, etc.), and to simultaneously measure device performances (such as transconductance, threshold voltage, etc.) is an important breakthrough in the study of the fundamental physics of reliability in MOS devices and technologies. 1000

800 GOO 400 200 -0.7-O.G-0.5-0.4-0.3-0.2-0.1

3270

0

3310

3330

3350

3370

3390

MAGNETIC FIELD (G)

GRTE VOLTAGE (V)

(a)

3290

(b)

Fig, A2-4 (a) Typical generation-recombination current in a gate controlled p-n junction (MOSFET) after a Fowler-Nordheim injection at 9 MV/cm, 1.6x10'^C/cm^. Device characteristics are: p-MOSFET, L = 5 iim, W = 100 jum, tox = 20 nm. Measurement parameters: Vj) = 0.3 V. (b): Typical EDMR spectrum of the Pi,o center, recorded at room temperature (upper curve) and at 195 K (lower curve) for the above stressed transistor. The magnetic field was along the [100] direction. (After [110]).

Hot Carrier Injections in Silica

335

LIST OF REFERENCES [I] [2] [3] [4] [5] [6] [7] [8-a] [8-b] [9]

S.M. Sze, "Physics of semiconductor devices", 2nd edition (Wiley, New York, 1981), Chap 8, p. 482. Y.A. El-Mansy and D.M. Caughey, lEDM Tech, Dig., 31 (1975). P.K. Ko, R.S. MuUer and C. Hu, lEDM Tech. Dig., 600 (1981). S. Tarn, P.K. Ko, C. Hu and R.S. Muller, IEEE Trans. Electron Dev., ED-29,1740 (1982). C.R. Crowell and S.M. Sze, Appl. Phys. Lett. 9, 242 (1966). T.Y. Chan, P.K. Ko and C. Hu, IEEE Electron Dev. Lett. EDL-6, 551 (1985). C. Hu, S.T. Tarn, F. Hsu, P. Ko, T. Chan and K.W. Terrill, IEEE Trans. Electron Dev. ED-32, 375 (1985). A. Schiitz, S. Selberherr and H.W. Potzl, IEEE Trans. Computer-Aided Design, CAD-1, 77 (1982). W. Hansch and S. Selberherr, IEEE Trans. Electron Dev., ED-34, 1074 (1987). D. CoUard, B. Baccus, E. Dubois and D. Morel, "Software tools for Process, Devices and Circuit Modeling", ed. W. Crans (Boole Press, Dublin, 1989), p. 16. [10] M.R. Pinto, C.S. Rafferty, H.R. Yeager and R.W. Dutton, Stanford Electrons Lab, Stanford Univ., Palo Alto, CA, Tech. Rep. (Feb. 1896). [II] R. Subrahmanyan, Microelectronics Engineering 19, 585 (1992). [12] M.E. Law and R.W. Dutton, IEEE Trans. Comp. Aid Design, 7, 181 (1988) [13] W. Hansch, M. Orlowski and W. Weber, J de Physique, 49, C4-597 (1988). [14a] K.R. Hofmann, C. Werner, W. Weber and G. Dorda, IEEE Trans. Electron Dev., ED.32, 691 (1985). [14b] E. Takeda, H. Kume, T. Toyabe, S. Asai, IEEE Trans. Electron Dev., £0-29, 611 (1982) [15] F.H. Gaensslen and J.M. Aitken, IEEE Electron Dev. Lett., EDL-1, 231 (1980). [16] N.S. Saks, P.L. Heremens, L. Van den Hove, H.E. Maes, R.F. DeKeersmaecker and G.J. Declerck, IEEE Trans. Electron Dev., ED-33,1529 (1986). [17] S. Tarn, P. Ko and C. Hu, IEEE Trans. Electron Dev., ED-31, 1116 (1984). [18] T.H. Ning, C M . Osburn and H.N. Yu, J. Appl. Phys. 48, 286 (1977). [19] M. Garrigues, A. Alexandre, P. Rojo, K. Belhaddad and A. Poncet, J. de Physique, 49, C4-673 (1988). [20] D.R. Young, J. Appl. Phys. 47, 2098 (1976). [21] E. Takeda, H. Kume, T. Toyabe ans S. Asai, IEEE Trans. Electron Dev., ED-29, 611 (1982). [22] S. Baba, A. Kita and J. Ueda, lEDM Tech. Dig., 734 (1986). [23] M.K. Orlowski, C. Mazure, A. Lill, H.M. Mulhoff, W. Hansch, A. Schwerin and F. Neppl, Proc. ESSDERC'89, ed. A. Heuberger, H. Ryssel and P. Lange (Springer-Verlag, Berlin, 1989), p. 711. [24] P. Roblin, A. Samman and S. Bibyk, IEEE Trans. Electron Dev., 35, 2229 (1988). [25] W. Schockley, Solid State Electron., 2, 1537 (1958). [26] N.L Tisnek and A.P. Dimitrev, Sov. Phys. Semicond 31, 93 (1987). [27] Th. Vogelsang and W. Hansch, J. Appl. Phys. 69, 3592 (1991). [28] N. Goldsmann and J. Frey, Solid State Electron. 31, 1089 (1988). [29] B. Ridley, J. Phys. C 16, 3373 (1983). [30] N. Golsdmann, L. Henrickson and J. Frey, IEEE Electron Dev. Lett., EDL-11,472 (1990). [31] M. Lanzoni et al., IEEE Electron Dev. Lett., 10, 173 (1989) [32] M. Lanzoni; E. Sangiorgi, C. Fiegna, M. Manfredi and B. Ricco, IEEE Electron Dev. Lett., 12, 341 (1991). [33] C. Jacoboni and L. Reggiani, Rev. Mod. Phys. 55, 645 (1983). [34] C. Hao, J. Zimmermann, M. Charef, R. Fauquembergue and E. Constant, Solid-State Electron. 28, 733 (1985). [35] M.V. Fischetti and S.E. Laux, Phys. Rev. B, 38, 9721 (1988). [36] M.V. Fischetti, S.E. Laux and W. Lee, Solid-State Electron. 12, 1723 (1989). [37] C.G. Hwang, R.W Dutton,J.M.Higman and K. Hess, IEEE Trans. Electron Dev. ED-34, 2385 (1987). [38] S. Bandyopadhyay, M.E. Klausmeier-Brown, C M . Maziar, S. Datta and M.S. Lundstrom, IEEE Trans.Electron Dev. ED-34, 392 (1987). [39] E. Sangiorgi, B. Ricco and F. Venturi, IEEE Trans. Computer-Aided Design CAD-7, 259 (1988). [40] J.M. Higman, K. Hess, C.G. Hwang and W.R. Dutton, IEEE Trans Electron Dev. ED-36, 930 (1989).

336

[41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] [59] [60] [61] [62] [63] [64] [65] [66] [67] [68] [69] [70] [71] [72] [73] [74] [75] [76] [77] [78] [79] [80] [81] [82]

D, Vuillaume

E. Dubois, P.H. Bricout, R. Fauquembergue and D. Collard, lEDM Tech Dig,, 519 (1991). C. Hu, S.T. Tarn, F. Hsu, P. Ko, T. Chan and K.W. Terril, IEEE Trans. Electron Dev. ED-32, 375 (1985). P. Heremans, R. Bellens, G. Groeseneken and H.E. Maes, IEEE Trans. Electron Dev. 35, 2194 (1988). A. Schwerin, W. Hansch and W. Werner, IEEE Trans. Electron Dev. ED-34, 2493 (1987). B.S. Doyle, M. Bourcerie, C. Bergonzoni, R. Benechi, A. Bravaix, K.R. Mistry and A. Boudou, IEEE Trans. Electron Dev. 37, 1869 (1990). E. Takeda and N. Suzuki, IEEE Electron dev. Lett. EDL-4, 111 (1983). W. Weber and F. Lau, IEEE Electron Dev. Lett. EDL-8, 208 (1987). Q. Wang, W.H. Krautschneider, M. Brox and W. Weber, Microelec. Engineering 15,441 (1991). D. Vuillaume, J.C. Marchetaux, P.E. Lippens, A. Bravaix and A. Boudou, IEEE Trans. Electron Dev., 40, 773 (1993). M. Bourcerie, J.C. Marchetaux, A. Boudou and D. Vuillaume, Appl. Phys. Lett. 55, 2193 (1989). S.K. Lai, Appl. Phys. Lett. 39, 58 (1981), J. Appl. Phys. 54, 2540 (1983). G. Groeseneken, H.E Maes, N. Beltran and R.F. DeKeersmaecker, IEEE Trans. Electron Dev. ED-31,42 (1984). T. Tsuchiya, T. Kobayashi and S. Nakajima, IEEE Trans. Electron Dev. ED-34, 386 (1987). D. Vuillaume, J.C. Marchetaux and A. Boudou, IEEE Electron Dev. Lett. EDL-12, 60 (1991). B. Doyle, M. Bourcerie, J-C. Marchetaux and A. Boudou, IEEE Trans. Electron Dev. ED-37, 744 (1990). R. Annunzianta, G. Dalla Libera, E. Ghio and A. Maggia, Proc. ESSDERC'87, ed. A. Heuberger, H. Ryssel andP. Lange (Springer Verlag, Berlin, 1987), p. 715. G. Reimbold, F. Paviet-Salomon, H. Haddara, G. Guegan and S. Cristoloveanu, Proc. ESSDERC'88, ed. J.P. Nougier and D. Gasquet (Les editions de Physique, Paris, 1988), p. 665. A. Acovic, M. Dutoit and M. Ilegems, IEEE Trans. Electron Dev. ED-37,1467 (1990). D. Vuillaume and B.S. Doyle, Solid-State Electronics 35, 1099 (1992). B.S. Doyle, J. Faricelli, K.R. Mistry and D. Vuillaume, IEEE Electron Dev. Lett. 14, 63 (1993). J.C. Marchetaux, M. Bourcerie, A. Boudou and D. Vuillaume, Electron Dev. Lett. 11,406 (1990). K.K. Ng and G.W. Taylor, IEEE Trans. Electron Dev. ED-30, 871 (1983). J.J. Tsou, C.C. Yao, R. Cheung and H.W. Chan, IEEE Electron Dev. Lett. EDL-7, 5 (1986). W. Weber and F. Lau, IEEE Electron Dev. Lett. EDL-8, 208 (1987). Y. Hiruta, K. Maeguchi and K. Kanzaki; lEDM Tech. Dig., 718 (1986). T. Mizuno, J. Kumagai, Y. Matsumoto, S. Sawada and S. Shinozaki, lEDM Tech. Dig., 116 (1986). Y. Tang, D.M. Kim, Y. Lee and B. Sabi, IEEE Electron Dev. Lett. EDL-11, 203 (1990). B.S. Doyle and K.R. Mistry, IEEE Trans. Electron Dev. ED-37, 1301 (1990). G. Reimbold, P. Saint-Bonnet and J. Gautier, lEEE/IRPS, 270 (1990). B.S. Doyle and K.R. Mistry, IEEE Electron Dev. Lett. EDL-11, 547 (1990). F. Matsuoka, H. Iwai, H. Hayashida, K. Hama, Y. Toyoshima and K. Maeguchi, IEEE Trans. Electron Dev. ED-37, 1487 (1990). T. Ong, P. Ko and C. Hu, IEEE Trans. Electron Dev. ED-37,1658 (1990). T. Tsuchiya, Y. Okazaki, M. Miyake and T. Kobayashi, IEEE Trans. Electron Dev. ED-39,404 (1992). Q. Wang, M. Brox, W.H. Krautschneider and W. Weber, IEEE Election Dev. Lett. 12, 218 (1991). A. Bravaix and D. Vuillaume, Microelectronic Engineering 19,469 (1992). R. Bellens, G. Groeseneken, P. Heremans and H.E. Maes, Microelectronic Engineering 19,465 (1992). T. Ong, P. Ko and C. Hu, Electron Dev. Lett. EDL-8, 413 (1987). A. Bravaix; PhD thesis. University of Paris VII (1990). L.C. Parillo, S.J. Hillenius, R.L. Field, E.L. Hu, W. Fichtner and M. Chen, lEDM Tech. Dig., 418 (1984). W. Weber, M. Brox, G. Groeseneken, A. v Schwerin and H.E. Maes, in "Hot carrier design considerations for MOS devices and circuits", ed. C.T. Wang (Van Nostrand Reihild, New York, 1992), pp. 250-310. W. Weber, C. Werner and G. Dorda, IEEE Electron Dev. Lett. EDL-5, 518 (1984). K. Chen, S. Sailer and R. Shdih, IEEE Trans. Electron Dev. ED.33, 424 (1986).

Hot Carrier Injections in Silica 83] 84] 85] 86] 87] 88] 89] 90] 91] 92] 93] 94] 95] 96] 97]

337

J.Y. Choi, P.K. Ko and C. Hu, IEEE Electron Dev. Lett. EDL-8, 333 (1987). W. Weber, IEEE Trans. Electron Dev. 35, 1476 (1988). R. Bellens, P. Heremans, G. Groeseneken and H.E. Maes, lEDM Tech. Dig., Ill (1988). K.R. Mistry and B. Doyle, IEEE Electron Dev. Lett. 11, 267 (1990). R. Subrahmaniam, J.Y. Chen and A.H. Johnston, IEEE Electron Dev. Lett. 11, 21 (1990). N. Revil, S. Cristoloveanu and P. Mortini, Microelectronics Engineering 19,461 (1992). R. Bellens, P. Heremans, G. Groseneken, H.E. Maes and W. Weber, IEEE Trans. Electron Dev. 37, 310 (1990). J.Y. Choi, P.K.KO and C. Hu, in "Proc. VLSI Symp.", 45 (1987). B.S. Doyle and G.J. Dunn, IEEE Electron Dev. Lett. 12, 63 (1991). M. Brox and W. Weber, IEEE Trans. Electron Dev. 38, 1852 (1991). W. Hansch and W. Weber, IEEE Electron Dev. Lett. 10, 252 (1989). W. Weber and M. Brox, Microelectronics Engineering 19,453 (1992). R.C. Hughes, Phys. Rev. B 15, 2012 (1977). K. Mistry and B. Doyle, IEEE Electron Dev. Lett. 12,492 (1991). W. Weber, M. Brox, T. Kunemund, M. Muhlhoff and D. Schmitt-Landsiedel, IEEE Trans. Electron Dev. 38,1859 (1991). 98] J. Winnerl, A. Lill, D. Schmitt-Landsiedel, M. Orlowski and F. Neppl, lEDM Tech. Dig., 204 (1988). 99] E.H. Poindexter and P.J. Caplan, Prog. Surf. Sci. 14, 201 (1983); E.H. Poindexter, P.J. Caplan and G.J. Gerardi, in "Physics and Chemistry of Si02 and its interface", ed. C.R. Helms and B.E. Deal (Plenum Press, New York, 1988), p. 299; N.M. Johnson, ibid, p. 319. 100] G.J. Gerardi, E.H. Poindexter, P.J. Caplan and N.M. Johnson, Appl. Phys. Lett. 49, 348 (1986). 101] J.H. Stathis and L. Dori, Appl. Phys. Lett. 58,1641 (1991). 102] D. Vuillaume, D. Goguenheim and J.C. Bourgoin, Appl. Phys. Lett. 58,490 (1991). 103] D. Vuillaume, Proc. INFOS'93, Microelectronic Engineering 22, 201 (1993). 104] H. Miki, M. Noguchi, K. Yokogawa, B. Kim, K. Asada and T. Sugano, IEEE Trans. Electron Dev. 35, 2245 (1988). 105] L.P. Trombetta, G.J. Gerardi, D.J. DiMaria and E. Tiemey, J. Appl. Phys. 64, 2434 (1988). 106] W.L. Warren and P.M. Lenahan, Appl. Phys. Lett. 49, 1296 (1986). 107] R.L. Vranch, B. Henderson and M. Pepper, Appl. Phys. Lett. 52, 1161 (1988). 108] J.T. Krick, P.M Lenahan and G.J. Dunn, Appl. Phys. Lett. 59, 3437 (1991). 109] J. Stathis, D.J. DiMaria, Appl. Phys. Lett. 61, 2887 (1992). 110] D. Vuillaume, D. Deresmes and D. Sti6venard,. Appl. Phys. Lett. 64,1690 (1994). I l l ] J.C. Bourgoin and M. Lannoo, "Point defects in semiconductors" (Springer Verlag, Berlin, 1981), Vol. 2, p. 52 112] D.J. DiMaria, D. Arnold and E. Cartier, Appl. Phys. Lett. 60, 2118 (1992); Appl. Phys. Lett. 61, 2329 (1992); J. Appl. Phys. 73, 3367 (1993). 113] A. Mir and D. Vuillaume, Appl. Phys. Lett., 62(10), 1125 (1993); Microelectronics Journal 24, 361 (1993). 114] S.T Chang and S.A. Lyon, Appl. Phys. Lett. 48,136 (1986). 115] D.M. Fleetwood, P.S. Winokur, R.A. Reber, T.L. Meisenheimer, J.R. Schwank, M.R. Shaneyfelt and L.C. Riewe, J. Appl. Phys. 73, 5058 (1993). 116.a] D. Vuillaume, J.C. Bourgoin and M. Lannoo, Phys. Rev. B 34,1171 (1986). 116.b] H. Lakhdari, D. Vuillaume and J.C. Bourgoin, Phys. Rev. B 38, 13124 (1988). 117] R.E. Paulsen, R.R. Siergiej, M.L. French and M.H. White, IEEE Electron Dev. Lett. 13, 627 (1992). 118] D. Vuillaume, A. Mir, R. Bouchakour, M. Jourdain, A. El-Hdiy, and G. Salace, J. Appl. Phys. 73, 277 (1993). 119] D.R. Young, A.E. Irene, D.J. DiMaria, R.F. DeKeersmaecker and H.Z. Massoud, J. Appl. Phys. 50, 6366 (1979). 120] R. Gale, F.J. Feigl, C.W. Magee and D.R. Young, J. Appl. Phys. 54, 6938 (1983). 121] D.J. DiMaria and J.W. Stasiak, J. Appl. Phys. 65, 2342 (1989). 122] D. Vuillaume, Appl. Phys. Lett. 59, 3118 (1991). 123] E. Cartier, D.A. Buchanan and G.J. Dunn, Appl. Phys. Lett. 64, 901 (1994). 124] D.L. Griscom, J. Appl. Phys. 58,2524 (1985); M.L. Reed and J.D. Plummer, J. Appl. Phys. 63, 5776 (1988).

338 [125] [126] [127] [128] [129] [130] [131] [132] [133] [134] [135] [136] [137] [138] [139] [140] [141] [142] [143] [144] [145] [146] [147] [148] [149] [150] [151] [152] [153] [154] [155] [156] [157] [158] [159] [160] [161] [162] [163] [164]

D. Vuillaume G.J. Gerardi, E.H. Poindexter, P.J. Caplan, M. Harmatz and W.R. Buchwald, J. Electrochem. Soc. 136, 2609 (1989). P. Solomon, 7. Vac, Set Technol 14,1122 (1977). M.V. Fischetti, D.J. DiMaria, S.D. Brorson, T.N. Theis and J.R. Kirtley, Phys. Rev, B 31, 8124 (1985). D. Arnold, E. Cartier and D.J. DiMaria, Phys. Rev. B 45, 1477 (1992). S.J. Wang, J.M. Sung and S.A. Lyon, Appl. Phys. Lett. 52, 1431 (1988). G.J. Gerardi, E.H. Poindexter, M. Harmatz, W.L. Warren, E.H. Nicollian and A.H. Edwards, J. Electrochem. Soc. 138, 3765 (1991). C.T. Sah, Solid State Electron. 33, 147 (1990). D. Vuillaume, D. Goguenheim and G, Vincent, Appl. Phys. Lett. 57,1206 (1990). D. Vuillaume and A. Bravaix, J. Appl. Phys. 73, 2559 (1993). T. Hori and H. Iwasahi, IEEE Electron Dev. Lett. EDL-10, 64 (1989). T.P. Ma, J. Vac. Sci. Technol. A 10,705 (1992) and references therein. H. Fukuda, T. Iwabuchi and S. Ohno, Jap. J. Appl Phys. 27, L2164 (1988). J. Hwu and J. Chen, IEEE Electron Dev. Lett. 11, 82 (1990). J. Mitsuhashi, S. Nakao, T. Matsukawa, lEDM Tech. Dig., 386 (1986). S. Yoshida, K. Okuyama, F. Kanai, Y. Kawate, M. Motoyoshi and H. Katto, lEDM Tech. Dig., 22 (1988). J.J. Sanchez, K.K. Hsueh and T.A. DeMassa, IEEE Trans. Electron Dev. 36, 1125 (1989). M. Orlowski and C. Werner, IEEE Trans. Electron Dev. 36, 382 (1989). T. Hori, J. Hirase, Y. Odake and T. Yasui, IEEE Trans. Electron Dev. 39, 2312 (1992). T.Y. Chan, A.T. Wu, P.K. Ko and C. Hu, IEEE Electron Dev. Lett. EDL-8, 326 (1987). I. Chen, C.C. Wei and C.W. Teng, IEEE Electron Dev. Lett. 11, 78 (1990). A.F. Tasch, H. Shin, T.J. Bordelon and C. M. Maziar, IEEE Electron Dev. Lett. 11, 517 (1990). T.Y. Huang, W.W. Yao, R.A. Martin, A.G. Lewis, M. Koyanagi and J.Y. Chen, IEEE Electron Dev. Lett. EDL-8, 151 (1987). R. Izawa, T. Kure and E. Takeda, IEEE Trans. Electron Dev. 35, 2088 (1988). J.E. Moon, T. Garfinkel, J. Chung, M. Wong, P.K. Ko and C. Hu, IEEE Electron Dev. Lett. 11, 221 (1990). L.C. Parrillo, J.R. Pfiester, M.P. Woo, B. Roman, W. Ray, J. Ko and G. Gunderson, IEEE Electron Dev. Lett. 12, 542 (1991). K. Hieda, K. Sunouchi, H. Takato, A. Nitayama, F. Horiguchi and F. Matsuoka, IEEE Trans. Electron Dev. 39, 671 (1992). G.G. Shahidi, D.A. Antoniadis and H.I. Smith, IEEE Electron Dev. Lett. EDL-9, 94 (1988). G.A. Sai-Halasz, M.R. Wordeman, D.P. Kern, S. Rishton and E. Ganin, IEEE Electron Dev. Lett. EDL-9,464 (1988). G.G. Shahidi, D.A. Antoniadis and H.I. Smith, IEEE Electron Dev. Lett. EDL-9,497 (1988). J.P. Mieville, J. Barrier, Z. Shi, M. Dutoit, Y. Oppliger, J.M. Moret and A. Perret, Microelectronics Engin. 13, 189 (1991). J.E. Chung, M. Jeng, J.E. Moon, P. Ko and C. Hu, IEEE Trans. Electron Dev. 37, 1651 (1990). K.R. Farmer, M.O. Andersson and O. Engstrom, Appl. Phys. Lett. 58, 2666 (1991). A. El-Hdiy, G. Salace, C. Petit, M. Jourdain and D. Vuillaume, /. Appl. Phys. 74, 1124 (1993). K. Brennan and K. Hess, IEEE Electron Dev. Lett. EDL-7, 86 (1986). E. Sangiorgi, B. Ricco and P. Olivo, IEEE Electron Dev. Lett. EDL-6, 513 (1985). R. Shirota and T. Yamaguchi, lEDM Tech. Dig., 123 (1991). J.-P. Mieville, T. Ouisse, S. Cristoloveanu, L. Forro; N. Revil and M. Dutoit, / Appl. Phys. 75,4226 (1994). N. Revil, J.-P. Mieville, S. Cristoloveanu, M. Dutoit and P. Mortini, Microelectronics Engineering 22, 293 (1993). K.K. Likharev, IBM J. Res. Dev. 32,144 (1987). T.A. Fulton and G.J. Dolan, Phys. Rev. Lett. 59, 109 (1987).

Hot Carrier Injections in Silica

339

[165] P.J.M. Van Bentum, H. Van Kempen, L.E.C. Van de Leemput and P.A.A. Teunissen, Phys. Rev. Lett. 60, 369 (1988). [166] H. Pothier, P. Lafarge, C. Urbina, D. Esteve and M. Devoret, Europhys. Lett. 17, 249 (1992); M. Devoret, D. Esteve and C. Urbina, Nature 360, 547 (1992). [167] M.J. Kirton and M.J. Uren, Adv. Physics 38, 367 (1989). [168] K.S. Ralls et al., Phys. Rev. Lett. 52, 228 (1984). [169] M.J. Uren, D.J. Day and M.J. Kirton, Appl. Phys. Lett. 47, 1195 (1985). [170] K.K. Hung, P.K. Ko, C. Hu and Y.C. Cheng, IEEE Elec. Dev. Lett. 11, 90 (1990). [171] O. Roux, G. Ghibaudo and J. Brini, Solid-State Electron. 35, 1273 (1992). [172] E. Simoen, B. Dierickx, C.L. Claeys and G.J. Declerck, IEEE Trans. Electron. Dev. 39,422 (1992). [173] M.J. Kirton and M.J. Uren, Appl. Phys. Lett. 48,1270 (1986). [174] D.H. Cobden, M.J. Uren and M.J. Kirton, Appl. Phys. Lett. 56, 1245 (1990). [175] M. Shulz, J. Appl. Phys. 74, 2649 (1993). [176] M.J. Uren, M.J. Kirton and S. Collins, Phys. Rev. B 37, 8346 (1988). [177] Z.M. Shi; J.-P. Mi6ville and M. Dutoit, IEEE Trans. Electron. Dev., in press (1994). [178] D. Vuillaume, Z.M. Shi, J.-P. Mieville and M. Dutoit, 24th Semiconductor Interface Specialists Conference (SISC 1993), unpublished results. [179] P. Fang, K.K. Hung, P.K. Ko and C. Hu, IEEE Electron. Dev. Lett. 12, 273 (1991). [180] J.C. Marchetaux, private communication. [181] J.E. Wertz and J.R. Bolton, " Electron Spin Resonance. Elementary theory and practical applications " (Chapman and Hall, New York, 1986). [182] D.J. Lepine, Phys. Rev. B 6,436 (1972). [183] I. Solomon, Solid State Comm. 20, 215 (1976). [184] G. Mendz and D. Haneman, J. Phys. C: Solid St. Phys. 13, 6737 (1980). [185] I. Solomon, D. Biegelsen and J.C. Knights, Solid State Comm. 22, 505 (1977). [186] F.C. Rong, E.H. Poindexter, M. Harmatz, W.R. Buchwald and G.J. Gerardi, Solid State Comm. 76,1083 (1990). [187] F.C. Rong, W.R. Buchwald, E.H. Poindexter, W.L. Warren and D.J. Keeble, Solid State Electron. 34, 835 (1991). [188] F.C. Rong; G.J. Gerardi, W.R. Buchwald, E.H. Poindexter, M.T. Umlor, D.J. Keeble and W.L. Warren, Appl. Phys. Lett. 60, 610 (1992). [189] P. Christmann, C. Wetzel, B.K. Meyer, A. Asenov and A. Endros, Appl. Phys. Lett 60, 1857 (1992). [190] B. Stich, S. Greulich-Weber, J.M. Speath and H. Overhof, Semicond Sci. Technol. 8, 1385 (1993). [191] D. Kaplan and M. Pepper, Solid State Comm. 34, 803 (1980). [192] B. Henderson, Appl. Phys. Lett. 44, 228 (1984). [193] M.A. Jupina and P.M. Lenahan, IEEE Trans. Nucl. Sci. 36, 1800 (1989). [194] M.A. Jupina and P.M. Lenahan, IEEE Trans. Nucl. Sci. 37, 1650 (1990). [195] J.H. Stathis, Microelectron. Engineering 22, 191 (1993). [196] B. Henderson, M. Pepper and R.L. Vranch, Semicond. Sci. Technol. 4, 1045 (1989). [197] J.W. Gabrys, P.M. Lenahan and W. Weber, Microelectron. Engineering 22, 273 (1993). [198] M. Lannoo, D. Vuillaume, D. Deresmes, D. Stievenard, Microelectronic Engineering 22, 143 (1993). [199] M. Lannoo, D. Stievenard, D. Deresmes, D. Vuillaume, Proc. ICDS 17, ed. H. Heinrich and W. Jantsch, (Trans Tech Publications, Aedermannsdorf, 1994), Materials Science Forum, Vols. 143-147, p. 1359. [200] G. Barbottin and A. Vapaille, "Instabilities in Silicon Devices", Chap. 9 of Vol. 1, (North Holland, 1986). [201] G. Barbottin and A. Vapaille, "Instabilities in Silicon Devices", Chap. 15 of Vol. 2, (North Holland, 1989). [202] G. Barbottin and A. Vapaille, "Instabilities in Silicon Devices", Chap. 10 of Vol. 2, (North Holland, 1989). [203] D. Vuillaume, A. Bravaix, D. Goguenheim, Microelectron. Reliab, 38, 7 (1998).

This Page Intentionally Left Blank

INSTABILITIES IN SILICON DEVICES Silicon Passivation and Related Instabilities G. Barbottin and A. Vapaille (Editors) © 1999 Elsevier Science B.V. All rights reserved.

341

CHAPTER 5

MULTILAYER DIELECTRICS FOR MEMORY APPLICATIONS by P. GENTIL(i)

Key items Two-layer dielectrics MNOS non-volatile memory Charge storage models Voltage switching models Charge retention models Silicon Dangling Bond trap Nitrogen Dangling Bond trap Three-layer dielectrics MONOS and SONOS memories ONO dielectric for DRAM capacitor

(1) Laboratoire PCS UMRCNRS5531 ENSERGINPG 23 Avenue des Martyrs 38016 Grenoble Cedex 1 France

342

P. Gentil

Abstract of Chapter 5: Multilayer dielectrics for memory applications This chapter presents the applications of two-layer and three-layer thin films to memory devices. The behavior of silicon dioxide and silicon nitride films as well as the behavior of the oxide/nitride interface are specifically analyzed. We first recall some generalities on how an MNOS structure, used as a non-volatile memory cell, works, i.e. how data can be written, read and erased. We then recall the basic phenomena which underlie this "memory" behavior. We also recall the basic equations which link the charge distribution, the potential distribution and the currents in such a structure. We then briefly present several models used to explain and quantify how the charge is injected in the nitride and how this leads to a variation in threshold voltage of any transistor possessing an MNOS structure instead of a regular gate structure. Various new results on the origin and the characteristics of nitride traps are then presented. Silicon nitride is shown to contain amphoteric traps possessing three states of charge, whose origin is mainly attributed to Silicon Dangling Bonds, not linked to a Nitrogen atom. These traps are shown to be widely distributed throughout the nitride and possess numerous energy levels. Recent models describing the switching and/or the retention behavior of MNOS structures are mentioned next In all these models one considers that the traps are distributed uniformly in the nitride bulk, although in some of them, an additional trap density is introduced at the nitride/oxide interface. MNOS memory devices are now proposed as commercial products. However, the fact that the stored charge is spread throughout the nitride, limits the possibilities of scaling down these devices. This limitation can be circumvented by introducing a third insulating layer, made of silicon oxide, between the nitride and the gate electrode. These new devices are called MONOS or SONOS, depending on the electrode material (metal or polysilicon). Their behavior can be modeled and the models take into account the presence of amphoteric traps. The ONO (Oxide/Nitride/Oxide) structure is also studied for its applications as a storage capacitor for dynamic random access memory and as an inter-gate insulator for floating gate memories. The physics and the modeling of the ONO insulator are presented. Resume du chapitre 5: Les dielectriques multi-couches pour application aux memoires Ce chapitre presente les applications des double et triple couches isolantes aux composants a effet memoire. Le comportement des films d'oxyde de silicium et de nitrure de silicium ainsi que celui de leur interface sont plus particulierement analyses. Les principes d'utilisation de structures MNOS comme memoires non volatiles sont rappeles pour les differentes phases d'ecriture, de lecture et d'effacement de Vinformation. Les phenomenes de base ainsi que les equations s 'y rapportant sont rappeles afin de presenter brievement les nombreux modeles qui decrivent la variation de charge dans les isolants et la variation de tension de seuil des transistors utilisant la structure MNOS a la place d'une structure MOS classique. Les recents et nombreux travaux sur I'origine et la nature des pieges dans le nitrure de silicium sont ensuite analyses afin d'introduire de nouvelles hypotheses dans la modelisation des structures memoire de type MNOS. Le nitrure contient des pieges amphoteres, a trois etats de charge dont I 'origine serait une liaison pendante du silicium, non liee a un atome d'azote. Ces etats sont largement distribues dans le volume dufilm de nitrure. Tous les travaux recents sur la modelisation des memoires MNOS incluent une distribution volumique de pieges memoires avec, dans certains cas, une distribution excedentaire liee a I 'interface oxydenitrure. Les memoires non volatiles MNOS sont aujourd'hui des produits commerciaux. Toutefois, la reduction de I'epaisseur du nitrure est soumise a des limites en raison de I'etendue de la charge (memoire) piegee dans le volume du nitrure. Une solution proposee est I'introduction d'une troisieme couche isolante, constitute d'oxyde de silicium, entre le nitrure et la grille. Ces nouvelles structures, appelees MONOS ou SONOS selon que le materiau de grille est en metal ou en silicium polycristallin, sont presentees et comparees aux structures MNOS. Leur modelisation inclut des pieges amphoteres distribues dans le volume du nitrure.

Multilayer Dielectrics for Memory Applications

343

La meme combinaison d'isolants : Oxyde-Nitrure-Oxyde (ONO), est egalement etudiee comme dielectrique de la capacite de stockage des memoires dynamiques DRAM et comme dielectrique intergrille des memoires a grille flottante. Les avantages des structures ONO et le principe de leur modelisation sent presentes en relation avec les sections precedentes sur les memoires MNOS et MONOS. Zusammenfassung zu Kapitel 5: Dielektrische Vielfachschichtenfiir Speicher-Anwendungen, Dieses Kapitel beschreibt die Anwendung von Zwei- und Dreifach-Schichten fur Speicheran- wendungen. Besonders wird das Verhalen von Silizium-Oxid- und Silizium-Nitrid-Schichten und das Verhalten der Oxid/Nitrid-Phasengrenze untersucht. Zundchst wird an einige allgemeine Zusammenhdnge erinnert, wie eine MNOS-Struktur als Permanentspeicher-Zelle arbeitet, z.B. wie Daten geschrieben, gelesen und geloscht werden konnen. Dann erinnern wir uns an die grundsdtzlichen Prozesse, die diesem, "Speicher" - Verhalten zugrunde liegen. Ebenso erinnern wir uns an die Grundgleichungen, die den Zusammenhang zwischen Ladungsverteilung, Potentialverteilung und Stromen in dieser Struktur liefern. Dann werden einige Modelle beschieben, die erkldren und berechnen, wie die Ladung in das Nitrid injiziert wird und wie dies zur Verschiebung der Schwellenspannung eines Transistors fuhrt, der anstelle eines Ublichen Gates eine MNOS-Structur besitzt. Zahlreiche neue Ergebnisse fiber den Ursprung und das Verhalten der Traps im Silizium-Nitrid werden vorgestellt. Wie gezeigt wird, sind die im Silizium-Nitrid enthaltenen Traps amphotdrer natur mit drei Ladungszustdnden, deren Ursprung Hauptsdchlich auf nichtabgesdttigen Silizium-Bindungen beruht und nicht auf solchen mit Stickstoff Diese Traps sind, wie gezeigt, in Silizium-Nitrid verteilt und besitzen eine Vielzahl energetischer Niveaus. Anschliessend werden neuere Modelle, die das Schaltverhalten und die Bestdndigkeit des Speicherverhaltens beschreiben, vorgestellt. Allen diesen Mode lien gemeinsam ist die Annahme einer gleichformigen Vereilung dieser Traps, jedoch wird in einigen auch eine zusdtzlich Trapdichte an der Nitrid/Oxid-Phasengrenze eingefurht. MNOS-Speicher werden heute als kommerzielle Produkte vorgeschalgen. Die Tatsache jedoch, dap die gespeicherte Ladung im gesamten Nitrid verteilt ist, begrenzt die Skalierbarkeit dieser Bauelemente. Diese Begrenzung kann durch die EinfUhrung einer dritten isolierenden Schicht aus Silizium zwischen der Nitrids chicht und Gate-Elektrode umgangen werden. Diese neuen Bauelemente werden MONOS oder SONOS genannt, abhdngig vom Elektrodenmaterial (metall oder poly-Silizium). Ihr verhalten kann siumliert werden und die hierfur verwendeten Modelle gehen von der Anwesenheit amphotdrer Traps aus. Die ONO-(Oxid/Nitrid/Oxid-) Struktur wird ebenfalls fiXr die Anwendung als Speicherkondensator fiXr dynamische Speicher und als Zwischen-Gate-Isolator fur Floating-Gate-Speicher untersucht. Die Physik und die Simulation des ONO-Isolators werden vorgestellt.

344

P, Gentil

Chapter 5: Multilayer dielectrics for memory applications Table of contents List of symbols and abbreviations used 1. Introduction 2. Generalities on MNOS memory devices 2.1. The discovery of the MNOS memory effect 2.2. How a two-layer dielectric memory cell works 2.2.1. Writing of the memory cell 2.2.2. Data reading 2.2.3.Data erasure 2.3. Deviations from the ideal working of an MNOS device 2.4. The desirable characteristics of a practical MNOS memory device 3. The basic equations of an MNOS memory cell 3.1. The band diagram of the MNOS structure 3.2. Relationships linking charges and voltages 3.3. Relationships linking currents and charges 3.4. Expression of the various currents during the "write" and "erase" operations 3.4.1. Basic assumptions 3.4.2.The band-to-band currents 3.4.3.The band-to-traps currents 3.4.4.Carrier motion in the nitride 4. A brief review of the early models describing how MNOS cells operate 4.1. Models describing threshold voltage switching 4.1.1. Analytical models which assume that the memory traps are located at or near the oxide-nitride interface 4.1.2. Models which do not assume direct transitions towards memory traps 4.1.3. Analytical models which assume that the memory traps are widely distributed in the bulk of the nitride 4.1.4. Model proposed by Arnett 4.2. Models describing the retention of the stored charge 4.3. Conclusion 5. The nature and properties of silicon nitride traps 5.1. The structure and composition of silicon nitride 5.1.1. Stoichiometry and dangling bonds 5.1.2. The presence of hydrogen 5.1.3. The presence of oxygen 5.2. The origin of the nitride memory traps 5.2.1. The various possible defects 5.2.2. The important role of silicon dangling bonds 5.3. Some properties of the nitride traps 5.3.1. Some usual hypotheses 5.3.2. Volume distribution

Multilayer Dielectrics for Memory Applications 5.3.3. State of charge 5.3.4.Energy levels 5.4. The study of nitride traps using thick oxide MNOS devices 5.4.1. Why use thick oxide MNOS structures? 5.4.2. The results of Park et al 5.4.3. The results of Martin et al 5.5. Evidence of hole trapping in the nitride of a thin oxide MNOS device 5.6. Conclusions 6. Shortcomings and limitations of MNOS structures 6.1. The role of hole injection during MNOS switching 6.1.1. The carrier injection mechanisms caused by negative biases 6.1.2. The usefulness of MONOS structures 6.1.3. Charge separation measurements 6.2. Limitations to the scaling down of memory devices due to the space charge distribution 6.2.1. Limitations due to charge storage possibilities 6.2.2. Limitations due to charge retention and endurance possibilities. 7. Theory and modeling of the MONOS structure used as a non-volatile semiconductor memory 7.1. Two reasons to introduce an additional oxide layer 7.2. Some properties of the blocking oxide 7.3. Relationships linking charges and potentials 7.4. Relationships linking currents and charges 7.5. Charge trapping by amphoteric traps in silicon nitride 7.6. Modeling of the memory behavior of MONOS and SONOS devices 7.6.1. The main assumptions of White's models 7.6.2. A simplified model of the switching behavior considering amphoteric traps 7.6.3. A more complete model of the switching of MONOS/SONOS memories 7.7. Modeling of the retention behavior of MONOS/SONOS devices 7.7.1. Discharge of the nitride by back tunneling of trapped carriers 7.7.2. A more complete model of the nitride discharge 7.8. Conclusions 8. Using the ONO structure as a DRAM capacitor 8.1. Two other possible applications of the ONO structure 8.2. The main advantages of the ONO structure 8.3. The modeling of the ONO structure 8.4. Perspectives of the ONO structure 9. Conclusions and perspectives Acknowledgements List of references

345

346

P. Gentil

LIST OF SYMBOLS AND ABBREVLVTIONS USED Ce

F.cm-2

CN

F.cm-2

c cn,p

cm-3s-l

D E

C.cm-2 eV eV

E c (Si,N)

Ep EpM

F.cm-2

eV eV

EtA' EtD

s-1 eV eV

Ev(Si,N)

eV

^N

V.cm-1

^

V.cm-1

Sox

V.cm-l

^s

V.cm-1

®n,p

Et

f+,fo,ffs ft

-

n ID

J.s A

^n'^p

A

J JN

A.cm-2 A.cm-2

•'ox

A.cm-2

k n,nt

eV.K-l Kg cm-3

Nc

cm-^

Nt p*

cm-^

m*N,ox

-

s-l

Capacitance per unit area of the series assembly of the two insulating layers Capacitance per unit area of the nitride layer Trap capture coefficient for electrons and holes respectively Capacitance per unit area of the Si02 layer Electric displacement Energy level Lower edge of the silicon conduction band, of the nitride conduction band respectively Fermi level of the semiconductor Fermi level of the metal Trap emission probability for electrons and holes respectively Trap energy level Energy level of amphoteric traps in an acceptor state and donor state respectively Upper edge of the valence band Electric field in the nitride Characteristic electric field defined by identity (5.12) Electric field in the oxide Electric field at the semiconductor surface Fraction of traps in the D+,D^,D- states respectively Probability that an energy level at the Si/Si02 interface be occupied Probability that a bulk trap in the nitride be occupied by an electron Planck's constant divided by 2 %{% = 1.054 lO-^^j s) Drain current Electron and hole current respectively Current density Current density in the nitride Current density in the oxide Boltzmann's constant (k = 8.619 10-5 eV.K-l) Effective mass of a carrier in the nitride, respectively in the oxide Concentration of free electrons, respectively trapped electrons, in the nitride Effective density of states in the conduction band Trap density per unit volume in the nitride Probability of tunnel crossing, per unit time

Multilayer Dielectrics for Memory Applications

PN.OX

-

347

Probability of tunnel crossing through the nitride layer, respectively through the Si02 layer

AQN

C.cm-2

Variation of Q ^ (due to the capture of injected carriers)

AQON

C.cm-2

Variation of Q Q N (due to the capture of injected carriers)

Q q

C.cm-2

Charge per unit area

C

Electron charge (q = 1.6 10-19 C)

QBOM

C.cm-2

Charge per unit area at the blocking oxide/metal interface

QN

C.cm-2

Charge per unit area in the nitride (i.e. the integral of p ^ over the

QNBO

C.cm-2

nitride thickness) Charge per unit area at the nitride/blocking oxide interface

QNM

C.cm-2

Charge per unit area at the nitride/metal interface

QON

C.cm-2

Charge per unit area at the oxide/nitride interface

Qox

C.cm-2

Charge per unit area in the oxide (i.e. the integral of p^^ over the

C.cm-2

oxide thickness) Charge per unit area in the semiconductor space charge layer

C.cm-2

Charge per unit area at the semiconductor/oxide interface

^N.ox, BO

K s cm

[^

cm

U

^N,ox

eV V V cm.s-1 V V V

Absolute temperature Time Thickness: of the nitride layer, of the tunnel oxide layer and of the blocking oxide respectively _ Distance separating the barycenter (X j^) of the charge trapped in the nitride, from the oxide/nitride interface Correlation energy Flat band voltage variation (e.g. due to a stored charge)

VT VTO,VTI

V V

X

cm

Xjsj XQX

cm cm

Qsc Qso T t

AVpB AVx Vd VFB VG

Threshold voltage variation (e.g. due to a stored charge) Saturation velocity of carriers Flat band voltage Gate voltage Voltage drop across the nitride layer, respectively across the Si02 layer Threshold voltage of an MNOS transistor or of an IGFET Initial threshold voltage, respectively threshold voltage after a writing cycle Space coordinate perpendicular to the interface planes (the origin is the Si-Si02 interface) Coordinate of the nitride/metal interface for MNOS devices Distance between the Si-Si02 interface and the Si02-Si3N4 interface (oxide thickness)

348

Xs ^N,ox

6

P. Gentil

cm cm cm.V-1

^

F.cm F.cm F.cm cm V eV eV

^o

s-1

P PN,OX,BO

C.cm-3 C.cm-3

^t

cm2

Vs

V

% ^N,ox

es

X MS ^i

Characteristic length of the trap distribution in Eq.(5.30) Barycenter of charges in Si3N4, and in Si02 respectively Poole Frenkel coefficient Permittivity of vacuum (£o=8.85 10-14 F.cm-l) Dielectric constant of the nitride, of the oxide resp. E^=1EQ. SQX'^^^O Dielectric constant of silicon. £S=12£Q Characteristic distance defined by Eq.(5.19) Metal/semiconductor work function difference expressed in Volt Energy difference between E^ and E^ Energy barrier Vibration frequency Volume charge density Volume charge density in the nitride, in the tunnel oxide and in the blocking oxide respectively Capture cross section of the traps Surface potential

A£ APCVD CVD D+,Do,DDRAM EEPROM FAMOS FET FLOTOX IC IGFET LPCVD MNOS MNS MONOS MOS N2O NH3

Aluminum Atmospheric pressure CVD Chemical vapor deposition States of charge of an amphoteric trap: positive, neutral, negative Dynamic random access memory Electrically erasable programmable read only memory Floating gate avalanche injection MOS transistor Field effect transistor Floating gate tunnel oxide MOS transistor Integrated circuit Insulated gate FET Low-pressure CVD Metal-nitride-oxide-silicon (structure) Metal-nitride-silicon (structure) Metal-oxide-nitride-oxide-silicon (structure) Metal-oxide-semiconductor (structure) Nitrous oxide Ammonia

ONO PECVD

Oxide-nitride-oxide three-layer dielectric Plasma-enhanced CVD

Multilayer Dielectrics for Memory Applications Si Si3N4

Silicon Silicon nitride

SiH2Cl2 SiH4

Dichlorosilane

Si02 SiO^Ny

Silicon dioxide

SONOS S/0 0/N Subscript N Subscript ox

Poly silicon-oxide-nitride-oxide -silicon structure Silicon/Oxide (interface) Oxide/Nitride (interface) refers to the nitride layer refers to the Si02 layer

WKB =N* =Si*

Wentzel Kramers Brillouin (model of tunnel effect) NDB: Nitrogen dangling bond SDB: Silicon dangling bond

Silane Silicon oxynitride

349

350

P. Gentil

1. INTRODUCTION When Vol. 2 of this series was first pubUshed (1989), an entire chapter (Chap. 16) was devoted to MNOS (Metal-Nitride-Oxide-Silicon) structures and to their application to nonvolatile memories. Since then, this promising new technology has not been as successful as originally anticipated. In fact, only a few manufacturing plants in the whole world succeeded in mastering the industrial production of this two-layer structure with satisfactory yield and reproducibility. Moreover, during the same period, floating gate memories enabled the same memory applications while being easier to produce. Nevertheless, progresses in technology and a better knowledge of nitride traps have recently made it possible to improve both the performances of MNOS devices and their modeling. Furthermore, multilayer dielectric structures appear today to benefit other applications than non-volatile memories. All these considerations make an update of the original 1989 text indeed necessary. We first recall in Section 2 that in the early days of device manufacturing, an additional nitride layer was first introduced to stabilize IGFET's (Insulated Gate Field Effect Transistors). Although these early attempts failed, they led to the discovery that such twolayer structures possess a memory effect. This memory effect can be described by a simple model in which electrons are injected (and subsequently trapped) during the "writing" phase and re-emitted during the "erasing" phase. The presence (or the absence) of electrons trapped at the oxide/nitride (abbr. 0/N) interface constitutes "stored data". However, carrier injection and carrier trapping phenomena are much more complex than what this simple model suggests. This is described in detail in further sections. In Section 3 we recall the basic equations which link the space charge densities, the current densities and the voltages in an MNOS structure. These equations let us derive the expressions of the many currents which exist in the structure and which are due to the exchange of carriers between: the silicon bands, the O/N interface, the nitride bands, and the nitride traps. Since these equations have already been derived in Vol. 2 of this series, only the major results, to be used later on, are recalled in the section. Numerous analytical and numerical models have been proposed in the literature to explain the behavior of MNOS devices during both the writing phase and the charge storage phase. Since many of these models have been described in Chap. 16 of Vol. 2, we review in Section 4 only the most important ones. Models proposed for the "write" phase differ depending on the hypotheses being made. For example, the memory traps may be considered either as being located near the O/N interface, within or beyond tunneling distance from the oxide, or as being distributed in the nitride. Emphasis is given to the latter hypothesis which appears to be the most likely one as proved by numerous experiments performed since the publication of Vol. 2. Likewise, models proposed for the storage (retention) phase depend on the nature of the carriers and on the nature and characteristics of the transport, trapping and emission mechanisms. In Section 5, we review those defects contained in the nitride which can behave as carrier traps and thus explain the memory effect of MNOS structures.

Multilayer Dielectrics for Memory Applications

351

We show that the two likely candidates are the Silicon Dangling Bond (SDB) and the Nitrogen Dangling Bond (NDB), and that among these two defects, the SDB seems to play the major part. Measuring the physical properties of these defects is difficult because it is always performed indirectly. Both from theoretical and experimental approaches, the SDB is shown to be amphoteric with three possible states of charge (-1, 0, +1). SDB defects are fairly uniformly distributed in the nitride bulk and are widely distributed in energy in the nitride band gap. Unfortunately most of the experimental results are obtained on special test structures which differ markedly from real MNOS devices. Results of recent experiments are also presented. We show that for moderate injection fields and for thick oxides, only electrons can be injected from silicon if the gate voltage is positive. However, for negative gate voltages and thin oxides, hole injection from silicon is also shown to be possible. In Section 6 we try to better understand the switching behavior of an MNOS structure, by taking into account hole injection. Electrons and holes both get trapped in the nitride bulk and at the O/N interface which implies either that the existing carrier traps are amphoteric or that both donor-like and acceptor-like traps are present. Because carriers are trapped throughout the nitride layer, the thickness of this layer cannot be reduced below an optimum value. For practical applications this value varies between 10 and 20 nanometers. The introduction of an additional oxide layer between the metal gate and the nitride not only prevents hole injection from the gate, but brings about many other advantages. This is explained in Section 7. The relationships linking charge distributions, electric fields and potentials in MONOS structures, may be derived in a manner similar to that used for MNOS structures. However, the presence of an additional layer and the fact that the traps are amphoteric introduce many new carrier exchange mechanisms. This renders the modeling of the switching and retention behaviours of MONOS structures quite complex. The three-layer ONO (Oxide/Nitride/Oxide) structure, which improves the switching and retention properties of memory cells, can also be used as a storage capacitor in dynamic RAMs. We show in Section 8 that ONO capacitors have many advantages over simple oxide capacitors but that their modeling is more complex. At the present time, several research teams and manufacturers are studying nitride layers and multilayer dielectrics. Nitride layers are of great interest not only for memory applications but also for thin film transistors. Multilayer dielectrics appear to be promising structures to produce devices such as non-volatile memories and DRAMs. They allow to move towards higher densities, faster access times, lower power consumption, and the use of a single low voltage power supply. 2. GENERALITIES ON MNOS MEMORY DEVICES Let us first review, from a phenomenological point of view, how an ideal MNOS memory device works and then examine how a real structure deviates from this ideal mode of operation. A more thorough description can of course be found in Chap. 16 of Vol. 2 of this book series [1].

352

P. Gentil

2.1, T H E DISCOVERY O F THE MNOS MEMORY EFFECT

As already mentioned in [1], the search for ways to improve the stability of IGFET led to the discovery of the MNOS memory effect. Since the 1960's, the silicon-silicon dioxide system has been recognized as the best combination available to produce solid state devices and integrated circuits (IC's) for many applications. This stems from the compromise reached between the electronic properties of such a system and the ability to develop a full technology from an industrial point of view, including aspects such as large volume production, performance, reliability, low cost, etc. Let us note however that some of the electronic properties of these two basic materials are not the best possible ones. For instance, other semiconductors exhibit higher electron mobility than silicon and therefore enable devices to operate at higher frequency. On the other hand, silica possesses a rather low dielectric constant compared to other insulators. For MOSFET devices, this means that a smaller oxide thickness must be used in order to obtain the same current in given conditions. This reduction in oxide thickness has several consequences: • very small insulator thicknesses can in turn lead to local defects which limit fabrication yield and reliability, • for future generations of MOSFETs, scaling down the thickness of the gate oxide will lead to the direct tunneling of carriers between the gate electrode and the semiconductor, • finally, very thin oxides offer an insufficient protection against the diffusion of elements such as boron (the usual P-type dopant of silicon) or contaminating ions. Alternatives to the Si-Si02 system have thus been topics of research for a long time (see for instance [2]). They continue to be investigated [3-8] for deep submicron technologies. The Si-Si02 system appears however to be the best one yet to fabricate stable devices for advanced IC's. In the search for Si02 substitutes, the Si-Si02 interface has appeared as rather unique because of its high energy barrier, due mainly to the wide band gap of silica, and because of its very low density of fast surface states. It was thus quickly proposed to use a multilayer dielectric consisting of a thin Si02 layer, obtained by the thermal oxidation of Si, covered by a second insulator [9]. Silicon nitride (Si3N4) had first been used in the IC industry to protect the semiconductor from the diffusion of impurities [10] and then for the masking of silicon during oxidation [11]. The use of MNOS structures was thus soon attempted [9] for the production of stable IGFETs. Although it failed at that time for this purpose, the instability, resulting from the trapping of carriers into the multilayer dielectric, was recognized as a phenomena potentially usable for memory applications [12-14].

Multilayer Dielectrics for Memory Applications

353

2.2. H o w A TWO-LAYER DIELECTRIC MEMORY CELL WORKS

Let us consider an n-channel IGFET possessing, as a gate dielectric, a thin layer of thermal Si02 (about 10 to 50 A thick) and a second layer of Si3N4 (about 100 to 500 A thick) deposited on top. At low applied voltages (a few volts) this device behaves like a stable IGFET, displaying the ID(VQ) characteristics shown in Fig. 5.1.a, and possessing a threshold voltage V^po- Such a structure can indeed be used as a logic memory cell by using adequate biasing conditions, as we show next. 2.2.1. Writing of the memory cell Let us apply a high-amplitude voltage pulse to the gate electrode, positive with respect to the silicon substrate (for instance a few tens of volts for a fraction of a second). Let us assume that, in such conditions, Si02 conducts significantly due to electronic injection from the silicon while Si3N4 exhibits negligible conduction. Electrons leaving the silicon accumulate then at the O/N interface (see Fig. 5.1.b). If traps of appropriate characteristics exist at this interface, electrons get trapped. *G

0

1

ll|U

Sis N4

Sis N4

loA

A

Si02

lU^

rKF Si P

Si P a)

initial state /

T

b)

'TO final state

c)

flm

VT,
p

fio

Sis N4

Sis N4

TNJ mr r^>of!:fmm± M

-^SiO;

Nl Si P d)

0

VTOVGVT. read

e)

V G « 0

ilm

Si P

f)

nrn

Fig. 5.1. - Illustration of how a two-layer memory cell works: a) Initial Ij^iVo) curve of an MNOS transistor, b) Writing operation. Electrons are injected from Si to the traps of the Si02/Si^N^ interface, c) Storage of the negative charge at the O/N interface after the writing pulse has ended, d) Illustration of the shift in the IJ)(VQ) curve due to charge storage, e) Read operation of the memory cell, f) Erase operation

354

P. Gentil

If V Q is brought back to a low value (e.g. V Q = 0 ) , the trapped electrons remain stored at the interface (see Fig. 5.1c). Compared with the initial state, an additional negative charge, due to the trapped electrons now exists at the 0/N interface. The IGFET exhibits now a new threshold voltage, V'^j, whose value is given by [1]: Vr/=Vr<,-^

(5.1)

where C^ is the nitride capacitance per unit area and AQQN is the increase in interface charge (expressed per unit area). C^ is given by:

2.2.2. Data reading If we assume that under moderate gate voltages, the "leakage" currents in the insulators remain negligible, the IGFET is stable after writing and exhibits a new IE)(VG) curve with the corresponding threshold voltage V^i (see Fig. 5. Id). If the gate is biased between Vjo ct V^i (see Fig. 5.1e) the resulting drain current remains negligible (e.g. less than l|xA), whereas the same gate voltage would have led to a significant drain current in the previous state (i.e. that corresponding to threshold voltage V^o without stored electrons in the insulators). This difference in current reading allows us to check (read) whether "data" (i.e. electrons) have been stored or not. 2.2.3. Data erasure Let us now apply a high-amplitude negative voltage pulse to the gate (see Fig. 5.If), ff the assumptions used for writing apply, the electrons will now go back to the silicon thus enabling the device to retum to its initial state. The stored "data" have been erased. 2.3. DEVIATIONS FROM THE IDEAL WORKING OF AN MNOS DEVICE

In the above discussions, we made several assumptions which are not fully verified in real MNOS devices. • When the high-amplitude gate voltages are applied during the write and erase operations, conduction in the nitride is not always negligible. Furthermore, as the number of trapped electrons varies, the resulting space charge modifies the electric field in the insulators. For instance, during the writing phase, the magnitude of the electric field in the oxide (^Q^) decreases with time while the magnitude of the nitride field (^N) increases. Due to these field variations, currents vary in such a way that the oxide current decreases while the nitride current increases. This phenomena may limit the quantity of stored electrons.

Multilayer Dielectrics for Memory Applications

355

• The simplified phenomenological model also assumes that only one type of carrier is injected into the insulators. In practice, this is not always true. For example, the application of a positive gate bias (VQ > 0) favors the injection of electrons from one electrode (silicon) and the injection of holes from the other electrode (the metal gate). The stored charge is reduced if both types of carriers are injected. Assuming that AQQN is only due to the conduction of one insulator (e.g. Si02) after a write pulse allowing electrons to be stored at the interface, there still exist two possibilities for data erasure. Erasure can be performed either by letting the electrons leave the traps and return to the silicon or equivalently by injecting holes from the silicon and letting them recombine with the trapped electrons. In the latter case, excess holes can also be trapped giving rise to a positive charge and to a negative V^ shift. • Trapping has been supposed to occur only at the 0/N interface. However, it has been known for a long time that traps are also present in the bulk of most insulators. While Si02 has a low trap density, large densities of electron and hole traps exist in the bulk of Si3N4. If the electric charge is stored in the nitride, far from the Si02 interface, its influence on the silicon surface will be less. Equation (5.1) is then no longer valid. For a given stored charge, the deeper into the nitride the charge is, the smaller the threshold voltage variation. • It has also been assumed that under low voltage biases, an IGFET exhibits a stable V^ i.e. that there is no charge motion in the insulators. In fact, the stored charge itself induces an internal electric field that favors a retum to equilibrium by various mechanisms. There is no true threshold below which no current flows in the insulator. The retention of the stored charge may be long but it is not infinite. • Finally a cycle has been described in which a charge has been stored after writing and then nullified after erasure. Even if the same initial V^ value is measured after a full cycle, there is no guarantee that the device is again in its initial state. First, different carrier distributions in the insulators can give the same V j . Secondly, the injection of carriers into the insulators involves high electric field and high energy carriers which may modify the electronic properties of the structure. Thus, cycle after cycle, Si-Si02 interface states as well as nitride traps can be created. In actual devices, a drift of V j and a lower retention are observed after many switchings. This limits the number of write/erase cycles. 2.4. THE DESIRABLE CHARACTERISTICS OF A PRACTICAL MNOS MEMORY DEVICE

It must be stated that although practical MNOS devices are not ideal, and that quite complex phenomena occur in the memory cell, an acceptable compromise can be obtained. This leads to industrial products which have the following satisfactory characteristics: • the insulators can be charged or discharged, during the writing or erasure cycles under relatively low switching voltages (10-20V) and within a short period of time (a few hundred ms), • a difference of a few volts between the two threshold voltages (called the memory window) can be obtained and is easily usable in MOS circuits.

P, Gentil

356

• the electric charge stored in the insulators is sufficiently stable under low electric field. This gives rise to the non-volatile memory property and to the non-destructive reading of the data. Retention of the data for ten years is possible without any significant power consumption, • more than 10^ cycles can be applied before the memory degrades and becomes unusable. 3. THE BASIC EQUATIONS OF AN MNOS MEMORY CELL Let us now consider an MNOS structure and try to establish the basic equations which will allow us to derive expressions for the various currents. Since these calculations have already been performed in Vol. 2 of this series, only the major results will be repeated. 3.1. THE BAND DIAGRAM OF THE MNOS STRUCTURE If we assume that the electric charge is nil everywhere and that the difference in work function between the metal and the semiconductor is also nil, then the band diagram of the structure, without any applied voltage, is that of Fig. 5.2. Since the typical thickness of the Si02 layer is around 20 A, it is not certain whether the oxide layer can be considered as a uniform material with properties comparable to those of much thicker layers. One or more oxide parameters (thickness, barrier heights, dielectric constant) may have to be adjusted when comparing theoretical and experimental results. SiOo

Si

Si3N4

Al

3,1

2,1 UX

5,1

^FM

Fig. 5.2 - Band diagram of an MNOS structure. Energies are given in eV. 3.2. RELATIONSHIPS LINKING CHARGES AND VOLTAGES

Let us now consider an MNOS structure under bias. Voltage VQ is applied to the gate electrode, e.g. positive with respect to the silicon substrate. Generally speaking, a volume distribution p of charges exists within each insulator and a surface density Q of charge exists at each interface as illustrated in Fig. 5.3. The relationships linking charges and voltages or charges and electric fields are obtained from the Poisson's equation:

357

Multilayer Dielectrics for Memory Applications O 1

8N

Pox O

H

M —//—

N

1

QJN

M

' ' ^V

'l V

'

J* J*

'

'

/*>

tN

*^ox

11

—i

0

X

-//

,

^

)— X N

XQJ^

ox

x^

F/g. 5.5 - Cross section of an MNOS capacitor and definition of symbols used

AV-^^=0

or

£

divi-^=0

(5.2)

8

Solving this equation leads to the relationships which have been established in Vol. 2 of this series [1] (see Eqs.(16.19-20) p. 683). The result is the determination of useful expressions such as that of the electric field in the oxide at the Si-Si02 interface ^ox(O) ^^^ that of the electric field in the nitride at the 0/N interface ^ N ( X ) • Fields ^x(O) ^^^ ^N(X ) can easily be obtained from the following equations: yG-'(l>MS-¥s=-Qi

yG-Ms-¥s=-Q,

^ox ~ ^ox

^N

^ox

^N

ox

OX

^ox

\

( Xj^ - X ^ I Qgf^ -QN]^

Xfj-X -QN

•

N

e^v

^ox

^N

QON

^

+

^ox ^xiO)

(5.3)

'N

^N^N(0)

(5.4)

^OX

Likewise, the flat band voltage of the structure, which corresponds to that value of VQ which must be applied to obtain \|/s = 0 , ^g = 0 and Q^^ = 0, can be deduced: ypB = 0M5 - Q.ox

^ox

~ ^ox ^OJC

^N EN

^N -QN

^N

^N

-\

Qso

QoN

(5.5)

^N

In the above equations, Q^ and Q^^ are respectively the total charge (expressed per unit area) in the nitride and in the oxide (i.e. the integrals of p^ and p^^ over the insulator thickness). Distances X ^ and X ^^ are respectively the barycenters of the charge distributions in the nitride and in the oxide. Q^Q is the charge at the silicon/oxide (abbr. S/O) interface and QoN the charge at the O/N interface (Q^Q and QQN are also expressed per unit area). Symbols ^ S ' ^ox' ^N ^^^^ their usual meaning.

358

P. Gentil

^ox' CN» Cg are respectively the capacitances per unit area: of the oxide layer, of the nitride layer and of their series association. C^ is given by Eq.(5.1a) while C^^ and C^ are given by: ^OX

-ox

1

(5.5a)

^OX

-

Ce

1

c

1

+

(5.5b)

^ox

During the operation of an MNOS memory, only QQN ^^d Q N may vary. It follows that Eq.(5.5) can be written in a more useful form as:

^FB =

^'FB

-

^N QN

^N

^N

QON

(5.6)

'A^

where V'pg is a constant. The threshold voltage V-j- and the flat band voltage Vpg of the structure only differ by a constant. Therefore, a variation AQN taking place in the nitride bulk and a variation AQQN taking place at the 0/N interface lead to a shift in threshold voltage given by: AVT = AVpB = - ^QN

r

^QON

(5.7)

'AT

If a charge variation occurs only at the 0/N interface then relation (5.7) simplifies further into (5.1). 3.3. RELATIONSHIPS LINKING CURRENTS AND CHARGES

In the case of a one-dimensional MNOS structure, the conservation of the total current (i.e. the sum of the conduction and displacement currents) is expressed as: div i(gf = div I {x, t) + -J^D [x, t)= 0

(5.8)

By using the Poisson equation linking the electric displacement vector D (with D = e^) to the charge volume density, relation (5.8) applied to the nitride becomes:

Multilayer Dielectrics for Memory Applications

d Jj^ \Xyt)

dpjsj [x, t)

^x

^^

359

(5.9)

where p^ is the charge density (expressed per unit volume) in the nitride and J^ is the current density in the nitride. Finally, by using Gauss law at the O/N interface, we obtain from relation (5.8): / \ Jox [^ox, tj^

/ \ ^QON it) JN \^OX, t) = 'J^

(5-10)

Equations (5.9) and (5.10) express that a spatial variation in carrier current causes a temporal variation in the amount of charge, respectively in the bulk and at an interface. Steady state conditions are said to exist when the value of the current density is preserved throughout the structure. In that case, there is no charge variation, neither in the bulk of the insulator (3p/9t = 0) nor at any interface (dQ/dt = 0). Although similar equations can be written for the bulk of the oxide and for the other interfaces of the structures, in practical MNOS devices the corresponding charge variations in these areas can be neglected. 3.4. EXPRESSION OF THE VARIOUS CURRENTS DURING THE "WRITE" AND "ERASE" OPERATIONS

If VQ is large, the energy band diagram takes the form illustrated in Fig.5.4. To be able to derive the expressions of the various currents some assumptions must be made. 3.4.1. Basic assumptions Because of the high field and of the use of a very thin oxide layer, we can assume that carrier tunneling dominates and determines the current value at the S/O interface. Hot carriers (i.e. electrons with energy above the silicon conduction band edge E(;^(si)) are not produced in the normal operation of an MNOS structure and are thus neglected here. Because of the existence of large densities of traps at the O/N interface and in the nitride and because of the possible contribution of both electrons and holes, several types of current components can be expressed, as illustrated in Fig. 5.4. In Fig.5.4, the energy barrier at the interface seems more favorable to hole tunneling (currents J'^ and J'2) than to electron tunneling (currents J^ and J2). However, the value of each current depends also on the number of holes or electrons available for the tunneling transition. It also depends on the number of free states available on the opposite side of the barrier. In practice, whether the electron current (Jj or J2 or J3) or the hole current (J' i or J'2 or J'3) predominates depends on:

360

P. Gentil

• device parameters: i.e. the oxide and nitride thicknesses, the energy and spatial distribution of the traps, the nature of the traps (donor, acceptor, amphoteric), etc, • biasing conditions: positive or negative gate bias, low field or high field in the insulators, • the history of the device which determines the charge already stored in the insulators. In the same way, for the nitride, the predominance in the bulk of an electron current (J^i or 1^2) or of a hole current {T^i or J'N2) depends on device parameters, gate bias and the history of the device. Furthermore, the temperature influences the predominance of either the thermal excited currents (J^i, J ' N I ) ^^ ^^^ tunneling currents (JN2» J'N2)We only give below the relationships obtained in the case of electrons and positive gate bias. Formulae corresponding to holes and negative gate bias can be obtained by an appropriate change in notation. 1,6 eV

Fig. 5.4 - Band diagram of an MNOS capacitor with the following characteristics : tax = 25 A, t^ = 600 i , V^ = + 25 V, xif, = (t>j^s = 0. Qso = Qox = QON=QN

=0

At the S/O interface, two types of electron current must be distinguished: one corresponding to transitions between the silicon conduction band and the nitride conduction band (current Jj in Fig. 5.4, called below the band-to-band current) and one corresponding to direct transitions between both silicon bands and the nitride traps (currents J2 and J3 in Fig. 5.4, called below the band-to-trap currents). 3A.2. The band-to-band currents Electrons in the silicon conduction band must tunnel through a barrier whose form depends on the magnitude of the applied electric field, as indicated in Fig. 5.5. The general relationships, derived in [1], (p. 693), let us express the oxide current density as a function of the electric field:

Multilayer Dielectrics for Memory Applications Oxide

Oxide

Oxide

361 Nitride

2

X XQX

b)

a)

: ^ . Xy

X

c)

Fig, 5.5 - Illustration of how the conduction band diagram of an MNOS structure varies under the action of an electric field, a) Case of strong fields: q ^QX tox >1 • l^) Case of medium fields: 0/ -2<(l^ox tox <^1 • ^) Case of weak fields: q ^ox tox <^1-2' h

-

JQX

(5.11)

- " Q ^ox ^ox ^N

where constant C^ is independent of b,^^. Parameters P^^ and P^ are the transition probabilities of an electron through the oxide and nitride barrier respectively. Probabilities P^^ and PN can be estimated by the WKB method (Wentzel, Kramers, Brillouin). Depending on the magnitude of the electric fields, several cases may be distinguished. i) strong electric fields. In this case, illustrated in Fig. 5.5a, PN = 1 and the oxide barrier is triangular-shaped. The tunnel current is of the Fowler-Nordheim type. P^^ is given by: 4 Pox = exP

{^mlx) 3qfi^x

3/2

07

= exp

(5.12) hox

where 4o is a negative constant, fi is the reduced Planck's constant, m*ox is the effective mass of the electron in the oxide, and ^i is the S/O barrier height. ii) moderate electric fields. In this case, illustrated in Fig. 5.5b, P N = 1 and the oxide barrier is trapezoidal-shaped. P^^ is given by: \3/2

f Pox = exp

1-

1-

(5.13)

^x

lit) weak electric fields. In this case, illustrated in Fig. 5.5c, P^^ is given by Eq.(5.13) and Pjvj is given by:

362

P. Gentil

/

* \l/2

Pj^ = exp

(5.14)

where m*^ is the effective mass of the electron in the nitride, and ^2 is the O/N barrier height. In the above three equations, we have assumed that the energy bands are linear i.e. that l^^ and ^N ^ ^ constant. This, in turn, supposes that the electric charge is nil in the oxide and in the nitride bulk. 3.4.3. The band-to-traps currents The principle behind the calculation of the band-to-traps currents is the same as that used for the band-to-band currents, but the fact that the number of traps which take part in the tunnel transitions is limited must also be taken into account. Let us call N^ the trap density (expressed per unit volume and energy) in the nitride. The density of the current flowing towards the bulk traps contained in a differential element dx d0t (illustrated in Fig. 5.6) is the sum of the exchanges taking place: between the filled energy states of the silicon and the empty traps, and between the filled traps and the empty states of silicon. This can be written:

dJ = qN, [f^(l-f,)-f^ (1 - / J ] P* dx d(t>,

(5.15a)

where f^ represents the probability that the nitride traps of the differential element be occupied by an electron, f^ is the probability that the levels at the silicon surface be occupied, and P* is the crossing probability. This expression simplifies into: dJ = qN,{f,^f,)p*

dxd(t>,

(5.15b)

The total current density is obtained by integrating Eq.(5.15.b) over space and energy. J=\

\ dJ

where J is either current J2 illustrated in Fig. 5.4 and Fig. 5.6 or J3 (or both), depending on the device parameters and on the biasing conditions. The crossing probability per unit time P* is expressed as: P* = P, P,^ P^

(5.16)

where P^ is a constant, independent of the electric field, and P^^ and P^ represent the probability that an electron tunnel through the trapezoidal-shaped oxide and through the nitride barrier respectively.

Multilayer Dielectrics for Memory Applications

363

q&,,(x-t )

Fig. 5.6 - Illustration of the various components of the band-to-trap current. Carriers tunnel from the semiconductor bands to traps located in the band gap of the nitride.

Probability PQ^ is given by Eq.(5.13) where ^i is replaced by ^i .Quantity ^i is here a function of bias as visible in Fig.5.6. It can be written: 0i* = ^^ox ^ x + ^ (^ - ^ox) ^N +h

(5.17)

+ ^t

(|)t being the "depth" of the trap, counted from EQ^^^ i.e. the lower edge of the nitride conduction band. Probability P^ has a form similar to that of P^^ but with the appropriate notation of the nitride barrier. It yields: \l/2

P/y = exp

4 (2m^)

3hq^N

\3/2 K3/2

^j^^^-^ox)^N V

0r

-i

(5.18)

Depending on the circumstances, several simplifications may be introduced in Eq.(5.16) describing probability P* and consequently in the expressions of J2 and J3. 1) If the traps are located at the interface of the two insulators, then PN = 12) In the case of low fields, the barrier lowering term (i.e. qCx-t^^) ^N) ^^^ be small compared with (^^. Consequently, the term in brackets in the tunneling probability given by (5.18) can be approximated.

364

P, Gentil

3) For very weak electric fields and traps at the interface, the oxide barrier is rectangular and the probability of crossing such a barrier is equal to: (5.19a)

^.;cfe.^0) = expfY' where 1/2

>l =

(5.19b)

8^lx i^t +^2). The above equations can be applied in different ways depending on the trap properties. • If we consider shallow traps of the nitride corresponding to J2 in Fig. 5.4 and Fig. 5.6, the probability that the captured electrons will be re-emitted into the conduction band of the nitride is high. It follows that these traps can be considered as always empty, i.e. f^ = 0 in Eq.(5.15). • On the other hand, if we consider deep traps, corresponding to J3 in Fig. 5.4 and Fig. 5.6, it can be assumed that these traps are those used for the memory effect in the structure and that they retain the captured electrons. Consequently, the number of traps available to capture an electron decreases with increasing time. It follows that in Eq.(5.15), f^ increases with time. 3.4.4. Carrier motion in the nitride Compared to silicon oxide, silicon nitride has a smaller band gap and smaller barrier heights at its electrodes, as illustrated in Fig. 5.2. Like most insulators, silicon nitride exhibits a large density of traps in its bulk (much larger than that of silicon oxide). It possesses shallow traps from which the exchange of carriers with the conduction and valence bands is easy, which can limit carrier motion. In MNOS memories, around room temperature, and in high field conditions, the conduction mechanism in the nitride is controlled by the Poole-Frenkel effect. This effect is based on the emission of an electron from a charged trap (positive when empty) towards the conduction band as shown in Fig. 5.7a. The corresponding current depends strongly on the applied electric field. This field lowers the potential barrier resulting from the attraction of the charged trap and the emitted electron (see e.g. Vol. 1, Chap. 5, § 4.4.). At room temperature and for large fields, the nitride current (J^i in Fig. 5.4) is given by:

JNI

- Q <^^ exp —

He

-(l>t

t \l/2 = Cj ^is/ exp (K,)-"-^ kT

where £*N is the high frequency dielectric constant of the nitride.

(5.20)

Multilayer Dielectrics for Memory Applications

365

In the case of low temperatures, a tunneling emission process between traps and the conduction band, as shown in Fig. 5.7b, can predominate. Since the barrier is triangular shaped, the equation giving the corresponding 1^2 current (see Fig. 5.4) has the same form as that of the Fowler-Nordheim effect (i.e. Eq.(5.12) with the appropriate changes in notations).

Ec(^N=0)

Ec(^N^^)

a)

b)

Fig. 5.7 - Illustration of the conduction mechanisms in the nitride, a) Poole - Frenkel effect. Jf^i b) Field emission mechanism. Jfs^2.

4. A BRIEF REVIEW OF THE EARLY MODELS DESCRIBING HOW MNOS CELLS OPERATE Numerous simplified models have been proposed in the past to model the switching of the threshold voltage of MNOS memory devices. These models use the basic relations and phenomena from the previous sections. However, such a set of equations does not yield analytical solutions. Furthermore, even in the case of numerical solutions, the value (and sometimes even the importance) of several parameters are quite unknown. For example, even though nitride traps and O/N interface traps are of major importance for the memory behavior, their characteristics remain unknown. It follows that additional hypotheses must be made to derive usable models. Numerous hypotheses have been proposed regarding the trap distribution inside an MNOS memory in order to describe its main behavior during the writing and erasure cycles. 4.1. MODELS DESCRIBING THRESHOLD VOLTAGE SWITCHING

The models proposed in the past can be roughly classified into three families. 4.1.1. Analytical models which assume that the memory traps are located at or near the oxide-nitride interface These models assume that the stored charge is located at the O/N interface or very close to it. It follows that Eq.(5.1) applies. These models also consider that AQQN is due to a transfer of electrons between the silicon substrate and the traps and that there is no charge motion anywhere between the traps and the gate electrode. This implies that JN(x,t) = 0.

P. Gentil

366

Under these assumptions, Eqs.(5.1), (5.10), (5.15) yield:

"^FB-^l",

[\J^^qN,[f,-f,)pUxd(i>^^dt

(5.21)

Equation (5.21) can be solved for various trap distributions and various expressions of the tunnel probability. We list below some of the resulting models proposed in the literature. • Wallmark, Scott and Ross [15,16] use the trap distribution illustrated in Fig. 5.8a. They assume that the electrons tunnel from the filled valence band of silicon (f^ = 1) towards the nitride traps through a barrier which is rectangular-shaped and independent of time. The real time dependence is then given by the variations in f^, i.e. the fraction of traps occupied by an electron: dt where

=

{Nt-n,)p'

(5.22a) (5.22b)

rtt = NJ^.

The above authors consider that the traps are spatially distributed away from the O/N interface. Ferris-Prabhu has extended this model by integrating Eq.(5.21) between any two limits [17,18]. • Pulver and Dorda [19,20] use the trap distribution illustrated in Fig. 5.8b. The tunneling probability is also assumed to be independent of time and constant for all traps. In this model, the time dependence is controlled by the energy domain of the traps facing the silicon valence band. The extension of this domain varies with the oxide field which in turn depends on the stored charge. Ferris - Prabhu [21] has extended this model to traps distributed both in energy and space. Si

Si

Si02

Si3N4 tunneling/* domain X-TL

a)

3 «v^x(o Si02

Si3N4 tunneling ^ domain ^

b)

Fig. 5.8 - Illustration of the two hypotheses used to explain the switching behavior of an MNOS structure for VQ>0. a) The bulk traps are monoenergetic and spatially distributed, b) The interface traps are distributed in energy.

Multilayer Dielectrics for Memory Applications

3 67

• White and Cricchi [22] assume that all traps are monoenergetic and located at the O/N interface. They obtain a time dependence by considering that the tunnel probability varies with ^Qx according to a simplified form of Eq.(5.13). Using the same description for the tunneling probability, Ferris-Prabhu [23,24] introduces in addition both kinetics equation (5.22) and a space distribution of traps [25]. 4.1.2. Models which do not assume direct transitions towards memory traps Unlike the models described in § 4.1.1., the models considered next do not assume that the electrons transit between the silicon bands and the memory traps. The current flowing through the oxide is now due to electrons tunneling from the silicon bands towards: either the nitride or the oxide conduction band or to shallow relay traps. After tunneling, electrons are assumed to be trapped in deep traps located close to the O/N interface which implies that Eq.(5.1) is still valid. The characteristics of memory traps are not described. The traps are only able to store the full charge corresponding to the difference between the oxide and the nitride currents as given by Eq.(5.10). An additional difference between the models of § 4.1.1 and those of the present section is introduced by considering that the nitride current is not nil. The use of simplified current relationships of the form. In J a |^|, has been proposed in Refs. [26,27]. Analytical solutions are then possible and can be applied within a small range of biasing conditions. • Frohman-Bentchkowsky and Lenzlinger [28,29] use the Fowler-Nordheim relation (5.12) in the oxide and relation (5.20) for the nitride current. In such conditions, the equations are numerically solved and applied to the case of the thick oxide MNOS structure. Svensson and Lundstrom [30,31,32,33] and Buguwala and Gunckel [34] apply the same set of equations to thin oxides by considering the appropriate W.K.B. tunneling equations (5.11) to (5.14). • Maes and Van Overstraeten [35,36] explain the working of thin oxide MNOS devices under a weak electric field by considering that tunnel transitions take place between the silicon conduction band and shallow traps of the nitride as described in § 3.4. and illustrated in Fig.5.6. These shallow traps are not the memory traps. An electron trapped on a shallow trap is then emitted towards the nitride conduction band and, after traveling a certain distance in the nitride, is trapped again but on a deep memory trap. Thus f ^ = 0 in Eq.(5.15). The threshold voltage variation can be evaluated numerically or analytically by performing series development. 4.1.3. Analytical models which assume that the memory traps are widely distributed in the bulk of the nitride Some features, among them the measured values of X ^ in MNOS memory devices, clearly show the shortcomings of the models listed above, which all consider that the charge is stored solely at the O/N interface and thus describe threshold voltage shifts by means of Eq.(5.1).

368

P. Gentil

Different methods have been appUed, in order to determine whether the charge in MNOS devices is mainly stored at the 0/N interface or in the nitride bulk. In these methods, experimental results are compared with Eq.(5.6) which can be re-written as follows: FB = yFB-^-^{>N

-%) =V ' ™ - f ^ - f

f

(,„ - . ) p ,
where t ^ is the barycenter of the stored charge measured here from the O/N interface. • Yun [37,38] has performed the simultaneous measurements of Vpg and of the injected charge (by measuring the integral of the "write" current). Assuming that the initial charge is nil and identifying the measured injected charge as Q^, the first form of Eq.(5.23) is verified and allows the determination of t ^ which varies from a few ten A to a few hundred A depending on the charge injected [37,39,40]. A modified version of Yun's method has been proposed by Lehovec et al. [41] by changing the writing procedure and thus approaching conditions of constant current injection. • Maes and Van Overstraeten [35,42] have used a series of identical MNOS structures except for the nitride thickness. Using identical writing conditions and thus assuming that the same Q^ charge has been stored, the Vpg (t^) curves thus obtained verify the first form of Eq.(5.23) and allow the determination of t ^ and Q^. This method has led to the same conclusion: the stored charge is widely spread in the nitride. • Finally, Endo [43] has drawn the same general conclusion from a quite different measurement based on the variation of the conductance of an MNOS transistor as a function of t^ (obtained by successive lapping of the nitride) after a single writing of the device. 4.1.4. Model proposed by Arnett Following the above experimental results and conclusions on the stored charge, a model has been proposed by Amett [44] to explain the build-up of the charge in the nitride and to determine the charge distribution (see also p.714 in Vol.2). The basic relations and phenomena taken into account in the Amett's model are indicated below. • The Poisson equation (5.2) is applied to the nitride. It reads: eN^^

= PN

(5.24)

• The total nitride current is conserved, i.e. Eq.(5.9) holds. • The charge in the nitride is only due to trapped electrons. Holes are neglected. The following formulae thus apply: pN = qn,

(5.25)

JN = q^^d

(5.26)

Multilayer Dielectrics for Memory Applications

369

where n and % are respectively the densities of free electrons and trapped electrons, and v^ is the electron velocity which is assumed to saturate under the strong electric field applied during writing. • The nitride traps are supposed to be shallow, monoenergetic, of the donor-type, and distributed in the nitride bulk. The kinetics of capture and emission of free electrons by traps are described using the Shockley Read Hall theory. The emission probability e^ is fielddependent as described in the Poole-Frenkel effect. We can thus write: - ^ = ^ ^rA ^t [Nt ''n,)-n,e^

(5.27)

-^An.r

(5.28)

with e^ = % ^^P

kT

where i^th is the average thermal velocity of the electrons, at the capture cross section of the electrons by traps and DQ a vibration frequency. Even when the above simplifying hypotheses are used, this model must be solved numerically [45,46]. Approximate analytical solutions have been obtained by introducing further simplifications. • Amett and Yun [39,44] have obtained a simple exponential distribution of the trapped charge assuming negligible detrapping (c^ = 0 in Eq.(5.27)) and small values of the injected charge. • Lehovec [46,47,48] has obtained other simplified and analytical solutions by considering the case of strong detrapping ( n ^ « N^). To compare the solutions of these models with experimental results obtained through the writing of an MNOS memory is not straightforward. The approximate solutions of the models assume as a limit condition that the injection current entering the nitride is constant. However, for all practical purposes, the writing and erasure of MNOS memories are performed under a constant gate voltage bias. In that case, the injected current decreases with time due to the build up of the stored charge. 4,2. MODELS DESCRIBING THE RETENTION OF THE STORED CHARGE

It is of great interest to evaluate to what extent the stored data in a practical memory is permanent. In the general case, the charge stored in the insulator of a non-volatile memory after applying a writing or an erasure pulse causes the device to be in a non-equilibrium state. This state cannot be permanent. The device tends to return to its equilibrium state through a loss of the stored charge. This phenomenon has been described in Vol. 2, p.721. The main elementary mechanisms and results are briefly recalled below.

370

P. Gentil

Let us assume that a writing cycle has caused an excess of electrons distributed in the nitride or in the vicinity of the 0/N interface. The device is then submitted to a small gate bias for reading, or more frequently to zero bias, as indicated in Fig. 5.9. However, even for V Q = 0 , the stored charge generates an intemal electrical field which makes the detrapping of the stored charge easier. Various elementary mechanisms, illustrated in Fig. 5.9, can contribute to the loss of the stored charge. These are: (1) the back tunneling of electrons towards the silicon conduction band, (2) the back tunneling of electrons towards fast states of the Si - Si02 interface, (3) the detrapping and motion of the electrons within the nitride bulk towards both electrodes. Under the effect of the stored negative charge considered here, the intemal electric field is such that it can also further hole injection which in tum neutralizes the negative charge. Two more mechanisms must thus be considered: (4) hole tunneling from the silicon valence band towards the nitride band or deep traps, (5) hole injection from the metal electrode and their transport through the nitride. ql^J

(X-XQX)

Metal

Silicon 0

xox

X

X

Fig. 5,9 - Illustration of the various mechanisms responsible for a loss of the stored charge.

• Lundkvist et al. [48] have proposed a model of charge loss due to mechanism (1) which can dominate in thin oxide MNOS devices. Assuming low field conditions, the tunnel probabilities through the nitride and the oxide are given by expressions similar to (5.19). The kinetics of detrapping is expressed in a way similar to that used for Eq.(5.27), namely: drif = - HfP* dt

(5.29)

Multilayer Dielectrics for Memory Applications

371

where P* is a function of the trap location (x - x^^) in the nitride. Integrating Eq.(5.29) over time gives n^ as a function of space and time. The solution implies that the initial distribution of trapped electrons, n^ (x, 0), is known. By assuming a uniform initial distribution, Lundkvist has obtained an analytical solution giving the remaining stored charge in the nitride after a retention time t. For more realistic initial charge distributions, the problem can only be solved numerically. • A model explaining charge loss through mechanism (2) has been proposed by White and Cricchi [49]. This model considers that the electrons are trapped at the 0/N interface. FerrisPrabhu [50] has extended this model by considering that the trapped electrons are distributed over a certain distance within the nitride. • For long storage times, mechanism (3) must be taken into account in the evaluation of the stored charge. This was introduced by Lundkvist [55] by assuming that electrons trapped can be thermally emitted into the conduction band of the nitride. Lehovec and Fedotowsky [51] have introduced in their model an emission of the stored electrons, reinforced by a Poole Frenkel barrier lowering effect. Williams and Beguwala [52] have considered both mechanisms (1) and (3) and have proposed numerical solutions to the problem. For thick oxide structures Efimov et al. [53] have considered that both the motion of electrons and that of holes in the nitride is limited by the Poole - Frenkel effect. 4.3. CONCLUSION

All the early models mentioned above are able to describe the behavior of some memory structures for specific conditions of operation. However, a general model, usable for the write, erase and retention operations of every MNOS devices is presently not realistic. Too many elementary mechanisms are present, and there exist too many parameters whose value depends on the fabrication process of the device. The role the traps play in the insulators is of primary importance. Considerable efforts have been made in recent years in order to better know the nature and the distribution of the nitride traps. The main results of these works are presented in the next section. These results have been used to develop better models which are presented in Section 7. 5. THE NATURE AND PROPERTIES OF SILICON NITRIDE TRAPS The memory behavior of an MNOS structure depends strongly on the way the injected carriers are trapped and released. The trapping properties are in turn strongly dependent on: • the interaction processes between traps and free carriers, • the spatial distribution of the traps, • the energy distribution of the traps.

372

P. Gentil

All these properties are themselves dependent on the origin of the traps. Just like in Chap. 11 of this volume, where the chemical and structural origins of the major oxide traps are reviewed, it is of interest to know which chemical bond(s) or defect(s) are responsible for the presence of traps in the nitride. This knowledge is necessary to monitor the total trap density and the trap distribution and to optimize memory properties such as: switching, retention and endurance. 5.1. THE STRUCTURE AND COMPOSITION OF SILICON NITRIDE

The nature and the concentration of nitride traps depend on the deposition process of the nitride film and on the subsequent annealing. The most widely used method to obtain amorphous silicon nitride layers for microelectronics applications is the Chemical Vapor Deposition (CVD). CVD may be performed either at Atmospheric Pressure (APCVD), or at Lx)w Pressure (LPCVD) or may be Plasma-Enhanced (PECVD). These deposition techniques are described in Chap.l of this volume. For non-volatile memories, most of the experiments performed in the past have used an LPCVD nitride. 5.1.1. Stoichiometry and dangling bonds The stoichiometry of nitride films obtained by LPCVD is generally close to ideal. In a near perfect stoichiometric amorphous nitride, the Si atoms are co-ordinated by four N atoms in a distorted tetrahedral arrangement while the N atoms are co-ordinated by three Si atoms in a nearly planar trigonal arrangement. The amorphous structure is due to a random distribution of distances and bond angles around the values found in the crystallized material [20,25]. Depending on the deposition conditions, some of the bonds are broken and give rise to structural defects called dangling bonds. Silicon Dangling Bonds (abbr. SDB) are represented as =Si» and Nitrogen Dangling Bonds (abbr. NDB) as =N». In an almost perfect stoichiometric amorphous nitride, concentrations of SDB and NDB should be roughly identical. 5.1.2. The presence of hydrogen However, Si atoms and N atoms are not the only elements found in nitride films. In the LPCVD process, amorphous silicon nitride is formed by the decomposition and the reaction of ammonia (NH3) and silane (SiH4) or by the decomposition and reaction of anmionia and dichlorosilane (SiH2Cl2). In both cases, there is an abundance of hydrogen during deposition. Hydrogen incorporated in the film is easily bonded to Si and N atoms by forming =Si-H and =N-H units. Consequently, the presence of H atoms reduces the concentration of dangling bonds. In the usual LPCVD process used to manufacture non-volatile memories, the nitride layer contains a few atomic percentage (about 2-8%) of hydrogen [54,55]. In the process using the decomposition of NH3 and SiH2Cl2, the atomic percentages of N, Si and H depend on the gas ratio and on the deposition temperature [56,57]. In the usual ranges of temperature (from 650°C to 850°C) and of NH3 to SiH2Cl2 ratio (from 2 to 30), the Si content remains almost constant while N and H appear to be competing species: • the higher the deposition temperature, the higher the nitrogen content and the lower the hydrogen content.

Multilayer Dielectrics for Memory Applications

3 73

• the higher the NH3 to SiH2Cl2 ratio, the higher the hydrogen content and the lower the nitrogen content. Once a nitride film has been deposited, an annealing can modify its content. Annealing at high temperature in a neutral atmosphere (e.g. in N2) breaks the H bonds. The out-diffusion of H results in a lower atomic percentage of H in the film and in a higher concentration of dangling bonds [55,58]. On the other hand, an additional annealing in hydrogen can, to a certain extent, reintroduce hydrogen atoms in the silicon nitride film and consequently neutralize some dangling bonds. 5.1.3. The presence of oxygen The introduction of oxygen (O) in the nitride layer is possible as determined by Kapoor et al [56,57] by adding gaseous nitrous oxide (N2O) to the ammonia dichlorosilane gas mixture during the LPCVD process. The result of this process is an oxynitride film (SiO^Ny) in which the structure remains similar to the silicon nitride structure, but with O atoms replacing N atoms in some locations. Moreover, it appears that some O atoms tie up some SDBs. The incorporation of oxygen also reduces the hydrogen content of the film. More information on oxynitride films can be found in Chap. 1 of this volume. 5.2. THE ORIGIN OF THE NITRIDE MEMORY TRAPS

Various theoretical and experimental studies have looked into the origin and the state of charge of the traps associated with memory effects in silicon nitride. 5.2.1. The various possible defects Given the structure described above, the following defects are thought to disturb the natural density of states of amorphous LPCVD silicon nitride: • silicon dangling bonds

sSi»,

• nitrogen dangling bonds =N», • silicon-hydrogen bonds

=Si-H,

• nitrogen-hydrogen bonds =N-H. In all studies, it has been shown that =Si-H and =N-H bonds give rise to states which lie outside the nitride gap and thus cannot contribute to the memory effects. Other defects such as =Si-Si= can also be expected. However, according to [59] =Si-Si= is found to give rise to a bonding state lying just in the gap at about 0. leV above the valence band while the antibonding state is in the conduction band. Consequently =Si-Si= centers only give rise to a narrow valence band tail. Silicon dangling bonds and nitrogen dangling bonds are thus the defects most likely to contribute to the memory effects, although authors disagree about their respective role.

374

P. Gentil

Starting from a theoretical point of view, Kirk [60] has proposed that defective nitrogen bonds are mainly responsible for charge trapping effect. From theory, Robertson and Powell [59] and on the other hand from empirical study, Ngai and Hsia [61] have attributed the memory effect to the SDB center. In [59], the NDB center is identified as the hole trap, being negatively charged when empty, enabling hole conduction by Poole-Frenkel effect. 5.2.2. The important role of silicon dangling bonds In a more recent paper, Krick et al. [62] present a direct and strong experimental correlation between the density of SDBs and charge trapping phenomena. The Electron Spin Resonance (ESR) technique allows them to measure the paramagnetic spin density. In silicon nitride, neutral SDB centers are measured by ESR. By performing ESR and capacitancevoltage measurements on the same sample, after selectively charging the nitride film with a positive or a negative space charge, and also by eliminating these charges by UV illumination, the authors show that a paramagnetic neutral SDB defect may capture either an electron or a hole. The capture of either carrier makes the SDB defect diamagnetic and charged. A recent study based on electron-nuclear double-resonance and ESR experiments [63] shows that the SDB center is made up of a silicon atom bonded to nitrogen atoms with the unpaired spin density mainly on the silicon. It must be noted that virgin samples of nitride exhibit lower ESR signal than UV illuminated ones [62,64,65,66]. This feature seems to indicate that in virgin nitrides, most of the SDB centers are not neutral and paramagnetic. The initial state of charge of the traps encountered in an as-grown nitride is presently a subject of discussion as presented below. Although its initial state of charge is not clear, the SDB appears to be that defect which contributes most to memory traps in MNOS devices. It is distributed roughly uniformly in the nitride bulk. This mode of distribution, which could be inferred from the structural origin of the defect, has been confirmed by experiments. 5.3. SOME PROPERTIES OF THE NITRIDE TRAPS

5.3.1. Some usual hypotheses Starting from a well-identified defect, an electronic structure can be calculated. However, various hypotheses must be made which lead to various trap level characteristics. As proposed by Kirk [20], a defective Si-N bond can lead to a more complex situation than a simple couple of one =Si» and one =N» because of defects rearrangements. Furthermore, following a general work on amorphous materials [67], it is assumed in [59] that SDBs outnumber NDBs due to constraints in the random network. NDBs are also more effectively passivated by hydrogen since the bonding energy of N-H is larger than that of Si-H [68]. Different hypotheses can also be made about the donor-like, acceptor-like or amphoteric behavior of the defect. From this latter hypothesis. Kirk [60] and Ngai and Hsia [61] consider that dangling bonds have a negative correlation energy which means that it is more favorable for states to be doubly occupied than singly occupied. Robertson and Powell [59] argue that this is not valid for Si3N4 and consider that the correlation energy is positive.

Multilayer Dielectrics for Memory Applications

3 75

Nowadays, some uncertainties persist about the precise nature of the nitride traps and consequently about their main electronic properties. Although a unique and precise model of nitride traps is not available today, some general features must be taken into account if one wants to analyze and model the memory behavior of MNOS structure. These features are described next. 5.3.2. Volume distribution There are objective reasons to believe that a large density of traps, ranging from 10^^ to 10^^ cm-^, is distributed throughout the nitride bulk. This feature is consistent with the studies conducted on the structure of silicon nitride described above and agrees with previous works based on the direct measurement of the stored charge in MNOS memory transistors [35,37]. As pointed out in Chap. 16 of Vol. 2 of this series [1], the first MNOS memory models which considered that the nitride traps are located only at the O/N interface are no longer valid. However, specific structural defects can indeed exist at the interface, giving rise to a somewhat higher trap density near the O/N interface, as it was suggested in [68]. This has also been introduced in recent works [69,70], by assuming both a uniform density of bulk traps and an excess of near-interface traps. 5.3.3. State of charge As pointed out in § 5.2., several theories and experiments have led to different conclusions on the origin of the memory traps: SDB, NDB or both. In connection with their origin, the nature: amphoteric, donor-like, acceptor-like (or an association of these different types) of memory traps is a matter of discussion. Some important features of this discussion are reported below. • From a theoretical point of view, but without calculation. Kirk [60] first proposed that memory traps arise from two types of defects associated with nitrogen. He assumes that both defects exhibit three states of charge (+,0,-). By applying the Anderson concept [71] of a negative correlation energy (U), Kirk describes the equilibrium state of the nitride by a trap level negatively charged lying near (1-2 eV) the conduction band and a trap level positively charged lying near (1-2 eV) the valence band. Both traps are present in equal concentrations giving a globally neutral charge when the nitride is in equilibrium. • Ngai and Hsia [61] used the same Anderson negative U concept, but applied it to SDB defects whose energy levels are located deep in that portion of the nitride gap facing the silicon gap. • Robertson and Powell [59] established in their theory that the SDB defects are the deep traps responsible for the long term memory effect. They proposed a positive correlation energy (U) for both SDB and NDB centers. The SDB center is amphoteric, exhibiting one donor-like level at about 2.1 eV below Ec(N)' (the nitride conduction band edge) i.e. in front of the silicon forbidden gap and one acceptor-like level at an energy U (-- 0.4 eV) above the donor-like level. At equilibrium, part of the SDB centers are neutral (and paramagnetic) while some are positively charged.

376

P. Gentil

The NDB centers give a valence band tail about 1-1.5 eV wide. They are doubly occupied (negatively charged) and act as hole traps responsible for the Poole-Frenkel hole conduction. • Fujita and Sasaki [68] have found a correlation between ESR measurements giving the density of paramagnetic SDB centers and the write/erase, retention measurements. The correlation has been confirmed on various samples obtained with a large variation of the NH3/SiH4 ratio. Their conclusion is that the SDB center with its three possible states of charge (+,0,-) constitutes the origin of the memory trap. However, the authors outline that the sole measurement of the flat-band voltage of MNOS devices does not enable us to conclude what the equilibrium (initial) state of the traps is. These traps can be mostly in the neutral state or they can be split between negative and positive states if the negative U concept is used. Moreover, in their experiments, Fujita and Sasaki report that the measured trapped charge density is much larger than the spin density of the paramagnetic neutral SDB centers. This can be explained by the negative U concept which mainly results in negative and positive states with no spin. However the same experimental data can also be explained by the Robertson and Powell theory. By taking a positive U energy into account, it yields a distribution of states which are partially neutral and partially positive, the latter being compensated by centers in a negative state from another defect origin, in almost equal density. Furthermore, since ESR measurements are performed on thick devices, a non-uniform trap distribution with a higher density of traps in the neutral state near the 0/N interface region may also explain the results as discussed by Fujita and Sasaki in [68]. 5.3.4. Energy levels The energy levels of the traps and their capture and emission coefficients are three parameters which play a very important role in the memory behavior of the structure since: • energy levels determine the prevailing mechanism during the writing and erasing phases, • energy levels, capture and emission coefficients determine the loss of charge taking place during the retention phase and the information reading phase. Finally, all three parameters can also play a role in the fatigue phenomena observed after a large number of write/erase cycles. It is however not easy to obtain a direct and unambiguous information on these parameters. First of all, as pointed out before, the fabrication process influences the dominant defects in the nitride, and therefore the dominant properties of the traps. Electronic trap properties may differ from one work to another. Secondly, most experimental techniques used to determine energy levels consist in measuring the thermal and optical excitation effect of electrons which have been stored into the nitride after a writing cycle. Experimentally measured electronic properties may thus depend on the writing procedure as well as on the measurement procedure used after writing.

Multilayer Dielectrics for Memory Applications

?>11

Various experiments have been carried out for a long time in order to determine the energy levels of the electrons trapped in the nitride of MNOS memory devices. Most of these determinations use a first step which consists in filling the trap. The trap levels are then determined by re-emitting the trapped carrier. • Several authors working on different structures have determined the following trap depths by using thermally stimulated current techniques (the depth is the distance in energy below Ec(N)): 0.5-0.9 eV [72], 1.1 eV-1.2 eV [73], 2.55 eV [74] and 1-2.5 eV [75]. • Kapoor and Bibyk [76] using photodepopulation techniques have found traps at: 2.5 eV, 2.76 eV, 3.03 eV, 3.36 eV and 3.76 eV below EQN) with a width at half maximum of 0.08 eV, 0.02 eV, 0.05 eV, 0.32 eV and 0.17 eV respectively. • Information about trap energy depth can also be deduced from memory charge decay observed through the time dependence Vpg or N^ in MNOS devices. Trap depths have thus been determined at 1.3 eV [52], 1.5 eV [51], 1.8 eV [77] and 0.6-1.2 eV [78]. • From steady state electrical conduction in silicon nitride, the Poole-Frenkel emission process leads also to trap depth results in the 1-1.5 eV range [64]. In fact, traps are found to be widely distributed in energy over the nitride gap. Several hypotheses may thus be considered when modeling the working of devices which include a nitride layer. Depending on the phenomenon to be modeled, importance may be given to a specific energy level or to an energy distribution. Most often, the energy levels of traps are used -explicitly or implicitly- as fitting parameters when comparing experimental and theoretical results. 5.4. THE STUDY O F NixRroE TRAPS USING THICK OXIDE MNOS DEVICES Our knowledge of nitride traps and of their distribution has recently improved due to experimental work carried out on thick oxide MNOS devices. 5.4.1. Why use thick oxide MNOS structures? Oxide layers thicker than 30 A neither allow direct tunneling to nitride traps nor allow modified Fowler-Nordheim injection from silicon. Furthermore, once the charge is trapped in the nitride, fast back-tunneling to silicon is not permitted. It follows that the charge distribution in the nitride is easier to measure using thick oxide MNOS structures than using thin oxide ones. Moreover, a thick oxide can be manufactured under well-controlled conditions and thus possess well-defined properties such as a low trap density. Thus, in thick oxide MNOS devices, all electrons injected from the silicon conduction band (for V Q > 0) are assumed to arrive at the O/N interface and are further injected into the nitride conduction band. In the nitride, carrier transport and trapping are described by Amett's model [44] recalled in § 4.3. and described by Eqs.(5.24 to 5.28). The latter set of equations also assumes that holes have negligible effects, which seems to be verified in every experimental result reported for moderate gate voltages and stored charge.

378

P. Gentil

5.4.2. The results of Park et al Using thick-oxide devices, Park et al [69] have studied the injection of electrons under relatively low fields in the dielectrics. The detrapping of electrons is shown to be negligible in trapping equation (5.27). The set of equations can be solved numerically. By experimentally determining the change in the charge centroid and the injected charge, the density of electron traps is then determined from the model. Their data is well explained by considering a uniform bulk density of about lO^^ cm-3 and an interface trap density of about 1.5 10^^ cm-^ extending 150 A into the nitride layer for LPCVD nitrides. PECVD nitrides exhibit a lower interface trap density than LPCVD nitrides. The origin of the enhanced defect density at the interface can be related to a hydrogen-depleted layer where silicon dangling bonds or other defects are not passivated. 5.4.3. The results of Martin et al The same set of equations has been used by Martin et al [70,79,80]. In this case, detrapping is not neglected and is described by the Poole-Frenkel effect (Eq.(5.28)). In [70], the experiment first involves a writing operation under a high amplitude and long positive V Q pulse. In such a device and with such biasing conditions, the distribution of the stored electrons in the nitride is assumed to be equal to the distribution of traps. The traps are then emptied by applying a lower positive gate voltage which allows the detrapping of the electrons and their motion towards the gate electrode where they are collected. Under such a bias, both electron injection from the silicon and electron re-trapping are negligible. Martin et al show that the observed variation of Vpg as a function of time is well described by a distribution of traps given by: A^^ = A^^ exp

(

x^

+ N^

(5.30)

^S J

where N^ is the trap density per unit volume, N^ the trap density in the nitride bulk, Ng the excess trap density at the 0/N interface and x^ the characteristic length of the trap distribution. The origin (x = 0) of the charge distribution is taken at the 0/N interface. The best fit is obtained by considering N^ = 1.5 10^^ cm-^, N^ = 2.4 lO^^ cm-^ and x^ = 36A. Both the work of Martin et al and that of Park et al conclude on the presence of an excess of electron traps near the 0/N interface, whose density is about 10 times larger than the trap density in the nitride bulk. 5.5. EvroENCE OF HOLE TRAPPING IN THE NITRffiE OF A THIN OXmE MNOS DEVICE

In thick-oxide MNOS memories, the variation in stored charge is mainly attributed to trapped electrons. The injection of holes is considered to be negligible since the energy barrier heights are larger for holes at the injecting interfaces. Most of the experimental results can be explained by considering only electrons.

Multilayer Dielectrics for Memory Applications

379

Deviations of the corresponding models are observed only for large gate biases which give rise to high electric field, whose magnitude can be further enhanced by a charge stored in the insulators. In thin oxide structures, under negative gate biases, band-to-band or band-to-trap hole tunneling allow the injection of holes into the nitride at relatively low fields. The difference between thin and thick oxide is illustrated in Fig. 5.10.

Si

SiO^

SigN^

Si

(D"

a)

SiO^

O ©

SigN^ ^^

tP^

b)

Fig. 5.10 - Energy band diagram of an MNOS device under a negative gate bias giving an oxide field of ^^^ = 7MV cm a) Case of a 60 A thick oxide: hole tunneling is not permitted, b) Case of a 15 A thick oxide: hole tunneling through CD band-to-band and ©band-to-relay traps mechanisms is possible.

Consequently, the switching of thin oxide devices can be analyzed in terms of electrons stored in the nitride, after a positive gate pulse, and in terms of holes stored in the nitride after a negative gate pulse. This dual trapping implies that both electron and hole traps exist in the nitride. Recent works on nitride traps indeed show that either both types of trap exist or that amphoteric traps are present. Experimentally, it has been known for a long time that both negative and positive charges can be stored in the nitride. Hampton and Cricchi [81] have reported measuring the charge distribution for holes and electrons in steady state conditions by using the Maes and Van Overstraeten method [36,42]. Their results show that the number of trapped holes is greater than that of trapped electrons under the same maximum nitride field. However, the value of the hole centroid, counted from the 0/N interface, is much greater than that of the electron centroid at room temperature. It follows that the shift in W^ is somewhat smaller for stored holes than for stored electrons.

380

P. Gentil

5.6. CONCLUSIONS

Silicon nitride exhibits quite a complex structure of traps which strongly depends on the preparation method. For memory applications, LPCVD performed with a mixture of NH3/SiH2Cl2 or NH3/SiH4 is the most often used method. The composition of LPCVD nitrides is near stoichiometry with a low hydrogen content. The exact composition and structure of the nitride depend on: the gas ratio, the temperature and on the subsequent annealing. It is now believed that the main traps, responsible for the memory effect are the SDB centers. Hydrogen has a passivation effect both for the SDB and the NDB centers. SDBs appear to introduce energy levels deep in the nitride gap and possess three states of charge (+,0,-). This allows to store a positive or a negative charge on this unique defect. Today it seems difficult to conclude on the initial state of charge of the traps which can be either mainly neutral or be evenly split between positive and negative states. The experimental determination of the trap energy levels reveals a complex structure exhibiting multi-energy levels which may either be attributed to SDBs or to other defects. Recent experiments performed on thick oxide MNOS devices have been explained by a uniform density of electron traps inside the nitride bulk and a higher density of electron traps near the O/N interface. Other experiments performed on thin oxide MNOS devices have clearly shown that both a negative charge and a positive charge can be trapped in the nitride films. Although our knowledge of the electronic properties of silicon nitride has greatly improved in recent years, it remains subject to several hypotheses. Furthermore, the values of the main electrical parameters strongly depend on fabrication parameters. The independent and direct measurement of the various electrical parameters cannot be performed directly on the MNOS device used in non-volatile memory ICs. The modeling of the write, erase, reading and retention operations of MNOS devices is now possible but still relies on a lot of hypotheses and parameters. 6. SHORTCOMINGS AND LIMITATIONS OF MNOS STRUCTURES The design and the use of MNOS structures as non-volatile memories must consider two additional factors: hole injection and device dimensions. Hole injection, previously disregarded as a possible carrier exchange mechanism, must now be taken into account and controlled. Furthermore, since the stored charge is in fact widely distributed in the nitride bulk, the shrinking of device dimensions is limited. We examine these two factors in more detail next. 6.1. T H E ROLE O F HOLE INJECTION DURING MNOS SWITCHING

The measurements reported in Section 5 yield the net charge in steady state conditions. This is very important information but it does not allow us to definitely conclude the precise nature of the mechanisms and the carrier type responsible for establishing this net charge. As explained next, a new experimental approach is needed.

Multilayer Dielectrics for Memory Applications

381

6.1.1. The carrier injection mechanisms caused by negative biases As illustrated in Fig. 5.11, when a negative gate voltage is applied to an MNOS device, several elementary carrier motions can take place and contribute to the final net charge in the nitride: • component © corresponds to the injection of holes from the silicon substrate into the nitride layer • component ® corresponds to electrons, previously trapped in the nitride, that escape towards the silicon. Component © would seem to be the most simple process and thus that most likely to be observed on a virgin device. Indeed, it can be shown that in a virgin device the net charge is nil before applying the bias and that the net charge is positive after applying the negative bias. However as reported in Section 5 an initially nil charge could also be given by an equal number of negative and positive charged traps. Furthermore carrier exchanges between the nitride and the gate electrode can occur through two other types of motion: • component ® corresponds to holes that escape from the nitride to the metal gate, • component ® corresponds to the injection of electrons from the gate into the nitride. Components (D and ® tend to reduce the effects of © and ®.

Metal Si

Fig. 5.11 - Carrier motion at the electrodes under a negative gate bias.

Each of the elementary carrier motion can be described by different mechanisms (for instance motion © can be described by band-to-band tunneling or by band-to-trap tunneling). Similar carrier motions and elementary mechanisms are of course possible by applying a positive gate bias.

382

P. Gentil

6.1.2. The usefulness of MONOS structures In order to better control the charge build-up in the insulator, and to better understand the trapping and detrapping mechanisms in the nitride, it appears desirable to restrict the possibilities of carrier injection to only one electrode, namely the silicon substrate on which the thin tunnel oxide has been grown. To prevent an exchange of carriers between the nitride layer and the metal gate, a third dielectric layer may be inserted between the two. This third layer can be made of Si02, thick enough to prevent direct tunneling. Si02 also exhibits a greater barrier height with the metal gate than does Si3N4. Such a MONOS structure was first used by Agarwal and White [82,83] in order to determine the type of charge species being injected from the silicon under positive and negative gate biases. The general working of MONOS memory devices will be presented in Section 7. Let us simply assume here that a MONOS structure is an MNOS structure in which no carrier exchange with the gate is possible. + 10Vi

+ 10V

Fig. 5.12 - Principle of a charge separation measurement performed on a MONOS structure.

6.1.3. Charge separation measurements Using MONOS structures, it is of interest to use experimental techniques to separate the injection (or the extraction) of holes from the extraction (or the injection) of electrons during a variation of the gate voltage. The measurements are based on the charge separation concept of Ginovker et al [84] and on the linear voltage ramp technique that has been used to study the properties of the siliconoxide interface in MOS structures [85]. These experiments must be carried out carefully in order to eliminate every parasitic current component.

Multilayer Dielectrics for Memory Applications

383

Let us consider the structure represented in Fig. 5.12. First a positive gate bias is applied for a long time resulting in a net negative charge stored in the nitride and a large positive flat band voltage. Then, VQ is linearly decreased from a positive low voltage (for which the semiconductor is in weak accumulation) to a large negative voltage (for which the semiconductor is in strong inversion and allows a significant charge variation in the nitride) and finally back to the initial positive value. The semiconductor remains in quasi equilibrium during the voltage ramp since electrons are easily provided by the N bulk and holes easily provided by the P+ region. Let us consider the structure, during the voltage sweep towards the negative value, when the semiconductor is in the depletion and inversion regimes (see Fig. 5.13.a). The P+ region supplies holes for the inversion layer and for the charge variation in the nitride (Ip < 0 with the sign conventions of Fig. 5.13). On the other hand, if electrons stored in the nitride tunnel back to the silicon, they are swept into the substrate and are collected by the N+ region and finally by the back contact (I^ < 0 with the sign conventions of Fig. 5.13). At the most negative V Q value a net positive charge is stored in the nitride giving a new flat band voltage.

VG=-«t+Vo

Vc = + a t + V '

Fig. 5,13 - Hole and electron motions during a charge separation measurement a) During the voltage sweep from flat band to strong inversion. b) During the voltage sweep from inversion to flat band.

During the reverse voltage sweep, holes are removed from the inversion layer to the P+ region to contribute to the Ip current which is now positive (see Fig.5.13.b). While the semiconductor is still in inversion or in depletion some holes can be injected into the nitride and some electrons can tunnel to the silicon (I^ remains < 0).

384

P. Gentil

By considering a voltage sweep which brings the silicon substrate from flat band to strong inversion and back to flat band, the integral over time of current Ip gives the hole charge injected during the sweep. The integral over time of current I^ gives the electron charge extracted during the sweep. It must be outlined that holes leaving the nitride for silicon will recombine with electrons, if the n-type silicon substrate is in accumulation. In order to distinguish between the electron and the hole motions contributing to the variation of the stored charge when the initial charge is positive, a dual structure with a p-type semiconductor must be used. The main conclusion of this work is that holes are injected from the semiconductor into the nitride for VQ < 0 while electrons are injected for VQ > 0. For the devices used in this study and under the biasing conditions applied, the switching of an MNOS structure cannot be explained by a single carrier model. It can be concluded that a recombination of electrons and holes takes place in the nitride by means of amphoteric traps associated with the silicon dangling bond defects mentioned in Section 5. Unlike previous works, reported for example in Chap. 16 of Vol.2 [1], modeling the switching of modem thin oxide MNOS or MONOS memories must now be carried out by taking both carriers into account. 6.2. LIMITATIONS TO THE SCALING DOWN OF MEMORY DEVICES DUE TO THE SPACE CHARGE DISTRIBUTION

To gain space and speed of operation and to reduce power consumption, device dimensions are constantly scaled down. This trend also applies to MNOS devices for which attempts are made to reduce both the oxide thickness and the nitride thickness. • Thinner oxides ensure a faster switching under relatively low applied gate voltages (for practical MNOS devices, t^^ is in the 1.5-2 nm range) • For thinner nitrides, the gate voltage which ensures a given injection field during the write or erase operation may be lowered, as deduced for instance from Eq.(5.3). However, if the nitride layer is thinner, the AVj value corresponding to a given AQQN is smaller, as visible from Eq.(5.7). Furthermore, this effect is more pronounced if the charge is widely distributed in the nitride rather than located at the O/N interface. 6.2.I. Limitations due to charge storage possibilities This limitation was announced early on by Hampton and Cricchi [86]. They consider that the steady-state condition is obtained when detrapping balances trapping in the nitride region. They consider that the balance is established when occurring locally in the area where the field is maximum (taking into account the effect of the stored charge). The authors define a limit to the scaling down by considering an arbitrary level of stored charge and a nitride thickness which is twice the charge centroid. This limit is shown to depend on the nitride deposition process and on the temperature of the write/erase operation since detrapping is temperature enhanced.

Multilayer Dielectrics for Memory Applications

385

For the best deposition process, and for devices operating at room temperature, they experimentally define a minimum nitride thickness of about 190 A which permits a threshold voltage variation between - 1.5V for stored holes and +2.2V for stored electrons. These values are steady state ones. Since in a practical application the duration of the write or erase phase is limited, higher fields may be necessary to obtain the same amount of stored charge. However any field increase affects the detrapping process and the charge centroid. The ensuing threshold voltage window is smaller. 62.2. Limitations due to charge retention and endurance possibilities The above considerations about scaling down the nitride thickness in MNOS memory devices take into account criteria relative to the initial charge state or to the initial threshold voltages after the application of a write or erase gate pulse. However, since the MNOS structure is actually used as a non-volatile memory, one must also know how this device behaves after a long retention time at a maximum temperature (typically ten years at 70°C). Furthermore, the decay rate of the threshold voltage is known to increase with the number of write/erase cycles as defects are created in the device. MNOS memory products must thus also guarantee a minimum number of write/erase cycles (typically 10^). The retention characteristics of MNOS memory devices are degraded by write/erase cycles. Such degradation has been observed [87,88]. It is assumed that the highly energetic carriers which are injected to modify the stored charge create some defects in the structure. These defects can introduce additional fast states at the O/N interface as well as traps near it. Both types of traps will contribute to a fast decay of the stored charge after cycling [57]. Furthermore, the degradation is also accompanied by a large increase in nitride conductance [89] which also contributes to a faster discharge of the stored charge through the nitride layer. These retention and endurance characteristics behave as shown in Fig.5.14. Obviously, the behavior after 10 years must be extrapolated from very precise and carefully defined experimental results obtained after relatively short test periods.

10 years •

i

r"7

1

10_, 10\

10 cvcles

TT

rr

r—

I-T

TT

lo'

lo'

lo'

lo'

lo'

ITP"*

lo'

t(s)

1(

2 H-

Fig. 5.14 - Decay of the threshold voltage observed during retention, with the number of write/erase cycles as a parameter. Top curves correspond to stored electrons, bottom curves correspond to stored holes [90].

386

P. Gentil

Recently, Minami and Kamigaki [90] have reported results obtained from a highly stable and controllable MNOS process used for commercial products. This process includes a polysilicon gate, an optimized tunneling oxide [91] and a nitride thickness ranging from 200 A to 270 A. Their experimental retention data shows that the decay rate of V^ decreases with t^ for a fixed initial V j corresponding to the storage of electrons. When holes are stored, instead of electrons, the decay rate of V j is constant when t^ decreases. Minami and Kamigaki, by carefully analyzing the decay rate and the charge distribution, have extrapolated their result to define a minimum nitride thickness of 123 A which can be used with a write or erase voltage of 8V in a 16 Megabit EEPROM product. 7. THEORY AND MODELING OF THE MONOS STRUCTURE USED AS A NONVOLATILE SEMICONDUCTOR MEMORY Regular MNOS structures have several limitations. These may be overcome by introducing an additional oxide layer between the nitride and the metal electrode. Let us examine in more details the advantages of the MONOS structure, when used as a non-volatile semiconductor memory. 7.1. T w o REASONS TO INTRODUCE AN ADDITIONAL OXIDE LAYER

First, the use of an aluminum gate in an MNOS device does not allow the manufacture of dense and high speed circuits because Al deposition is not a self-aligned process. Moreover, the integration of the MNOS technology in a VLSI or ULSI process is not easy. It thus appears desirable to develop a polysilicon gate technology. Replacing aluminum by polysilicon seems a simple approach but it is an unpractical one. The silicon/silicon nitride interface is unstable as has been shown [92]. This instability, observed in a SNOS (poly Silicon-Nitride-OxideSilicon) memory capacitor has been remedied by employing a SONOS (poly Silicon-OxideNitride-Oxide-Silicon) structure [93]. Secondly, the existing MNOS non-volatile memories require relatively high voltage pulses, typically 15V - 25V, for writing and erasing. It is quite desirable to decrease this voltage for future applications in VLSI technology. This can only be performed by reducing the nitride thickness. However, the fact that the charge stored in the nitride is widely distributed, limits the possibilities of scaling down the nitride thickness. Here again, an alternative solution to the MNOS memory structure is the MONOS (or SONOS) device [94]. In MONOS structures, the charge centroid is closer to the silicon surface. The presence of an Si02 layer between the nitride and the gate electrode modifies the conditions which limit the amount of charge which can be stored in the nitride during writing or erasing. It also modifies the decay of the stored charge during retention. 7.2. SOME PROPERTIES OF THE BLOCKING OXIDE

Assuming that the charge is nil everywhere and that the difference in work function is also nil, the energy band diagrams of the MONOS and SONOS structures at equilibrium are those given in Fig. 5.15. By looking at these band diagrams, the nitride layer can be described as a potential well between two Si02 layers. Such a structure resembles a floating gate memory.

Multilayer Dielectrics for Memory Applications

387

3.1 eV

3.8 eV

Si

O tunnel

O blocking

M(A1)

Si O

N

tunnel

O

poly Si

blocking

Fig. 5.15 - Energy band diagram a) of a MONOS device b) of a SONOS device.

There are however strong differences between the two structures. Free carriers in the conduction and valence bands of the nitride encounter relatively low barrier heights at the Si02 boundaries. In a non-volatile memory, these barriers can maintain the carriers, injected from silicon, confined in the nitride during the write or erase operations but only trapping on the deep nitride traps can ensure the long term retention of the stored charge. On the other hand, in a floating gate memory, the stored charge is made up of free carriers and a single defect extending throughout the Si02 layer causes the memory to fail. In this case, a reduction in the thickness of the insulators appears more difficult to achieve. The method most widely used to manufacture the blocking oxide (BO), located between the nitride and the gate electrode, is the thermal oxidation of the silicon nitride. Electronic properties at the N/BO interface can be quite different from those found at the O/N interface because of the different preparation methods. A large number of traps, attributed to oxygen, can be created at the N/BO interface and can also contribute to the memory effect [94]. In fact, there exists a transition layer made up of silicon oxynitride, SiO^Ny, between the nitride and the blocking oxide, whose thickness has been estimated at about 20 A [95]. The transition region causes the energy band diagram to vary slowly as shown by the dotted line of Fig. 5.15b. The blocking action of the top oxide is therefore less efficient. Li order to obtain a sharper barrier, one has proposed in [95] fabricating the blocking oxide by CVD and converting it into a stoichiometric Si02 by a pyrogenic annealing performed at a temperature lower than the thermal oxidation temperature. 7.3. RELATIONSHIPS LINKING CHARGES AND POTENTIALS

The basic relationships of the MONOS/SONOS structures can be derived in a manner similar to that used for MNOS structures. However, solutions are now more complex due to the presence of both an additional layer and an additional interface, as shown in Fig. 5.16. Poisson's equation (5.2) must be solved in order to obtain the different electric fields and voltages, as previously done in Chap. 16 of Vol. 2 of this series [1] or as summarized in § 3.2.

388

P, Gentil tunnel Oxide

Silicon

-//-

H

Metal

yA

Pox

Qsr sc Q: ^sp

i/-

blocking Oxide

Nitride

QN BO

ON ='N

ox

^

^RO

LK.

^?x ^

^

BCbM

^ox

^N

^BO

F/g. 5.16 - Cross section of a MONOS capacitor and definition of symbols used.

When a MONOS memory operates, the only charge distributions which vary are: QQN. PN and its integral over tN (i.e. QN), and QNBO- It follows that the flat band voltage can be written in a useful form, similar to that of Eq.(5.5). ^N ^FB

=

^'FB

^ ^BO

^N

~^N

-QN

- QON ^ox

.

^N

-QNBOT^(5'^^) •^ox

Equation (5.31) allows one to calculate Vpg as a function of i^ and tgo for a given set of QON' Q N ^^^ QNBO values. However, for a given Vpg value, there still exists an infinity of possible values for the (tjs[, tgo) couple. Furthermore, for a given writing or erasure pulse, the values of the charges QQN' Q N ^^^ QNBO stored in the insulators also depend on the tj^ and tfiO values. The choice of the tj^ and tgo values giving an expected Vpg is thus difficult. In practice, two technological approaches have been proposed for the MONOS structure [95]. The first approach [96] is to scale down the nitride thickness for a low voltage operation while the memory charge is mainly stored in the nitride. In that case, the blocking oxide is just thick enough (a few tens of Angstroms) to block the exchange of carriers by direct tunneling between the gate and the nitride. Since t s o is as thin as possible, the effect of QNBO i-^- the charge stored at the N/BO interface, on Vpg (and thus on Vj) is rather small, as can be seen from Eq.(5.31). The V^ shift is mainly due to the Q^ charge as in an MNOS structure. In this first approach, no special effort is needed to obtain a high density of traps at the N/BO interface. The other approach [94] is to make a thinner nitride layer while using a thicker blocking oxide in order to increase the V j shift produced by charge QNBO- ^ that case, the fabrication method is devised to enhance the density of traps at the N/BO interface. Whatever approach is considered, it does not appear that a precise model of the V^ shift can be developed by taking into account the variations of only one type of charge in Eq.(5.31).

Multilayer Dielectrics for Memory Applications

3 89

As previously proposed in § 5.4, an interface trap density can also be considered as a large increase in bulk trap density in a very narrow region near this interface. However, the electronic properties of these traps are probably different from the bulk ones since their origin is different. 7.4. RELATIONSHIPS LINKING CURRENTS AND CHARGES

The continuity equations ((5.9) and (5.10)), given in § 3.3. also apply to the case of a MONOS or SONOS structure. However, an additional continuity equation must now be written for the N/BO interface. It yields: JN

\^N

' 0 " J BO \^N > V =

'J^

(532)

In Equation (5.32), JBO is the current density in the blocking oxide. Of course, if the blocking action is perfect, JBO is nil but this condition is never quite met in practical devices. It must be noted that during write or erase operations, significant currents flow through the device. In the general case, the charge density must include both the free carriers and the trapped carriers. The charge due to the free carriers may not be negligible in the nitride. Especially in the vicinity of the N/BO interface, if trapping efficiency is low and the blocking action is good, free carriers can accumulate and contribute significantly to the charge density. All the elementary carrier exchange mechanisms taking place in an MNOS structure, which are indicated in § 3.4. and described in more details in [1], can also occur in a MONOS structure. An additional current component must now be considered, namely that flowing through the blocking oxide. Since the blocking oxide is thick enough, no direct tunneling current can occur between the gate and the traps of the BO/N interface (or the nitride traps). The only possible mechanism is a band-to-band transition taking place through the blocking oxide when the latter is triangular-shaped by a high electric field. It then gives rise to a Fowler-Nordheim relationship similar to Eq.(5.12). 7.5. CHARGE TRAPPING BY AMPHOTERIC TRAPS IN SILICON NITRIDE

As described in Section 5, and from research on the origin of nitride traps, it seems that the existence of silicon dangling bonds (SDB) which possess three states of charge is the most likely explanation for the memory effect of the nitride layer in MNOS and MONOS devices. This strong possibility has been extensively studied by White et al [97,100] who have developed theories about charge transport and storage in MONOS/SONOS devices. The amphoteric nature of the traps has also been qualitatively considered for MNOS devices [60,62,65,66,68] in order to explain experimental results. The three states of charge of amphoteric traps are denoted D+, D°, D". A trap in a D+ state contains a positive charge and can be considered as devoid of electrons (or doubly occupied by holes), A trap in a D° state is neutral and can be considered as occupied by a single electron (or by a single hole).

390

P. Gentil

A trap in a D" state contains a negative charge and can be considered as doubly occupied by electrons (or devoid of holes). An amphoteric trap interacts with both free electrons and free holes. The combination of D+/D^ states can be regarded as corresponding to a donor-like behavior and the combination of D°/D- states can be regarded as corresponding to an acceptor-like behavior. However, there is a strong difference between two independent (donor-like and acceptor-like) traps and an amphoteric trap since for the latter the neutral state can give rise to both a donor-like and an acceptor-like behavior. When a neutral trap becomes negatively (resp. positively) charged, a donor-like (resp. acceptor-like) trap disappears. In other words, with amphoteric traps the number of donor-like traps and that of acceptor-like traps are not independent. Their occupancy is described by coupled equations. The different interactions between an amphoteric trap, with its three states of charge, and free electrons and holes are illustrated in Fig. 5.17a. a)

electron capture hole emission hole capture electron emission positive state

J)

neutral state

electron capture hole emission hole capture electron emission

D negative state

Fig. 5.17 - Illustration of the different states of charge (a) and of the carrier exchange processes of an amphoteric trap (b).

By considering that the amphoteric trap possesses two energy levels, E^ and E^Q, the possible transitions are illustrated in Fig. 5.17b on an energy band diagram of the nitride bulk. In this representation the neutral state is associated with energy level EfD while E^ is above E^i). That means for instance that, by considering that an initial D" state emits an electron from the E^^ level, a fast relaxation of the electron and lattice occurs giving rise for the following step, to the E^D trap level. Whether the E^^ level is above or below the E^j) level is given by the positive or negative correlation energy (U) concept, respectively. As presented in Section 5, these two concepts are now discussed for the silicon nitride material. The same elementary electron and hole processes are possible with both concepts. However, the most probable state of charge of the traps is different in each concept.

Multilayer Dielectrics for Memory Applications

391

For instance, the thermal equilibrium condition (assumed to exist in a virgin device) gives neutral amphoteric traps with the positive U concept while a share between positive and negative traps is given by the negative U concept [68]. The fraction of traps encountered in the D+, D"", D* states are denoted respectively by f+, f, f-. The variations of these occupancy functions can be expressed by considering that the elementary capture and emission processes defined in Fig. 5.17b obey the Shockley, Read, Hall (SRH) theory: (5.33)

dt dt

= -C°nfif°

-el f° +e~ f~ +C~

pf~

(5.34)

f+f+r=i

(5.35)

In the above equations, n and p are the densities of free electrons and free holes in the nitride conduction and valence bands respectively, C and e are the capture coefficients and emission probabilities respectively. The upperscript denotes the initial state of charge (+, 0, -) and the subscript indicates the carrier type (p or n) involved in the process. The density of the charge trapped in the nitride (PN) is now given by:

PN = qNt[r

-r)

(5.36)

If the nitride traps are located near the 0/N interface, a carrier exchange can take place not only between the traps and the nitride bands but also between the traps and either the silicon bands or the fast states of the Si/Si02 interface. In these cases, the e and C coefficients, which now involve tunnel exchange mechanisms, differ from those of the SRH theory which only imply thermal processes. This is illustrated in Fig. 5.18 for two elementary emission processes. A

i

'^^ •

'

T2

^

s ^^

( ^

• • • • \ ™ ^ i y f _ j ___

Si

tunnel 0

^tA

b ^_

^^__

"

^tD

N

Fig. 5.18 - Representation of two types of electron emission process for both D' state (E^^) and D° state (E^j^)

392

P. Gentil

Modeling the behavior of an MONOS cell while taking into account all elementary carrier exchange processes appears as a rather complex task. The problem can be simplified by considering specific conditions regarding the trap energy levels, the initial state of charge and the applied bias. Unfortunately, since the memory trap levels are subject to discussion, a lot of hypotheses are possible. For instance in Fig. 5.18, if E^D is lowered to be aligned with the silicon valence band, electron emission to silicon by direct tunneling becomes impossible. 7.6. MODELING OF THE MEMORY BEHAVIOR OF MONOS AND SONOS DEVICES

7.6.1. The main assumptions of White's models The full set of equations corresponding to the basic phenomena reported in sub-sections 7.3 to 7.5 cannot be solved in a universal model usable for any MONOS/SONOS memory operation. Too many parameters are unknown, and especially the trap parameters, i.e.: the space and energy distributions, the acceptor, donor or amphoteric character of the traps, and the capture and emission coefficients. Other parameters such as: the tunneling oxide thickness, the barrier heights,... do not have a precise value. The most recent quantitative models of the memory behavior of such devices have been derived by White et al [97,100]. As indicated above, the conmion feature of these models is that an amphoteric trap (with E^y^ > E^D) is assumed to be uniformly distributed in the nitride layer. One considers that no specific trap exists at the 0/N interface nor at the BO/N interface. The devices have a 20 A-thick tunnel oxide, thermally grown on the silicon substrate. The t^ values range from 50 A to 120 A which shows that the limitation in nitride thickness (at about 120 A - 190 A) encountered when scaling down MNOS devices [86,90] can be overcome with MONOS/SONOS structures. The models also imply, for these thin tunnel oxide devices, that both types of carriers can be: injected and trapped during the write/erase operations and slowly detrapped and evacuated towards the electrodes during the retention phase. 7.6.2. A simplified model of the switching behavior considering amphoteric traps In reference [97], injection from the silicon conduction band and electron trapping in the amphoteric traps for VQ > 0 is modeled by taking into account only two of the eight possible capture and emission processes illustrated in Fig. 5.17. These two processes are the capture of electrons in the nitride conduction band by either the positive charge state (D"^, C^) or the neutral charge state (D"*", C^). Electron and hole emission processes are neglected. Equations (5.33) and (5.34) thus simplify to: dt ^

= -Clnf^

(5.37)

= - C; n / +

(5.38)

Multilayer Dielectrics for Memory Applications

3 93

These equations are solved using relations (5.35) and (5.36), and the continuity equation (5.9) in which the drift current is expressed by (5.26) as a function of the free electron density n. The initial condition considers that f"*" = 1, which means that all amphoteric traps are in the D+ state. White et al have solved this equation set to determine the spatial distribution of f+, f°, f-. They show that the f° distribution and the centroid of the stored charge approach the results I

O

given by Amett's model if C^ » C^. In that case, the conversion rate between the D° and the D" states is low, and the amphoteric traps behave like the single occupancy traps considered by Amett. I

O

On the contrary, if Cj^ and Cj^ have about the same value, a large fraction of D+ states are converted to D" states by a double capture of electrons near the electron injection boundary. In that case the amphoteric trap model differs strongly from Amett's model. White's model yields a value for the centroid of the stored charge which is much smaller than that given by Amett's model in the case of high injection levels. The same procedure is used for hole injection (for VQ < 0). Comparing the experimental I

results and the model leads to a C^IC^ __

O

ratio of about 10. The same ratio value is obtained

o

for holes (i.e. for Cp /Cp). The experimental results also show a threshold voltage window of more than 6V with a programming voltage as low as + 8V for the scaled-down device with dimensions of 20 A for the tunnel oxide, 85 A for the nitride and 51 A for the blocking-oxide. 1.63. A more complete model of the switching of MONOS/SONOS memories In reference [98], write and erase operations are also modeled but use less simplifying hypotheses. The set of equations is numerically solved. Both free electrons and holes are assumed to exist in the nitride. They are injected into or escape from the nitride by FowlerNordheim or modified Fowler-Nordheim effects (Eqs. (5.11) to (5.14)) as indicated in Fig. 5.19a (Jon» JBOII' JfiOp' Jop) ^^^ ^ negative gate bias. A trap-assisted tunneling current is also considered for electron injection from the silicon under positive gate bias and low field condition (JJA on Fig. 5.19b). In the case of a negative gate bias, with a high initial occupancy rate of the D" state, the back tunneling of electrons (JBT ^^ Fig- 5.19a) is also considered. The continuity equation (5.9) now takes into account both electron current density Jj^ and hole current density Jp. The total nitride charge includes: trapped holes, trapped electrons and the free carriers, i.e. electrons in the conduction band and holes in the valence band. This can be written: PA^=^[^r(/''-/") + P-^]

(5.39)

For the write/erase process, the equations describing the variations of the occupancy functions neglect the emission (detrapping) processes but retain the four capture processes of holes and electrons.

P. Gentil

394

b)

Fig. 5.19 - Electron and hole currents flowing through a SONOS structure a) Under negative gate bias, b) band-to-trap current under positive gate bias

Relations (5.33) and (5.34) then become:

dt

= -'C^nr+C^pf

df ^-C^nf dt

+Cp

pf

(5.40)

(5.41)

The set of equations can be solved for any initial distribution f^,t=0 ^ ^ fx,t=0 ^ ^ ^^Y spatial trap distribution in the nitride N^(x), This model was successfully compared to experimental results obtained on devices possessing various characteristics including: n-channel and p-channel MONOS and SONOS transistors, MONOS capacitors with aluminum and gold gates, nitride thicknesses ranging from 50 A and 120 A and blocking-oxide thicknesses ranging from 35 A and 50 A. The blocking-oxide was also manufactured through two processes: the thermal oxidation of nitride and LPCVD deposition. This work also presents the possibility of obtaining an initial Vj window of 5V by using a programming voltage as low as + 6V on a MONOS device possessing the following characteristics: tQx=20 A, tN=50 A, tBo=35 A. An extrapolated 0.5V memory window is expected after 10^ write/erase cycles and 10 years of data storage.

Multilayer Dielectrics for Memory Applications

395

7.7. MODELING OF THE RETENTION BEHAVIOR OF MONOS/SONOS DEVICES

The work presented by White et al. in Refs. [99,100] is mainly devoted to the retention characteristics of the charge stored in the nitride. 7.7.1. Discharge of the nitride by back tunneling of trapped carriers In reference [99], the discharge of (previously negatively charged) amphoteric traps is considered to be due to the back tunneling of electrons from the traps in the D" state (see Fig. 5.19). The processes of thermal emission into the nitride bands are neglected by considering a low temperature operation. Hole capture by the traps in the D° state is also neglected by assuming that an appropriate bias condition is applied during storage. The dominant processes considered here are represented in Fig. 5.20. The model includes an energy distribution of traps with a constant energy difference U = E^A - E^D and is applied, under the same assumptions and conditions, to the cases of electron (see Fig. 5.20a) and hole (see Fig. 5.20b) discharge by back tunneling.

-©•

a)

0"\1 blocking

Si "^ O Tunnel

poly Si b)

Fig. 5.20 - Band diagram of a MONOS structure in the retention mode. a) With a large negative charge stored in the nitride, b) with a large positive charge stored in the nitride.

7.7.2. A more complete model of the nitride discharge In reference [100], the discharge of (previously negatively charged) amphoteric traps is assumed to take place through the first three elementary processes presented in Fig. 5.21. As in Ref. [99], the back tunneling of electrons from the traps in the D" state (process (1) Cn) is taken into account. In addition, the back tunneling of electrons from the traps in the D° o

state (process (2) c^) to the fast states of the Si/Si02 interface and the capture of holes from o

the silicon valence band by the traps in the D° state (process (3) Cp) contribute to the discharge of the nitride. In such conditions, the equations expressing the variations in occupancy functions become:

dt

=+e„/

+Cpf

(5.42)

396

P. Gentil

(5.43)

dfZ

dt = ~^n / '

In Eq.(5.42), p is the free hole density in silicon at the Si/Si02 interface. Only two single levels, Ej;^, Etj), are considered and all traps are assumed to be initially in the D" state.

B.

EtA

EtD

O tunnel Fig. 5.21 - Illustration of the various exchange mechanisms which take part in the discharge of the nitride when a large negative charge is stored.

The use of this model and experimental data show important retention properties. The short term decay of the stored charge is govemed by process (1) while the charge loss occurring during long term retention is mainly govemed by processes (2) and (3). Long term retention can be improved in two ways. First, the fabrication process may be optimized in order to reduce the density of (Si/Si02) interface states involved in process (2). This is possible by using a triple-wall oxidation process [101]. Secondly, hole capture can be reduced by controlling the surface potential of silicon. This can be performed by a surface implantation which creates a buried channel and thus reduces the number of holes available at the surface to be captured by the nitride traps in the D° state. However, this work does not take into account the thermal (Poole-Frenkel) emission of electrons trapped in the bulk of the nitride (process (4) of Fig. 5.21). This emission process may be the limiting factor for long term retention, as suggested in Ref. [78]. 7.8. CONCLUSIONS

MONOS and SONOS structures are new and promising for future applications in non volatile memories. Numerous basic phenomena take place in a MONOS/SONOS memory device and modeling is only possible after making many assumptions, especially regarding trap parameters. Recent works about nitride traps reveal the existence of amphoteric traps. This had not be considered in the works reported in Vol. 2 [1] and must now be taken into account.

Multilayer Dielectrics for Memory Applications

397

The presence of amphoteric traps spatially distributed through the nitride layer can explain the main memory properties of MONOS/SONOS devices. The trap parameters are strongly dependent on the fabrication process. By using an adequate fabrication process, a large density of traps at the BO/N interface can be the dominant contribution to the stored charge [102]. Various experimental works [78,94,95,97,100,102,103] have shown that MONOS and SONOS memory devices make it possible to scale down the insulator thickness and therefore to operate at low voltages and to integrate the structure in a VLSI fabrication process. 8. USING THE ONO STRUCTURE AS A DRAM CAPACITOR The Oxide-Nitride-Oxide dielectric multilayer (abbr. ONO) which we have presented and studied in the previous sections allows us to obtain well-controlled V^ variations in transistor devices usable as non-volatile memory EEPROM. It has other useful applications which we examine next. 8.1. T w o OTHER POSSIBLE APPLICATIONS OF THE ONO STRUCTURE

Since 1984 [104], the ONO structure has also been recognized as a promising solution for the storage capacitor of dynamic-random-access-memories (DRAMs) whose basic cell is represented in Fig. 5.22a. ONO films are also of interest when placed between the floating gate and the control gate of a FAMOS (floating-gate avalanche injection metal-oxidesemiconductor) device and as an intermediate dielectric layer in a FLOTOX (floating-gate tunnel oxide) memory device [105,106]. The basic cell of a floating gate device is represented in Fig. 5.22b. In both cases, a DRAM capacitor or FAMOS/FLOTOX transistor, the ONO film is located between two electrodes which have a metallic behavior. In these two applications the ONO structure is not used for its ability to modify the threshold voltage of the device but for its dielectric properties. It is proposed as an altemative to silicon dioxide in such devices. The dielectric constant of silicon nitride (£N=78Q) is greater than that of silicon dioxide (BOX^^BO)This is of interest for obtaining a larger capacitance value for given dimensions or an identical capacitance value when dimensions are scaled down.

9

address transistor

'

gate

floating

. y gate

storage capaciti tunnel or avalanche injection Fig, 5,22 - Different uses of the ONO dielectrics, a) In a DRAM capacitor, b) Between the two gates of a FAMOS/FLOTOX memory transistor.

398

P. Gentil

However, the ONO film has got other advantages which are extremely useful to manufacture memories. Compared with regular silica films, ONO layers exhibit better performance and greater reliability (correlated to a higher breakdown field). Furthermore, the leakage current density observed in ONO films, is much smaller for the same bias and film thickness than in silica films. Most of these properties can be related to the charge transport and charge trapping properties in ONO films. Thus instabilities due to carrier trapping and detrapping in insulators, which are undesirable features in some devices like stable IGFETs, appear to be favorable for other structures, as we show next. 8.2. THE MAIN ADVANTAGES O F THE ONO STRUCTURE

The superiority of ONO films over silica films can be understood from the phenomena and principles which have been presented for the operation of MNOS or MONOS/SONOS nonvolatile memory devices. However, some strong differences exist and must be considered. First, as mentioned above, for DRAM capacitors and floating-gate transistors, the ONO is placed between two electrodes which have a metallic behavior. For technological convenience, these electrodes can be made of a true metal, a metal silicide, a polysilicon, or a monocrystalline substrate. In the latter two cases, doping is assumed to be large enough to avoid significant depletion or inversion. Therefore there exist no potential difference across the electrodes in those structures nor capacitance associated with them. Secondly, we assume, to simplify the explanation, that both oxide layers are thick enough (e.g. > 30 A) to avoid direct tunneling between electrodes and nitride layers. Such structures have been topics of extensive research from the point of view of their technology, physics and modeling as reported in Refs. [108-110]. As reported in Section 6, for such "thick" oxides, the tunneling of electrons from the electrodes by Fowler-Nordheim effect is the dominant carrier injection mechanism in the structure. Because of a higher barrier height, hole transport is negligible. Let us consider a SONOS structure with a heavily doped substrate and a polysilicon electrode (called "gate" below). Its energy band diagram is illustrated in Fig. 5.23. In Fig. 5.23a, the structure is at equilibrium as can be expected from a virgin device under zero gate bias and a nil net charge everywhere in the insulators. • Under a large negative gate bias, the tunneling of electrons occurs from the gate through the triangular-shaped barrier (Fowler-Nordheim effect) of the top-oxide (see Fig. 5.23b). Electrons are trapped at the top-oxide/nitride interface and in the vicinity of this interface in the nitride. • As the charge builds up in the nitride, the band diagram is bent as indicated in Fig. 5.23b. The magnitude of the electric field at the injecting electrode decreases and the injected electron current decreases too. Once a steady state condition is reached, the leakage current in the ONO structure is much less than that obtained on an equivalent structure made of Si02 where the initial electric field at the injecting electrode is almost constant (because there is no significant charge storage in the Si02).

Multilayer Dielectrics for Memory Applications N

O

399

poly Si ("gate")

Fig. 5.23 - Band diagram of an ONO capacitor. a) Case of a virgin device, with no charge and no bias. b) The structure is submitted to a large negative bias, c) After electron injection the bias is brought back to zero.

• When the gate bias is brought back to zero, most electrons remain stored for a long time on the deep nitride traps. By comparing the initial band diagram (see Fig. 5.23a) to that obtained after a large-amplitude and long-duration bias (see Fig. 5.23c), it appears that the structure with the stored charge is less favorable to the injection of further electrons at both electrodes. A much smaller leakage current will thus be obtained for the same biasing conditions during the second and following biases no matter what the sign of the bias is. It can be noted that electron injection from the gate electrode appears here to be a benefit while it constitutes an undesirable effect in the SONOS memory device. Another advantage of the ONO structure is that weak points or defects in each individual layer have a lower probability to extend throughout the full multilayer. In the ONO structure, some defects of the nitride layer can be cured by the thermal oxidation of the nitride during the top oxide process as illustrated in Fig. 5.24a. Furthermore, if weak spots do exist, a local injection will take place, but the greater trapping of electrons which occurs will eventually reduce the leakage current (see Fig. 5.24b). In order to minimize the size of the memory cell in DRAMs, the storage capacitor, in current technology, is built in a trench of the silicon substrate. The oxidation rate at the comers of the trench is lower due to stress during growth, and thus the oxide is thinner [108].

400

P. Gentil

O

N O

a)

b)

Fig. 5.24 ' Origin of the better yield ofONO structures. a) By oxidation of a pinhole in the nitride layer, b) By charging of the nitride at a weak spot of the layers.

This phenomenon is reduced by using the ONO technology since the nitride layer and the top oxide do not experience this thickness reduction. All the above properties contribute to make the ONO technology more suitable for manufacturing DRAM capacitors. 8.3. T H E MODELING OF THE ONO STRUCTURE

Since the phenomena taking place in ONO structures are identical to those of MONOS memory devices, one uses the basic relations described in Section 3 to model them. This includes: • the continuity equations at the interfaces (Eq.(5.10)) and/or in the nitride layer (Eq.(5.9)), • poisson's equation, • the charge transport equation through the oxide layers. As described in sub-section 7.4, in the absence of tunnel oxide layers, the current is of the Fowler-Nordheim type, given by Eq.(5.11) with ?^=l and Eq.(5.12). • The charge transport equation in the nitride It is given by the Poole-Frenkel law (Eq.(5.20)) if trapping is neglected in the nitride bulk (and is thus assumed to occur only at the nitride/oxide interfaces). • The trapping equation It is given by the model of Amett (Eq.(5.27)), (if only electron trapping is considered) or by the models presented in Section 7 (if both electron and hole trapping are considered). This set of equations differs from that of MONOS memory studies because of the different nature of the electrode. The equation system is also solved for a different purpose since for DRAM capacitors, the most important property is the I-V characteristics in steady state conditions or under a slow voltage ramp [110]. In some experiments [106], it has also been shown that hole injection from electrodes cannot be neglected whatever the bias stress may be.

Multilayer Dielectrics for Memory Applications

401

8.4. PERSPECTIVES O F THE ONO STRUCTURE

The ONO multilayer is an excellent dielectric to manufacture DRAM capacitors. Internal phenomena are identical to those of the MONOS memory structure. The modeling of ONO capacitors is therefore achieved by using the same basic relations as in MONOS memory devices although the purpose of the modeling is different. A considerable amount of experimental work is being carried out on ONO structures to obtain better yields and lower leakage currents [111,115]. Altemative structures for DRAM capacitors are also studied, including multilayer dielectric systems, with insulators having a higher dielectric constant than silicon nitride [116,3-6]. 9. CONCLUSIONS AND PERSPECTIVES The purpose of this chapter was to update the material presented in Chap. 16 of Vol. 2 of this series, published in 1989. Since 1989, numerous works have permitted both a large improvement in the technology of the multilayer dielectrics used for non-volatile memory applications and a better knowledge of their physics. Recent works presented in this chapter mainly deal with the trapping properties of the silicon nitride from a theoretical point of view, in connection with the deposition process used. The results which are definitively acquired are: the existence of a large density of memory traps, distributed in the bulk of the nitride, and the capability of trapping both holes and electrons in the bulk of this material. The physical origin of the traps responsible for the memory effect in the nitride is not quite clear yet. However, the most likely candidate seems to be the Silicon Dangling Bond (SDB). It is now well established that the SDB behaves as an amphoteric trap. However, there is also ample evidence that a large variety of traps exists in the nitride as revealed by the measurement of the energy level of these traps. The existence of amphoteric traps must be taken into account in the modeling of the stored charge but this is not sufficient to explain the precise behavior of every MNOS device in the different modes of operation. Numerous and recent experimental works have shown that it is possible to control, to a certain extent, the density and the properties of the traps by choosing the fabrication process of the nitride, by annealing, and by adjusting the process parameters. When the device dimensions are scaled down, regular MNOS memory transistors display severe limitations. A new structure, made up of three dielectric layers, called MONOS, has been proposed. MONOS memories seem to permit the use of thinner insulators and can operate under lower voltages. Furthermore, the three-layer dielectrics, ONO, allows one to fabricate a memory device with a poly-silicon gate. The resulting SONOS memory transistor can be more easily integrated in a classical MOS or CMOS process on the same chip. Several ways of modeling the memory effect of a MONOS (or SONOS) device have been proposed, which take into account the amphoteric traps of the nitride. The set of equations describing such a device is rather complex. Exact solutions to this problem are only obtained by numerical methods. It is not easy to prove the validity of the solutions because they contain a lot of parameters whose values cannot be directly obtained on a single structure. It appears that the adjustment of some of these parameters is, and will remain, an obligation.

402

P. Gentil

Today, the use of two-layer and three-layer dielectrics still appears as a very important solution to the manufacture of EEPROM memories. The ONO structure is very attractive because of its ability to store information in the nitride and because it permits to scale down the device dimensions, to operate at lower yoltages, and to be more easily integrated in a CMOS process. ONO structures are also promising for other applications such as DRAM capacitor and floating gate in EEPROM. In the latter two applications, the multilayer dielectrics allows lower leakage currents and a better yield. The real impact of these new technologies on the mass production of devices will depend on criteria such as repeatability, global yields, reliability and.. .cost. ACKNOWLEDGEMENTS The author wishes to thank G. Barbottin, A. Vapaille and G.C. Messenger for their critical reading of this text and for their useful comments. He is also grateful to D. Brame for her help in translating some items and for the typing of the manuscript and drawings. LIST OF REFERENCES [I] [2] [3] [4] [5] [6] [7] [8] [9] [10] [II] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25]

Gentil P. (1989) Instabilities in silicon devices, Vol.2, edited by G. Barbottin and A. Vapaille, Elsevier science publishers B.V. (North Holland), 659. Balk P. (1975) J. ofElectr. Mat, 4, 635. Marchanda L. and Gurvitch M. (1988), IEEE Tr, on ED. left., 9, 180. Shinriki H., Kisu T., Kimura S.-I., Nishioka Y., Kawamato Y. and Mukai K. (1990) IEEE Tr. on ED., 31, 1939. Kamiyama S., Saeki T., Mori H. and Numasawa Y. (1991) lEDM Tech. Dig., 828. Koyama K., Sakuma T., Yamamichi S., Watanabe H. Aoki H., Ohya S., Miyasaka Y. and Kikkawa T. (1991) lEDM Tech. Dig., 823. Kong S.O. and Kwok C.Y. (1994) Solid State Electr., 37,45. Kong S.O. and Kwok C.Y. (1994) Solid State Electr., 37, 189. Chu T.L., Szedon J.R. and Lee C.H. (1967) Solid State Electr., 10, 897. Doo V.Y. (1966) IEEE Tr. on ED., ED 13, 561. Appels J. A. and Kooi E. (1969) 3rd conf. on Solid State Devices, Exeter Wegener H.A.R., Lincoln A.J., Pao H.C., O'Connel M. and Oleksiak R.E. (1967) lEDM Conf. Washington. Pao H.C. and O'Connel M. (1968) Appl. Phys. Lett., 12, 260. Frohman-Bentchkowsky D. and Lenzlinger M. (1968) lEDM Conf., Washington. Wallmark J.T. and Scott J.H. (1969) RCA Rev., 30, 335. Ross E.C. and Wallmark J.T. (1969) RCA Rev., 30, 366. Ferris-Prabhu A.V. (1972) Appl. Phys. Lett., 20, 149. Ferris-Prabhu A.V. (1972) Phys. Stat. Sol. (a), 11, 81. Pulver M. and Dorda G. (1970) Phys. Stat. Sol. (a), 1, 65. Dorda G. and Pulver M. (1970) Phys. Stat. Sol. (a), 1, 71 Ferris-Prabhu A.V. (1973) IBM J. Res. and Dev., 17, 125. White M.H. and Cricchi J.R. (1972) IEEE Tr. on ED., ED 19, 1280. Ferris-Prabhu A.V. (1976) Phys. Stat. Sol. (a), 35, 243. Ferris-Prabhu A.V. (1977) IEEE Tr. on E.D., ED 24, 524. Ferris-Prabhu A.V., Lubart N.D. and Medve T.J. (1977) Solid State Electr., 20, 74.

Multilayer Dielectrics for Memory Applications [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] [59] [60] [61] [62] [63] [64] [65]

403

Gentil P., Borel J. and Le Goascoz V. (1972) Onde electrique, 52, 427. Card H.C. and Elmasry M.I. (1976) Solid State Electr., 19, 863. Frohman-Bentchkowsky D. and Lenzlinger M. (1969) J. AppL Phys., 40, 3307. Frohman-Bentchkowsky D. (1970) Proc. IEEE, 58, 1207. Svensson C. (1971) Proc. IEEE, 59, 1134. Svensson C. and Lundstrom I. (1970) Electr. Lett., 6, 645. Lundstrom I. and Svensson C. (1972) IEEE Tr. on ED., ED 19, 826. Lundstrom L and Svensson C. (1972) J. Appl. Phys., 43, 5045. Beguwala M. and Gunckel T.L. (1978) IEEE Tr. on ED., ED 25,1023. Maes H. and Van Overstraeten R. (1973) Electr. Lett, 9, 19. Maes H. and Van Overstraeten R. (1976) J. AppL Phys., 47, 664. Yun B.H. (1973) AppL Phys. Lett., 23, 152. Yun B.H. (1974) AppL Phys. Lett., 25, 340. Arnett P.C. and Yun B.H. (1975) AppL Phys. Lett., 26, 94. Neugebauer C.A. and Burgess J.F. (1976) J. AppL Phys., 47, 3182. Lehovec K., Chen C.H. and Fedotowsky A. (1978) IEEE Tr. on ED., ED 25, 1030. Maes H. and Van Overstraeten R. (1975) AppL Phys. Lett., 27, 282. Endo N. (1978) Solid State Electr., 21, 1153. Arnett P.C. (1975) J. AppL Phys., 46, 5236. Lehovec K. and Fedotowsky A. (1977) IEEE Tr. on ED., ED 24, 536. Lehovec K. and Fedotowsky A. (1977) J. AppL Phys., 48, 2955. Lehovec K. (1977) J. Electr. Mat., 6,11. Lundkvist. L., Lundstrom I. and Svensson C. (1973) Solid State Electr., 16, 811. White M.H. and Cricchi J.R. (1972) IEEE Tr on E.D., ED 19, 1280. Ferris-Prabhu A.V. (1977) IEEE Tr on ED., ED 24, 524. Lehovec K. and Fedotowsky A. (1978) AppL Phys. Lett., 32, 335. Williams R. and Beguwala M. (1978) IEEE Tr. on E.D., ED 25, 1019. Efimov V., Kolosanov V. and Sinistra S. (1978) Phys. Stat. SoL (a), 49, 217. Stein H.J., Picraux S.T. and Holloway P.H. (1978) IEEE Tr on ED., ED 25, 1008. Stein H.J. and Wegener H.A.R. (1977) J. Electrochem. Soc, 124, 908. Kapoor V.J., Bailey R.S. and Turi R.A. (1990) J. Electrochem. Soc, 137, 3589. Kapoor V.J., Xu D., Bailey R.S. and Turi R.A. (1992) J. Electrochem. Soc, 139, 915. Peercy P.S., Stein H.J., Doyle B.L. and Picraux S.T. (1979) J. Electron. Mater, 8, 11. Robertson J. and Powell M.J. (1984) AppL phys. Lett, 44, 415. Kirk C.T. (1979) J. AppL Phys., 50, 4190. Ngai K. and Hsia Y. (1982) AppL Phys. Lett., 41, 159. Krick D.T., Lenahan P.M. and Kanicki J. (1988) Phys. Rev. B, 38, 8226. Warren W.L. and Lenahan P.M. (1990) Phys. Rev. B, 42, 1773. Lowe A.J., Powell M.J. and Elliot S.R. (1986) J. AppL Phys., 59, 1251. Warren W.L., Kanicki J., Robertson J., Poindexter E.H. and Mc Whorter P.J. (1993) /. AppL Phys., 74, 4034. [66] Warren W.L. Robertson J. and Kanicki J. (1993) AppL Phys. Lett., 63, 2685. [67] Phillips J.C. (1979) Phys. Rev. Lett., 42, 1151. [68] Fujita S. and Sasaki A. (1985) J. Electrochem. Soc, 132, 398. [69] Park Y.C., Jackson W.K. and Johnson N.M. (1990) J. AppL Phys., 68, 5212. [70] Martin F. and Aymerich X. (1992) Thin solid Films, 221, 147. [71] Anderson P.W. (1975) Phys. Rev. Lett., 34, 953. [72] Kendall E.J.M. (1968) Can. J. Phys., 46, 2509. [73] Chaudhari P.K., Franz J.M. and Acker C.P. (1973) J. Electrochem. Soc, 120, 991. [74] Katsube T., Adachi Y. and Ikoma T. (1976) Solid State Electr. ,19,11. [75] Lundkvist L., Svensson C. and Hansson H. (1976) Solid State Electr, 19, 221. [76] Kapoor V.J. and Bibyk S.B. (1981) Thin Solid Films, 78, 193. [77] Jeppson K.O. and Svensson C. (1979) IEEE J. Solid State Circ, SC14, 723.

404

[78] [79] [80] [81] [82] [83] [84] [85] [86] [87] [88] [89] [90] [91] [92] [93] [94] [95] [96] [97] [98] [99] [100] [101] [102] [103] [104] [105] [106] [107] [108] [109] [110] [Ill] [112] [113] [114]

P. Gentil

Miller S.L., Mc Whorter PJ., Dellin T.A. and Zimmerman G.T. (1990) J. Appl Phys., 67, 7115. Martin F. and Aymerich X. (1991) Micro J., 22, 5. Martin F., Aymerich X., Campabadal F. and Acero M.C. (1992) Thin Solid Films, 213, 235. Hampton F.L. and Cricchi J.R. (1979) Appl. Phys. Lett., 35, 802. Agarwal A.K., Chao C.C, Vogel R.H. and White M.H. (1983) lEDM Tech. Dig., 400. Agarwal A.K. and White M.H. (1985) IEEE Tr. on E.D., ED 32, 941. Ginovker A.S., Gritsenko V.A. and Siatsa S.P. (1974) Phys. Stat. Sol. (a), 26,489. Kuhn M. (1970) Solid State Electr., 13, 873. Hampton F.L. and Cricchi J.R. (1979) lEDM Tech. Dig., 374. Neugebauer C.A. and Burgess J.F. (1976) J. Appl. Phys., 47, 3182. White M.H., Dzimianski J.W. and Peckerar M.C. (1977) IEEE Tr. on E.D., ED 24, 577. Takahashi Y. and Ohnishi K. (1993) IEEE Tr. on E.D., 40, 2006. Minami S. and Kamigaki Y. (1991) IEEE Tr. on ED., 38, 2519. Minami S. and Kamigaki Y. (1991) lEICE Tr. Electr., E74, 875. Chu T.L., Szedon J.R. and Lee C.H. (1967) Solid State Electr., 10, 897. Chen P.C.Y. (1977) IEEE Tr. on ED., ED 24, 584. Suzuki E., Hiraishi H., Ishii K. and Hayashi Y. (1983) IEEE Tr. on ED., ED 30, 122. Minami S. and Kamigaki Y. (1993) IEEE TR. on ED., 40, 2011. Yatsuda Y., Hagiwara T., Minami S., Kondo R. and Uchida K. (1982) Jpn J.Appl. Phys., 21, 85. Chao C.C. and White M.H. (1987) Solid State Electr., 30, 307. Libsch F.R. and White M.H. (1990) Solid State Electr., 33, 105. Roy A. and White M.H. (1991) Solid State Electr., 34, 1083. Hu Y. and White M.H. (1993) Solid State Electr., 36, 1401. Yoon S. and White M.H. (1990) J. Electron. Mater., 19, 487. Suzuki E. and Hayashi Y. (1986) IEEE Tr. on E.D., ED 33, 214. Suzuki E., Miura K., Hayashi Y., Tsay R.P. and Schroder D.K. (1989) IEEE Tr. on E.D., 36, 1145. Watanabe T., Menjoh A., Ishikawa M. and Kumagai J. (1984) lEDM Tech. Digest, 232. Manzini S. and Volonte F. (1985) J. Appl. Phys., 58, 4300. Manzini S. and Queirolo G. (1987), Solid State Electr., 30, 587. Nariani S.R., Gabriel C.T. and Hu C. (1994), Solid State Tech., 37, 79. Honlein W. and Resinger H. (1989), Appl. Surf. Sc, 39, 178. Spitzer A. and Baunach R. (1989), Appl. Surf. Sc, 39, 192. Baunach R. and Spitzer A. (1989), Appl. Surf. Sc, 39, 200. Naito Y., Hirofuji Y., Iwasaki H. and Okada H. (1990), J. Electrochem. Soc, 137, 635. Tanaka H., Uchida H., Ajioka T. and Hirashita N. (1993) IEEE Tr. on E.D., 40, 2231. Mazoyer P., Mondon F., Martin F., Guillaumot B. and Hartmann J. (1993) ESSDERC '93 Proc, 595. Yoon G.W., Joshi A.B., Kwong D.L., Mathews V.K., Thakur R.P.S. and Fazan P.C. (1994), IEEE Tr. on ED., 41, 347. [115] Ma Y., Yasuda T. and Lucovsky G. (1994), Appl. Phys. Lett., 64, 2226. [116] Nishioka Y., Kimura S., Shinriki H. and Mukai K. (1987) J. Electrochem. Soc, 134, 410.

INSTABILITIES IN SILICON DEVICES Silicon Passivation and Related Instabilities G. Barbottin and A. Vapaille (Editors) © 1999 Elsevier Science B.V. All rights reserved.

405

CHAPTER 6

CHARGE PUMPING TECHNIQUES Their use for diagnosis and interface states studies in MOS transistors by J.L. AUTRAN(i-2), B. BALLANDd) and G. BARBOTTINC^)

Key items MOS transistors Charge-pumping (CP) phenomena Interface traps CP current Two-level CP method Spectroscopic CP method Three-level CP method Interface traps characterization Determination of Dj^ (E) Determination of Dj^ (x) Determination of a (E) Explorable energy range Emission modes Submicrometer devices (1) Laboratoire de Physique de la Matiere Institut National des Sciences Appliquees 20, avenue Albert Einstein 69621 Villeurbanne - France

(2) During the writing of this review paper, Centre d'Etudes de Bruyeres-Le-Chdtel with CEA-DAM BP 12 91680 Bruyeres-le-Chatel - France

(3) AEROSPATIALE Service YY/ST Route de Verneuil 78130 Les Mureaux - France

406

J,L, Autran et aL

Abstract of Chapter 6, Charge pumping techniques. Their use for diagnosis and interface states studies in MOS transistors The charge pumping (CP) technique is a powerful tool used to characterize the traps of the Si-Si02 interface in submicrometer MOS devices. It is based on the exploitation of a repetitive process whereby majority carriers coming from the substrate recombine with minority carriers previously trapped in interface states, when the MOSFET is submitted to well-chosen biasing cycles. By taking into account the emission processes which control the exchange of charges at the interface, information concerning the capture cross-section and the energy distribution of the interface states can be obtained. In this chapter, we describe various charge pumping techniques and their applications. We first show that a "pumping current" is detected under certain circumstances in a MOS transistor and we present the fundamentals of the charge pumping technique. We then describe the early version of the two-level (2CP) technique. The first-order modeling is not sufficient to explain all the experimental results found. We thus introduce a more thorough analysis of the various physical phenomena which take place when a triangular, trapezoidal or sinusoidal voltage pulse is applied to the gate electrode. We then review the experimental parameters which affect the CP response of the MOS transistor (the frequency and the profile of the gate pulse, the reverse bias of the source and drain junctions, the device temperature) and we indicate the accuracy and the limitations of the classical 2CP method. We show next how the 2CP method enables us to calculate the average density of the interface states and their average cross-section . By adjusting some experimental parameters we also gain access to the energy distribution of the states Dn (E) and to their spatial distribution Djf (x). With the spectroscopic technique, we explain that it is possible to define an energy window by exploiting a differential signal and that D^ (E) and a (E) are accessible by performing a temperature sweep. The introduction of a third voltage level in the gate pulse gives access to the same parameters as the 2CP but requires less simplifying assumptions. We show that the 3CP and its variants are powerful tools to determine the Di( (E) and a (E) distributions. We end this chapter by describing some clever applications of the 2CP method: characterization of interfaces (degraded homogeneously or not) characterization of border traps (by using a frequency sweep) and characterization of grain boundary traps in polysilicon thin-film transistors. Given the shrinking dimensions of elementary transistors, the various CP techniques are to date the only techniques which make it possible to characterize the Si-SiO2 interface directly in the transistor itself They thus have a promising future. Resume du chapitre 6, Les techniques de pompage de charge. Leur utilisation comme outil de diagnostic et d^etude des etats d*interface dans les transistors MOS La technique de pompage de charge est un puissant outil pour la caracterisation des pieges de I'interface Si-Si02 dans les composants MOS submicroniques. Elle est fondee sur I'exploitation du phenomene repetitif de recombinaison des porteurs majoritaires venant du substrat et des minoritaires qui sont pieges dans les etats d'interface quand le transistor MOS est soumis a un cycle de polarisation bien choisi. En tenant compte des differents mecanismes d'emission qui controlent les echanges de charge a I'interface, elle permet d'obtenir des informations relatives aux sections efficaces de capture et a la densite des etats de I'interface. Dans ce chapitre, nous decrivons differentes techniques de pompage de charge et leurs applications. Nous montrons d'abord I'existence d'un "courant pompe" dans un transistor MOS sous certaines conditions et nous presentons les principes fondamentaux de la technique du pompage de charge. Nous decrivons I'experience originale de la premiere version, dite "technique a deux niveaux". Le modele theorique du premier ordre etant insuffisant pour expliquer I'ensemble des resultats experimentaux, nous proposons une analyse plus precise des differents phenomenes physiques qui s'etablissent quand une impulsion de tension de profil: trapezoidal, triangulaire ou sinusoidal, est appliquee sur la grille. Apres avoir passe en revue les parametres experimentaux qui influent sur la reponse en pompage de charge des transistors MOS (la frequence et le profil de I 'impulsion de tension appliquee sur la grille, les polarisations inverses des jonctions de source et de drain, la temperature), nous indiquons les limites et la precision de la methode "classique".

Charge Pumping Techniques

407

Nous montrons ensuite comment la technique a deux niveaux (2CP) permet de calculer la densite moyenne des etats d'interface et leur section efficace (moyenne) de capture . L'ajustement de certains parametres experimentaux permet egalement d'acceder a la distribution energetique D// (E) et spatiale Dit (x) des etats. Avec la technique spectroscopique, nous montrons qu 'il est possible de definir une fenetre en energie, en exploitant un signal differentiel, et que la distribution energetique Da (E) des etats d'interface et celle de leurs sections efficaces de capture a (E) sont accessibles grace a un balayage en temperature. L'introduction d'un troisieme niveau de tension dans Vimpulsion de grille permet d'acceder aux memes parametres qu 'avec la technique a deux niveaux mais sans avoir besoin de faire autant d 'hypotheses simplificatrices. Nous montrons que la technique du pompage de charge a trois niveaux ainsi que ses diverses variantes sont des outils puissants pour determiner les courbes Du (E) et a (E). Nous terminons ce chapitre en decrivant quelques applications originales de la technique a deux niveaux : la caracterisation des interfaces degradees de maniere homogene ou non lors d'un vieillissement, la caracterisation des etats lents (en pratiquant un balayage en frequence) et la caracterisation des pieges aux joints de grain dans des transistors a film mince de silicium polycristallin. Compte tenu de la taille sans cesse decroissante des compos ants elementaires, la technique de pompage de charge reste a I 'heure actuelle la seule qui permette encore de caracteriser I 'interface directement dans des transistors tres fortement submicroniques. Elle est done promise a un bel avenir. Zusammenfassung zu Kapitel 6: Ladungspump-Methoden: Ihr Nutzen fur Diagnose und Untersuchungen von Phasengrenz-Zustdnden in MOS-Transistoren Die Ladungspump-Methode ist ein wichtiges Hilfsmittel zur Charakterisierung von Zustanden der Si-Si02Phasengrenze in Submikrometer-MOS-Bauelementen. Sie basiert auf einem sich wiederholenden Frozep, bei dem Majoritatsladungstrager, die aus dem Substrat zufliessen, mit Minoritatsladungstrdgem, die in Phasengrenzzustanden eingefangen worden sind, rekombinieren, wahrend der MOSFET an einem definierten Arbeitspunkt vorgespannt ist. Aus dem Emissionsvorgang, der den Ladungsaustausch an der Phasengrenze regelt, erhdlt man die Information Uber Einfangquerschnitt und die energetische Verteilung der Phasengrenzzustande. In diesem Kapitel werden verschiedene Ladungspump-Methoden und ihre Anwendung vorgestellt. Wir zeigen zundchst, daj3 ein Pump-Strom in einem MOS-Transistor unter bestimmten Umstdnden gemessen werden kann, und stellen die Grundlagen der Ladungspump-Methode dar. Danach beschreiben wir die ursprUngliche Version der Zweistufen- (2CP-) Methode. Die Simulation erster Ordnung genUgt nicht zur Beschreibung aller experimentellen Befunde. Wir fuhren daher eine tiefergehende Analyse der verschiedenen physikalischen Erscheinungen durch, die bei Anlegung dreieckformiger, trapezformiger oder sinusartiger Pulse and den Gate-Kontakt auftreten. Wir beschreiben dann die experimentellen Parameter, die die CF-Antwort des MOS-Transistors die Frequenz und (die Form des Gate-Pulses, die Sperrspannung an Source- und Drain-Ubergangen, die Temperatur des Bauteils) beeinflussen und wir schdtzen die Genauigkeit und die Grenzen der klassischen 2CP-Methode ab. Als ndchstes zeigen wir, wie die 2CP-Methode die mittlere Dichte der Phasengrenz-Zustdnde und deren mittleren Einfangquerschnitt zu ermitteln gestattet. Durch geeignete Wahl einiger experimenteller Parameter hat man auch Zugriffzur energetischen Verteilung der Phasengrenz-Zustdnde Dj^(E) und ihrer ortlichen Verteilung Mit der spektroskopischen Methode erkldren wir, dapes moglich ist, ein Energie-Fenster zu definieren, indem man ein Differenzsignal anlegt, unddapDi^(E) und <j(E) aus einem Temperaturscan extrahiert werden konnen. Die Einfuhrung eines dritten Spannungspegels fur den Gate-Puls ergibt den gleichen Parameter-satz wie die 2CPMethode, vermeidet aber vereinfachende Voraussetzungen. Wir zeigen, dap die 3CP-Methode und ihre Varianten ein wichtiges Hilfsmittel zur Bestimmung der Djf(E)- und a(E)-Verteilungen ist. Wir beenden das Kapitel mit der Beschreibung einiger scharfsinniger Anwendungen der 2CP-Methode: Charakterisierung von Phasengrenzen, gleichformig oder lokal degradiert, Bestimmung von border-traps (mit Hilfe eines Frequenz-Scans), sowie die Charakterisierung von Komgrenzen-Fehlem in poly-Si-DUnnfdm-Transistoren. Angesicht der Verkleinerung der Dimensionen einzelner Transistoren stellen die unterschiedlichen CP-Methoden heute die einzige Methode dar, die die Charakterisierung der Phasengrenze am Transistor selbst moglich machen. Si haben daher eine vielversprechende Zukunft.

408

J,L, Autran et aL

Chapter 6 : Charge pumping techniques. Their use for diagnosis and interface states studies in MOS transistors Table of contents List of symbols and abbreviations used 1. Introduction 2. The charge pumping phenomenon in MOS transistors 2.1. The basic experiment 2.2. A qualitative interpretation of the charge pumping phenomenon 2.2.1. How an inversion layer builds up or disappears 2.2.2. The origin of the charge pumping effect 2.3. A first-order model of the pumped current 2.3.1. The geometric current component 2.3.2. The current component due to interface states 2.3.3. Expression of the total pumped current 2.4. An early approach to the two-level charge pumping method 2.4.1. First version: VQL = V^cc and AVQ increases 2.4.2. Second version: VQH "= Vj^v and AVQ increases 2.4.3. Third version: AVQ remains constant but VQL increases 2.4.4. Possible applications of the second version 2.5. Conclusion on the first-order theory 3. A more comprehensive analysis of the charge pumping phenomenon 3.1. Some recent theories on charge pumping 3.2. Definition of the waveform applied to the gate 3.3. The different processes occurring during one cycle 4. Calculation of the charge pumping current 4.1. Electron and hole contributions to the charge pumping current 4.2. The demarcation emission levels 4.3. Validity of the standard model 4.4. The net charge pumping current 5. Influence of different parameters on the charge pumping current 5.1. Influence of the pulse characteristics 5.1.1. Influence of the pulse frequency 5.1.2. Influence of the pulse shape 5.1.3. Influence of the pulse amplitude 5.1.4. Inversion step duration versus trapping time constant

Charge Pumping Techniques

5.2. Dependence on the source-substrate and drain-substrate reverse bias 5.3. Dependence on temperature 5.4. Discussion: limits and sensitivity of the 2CP method 5.4.1. Limits 5.4.2. Sensitivity 6. Determination of the interface trap parameters 6.1. Calculation of Dj^ and a using I^p curves 6.1.1. Calculation using trapezoidal pulses 6.1.2. Calculation using triangular pulses 6.2. Determination of the trap energy distribution 6.3. Determination of the spatial distribution of interface states 6.3.1. General principle 6.3.2. Method based on the symmetrical modulation of the effective channel length 6.3.3. Method based on the asymmetrical modulation of the effective channel length 7. The spectroscopic charge pumping technique 7.1. Principle 7.2. Spectroscopic signals 7.3. Determination of the trap energy distribution 7.4. Determination of the capture cross-sections 7.5. Sensitivity and accuracy of the spectroscopic method 8. The three-level charge pumping technique 8.1. Definition of the three-level waveform 8.2. Theory of the three-level charge pumping method 8.3. Expression of the charge pumping current 8.4. Validity of the model 8.4.1. The emission time constant window 8.4.2. Limits on the explorable energy range 8.5. Experimental limitations 9. A review of various three-level charge pumping techniques 9.1. First method 9.2. Second method 9.3. Third method 9.4. Fourth method 9.4.1. Principle 9.4.2. Determination of the interface state density 9.4.3. Determination of the capture cross-sections

409

410

y.L. Autran et aL

9.5. Numerical simulations 9.5.1. Analysis of the emission and capture regimes 9.5.2. Basic equations 9.5.3. Simulation results 10. Examples of applications of charge pumping techniques 10.1. Application to the study of a uniform degradation 10.1.1. Degradation of MOS transistors 10.1.2. Degradation of EEPROM memories 10.2. Application to the study of a non-uniform degradation 10.2.1. Case of an n-channel MOSFET 10.2.2. Case of a p-channel MOSFET 10.2.3. An experimental case 10.3 Application to the detection and characterization of border traps 10.3.1. Definition 10.3.2. Characterization using the standard CP technique 10.3.3. Evaluation of the border trap density using the dual-transistor technique 10.4. Application to the evaluation of grain boundary traps in polysilicon TFTs ' 10.4.1. Typical CP characteristics in polysilicon TFTs 10.4.2. Density of grain boundary traps 11. Conclusion Acknowledgements List of references

Charge Pumping Techniques

411

LIST OF SYMBOLS AND ABBREVIATIONS USED* AG Aeff

Cox Csc Dit , Dit Dit(E)

nfi m^ F.m-2 F.m-2 J-l.m-2 J-l.m-2

Ei, Ej^bulk Eem,e

J-l.m-2 J-l.m-2 J,eV J,eV J,eV J,eV

Eem,h

J^^V

EG

J,eV J,eV J,eV J,eV J,eV J,eV J,eV J,eV J,eV J,eV

Dit(^s)

E* Ec

Ep Ep.acc EF,inv Epd EpM

Epn Et Ev Es AE f ICP(VGL)

Icp(V3) ^cp Icp,max IDS

Igeom lit Isub

k

J,eV Hz A A A A A A A A J.K-i m

Gate area of the MOS transistor Effective area of the channel (Aeff = WxLeff) Gate oxide capacitance expressed per unit area (Cox = Box/tox) Space charge capacitance (in the semiconductor substrate) Interface trap density Average interface trap density Interface trap density as a function of energy Interface trap density as a function of surface potential Energy level explored by the energy window Lower edge of the conduction band (in Si or Si02) Intrinsic Fermi-level energy, resp. in the silicon bulk Energy level reached at the end of the non-steady-state emission of electrons Energy level reached at the end of the non-steady-state emission of holes Energy bandgap (in Si or Si02) Fermi-level energy (in metal or in silicon) Fermi-level energy in the accumulation mode Fermi-level energy in the inversion mode Dynamic quasi-Fermi level Fermi-level energy in the metal electrode Quasi-Fermi level for electrons trapped at the interface Energy level of an interface trap Upper edge of the valence band (of Si or Si02) Energy level reached during the intermediate step in the 3CP method Energy range explored by the voltage sweep Frequency of the gate pulses Variations of the CP current in the two-level method Variations of the CP current in the three-level method Charge pumping current Maximum charge pumping current Drain-source current Geometric component of the charge pumping current Component of the CP current due to interface states Total substrate current Boltzmann constant (k = 1.38x10-23 j-K-l) Channel length of the transistor, effective channel length

L,Leff * Only those symbols which appear more than once in the text have been listed.

412

J,L. Autran et al,

Ls, L D

m

NA,ND

ns

m-3 mr^ m-2 m-3

Hi Ps

m-3 m-3

q Qcp,e

C C.in-2

Qcp,h

C.m-2

Vem.e

C.m-2

Qem,h

C.m-2

Qit Qox Qn,Qp

C.m-2 C.m-2 C.m-2

Qsc

C.m-2

Qsub QT Qt Sf Sr T Tp tacc

C.m-2 C.m-2 C.m-2 A A K s s

t3 tem,e tem,h tf tfl, tf2 tinv

s s s s s s

Nsub Nit

Width of the space charge regions of the source-substrate and drain-substrate junctions Concentration of acceptor-Uke, resp. donor-like, doping atoms Concentration of doping atoms in the substrate Number of fast interface traps per unit area Concentration of free electrons in the conduction band at the surface of the semiconductor substrate Intrinsic carrier concentration Concentration of free holes in the valence band at the surface of the semiconductor Absolute value of the electronic charge (q = 1.6x10-19 Q Variation in the amount of charge trapped at the interface, due to electron trapping, expressed per unit area Variation in the amount of charge trapped at the interface, due to hole trapping, expressed per unit area Variation in the amount of charge trapped at the interface, due to electron emission, expressed per unit area. Variation in the amount of charge trapped at the interface, due to hole emission, expressed per unit area Density of charge trapped in interface traps, expressed per unit area Density of the fixed oxide charge, expressed per unit area Density of free electrons, resp. free holes, in the inversion layer, expressed per unit area Density of the space charge in the Si substrate, expressed per unit area Total charge flowing to the substrate, expressed per unit area Net pumped charge, expressed per unit area Charge trapped on grain boundary traps, expressed per unit area Spectroscopic CP signal obtained for constant fall time Spectroscopic CP signal obtained for constant rise time Absolute temperature Period of the waveform applied to the gate Duration of the gate pulse during which the substrate is in accumulation Duration of the intermediate (or third) level of the gate pulse Non-steady-state emission time for electrons Non-steady-state emission time for holes Fall time of the gate pulse Consecutive fall times used in the SCP technique Duration of that step of the gate voltage waveform during which the substrate is in inversion

Charge Pumping Techniques

413

^n^^p

nfi nfi

, a

m^

Rise time of the gate pulse Consecutive rise times used in the SCP technique Gate oxide thickness Stress time Time at which saturation occurs in the 3CP experiment when the duration of the intermediate gate voltage level increases Gate voltage which brings the substrate in strong accumulation Source-substrate, resp. drain-substrate, reverse bias Value of the intermediate voltage in the 3 CP method Different values of the intermediate gate voltage level Platband voltage Applied gate voltage Upper level of the gate voltage pulse Lower level of the gate voltage pulse Amplitude of the gate voltage pulse (AVQ = VQH - VGL) Gate voltage which brings the substrate in weak inversion Gate voltage which brings the substrate in strong inversion Gate voltage which brings the surface potential at midgap Reverse voltage applied equally to the source-substrate and drainsubstrate junctions Threshold voltage of the MOS transistor Thermal velocity of carriers Channel width of the MOS transistor Characteristic parameter for a triangular pulse (a = tj-xf) Fraction of free carriers located under the gate which recombine in the bulk of silicon Surface potential of the silicon substrate Surface potential reached during the intermediate step in the 3CP method Surface potential reached when Vacc is applied Potential in the silicon bulk (q^B = Ei^bulk - Epd) Potential linked to the quasi-Fermi level at the interface Surface potential reached when Vinv is applied Total sweep of the surface potential Capture cross-section of interface traps as a function of energy Capture cross-section for electrons, for holes Geometrical mean value of the capture cross-sections

£0

F.m"l

Permittivity in vacuum

tr trb tr2 tox tstress tsat

s s m s s

VMG VR

V V V V V V V V V V V V V

VT

V

Vth

W

m.s"l m

a

-

Y

-

¥s

V V

Vacc VS.VD V3 V3I, V32 VFB VG VGH VOL AVG VH Vinv

^3 ^acc ^PB *PFn linv

A»Ps

a(E)

V V V V V

y.L. Autran et al.

414 8ox, Bsi Te

F-m-1 s

'^em,e9 '^em,h

^

CB,VB CP C-V 2CP 3CP DC DLTS EEPROM I-V GBT QSM MOS MOSFET SCP SRH TFT

Permittivity of silica, of silicon Emission time constant of a trap Emission time constant for electrons, for holes Capture time constant for electrons, for holes Conduction Band, Valence Band Charge Pumping (current or phenomenon) Capacitance-Voltage characteristic (e.g. of a MOS structure) 2-level Charge Pumping 3-level (staircase) Charge Pumping Direct Current Deep Level Transient Spectroscopy Electrically Erasable Progranmiable Read Only Memory Current -Voltage characteristic (e.g. of a MOS structure) Grain Boundary Trap Quasi Static Method (or Measurement) Metal-Oxide-Semiconductor (structure or transistor) Field Effect Transistor in the MOS technology Spectroscopic Charge Pumping Schockley-Read-Hall (formalism and notation) Thin-Film Transistor

Charge Pumping Techniques

415

1. INTRODUCTION In Chapter 12 of Vol. 2 of this book series [1] various electrical techniques, used to measure state densities at the Si-Si02 interface directly in metal-oxide-semiconductor (MOS) devices (capacitors or transistors), were described. These methods included the quasi-static (QSM) and capacitance-voltage (C-V) measurements. Deep Level Transient Spectroscopy (DLTS), the weak-inversion method and 1/f noise measurements. However, many of these techniques have unwelcome limitations. For example, the use of the low frequency C-V technique introduces a large error in the interface trap density (Djt) results when band bending brings the structure either close to accumulation or close to inversion. The Charge Pumping (CP) technique is based on the selective recombination of carriers previously trapped in interface states. By taking into account the various emission processes which participate in the charge exchange at the interface, information conceming the capture cross-section and the energy distribution of the interface states can be obtained. A major advantage of the CP technique is that measurements are carried out directly on MOS transistors, as opposed to other techniques (e.g. C-V) which preferentially use capacitors ; CP measurements thus allow a direct correlation between interface quality in the device and changes in fabrication process parameters. In the last ten years, the CP technique has come into wide use to characterize, both qualitatively and quantitatively, interface states in Field Effect Transistors in the MOS technology (MOSFETs). The prime reason for this is that the technique is easy to implement and has excellent accuracy and resolution: one can detect interface state densities as low as 10^ eV"l cm"^. The CP technique appears currently to be the only reliable technique capable of evaluating interface states in small-size MOS transistors with an excellent accuracy and sensitivity. It has thus become an indispensable tool for the development of present and future Very Large Scale Integration (VLSI) processes. In this chapter, various charge pumping techniques and their main applications are described. In Section 2, we review the basic principles of the two-level charge pumping (abbr. 2CP) technique. We show that, under certain conditions, a "pumped current" is measured in the substrate of a MOS transistor during the rise phase and fall phase of a highfrequency voltage pulse applied to the gate. For an n-channel transistor, this current is due to substrate holes which recombine, either with free electrons contained in the inversion layer or with electrons re-emitted by interface traps. Three versions of the two-level CP technique are described. A first-order theory lets us establish simple expressions for the two components of the pumped current. Because of its shortcomings, this simple theory has been improved upon as described next. Recent models give a comprehensive picture of the various emission, capture and recombination processes which take place during a full CP cycle. In Section 3, we consider two types of gate pulse (triangular and trapezoidal) and we establish the expressions of the charge exchange processes for all six phases of the CP cycle (accumulation, accumulation to depletion, depletion to inversion, inversion to depletion, depletion to accumulation).

416

y.L. Autran et al.

The above results are used in Section 4 to derive a "standard expression" of the CP current. For that matter we define two (demarcation) energy levels which, in the case of an n-channel MOSFET, correspond respectively to the end of the (non-steady-state) hole emission during the rise phase of the gate signal and to the end of the (non-steady-state) electron emission during the fall phase of the signal. We show that if the rise and fall times of the signal exceed - 10-'7 s, the charge pumping current takes a rather simple form which gives us access to the average density of interface traps and to their capture cross-section. In Section 5, we examine the influence of various parameters on the amplitude of the pumped current, namely: the shape, the frequency and the amplitude of the gate signal, the magnitude of the reverse bias applied to source and drain, and temperature. We also show how the measurement parameters, as well as the characteristic parameters of the transistor, limit that portion of the energy bandgap which can be explored and the sensitivity of the method. We show in Section 6 how the CP current obtained by means of the "classical" 2CP technique or its variants, enables us to calculate the average density of interface traps and their average cross-section. It is also possible to calculate the energy distribution of the traps in a wide portion of the bandgap by adjusting the rise time and/or the fall time of the gate signal. Finally, we show that, by modulating the effective channel length of the transistor, we can determine the spatial distribution of the interface traps along the channel. This modulation is obtained by adjusting the source-substrate and drain-substrate reverse bias simultaneously or separately. The so-called spectroscopic charge pumping technique and its variants are described in Section 7. In this method, we exploit a signal Sj. (or Sf) which is the difference between two CP currents measured consecutively and for which only the rise times (or the fall times) of the trapezoidal gate signal differ. This spectroscopic signal defines an "energy window". By varying the temperature of the transistor we can raise (or lower) this energy window in the bandgap. The energy distribution of the interface traps can thus be determined over a much larger part of the forbidden bandgap than with the classical 2-level technique. Likewise the energy distribution of the capture cross-section can be theoretically assessed. Half of the bandgap can be explored by exploiting the variations of Sj. (T), and the other half by exploiting Sf(T). The introduction of a third voltage level in the trapezoidal gate signal adds new possibilities to the 2CP technique. We show in Section 8 that if, after the inversion (or the accumulation) level, we temporarily apply an intermediate level which brings the structure in weak inversion, we can explore part of the gap without the need for simplifying assumptions. Both the energy distribution of the trap density and that of the capture cross-section can thus be obtained. Since the three-level signal is technically difficult to generate, the possibilities of this so-called 3CP or "staircase" CP technique are limited. Although the 3CP can only explore part of the bandgap and enables us to study only those traps which are inside an emission window, it represents the most advanced charge pumping technique to date.

Charge Pumping Techniques

417

In Section 9, we review some variants of the 3CP technique and we give some experimental results. The 3CP technique can be performed at varying temperatures or the third level can be chosen to position the surface potential of the substrate at midgap. A last variant consists in letting both the position of the third level and its duration vary, and in exploiting the differential signal. All these variants of the 3CP make possible the determination of Dit(E) and a(E) over a more or less wide energy range. We then present numerical simulations which corroborate the assumptions we made while establishing the basic equations of the 3CP method. These simulations permit also to take into account, depending on the position of the intermediate level and on the doping concentrations, various modes of carrier emission or carrier capture. We review in Section 10 several other applications of the 2CP technique. We show that this CP technique is the ideal tool to study the degradation of the Si-Si02 interface, whether this degradation is homogeneous (e.g. following an irradiation or a Fowler-Nordheim injection) or non-homogeneous (e.g. following hot electron injection from the drain). We show that the 2CP technique not only enables us to measure variations in Djt but also variations in the amount of trapped charge above the channel (case of EEPROM devices). The 2CP technique allows us also to detect and characterize border traps, i.e. traps located inside the silica layer but close enough to the substrate to be able to exchange carriers with silicon (but with long time constants). In this case the 2CP curves are recorded for decreasing frequencies. The 2CP method has also been used to study grain boundary traps in Polysilicon Thin-Film Transistors (PTFT). This chapter shows that, as dimensions of elementary devices keep shrinking, the CP technique remains virtually unchallenged to study the channel area in small-size transistors. The CP technique and its many variants should be techniques of choice for many years to come. 2. THE CHARGE PUMPING PHENOMENON IN MOS TRANSISTORS The term "charge pumping" was introduced by Brugler and Jespers [2] in 1969. These authors showed the existence of a DC "pumped current" in the substrate of a MOS transistor whose surface is periodically switched from accumulation to inversion by square gate pulses. We present next a first (mostly phenomenological) description of this phenomenon and show how the measurement of the pumped current gives us access to some properties of the interface. 2.1. THE BASIC EXPERIMENT

The basic measurement setup is illustrated in Fig. 6.1, in the case of an n-channel MOS transistor. The gate of the transistor is connected to a pulse generator. Trapezoidal or triangular pulses with adjustable rise and fall times are periodically applied to the gate of the device while the source and the drain are connected together and maintained at a given reverse bias voltage VR with respect to the substrate.

418

/.L. Autran et aL

Switching the silicon surface from accumulation to inversion, with a sufficiently large pulse amplitude, gives rise to a DC substrate current, which can be monitored with a picoanmieter (or electrometer).

m

PULSE GENERATORl

SCOPE

Jh

SOURCE VR-

GATE

SUBSTRATE P-type

^n

DRAIN Fig. 6.1 - Schematics of the experimental setup used for charge pumping measurement, as introduced by Brugler and Jespers [2].

ELECTROMETER

• When no gate pulse is applied, the anmieter indicates a small positive substrate current: it corresponds to the leakage current of the reverse-biased source-substrate and drain-substrate junctions. Because source and drain are at the same bias, no current flows from source to drain. • When the surface of the p-type substrate is periodically switched from accumulation to inversion by means of positive gate pulses, one observes that the substrate current is reversed and becomes negative. Its magnitude increases with the pulse frequency in a linear fashion as long as leakage effects are negligible. • The fact that the amplitude of the DC substrate current varies linearly with pulse frequency is clearly indicative of a "pumping action" whereby a fixed amount of charge is measured at each gate pulse. Since no DC current can flow through the oxide, this charge must be injected across the source-substrate and drain-substrate junctions. A current called Charge Pumping (CP) current is thus shown to flow in the (forward) direction opposite to the leakage current of the junctions, even though these junctions are reverse biased. • For a pumped current to be measured, one finds that the amplitude of the gate pulse must exceed a "threshold" value. This measured threshold amplitude is in good agreement with that measured in MOS capacitors to switch the substrate from accumulation to inversion. As the gate pulse amplitude increases, a sharp rise in CP current is observed, followed by a saturation. • A strong dependence of the pumped current on the geometric characteristics of the transistor is also observed: the current is found to be roughly proportional to the area of the gate.

Charge Pumping Techniques

419

2.2. A QUALITATIVE INTERPRETATION OF THE CHARGE PUMPING PHENOMENON The above basic charge pumping experiment [2] suggests that the CP phenomenon is related to the charge stored under the gate electrode at each cycle. The pumped current may be interpreted as being due to the fact that a fraction of the total charge stored under the gate electrode is lost through recombination with majority carriers coming from the substrate at the end of each cycle. This is confirmed by the fact that the CP current is a linear function of the gate pulse frequency and is proportional to the gate area of the device. 2.2.1. How an inversion layer builds up or disappears To explain how charge pumping occurs, it may be useful to first briefly recall how an inversion layer builds up in a MOS device and how it later disappears. Two cases must be distinguished depending on whether a junction capable of injecting minority carriers is available nearby. • In the absence of junction (and without illumination) The sudden application of a positive and large enough DC gate voltage to a p-doped MOS capacitor generally results in a situation of non-equilibrium in which no inversion layer exists at first but only a deep depletion layer extending far beyond its steady-state depth (see e.g. Chap. 4 of Vol. 1 [1]). Then, as time increases, various sources of minority carriers contribute to the formation of the inversion layer, while the depth of the depleted region decreases. These minority carriers are due to: surface generation, generation in the depleted region, diffusion from the bulk, within a diffusion length, towards the depleted regions, followed by a rapid sweep across the depleted region. However, all these generation processes are slow, typically with time constants ranging from a few milliseconds to a few seconds. • When a junction is present If a junction is located nearby, the transient behaviour of a MOS device is quite different from that described above, since the n-doped region is a source of minority carriers which can be supplied to the inversion layer of the p-substrate. When a DC gate voltage leading to inversion is applied, the potential barrier across the junction is reduced below its equilibrium value for a very short time. This allows a large flow of free electrons from the n-region to the p-region in order to restore equilibrium. The inversion layer can now build up fast and it seems a reasonable assumption to consider that the contribution of the substrate to this buildup may be completely neglected. 2.2.2. The origin of the charge pumping effect In the following discussion, we shall only consider the case of an n-channel MOS transistor (p-type substrate). To discuss the case of p-channel structures, the majority- and minoritycarrier types, as well as the polarity of all applied and internal voltages, would have to be reversed. The existence of a pumped current can be understood as follows.

420

/.L. Autran et aL

• When the transistor is pulsed into inversion (i.e. when gate voltage V Q is larger than threshold voltage VT), the surface of the p-substrate becomes first deeply depleted and the electrons flow from the source and drain regions into the channel. Some of them get captured by the surface states, while others remain free in the inversion layer. • When the gate pulse is removed or when the gate pulse drives the surface back into strong accumulation (i.e. V Q is now smaller than the flatband voltage VFB). the inversion layer disappears. Part of the mobile electrons drift back to the source and drain regions under the influence of reverse bias voltage VR. The mobile electrons which have not drifted yet toward source and drain and the electrons previously trapped in the interface states recombine with the holes coming from the substrate, giving rise to a substrate (pumped) current. 2.3. A FIRST-ORDER MODEL OF THE PUMPED CURRENT

Experimental evidence indicates that the CP current can be split into two components depending on whether recombination occurs via interface traps (surface states) or directly in the substrate bulk. We may therefore express the net pumped charge Qj per unit area and per gate pulse as follows: QT=rQn'^Qit

(6.1)

where Qn is the charge corresponding to the free electrons of the inversion layer, y is the fraction of those (free electrons) which recombine in the bulk and Qit is the charge due to electrons trapped in interface states, which eventually recombine with the incoming free holes. 2.3.1. The geometric current component The first current component is due to free electrons of the inversion layer which do not have time to return to the source and drain regions while the substrate is switched from inversion to accumulation. These free minority carriers recombine with majority carriers (i.e. holes) arriving at the interface. This gives rise to an excess recombination current called "geometric current" (Igeom) because it is proportional to the channel length and width. Its magnitude is neither linked to the density nor to the characteristics of interface trap parameters. The first right-hand side term of Eq. (6.1) corresponds to this "geometric current", yis the fraction of free channel electrons which are readily driven into the substrate rather than towards the junction and which recombine in the substrate bulk. From the MOS theory (see e.g. Chap. 15 of Vol. 1 [1]), the charge in the inversion layer, per unit area, is given by: Qn^O

whenlVcl

< IVjl

Qn - CJVG-VT)

when IVG I > IVJI

(6.2)

Charge Pumping Techniques

421

where Cox is the oxide capacitance per unit area, VQ is the gate-bulk voltage and V T is the threshold voltage of the transistor. The total number of free electrons driven into the substrate can thus be expressed as: Qmob = rCoJVG-VT)

(6.3)

If we multiply Eq. (6.3) by the effective area of the channel and by the frequency f of the gate signal, we can express the geometric component of the substrate current by: Igeom = yfAeffCo,(VG-VT)

(6.4)

where A^ff = WxL^ff represents the effective area of the channel under the gate electrode, W is the channel width and L^ff is the effective channel length. The magnitude of this current component depends on the device geometry, i.e. on the area and geometric form of the gate and on the effective channel length. This component is usually negligible in most MOS transistors because the channel length is always kept small. However, the phenomenon may become important in the case of large geometries (typically for Leff>10^m). Igeom depends also on the shape of the applied pulses [3], as follows: • A very slow decrease in gate voltage leaves sufficient time for rearrangements and most channel electrons get a chance to reach the nearest junction. The slower the decrease, the smaller the recombination current. • For a quick decrease in gate voltage, a larger fraction of electrons gets stuck far away from the junctions, and more holes must flow towards the surface to provide electrical neutrality. The faster the decrease, the larger the recombination current in the substrate. Because this geometric current component contains no information about interface traps, one tries to reduce it as much as possible. It has been shown experimentally [3] that by using sawtooth gate signals, Igeom becomes negligibly small. 2.3.2. The current component due to interface states Another contribution to the CP current involves recombination through interface traps. When the substrate is switched from accumulation to inversion, minority carriers supplied by the source and drain (electrons in our case) flow into the channel and some of them are captured by empty interface traps. When the substrate is switched back to accumulation, these trapped electrons recombine with holes which gives rise to a substrate current. During each cycle, the interface traps are filled again with electrons coming from the source and drain; these carriers are then "pumped" into the substrate. The second right-hand side term of Eq. (6.1) corresponds to this charge-pumping mechanism. A simple interpretation of how interface traps are able to act as a charge-coupling medium is presented in Fig. 6.2 for a p-type substrate. When a gate voltage V Q is applied, the distribution of free carriers in the substrate can be described by Ep^, the dynamic quasi-Fermi level (Ep being the Fermi level when the structure is in equilibrium).

422

J,L, Autran et aL

The distribution of electrons trapped in interface traps is described by Ep^, the quasi-Fermi level of interface electrons. In the following discussion, the system is assumed to be in quasiequilibrium at all times, and thus Ep = Ep^. • When a negative gate voltage VQI is applied (VQI < 0 with respect to the substrate), the energy bands are bent upwards near the interface. The Fermi level at the interface moves towards the valence band. This is consistent with an increase in the probability of occupation of states by holes near the semiconductor surface. Consequently, most of the trap levels are above the Fermi level Ep = Ei and the trapped charge is positive (donor traps are empty). The energy band diagram for the system in accumulation is shown in Fig. 6.2 a.

Vr.i=V.

VG2 = Vi„v

interface states

Fig, 6.2 ' Illustration of the trapping mechanisms at the interface: a) In accumulation, most interface traps are empty, b) In inversion, most interface traps are filled.

• When a positive gate voltage VQI is applied (VG2 > 0 with respect to the substrate), the energy bands are bent downwards near the interface. The Fermi level at the interface moves towards the conduction band. Most of the trap levels are now below Ep = E2 and the trapped charge is negative (traps considered to be donors are filled). This situation is illustrated in Fig. 6.2 b. We consider that all the interface traps whose energy level lies inside energy range AE = E2 - El can emit or capture an electron. The states are thus in quasi-equilibrium with the energy bands. This supposes that the variations in gate bias are slow, compared with the trapping and detrapping time constants x. The distribution of interface traps within the bandgap is generally not uniform. The pumped charge Qn (AE) per unit area, which recombines via interface traps, is given by:

Qi,(AE) = qj^'Di,(E)dE

(6.5)

Charge Pumping Techniques

423

where Ei and E2 are the boundaries of the energy range which is scanned, q is the electronic charge and Dit(E) is the interface trap density at energy E (i.e. the effective number of traps, expressed per unit area and per unit energy). Expression (6.5) can also be written: Qi,(AE)^qDitAE

(6.6 a)

Qi,(A%)^q'Di,A%

(6.6 b)

or

where Dj^ is the mean interface trap density, averaged over AE, and AW^ = ^§2 ' ^ S l ^^ the corresponding scan of surface potential per cycle. Multiplying Qit given by Eq. (6.6 b) by the channel area and by the frequency f of the signal applied to the gate, we can express the pumped current due to interface traps by: Iit-fAeffq'Dit^%

(6.7)

2.3.3, Expression of the total pumped current From Eqs. (6.4) and (6.7) we can deduce the expression of the total pumped current, also called charge pumping current and further on labelled I^p. For | VQ | > | V ^ | , I^p is given by: Icp-rfAeffCox(VG-VT)+fAeffQit

(6.8)

where the first right-hand side term is the geometric current component Igeom ^^^ the second term is the "interface state current component" \ , In practice, Igeom ^^ reduced to a negligibly small value (see § 2.3.1) [2,3]. Current I^p is then directly proportional to Duand can be written: Icp-Iit^fAeffq'Dit^¥s

(6.9)

It follows that an estimate of Dit can be obtained by measuring I^p. 2.4. AN EARLY APPROACH TO THE TWO-LEVEL CHARGE PUMPING METHOD

Let us assume from now on that Igeom is negligible and let us apply a quasi-rectangular waveform to the gate of the transistor while a constant reverse bias is applied to source and drain. The pulse has a constant rise time tj. and a constant fall time tf, an amplitude A V Q = VQJJ - VQL ai^d a period Tp (i.e. a frequency f = 1/Tp). VQH is the upper level (or high level) of the gate voltage pulse and VQL is the base level (or low level).

424

J.L. Autran et al. VA 'GH

Fig. 6.3 - Rectangular voltage pulses applied to the gate of the transistor under test :

4

AVQ

VQI= low level of the gate voltage VQJJ = high level of the gate voltage

'GL

t

AVQ = amplitude of the voltage pulse r = period of the waveform.

Three versions of this simple two-level charge pumping method can be performed: • We can use a VGL value such that the surface is initially in accumulation and then bring the surface towards inversion with pulses of increasing ampUtude. • We can use a VQH value such that the surface is initially in inversion and then bring the surface towards accumulation with pulses of increasing amplitude. • We can linearly increase (ramp) the VQL value, while keeping the amplitude of the pulse constant. Let us examine the characteristics of these three versions. 2.4.1. First version: VQL = Vacc ^^^ ^G increases This method, first used by Brugler and Jespers [2] is illustrated in Fig. 6.4. A charge pumping current appears as soon as V Q ^ exceeds Vpg (zone 2 of Fig. 6.4). This current reaches a saturation level, given by Eq. (6.9) and illustrated by the upper curve (a), when V Q ^ exceeds V^ (AVQ is thus greater than V^ - Ypg). This saturation value (Icpmax) ^^^^ ^^ ^^ed to estimate Dit. let

. . (b) — (a)

cpmax

->V,GH V "VGH VT-. AVG VFB * -VGL= Vace -•t

Fig. 6.4 - Schematic illustration of the 2CP method applied to an nchannel MOSFET. In this case the amplitude of the gate pulse is increased while the low level keeps the substrate in accumulation (VQL = V^^CQ)' The upper curve shows the variations of the resulting pumped current versus VGH- Curve tail (a) corresponds to the saturation level oflcp. Curve tail (b) corresponds to an increase in the saturation level, sometimes observed.

Charge Pumping Techniques

425

A logarithmic increase of the saturation level of I^p has sometimes been observed in zone 3 of Fig. 6.4 (curve b). Declercq and Jespers [4] have suggested that this dependence of the current on the duration of the high and low levels of the gate pulse (the frequency being kept constant) was the result of the capture of carriers by oxide traps located close to the interface, due to a tunneling mechanism. 2.4.2. Second version: VGH = Viny ^^^ ^G

increases

This case is analogous to the previous one except that now the surface is initially in inversion and it is pulsed toward accumulation with increasing amplitudes. The saturation value of Icp, given by Eq. (6.9), is expected when VQL gets below the flatband voltage of the MOS transistor. 2.4.3. Third version: AVg remains constant but VQL increases In this case, voltage VQL increases and brings the top surface from accumulation to inversion. The amplitude AVQ, the frequency f and the rise and fall times (tr and tf) of the gate voltage pulses are kept constant. AVQ is positive and larger than (Vj - Vpg). As shown in Fig. 6.5, when VQL varies from V^cc (for which the substrate surface is in weak accumulation) to Vjnv (foi* which the substrate surface in strong inversion), five regions can be distinguished in the behavior of the substrate current, depending on the value of VQLRegion l:VGL
=>lcp = 0

In region 1, VQL and VQJJ are both below the flatband voltage. Therefore, the surface remains in accumulation or is switched from accumulation to depletion and vice versa. This means that I^p = 0 because the fast interface traps are permanently filled with holes and consequently no recombination current can be measured. Region 2: VGL0 hp - hprmx When VQL is below Vpg while VQH is above V j (VQH = Vj^v). the charge pumping effect is maximum. The substrate current is given by Eq. (6.9): the saturation value of the pumped current, i.e. Icpmax' corresponds to the largest possible sweep of surface potential, given the bias conditions, i.e. /^^,

426

J.L. Autran et al.

• let

- ^ I ,cp, max

'GL ( V T - AVG)

«VFB

VTVFB

JL'

GH

^GL

ff-tfli

Region 4: Vps < VQI KVJK

VGH

Fig. 6.5 ' Schematic illustration of the two-level method applied to an nchannel MOSFET. In this case, the lower level of the gate pulses is increased and brings the substrate from the accumulation mode to the inversion mode, while the amplitude of the pulse is kept constant. The upper curve shows the variations ofl^^ with VQ^ during one sweep (After Heremans et al. [5]).

^ ^ ^cp ^ ^cpmax

In region 4, I^p decreases from Icpmax (when V Q L + AVQ « Vj) to zero (when VQL « Vj). The recombination process disappears when going from regions (3) to (5), because the channel can no longer be flooded with holes and the surface is driven in strong inversion. Therefore, the falling edge of the ICP(VQL) curve is located at VQL = Vpg. This lets us estimate the flatband voltage of the structure. Region 5: VQI >Vf

=Pl^p = 0

In region 5, VQL and VQH are both above Vj. Therefore, the surface remains in inversion, the channel is permanently formed and the fast interface traps are permanently filled with electrons. Consequently, no recombination current is measured. The only measurable substrate current is that due to the source and drain leakage currents, which generally have negligible values. This means that I^p « 0. Two remarks should be made at this point: • The experimental threshold voltage value, deduced from the rising edge of the Icp(VGL) curve, must be defined as that gate voltage for which the concentration of free electrons at the surface is sufficiently large (for example ns « lO^^ cm"^) so that the fast interface traps below the Fermi level can all capture electrons while the gate voltage is applied. Let us recall that the time constant for electron capture is approximately given by: T

^n,c

=

1 ^th^n^s

(6.10)

Charge Pumping Techniques

427

where n^ is the surface concentration of minority carriers (whose value depends on the surface potential value), v^j^ is the thermal velocity of carriers and a^ is the capture cross-section for electrons. • Likewise, the experimental flatband voltage value deduced from the falling edge of the curve must be defined as that gate voltage for which the hole concentration at the surface is sufficiently large (for example ps - 10^^ cm-^) so that the detrapped electrons can all recombine with the holes while the gate voltage is applied.

ICP(VQL)

From these definitions and for an n-channel MOS transistor, it follows that the experimental V j value increases and the experimental Vpg value decreases when the rise and fall times of the gate pulses decrease [5]. 2.4.4. Possible applications of the second version The most conmionly used version of the CP method is the third one, i.e. that described above. Only region 3 of Fig. 6.5 yields a CP current described by Eq. (6.9). It is possible to go somewhat further and determine the Djt(4^g) distribution using the CP method. This has been done by Elliot [6] who used the second version (described in § 2.4.2). He derived the Dj^ distribution from the rising edge of the ICP(VGL) curve, when V Q L drives the substrate from inversion to accumulation, while VGH keeps it in inversion. For this purpose, it is necessary to determine the relationship between V Q and ^^ to calculate the energy of interface states and to extract Dit(^s) from the ICP(VGL) curve. A preliminary capacitance-voltage (C-V) study can be performed on the MOS capacitor associated with the test device by means of (C-V) measurements or directly performed on the MOSFET under test (in this case, source and drain are shorted to the substrate). The ^ S ( ^ G ) relationship can be derived in two ways: either from the quasi-static (C-V) characteristics, by applying Berglund's method or by using (C-V) measurements in high frequency. A detailed description of these methods and of the measurement setup is given in [1]. Equations (6.5) to (6.7) let us write: 1 dQit ^

Dit(¥s) = —±^= q^ d¥s

1

...

dljt dVc

J

q^fA^ff ^^G ^Ws

..,.

(6.11)

In the above expression, d\/dYQ is deduced from the ICP(VGL) curve and dVo/d^^g is deduced from the ^ S ( ^ G ) relationship. However this method only gives information in a very small region of a few kT's around the flatband position, and not over the whole range from flat band to inversion. It will be shown next that, by taking into account the emission and capture processes, we can obtain the Dj^ distribution over a larger part of the forbidden energy gap by doing a simple experiment and without needing the ^ S ( ^ G ) relationship.

428

J.L, Autran et al.

2.5. CONCLUSION ON THE FIRST-ORDER THEORY

If we neglect the fact that the distribution of interface states is not uniform in the bandgap, the large signal used in the two-level CP technique enables us to determine Dit using Eq. (6.9) and Dit(^s) when the ^ S ( ^ G ) relationship can be established [7-14]. However, this first-order model is unable to explain the fact that, for example, the experimental value of Icpmax• depends on the pulse shape; • depends on the frequency of the signal, in a non-linear fashion, for triangular pulses; • increases when the upper voltage level

(VQJJ)

increases.

A more elaborate model is thus necessary to explain the behavior of I^p and to extract more information (about the trap parameters) from the experimental I^p values. 3. A MORE COMPREHENSIVE ANALYSIS OF THE CHARGE PUMPING PHENOMENON The correct understanding of charge pumping requires that the different mechanisms, which take place when gate pulses are applied, be considered in more detail. We indicate next the most comprehensive theories regarding charge pumping proposed to date and we establish expressions for the various charge exchange mechanisms occurring during a full CP cycle. 3.1. SOME RECENT THEORIES ON CHARGE PUMPING

A theory, originally developed by Sinmions and Wei [15], completely describes the transient recombination mechanism taking place through interface traps, during the transition periods corresponding to the rising and falling edges of the pulse, by an extension of the conventional Shockley-Read-Hall (SRH) theory [16-17]. The transient SRH theory is able to analyze situations where the emission and capture of carriers trapped at the interface do not take place in steady-state conditions. From this transient SRH theory, Kaden and Reimar proposed a detailed model of the charge pumping mechanism in MOS transistors [18-22]. In their model, the probability of occupancy of a particular trap can be approximated by a time-dependent Fermi-Dirac distribution function. Based on this work, Groeseneken et al. [23-24] presented a quantitative model that yields expressions of Dit and of a geometrical mean value of capture cross-sections. These authors thus explain all the phenomena previously not well understood. Their model takes into account the emission of holes and electrons, respectively toward the valence or the conduction band, depending on the state of the Si-Si02 interface traps. We present next this comprehensive analysis.

Charge Pumping Techniques

429

3.2. DEFINITION OF THE WAVEFORM APPLIED TO THE GATE

A voltage waveform with two levels, as described in Fig. 6.6, is applied to the gate of the transistor. It has a rise time t^ and a fall time tf, an amplitude AVQ = VQH - VQL and a period Tp = 1 / f, f being the frequency of the signal. These parameters are indicated in Fig. 6.6 (a) for square (or trapezoidal) pulses and in Fig. 6.6 (b) for triangular (or sawtooth) pulses. In the latter case, an additional parameter a (with 0 < a < 1) is defined by tj. = a / f and tf=(l-a)/f.

Fig. 6.6 ' Waveforms used in the two-level charge pumping technique. Definition of the various parameters of square (or trapezoidal) pulses (a) and of triangular (or sawtooth) pulses (b).

All transition times are assumed to be much larger than the dielectric relaxation time. This allows electrons and holes of the conduction and valence bands to stay in dynamic equilibrium with gate bias at any time. The distributions of free carriers in silicon can thus be obtained by using Epj, the dynamic quasi-Fermi level, and the trap occupancy factor is described by introducing Epn, the quasi-Fermi level at the interface. We also assume that the geometric current is negligible (Igeom = 0) and thus that I^p = \ . 3.3. THE DIFFERENT PROCESSES OCCURRING DURING ONE CYCLE

When V Q increases from VQL (low level) to VQH (high level), with VQL < Vpg and > Vx, the channel goes through three space charge modes: accumulation ( V Q < Vpg), depletion (Vpg < V Q < V^) and inversion (VQ > V^). Let us analyze the emission and recombination mechanisms which are at work during each bias cycle. The voltage waveform of period Tp can be split into five regions, as indicated in Fig. 6.6: an accumulation time (tacc)? a rise time (tr), an inversion time (tinv). a fall time (tf) and again an accumulation time (tacc)-

VQJJ

First phase: accumulation time (t^cc)' ^G = ^GL = ^acc During this time interval, the system is assumed to be in quasi-equilibrium (Ep^ « Ep^). The surface is in accumulation (VQ < 0). The interface states are in equilibrium with the energy bands: the interface traps below Epd are filled with electrons, while those above it are empty. This first phase is illustrated in Fig. 6.7 a.

430

J.L, Autran et aL

Second phase: rise time (t^), Vacc "^^G^^^H ((accumulation -^depletion). When YQ increases, the surface potential is changing at a certain rate : the surface is first depleted (when VQ = Vpg) and then weakly inverted (when Vpg < VQ < Vjj with voltage Vjj defined below). The Fermi level at the substrate surface follows the evolution of the gate voltage and rises in the forbidden gap. The interface states whose energy level lies in that portion of the gap swept by Epd must trap electrons. They first do so by emitting holes towards the valence band (i.e. by capturing electrons from the valence band), as illustrated in Fig. 6.7 b. As long as the hole emission rate from the interface states, i.e. [dQit/dtJ^m^h' remains larger or equal to the charge variation necessary to maintain equilibrium, i.e. [dQi^/dtlgq, the structure remains in equilibrium. This condition can be expressed as: \dQu_'

> 'dQit 1

dt J

em,h

(6.12)

eq

or > 'dQit 1

\dQit'

L dt

em,h

. dt J

= -^'Av

eq

'dVa}-' dVc d'fsj

(6.13)

dt

As explained in Chap. 4 of Vol. 1 [1], the surface potential in silicon^*^ can be expressed as a function of V Q by: ^s

(YG -VFBKOX -27T Cox+rDi,

Qsc

(6.14)

Co,+q'Dit

where Qsc» the space charge in the siHcon substrate^^\ is given by:

Qsc = ±

^Q^Si^A

nexp(-fi\j/,) + fiii/,-l + -^(exp(

Nl

17/2

+PWs)-

P¥s

-^)

(6.15)

with P = q/kT. As soon as the rate of change of Qit imposed by the emission process becomes smaller than the rate required by the voltage sweep at the gate (i.e as soon as Eq. (6.13) is no more verified), the channel is in the non-steady-state regime. The transition from steady-state to non-steady-state occurs at a certain position E^^^^ of the Fermi level at the surface which corresponds to a certain gate voltage Vjj which can be calculated from Eqs. (6.14) and (6.15). Because of the shape of the ^ S ( V G ) curve, this transition point between steady-state and nonsteady-state will always be very close to the flat band voltage Vpg. The charge (expressed per unit area) emitted during this second phase is worth: Qem,h=-qj^'"''''

Di,(E)dE

(6.16)

F,acc

(1)

Use Eqs. (4.8) and (4.9) of ref. [1] with Q^ = - Qsc + Q I^it "^s

Use Eqs. (4.41) and (4.38) of ref. [1]

Charge Pumping Techniques

431

Vacc
^G"^acc interface states

^em,h holes

VH
VG=Vinv

electrons Ec

d)

c) VE
Vacc
Ec Ei Epd

qVo

Ev o holes f)

Fig. 6.7 - The various emission and capture processes occurring during one charge pumping cycle with the two-level method (see text).

432

J,L, Autran et al.

By convention, this charge is negative since it corresponds to a transfer of positive charges from the interface to the substrate (i.e. to the capture of electrons coming from the substrate). The charge pumping current, associated with this regime of hole emission from the interface traps to the substrate, will by convention be considered as positive. Assuming that Dj^ is equal to its mean value Dj^, the charge pumping current associated with this regime of hole emission is then given by: IA = ^ A r / % (^em,A - Ep^acc)

(6.17)

Third phase: rise time (t^), Vff inversion). Because of the high rate of change in surface potential, the channel stays in a non-steadystate regime until the gate voltage exceeds the threshold voltage. Then, the remaining traps not yet emptied of holes get filled with electrons coming from the source and drain junctions as illustrated in Fig 6.7.C. From that moment on, the channel is back in equilibrium with the energy bands. Therefore, interface traps above E^n^ ^ get filled primarily with electrons coming from the silicon conduction band and supplied by the source and drain. During this third phase, the amount of negative charges trapped at the interface increases of a quantity Qcp,e, given by: Qcp,e=-^j^'"''Di,(E)dE

(6.18)

em,h

Assuming that Dit is equal to its mean value Dj^ the charge pumping current associated with this regime of electron capture by interface traps is given by: ^1 = 'Afi^eff

(EFMV

- Eem,h )

(6-19)

With the sign convention chosen for current I4, current Ii is negative. Fourth phase: inversion time (tinvhVQ = VQfj = V/„y. The gate voltage now exceeds the threshold voltage, and the surface is inverted. The inversion layer builds up and the interface traps get filled with electrons coming from the source and drain junctions, and all the interface traps below Ep j^v ^^ occupied. The system returns to a quasi-equilibrium (Ep^ = Ep j^y). This situation is illustrated in Fig. 6.7 d. Fifth phase: fall time (tA V^^y >VQ>V£; (inversion -^ depletion). When the substrate is pulsed back from inversion to depletion, transient electron emission dominates until VQ = Vp (voltage Vp is defined below). The mechanisms at work during this time interval are illustrated in Fig. 6.7 e. Electrons are emitted from the interface traps and flow back to source and drain in a steady-state regime, until the Fermi level Epj^ reaches level Eem,e (^^ which point VQ = Vp). Energy level E^^^ and voltage Vp play a role similar to the role played by E^jj^ ^ ^ ^ ^H- The negative charge trapped at the interface decreases in magnitude of a quantity Qem,e, due to electron emission.

Charge Pumping Techniques

433

Charge Qein,e' expressed par unit area, is positive and given by: Qem,e=itiE)dE

(6.20)

Assuming that Dit is equal to its mean value Dj^, the charge pumping current (positive with our sign convention), associated with this electron emission phase, is given by: h = ^Atf^jf

(EFMV

- ^em^e)

(6.21)

Sixth phase: fall time (tf), V^* > VG > ^acc (depletion -> accumulation). The recombination mechanisms at work during this time interval are illustrated in Fig. 6.7 f. As VG gets below VE, the transient electron emission is negligible. The trapping of holes becomes important and holes recombine on traps still filled with electrons. To a good approximation, all electrons trapped in interface traps recombine by hole capture. During this phase, the amount of negative charge trapped at the interface decreases further of a quantity Qcp,h. Charge Qcp,h, due to hole capture, is positive and given by: Qcp.h=q\l'''^'

J^itiE)dE

(6.22)

^ F,acc

Charge Qcp,h corresponds to a net transfer of positive charge from the substrate to the interface. If we assume that Dj^ is equal to Dj^, the (positive) charge pumping current, corresponding to the flow of holes coming from the substrate, can be expressed as: h = -^DitMeff

(Eem,e " Ep^acc)

(6-23)

Given our sign conventions, current I3 is negative. 4. CALCULATION OF THE CHARGE PUMPING CURRENT In the previous section, we established expressions: i) for the charge being emitted, or trapped, during various phases of an applied periodic signal; and ii) for the resulting components of the charge pumping current. Let us now try to derive a usable expression of the charge pumping (CP) current itself. 4.1. ELECTRON AND HOLE CONTRIBUTIONS TO THE CHARGE PUMPING CURRENT We have represented, in Fig. 6.8, the various carrier exchanges which take place between the interface and the junctions (currents I^ and I2) and between the interface and the substrate (currents I3 and I4), when the structure is submitted to a periodic signal. "Horizontal" currents Ii and I2 are made up of electrons while "vertical" currents I3 and I4 are hole currents. Although the emission, capture and recombination processes described in Section 3 occur consecutively and not simultaneously during a CP cycle, the fact that these processes are repeated f times each second, allows us to consider currents I^, I2, I3, I4 as permanent contributions which can thus be added algebraically.

434

/.L. Autran et aL

Fig. 6.8 - Illustration of the various currents flowing in an n-channel MOSFET during one charge pumping cycle: Substrate P

Top) Cross-section of the transistor and directions of the various currents. Bottom) Position of the Fermi level (Ep^) in the bandgap and corresponding currents. II is the current due to electron trapping; 12 is the current due to electron emission, (a) during the steady-state phase, (b) during the nonsteady-state phase; 13 is the current due to hole trapping; 14 is the current due to hole emission, (c) during the steady-state and (d) during the non-steadystate phase. (After Groeseneken et al. [24]).

The electronic current, which flows through source and drain, IS/D* is thus given by: h/D

=Il+l2=

-^Atf^eff = -^^^itf^eff

(Ef^inv " ^em,/i ) + ^^tfi^eff

(Ef^v

" ^em,^ ) (6.24)

(Eem,h " ^em^e )

Likewise, the hole current, which flows through the substrate, Isub, is given by: ^sub = ^ i + ^^ = "^^itfi^eff

( Eem,e " ^F^acc ) + Q^itf^ff

= '^Qj^itfKff(Eem,h

( ^em^h " ^F^acc )

- Eem,e )

(6.25)

We note that expressions (6.24) and (6.25) are identical. We can thus write : ^cp = / i + / 2 = ^3 + ^4 = -^Q^itfKff

(Eem,h " ^em^e )

(6.26)

Energy levels Eem,h and Eem,e are called the "demarcation" emission levels. They correspond to the end of the non-steady-state hole emission and to the end of the non-steadystate electron emission. As illustrated in Fig. 6.8, they define a domain of the energy bandgap (hatched area) in which interface traps are involved in the electrical response of the device under test. We need to express them in more detail to be able to derive a usable expression for current Icp.

Charge Pumping Techniques

435

4.2. THE DEMARCATION EMISSION LEVELS

A simple reasoning allows us to assess these demarcation levels. To determine level Egjn,h, we consider that the interface states comprised between Ep^^c ^^^ ^tm,h ^^^^ ^ hole emission time constant T^JJ^ ^ which is small compared with t^jj^ j^ the time period during which these traps can emit holes (t^j^^h ^^ defined later). The closer to the valence band, the easier it is for the traps to re-emit holes into it. According to the SRH theory [16-17], T^m^h ^^^ be expressed as:

^-'''=—WM (TpVthni exp|^

^^

^^^ -^^ J

where Op is the capture cross-section of holes, vth is the thermal velocity of carriers, iij is the intrinsic carrier concentration, Ej is the intrinsic Fermi level, and Et is the energy level of the interface trap being considered. On the contrary, for those interface traps located between Egj^j jj and Ep jn^, the emission time constant is greater than tem h- Demarcation level Egj^ ji is thus given by the condition 'Cem,h = tem,h. which yields: (6.28 a)

Eem.h - Ei = kTln(vth Op Hi t,^^h) Likewise, we would find:

(6.29 a) A more comprehensive analysis, which can be found in Ref. [15] (see Eq. (31)) yields a slightly more complex set of expressions: ^ m , A - ^ ; = + ^ ^ l n | ^th^p^i^em^h

^F,acc + exp

^i I

'Fyinv ^eniye

^i ""

^^ ^^' ^th^n^ihm^e'^^m

(6.28 b)

—

E^

(6.29 b)

kT

The exponential terms of Eqs. (6.28 b) and (6.29 b) are negligible as long as 'F, ace - E i ^

^F, inv

^EA

.This kT kT y J condition is verified in practice when tr and tf exceed a few nanoseconds. Expressions (6.28 b) and (6.29 b) can thus be simplified and reduced to (6.28 a) and (6.29 a). In a first approximation, the non-steady-state emission processes only occur when the surface is depleted, i.e. when VQ is between Vpg and Wj [24]. After Fig. 6.6, the emission durations tem, h and tem, e are thus given by: Vth ^ p « i tem.h

»exp

and ^th ^ n ^ i tern, e » e x p

J.L, Autran et al.

436 for a trapezoidal waveform:

V

^^

Wfe=—IT;—^r AVr

and

r^;^,/j =

(6.30)

for a triangular waveform: f

IvV-V^fila em,e

AW

f

kr-^F^Id-g) AW

(6.31)

/

using parameters tr, tf, f and a defined earlier and represented in Fig. 6.6. 4.3. VALIDITY OF THE STANDARD MODEL

The comprehensive model of Groeseneken et al presented up to now can be considered as the "standard model". It is usable for most applications and has been formulated in different ways [25-26]. A more elaborate analysis of the carrier emission process during charge pumping has been proposed by Van den Bosch et al. to examine the validity of this standard model at temperatures significantly different from room temperature [27-28]. In this model, the thermal (non-steady-state) emission of carriers from interface traps has been analyzed and the theory of non-steady-state charge dynamics in systems containing uniformly distributed traps has been extended to the case of a non-uniform distribution. • Let us consider next the case of hole emission in an n-channel MOSFET. Van den Bosch et al. [28] define a non-steady-state emission function given by: (6.32)

F(Eut) = ep(Et)ll -f(EuO)] txp(-ep(Et)t)

where ep(Et) is the hole emission rate [s'^] for traps of level E^ and f(Et,0) is the occupancy function of these traps when the non-steady-state conditions set in (t = 0). Function F(Et,t) is sharply peaked around a certain energy level Ep ^(t), indicating that only energy levels near Ep ^(t) contribute to the emission process. Solving for Ep ^(t) yields the following good approximation [28]:

(

Ep^h(^) = E,^^h(^) = Ei+kTln\ Vf^iCpHit + exp

£,^,;,(0)-£,\ kT

(6.33)

where E^m^hCO) is the (equilibrium) Fermi level at the onset (t = 0) of the non-steady-state emission (for V Q = VGh(O)). Expression (6.33) is identical to Eq. (6.28 b), with Ep^cc replaced by Eejn,h(0)- Consequently, energy level Ep,h(t) corresponding to a maximum emission from a non-uniform interface trap distribution, corresponds to the non-steady-state emission level obtained for a uniform interface trap distribution. It can be demonstrated that this conclusion is valid down to very short emission times (« 10-9 s) over the entire temperature range studied [28].

Charge Pumping Techniques

437

• For the case of electron emission, an analogous reasoning is followed. It yields: ^em,e (0) "" Ei Ei-kTln Vr/iO-n«j? + exp - •

Ep,eit) = Ee,n,e(^) =

kT

(6.34)

The emission level is reached at time t after the beginning of the non-steady-state emission. Here Eg^ ^(0) is the energy level reached at the onset (t = 0) of the non-steady state emission of electrons. • Consequently for trapezoidal gate pulses, the total non-steady-state emission times for electrons and holes are given by:

Vch^-^FB

yT-VG^e(0) (6.35) Ay,G AV,G where VQ ^(0) corresponds to the energy level E^uj ^(0) and V^eCO) corresponds to Eem^eC^)t.em,e

FatI Tlm0

tf

and t^^^h =

[sj

Fig. 6.9 - Left) Evolution of the emission levels as a function of rise and fall times at 300 K. Einv and Eacc correspond to the equilibrium Fermi levels at the high and low level of the pulse. E^^ and Effj correspond to the equilibrium Fermi levels at threshold and flat-band conditions.

Rise

Time [sJ

0.4

Right) Evolution of the emission levels as a function of temperature for rise and fall times oflps

-^

0.2

*^

0.0

Eeme

(After Van den Bosch et al [28]). 100

200

300

400

TBtnp [K]

For rise and fall times of about lO-^ to 10-5 s, VG,h(0) and VG,e(0) are well approximated by VpB and V T respectively, as stated in the standard model. By inserting the corresponding values of tein,h and tein,e. we get: EemM^r)

=

Ei-hkTln\

\VT-VFB\'

(6.36)

438

J.L. Autran et al.

EemA^f)

=

Ei-kT\n\

\VT-VFB\^

(6.37)

^Vr

These two functions have been plotted and are represented by the square symbols in Fig 6.9. As can be seen, the approximations are sufficiently accurate for rise and fall times above -- a few ns. In Fig. 6.9 b, energy levels Eein,h ^ d Egjn,e have been plotted versus temperature. We note that, by reducing the temperature (e.g. from 400 to 100 K), a much larger energy range can be probed than by only changing the rise and fall times of the pulse (e.g. between 100 ns and 100 ms). In this figure, the energy domain which can be probed extends from 0.15 to 0.50 eV, away from midgap. 4.4. T H E NET CHARGE PUMPING CURRENT

The net CP current measured in the substrate of an n-channel transistor can be obtained by inserting the values of E^^^h ^^^ Eem,e ^^ E^- (6.26). It yields: hp = ^^itfi^eff (Eem^h " ^m,e) = ^^^Wit^ajf

lY^ft^/V^i^VWW

(6.39)

This current is directly related to the mean interface trap density in the channel, the area of the transistor, the frequency and the pulse shape (through tr and tf): • For trapezoidal waveforms, Icp varies linearly with f since the rise and fall times remain constant when f varies. It yields: I,p=2qkTfDitA,ff\v\

VT-V,

^th^i'yl^<'

AVr

v^^

FBI

/

(6.40)

• For triangular waveforms, given the frequency-dependent rise and fall times, we obtain the following non-linear relationship between I^p and f: I,p=2qkTfDi,A,ff\n\

-\VT-VFB\^|a(l-a) ^th^i^|^<^

AVG

f

(6.41)

To illustrate the validity of the approximations made so far, both experimental I^p values and Icp values calculated using (6.40) and (6.41) have been plotted versus f, for both types of pulses, in Fig. 6.10. The gate voltage was switched between - 4 V and + 4 V, the reverse voltage applied to the source and drain was 0.2 V, the temperature was 300 K. The geometrical configuration was chosen to minimize Igeom- The transistor parameters for the different devices used in this study are indicated in the figure caption. The obtained Dj^ value was found to be 3 x lO^^ eV-^cm-^. Experimental and theoretical data agree nicely over two decades of frequency.

Charge Pumping Techniques

439

Fig, 6.10 - The variations of the charge pumping current with frequency are plotted for both trapezoidal and triangular pulses, and for two transistor geometries: W/L = 25 /lO /jm (•) and W/L = 25/2.5 jjun f+j. The continuous lines correspond to theoretical (i.e. calculated) values. N'Channel transistors NA = 2.6xl0^^cm-^ tox = 30 nm Vj^ 0.97 V VFB =

-0.8V

VGL=-4y VGH = -^4V VR = 0.20 V

10

10^

10"

T=300K (After Balland et al [29J).

Frequency (Hz)

5. INFLUENCE OF DIFFERENT PARAMETERS ON THE CHARGE PUMPING CURRENT Let us now examine the influence of several experimental parameters on the CP current, namely: the pulse frequency, the pulse shape (characterized by its rise and fall times), the gate voltage, the reverse voltage applied to the source and drain, and temperature. The dependency of Icp on some of these parameters will be used later on to better characterize the interface traps. 5.1. INFLUENCE OF THE PULSE CHARACTERISTICS

5.1.1. Influence of the pulse frequency In Fig. 6.10 the magnitude of the CP current has been plotted versus frequency for trapezoidal pulses and for triangular pulses (with duty cycle a = 0.5). We note that when f increases, Icp,inax increases also, which is to be expected from Eq. (6.41). We note that for trapezoidal pulses, Icp,max varies linearly with frequency whereas it varies sub-linearly in the case of triangular pulses. This can be explained by the fact that for trapezoidal pulses, tj. and tf remain constant when f increases (only the durations of VQL and VQJ^ decrease) whereas in the case of triangular pulses, tj. and tf decrease slightly when f increases.

440

7.L. Autran et al

When rise and fall times are kept unchanged, over several decades of frequency, it gives rise to a constant amount of emitted charge per cycle and consequently to the same recombined charge per cycle. For triangular pulses, the recombined charge per cycle, given by Qit = Icp,max Z^' ^^ ^ linear function of ln(f). 5.1.2. Influence of the pulse shape We likewise note in Fig. 6.10 that, for a similar frequency, Icp,max is consistently larger for a trapezoidal signal than for a triangular signal. This stems from the fact that, for an identical pulse frequency tj. and tf are longer for a triangular signal and thus that the demarcation emission levels are closer to midgap as visible in Fig. 6.9 a. The distance between E^j^^ j^ and Eem,e S^ts shorter which reduces the value of I^p, as confirmed by Eq. (6.39). 5.1.3. Influence of the pulse amplitude When parameters VQL, f, tj., and tf of a trapezoidal waveform remain unchanged, an increase in V Q H causes an increase in I^^p. Indeed, if we increase VQJJ, and thus AVQ, we decrease the duration of the depletion step of the transistor, and consequently the time available for emission. Therefore, there will be less emission and more recombination, and thus I^,p will increase. Likewise, if VQJJ remains unchanged and we increase VQL, current I^p increases (see Fig. 6.11 a and Eq. (6.40)). 5.1.4. Inversion step duration versus trapping time constant The time during which the channel is in inversion (tj^v) should be long enough to allow the carriers to be trapped by the fast interface traps. When the inversion time becomes smaller than the trapping time constant of the interface states, these are no longer completely filled and I^p decreases because the possibilities of recombination decrease. For example, when using triangular pulses with a VQH level of a few millivolts above threshold, the time during which the gate voltage is above threshold becomes very small (~ 1 ns) and for high frequencies the interface traps can no longer be totally filled. As a result, I^p decreases when f increases. Likewise, the oxide traps located close to the interface may not be filled anymore for pulses of very small duration and thus do not contribute either to the CP current. 5.2. DEPENDENCE ON THE SOURCE AND DRAIN REVERSE BIAS

When reverse bias VR is increased, we observe a variation in charge pumping current. For an n-channel transistor, 4p decreases when VR increases (VR > 0). This is due to the fact that both threshold voltage and channel length vary with VR, as we show next. • V'T varies with VR, due to the bulk effect, according to the following formula [31]: y^ = VpB + 2|^5 \ + \VR\ +

^—^—•

— + AVT

(6.42)

Charge Pumping Techniques

441

with ^VT=-

^^ALS^D^

1+-

2L'5,D

\l/2

(6.43)

~1

^ox

where Lg ^ is the width of the space charge regions of the source-substrate and drain-substrate junctions, N ^ is the concentration of the acceptor-like doping atoms of the p-type substrate, rj is the depth of the source/substrate and drain/substrate junctions, ^ g is the potential of the substrate bulk, and 8si is the permittivity of silicon. From (6.42) we note that an increase in VR leads to an increase of IVpg - Vjl and therefore, as predicted by Eqs. (6.40) and (6.41), to an increase in I^p. • By increasing the reverse voltage applied to the source-substrate and drain-substrate junctions, we increase width LS,D ^ d thus decrease the effective length Leff of the channel, given by Leff = L - 2LS,D- It follows that the effective gate area Aeff and thus Icp decrease. Width Ls,D is given by [31]: ni/2 ^5,D(^/?) =

f;^y.\^A'^s\)

(6.44)

Thus, by using a simple one-dimensional model, the effective gate area Aeff can be expressed as: A^ff

2£,

^W[L--2LSMV^)]^W\L-2\-^

111

(6.45)

The modulation of Leff via VR can be used experimentally to probe the spatial distribution of the interface traps along the channel of the MOS transistor, between source and drain, as explained in Section 6. 5.3. DEPENDENCE ON TEMPERATURE Since carrier emission from the interface traps depends strongly on temperature, CP measurements are also very sensitive to temperature. When T increases, the emission processes from the traps increase while the recombination processes decrease. Because holes and electrons are emitted more readily at higher temperatures, levels Eem,h ^^^ Eem,e ^ ^ closer to Ei with increasing temperature, as visible in Fig. 6.9 b, leading to a decrease of current I^p. As illustrated in Fig. 6.11 a, the maximum of the ICP(VGL) curve decreases when T increases. The spread of the curve edges can be explained by small variations of V^ and Vpg with T.

442

J.L. Autran et al.

By using Eq. (6.40), and after introducing the temperature dependence of all parameters (v^j^ and Uj), we can obtain the theoretical Icp,max (T) characteristic for trapezoidal waveforms. As visible in Fig. 6.11 b, the predicted curve fits nicely with the experimental data which confirms the validity of the emission theory proposed for charge pumping. Van den Bosch et al. [27-28] have expressed the dependence of I^p on T by: I^p=-aT-bTln(T)

(6.46)

+c

where a, b and c are defined by: f3k

a = 2qkfA^ffDit\n\

b = MkfAeff Dit

and

\VT-VFB\

c = qfA^^ D^^ EQ

r—

(6.47)

(6.48)

where k = 1.38x10-^3 j K-1 is the Boltzmann constant, m* is the average effective mass of the carriers, Kj is a constant, and E Q is the silicon bandgap. Parameters m*, Kj, V^, Vpg, A^ff, Djt, and E Q are assumed to be independent of temperature. In Fig. 6.11b, the solid line has been calculated using Eqs. (6.46), (6.47) and (6.48) for a given set of Dj^ and Jo^a^ values. As we shall see in Sect. 7, the spectroscopic charge pumping technique is based on this Icp(T) dependency. 70

L

1

1

1

1

T

1

1

60 50

<

40 30

rL

/'"''''''^ iv-^""

'I

F

-8

a)

i

1 M) 1

1

1

200 K j

250K 1 1 300K 1

20 t 10 0

'

100 K j 150 K j

1

1

V ^ 1 «^i 1

-6 -4 -2 L O W L E V E L V ^ (V)

J T

b)

100 150 200 250 300 T E M P E R A T U R E (K)

350

Fig. 6.11 - Illustration of the temperature sensitivity of Icp: a) Experimental ICP(VGL) curves for various temperatures, b) Experimental data (+) and calculated curve (—) of Icpmax versus T have been plotted for = 3x10^^ eV'^ cm'^ and «J> = 2x10'^^ crn^. Measurement conditions were: AVG - 6V,f50 kHz, and tr = tf= 600 ns. (After Autran et al. [30]).

Charge Pumping Techniques

443

5.4. DISCUSSION: LIMITS AND SENSITIVITY OF THE 2CP METHOD

5.4.1. Limits The four energy levels previously introduced: Ep^^cc Ep,inv' ^em,c ^^^ ^emM depend on several parameters: a^, (Jp, tj., tf, N^ and T. • Levels Ep ^cc ^^^ Ep jj^y have been defined as the positions of the Fermi level when the substrate is in accumulation and in inversion, respectively. Both limits depend on N ^ and T. We can write the following approximate solution [31]: ^F,mv "" El -El - Efface - ^rin

A^^^

(6.49)

V ^i J

These Fermi levels get closer to the conduction band or to the valence band edges when T decreases and/or when N^ increases. During a 2CP experiment, these limits are reached only when the rise and fall times are larger than the trapping time, which itself depends on values of the capture cross-sections. For example, if: N^ = 10^^ cm-^ and T = 300 K, these limits are defined by Ep^^c " ^i = Ej - Ep inv = 0.407 eV. • The amount of pumped charge corresponds to the charge stored in the interface traps located between E^jj^ jj and E^jj^ ^ (i.e. to the hatched area of Fig. 6.8). The expressions of Eein,h ^ d Eein,e (s^^ Eqs. (6.28) and 6.29)) depend on a^, Gp, T, tj. and tf. By decreasing tr and tf, trap levels closer to the edges of the bandgap can be probed, as illustrated in Fig. 6.9 (left). Likewise, by decreasing temperature, levels closer to the band edges can be probed, because of the temperature dependence of the emission process, as illustrated in Fig. 6.9 (right). For example, for AVQ = 4 V, | V ^ - Vpg | = 2 V, T = 300 K, Gn = Gp = lO'l^ cm^ and t^ = tf = 1 |Lis, the limits are Ej - E^jj^ ^ = Eein,e" ^i = 0.235 eV. 5.4.2. Sensitivity The sensitivity of the 2CP technique can be predicted from (6.40) and (6.41), but it depends on the sensitivity of the apparatus used to measure Icp and on the quality of the pulse generator. By using the mean values of the different parameters as determined experimentally, densities as low as 10^ eV-^cm-^ can be measured on transistors of « 1 [im^ channel area at a frequency of 100 kHz. In any case, the technique is much more sensitive than capacitance techniques applied to devices of the same size [30].

444

J,L, Autran et aL

6. DETERMINATION OF THE INTERFACE TRAP PARAMETERS In addition to yielding Dj^, the standard 2CP technique gives us access to the energy distribution Djt(E) on a large part of the silicon bandgap, to the spatial distribution Dj^Cx) along the channel of the transistor, and to the geometrical mean value of the capture crosssections a = JcnCJp . This can be obtained either by exploiting the Icp(f,VQ) curves, or by letting experimental parameters such as t^, tf, VR vary, as we show next. 6.1. CALCULATION OF Djt AND a USING I^p CURVES

6.1.1. Calculation using trapezoidal pulses • Determination of D^^; According to Eq. (6.40), Dj^ can be directly deduced from the measured value of Icp. We obtain: dicp

1

Dit = - ^ df

riTr^

(6.50)

2qkTAgff In AVG\

AVQQ

being the value of

AVQ

for which I^p = 0 (see below).

• Determination of a : According to Eq. (6.40), Icp is a linear function of In(AVG). If we prolong the I^p (In(AVQ)) curve, we obtain value AVQQ for which I^p = 0. It yields:

\^T'^FB\

^th^i^l^n^p —^

I

/rV =^

(6.51)

We can then calculate the geometrical mean value of the capture cross-sections using:

a = Ja^

= ^ , ^^% J—

(6.52)

6.1.2. Calculation using triangular pulses According to Eq. (6.41), the recombined charge per cycle and per unit area (i.e. Qit" Icp/f^eff) is a linear function of ln(f). We can thus write:

Charge Pumping Techniques

Qu = - ^ = 2^^rD,-, l^vthfii^Or^Op] + ln|

445

VT-^FBIM^-OC) AW

(6.53)

/

• Determination of J<Jn<^p ' If we prolong the Qit(f) curve we obtain an f^ value for which Qit = 0. This lets us calculate d as:

d=^^

^Vc

fo ^th^i |\^r-V/rs|V«(i-«)

=—

(6.54)

• Determination of D^: The slope of the Qit(ln f) curve allows the determination of Djj without needing any parameter other than temperature and the gate area. Indeed, by differentiating Q^<^ (given by Eq. (6.53)) with respect to f, we obtain:

A> = "

1 dQu 2qkTd{h\f)

(6.55)

6.2. DETERMINATION OF THE TRAP ENERGY DISTRIBUTION

To determine the energy distribution of the interface traps, we use trapezoidal pulses and we let tr and tf vary independently. • If we let tf vary while keeping tj constant, we can let Egn, g vary while keeping Egjj^^j, constant (see Eqs. (6.36) and (6.37)). Since we have

Qit = qll'""^'Di,{E)dE

(6.56)

"em,h

we can write

dtIf

dti aif

(6.57)

Since we can also write, using (6.37) dE em,e _ kT dt /

(6.58)

446

J.L. Autran et al.

we finally get tf

dlcp

(6.59)

A>(^m,e) = — qkTfAgff dtf

• Likewise, if we let tr vary while keeping tf constant, we obtain in a similar way =

dE,em,h

-qDit(E,^h)-

(6.60)

dty

Since after (6.36), we can also write dEem^h _ kT

(6.61)

we finally get Dit(Eem,h)

= -

(6.62)

qkTfA^ff dtj.

By measuring consecutive CP currents with variable rise and fall times (see Sect. 7), we can easily obtain the energy distribution of the interface states in a large part of the forbidden silicon bandgap, while the temperature can be an extra variable. As an example of the proposed method, Fig. 6.12 shows the Dit(E) distribution obtained on an n-channel transistor with such a technique. The average Dj^ value obtained here agrees with the D^^ value obtained with the method using triangular pulses from curve Qit(f), namely: Dit - 2 X lOlO eV-i cm-2 and a « 2 x 10-15 cm^.

-0.4

-0.2

0

0.2

0.4

Trap energy Et - Ei (eV) Fig. 6.12 - Plot of a Dit(E) distribution obtained on an n-channel submicrometer transistor (Leff = 0.5 fim) using the l-level technique with trapezoidal pulses (After Autran et al [30]).

Charge Pumping Techniques

447

Let us note that in this differentiation, Gn and Gp are assumed to be independent of energy, which is probably not correct [23]. However, around the middle of the energy gap, these capture cross-sections are almost energy-independent, and therefore, the obtained energy dependence of Dj^ is reliable in this region. A more elaborate study on the determination of the Dit(E) distribution will be presented in the following sections which deal with spectroscopic charge pumping and with the 3-level charge pumping technique. 6.3. DETERMINATION OF THE SPATIAL DISTRIBUTION OF INTERFACE STATES

An important application of the two-level CP technique is the determination of the spatial distribution of interface states Dj^Cx) along the transistor channel [11, 29, 32-39]. We present below two methods proposed in the literature for such measurements. 6.3.1. General principle The measurement of Dit(x), along the channel length at the Si-Si02 interface, is based on the modulation of the effective channel length L^ff by the reverse voltages applied to the source-substrate junction (Vg) and to the drain-substrate junction (Vj)), as shown in Fig. 6.13. When Vg (resp. Yjy) increases, the effective length L^ff decreases and the interface states located in the extended depletion zone of the source-substrate junction (resp. drain-substrate junction) no longer contribute to the CP current. By decreasing the channel length step-by-step and by considering the difference between two steps, it is possible to estimate Djt(x) locally at the channel surface if the variations in width of the depleted zones with Vs and V D are known. • Effective channel area of MOS transistors: Until now, the effective channel area A^ff of the MOS transistor was considered as constant in the expressions of I^p or Qj^ and equal to the product of the channel width W by the effective channel length L^ff. If we consider now A^ff as a variable term, we must use a more general expression of I^p given by:

icp(ys>VD) = qWf

2

f ^^^^Dit(E,x)dEdx

(6.63)

where Vg and Vj) are the reverse biases applied respectively to source and drain, Lg and L^ the widths of the depleted zones of the source-substrate and drain-substrate junctions respectively and L the drawn channel length (the x values are counted from mid-channel). As we saw in Section 5 in the case of a simple one-dimensional model, the widths of the depleted zones can be easily calculated from Eq. (6.44).

448

y.L. Autran et al.

• Measurement methods: Two main measurement methods have been reported in the literature. The first one consists in applying the same bias on source and drain (i.e. Vg = V^ = VR) and thus in modulating L^ff in a synmietrical way [11, 29, 32-36]. The second method, more recently proposed, lets one modify Vg and V^ separately [37-39]. We examine next, the calculations, advantages and drawbacks of each method.

- - • X

Fig. 6.13 - Definition of the main parameters used in the determination of the D^/x) distribution along a MOSFET channel (using a one-dimensional transistor model). In this case V^ ^ VQ.

6.3.2. Method based on the symmetrical modulation of the effective channel length This method was first proposed by Maes and Groeseneken [11], then developed and used by other authors [29, 32-36]. In this method, biases Vg and Vj) are equal. Assuming a constant doping concentration along the channel and technologically identical junctions, the modulation of L^ff is symmetrical about the middle of the channel. It follows that Leff = L-2Ls,D. • If we consider a uniform distribution of interface states, then Dj^Cx) = Dj^ all along the channel and I^p is proportional to L^ff. • In the case of a non-uniform spatial distribution of interface states, the mean density of these states, for an effective channel length Leff, is equal to: (6.64) Distribution in a non-degraded transistor: For a non-degraded transistor and since the source and drain junction areas are the same, we obtain by differentiating Eq. (6.64): ^ejf

^^ff.

o

dDit{L,ff)

Ar(—^) = A r ( + ^ ) = Ar(%) + % X ^ ^

'-ff

(6.65)

Charge Pumping Techniques

449

The variation of Leff is obtained by progressively increasing bias VR = Vg = V^; the bias increment determines the spatial resolution of the measurement. For each value of VR (and thus of Lgff), it is possible to calculate Dj^Cx) in the channel, near the source and drain (symmetrical distribution). • Distribution after a non-uniform degradation: Unlike in the previous case, the determination of the Dit(x) distribution after a degradation mechanism (e.g. after hot carrier injection in the channel) requires several calculation steps and measurements before and after degradation [30, 381. 1) Before degradation, the CP current, obtained for trapezoidal signals, is expressed by:

^cpi=^ir^j/2Aviw^

(6.66)

where Ki is a constant extracted from Eq. (6.40):

Ki = IqkTfAgff hv. ^thni^<^nl<^pl

'FB1\

'Tl

AVr

v^^

/

(6.67)

2) After degradation, the CP current is expressed by: f+Lgff II

(6.68)

where K2 is a constant given by:

K2=2qkTfA,ffln\

I

\VT2

~ ^FBl

I r——

(6.69)

In these expressions, a^i and Op^ are the capture cross-sections of the traps before degradation, whereas 0^2 and <5^2 are the capture cross-sections after degradation. The variations in Vpg and V j , generally observed after an electric stress, are mainly due to charge trapping in the oxide bulk. If, to simplify, we assume that Djt is not modified near the source (i.e. that the degradation takes place mostly near the drain), we obtain: ^ejf

'eff

^eff

An(—f-) = A/i(+-f^) = A>2(-^)

(6.70)

450

J.L. Autran et al.

which allows us to write, by differentiation of U = Icn2/I cpl21.cpl

dU (dLeff ^ dV^

Kn

KlU Ko

d(K2/Ki) dV^

2KiU

"1

^eff

AYi(-f)

(6.71)

dV^R J

where ratios U and dU/dV^ are obtained from experimental values of I^pi and \^2 versus VR. Ratios dL^ff/dVR and d(K2/Ki)/dVR can be determined from Eqs. (6.40), (6.42) and (6.45). Using Eq. (6.71), one can calculate the distribution of interface traps created by an electric stress near the drain [29, 32]. Ancona and Saks [34-35] remarked that applying bias VR during the entire polarizing cycle could lead to wrong experimental results, especially for low Dj^ values. Indeed, during the inversion phase ( V Q = Vj^v), source and drain biases could affect the surface potential distribution at the channel extremities. This results in a variation of the filling conditions of the interface states located near the source and drain during inversion, which may lead to important errors in Dj^ values. The authors then suggest to apply V R only during the accumulation phase (by using a second voltage generator synchronized with the gate bias generator). This way, the electric field at the interface during inversion is not modified (VR = 0) but the spatial selection of interface states normally occurs during accumulation (VR9^0)[34].

Figure 6.14 a shows that the difference between the two profiles, one obtained by the classical method and the other one obtained by this "constant field" method (both applied to the same non-degraded device), can be sizeable. The authors conclude that the large increase in Djt values obtained by the classical method could be a measurement artifact. In Fig. 6.14 b, which deals with a degraded device, we see that the difference between the two methods is much less important than for a non-degraded device. Let us note that, in both cases, only a difference in the distribution amplitude is observed: the positions of the different curve maxima coincide exactly, which shows that both measurements give interesting qualitative information. 6.3.3. Method based on the asymmetrical modulation of the effective channel length In this method proposed by Saw and Wu [37], and by Li and Deen [38-39], source and drain are polarized in a slightly different way, as shown in Fig. 6.13 (Vg ^ Vj)). The Djt(x) distribution near the source can be obtained by varying V^ while keeping Vg constant. By differentiating Eq. (6.63), we obtain: Dit{--

+ Ls) =

1 q^JW{E^em,e

v-l dLs_ fdl cp

^em,h )[dVs

dVc

(6.72) Vj)=cst

Charge Pumping Techniques

451

o

Z

'

CONSTANT FIELD j METHOD

13

a)

Position along channel (jam)

b)

1.15

Position along channel (\xm)

Fig . 6.14 - Comparison oftheDi/x) distributions obtained by a symmetrical modulation ofL^^ for an n-channel MOSFET: a) virgin sample ; b) sample stressed 3000 s under VQ = Vj^^ = 3V. The experimental results have been obtained both with the standard method ( ) and with the constant field method (—-)(see text) (After Ancona et al [34]).

Likewise, the Dj^ distribution near the drain can be obtained by varying Vg for a given V^ value, which yields:

Du(--L^)

=

1

q^fW{E,em,e

^em,h)

dV

(6.73) ^^Vs=cst

With this method, no assumption about the initial Dj^ distribution is necessary to calculate the final D^^(x) profile. Especially, there is no need to make the restrictive hypothesis that the Dit(x) profile in the channel be the same near source and drain before degradation. To conclude, let us emphasize the increasing importance of simulation tools for a precise calculation of the Ls(Vs) and L£)(V£)) relations, especially for submicrometer devices and LDD (Lightly Doped Drain) ones. For such devices, Eqs. (6.44) and (6.45) are no longer appropriate because short channel effects and non-uniform doping render the relation between the depleted zones and the biases applied to the device more complex. Figure 6.15 shows different Djt(x) profiles obtained for an n-channel LDD transistor in the drain area. The curves have been obtained by means of the asymmetrical modulation of Leff associated with twodimensional numerical simulations (using the PISCES® software).

J.L. Autran et al.

452 itU

-

's "b

« ^

^ S T R E S S TIME = 6.2 HOURS

15 -

[•

Fig. 6.15 - Interface state densitieSy after a hot-carrier injection, measured in the channel drain area of an n-channel LDD transistor. These curves have been obtained by performing an asymmetrical modulation of L^^ (After Shaw and Wu. [38]).

W*

00

» ^ ^ ^ ^ 1.5 HOURS

^

10 -

1

5 -

1

0.1 HOURS 0 1.06

.^^^^^^"^"^"^^^Jx

1

1

,

1.08

1.10

1.12

^

>

1.14

^ 1.16

, — i 1.18

1.20

Position (i^m)

7. THE SPECTROSCOPIC CHARGE PUMPING TECHNIQUE In the classical procedure reviewed in Sect. 6, the bandgap is scanned by applying pulses with variable t,. or tf times. This variation in transition times defines different energy windows from which the CP signal is measured [24]. In the procedure described next and proposed by Van den Bosch et al. [27-28], only one energy window is defined (in the upper or lower half of the bandgap) and is forced to move through the bandgap by changing the sample temperature. This so-called "spectroscopic" method has several advantages: it lets us explore a part of the bandgap which is larger than in the classical approach, it simplifies the processing of the obtained data, and it theoretically yields information about capture cross-sections separately, using the fact that carrier emission by interface traps is temperature-dependent. 7.1. PRINCIPLE

The spectroscopic CP method consists in monitoring and substracting the CP currents obtained with a trapezoidal signal for two distinct and consecutive tj-j and \^2 values of the rising edge of the gate pulse, while keeping the falling edge unchanged; the other parameters being likewise kept unchanged (as shown in Fig. 6.16 a). The difference between the two CP currents is due to the fact that hole emission stops earlier (i.e. Eem,h (tri) < Eem,h (tr2)) when the rising edge is sharper (i.e. tj-i < tj.2). By substracting the two signals, we obtain a third signal whose magnitude depends on the portion of energy bandgap thus scanned. The lower half of the bandgap can thus be scanned by an energy window (defined by t^j and \^2 ^^ constant tf) forced to move through the bandgap by varying the sample temperature as illustrated in Fig. 6.16 b. Likewise, the upper half can be scanned by using two distinct tf values (while maintaining tj. constant) and by varying T.

Charge Pumping Techniques

453

Ec -'^F,inv

'em,h(tr2)

Kr

3 Eem,h(trl)

- _ - - - _ - - • EF,acc

Fig. 6.16 - Illustration of the spectroscopic charge pumping technique, a) The emission window in the lower half of the bandgap is defined by 2 distinct values of the rise time, the other transition times of the signal being kept constant, b) Distribution of interface states and domain of the energy bandgap which can be explored by the SCP technique using the signal defined in (a). (After Autran et al. [40]). 7.2. SPECTROSCOPIC SIGNALS

• We call spectroscopic signal (symbol Sj.) corresponding to the energy window defined by tj.1 and tj.2 at constant tf, the differential CP current given by: Sr{trl.tr2)^hpitr2^^f)-hpitr\.tf)

(6.74)

and EQJ^ the mean energy level corresponding to window (t^i, \^2)' F^^^ Eq. (6.36), EQ^ can be expressed by: IVJ-V/TBI tr\-^tr2 (6.75a) E^f. = El + kTin\ <^p^th^i AVG

(6.75b)

= Ei + knn[(JpVthniP t^r]

where tor is the mean rise time (tj.^ + tj.2) /2 and P is ratio IV^ - Vpgl /AVQ. Let us note that EQJ is temperature-dependent, and thus that a temperature scan corresponds to an energy scan in the lower half of the bandgap. Using Eq. (6.26), the expression of Sj. can be simplified into: S^ (^rl' ^r2 ) = ^^eff

^it i^or )[^em,h (^rl) "' ^em,h (^rl)J

(6.76)

which, using Eq. (6.36), can also be written as: Sr{tri.tr2)

= qfA,ffDi,{E^rW\A

^

Vr\) Density Dit(Eor) is thus linearly proportional to the measured spectroscopic signal.

(6.77)

454

7.L. Autran et al.

• Likewise, we call spectroscopic signal (symbol Sf) corresponding to the energy window defined by tfj and tf2 at constant tj., the differential CP current given by: ^/(^fl^^fl)^

^cpi^r^^fl)" ^cpi^r^^fl)

(6.78)

Signal Sf can also be written: SfitfiJf2)

= qfAeffDi,(E^f)kT\n\

^2

(6.79)

l^/l if we call Dit(Eof) the mean value of the interface states density at E^f, E^f being the mean energy level corresponding to window (tfj, tf2). From Eq. (6.37), level E^f can be expressed as: E^f = El - ^ r i n | <^n^thni

•

—

(6.80a)

AVG

= Ei - kT ln[cT„v^/^n;j3 t^f ]

(6.80b)

Level E^f is temperature-dependent, and a temperature scan corresponds to an energy scan in the upper half of the bandgap. • Quantities AEj. = kT In (tr2/tri) and AEf = kT In (tf2/tfi) are the effective energy intervals which contribute to Sj. and Sf. They can be interpreted as the widths of the trap emission distribution functions, as originally found in the CC-DLTS theory. These quantities determine the (energy) accuracy with which Dit can be measured. This accuracy decreases linearly with temperature. As an example. Fig 6.17 shows a number of spectroscopic signals obtained on an n-channel MOSFET. We note that the Sj. signals are almost identical (for a given T) as long as ratio trl/^l remains constant. 7.3. DETERMINATION OF THE TRAP ENERGY DISTRIBUTION

As seen in Eqs. (6.77) and (6.79), the experimental Sj. and Sf values vary linearly with Dj^. Thus, for a given temperature and a given set of tj. (or tf) values, Djj(E) can be calculated using the Sj. (or Sf) values and the experimental and device parameters. By varying the sample temperature, it is possible to determine Dit(E) on almost the entire bandgap as illustrated in Fig. 6.18. To each value of T corresponds a value of E^ given by Eqs. (6.75) or (6.80). Energy level EQ can be computed for each T value if a values are known (or assumed).

455

Charge Pumping Techniques

Fig. 6.17-(a) Spectroscopic signals obtained on an nchannel transistor for different emission windows defined by two distinct values of the rise time (with tf=l ps).

80

120 160 200 240 280 320 360 400 Temperature (K)

a 250 - 500 ns + 500 ' 1000 ns 0 1000 - 2000 ns X 2000 - 3000 ns

25

(b) Spectroscopic signals obtained on the same device for different emission windows defined by two distinct values of the fall time (with t^ = 1 ps) (After Autran et al. [40]).

80

120 160 200 240 280 320 360 400

Temperature (K) Fig. 6.18 - Example of Di/E) distributions obtained by spectroscopic charge pumping, assuming that 7^ = a := 5x10'^^ cm^ (After Autran etal.[30]).

-0.6

-0.4

-0.2

0

0.2

0.4

Trap energy Et - Ei (eV) 7.4. DETERMINATION OF THE CAPTURE CROSS-SECTIONS

Let us for example consider the case of hole capture cross-sections. When applying more than two distinct values of pulse edge, the bandgap is scanned by more than one emission window, giving rise to several spectroscopic signals. Information about Gp can be deduced from the shift between two S^ signals recorded with different sets of rise and fall times (t^i, tj.2 and tj.3, tj.4) if we assume that Gp is independent of T.

456

J.L. Autran et al.

An average energy level E*, confined in the lower part of the bandgap, corresponds to an emission window (t^i, ti.2) at temperature Tj, but can also be reached at temperature T2 by a second window (tj3 and 1^4). From Eq. (6.77), it follows that: In

Jr3

(6.81)

In and if the rise time ratios are chosen equal: i.e. tj2/tri = W^rS' Eq- (6.81) can be rewritten: (6.82) The energy level E* is given by: E* = Ei + kTi ln[(TpV,;,n,-^ t^n ]

with

t^ri =

E*=Ei+kT2lr{cpVfhnifit„r2\

with

t^r2=^^^^Y^

2

(6.83 a)

or ^^'^^^^

where to^j and tor2 are the average rise times corresponding to the two applied windows. If we suppose that Op is independent of temperature on interval [Tj, T2], then, by combining (6.83 a) and (6.83 b), we can write: T2

(yo(E) =

1

T1-T2

71-72

Wl(VrA«/^)l

(6.84)

Subscripts 1 and 2 of (v^j, nj P) refer to evaluations carried out at temperatures Tj and T2 respectively. Therefore, it is in principle possible to obtain the ap(E) relationship for the measured traps in the lower half of the bandgap. A similar procedure can be used to determine the an(E) distribution in the upper half of the bandgap. 7.5. SENSITIVITY AND ACCURACY OF THE SPECTROSCOPIC METHOD

In theory, it is possible to scan the entire bandgap using the spectroscopic CP technique. In practice, the levels that can be reached are confined to a somewhat smaller interval. The accessible energy levels depend on the parameters of the trapezoidal pulse (i.e. on rise and fall time values), on temperature, and on the values of capture cross-sections, as can be deduced from Eqs. (6.79) to (6.84). The lower the value of these parameters (minimal temperature and tr f « 1 ns), the closer to the band edge we are able to measure. The farthest levels are more than ~ 0.5 eV away from midgap.

Charge Pumping Techniques

457

In order to reach deep levels (i.e. in order to bring Eor close to the midgap), temperature should be as high as possible and rise (fall) times should be as long as possible (see Fig. 6.9 a & b). However, a very high temperature results in high reverse leakage currents, and consequently, in lower measurement accuracy and larger errors. Broad pulse edges imply low measurement frequency and thus low current levels, which again limits accuracy. Consequently, an energy interval of --0.25 eV centered around midgap (as illustrated in Fig. 6.18) cannot be scanned with this method. The lowest measurable trap density is determined by the current level and the sensitivity of the ammeter. For a given frequency, the CP current is proportional to the gate area of the transistor. The measurement sensitivity of the spectroscopic CP technique ranges from - 10^ eV-lcm"2 to ~ 10^^ eV-^cm-^, depending on the size of the transistor under test. 8. THE THREE-LEVEL CHARGE PUMPING TECHNIQUE The previous methods are basically transient techniques which use the SRH modeling of the behaviour of interface states to determine a time-dependent occupancy function. These methods tend to yield Dit profiles which are highly sensitive to errors made either in the trap model or in the determination of the modeling parameters. Furthermore, in order to be selfsufficient, these methods are based on rather gross modeling assumptions, e.g. that capture cross-sections are energy-independent. In this section, we present an improved CP technique which uses three voltage levels. As we show next, this 3-level or staircase charge pumping (abbr. 3CP) technique, first introduced by Tseng [41] in 1987, enables us to determine both Dit(E) and a(E), i.e. the capture crosssections of the traps as a function of their energy level in the silicon bandgap. 8.1. DEFINITION OF THE THREE-LEVEL WAVEFORM

In the 3CP technique, one uses a trapezoidal waveform which has been modified to include a third voltage step (V3), during the rising or the falling phase, as illustrated in Fig. 6.19. The duration (t3) and the value (V3) of this third level are key in determining the Dit(E) and a(E) distributions. Let us note that the basic experimental setup used for 3CP measurements is similar to that described in Fig. 6.1. The main experimental difficulty is to correctly generate the 3-level gate signal waveform with a sufficient accuracy. A gate signal of high voltage stability and high time resolution is indeed a prime condition to measure the fine changes in CP characteristics due to interface traps [30]. As illustrated in Fig. 6.19, the pulse period (Tp) can be subdivided into 6 time intervals: an accumulation time (t^cc)? ^ rise time (t^), an inversion time (tinv)? a first fall time (tfj), a step (or intermediate) time (t3) and a second fall time (tf^). Three voltage levels are also defined: a strong accumulation voltage Vacc (Vacc < ^ F B ) . an intermediate or step voltage V3 (V^cc < V3 < Vjnv) and a strong inversion voltage Vjj^y (Vjj^y > V^). Since a quasi-equilibrium exists when these three levels are applied, three corresponding surface potentials can be defined, namely: \f^^^, \|/inv and 11/3.

458

y.L. Autran et al.

All transition times are assumed to be much larger than the dielectric relaxation time which allows electrons and holes in the conduction and valence bands to stay in dynamic equilibrium with V Q at all times. 8.2. THEORY OF THE THREE-LEVEL CHARGE PUMPING METHOD

A model for the 3CP method was first proposed by Tseng [41], then developed by Chung and MuUer [42]. In the following analysis (after [42]), the distribution of the free carriers in the substrate can be described by Epj while the distribution of electrons trapped in interface traps is described by Epn- The geometric current is assumed to be negligible (Igeom = 0)- ^^^ pumped current is thus only due to interface states (I^p = lit).

Fig, 6.19 - Typical profile of the gate voltage pulse used in the 3CP technique in the case ofn-channel MOS transistors.

The analysis, figures and discussion presented next apply to an n-channel transistor (i.e. to a p-type substrate). For p-channel structures, the majority- and minority-carrier types as well as the polarity of all applied and internal voltages must be reversed (using a complementary voltage pulse). Let us examine now the different processes occuring during one cycle. The accumulation phase - During time interval t^^,^, VQ =Vacc < 0 ^^d the semiconductor surface is in accumulation. If t^cc is long enough, the system is assumed to be in quasiequilibrium (Epj = Ep^). All interface states whose energy level lies below Ep^ are filled with electrons while interface states above Ep^j are empty. The surface potential is less than (or equal to) zero. A large concentration of holes and a negligible number of electrons exist at the surface. The situation is that illustrated in Fig. 6.20 a. The rise phase - During the transition period, from accumulation to inversion, i.e. t^, Epj^ rises and additional interface states begin to fill (with electrons) by emitting holes towards the valence band (into the substrate). The exchange mechanisms at work during this time interval are illustrated in Fig. 6.20 b.

Charge Pumping Techniques

459

A demarcation-level E^m h' which lies between Ep^Ctacc) and Epi^(tinv) can be defined (see § 3.3). Interface traps below E^^^h ^ ^ filled primarily by emitting holes into the substrate while interface traps above E^^ ^ ^ ^ filled primarily by electrons supplied from the source and drain. The charge, corresponding to hole emission, is given by Eq. (6.16) and the charge that fills the empty traps by electron capture is given by Eq. (6.18). Both (6.16) and (6.18) are recalled below. The magnitudes of Qem,h and Qcp,e depend on several parameters, namely: ^eff' ^it' ^' ^acc ^inv ^FB' ^T ^^^ on the capture cross-sections of interface traps. If tj., Vacc» Vinv are kept constant, Qem,h and Qcp,e ean be assumed to be independent of tf^, t3, tf2 and V3. Qem,h=-
Dit(E)dE

(6.16)

^F,acc

Qcp.e=-q\l'"''

Du(E)dE

(6.18)

The inversion phase - During this period, of duration tj^v* the semiconductor surface is strongly inverted and the inversion n-channel builds up. The system returns to quasiequilibrium (Epj = Ep^). The surface potential is equal to or greater than 2 ^ ^ . A large concentration of electrons and a negligible number of holes exist at the semiconductor surface, as illustrated in Fig. 6.20 c. The electron capture process dominates over the hole emission process in filling the interface traps. The first fall phase - The gate voltage drops from Vjj^y to V3 during time tfi. The exchange mechanisms which take place during this time interval are illustrated in Fig. 6.20 d. As V Q decreases below V^, transient electron emission dominates until all interface traps above level E3 = - c^i^ are emptied into the conduction band. Electrons in traps below level E3 are not affected since E3 is much larger than Ep^^^^ and hole capture can be considered as negligible. The total charge, trapped per unit area of interface varies of a quantity Qem,e due to electron emission, which can be expressed as: Qem.e=q\^„^"''Du(E)dE

(6.85)

The emitted electrons flow into the substrate. A geometric current can occur if the emitted electrons do not immediately drift to the source and drain terminals. The intermediate (step) phase - Assuming that the duration of the intermediate phase, t3, is kept sufficiently long (longer than the emission time constant T^j^^e ^f the traps), the interface reaches a quasi-equilibrium. The semiconductor surface is in depletion or weak inversion and the occupancy factor of the traps tends towards its quasi-equilibrium value. We can write: Ep^ = Epn3 = - q4^3. At the end of the step, all interface traps above Epn3 are virtually empty while states below Epn3 remain filled with electrons. All previously filled traps whose energy level is above Epn3 have emitted their electrons into the conduction band. These electrons drift via the channel to the source and drain. This situation is shown in Fig. 6.20 e.

460

J.L, Autran et al.

interface states

hole emission

Ei

qVo. Epd =-qv|/3

Epd

%

Ev

hole capture

e)

f)

Fig. 6.20 - Carrier exchange mechanisms occuring during (a) the accumulation phase, (b) the rise phase, (c) the inversion phase, (d) the first fall phase, (e) the intermediate step phase and (f) the second fall phase. See text for more details (After Chung and Muller [68]).

Charge Pumping Techniques

461

The second fall phase - The exchange mechanisms which take place during this second transition phase of duration tf2 are illustrated in Fig. 6.20 f. Voltage VQ decreases from V3 to V^cc and transient electron emission should be the main mechanism. However, for short fall times (e.g. a few nanoseconds), VQ reaches Vpg so quickly that electron emission is negligible. With a good approximation, we can assume that the electrons trapped in interface states below - q^3 cannot be re-emitted toward the conduction band but rather disappear by hole capture. Therefore, the interface-trapped charge per unit area varies, due to hole capture, of a quantity given by: Qcp,h=qU^'Di,(E)dE

(6.86)

''F,acc

8.3. EXPRESSION OF THE CHARGE PUMPING CURRENT

By varying the parameters of the third level, i.e. bias V3 and duration t3, we can select the interface states involved in each charge pumping cycle. One of the energy limits of the domain scanned in the bandgap depends on the value of V3 whereas the value of t3 determines which are the traps, in this energy window, that can emit their electrons. From Eqs. (6.16) and (6.86), the total charge per unit area pumped from the interface into the substrate, Qsub' ^^^ ^^^^ waveform period, can be written: Qsub = Qit = Qem,h + Qcp^h = ^yf'

Di,iE)dE

(6.87)

em,h

Likewise, the total charge per unit area pumped from the source and drain into the interface states, for each waveform period, can be expressed, using (6.18) and (6.85), as: QsiD = 'Qsub = Qcp.e + Qem.e = " ^ J;,

A r iE)dE

(6.88)

The charge pumping current due to interface states can thus be written as: lap = ht = fAeff Qsub = q fAeff L

A v (E)dE

(6.89)

Let us now differentiate Eq. (6.89) with respect to ^2 ^ ^ assume that Egjjj^jj is independent of ^2- By expressing the partial derivative of 1^.^ with respect to VQ and solving for Djt(*P3), we obtain the density of interface traps: 1

dicp

Ar(^3) = - 2 7 : ^ id^o ;? q fAeff

(6.90)

462

7.L. Autran et al.

As seen in Eq. (6.90), only the effective area of the device and the frequency are needed to obtain Dj^ (^3). In practice, we measure I^p as a function of gate voltage V3, which leads to:

Dit(^3) =

1

dl^j, dV. cp

q fAeff

dV^ J^a

(6.91)

Equation (6.91) indicates that Dit can be determined from the functional dependence of I^p with V3 if we know the relationship linking ^ 3 and V3. This ^ S C ^ G ) relationship can be obtained by means of C-V or I-V measurements [1,43]. According to the hypotheses made above, this method yields distribution 01^(^3) only for those states whose emission constant T^ni,e ^^ comprised between tfj and t3 (tf^ < %^^Q < t3), i.e. those states which have re-emitted their charge after the first transition time and before the end of the intermediate step. Consequently, the I^p (V3) curve displays three distinct regions, as illustrated in Fig. 6.21. • In region A, voltage V3 places the Fermi level Epj^3 close to the midgap, where some interface traps have time constants such that T^m^e >^ ^3. These traps always contribute to the CP current (i.e. electrons trapped on these levels always recombine with holes because they are not emitted during t3). It follows that Eq. (6.91) does not apply and cannot be used to estimate Dj^. • In region B, level Epj|3 is located in that part of the bandgap where interface states fall within the window defined by tf^ < x^^^ ^ < t3. The slope of the Icp(V3) curve is then directly proportional to Dj^, as analytically given by Eq. (6.91). cp

4 Fig. 6.21 - Shape of the theoretical charge pumping current as a function of intermediate voltage 1^3. All timing and voltage features of the gate waveform are kept constant, except V^ (After Tseng [41]).

^V3 • In region C, level Epna is confined in a region of the bandgap close to the conduction band edge and some traps may have a time constant x^^^e "^ ^fV These traps always emit their electron during the first fall phase and are not detected during the measurement cycle. It follows that the Icp(V3) curve is not proportional to Dj^ in that region.

Charge Pumping Techniques

463

8.4. VALIDITY OF THE MODEL

8.4.1. The emission time constant window In the case of the 3-level waveform of Fig. 6.19, only those interface traps whose emission time constant T^m^e li^s inside the "time-constant window", i.e. such that tfj < x^j^e < 13, can be detected by the 3CP technique. To illustrate this, let us consider two particular cases that fall outside the time-constant window. • First case: An electron which occupies a trap above -q^3 but whose electron-emission time constant verifies x^jj^^ > t3, does not have sufficient time to escape to the conduction band. Once the intermediate step ceases and the interface is brought to accumulation, the density of holes is such that hole capture dominates. When ^^ changes from 4^3 to ^acc this particular trap is emptied by hole capture instead of electron emission. A non-equilibrium situation is established at the end of the intermediate step, and the charge pumping current is increased. • Second case: Another situation corresponds to the traps which, energywise, are located below -q^3 and which have a short electron-emission time constant \^^Q < tf2. During tf2, the semiconductor surface does not reach accumulation quickly enough to ensure that hole capture occurs. These interface traps are assumed to empty by electron emission instead of hole capture. These emitted electrons drift then to the source and drain terminals, and do not contribute to the CP current. These traps are too fast and are not detected by the technique. 8.4.2. Limits on the explorable energy range • The 3CP model is valid only if the voltage of the third level brings the structure into a weak inversion or depletion mode. Indeed, as V3 gets closer to Vinv, the assumption that all traps below -q4^3 empty by hole capture is no longer valid. Interface traps close to Ep jj^y, empty during tf2 by electron emission rather than hole capture even if they are below -q^3. Thus, for V3 close to Vjnv, electrons in interface traps below -q^3 are not all pumped into the substrate. Energy level Ep j^v ^^^ t)e approximated as the upper bound of the range of surface potential for which the model is not strictly valid. Two mechanisms become significant as V3 approaches V ^ Q , i.e. the V Q value which brings 4^3 at mid-gap. • First, the emission time-constant of a trap increases exponentially when the energy depth of the trap increases. Consequently, at some energy level above -q^3, the occupied traps do not empty by electron emission to the conduction band during time interval [tfj, t3]. These traps remain filled with electrons until the end of the intermediate step. Because of this nonequilibrium situation, the CP current increases since these traps are emptied by hole capture when the system retums to accumulation during time interval tacc • The second effect results from an increase in Igeom when the semiconductor surface is switched instantaneously from inversion to a state close to accumulation during transition time tfi. It requires a finite time to evacuate the electrons of the inversion layer towards the source and drain in response to the change in surface potential.

464

J,L, Autran et aL

In order to maintain charge neutrality, substrate holes which can respond to changes in the applied potential within the dielectric relaxation time are attracted to the surface. Consequently, the sharper the transition from Vj^v to V3, the longer the charge remains in the inversion layer, and the greater the amount of generated Igeom- Thus, as V3 nears V ^ G , a parasitic current may dominate the charge pumping current response, depending on the value chosen for tfi. 8.5. EXPERIMENTAL LIMITATIONS

We indicate next, some of the experimental limitations encountered when using the 3CP. • Because of Igeom' ^eff should be less than a few micrometers. There is, however, no constraint on W. • The gate oxide can be of any thickness as long as the oxide current due to tunneling is negligible compared with I^p. • To avoid significant edge effects, the substrate doping at the surface Ng^b ^ d channel length Lgff should satisfy the following condition [42]: ^I^>25x\0\nr^V-'

(6.92)

where VR is the reverse bias across the source-substrate and drain-substrate junctions and ^^ is the built-in potential. • To improve the sensitivity of this technique, A^ff and the waveform frequency should be as large as possible. According to Chung and MuUer [42], a useful rule of thumb can be used to estimate I^p, namely:

Icp(pA)^L6xlO'~^xA^ff(lim^

)xf(kHz)xDit(10%V'^cm~^)

(6.93)

Relation (6.93) yields a quick estimate of the number of expected pico-amperes of I^p per |Lim2 of gate area, per kilohertz of frequency, and per 10^ eV'^cm'^ of interface traps density. 9. A REVIEW OF VARIOUS THREE-LEVEL CHARGE PUMPING TECHNIQUES The basic 3CP technique whose theory has been described in Sect. 8, has given birth to several variants [41-50]. We propose next a brief review of these variants and indicate some of the obtained experimental results [41-48]. 9.1. FIRST METHOD

Introducing the 3CP concept, Tseng [41] demonstrated that Dit(E) can be accurately determined without having to assume that c^ and Gp are independent of E. The Tseng method does not use the SRH statistics to model the trapping mechanisms. It has, in theory, an accuracy equal to or better than other 3CP techniques. Another significant advantage of the Tseng technique is its ability to measure Dj^ close to the band edges, since energy levels E^jj^^ and Egjjj j^ depend on temperature (see Sect. 4). Distribution Djt(E) can be determined over most of the bandgap on either n or p substrates by changing the measurement temperature.

Charge Pumping Techniques

465

Applying the 3CP technique to different sets of n-channel transistors with various geometries, Tseng measured Dj^ up to within 80 meV of the conduction band, i.e. almost in the entire upper half of the bandgap. The Dit(E) distribution, shown in Fig. 6.22, was obtained from Icp(V3) curves measured at 78 and 298 K by using Eq. (6.91). The energy level of the traps was determined by performing charge-voltage measurements [51] directly on the transistor at 78 and 298 K.

Fig. 6.22 - Dit(E) distribution measured by the Tseng method on an n-channel MOSFET (W/L = 100/25 urn) at 78 K (A) and 298 K (•) (After Tseng [41]).

Ec-Et(eV) 9.2. SECOND METHOD

This method is similar to the Tseng method. The theory was presented in Sect. 8. Chung and MuUer [42] have applied the 3CP method to n- and p-channel submicrometer transistors. The Dit(E) distribution is obtained respectively in the upper-half of the bandgap for nchannels and in the lower half of the bandgap for p-channels. Figure 6.23 shows a Dj^CE) distribution deduced from an Icp(V3) curve for a transistor with ratio W/L = 100 /0.65 |Lim. The observed sensitivity of the technique is of the order of - 5x10^ eV-^cm-^ and interface traps have been observed within 50 meV of E^. These results apply to interface traps with Tem comprised between -- 10 ns and --100 ms, i.e. over four orders of magnitude of recombination time constant. In the same study, the 3CP technique has been employed to monitor the degradation of the gate oxide in a MOSFET subjected to a constant-current stress (i.e. to Fowler-Nordheim tunneling and hot-electron injection). 9.3. THIRD METHOD

A simple variant of the 3CP technique has been proposed by Hofmann, Krautschneider and co-workers [44-45]. The usual method has been modified to simplify the experimental procedure and data evaluation. The intermediate level V3 is chosen in such a way that the Fermi level at the interface Epjj3 is located at midgap. hi these conditions, the interface is devoid of free carriers and the interface traps cannot capture any carrier. All filled traps, whose emission time constant x^^ is less than t3 re-emit their trapped carrier during the application of V3.

J.L. Autran et al.

466 3.0 "• Data point

2.6

Fig. 6.23 ' Illustration of the 3CP method applied to an n-channel MOSFET with the following characteristics:

2.2 . 8-

1.8

1.4 -

^ \ j

Geometric current Dominated

1

1

^\m^ Interface trap ,^^ . ^ Dominated

_J

1

J

1.

0

V3(V)

= 100/0.65 im = 10 nm N,sub = 1.8x10^^ crn^ = 2.4V 'FB = - 0.9 V. W/L

The waveform used had the following characteristics: = 3.2V ^ ace = -2.2 V = ti„, = t3 = 100fis ^acc = 5 fis, tfi = 10 lis = 1 fU f/2 Measurement temperature: T = 300 K (After Chung and Muller [42]). UnV

v

1.0

q^3(eV)

In this technique, V3 as well as the other features of the waveform are kept constant. The only parameter which is adjusted is t3. Thus, the contribution to Icp of the other parts of the waveform are constant and can be eliminated by a differential data evaluation. A straightforward analysis of the emission process yields a simple evaluation of the interface states distribution. • According to the SRH formalism, the emission time constant x^^ of a filled trap is an exponential function of its energy level E^ in the silicon bandgap. We can write: 1

(6.94)

^em ~ VthniCexp\+

^^

Where the - sign (resp. + sign) refers to a trap located in the lower (resp. upper) half of the bandgap.

Charge Pumping Techniques

467

Consequently, the energy level Et of an interface trap whose emission time constant is equal to ts is given by: ^r(^em = ^3) = Ei±kT\n{v,h

Gn^ t^)

(6.95)

where the + sign is for traps located in the upper half of the bandgap and the - sign for traps in the lower half. With Eq. (6.95), we can explore part of the bandgap by increasing the value of t3. The longer the t3 value, the deeper the traps we can probe. • The pumped charge at each cycle of the gate signal (expressed per unit area) and due to the interface states involved for a given value of t3, is equal to:

a>=4 '

Du{E)dE

(6.96)

If t3 increases by steps of At, the difference in pumped charge between two steps (t3 - At and t3 + At) is given by: ,

,

\^EAu-tsx)

(6.97)

On the interval AE = | Et(t3 - At) - Et(t3 + At) | centered around Et(t3) (given by Eq. (6.95), the interface state density is thus expressed by the following relation: 1 dQit 1 AQu Dit(Et) = - ^ — ^ q dEf q AEf Af yEf)'=

(icjHtj +At) - hp(ts -At)]Tp + [hpits ^At) + hp(ts -At)]^ J —T

(6.98 a)

,^oo,, (6.98 b)

• How close to the band edges can Dj^ be measured is directly determined by the smallest t3 value which can be applied without any distortion of the gate pulses. On the other hand, for theoretical reasons, we cannot measure Dj^ closer than ~ 2kT/q around midgap. The probing of deep traps, requires a very long t3 time interval, which leads, at room temperature and for small geometry devices, to I^p currents hardly detectable with the resolution necessary for a differential data evaluation. Heating up the sample extends the energy range which can be studied towards midgap, whereas cooling it down extends the range towards the band edges.

468

J.L. Autran et al.

Figure 6.24 shows DjtCE) distributions obtained by this technique for two MOS transistors. The experimental parameters are the following ones: t3 = 20 ns, ta^c = W = 100 ns and the capture cross-section has been chosen equal to a = 4 x lO-^^ cm^. The Djt(E) distribution has been determined in the range (Ef - Ej) = ± 0.10 eV to (E^ - Ej) = ± 0.30 eV. ,10

10'

>

6

Fig. 6.24 - D^/E) distributions obtained for a conventional MOS transistor with W/L = 20/1.8 im (a) and for an LDD MOS transistor with W/L = 10/0.9 jjm (b) using the Hofmann and Krautschneider method. (After Hofmann and Krautschneider[68]).

tfV

10' -0.4

-0.2

0.0 Et - Ei (eV)

0.2

0.4

9.4, FOURTH METHOD

Later, Saks and Ancona [46-48] have proposed a technique which is, to date, the most complete synthesis of the various 3CP procedures. They demonstrated that by changing the value of V3 and that of t^, as illustrated in Fig. 6.25, one can determine Dit and a as a function of Ej. These parameters are obtained for both types of traps (electron and hole traps) using a single n- or p-channel MOSFET. This is a significant advantage over conventional analysis techniques.

Fig. 6.25 - Illustration of the changes in the 3CP signal used in the method proposed by Saks and Ancona.

-•t

Charge Pumping Techniques

469

9.4.1. Principle The modulation of V3 and 13 is the basic principle of this 3CP technique. During tinv, all interface traps are filled with electrons. When the pulse is switched to V3I, many trapped electrons are emitted back to the conduction band if their emission time \^^Q is short, ff t3 is long enough, all trapped electrons above Epj^ (determined by V3I) are emitted, and the trap occupancy reaches a quasi-equilibrium. Finally, during tf2, holes are brought to the interface which, with the remaining trapped electrons, gives rise to I^p (see Fig. 6.20 f). Two combinations are possible. • V3 is changed while t^ is kept constant: If V3I is changed to ¥3^ for a fixed t3 value as illustrated in Fig. 6.26, the equilibrium occupancy level of the traps changes. From the resulting change in I^p, the density of traps located between levels Eji and ^^2 (given respectively by V3I and ¥3^), with a time constant %^^Q verifying tf^ < X^^Q < t3, can be deduced as follows: Dit{E,) =

1 ^cp AV3 qfA,ff AV3 A£,

(6.99)

mv •E:i

•E,i

ace

Fig. 6.26 - Left: shape of the 3CP signal. Right: diagram of interface trap occupancy after filling with electrons and applying bias levels V^^ or Vj^ (After Saks andAncona [46]).

L=.Ev

• t3 is changed while V^ is kept constant: Experimental Icp(t3) curves for different values of V3 are shown in Fig. 6.27. If duration t^^ is changed to t^^ for a fixed V3, the interface traps whose energy level lies above Ep^, with a time constant TQ^^^^Q verifying t'^^ < 'Tem,e '^ ^3^, participate in the emission process. For small t3 values, the interface states are not in thermodynamic equilibrium with the energy bands and I^p is important. I^p decreases approximately linearly with ln(t3). For large t3 values, most traps above level Epj^ (given by V3) emit their electrons and retum to thermodynamic equilibrium with the energy bands. If t3 becomes larger than the greatest time constant of the traps, the emission process stops. A saturation rate is reached for tsat = '^em- ^^^ values of t3 above tg^t. the charge pumped during a cycle, when the transistor is switched to accumulation, remains constant, as visible in Fig. 6.27, and equal to the charge trapped in all interface states below Ep^.

470

7.L. Autran et al. 0.55

Bo

f=100Hz •*-° ° ° a a aoo

0.45

< KT

0.35

10"

oo o a oq

V 3 ^ •f

-•.7«V

o

-o.««

•

•0.S1

V

-.50

o

0.25

ooo

"*"-? o o «

,

^-sat ^^.

-.40

]


•

••!,»««>!¥

10-*

I

> » i t i n l

10-*

i i i i t i m i l

10"

10-

^ + -t- -H

I

I I I

Fig. 6.27 - Current I measured by means of the 3CP method is plotted as a function of t^ for electron emission, with pulse bias V^ as a parameter. I drops with In(t^) until saturation is reached for large t^ values. The emission time constant T^^ of the interface traps is determined from the saturation value of I (After Saks andAncona [46]).

10"

time t3 (s) 9A.2. Determination of the interface state density • First case: tj < tg^f. When V3 remains unchanged and 13 < tg^^, we have not reached the saturation mode yet. This means that traps whose x^^ value is above t3 contribute to I^p. Thus in this case, I^p can be expressed as a function of t3 instead of V3. It follows: 1 Dit(Et) =

dicp cp dt

qfAgff dt^ dEf

(6.100)

If we identify 13 with a single SRH emission time constant, we can express dt3/dEt using Eq. (6.94). It yields: dt3_ dEt

l3_ 1 + kT da kT <7 dEf

(6.101)

By inserting (6.101) into (6.100) we get: kT do dl cp h 1+Dit(E,) = qkTfA^ff [ a dE^ dti

(6.102)

which can also be written Dit(Et) = -

kT da dl cp 1+qkTfAeff a dEt\d{[nt3)

(6.103)

This explains why \.^ decreases with ln(t3) when the emission process is limited by step duration t3, as illustrated in Fig. 6.27. From Eq. (6.103), the slope of this Icp(ln(t3)) curve is proportional to Djt. If a is considered to be energy-independent, we have the approximate relation:

Charge Pumping Techniques

471

1

dhv D,,(E,) = / ; (6.104) qkTfA^ff d(lnt3 ) Let us note that Eq. (6.104) is similar to Eqs. (6.59) and (6.62) established for the 2CP technique in which the transition times tf and tj. have been replaced by t3. • Second case: t^ > tg^f. By selecting a t^ value large enough so that almost all interface traps indeed emit their charge, it is possible to calculate the Djt(E) distribution using relation (6.99) and considering the variation in the charge pumped per cycle in the saturation regime, as a function of t^, and for different values of V3. Distribution Djt(E) is calculated using relation (6.99) for the successive values of the pumped charge in saturation as a function of V3 and only for the hole-emission and the electron-emission regimes (because of the equilibrium character of these regimes). Practically, if Qj (respectively Qj+i) is the pumped charge in saturation for a Vj voltage (respectively Vj+i), then the mean interface state density between Ej and Ej+i is given by:

Dif(E)»

AQ 1 Qj^l-Qj\ ,"^^^= / 1'^''^ ^"1 qA,ffAE qA,ff

with

E =^

i^

(6.105)

^i+i~^i\

The knowledge of the 4^S(VG) relationship (i.e. the energy position in the silicon bandgap as a function of VQ) is required, in order to calculate the Dit(E) distribution. This relationship can be obtained independently by C-V or I-V measurements. 9A.3. Determination of the capture cross-sections The time at which saturation first occurs (tg^t) is equal to the electron emission time constant:

1 ^sat

"^em.e =

(e

( E.-EA xpl—^1

(6.106)

to the hole emission time constant: 1 ^sat

^em,h

(6.107)

^th^i^p

It is therefore possible to determine \^(E), the energy distribution of the emission time constants (see Fig. 6.28), and the capture cross-sections of electron and hole traps, by monitoring the charge pumped per cycle as a function of t3 and V3. We get: 1

f^Ef-EA

472

J.L. Autran et al. lOS 10-* t-

I 11 I 1 1 1 I 11 1 1 1 I I 11 I

Hole emission

11 I 1 1 1 1

/

111111111

Electron emission

Fig. 6.28 - Distribution of the emission time constants r^^ as a function of energy obtained for electron and hole traps related to a (100) Si-Si02 interface. Solid lines are exponentials with slopes ± 1/kT predicted by the SRH theory when a^ and Gp are considered to be energy-independent. After Nicollian and Goetzberger [52] (triangles), Saks and Ancona [46] (diamonds) [74], Autran and Balland [50] (circles).

en ^x•

JQ->

Exp(±Et/kT)

I I I I i I i I I I I I I I I I I I I I f I i I I I I I I I I I I I I I

-0.4

-0.3

-0.2

-0.1

0

O.I

0.2

0.3

0.4

Et - Ei (eV) As shown in Fig. 6.28, the values obtained for the emission time constants are, in this case, in good agreement with the assumption that capture cross-sections are independant of energy: a slope of - exp(± E^/kT) is obtained for both electron and hole traps, respectively in the upper half and in the lower half of the bandgap. The two distributions of emission time constants are well fitted by Eqs. (6.106) and (6.107) with c^ = c^ 10-15 cm^ 9.5. NUMERICAL SIMULATIONS

The aim of this paragraph is to re-examine the charge response of the interface traps and to present some theoretical results from one-dimensional numerical simulations. This analysis relies upon recent works by Saks, Ghibaudo and Ancona [48, 53-54]. 9.5.1. Analysis of the emission and capture regimes Until now, we have always considered that the third level of the 3CP method corresponds to an electron emission regime, i.e. that as long as V3 is applied, the electrons previously trapped on the interface states (i.e. while Vinv was applied) are re-emitted and no hole capture occurs. Of course this is true only as long as V3 is chosen above VJ^Q (which corresponds to an Epn and a ^^ value at midgap). This is schematically illustrated in Fig. 6.29 (upper curve). If V3 is chosen below VJ^G' electron emission does occur at first but hole capture quickly becomes the major mechanism. There results that if we plot Icp(V3) for a given t3 value, the I^p value decreases until 4^^ reaches midgap (VuG ~ 0 V) then increases again due to hole capture, as illustrated in Fig. 6.30 (upper curve). Let us note an important point. During the hole (or electron) capture regime, the semiconductor surface is in an out-of-equilibrium state. Indeed, the flow of carriers at the surface of the semiconductor is due to a fast change in surface potential. This rapid electrostatic response of the semiconductor leads to a density of free carriers whose value does not correspond to the equilibrium value and which is difficult to evaluate.

473

Charge Pumping Techniques

ELECTRON FILL

V^MG

Fig. 6.29 - Schematic representation of the gate bias waveform and of the various emission and capture regimes involved during a gate pulse period (of the 3CP technique) with regards to the position of the intermediate third level and the initial filling of the interface states (electrons or holes). Vj > Vj^Q > VpQ corresponds to the case of an n-channel transistor.

'FB

'MG

FB

y Fig. 6.30 - Pumped charge per cycle for saturation (i.e for a large t^ value of 1.2 ms) as a function of the third voltage level for the different electron and hole emission and capture regimes. Data has been obtained on an n-channel transistor with W/L = 100/0.5 pm (After Autran et al. [30]).

"S3

00

o

3

-2 -1.5 -1 -0.5 0

0.5

1

1.5

2

Intermediate voltage V3 (V)

There results that the capture cross-sections cannot be accurately calculated during this capture regime because the surface concentrations of carriers are unknown. Equation (6.108), based on an equilibrium value for the surface concentration of minority carriers, is not valid in this case. To sunmiarize, the 3CP method appears to be the only method which allows us to investigate emission and capture regimes from interface traps. By choosing a waveform as represented in Fig 6.29 (upper curve), electron emission and hole capture can be reached. We could of course use a waveform of opposite shape and choose a V3 level such that it corresponds to an equilibrium hole emission phase. This is illustrated in Fig. 6.29 (lower curve). The out-of-equilibrium phase would then be that of electron capture (V3 > V ^ Q ) .

J.L. Autran et al.

474

9.5.2. Basic equations An important work dealing with the numerical simulation of the 3CP technique was done by Saks and Ancona [48] to analyze the transient phenomena taking place during a CP cycle. This work follows the studies of Ghibaudo and Saks [53-54] related to the time analysis of physical processes involved in the 2CP phenomena (see also the work of Hofmann and Hansch [55]). • To summarize it briefly, the time analysis consists in using a quasistatic one-dimensional model to explain the transport mechanisms in the semiconductor. The semiconductor is supposed to instantaneously follow the variations in gate bias and the carrier movement at the interface. The interface kinetics are modeled by an SRH approach. Two time-dependent variables are introduced: the surface potential ^s(t) for the interface kinetics and the potential linked to the quasi-Fermi level at the interface ^Fn(0- By making various assumptions, the variations of these two variables can be linked to the interface states parameters and to gate bias using the following equations: d^Fn(0 dt

1 dQi, jcr_ Cox dt

yG<
1

1

\^cp,e

1

1

— + '^em,h '^'cp,h ) ^em,e

(6.109)

(6.110) ^ox

^ox

where Qsc is the space; charge in the semiconductor. Time constants %^^Q and T^j^^h ^ ^ deduced from Eqs. (6.106) and (6.107) and x^p^e ^t T^p^h ^ ^ given by the following expressions, assuming that the quasistatic hypothesis is verified: exp\ (6.111) 1 ^cp,h — ^th^i^p

exp\

The system of Eqs. (6.109) to (6.111) can be solved numerically, using time as a discrete variable. The I^p value is obtained by integrating these equations on a gate bias period Tp. We then obtain [48, 53]: \

kT cT^ \^cp,e

'^emyC)

kT cT

r \^cp,h

1 ^em,h

dt (6.112)

Charge Pumping Techniques

475

9.5.3 Simulation results These simulations enable, on one hand, to visualize the simultaneous variations of ^s(t) and ^Fn(t) during period Tp, and, on the other hand, to estimate the duration and the intensity of the various carrier emission and carrier capture transient currents during this same period. The difference existing between the ^^ and ^ p ^ potentials shows that interface traps, energetically located between -c^^ and -q^pn' ^ ^ ^^^ in equilibrium with the energy bands. In the following examples, the simulations apply to a p-channel transistor i.e. to an n-type substrate. The period Tp is taken equal to 10 ms and both rise and fall times are equal to 50 ns. • The electron emission regime When the n-type semiconductor surface is switched from inversion to accumulation, as illustrated in Fig. 6.31, hole emission at equilibrium Q¥^ = ^p^) begins at the very start of the rise time (t = 0). Then, electron capture quickly sets in during the following phase Q¥^ ^ ^p^) which leads to an intense current. A new equilibrium state is reached. During tfj and t3, the difference between potentials ^^ and ^f^n is zero, showing that the interface traps are indeed in equilibrium with the energy bands. In this example, it is important to note that no hole capture happens during tfi: the equilibrium of interface states is only controlled by electron emission. At the end of the intermediate level, and in accumulation, a low electron emission is rapidly hidden by the massive flow of holes at the interface which induces an intense recombination current. This current is the main contribution to I^^p. 0.5

n

1——1

1 0' i

r

]

I

0.25 10-

QUASI-FERMI LEVEL

9

0

S -0.25 o

K

^Fn

\

\

1—-i

r-—r

1 . 1

GATE VOLTAGE [ HOLE EMISSION

-3

ELECTRON CAPTURE HOLE CAPTURE

I

A

ELECTRIC POTENTIAL \

r

^10" ELECTRON EMISSION

1 GATE VOLTAGE

-0.5 J

-0.75

I

I

L_

Time (variable scale)

3

10*

Time (variable scale)

Fig. 6.31 - Results of numerical simulations applied to the 3-CP method. Left: Surface potential ^g ^^^ ^Fn have been calculated and plotted versus time (during a full CP cycle) for an n-type substratey and for an electron emission regime. Upper curves: ^ p ^ (t) ( ) and ^^ (t) ( ) Lower curve: Profile of the applied gate voltage. Right: The corresponding transient currents have been calculated and plotted. The voltage profile is shown in the inset (After Ancona and Saks [48]).

J,L, Autran et al.

476

• The hole capture regime The initial phase (filling of traps by electrons) and the final phase (recombination by hole capture) are the same as before. But when VQ is switched from Vacc to V3 a very different behaviour of the interface traps is observed as visible in Fig. 6.32. Although an electron emission takes place at the beginning of tf^, for traps located over a certain energy level E* (-- Ej + 0.1 eV), this emission phase is followed by hole capture out of equilibrium (large difference between ^^ and ^p^) for traps located between E* and Ep^. This capture phase nearly extends until the end of t3 at which point equilibrium is restored. As long as this hole capture exists (i.e. as long as electrons remain trapped in the interface states located between Epn and Eps), the difference between ^s and 4^pn results in a more negative interface charge than at equilibrium, which induces an additional bending of the energy bands. This additional bending implies a variation of ^s which has not reached the same value as at equilibrium. This effect is called the overshoot effect visible on Fig. 6.32 (dashed curve). Band relaxation and the disappearing of the overshoot effect exist when all traps over the Fermi level are emptied by hole capture. Going from V3 to Vinvfinallyinduces an additional hole capture to empty the states remaining full of electrons between - q4^3 and EF,inv.

This capture results in recombinations taking place during t3 and tf2 and thus contributes to Icp. Consequently, the I^p saturation level is defined by level E* because the traps involved in the recombination process (i.e. filled by hole capture) are located between E* and Ep i^v The calculation of Dj^ during the capture regime needs to correctly evaluate level E* for each value of V3. Moreover, it is absolutely necessary to take into account the variations of ^^ due to the overshoot effect. For all these reasons, the use of experimental results obtained during the capture regime is very critical. For example, a variation of ^^ of a few millivolts can induce a variation in capture cross-sections, larger than one decade. n

0.5

I

I

1

J

1

1

1

1

r-

QUASI-FERMI LEVEL

0.25

10"

1

1

1

1

1

\

1

r

GATE VOLTAGE

1 1 3

HOLE EMISSION ELECTRON CAPTURE

rv

.2

ELECTRON EMISSION

\\

'% -0.25 ••-»

o ^

.0.5 -0.75

0

T

Time (variable scale)

^

Time (variable scale)

Fig, 6.32 - Same diagrams as those of Fig. 6.31 but for the hole capture regime (After Ancona and Saks [75]).

Charge Pumping Techniques

" £ k Z ^ A A A A A A ^

i—r

T + 4 -H

-0.95V -1 05 V

X X

10*

10*

10'^

10

Fig. 6.33 - Experimental and simulated (—) Qcp(t2,V'i) curves for the electron emission regime in a p-channel transistor (After Saks cindAncona[75]).

-1.15V

f=100Hz 0.5 10*^

All

10'

Duration of V3 (s) To conclude and illustrate the method proposed by Saks and Ancona, Fig. 6.33 shows experimental and simulated Icp(t3,V3) curves obtained in the electron emission regime. The good agreement of experimental results and simulated curves shows that the one-dimensional approach is correct to describe the behaviour of interface traps during the 3CP measurements. 10. EXAMPLES OF APPLICATIONS OF CHARGE PUMPING TECHNIQUES All the CP techniques presented in the previous sections make it possible to study, directly on small geometry MOSFETs, such phenomena as: • the influence of technological process steps on the quality of the Si-Si02 interface, • the consequences of aging stresses on the interface trap properties, whether these stresses consist in uniform carrier injection, hot-carrier injection or irradiation. Aging phenomena in MOS transistors are increasingly studied because of their impact on the reliability of small-size components. Before the advent of CP techniques, the uniform degradation of MOS transistors, caused, for example, by radiation or by Fowler-Nordheim tunneling, was mostly studied on capacitor structures. One possible way to measure directly an increase in interface trap density on a MOS transistor was to analyze the slope of the subthreshold current characteristics, which is a partial, indirect and rather insensitive technique, especially for interface state density levels below - lO^ eV-l.cm-2. We show below how a uniform or a non-uniform interface degradation affects the CP response and we present some examples of typical curves. The determination of the spatial distribution of created interface traps is also briefly discussed. 10.1. APPLICATION TO THE STUDY OF A UNIFORM DEGRADATION

The uniform degradation of MOS devices exposed to ionizing radiation and/or to FowlerNordheim injection can be studied directly and quantitatively with the CP technique, even on floating-gate MOS memory devices [5, 57-64].

478

J.L, Autran et aL 10.1.1. Degradation of MOS transistors

Typical ICOCVGL) characteristics recorded using the 2CP technique on uniformly degraded MOS devices are given in Fig. 6.34. The curves obtained after a stress has been applied are generally of a larger amplitude and are shifted with respect to the initial characteristics. 1) The increase in Icp,max reveals an increase in the number of electrically active traps at the oxide/semiconductor interface. The rise and fall edges of the CP curve are also broadened due to the charging and discharging of the fast interface traps. 2) The sideways shift of the curve reveals an evolution of the Vpg and V^ values of the degraded structure. This shift AV is due to the generation of oxide charges in the bulk and/or near the interface. These charges are positive (resp. negative) if the curve shifts towards more negative (resp. more positive) voltages (see Chap. 10 of Vol. 2 of this series). This shift is given by: Ay = -

aox

X

1--

(6.113)

''OX J

^ox

where x is the centroid of the oxide charge, counted from the interface. In most real cases, it is difficult to determine the type of fast interface traps just created since from the shift of the CP curve, only the sign of the net charge (positive or negative) in the oxide and at the interface can be deduced [5]. .\

T

curve c curve b / // curve a \ ' \\ /

; fi

\i

\ b:.^

•

Fig, 6.34 - Illustration of the influence of the interface trapped charge on the ICP(VGL) curves: curve (a) is the CP curve for a low Du (a virgin MOS transistor); curve (b) indicates a high density of donor-like interface traps; curve (c) indicates a high density of acceptorlike interface traps (After Heremans et al I5]h

VGL

The characteristics of Fig. 6.34 make it possible to distinguish between the formation of fast interface traps and the build-up of the oxide charge. Indeed, the total number of fast interface traps in the channel is proportional to the amplitude of the recorded I^p current, while VpB and V^, whose values depend on the fixed oxide charges (Qf) and on the interfacetrapped charges, can be evaluated, to the first order, from the edges of the curve. As illustrated in Fig. 6.35, this CP threshold voltage (extracted from the value of VQL at 50 percent of the maximum CP current) can be plotted as a function of the Fowler-Nordheim injection time for different values of the gate voltage stress. We note that a turn-around effect is observed.

Charge Pumping Techniques

9

VgateslOV Vgate = 11 V Vgate = 12V Vgateri3V

0^

'o >

Fig. 6.35 - Illustration of a turn-around effect observed after FN injection: the threshold voltage of the transistor^ measured from CP curves, is plotted as a function of the Fowler-Nordheim injection time for different values of the stress voltage (After Heremans et al. [5]).

11

o

0

479

10-3 10-2 10-'' 10°

10^

102

103

10^

Injection time (s) 10.1.2. Degradation of EEPROM Memories A floating-gate transistor can be considered as a MOS transistor with a stacked gate dielectric. The charge stored on the floating gate leads to the same electrostatic influence as a uniformly distributed gate oxide charge. By applying the same formulas as those used for conventional MOS transistors, the density of interface traps can be determined, with the same accuracy, using a CP technique, in floating-gate devices. 1013

^ ^

^

1012 •

X

O

^

1010 •

109

-! 10^5

1

io16

1

^QM

Fig. 6.36 - The increase in Dit, observed during the aging of a thin-oxide floatinggate EEPROM device is plotted as a function of the fluence of injected electrons. These Du values have been directly obtained from CP measurements (After Heremans et al. 15]). t

10^8

^

1

10^9

1020

Fluence of injected electrons (cm"^) This application opens new and broad perspectives for correlating externally-observed aging effects in memories (e.g. threshold window opening and closing) to the physical mechanisms responsible for this degradation. The advantage of performing CP measurements directly on floating-gate devices is that the aging of the memory devices can be analyzed under real progranmiing conditions [65], i.e. under high-field conditions with alternating polarities. Moreover, changes in Dit can be observed for small quantities of electron injected during the write cycle, as shown in Fig. 6.36.

7.L. Autran et al.

480

Let us note, however, that during aging no conclusion can be reached regarding charge trapping in the oxide, since charges, uniformly trapped above the entire channel area, cannot be distinguished from charges stored on the floating gate. 10.2. APPLICATION TO THE STUDY OF A NON-UNIFORM DEGRADATION

Although conventional methods of electrical characterization (such as the study of the IDS(^GS) characteristics) let us analyze the uniform degradation of MOS transistors, they do not enable us to correctly study the non-uniform degradation mechanisms, because: i) it is difficult to separate the effects of the fixed charge from those of the interface states; ii) the threshold voltage of a degraded device is no longer physically meaningful because it varies along the channel (which renders the analysis of the IDSC^GS) curve difficult). The CP technique has the advantage of separating the contribution of the interface states from that of the fixed charge and of yielding information specific of the degraded zone of the channel [5]. Unlike the IDSC^GS) curves, the CP response of a degraded transistor; can be considered as the addition of several contributions, each coming from a different part of the channel, each part having its own V^, Dj^ and Qf values. •cp

^s I

l— 'cpi * 'cp2 Pig 5 57 . Schematic representation of the ICP(VGL) curves of a non-uniformly degraded n-channel transistor (see text). Curve I: CP response of area 1. — f 'cp^ Curve II: CP response of area 2. Curve III: global CP response of the transistor (source and drain connected). Curve IV: global response of the I— 'cp2 transistor with disconnected drain. In the inset, the source-substrate junction is on the left and the drainsubstrate junction on the right. (After ^ Heremans et al. [5]).

I

I N Nl IV

Vt2-AVA

VtrAVA

Vfb2

Vbas

10.2.1. Case of an n-channel MOSFET Figure 6.37 illustrates how the global response of an n-channel transistor, non-uniformly degraded along its channel, can be decomposed [5]. In this example, the channel is split into two areas: area 1 is not degraded (low Djti, V^i) while area 2 is degraded (Dit2 > Diti» Vx2 < Vji) due to the presence of a positive oxide charge. Curves 1, 2 and 3 in Fig. 6.37 show the respective contributions of areas 1 and 2 and the global response of the device, for a fixed VQL bias, and with source and drain connected. Curve 4 corresponds to the case where the drain is disconnected. In this example a negative charge is found to be located near the drain (this type of degradation is, for example, encountered after hot electron injection in an nchannel silicon-oxide-nitride-oxide-silicon transistor).

Charge Pumping Techniques

481

10.2.2. Case of a p-channel MOSFET The CP characteristics of a p-channel transistor with a positive charge trapped in the gate insulator over part of the channel can be derived as in the case of the n-channel device. Curves 1 and 2 in Fig. 6.38 represent the CP characteristics corresponding to the channel portions indicated in the inset of Fig. 6.38. Curve 3 is the resulting curve expected when both source and drain are connected during the CP measurement. In this case, the location of the degradation can be identified by disconnecting the source. Indeed, if the source is disconnected, holes from the drain can only reach part 1 of the channel if part 2 is inverted. In this case, the CP curve is expected to behave as shown on curve 4. However, when the drain is disconnected, the CP curve is identical to curve 3. Such a local injection of holes could for example be encountered in a p-type metal-nitride-oxide-silicon device, due to the high hole injection and trapping probability in the nitride layer (see Chap. 5 of this volume). •cp

^s

'cpi + 'cp2 Fig. 6,38 ' Schematic representation of the Icpi^Gh) curves of a non-uniformly degraded p-channel transistor (see text). Curve I: CP response of area I. Curve II: CP response of area 2. h- 'cpl Curve III: global CP response of the transistor (source and drain connected). Curve IV: global response of the transistor with disconnected drain. 'cp2 U \ In the inset, the source-substrate junction is on the left and the drain-substrate junction is on the right. (After Heremans et al. [5]).

aaaiii.-x..i»ji«««.*^

I ii III IV

Vfb2-AVA

Vfbi-AVA

Vt2

Vti

Vbase

10.2.3. An experimental case Figure 6.39. shows experimental ICOCVGL) curves measured on an n-channel transistor previously degraded by using a maximum substrate current [66]. This type of degradation, corresponds to both hole and electron injection [53]. We observe that I^p increases greatly after stress, which indicates the creation of a large number of interface states during aging. Moreover, after injection, the ICDCVGL) curves appear also distorted. The observed distortion means that, after degradation, the total gate oxide charge is positive. The curve obtained for a 180-minute stress, reveals that hole trapping in the gate oxide is more important for a prolonged stress. Its shape corresponds indeed to a hole injection followed by trapping which causes a non-uniform degradation along the channel of the aged transistor [5, 55, 66, 67]. This hole injection is known to follow an electron injection. Difference AVj, between curves 3 and 4 of Fig. 6.39, is attributed to hole trapping, whereas, difference AV2, between curves 1 and 3, may be due to the generation of interface states near the drain.

482

^ ®

y.L. Autran et al.

4/z I '

// '^

^^--.^^^ ^

\ ^

Fig' 6.39 - Icpi^Gi) ^w^^-y obtained for an n-channel transistor with W/L = 3.4/2.4 jUm, stressed under VQ = 5.7 V and V£> = 8 y dwrmg ft 50, 90 and 180 minutes (After Djahli et al. [66]).

-7,2 -6.4 -5.6 -4,8 -4.0 -3.2 -2.4 -1.6 -0,8 0.0 VGL(V)

The quantification of the positive trapped charge in the gate oxide after hole injection is somewhat complicated by the fact that interface traps created very near the drain in an nchannel transistor will, on a CP curve, appear left of the interface traps of the channel itself, even if no fixed positive charge is present. The analysis of Icp(VGL) curves is therefore a powerful technique to study distributions of electrically active defects in n- or p-channel transistors [5, 55, 66-78] as illustrated in Fig. 6.38 and Fig. 6.39. The decomposition of the CP characteristics of degraded devices makes it possible to perform numerical simulations to model and interpret the results [79-80]. Let us also mention the recent development of more specific techniques to determine the spatial distribution of the charge trapped in the oxide layer over the channel [81-83]. 10.3 APPLICATION TO THE DETECTION AND CHARACTERIZATION OF BORDER TRAPS

10.3.1. Definition The concept of "border trap" has been introduced by Fleetwood [84-86] to designate traps located in the oxide, but close to the interface, and capable of taking part in the electrical response of a MOS device under certain circumstances. The amount of border traps which exchange carriers with the substrate is strongly linked to the bias and frequency used. It is generally accepted that these traps interact with the valence or conduction bands of silicon through a tunnel mechanism, directly, or indirectly via fast interface traps [87-93]. This concept leads to several remarks about those interface states called slow states: i) slow states are generally observed when the Si/Si02 system is degraded (e.g. after injection or irradiation); ii) their emission time constant exceeds several seconds (even several hours), so their study is usually carried out by quasi-static or static C-V measurements; iii) these slow states are thought to be located in the oxide and some of them can be considered as border traps.

Charge Pumping

483

Techniques

It is thus important to note that the term "border trap" is strongly linked with the type of measurement technique performed on the device. For example, the largest time constants which can be characterized through CP measurement are typically about 10-^ s. Such a measurement only involves a fraction of slow states which are defined as border traps in the frame of a CP experiment. u

i.eo

a, 15.0 13.S

o

1.70

Slow states + (border traps)

12.0

1.60

+

u

T=l/f Fast states (interface traps)

^+++. . ^

>* 10.3

u

1.50 1.40

• 10 Mrad (Si02)

1.30

- ^ 9.0

1.20

G 7

1.10

Fast states (interface traps)

< 6

1.00

X

Virgin-

U 4

0.90

Q W 3

g s»

Fig. 6.40 ' The recombined charge per cycle Q^f is plotted versus frequency for a virgin device (lower curve and for the same device irradiated at 10 Mrad (Si02.) (upper curve) (After Autran et al. [91]).

O.BO

101

102

103

(04

105

FREQUENCY f (Hz)

10.3.2. Characterization using the standard CP technique The 2CP method using a trapezoidal gate signal at low frequency (less than IkHz) has been recently proposed by Paulsen and al [89-90] as a possible technique to characterize oxide traps located near the Si/Si02 interface. In this method, f varies while other parameters of the gate signal remain constant. • If only fast interface states exist in the interfacial region, the recombined charge per cycle is frequency-independent because all the states in the pumping window are able to exchange carriers and thus take a part in the charge pumping cycle. • But, if both slow and fast states co-exist, the pumped charge, at low frequency, increases when f decreases because slow states respond as soon as their time constant is compatible with the frequency of the gate signal. Figure 6.40 shows the low frequency CP response of a device before and after irradiation. Figure 6.40 shows that the measured value of Qj^ increases when f decreases below 600 Hz. This threshold or breakpoint frequency can be interpreted as the reverse of the time constant of the carrier exchange mechanism which takes place between the semiconductor and the nearest oxide traps. Analytical models of the tunneling mechanism have been developed which give the direct relationship between the time constant of the tunneling process x and the distance x separating the traps from the interface. Using the model proposed by Roy ([94] and quoted by Paulsen [89-90]), we have: *o f 2;cmj 1+

t(x) = -

1

-—^exp(27]ix)

r]2{hl2KyDu

(6.114)

484

J.L. Autran et al.

with 2 Vl =

2mj((l>B+Ec-Ef) 9

(h/2Kr 2

(6.115)

2m2(Ec-Ef)

^2 =

9

(h/2Kr where O B is the height of the potential barrier between the semiconductor and the oxide , m^* and m2* are respectively the mean mass of the electrons in the oxide and in the semiconductor and (EQ - Et), is the energy position of the trap. Figure 6.41 shows plots of x (x) using semi-logarithmic scales for different values of Dj^. If we use the breakpoint frequency evaluated in Fig. 6.40 and a Djt value of about 1012 eV-1 cm-2, this model yields, in this case, for the tunneling distance of radiation-induced border traps, a value between 1.5 and 2 nm. 10^ 10»

h

2 CO

C O

1•

L

10-' h

I

-1

y

/

/

y

Dit = 10 ^m^eV^ ^.^^^ / / / /

Dit = X^^^txi^ei'-^/// / y

/

\

J

/Irradiated Pure-oxide

10» 10-^

i 10-'

//// ' ^

r / /

/^

1

" ^ D j t = 10^\m'eV'

1

Ultra-thin Oxide SUNOS Device

10-^ \

io-»

Dit = 10 \m^eV'

/

/

/

/

1

10

15

1

1

20

25

A

Fig, 6.41 - Characteristic time constant of the tunneling process as a function of the tunneling distance of the traps (from the Si-Si02 interface), given for different values of D^^ and for E^' E^ = O.I eV (After Roy [100] quoted y Paulsen et al. [93]).

1

30

Tunneling Distance [A]

10.3.3, Evaluation of the border trap density using the dual-transistor technique Another method recently developed for the characterization of border traps is the DualTransistor Border Trap (DTBT) charge separation technique. This method, proposed by Fleetwood and coworkers [95-96], combines classical I-V and 2-CP measurements on both nand p-channel transistors fabricated with the same technology. It can provide reasonable quantitative estimates of border trap density by separating the respective contributions of fast interface traps, oxide traps and border traps to n- and p-channel V^ shifts. • The charge-separation method is based on the exploitation of the differences between the communication times of interface, border and oxide traps with the silicon substrate. Two consecutive I-V and 2CP measurements are performed on each transistor:

Charge Pumping Techniques

485

I-V measurements: in this standard I-V technique, the voltage sweep allows part of the interface and border traps to exchange carriers with the underlying silicon, typically in an effective frequency range of -- 1 Hz. All the traps, which cannot exchange carriers in less than -- 1 s, are then called fixed states. Because these traps cannot be separated from the bulk oxide charge, from an electrical point of view, this first measurement leads to a quantitative (higher bound) evaluation of the density of so-called "oxide traps". High-frequency charge pumping measurements: by performing a complementary charge pumping measurement at a frequency of -- 1 MHz, it is possible to separate interface traps from border traps which are electrically active in the ~ 1-10^ Hz frequency range. This second measurement yields thus an estimate of the densities of fast interface traps (which respond in less than ~ 10-^ s) and "border traps" (on time scales between 10-6 to 1 s). • It is important to note that for each transistor type, the energy domains scanned in the bandgap are different. In particular, only interface and border traps in the upper part of the bandgap contribute to the n-channel V^ shifts, while traps in the lower part of the bandgap contribute to the p-channel Vy shifts. As reported in § 5.4.1, the portion of the energy bandgap scanned with the 2CP technique depends on several parameters and especially on the doping concentration at the silicon surface. The doping levels are generally not the same for n-channel and p-channel devices. This difference must be taken into account for an accurate determination of the border trap density. • From an analytical point of view, the n-channel and p-channel V j shifts (AV^) due to the contributions of bulk oxide traps (AV^^), interface traps (AVj^) and border traps (AV^t) can be expressed as follows [96]: AVTn = AV^,^ + AVi,^ + AVi,t^

(6.116)

AVjp = AV^,p + AVi,p + AVi,tp

(6.117)

where subscripts n and p indicate the transistor type. If the transitors have been simultaneously fabricated and degraded (in particular by the same electric field measured during the degradation), it is reasonable to consider that the bulk oxide charge densities for both transistor types are the same, i.e. that AY^^^ « AV^^^ « AWQ^. Assuming that interface and border traps predominantly cause the n-channel V^ to shift positively and the p-channel V j to shift negatively, we can introduce the following notations: AVj^^ = S^, AVj^p = - Sp, AV^^n = yB, AV^tp = - (1 - Y) B, AVQ^ = - H, where S^, Sp, H and B are positive quantities. B is the total density of border traps in the accessible energy range of the silicon bangap and y is the effective fraction of the total border trap charge density that resides in the upper part of the bandgap. With these new variables, Eqs. (6.116) and (6.117) become: AVrn^-H+S^

+ yB

AVTp = -H-^Sp-(l-y)B

(6.118) (6.119)

486

7.L. Autran et aL

Substracting Eq. (6.119) from Eq. (6.118), we obtain: B = (AVrn - ^VTp) - (Sn + V

(6.120)

Quantities S^ and Sp are evaluated from standard charge pumping measurements at - 1 MHz (in order to only involve interface traps during the measurement). We get:

""^

Co.

'^

C,,

(6.121)

where ^^^ and ^gp ^ ^ respectively the n-channel and p-channel bulk potentials. Combining this set of equations into Eqs. (6.118) to (6.120), we obtain: / X B^[AVTn-^VTpj-

^(^itn¥Bn+^itp¥Bp)

(6.122)

1

«.-

^^

•-

r^-[r-2}^

(«-'23,

Since the exact value of yis not known, Fleetwood and coworkers assume that Y « 1/2. This value leads to equal border trap densities (which are physically oxide traps) for both n- and pchannel devices (degraded in the same conditions). The final expressions of the interface, border and oxide trap densities can thus be expressed as follows: ANit =

^

ANht =

^

^ « (^itn¥Bn + ^itpVBp)

^ - (ADi,„yfBn + ^itp¥Bp }

(6-124)

(6-125)

ri CO^[AVT„+AVTP)

^ot

=

^

ADjtnWBn-^itpWBp + 2

,^ ,,^, (6-126)

The oxide charge density is calculated assuming that oxide traps are close to the Si/Si02 interface, like the interface and border traps. In case of a distributed density of traps inside the oxide layer, an additional factor accounting for the charge centroid appears:

487

Charge Pumping Techniques

Co^t„:,[AVTn+^y'Tp ) ^ot

=

tox(^itn¥Bn

2qx

"

^itpWBp)

2x

(6.127)

where x is the distance from the gate to the centroid of the bulk oxide trap distribution. In the important particular case of the charge being distributed uniformly through the gate oxide (in this case x = tox/2), Eq. (6.127) simplifies into C,,[AVTn+AVTp) ANot =

ADitnYBn-ADitpYBp

(6.128)

Figure 6.42 illustrates how the DTBT evaluation technique has been used to monitor ANQJ, ANjt and AN^j in irradiated transistors. Note the respective evolutions of the three densities of traps after 25°C and 100°C anneals. 30 • 6 V, 25*C Anneal

E ^

H^

6 V, 1 0 0 X Anneal

Bulk Oxide Traps 10

O

(A C

Border Traps

Interface Traps _L

I

I I I I I ll

103

10^

L.

I

I I I ll

I

105

I

I

I I I I I

106

Fig. 6.42 - Plots ofANou ^it and ANbt vs. irradiation and anneal time for MOS transistors with non-hardened 50-nm oxides irradiated with 10-keV X-rays at a dose rate of - 9.5 krad (SiOiVmin and annealed at 25°C for ~ 12 hours and at 100°C for ~ I week. The bias applied during irradiation and during anneal was 6V (After Fleetwood et al. [97])

Irradiation and Anneal Time (s) 10.4. APPLICATION TO THE EVALUATION OF GRAIN BOUNDARY TRAPS IN POLYSILICON

TFTs Polysilicon thin-film transistors (poly-Si TFTs) have been extensively investigated in recent years because of their attractive applications to large-area electronics and display devices. It is well known that the electrical characteristics of poly-Si TFTs are significantly influenced by grain boundary traps (GBT) since the source-drain current flows through the polysilicon layer (a cross section of such a transistor can be found in Fig. 2.13 of this volume). It is thus very important to accurately evaluate the properties of these GBTs in TFTs, from an electrical point of view. The methods used to evaluate the GBTs and reported so far, are mainly based on measuring the channel current of the TFT. This current is affected by the potential barrier due to the presence of the grain boundaries. It is thus not directly related to the GBT properties themselves [98]. In order to assess these properties more accurately, it is necessary to measure a current more directly related to the traps. The CP technique is suitable for this purpose because the electron-hole recombination current taking place through the grain boundary traps dominates the CP current [99-102]. Hence, this CP current directly represents the GBT properties.

488

J,L, Autran et al.

10.4.1. Typical CP characteristics in poly-Si TFTs A typical set of 2CP curvqs (i.e I^p vs VQL) is shown in Fig. 6.43 a. In the figure, the pulse width is changed as a parameter under the fixed pulse period of 100 |Lis. We note that the CP current decreases as the pulse width increases since the time to supply holes becomes shorter under the constant pulse period. Such CP characteristics are similar to those obtained in MOSFETs. Here the GBTs play a role similar to that played by interface states in MOSFETs. From Fig. 6.43 a, one may conclude that a large number of acceptor-like and donor-like traps exist at the grain boundary in low-temperature TFTs because Wj has shifted toward more negative VQL values and Vpg toward more positive VQL values in the non-equilibrium conditions (i.e. for short durations of the pulse width). The holes captured in the donor-like traps at the grain boundary near the surface recombine with electrons supplied by the source when the surface switches from accumulation to inversion. Similarly, the electrons captured in the acceptor-like traps recombine with holes supplied through the body terminals when the surface switches from inversion to accumulation. The influence of process temperature is illustrated in Fig. 6.43 b. A sharp reduction in CP current is observed in the case of high-temperature TFTs (maximum process temperature of « 950°C). We also observe a shift of Vpg towards positive voltages, and a shift of V j toward negative voltages when process temperature is increased. These shifts can be interpreted as being due to a significant reduction in the density of acceptor-like and donor-like traps, in the case of high-temperature TFTs. 10.4.2. Density of grain boundary traps The energy distribution Djt(E) of GBT's can be obtained by evaluating how the CP current depends on the pulse fall time tf (or rise time t^) as detailed in § 6.2. We can thus obtain the Grain Boundary Trap density Dt(E) from Eqs. (6.59) and (6.62) respectively, in part of the upper half and lower half of the silicon bandgap (see § 6.2). Figure 6.44 shows an example of the GET density for high- and mid-temperature CP curves measured on TFTs. In this case, the GET density is significantly lower in hightemperature TFTs but increases toward the conduction band edge in this case. 11. CONCLUSION In the last fifteen years, charge pumping techniques have proved to be useful in such areas as the analysis of uniform and non-uniform interface degradations, the study of aging phenomena, the study of SOI structures [103-105] and power MOSFETs [106-108], etc. The main assets of these techniques are that measurements can be performed directly on the transistors themselves even when these are of submicrometer dimensions. They give access to the Dit(E) and a(E) distributions, and can yield the spatial D^^ix) distribution, especially in the vicinity of the drain. Their main features are summarized in Fig. 6.45.

489

Charge Pumping Techniques 1200

1200

-12

- 8 - 4

0

4

- 1 2 - 8 -4 0 4 Pulse Base Voltage Vci- (V)

Pulse Base Voltage Vet. (V)

Fig, 6.43 (a) - Dependence of the 2CP current on VQI in a low-temperature TFT (maximum process temperature of 600°C) with VQJJ = lOV and f=IO kHz (After Koyanagi et al [100]). 20

'> 0)

4->

1

I

I

I

Fig. 6.43 (b) - Comparison of the CP characteristics for medium temperature and hightemperature TFTs with VQH = IOV, f = 10 kHz, pulse width = 20 f4s (After Koyanagi et al. [100]).

»

• Mid Temp. f=100kHz A M i d T e m p . f= lOkHz • M i d T e m p . f= IkHz

1 6 h

N

cn c

'eo

Q

""O

a

X

CO

u

H

Fig. 6.44 - Energy distributions of the GBT density for low - and high-temperature TFTs (After Koyanagi et al. [100]).

-...•' OOkHz 1 OkHz 1 kHz

H i sr h T e m p . H i sr h T e m p. H i gh T e m p .

+J

.oSfig/. OOQO'

0.

1

Energy

0. 2

E-Ei

0. 3

0. 4

(eV)

Recently, low-frequency CP techniques have shown to be promising in the study of emission and capture processes with long time constants and in the electrical characterization of defects in the interfacial area. More recently, it has been shown that it is possible to observe and characterize individual traps in the gate area of very small metal-oxide-semiconductor field-effect transistors (MOSFETs) [109-110]: the obtained CP characteristics do not have the classical "top-hat" shape but reveal the contribution of each trap, and the individual CP response of a single trap is easy to obtain by deconvolution of the global CP current.

490

J.L. Autran et al. STANDARD Usable Waveforms

3-LEVEL

n

f\.\

/V A I V .

Device Temperature

fixed

fixed

Extracted Parameters

Du(E)

Dit(E) a(E)

Approximation used Explorable Energy Range

SPECTROSCOPIC 1

variable (e.g. 7 7 - 4 0 0 K)

|

Di,

1

Dit(E)

CT„ =CTp= Cte

Ey

Ej

Ec ^

«Jn = S = ^^

Ev

Ei

Ec ^ Ey

Ej

Ec ^

F/g. 6.^5 - Summary of the m^xin features of charge pumping techniques

As the dimensions of elementary transistors keep shrinking with progress in device integration, charge pumping techniques are regarded as the only techniques left, capable of characterizing the quality of the Si-Si02 interface directly in the channel area. These techniques should thus remain popular and keep developing in the near future. ACKNOWLEDGEMENTS The authors gratefully acknowledge the helpful contribution of Jose Autran (University of Nice Sophia-Antipolis) to this work. They especially thank Bernard Leroy and Louis-Marie Gaborieau (IBM, IC Manufacturing Plant of Corbeil-Essonnes) for their sustained interest and support. Special thanks are due to their colleagues Sylvie Pierunek, Christophe Raynaud, Carole Plossu, Frederic Seigneur, Christophe Chaneliere, Pascal Masson (INSA de Lyon), Roderick Devine (France Telecom, CNET-Meylan), Jean-Luc Leray, Philippe Paillet, Olivier Flament, and Olivier Musseau (CEA Bruyeres-Le-Chatel), Christian Chabrerie and JeanClaude Boudenot (Thomson CSF Conmiunications) for stimulating discussions. Special thanks are also due to Pr. Andre Vapaille who thoroughly reviewed this text and contributed many useful suggestions.

Charge Pumping Techniques

491

LIST OF REFERENCES [I] [2] [3] [4] [5] [6] [7] [8] [9] [10] [II] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43]

Barbottin G. and Vapaille A. (Editors), Instabilities in Silicon Devices (North-Holland : Elsevier Science Publishers B.V.), 1986 and 1989. Brugler J.S., Jespers P.G.A., IEEE Trans. Electron Devices, 1969,16, 297. Van Den Bosch G., Groeseneken G., Maes H.E., IEEE Electron Device Lett., 1993,14, 107. Declercq M., Jespers P.G.A., Acta Tech. Belgica, 191 A, 9, 244. Heremans P., Witter S J., Groeseneken G., Maes H., IEEE Trans. Electron Devices, 1989, 36, 1318. Elliot A.B.M., Solid-State Electron., 1976,19, 241. Golder J., Baldinger E., Helv. Phys. Acta, 1971, 44, 387. Leuenberger F., Phys. Stat. Sol. (a), 1971, 8, 545. Shuermeyer F.L., Young C.R., Sutton W.G. IEEE Trans. Electron Devices, 1977, 24, 552. Owczarek A., Kolodziejski J.F., Electron Technology, 1977, 10, 55. Maes H.E., Groeseneken G., Electron. Lett., 1982,18, 372. Backensto W.V., Viswanathan C.R., lEE Proc, 1981,128, 44. Schmitt D., Dorda G. Electron. Lett., 1981,17, 762. Takeda E., Shimizu A., Hagiwara T., IEEE Trans. Electron Device Lett., 1983, 4, 329. Simmons J.G., Wei L.S., Solid-State Electron., 1973,16, 53. Shockley W., Read W.T. Jr., Phys. Rev., 1952, 87, 836. Hall R.N., Phys. Rev.. 1952, 87, 387. Kaden G., Reimer H., Phys. Stat. Sol. (a), 1975, 32, 183. Kaden G., Reimer H. Phys. Stat. Sol. (a), 1977, 44, 117. Kaden G., Reimer H. Phys. Stat. Sol. (a), 1979, 52, 35. Kaden G., Reimer H. Phys. Stat. Sol. (a), 1979, 53, 195 Kaden G., Reimer H. Phys. Stat. Sol. (a), 1980, 59, 719. Groeseneken G., Maes H.E., Beltran N., De Keersmaecker R.F., Insulating Films on Semiconductors Conf. Proc. (Eindhoven : Elsevier Science Publishers), 1983, 153. Groeseneken G., Maes H.E., Beltran N., De Keersmaecker R.F., IEEE Trans. Electron Devices, 1984, 31, 42. Cilingiroglu U., Solid-State Electron., 1985, 28, 1127. Wachnik R.A., Lowney J.R., Solid-State Electron., 1986, 29,447. Van Den Bosch G., Groeseneken G., Heremans P., Maes H.E., European Solid State Res. Conf. Proc. (Nottingham : lOP Publishing Ldt), 1990, 579. Van Den Bosch G., Groeseneken G., Heremans P., Maes H.E., IEEE Trans. Electron Devices, 38, 1820. Balland B., Plossu C , Lubowiecki V., Ledys J.L., Rev. Phys. AppL, 1988, 23, 1837. Autran J.L., Ph.D. Thesis (Villeurbanne : Institut National des Sciences Appliquees), 1994. Sze S.M., Physics of Semiconductor Devices (New-York : Wiley & Sons), 1966. Plossu C , Lubowiecki V., Balland B. Solid-State Commun., 1988, 65, 1231. Henning A.K., Dimauro J.A. Electron. Lett., 1991, 27, 1445. Ancona M.G., Saks N.S., McCarthy D., IEEE Trans. Electron Devices, 1988, 35, 2221. Saks N.S., Ancona M.G. ffiEE Trans. Electron Devices, 1990, 37,1057. Latyshev A.V, Lisovskii G., Lomako V., Soviet Techn. Phys. Lett., 1991, 17,710. Shaw J-J., Wu K., Int. Electron Device Meeting Tech. Dig., 1989, 83. Li X.M., Deen J., Int. Electron Device Meeting Tech. Dig., 1990, 85. Li X.M., Deen.J., Solid-State Electron., 1992, 35, 1059. Autran JL., Seigneur F., Plossu C., Delmas J., Balland B., J. Phys. III., 1993, 3, 1947. Tseng W.L. J. Appl. Phys., 1987, 62, 591. Chung J.E., MuUer R. S., Solid-State Electron., 1989, 32, 867. NicoUian E.H. and Brews J.R., MOS (Metal Oxide Semiconductor) Physics and Technology, (New-York : Wiley & Sons), 1982.

492

[44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] [59] [60] [61] [62] [63] [64] [65] [66] [67] [68] [69] [70] [71] [72] [73] [74] [75] [76] [77] [78] [79] [80] [81] [82] [83] [84] [85] [86]

/ . L . Autran et al.

Hofmann F., Krautschneider W.H., / AppL Phys., 1989, 65, 1358. Przyrembel G., Krautschneider W.H., Soppa W., Wagemann H.G., European Solid State Res. Conf. Proc. (Bologna: Technoprint),1987, 687. Saks N.S., Ancona M.G. IEEE Electron Device Lett., 1990,11, 339. Saks N.S., Ancona M.G., Chen W., Insulating Films on Semiconductors Conf. Proc. (Eindhoven : Elsevier Science Publishers), 1991, 139. Ancona M.G., Saks N.S. J. Appl. Phys., 1992, 71,4415. Kejhar M., IEEE Electron Device Lett., 1992,13, 344. Autran J.L., Balland B., Rev. Sci. Instrum., 1994, 65, 2141. Ziegler K., Klausmann E., Appl. Phys. Lett., 1975, 26,400. Nicollian E.H., Goetzberger A , Bell Syst. Tech. /., 1967, 1055. Ghibaudo G., Saks N.S. /. Appl. Phys., 1988, 64,4751. Ghibaudo G., Saks N.S. J. Appl. Phys., 1989, 65,4311. Hofmann P., Hansch W. J. Appl Phys., 1989, 66, 3092. Van Overstraeten R.J., Declerck G.J., Muls P.A., IEEE Trans. Electron Devices, 1975, 22, 282. McWhorter P.J., Fleetwood D.M., Pastorek R.A., Zimmerman G.T., IEEE Trans. Nucl. Sci., 1989, 36, 1792. Nguyen-due C., Ghibaudo G., Balestra F., Phys. Stat. Sol. (a), 1991,126, 553. Schwank J.R., Reetwood D.M., Shaneyfelt M.R., Winokur P.S., IEEE Trans. Nucl. Sci., 1993, 40, 1666. Papadas C , Revil N., Ghibaudo G., Mortini P., Pananakakis G., European Solid State Res. Conf. Proc. (Grenoble : Editions frontidres),1993, 543. Moragues J.M., Oualid J., Jerisian R., Ciantar E., /. Appl. Phys., 1993,74, 5078. Saks N.S., Ancona M.G., IEEE Trans. Nucl. Sci., 1987, 34, 1348. Nishioka Y., da Silva E.F., Ma T.P., Appl. Phys. Lett., 1988, 52,720. Heyns M.M., European Solid State Res. Conf Proc. (Nottingham : lOP Publishing Ldt), 1990, 361. Witter J.S., Groeseneken G., Maes H.E., Int. Electron Dev. Meeting Tech. Dig., 1987, 544. Djahli F., Autran J.L., Plossu C., Balland B., Mat. Sci. Eng. B, 1994, 23, 120. Maes H.E., Groeseneken G., Heremans P., Bellens R., Appl. Surf. Sci., 1989, 39, 523. Heremans P., Bellens R., Groeseneken G., Maes H.E., IEEE Trans. Electron Devices, 1988, 35, 2194. Bellens R., Heremans P., Groeseneken G., Maes H.E., IEEE Electron Device Lett., 1988, 9, 232. Maes H.E., Heremans P., Bellens R., Groeseneken G. Quality and Reliability Engineering International, 1991,7,307. Houdt J.v., Heremans P., Deferm L., Groeseneken G., Maes H.E., IEEE Trans. Electron Devices, 1992, 39,1150. Revil N., Cristoloveanu S., Mortini P., Microelec. Eng., 1992,19, 461. Das N.C., Nathan V., J. Appl. Phys., 1993, 74,7596. Das N.C., Nathan V., Semicond. Sci. Technol., 1993, 8, 549. Chen W., Balasinski A., Zhang B., Ma T.P., IEEE Electron Device Lett., 1992,13, 201. Chen W., Ma T.P., IEEE Electron Device Lett., 1992,13, 319. Woltjer R., Hamada A., Takeda E., Semicond. Sci. Technol., 1992, 7, B581 Bellens R., Groeseneken G., Heremans P., Maes H.E., Microelec. Eng., 1992,19,465. Vuillaume D., Marcheteaux J.C., Boudou A., IEEE Electron Device Lett., 1991,12, 60. Habas P., Solid-State Electron., 1995, 38, 891. Chen W., Balasinski A., Ma T., IEEE Trans. Nucl. Sci., 1991, 38, 1124. Tsuchiaki M., Hara H., Morimoto T., Iwai H., IEEE Trans. Electron Devices, 1993,40, 1768. Lee R.G.H., Su J.S., Chung S.S., IEEE Trans. Electron Devices, 1996, 43, 81. Fleetwood D.M., IEEE Trans. Nucl. Sci., 1992, 39(4), 269. Fleetwood D.M., Winokur P.S., Reber R.A., Meisenheimer T.L., Schwank J.R., Shaneyfelt M.R., Riewe L.C., J. Appl. Phys., 1993, 73, 5058. Fleetwood D.M., IEEE Trans. Nucl. Sci., 1996, 43, 779.

Charge Pumping Techniques [87] [88] [89] [90] [91] [92] [93] [94] [95] [96] [97] [98] [99] [100] [101] [102] [103] [104] [105] [106] [107] [108] [109] [110]

493

Dniijf K.G., de Nijs J.M.M., van der Drift E., Granneman E.H.A. and Balk P., Microelectron. Eng., 1993, 22,231. Kerber M., Appl. Phys, Lett,, 1991, 56, 3416. Paulsen R.E., Siergiej R.R., French M. L. and White M.H., IEEE Electron Device Lett., 1992,13, 627. Paulsen R.E. and White M.H., IEEE Trans, Electron Devices,l994, 41, 1213. Autran J.L., Balland B. and Babot D., J, Non-Cryst, Solids,l995,187, 211. Bauza D. and Ghibaudo G., Solid-State Electron,, 1996, 39, 563. Warren W.L., Shaneyfelt M.R., Fleetwood D.M., Schwank J.R., Winokur P.S. and Devine R.A.B., IEEE Trans, Nucl. Sci„ 1994, 41, 1817. Roy A., Ph,D, Dissertation (Bethlehem, PA : Lehigh Univeristy), 1989. Schwank J.R., Fleetwood D.lVl., Shaneyfelt M.R., Winokur P.S., IEEE Trans, Nucl. ScL, 1993, 40, 1666. Fleetwood D.lVl., Shaneyfelt M.R., Warren W.L., Schwank J.R., Meisenheimer T.L., Winokur P.S., Microelectron. Reliab., 1995, 35, 403. Fleetwood D.M., Shaneyfelt M.R., Schwank J.R., Appl. Phys. Lett., 1994, 64, 1965. Levinson L., /. Appl. Phys., 1982, 53, 1193. Koyanagi M., Baba Y., Hata K., Wu I.W., Lewis A.G., Fuse M., Bruce R., Int. Electron Device Meeting Tech. Dig., 1990, 863. Koyanagi M., Baba Y., Hata K., Wu I.W., Lewis A.G., Fuse M., Bruce R., IEEE Electron Device Lett., 1992, 13, 152. Balasinski A., Sundaresan R., Hodges R., Huang K.W., Worley J., Liou F.T., Electrochem, Soc, Meeting Proc, (Miami Beach : The Electrochemical Society), 1994. Saks N.S., Batra S., IVIanning M,, Microelectr Eng, 1995, 28, 379. Wouters D.J., Tack, M.R., Groeseneken G., Maes H.E., Claeys C.L., IEEE Trans. Electron Devices, 1989,36,1746. Ouisse T., Cristoloveanu S., Elewa T., Haddara H., Borel B., loannou D.E, IEEE Trans. Electron Devices, 1991, 38, 1432. Li Y., Wang G., Ma T.P., Int. Electron Device Meeting Tech. Dig., 1995, 643. Habas P., Prijic Z., Pantic D., Microelectr Eng„ 1995, 28, 171. Prevost G., Augier P., Palau J.M., RADECS Proc, IEEE Catalog Number 95TH8147, 1995, 230. Witczak S.C, Galloway K.F., Schrimpf R.D., Titus J.L., Brews J.R., Prevost G., IEEE Trans, Nucl. ScL, 1996, 43, 2558. Saks N.S., Groeseneken G., De Wolf I., Appl, Phys, Lett,, 1996, 68, 1383. Groeseneken G., De Wolf I., Bellens R., Maes H.E., IEEE Trans, Electron Devices, 1996, 43, 940.

This Page Intentionally Left Blank

INSTABILITIES IN SILICON DEVICES Silicon Passivation and Related Instabilities G. Barbottin and A. Vapaille (Editors) © 1999 Elsevier Science B.V. All rights reserved.

495

CHAPTER 7

THE STUDY OF THERMAL NITRIDATION AND REOXIDATION MECHANISMS USING ISOTOPIC TRACING METHODS by J.-J. GANEM(i) and J.J.R. BAUMV0L(2)

Key items Nuclear reaction analysis Nuclear narrow resonance Isotopic tracing Thermal nitridation Thermal reoxidation Silicon oxynitride films Growth mechanisms Atomic exchanges

(I) Universite Pierre et Marie Curie Groupe de Physique des Solides T-23.2 Place Jussieu 75251 Paris Cedex 05, France

(2) Instituto de Fisica UFRGS Porto Alegre, RS 91540-000, Brazil

496

/./. Ganem and IJ,R. Baumvol

Abstract of Chapter 7. The study of thermal nitridation and reoxidation mechanisms using isotopic tracing methods. The electrical properties of thin films of silicon nitride and silicon oxynitride are closely linked to their structure and atomic composition. These in turn depend on growth mechanisms which were not well understood up to now. In this chapter, we show that the growth of films in well-controlled ambients (alternately natural and isotopically-enriched) combined with high-resolution profiling techniques, enable one to describe, on an atomic scale, the transport and exchange mechanisms taking place. We first recall the fundamentals of isotopic tracing and we describe two techniques used to measure the indepth concentration profiles: step-by-step chemical etching associated with an absolute quantitative analysis using Nuclear Reaction Analysis, and low-energy Nuclear (narrow) Resonance Profiling. By applying these two techniques to the thermal growth of nitride films, carried out on a silicon substrate in gaseous ammonia, we can clarify the part that each chemical species play. We show that film growth is due to the interstitial migration ofNH^ groups. Hydrogen liberated during nitridation diffuses towards the top surface of the nitride film. Likewise, these techniques show that the nitridation of silica in gaseous ammonia is due to the interstitial diffusion of NH^ groups. This diffusion is however accompanied by an atomic exchange (O atoms being substituted by N atoms) taking place near the top surface of the film. During the reoxidation of oxynitride films, these techniques show that the interstitial diffusion of oxygen is accompanied by an (N—>0) exchange and by a decrease in hydrogen content due to the formation of water vapor. The thermal growth of silicon oxynitride films can also be performed in a single step, using gaseous N2O. In this case, the films are devoid of hydrogen and nitrogen remains located near the Si/Si02 interface. Finally, when these oxynitride films are reoxidized, the interstitial diffusion of oxygen is accompanied by an important (0—MD) exchange and by a global loss of nitrogen which migrates towards the top surface. Resume du chapitre 7.: Etude des mecanismes de nitruration thermique et de reoxydation par les methodes de tragage isotopique, Les proprietes electriques des films minces de nitrure et d'oxynitrure de silicium sont etroitement liees a leur structure et a leur composition atomique qui, a leur tour, dependent de mecanismes de croissance qui etaient jusqu 'a present mal connus. On montre dans ce chapitre, que la croissance de films dans des atmospheres controlees, alternativement naturelles et enrichies, couplee a des techniques de profilage isotopique a haute resolution, permet de decrire a I'echelle atomique les mecanismes de transport et d'echange. On rappelle, tout d'abord, le principe du tragage isotopique et I'on decrit deux techniques de mesure des profits de concentration : la dissolution chimique pas-a-pas associee a la determination absolue des constituants par reaction nucleaire, et le profilage a basse energie par reaction nucleaire resonante etroite. L 'application de ces deux techniques lors de la croissance thermique de films de nitrure, sur des substrats de silicium dans I 'ammoniac gazeux, permet de clarifier le role des especes chimiques mises en Jeu. On montre que la croissance dufilm est due a la migration interstitielle de groupements NHx- L 'hydrogene libere lors de la nitruration diffuse vers la surface dufilm. De meme, ces techniques montrent que la nitruration de la si lice dans I 'ammoniac gazeux est egalement due a la diffusion interstitielle des groupements NH^ Toutefois, cette diffusion s'accompagne d'un echange atomique (0->N), qui a lieu essentiellement pres de la surface. Lors de la reoxydation de films d'oxynitrure, ces techniques de tragage montrent que la diffusion interstitielle de I'oxygene s'accompagne d'un echange atomique (N—>0) et d'une diminution de la teneur en hydrogene due a la formation de vapeur d'eau. La croissance thermique sous N2O permet de former en une seule etape et sans incorporer d'hydrogene, des films d 'oxynitrure dans lesquels I 'azote est situe pres de I 'interface. Enfin, lors de la reoxydation de ces films d'oxynitrure, la diffusion interstitielle de I'oxygene s'accompagne d'un echange (0—>0) tres important, et d'uneperte d'azote, ce dernier migrant, globalement, vers la surface.

The Study of Thermal Nitridation

497

Zusammenfassung zu Kapitel 7: Die Untersuchung thermischer Nitridierrungs- und Reoxidationsmechanismen durch isotopische Tracer-Methoden Die elektrischen Eigenschaften dUnner Filme aus Silizium-Nitrid und Silizium-Oxynitrid sind mit ihrer Struktur un ihrer atomaren Struktur eng verbunden. Dieses wiederum hdngt mit den Wachtumsmechanismen zusammen, die jedoch bis heute nicht sehr gut verstanden sind. In diesem Kapitel ziegen wir, dap das Schichtwachstum in kontrollierter Umgebung (entweder natiirlich oder isotopisch angereichert), verbunden mit der Anwendung hochempfindlicher Tiefenprofil-Mep\;erfahren, uns die Beschreibung der Transport- und Austauschmechanismen im atomaren MajSstab erlauben. Zunachst bringen wir die Grundlagen der Isotopen-Analyse in Erinnerung und beschreiben zwei Methoden, die verwendet werden, um Tiefenprofile der Zusammensetzung zu bestimmen: stufenweise chemische Atzschritte verbunden mit der absoluten Bestimmung durch Nukleare Reaktions-Analyse und Niederenergie(scharfe) Resonanz-Profdierung. Bei Anwendung dieser beiden Methoden aufdas thermische Aujwachsen von Nitrid-Schichten, auf SiliziumSubstrate, in gasformigem Ammoniak, konnten wir die Rolle, die jeder beteiligte Partner spielte, aufdecken. Wir zeigen, das das Schichtwachstum durch Zwischengitter-Wanderung von NH^-Gruppen geprdgt ist Wasserstoff, freigesetzt wahrend der Nitridierung, diffundiert zur vorderseitigen Oberfldche der Nitrid-Schicht. Ebenso zeigen diese Methoden, daP die Nitridierung von Siliziumoxid in gasformigem Ammoniak durch Zwischengitter-Diffusion von NH^-Gruppen erfolgt. Diese Diffusion wird jedoch begleitet durch atomaren Austausch (O-Atome werden durch N-Atome substituiert) nahe der Oberfldche der Schicht. Bei der Reoxidation von Oxynitrid-Schichten zeigen diese Methoden, dap die Zwischengitter-Diffusion begleitet wird durch einen Austausch (N —> O) und eine Abnahme der Wasserstoff-Konzentration, hervorgerufen durch die Bildung von Wasserdampf Das thermische Wachstum von Oxinitrid-Schichten kann in einem Schritt durch die Wahl von gasformigem N2O durchgefuhrt werden. In diesem Fall sind die Schichten arm an Wasserstoff und der Stickstoff bleibt nahe der Si/SiO 2-Phasengrenze. Werden diese Oxynitrid-Schichten schliesslich reoxidiert, so wird die Zwischengitter-Diffusion durch einen wichtigen (O -> O) Austausch begleitet, ebenso durch einen allgemeinen Verlust an Stickstoff der zur oberen Oberfldche wandert.

498

/./. Ganem and IJ.R, Baumvol

Chapter 7: The study of thermal nitridation and reoxidation mechanisms using isotopic tracing methods Table of contents 1. Introduction to labelling techniques 1.1. Fundamentals of isotopic tracing 1.2. Determination of depth concentration profiles in very thin dielectric layers 1.2.1. Review of currently used techniques 1.2.2. Fundamentals of Nuclear Reaction Analysis (NRA) 1.2.3. Examples of results obtained by combining NRA with step-by-step chemical etching 1.2.4. Fundamentals of Nuclear reaction Resonance Profiling (NRP) 1.2.5. Examples of results obtained by NRP 2. Mechanisms of thermal growth of silicon nitride films 2.1. Motion of nitrogen 2.2. Motion of hydrogen 2.3. Non-motion of silicon 2.4. Conclusion 3. Mechanisms of thermal nitridation of silica films 3.1. Most likely chemical reactions 3.2. Motion of nitrogen 3.3. Exchange phenomena during nitridation 3.4. Discussion and conclusion 4. Mechanisms of thermal reoxidation of oxynitride films 4.1. Role of oxygen 4.2. The combined role of oxygen and hydrogen 4.3. Role of nitrogen 4.4. Exchange mechanisms 4.5. Symmetrical behavior of the exchange mechanisms 5. Oxynitride films grown in N2O 5.1. Thermal treatment in N2O. A relatively new process 5.2. Growth kinetics 5.2.1. Time dependence 5.2.2. Pressure dependence 5.3. Motion of nitrogen during growth 5.4. Atomic transport mechanisms during growth in N2O 5.5. Reoxidation of N20-based oxynitrides 6. Conclusion List of references

The Study of Thermal Nitridation

499

1. INTRODUCTION TO LABELLING TECHNIQUES The electrical properties of thermal silicon nitride and oxynitride films are tightly linked to their structure and composition, the latter being, in turn, closely related to the growth mechanisms. Although numerous experimental results about the growth kinetics of these films, as well as about the kinetics of nitrogen incorporation into Si02 films, have been published, these results do not provide all the information necessary to model the nitridation process. A good understanding of the atomic transport mechanisms, and of the various chemical reactions which take place between the nitriding species and the growing dielectric film, is mandatory to improve the reliability of such dielectrics. ! • ! . FUNDAMENTALS OF ISOTOPIC TRACING

Isotopic tracing is potentially the most powerful tool available today to determine, on an atomic scale, the mechanisms at work during the thermal treatment of dielectric films. The method has been widely explained by S. Rigo in Chap. 1 of Vol. 1 of this book series [23]. Regarding the thermal oxidation of silicon, isotopic tracing has yielded vital information about the growth mechanisms. More recently it has been extensively used to understand the initial stages of "dry" oxidation which remains a subject of scientific debate [1,2]. The labelling of a given atom makes it possible to follow its migration in the growing dielectric film. To achieve this, the element to be traced should have a stable and rare isotope. Fortunately, this is true of the constituents of silicon nitride and oxynitride films (i.e. Si, O, N and H) as shown in the first column of Table 7.1. Isotopic tracing during thermal growth consists in performing thermal treatments alternately in natural and in isotope-enriched atmospheres, and in determining the in-depth concentration profile of the labelled isotope. By comparing the experimental depth profiles to theoretical profiles obtained through a probabilistic modeling of the atomic transport mechanisms [3], one can identify the growth mechanisms. 1.2. DETERMINATION OF DEPTH CONCENTRATION PROFILES IN VERY THIN DIELECTRIC LAYERS

1.2.1. Review of currently used techniques To measure the depth concentration profiles of the various elements encountered in thin layers of silicon nitride (< 6 nm) and silicon oxynitride (< 15 nm), we must use a high resolution depth analysis technique. A good depth resolution is particularly necessary in this case because (as we shall see next) concentrations vary rapidly underneath the surface of the growing film and at the dielectric/silicon interface. Secondary Ion Mass Spectroscopy (SIMS), although very sensitive to the atomic masses of the elements encountered in nitrides and oxynitrides, is difficult to use for very thin films because of transitory effects. These effects take place during the initial stage of sputtering and during the sputtering of interfaces (where the medium varies rapidly), and degrade both depth resolution and sensitivity.

500

JJ, Ganem and IJ,R: Baumvol

Alternative techniques must thus be used. Let us mention here the most commonly used ones: • Sputter-Auger Electron Spectroscopy (Sputter-AES), • X-ray Photoelectron Spectroscopy associated with chemical etching (XPS-chemical etching), • Medium Energy Ion Scattering (MEIS), • Nuclear Reaction Analysis associated with chemical etching (NRA-chemical etching), and • narrow Nuclear reaction Resonance Profiling (NRP). So far, only the last two methods have been successfully used to measure the migration of labelled atoms (isotopes) during the thermal growth of silicon nitrides and oxynitrides. They both possess the following suitable characteristics: i) a good in-depth resolution (better than 1 nm near the surface), ii) a high sensitivity for all the isotopes encountered in silicon nitride and silicon oxynitride films (of the order of 10^^ atoms/cm^). Moreover, both permit an absolute determination of atomic amounts, regardless of the matrix. The nuclear reaction yields do not depend on the matrix. Furthermore, in the case of NRP, the analysis is non-destructive. The fundamentals of these two methods are briefly recalled below and their main characteristics are given in Table 7.1. Non-resonant nuclear reactions Isotope 2H

180 160 14N 15N

Nuclear reaction

Incident particle energy (MeV)

Detection angle (degree)

2H(3He,p)4He 180(p,a)15N I60(d,po)l70 l4N(d,ai)l2c l5N(p,aY)l2c

0.70 0.73 0.81 1.45 1.00

150 150 90 150 150

Sensitivity (x 10l3.cm-2)

0.1 1.0 10 10 0.1

Resonant nuclear reactions Isotope

Natural abundance

Nuclear reaction

Resonance energy ER (keV)

Width of resonance peak (eV)

15N

0.365 0.204 4.68 3.05

15N(p,ay)l2c l80(p,a)l5N 29Si(p,Y)30p 30Si(p,Y)31p

429 151 324 620

120 100 100 70

180 29Si 30Si

Table 7.1 - Characteristics of the isotopes and of the nuclear reactions usedfor isotopic tracing experiments.

The Study of Thermal Nitridation

501

1.2.2. Fundamentals of Nuclear Reaction Analysis (NRA) The NRA technique consists in irradiating the target with charged particles which possess an energy sufficiently high so that they can penetrate the Coulomb barrier. Under these circumstances, a variety of nuclear reactions can occur. For a given incident particle and a given incident energy, each element encountered in the target can react and produce secondary particles whose energy depends on the reaction heat (Q). For example, to determine the amount of oxygen present in a target we can use nuclear reaction l6o(d,p)l'70. In this case, an incident beam of monoenergetic deuterons is used at an energy of 0.8 MeV for which the nuclear reaction cross-section varies only slowly with energy. Thus, as the incident deuteron looses energy by passing through the target, the probability that the nuclear reaction occurs remains unchanged. Each nuclear reaction event produces a proton with an energy of 2.4 MeV, which can be detected, and an ^^O nucleus in various states of excitation (the fundamental state is usually preferred for analysis purposes). The number of protons, measured with a surface barrier detector, in a given geometry and for a given dose of incident deuterons, is proportional to the areal density of l^O atoms encountered in the target. By comparing this number of protons with that observed from an l^O standard sample measured in the same experimental conditions, we can deduce the true areal density of ^^o in the target. 1.2.3. Examples of results obtained by combining NRA with step-by-step chemical etching The in-depth concentration profile of a given isotope in a film can be determined by combining a progressive chemical etching (carried out in a diluted buffered HF solution) with the determination, by NRA, of the total amount of isotopes remaining in the film after each etching step. By differentiating the curve giving that total amount as a function of film thickness, we get the local concentration of this isotope versus depth. This method leads to a depth resolution of about 1 nm across the whole nitride or oxynitride sample. Figures 7.1 a & b illustrate how the method has been applied to determine the concentration profile of deuterium (D) in an Si02 film thermally nitrided in D-enriched NH3. Figure 7.1 a a shows the dissolution curve which, when read from right to left, gives the amount of deuterium remaining in the film after each etching step, as a function of the total amount of oxygen plus nitrogen (N+O), also measured by NRA. Since the N and O atoms are only encountered in the oxynitride film, and since the amount of deuterium is rather small compared to the amount of N and O, the sum of the N and O atoms present in the film is an appropriate way to measure depth. We can thus use an equivalent depth scale, such that a quantity of lO^^ N atoms/cm^ is equivalent to 0.188 nm of a pure silicon nitride film and a quantity of 10^^ O atoms/cm^ is equivalent to 0.226 nm of a pure silicon oxide film [7]. The local concentration profile, i.e. [D] = D/(N+0) plotted versus (N+O), is obtained by differentiation of the dissolution curve as represented in Fig. 7.1 b.

JJ, Ganem and LJ,R, Baumvol

502

0.015

0.6

—

r-

Interface

'^

O H2:;

/ •

j ^

4

^w

Surface (b) I

35 N + 0 [ 1015 atoms/cm2 ]

70

-

»

35 N + 0 [ 1015 atoms/cm2]

70

Fig. 7.1 ' Illustration of Nuclear Reaction Analysis combined with step-by-step chemical etching, applied to a silicon oxide film nitrided in ND3 [7]. Left) The total amount of deuterium remaining after each etching step is plotted as a function of the total amount of remaining (N+0) atoms. Right) Plot of the deuterium depth concentration profile, obtained by differentiation of Curve a.

1.2.4. Fundamentals of Nuclear reaction Resonance Profiling (NRP) Unlike NRA, Nuclear reaction Resonance Profiling (NRP) uses a narrow resonance peak (of energy ER) of the nuclear reaction cross-section. By bombarding the target with particles of incident energy Ep greater than ER, we can identify and discriminate atoms located at depth e such that: Ep-ER e =

(7.1)

dx ratio dE/dx being the stopping power of the incident particle in the matrix. This formula only applies, of course, in the absence of energy fluctuations. By measuring the number of emitted particles (a or 7-rays) as a function of incident energy Ep, we obtain the so-called excitation curve. An example of excitation curve, corresponding to reaction ^^©(p, a) ^^N, with ER = 151 kev, is given in Fig. 7.3. If the target has a uniform concentration of the isotope of interest, and in the absence of energy fluctuations, the excitation curve is rectangular. The width of the plateau is proportional to dE/dx convoluted by the instrumental energy resolution function (the latter function being the convolution of the Lorentzian resonance line shape with the Gaussian ion beam spread). Another type of information is contained in such excitation curves: the height of the plateau is nearly proportional to the average atomic concentration of the analyzed element (e.g. 15N, I80) in the layer.

The Study of Thermal Nitridation

503

detector detection angle incident beam sample Fig. 7.2 - Schematics of the NRP detection technique.

For targets with a non-uniform distribution of isotopes, the excitation curves are more complex and the atomic depth concentration profiles are determined by means of a computerbased simulation program called SPACES [7]. The depth resolution of this profiling technique depends mainly on the width of the nuclear reaction resonance peak, on the stability of the beam energy, on the stopping power of the incident particles, and on the measurement geometry. For the isotopes described in Table 7.1, in materials like silicon nitride and silicon oxynitride, using a well stabilized accelerator, and for a tilt angle of 65° (see Fig. 7.2), one obtains a depth resolution of approximately 1 nm near the surface. 1.2.5. Examples of results obtained by NRP Figure 7.3 illustrates how the NRP method has been used to determine the 1^0 concentration profile in a silicon oxynitride film (Si^^OxNy) thermally reoxidized in dry I8O2. A 16-nm-thick Sil602 layer has first been nitrided in NH3 (P[NH3] = 30 mbar, T = lOOOX, t = 60min) and then reoxidized in I8O2 (P[^^02] = 100 mbar, T = lOOOX, t = 30 min). The experimental excitation curve of nuclear reaction l80(p,a)l5N, shown in Fig. 7.3, has been measured around the resonance energy of the reaction at 151 keV. A tilt angle of 70"" has been used to enhance the depth resolution. The dots correspond to the experimental data, whereas the solid lines represent simulated excitation curves obtained by using program SPACES (the upper solid line is the sum of the excitation curves contributed by each arbitrary thickness interval used for simulation). The resulting l^O concentration profile, i.e. [1^02] = 1^0/(16o+18o+N), is plotted versus depth, in the inset. 2. MECHANISMS OF THERMAL GROWTH OF SILICON NITRIDE FILMS The thermal growth of silicon nitride films on silicon is usually performed in gaseous ammonia (NH3) because the processing temperatures required (~ 900°C), are lower than those needed to promote nitride growth in N2 (>1200°C) [4,5]. When a silicon wafer is first exposed to ammonia, the adsorption, decomposition, and reaction of NH3 molecules at the Si surface promote the formation of one or two monolayers of silicon nitride as explained in Chap. 1 of this volume. The subsequent growth of the silicon nitride film depends on the transport of the nitriding species across this initial layer.

504

/./. Ganem and IJ.R. Baumvol

100 400 00

c o o ^

0

6

10

15

Depth (nm) 200

0

2

4

6

E - E R (keV) Fig. 7.3 - Excitation curve of nuclear reaction ^^0(p,a)^^N around the energy of the resonance at 151 keV (dots). The solid lines represent the simulated excitation curve obtained by using program SPACES. The ^^O concentration profile deduced from the excitation curve is shown in the inset.

Thermal growth is found to be very fast during the early stages, it slows down when the film thickness reaches about 2 nm, and then stops for a film thickness above 5 nm [4-6]. Nitride growth is said to be self-limited. Since the final film thickness is so small, the growth mechanisms are difficult to study. The isotopic tracing of nitrogen and hydrogen enables us to better understand the growth mechanisms. Three types of anmionia gas may be used: pure (electronic-grade) ammonia (l^NH3), l^N-enriched ammonia (I5NH3), ^ ^ ^H-enriched ammonia (^^N'^H^ also symbolized by ND3). 2.1. MOTION OF NITROGEN

To study the motion of nitrogen atoms during thermal growth in anmionia, the nitridation process may be performed in two different sequences: • in the first sequence, growth takes place in a ^^NU^ atmosphere (1st step) followed by growth in a 1^NH3 atmosphere (2nd step), • in the second sequence, the order is reversed (first growth in l^NH3 then in 15NH3). The [N] profiles (i.e. 14N/(14N+15N) versus (14N+15N) or 15N/(14N+15N) versus (14N+15N)) are obtained by combining NRA with chemical etching. The profiles of Fig. 7.4 a correspond to Si (100) wafers which have been nitrided first in 14NH3 (100 mbar, 900°C, 4 hours) then in 15NH3 (100 mbar, 900°C, 4 hours). The profiles of Fig. 7.4 b, correspond to the reverse sequence [7].

The Study of Thermal Nitridation

1

505

1

25 2^ ^0.5 II

A

\/Surface

h Interface

Yy

•

/ \

• - •

•

••

4

a)

j

14N

(a) 1 8

+ 15N (1015 cm-2)

12

b)

4 8 14N + 15N (1015

Fig. 7.4 ' Concentration profiles measured after a two-step thermal growth in ammonia [7]. a) Growth in ^"^NH^ followed by growth in ^^NHj. b) Growth in ^^NH^ followed by growth in ^"^NH^. (open squares correspond to [^"^N], black dots correspond to [^^N]. See text for detail).

We note that the nitrogen atoms which are incorporated during the second step remain mostly in the surface region and that there is an appreciable overlap of the [l^N] and the [l^N] profiles near the surface. This behaviour is fairly different from that observed for oxygen, during the thermal growth of Si02 in dry O2. In that case, isotopic tracing shows that oxygen introduced during the second step accumulates mostly at the Si/Si02 interface [3, 23]. 2.2. MOTION OF HYDROGEN

Thermal nitridation can also be performed entirely in a ND3 atmosphere. This procedure allows a quantitative analysis of hydrogen, devoid of contamination effects introduced by exposure to air. By measuring the deuterium profile, using NRA and chemical etching, we conclude that, after nitridation, D is mostly encountered close to the surface [7]. By performing nitridation first in ND3 then in NH3, we can show that a large amount of exchange takes place between H and D (large compared with the l^N
506

J.J. Ganem and I.J.R. Baumvol

2.3. NON-MOTION OF SILICON

The silicon atoms do not move during growth. This has been illustrated by the isotopic tracing of Si, using a 1.4nm-thick layer of 29si epitaxially deposited on a natural siUcon wafer, and by measuring the profiles of 29si before and after thermal nitridation in NH3. The result is shown in Fig. 7.5. The fact that the rising edges of the excitation curves of the 29Si(p,7)30p nuclear reaction, around the energy of the resonance at 324 keV, measured before and after thermal nitridation, coincide, proves that the 29si atoms have not moved and thus that the Si species in general are immobile during growth [9]. 800

1

*-

'

'

'

Cii«^n/'

1 ourtacc

600

•

• s »o

l

400 1

r

o

>

*

200

1

J

0

•

0

~|

•

0 •

J 00

•

h

00 • • •

1 1

-j

Before nitridation After nitridation

0

0

I

,

00 <

••

• «

J 0

0

• ° •

^

0 41n a » a a •

1

•

'

•

•

J '

E - E R (keV) Fig. 7.5 ' Excitation curve of the ^^Si(p, jj^^^P nuclear reaction near the resonance at 324 keV obtained from a 1.4-nm-thick layer of ^^Si, epitaxially deposited on a (100) silicon wafer, before (•) and after (o) thermal nitridation in NHj [9]. 2.4. CONCLUSION

From the above observations, we can conclude that the nitridation of silicon proceeds due to the transport of NHx species through the growing film. NHx moves towards the nitride/silicon interface, either as an interstitial defect reacting with the nitride network or as a substitutional defect driven by a diffusion mechanism. This transport is accompanied by a slight exchange of nitrogen atoms coming from the gas phase with nitrogen atoms already incorporated in the network (N4->N exchange). The motion of hydrogen is complex. Hydrogen is incorporated in the network, via the NHx species. Exchange phenomena take place whereby hydrogen atoms from the gas phase can substitute hydrogen atoms already incorporated ( H ^ H exchange). Moreover, part of the hydrogen atoms are liberated and outdiffuse in molecular form. Let us note, however, that the depth profiling of hydrogen is extremely difficult given the small thickness (< 4 nm) of the thermal nitride films and the absence of low-energy nuclear resonance reactions.

The Study of Thermal Nitridation

507

3. MECHANISMS OF THERMAL NITRIDATION OF SILICA FILMS In microelectronics applications, thermal oxynitride films are preferred to thermal silicon nitride films because they can be produced in thicker layers. Oxynitrides are commonly obtained by nitriding silica layers in gaseous NH3 [10]. (The thermal nitridation of silica directly in N2 is impossible (at T < 1 200°C) since no nitrogen atom gets incorporated in the network). Isotopic tracing enables us to better understand the various mechanisms at work during nitridation. 3.1. M O S T LIKELY CHEMICAL REACTIONS

The diffusing NH3 molecules react differently depending on their location across the film. Ammonia molecules chemisorb at the surface of silica at temperatures above 650°C and react as follows: Si'O-Si + NH3 ^ SiNH2 + SiOH

{12)

At the Si02/Si interface, because of the existence of free silicon atoms and considering the change in free energy of the chemical reactions, the following reactions can take place: Si02 •h3Si-\'4 NHj 4=> 2 Si2N20 + 6 H2 2 Si02 + Si-^4 NHj ^ SisN4 + 4 H2O

(7.3) (7.4)

Finally, in the bulk of silica, the nitriding species can react with the oxide network following: Si-O'Si + NH3 ^ Si2NH + H2O

(7.5)

This explains why silamine (Si2NH) and silanol (SiOH) groups, as well as silicon nitride and silicon oxynitrides are observed in silica films nitrided in NH3 [11,12]. The transport of the nitriding species during the thermal nitridation of the very thin («10 nm) Si02 films used for VLSI applications is rendered more complex by the closeness of the Si02/Si interface which acts either as a reactive zone, or as a reflecting wall. 3.2. M O T I O N OF NITROGEN

In order to isolate the influence of the Si02/Si interface, thermal nitridation should be carried out using thick (1 to 2 |Lim) Si02 films. In this case, the transport of the nitriding species proceeds in the absence of a reflecting wall. Several 1 |im-thick Si02 films have thus been nitrided in NH3 for: 30 s, 60 s, and 300 s (with P[NH3] = 1 bar, T = 700°C). The resulting [N] profiles, measured by SIMS, for these three nitridation times are shown in Fig. 7.6. These profiles can be fitted [13] with exponential functions of depth. The theory of diffusion in Si02, when the diffusing species also reacts with the silica network [14], gives indeed a concentration profile of nitrogen that decreases exponentially as a function of depth from the surface down into the bulk of the Si02.

J.J. Ganem and I.J.R. Baumvol

508

These profiles lead us to conclude that the main transport mechanism is the interstitial diffusion of NH3, and (less probably) that of NH^, (x<3), reacting with the siUca network.

1.e+18

1.e+17

K

\

300s

k '. 50s

Fig. 7.6-N concentration profiles, measured by SIMS, for SiOj samples nitrided in NH3 (1 bar, 700°C) for various durations, (after [13] slightly modified.)

V V. V/•^

1.e+16

« 11 11 1 1 1

0.0

I M^hf^M'..'^

I I 1< 11 1 1 1

0.2

M I 1 I 1 I • 1 1. ^ i l i . . 1 I . I t . .

0.4

0.6

* . . . . > t ..

0.8

.

1.0

Depth (|im) 3.3. EXCHANGE PHENOMENA DURING NITRTOATION

The incorporation of nitrogen into the Si02 film being nitrided is mostly due to the substitution of O atoms by N atoms [17]. At the same time the N and H atoms already incorporated in the oxynitride network are exchanged for N and H atoms coming from the gas phase. As shown next, the reaction of N with the Si02 network always involves an intermediate stage in which H bridges the reaction [15]. Most of the incorporated N atoms are found near the surface and near the interface (at least one monolayer of Si3N4 is formed at the interface) [16]. The exchange phenomena can be confirmed and quantified by measuring the total amounts of N and H isotopes remaining in the oxynitride films after the alternate nitridation of the Si02films.Two nitridation sequences may be used: (i) Nitridation in l^NHs (1st step) followed by l^NHj (2nd step), followed by l^NHj (3rd step); (ii) Nitridation in ND3 (1st step) followed by NH3 (2nd step), followed by ND3 (3rd step). Samples of silica films, 16 nm-thick, have been submitted to either sequence carried out in the same conditions (P[NH3] = 30 mbar, T = 1000°C, each step lasting 60 min.) [17]. The total amounts of i^N, 15N, and (^^N +15N), measured by NRA after each step, have been plotted in Fig. 7.7 a. Likewise, the total amounts of D and (D+H) measured by NRA after each step have been plotted in Fig. 7.7 b. We note in both figures that, although exchange mechanisms do take place, the total amount of nitrogen and that of hydrogen tend to saturate with nitridation time.

The Study of Thermal Nitridation 1

1

1

1

14N

16

509

1

+

15N

_ / ^

.

i J O

\

15N

(a) 1

14NH3

a)

1

1

15NH3

«

^^NH3

Nitridation step

1

b)

Nitridation step

Fig. 7.7 - Illustration of the (N<->N) and (H<->H) exchange mechanisms taking place during the nitridation of silica. a) Total amounts of ^^N, ^"^N and (^^N + ^"^N) measured by NRA in an oxynitride film obtained by successive nitridation steps of a 16-nm Si02 film in ^"^NHs (1st step), ^^NHs (2nd step), and ^"^NH^ (3rd step). b) Total amounts of(H-\-D) and D measured by NRA in oxynitride films prepared in ND^ (1st step), followed by NH^ (2nd step), followed by ND^ (3rd step).

In Fig. 7.8 we compare the [l^N] profiles assessed by NRP after simple and alternate nitridations. The first profile has been measured on a 16 nm-thick silica layer nitrided in 15NH3 while the second profile has been measured after a two-step sequence (first in 15NH3 then in 14NH3). For each step, the experimental conditions have been the same: 100 mbar, lOOO^C, 60 min [17]. We note that the N^^N exchange occurs mostly at the prface of silica. These experimental results show that the atomic exchanges, N<->N, and H^^H, take place mostly at the surface. This is also true of the 0^->N exchange [17].

Fig. 7.8 - Concentration profiles of ^%, as measured by NRP, in oxynitride samples obtained by thermal nitridations in ^^NH^ (—) and in-^^NHj followed by ^^NH^( ).

6 8 10 Depth (nm)

510

/./. Ganem andlJ.R, Baumvol

3 A. DISCUSSION AND CONCLUSION

The chemical equilibrium of the reactions which occur during thermal nitridation and the large mobility of the H and H2O species determine the amount of hydrogen which, at the end, remains in the oxynitride film. This amount is much smaller than the incorporated amount of N. The three atomic species (N, O, and H) taking part in the process are transported both towards the surface and towards the Si02/Si interface: the motion of N is due to the diffusion of NH3 (or NH^) whereas the migration of H and O is due to the diffusion of the H and H2O species produced by reactions such as (7.3), (7.4) and (7.5) [17]. The chemical species which reach the surface tend to desorb. By so doing they lower their concentration undemeath the surface and induce new atomic exchanges. The nitriding species are transported through the oxynitride film in spite of the diffusion barrier created by the incorporation of N in the Si02 film. This diffusion is fueled by an interstitial mechanism combined with a reaction with the silica network. The result is that an appreciable number of N atoms reach the Si02/Si interface, where they accumulate in the form of stable compounds such as Si3N4 or SiO^Ny [11,12]. For long nitridation times (typically around 1 hour), [N] below the surface increases at a much smaller rate than near the interface. This can be explained by the predominance of the N^^N exchanges over the N<-^0 exchanges in the near-surface region. On the other hand, H accumulates below the surface of the oxynitride film and in the region just above the oxynitride/Si interface as shown in Fig. 7.1 b. 4. MECHANISMS OF THERMAL REOXIDATION OF OXYNITRIDE FILMS The thermal reoxidation of oxynitride films in dry O2 is an essential complementary process step which removes hydrogen from the film. It is also used to decrease the concentration of nitrogen at the Si02/Si interface, thereby improving the electrical characteristics of this interface. 4.1. R O L E OF OXYGEN

The thermal reoxidation of oxynitride films causes the incorporation of additional O atoms mainly in the surface and interface regions. In this case, however, the increase in thickness of the silicon oxynitride film proceeds at a rate which is smaller than that corresponding to the thermal growth of a pure Si02 film in dry O2. This stems from the fact that oxygen diffusion is slowed down by the nitrogen-rich regions of the oxynitride film (which behave as diffusion barriers). It is also due to the enhanced rate of atomic exchanges. 4.2. COMBINED ROLE OF OXYGEN AND HYDROGEN In Fig. 7.9 we present the variations in deuterium content (measured by NRA) observed in an oxynitride film during its reoxidation in dry O2 (P[02] = 100 mbar, T = 1000°C).

The Study of Thermal Nitridation

20

40 60 Reoxidation time (min)

511

80

Fig. 7.9 ' The amount of deuterium remaining in an oxynitride film is plotted as a function of the reoxidation time in dry O2. The oxynitride had first been obtained by nitridation of a silica film in ND^ (see text) [17].

The oxynitride had initially been formed by the nitridation in ND3 (P[ND3] = 30 mbar, T = 1000°C, t = 60 min) of a 20 nm-thick Si02 film. The elimination of hydrogen from the oxynitride films during thermal reoxidation in dry O2, as illustrated in this figure, is a consequence of the diffusion and desorption of the H and H2O species which are formed by the cross-linking of the chemical reactions taking place in the system. However, one cannot attribute all the transport of oxygen during reoxidation to the high mobility of OH species because the amount of H encountered in the oxynitride films is one to two orders of magnitude smaller than the amount of incorporated O. It follows that part of the oxygen transport during reoxidation must be due to a mechanism similar to that responsible for the thermal growth of Si02 in dry oxygen [3].

^ o^

^

6

8

10

12

14

Depth (nm) Fig. 7.10 - [^^N] depth profiles, measured by NRP, observed after thermal nitridation of an Si02film in ^^NH^ (—), and after its reoxidation during 30 min ( j and 60 min (-- — ) .

512

/./. Ganem and IJ.R, Baumvol

4.3. R O L E OF NITROGEN

The high concentration of N atoms usually found at the surface of oxynitride films is almost completely erased by reoxidation due to an exchange of N atoms with O atoms. Moreover, the O atoms which diffuse to the oxynitride/Si interface react with Si thus promoting film growth, so that a new interface is formed having a smaller concentration of nitrogen. Profiles of [^^N] measured before and after reoxidation in O2 of a silicon oxynitride film are shown in Fig. 7.10. The 16-nm-thick Si02 film was initially nitrided in 15NH3 (30 mbar, lOOO'^C, 60 min) and then reoxidized in dry oxygen for 30 min and 60 min (P[02] = 100 mbar, T = 1000°C). Figure 7.10 clearly shows that during reoxidation, the N atoms migrate toward the surface and that a substantial part of them is lost through desorption. 4.4. EXCHANGE MECHANISMS

The inset of Fig. 7.3 shows an [^^O] depth profile measured after the thermal reoxidation in I8O2 ^f ^ silicon oxynitride film produced with natural gases. NRA experiments show that an exchange of atoms takes place during reoxidation. N and O atoms belonging to the oxynitride film are exchanged with freshly introduced O atoms. Figure 7.11 illustrates this exchange. In this figure, the total amounts of ^^o, ISQ, and ^^N atoms, and their sum, have been plotted after a silicon substrate was submitted to four consecutive treatment steps: 1-Oxidation in I6O2, P(02) = 100 mbar, 1050°C, 90 s, 2-Nitridation in l^NHs, P(NH3) = 30 mbar, lOOOX, 60 min, 3-Reoxidation in I8O2, P(02) = 100 mbar, lOOOX, 30 min, 4-Reoxidation in I8O2, P(02) = 100 mbar, lOOOX, 60 min.

100

Fig. 7.11 - Total amounts, measured by NRA, of ^^O, ^^O, ^^N, and O^O +^^0 +^%j after different thermal treatment steps (see text) [17].

15NH3

^^^2

^^02

(30 mm) (60 mm) Thermal treatments

The Study of Thermal Nitridation

513

4.5. SYMMETRICAL BEHAVIOR OF THE EXCHANGE MECHANISMS

There exists a symmetry between the mechanisms taking place during the thermal nitridation of Si02 films in NH3 and the mechanisms at work during the thermal reoxidation in dry O2 of oxynitride films. This symmetry may be due to the reversibility of the chemical reactions occurring in the system. The nitridation of silica proceeds via an atomic exchange between the nitriding species and the O atoms of the film while the reoxidation of an oxynitride film proceeds via an atomic exchange between the oxidizing species and the N atoms of the network. N atoms (or O, in the case of reoxidation) are incorporated in all regions of the nitrided (or reoxidized) films. This indicates that the prevailing transport mechanism for both migrating species is, in all cases, interstitial diffusion accompanied by reaction with the film network. Especially for oxygen, this represents a major change from the usual transport mechanism encountered in Si02 films. (Indeed, during the thermal oxidation of silicon, oxygen diffuses without reacting with the silica network, and reaches the Si02/Si interface where it reacts with silicon.). The symmetry can be extended somewhat further. During the thermal nitridation of an oxynitride, an important exchange takes place between the nitrogen atoms of the oxynitride film and those coming from the gas phase. In a synmietrical manner, during the thermal reoxidation (of an oxynitride), the O atoms of the oxynitride film are exchanged with those coming from the O2 gas phase. 5. OXYNITRIDE FILMS GROWN IN N2O The thermal treatment of silicon wafers in nitrous oxide (N2O) is one of the most promising ways of producing very thin (< 10 nm) and reliable gate dielectrics. This technique allows one to grow, in a single process step, a silicon oxynitride film free of hydrogen and possessing excellent electrical characteristics. However, the growth mechanisms of these films are still unknown and isotopic tracing techniques should help in identifying them. 5.1. THERMAL TREATMENT IN N2O. A RELATIVELY NEW PROCESS

Many authors have shown [18, 19] that a direct thermal treatment in N2O leads essentially to the growth of a Si02 film with a small concentration of nitrogen (1-5 atom %), mostly located in the region near the dielectric/Si interface. A recent study [20] has revealed that after the Rapid Thermal Processing (RTP) of Si wafers in N2O, nitrogen is found only near the interface, whereas after processing in a conventional (Joule effect) fumace, nitrogen atoms are also detected in the bulk of the oxide film (RTP and fumace processes using N2O are described in detail in Chap. 1 of this volume). From thermodynamic considerations, the authors suggest that atomic oxygen, produced by the decomposition of N2O in the RTP fumace, is responsible for the final nitrogen distribution. On the other hand, in a conventional fumace in which the gas is in equilibrium, only N2, O2 and NO groups (and no O atoms) are available to fuel the growth of the oxynitride film.

JJ. Ganem and LJ,R. Baumvol

514

The isotopic tracing of oxygen and nitrogen, using l^N and l^o, can bring important new information on the growth mechanisms of oxynitride films in N2O. Unfortunately, the cost and the availability of isotope-enriched N2O gases make these experiments very difficult to carry out. Nevertheless, the RTP growth of silicon oxynitride films in 15N2O, as well as their reoxidation in 1^62 in a conventional furnace have been studied [21]. 5.2. GROWTH KINETICS

As expected, the growth of oxynitride films in N2O depends both on time and on the gas pressure P[N20]. 5.2.1. Time dependence The growth kinetics of oxynitride films on Si in N2O, in an RTP furnace, is illustrated in Fig. 7.12 for the following processing conditions: P[N20] = 30 mbar, 1000°C. The film thickness is determined by measuring the total amount of oxygen with NRA, and is expressed in units of lO^^ O atoms/cm^. The conversion to nanometers can be performed by means of the Si20 equivalent thickness formula, namely: lO^^ O atoms/cm^ = 0.226 nm. We note that growth is rather fast at the beginning, but slows down for longer thermal treatments, although there is no observed saturation with these experimental conditions. The rate at which nitrogen is incorporated, as measured by NRA, is also given in Fig. 7.12. The N "concentration" (i.e. ratio N/(N+0)) in the oxynitride films is found to be approximately 2% that of oxygen for all processing times. The incorporation of nitrogen also slows down for longer RTP times. The measured amounts of O and N both vary with processing time as t^-5, showing that the incorporation of nitrogen and oxygen atoms in the growing dielectric is probably driven by a diffusion mechanism^*\

60

1

50 E 0 1—1

0

1

T

1

1

0 I

40 ^

30 20

\

^ 0

/ •

i-H

-^

o -\

N

10

0

a

-X)

1

1

•

1

50

100

150

200

0 250

Fig. 7.12 - Illustration of Rapid Thermal Treatment in N2O with P(N20) = 30 mbar and T = lOOO^'C. Upper curve: Growth kinetics of silicon oxynitride films on Si. Lower curve: Kinetics of N incorporation during growth [22] (see text for detail).

Time (s) {*) See Chap. 1 of Vol. 1 [23] for a more detailed discussion on time dependence laws.

The Study of Thermal Nitridation

515

5.2.2. Pressure dependence In Fig. 7.13, the thickness of the oxynitride film (expressed in units of 10^^ O atoms/cm^) has been plotted versus P[N02], the pressure of N2O in the RTF furnace. The corresponding amount of N incorporated in the film has also been plotted. The duration of the RTF process in all cases is 60 s, and the processing temperature is 1000°C. We note that the film thickness depends strongly on F[N20] in the lower pressure range. For pressures above 200 mbar, the film thickness seems to be independent of the gas pressure. The amount of incorporated N increases with gas pressure, while no saturation effect is observed in the pressure range investigated. The log-log plotting of the data shown in Fig. 7.13 a leads to straight lines, from which a pressure dependence of F^-^^ for O, and F^-^ for N are extracted (Fig. 7.13 b). This indicates that the nitriding species should result from a first-order decomposition of nitrous oxide, and that the oxidizing species should result from a second-order decomposition of the nitrous oxide^'. y^j

' ' '

"1

10

0

i -

I

S o

l.-^^

^

10 -

e

AJ

r—(

o

o

^

1 0

100

200

300

400

Pressure (mbar)

1

1

1

•

• • • • • !

10

11

1 — 1 1 1 1

N

III

t — 1 — 1 —

0,1

100

Pressure (mbar)

Fig. 7.13 - Illustration of the role played by pressure P[N20] during RTF growth in N2O (1000°C, 60 s). a) The thickness of the oxynitride film (in units of 10^^ O atoms/cm^) is plotted versus F[N20] (top curve). Likewise, the amount of incorporated N atoms is plotted versus F[N2^] (bottom curve). b) The same results are presented using a log-log plot. [22]. 5.3. MOTION OF NITROGEN DURING GROWTH

The excitation curves of the 15N(p^ocY)12c nuclear reaction, around the energy of the resonance at 429 keV, are shown in Fig. 7.14 for different sequences of growth in isotopically enriched N2O in an RTF furnace. (F[N20] = 30 mbar, lOOOX, 80 s (for each step)). In Fig. 7.14 a, the excitation curves corresponding to two growth sequences: one in 1^N20 and one in l^N20 (1st step), followed by l'^N20 (2nd step) are shown, as well as the curve that results from the subtraction of these two excitation curves (shadowed). (*) See Chap. 1 of Vol. 1 [23] for a more detailed discussion of pressure dependence laws.

516

JJ, Ganem and IJ.R. Baumvol

The hatched areas below and above the zero level represent, respectively, the local loss and the local gain in l^N after the second growth step in l'^N20. We see that the second step in l'^N20 pushes the ^^N distribution deeper into the growing oxynitride film. Furthermore, the area below the excitation curve (which represents the total amount of l^N) decreases after the second treatment step in 14N2O. Thus, during the second step, part of the l^N atoms are lost, while the total amount of nitrogen (l^N+^^N) increases. We can conclude that, during a thermal oxynitridation in an N2O ambient, at least two phenomena occur: • the migration of nitrogen to the dielectric/Si interface, • the local loss of nitrogen. In Fig. 7.14 b are shown the excitation curves obtained for the following three growth sequences: 15N2O, 15N2O (1st step), followed by 14N2O (2nd step), and 15N2O (1st step) followed by 14N2O (2nd step) and again followed by l'^N20 (3rd step). The third process step in l'^N20 produces a further growth of the oxynitride film, and the l^N distribution is pushed into the film, while being always located in the region near the new interface. However, during the third step, no additional loss of ^^N is observed showing that the local loss mechanism occurs only in the early stages of growth. During the subsequent oxynitridation stages, the prevailing phenomenon seems to be the migration of N towards the dielectric/Si interface. 8001

800

•T

'

r-

2nd step

600 h 600

I

400

Samples Surfacq

3rd step

§400 o

g 200

oh*^

200

-200 h -400 -1

a)

fe^ 0

1

2

1

3

E - E R (keV)

b)

2

3

E - E R (keV)

Fig. 7,14 ' Illustration of the motion of nitrogen during RTP treatment in N2O. a) Excitation curves of the ^^N(p,a'}j^^C nuclear reaction, measured after the 1st and 2nd processing steps described in the text. The curve that results from the subtraction of these two excitation curves is also represented, b) Excitation curves measured after the three growth steps described in the text.

Another technique of interest for the study of atomic transport mechanisms consists in performing a treatment in 15N2O followed by a treatment in 14N2O, and in the reverse order, i.e. 14N2O followed by l^N20. This has been performed in the same RTP conditions as those mentioned in the previous paragraph [22].

The Study of Thermal Nitridation

517

The ensuing l^N profiles, determined by NRP, are shown in Fig. 7.15. The ^^N profile for the sample obtained by a single growth step in ^^^2^ ^^ ^^^ shown in Fig. 7.15. In all three cases, nitrogen is only encountered at the oxynitride/silicon interface. Since the samples produced in the two-step sequence are perfectly symmetrical with respect to the two N isotopes, we can say that the ^^N profile determined for the sample grown in the second sequence (^^N20 followed by ^^N20) corresponds to the ^^N profile for the sample grown in the first sequence (I5N2O followed by ^^N^O). Figure 7.15 thus reveals the existence of a mixture of ^^N and ^^N near the interface for the oxynitride film grown in the first sequence (I5N2O followed by l'^N20). We can conclude that a second nitridation step in N2O redistributes the N atoms already incorporated during the first growth step: the newly incorporated N atoms are deeper in the film, and the N atoms already present are either pushed towards the surface or removed from the oxynitride film.

5

10 Depth (nm)

15

Fig. 7.15 - Illustration of the motion of nitrogen during RIP treatment in N2O. The ^^N profiles, measured by NRP, are shown for three growth sequences. The solid line (—) corresponds to a one-step growth in ^^N. The two dashed lines correspond to samples grown in two steps. Line ( ) corresponds to the sequence ^^N20 followed by ^'^N20 and line (— - -^ corresponds to the reverse sequence. Arrow 1 indicates the location of the interface after the one-step sequence. Arrow 2 indicates the location of the interface for the other two sequences [22]. 5.4. ATOMIC TRANSPORT MECHANISMS DURING GROV^TH IN N2O

In order to understand the atomic transport mechanisms which underly the above-described oxynitridations, we must consider the chemical reactions taking place in the system. The heating of the N2O gas near the Si wafer produces the following primary decomposition: N20<=>N2'^0

(7.6)

which can give rise to several secondary reactions: N20 + 0<=>N2 + 02 N20 + 0^2NO

(7.7) (7.8)

518

/./. Ganem and IJ.R, Baumvol

As mentioned in Sect. 3, no N is incorporated when oxynitride films are heated in N2. Thus, one can say that the NO, O, and O2 species resulting from the decomposition of N2O and the ensuing reactions are the species mostly responsible for N20-based growth and for the incorporation of N. From the time and pressure dependence mentioned above, we can conclude that the incorporation of nitrogen is driven by a diffusion mechanism. The nitriding species (most probably NO) diffuse into the growing film via an interstitial mechanism with a weak probability of reacting. Atomic oxygen, resulting from the decomposition of N2O, is probably responsible for the removal of N from the near-surface region as shown in ref. [20]. Molecular oxygen can fuel growth by a mechanism rather similar to that taking place during the thermal growth of Si02 films in dry O2: it diffuses through the growing film to react with Si at the interface (as explained in Chap. 1 of Vol. 1 [23]). Atomic oxygen could also take a part in the mechanism of oxygen incorporation. The oxygen atoms from the gas phase are thought to react at the sample surface and thus induce an exchange phenomenon between the oxygen from the gas phase and the oxygen from the film network. 5.5. Reoxidation of N20-based oxynitrides The l^N and ^^O distributions measured by NRP for various reoxidation times in 1^02 are shown in Fig. 7.16. A (100) silicon wafer has been initially nitrided in an RTF fumace in a 15N^16O ambient (10 mbar, 1090°C, 180 s) and reoxidized in a conventional fumace in ^^02 (100 mbar, 1090X) for 20 min, 40 min, and 120 min. We note in Fig. 7.16 a that, after the initial thermal treatment in nitrous oxide, N is encountered near the dielectric/Si interface in a rather small concentration (around 2%). During reoxidation, the nitrogen atoms diffuse in the film and drift to the sample surface. A significant loss of nitrogen across the film is also found, most probably due to the diffusion of defects (mainly interstitialcies) (see ref. [21] for more detail). We can infer from Fig. 7.16 b that during reoxidation, the oxygen atoms react at the interface to form new silicon oxide layers, while near the surface and in the bulk of the oxynitride film, a significant exchange takes place between the ^^o brought by the gas and the 1^0 of the film. An exchange of this magnitude has never been observed in the case of a silicon oxide being thermally reoxidized in the same "dry" conditions [3]. There is no evidence that the defects responsible for the motion of nitrogen and oxygen are identical. The behaviour of nitrogen can be explained by the existence of a concentration gradient of defects which favors their migration towards the surface [21]. 6. CONCLUSION In this chapter, we have reviewed what is presently known about the mechanisms of atomic transport and atomic exchange taking place during the thermal growth of silicon nitride and silicon oxynitride films. A few special aspects revealed by isotopic tracing techniques combined with controlled growth conditions are worth summarizing:

The Study of Thermal Nitridation

{'-"Before reoxidation 1

120 min

100 H

Before reoxidation

^ 2-1 1 2

1

40 min

1

U=^.— n^"-0 a)

\

\ r""""T n

5

40 min

20 min

40 min

J

519

10

15

120 min \

\ f

20

1 25

Depth (nm)

1 30

1J

35H-

^

80-

^

60-

»

402000

b)

1

1

I

120 min \

1

1

r*

1

1

1

j .J !-| 1

r

5

10

-T

15

20

25

1—pj_

1 — '

30

35

Depth (nm)

Fig. 7.16 - Illustration of the motion ofN and O atoms during the reoxidation ofN20-based oxynitrides. (The oxynitride film, originally grown in ^^N2^^0 is reoxidized in ^^O^, [21]. a) Profiles of ^^N measured by NRP, before reoxidation ( ) , after 40 min of reoxidation (—), and after 120 min (-—). The arrows indicate the location of the interface after each step, b) Profiles of ^^O, measured by NRP, during reoxidation : after 20 min (....), after 40 min (—), and after 120 min. (—-/

• The thermal growth of sUicon nitride films on Si in NH3 is basically driven by the dissociative adsorption of ammonia, and the subsequent interstitial migration of NH^ species (1 < X < 3) reacting with the growing nitride film. The continuous decomposition of the NH^ species produces H atoms which outdiffiise and desorb from the film surface, leaving rather small, although still measurable, amounts of hydrogen in the silicon nitride film, mainly in the surface region. • The thermal nitridation of Si02 films, in NH3, takes place essentially through an atomic substitution of O for N (N^f^O exchange). The atomic transport is due to the interstitial diffusion of NH3 reacting with the silica network. Both N and H are found underneath the surface and at the oxynitride/Si interface. Exchanges between the N and H atoms coming from the gas phase and those of the oxynitride film are also observed. Most of the atomic exchanges occur in the surface region of the film. The main mobile species are NH3 and H2O, the latter being produced by the chemical reaction of NH3 with Si02. • The mechanisms at work during the thermal reoxidation, in dry O2, of the oxynitride films are analogous to the mechanisms taking place during the thermal nitridation of silica. After reoxidation, the oxygen atoms are encountered at the sample surface as well as at the dielectric/Si interface. The incorporation of O during reoxidation is accompanied by a loss of N (through an 0<->N exchange). H is removed from the oxynitride film due to an additional production of H2O, which outdiffuses and desorbs. • Unlike in nitride films formed by the nitridation of silica in NH3, in oxynitride films grown by RTP in N2O, N is found near the oxynitride/Si interface only. Right after the initial stages of the oxynitridation, a local decrease in nitrogen is observed as well as a migration of nitrogen to the dielectric/Si interface. In fiirther stages, such a local decrease is no longer observed.

520

JJ. Ganem and IJ,R, Baumvol

• During the thermal reoxidation, in dry O2, of N20-based oxynitride films, O is observed to diflfUse interstitially, migrating to the oxynitride/Si interface to form the new oxide. The diflfiising oxygen atoms react in the bulk and are subjected to an exchange mechanism with the oxygen atoms already present in the film. Nitrogen atoms diffuse from their original location, which results in a net migration to the sample surface and a loss of nitrogen. Acknowledgements The authors wish to thank G. Barbottin and A. Vapaille for their suggestions and comments. They want to express their gratitude to G. Barbottin for his help in editing the English version of this text. List of References [I] E. Gusev, H.C. Lu, T. Gustafsson and E. Garfiinkel, Phys. Rev. B52, 1759 (1995). [2] I. Trimaille, F.C. Stedile, J.-J. Ganem, I.J.R. Baumvol and S. Rigo, "Mechanisms of Thermal Growth of Very Thin Films of Si02 in Dry O2" in The Physics and chemistry of SiOj and Si-SiOj Interface, in Proc. 96-1 edited by H.Z. Massoud, E.H. Pointdexer and C.R. Helms, The electrochem. soc, Pennington N.J., (1996), p 59 [3] I. Trimaille and S. Rigo, Appl. Surf ScL 39, 65 (1989). [4] P. Murarka, C.C. Chang and A.C. Adams, J. Electrochem. Soc. 126, 996, 1979. [5] Y. Hayafiiji and K. Kajiwara, J. Electrochem. Soc. 129, 2102, 1982. [6] J.J. Ganem, S. Rigo, I. Trimaille, G.N. Lu, P. Molle, Nucl. Instr. Meth. B64, 778, 1992. [7] I.J.R Baumvol, F.C. Stedile, J.-J. Ganem, S. Rigo and I. Trimaille, J. Electrochem. Soc. 142, 1205 (1995). [8] C.U.S. Larsson and A.S. Flodstrom, Surf. Sci. 241, 353, 1991. Idem 271, 349, 1992. [9] I.J.R. Baumvol, L. Borucki, J. Chaumont, J.-J. Ganem, S. Rigo, W.H. Schulte, F.C. Stedile and I. Trimaille, "Isotopic Tracing of Si During Thermal Nitridation of Si3N4 Ultrathin Films", Nucl. Instr. and Meth. B, Phys. Rev. B118 (1996) 499. [10] F.H.P.M. Habraken, A.E.T. Kuiper, Y. Tamminga, J.B. Theeten, J. Appl. Phys. 53, 6996 (1982). [II] H. Wong, B.L. Yang, and Y.C. Chmg, Appl. Surf Sci. 72, 49 (1993). [12] M. Bhat, J. Ahn, D.L. Kwong, M. Arendt and J.M. WhitQ, Appl. Phys. Lett. 64, 1168 (1994). [13] E. Breelle, S. Rigo, J.A. Kilner and J.J. Ganem, Appl. Surf Sci. 81, 127 (1994). [14] S. Rigo, F. Rochet, B. Agius and A. Straboni, J. Electrochem. Soc. 129, 867 (1982). [15] J.B. Oude Elferink, F.H.P.M. Habraken, W.F. Van Der Weg, E. Dooms, M. Heyns and R de Kersmaecker,yl/?/7/. Surf Sci. 39, 219 (1989). [16] K. Yamamoto, M. Nakazawa, Jpn. J. Appl. Phys. 33, 285 (1994). [17] I.J.R. Baumvol, F.C. Stedile, J.-J. Ganem, S. Rigo and I. Trimaille, "Thermal Nitridation of Si02 Films in Ammonia: The Role of Hydrogen", J. Electrochem. Soc, 143, 1426 (1996). [18] Y. Okada, P. J. Tobin, K. G. Reid, R. I. Hegde, B. Maiti, and S. A. Ajuria, Trans. Electron Devices, 41, 1608 (1994). [19] M. L. Green, D. Brasen, K. W. Evans-Lutterodt, L. C. Feldman, K. Krish, W. Lennard, H.-T. Tang, L. Manchanda, and M.-T. Tmg,Appl. Phys. Lett. 65, 848 (1994). [20] E. C. Carr, K. A. Ellis, and R. A. Buhrman, Appl. Phys. Lett. 66, 1492 (1995). [21] J.-J. Ganem, I. J. R. Baumvol, S. Rigo, F. C. Stedile, and I. Trimaille, "Dry Oxidation Mechanisms of Thin Dielectric Films Formed Under N2O Using Isotopic Tracing Methods", Appl. Phys. Lett. 68, to be published (1996). [22] J.-J. Ganem, I. J. R. Baumvol, S. Rigo, F. C. Stedile, and I. Trimaille, impublished results (1996). [23] G. Barbottin, A. Vapaille, Instabilities in silicon devices. Vol. 1, North-Holland/Elsevier (1986).

PART II SILICON DEVICES IN RADIATION ENVIRONMENTS

This Page Intentionally Left Blank

523 FOREWORD Part n of this volume contains five chapters entirely devoted to radiation effects and radiation-induced instabilities, with a special emphasis on phenomena encountered in space. In Chap. 8, we introduce the basic terms and definitions used in the field of radiationmatter interactions. We then describe the natural radiation environment encountered in space around the earth and show that its various components can be and have been modeled. This is justified by the fact that space is one of the most demanding environments and because the basic concepts introduced here are valid for other types of radiation surroundings. In Chap. 9, the major interactions of photons and particles with solid matter are reviewed from a physical point of view. The concepts, the mechanisms and the basic units are thoroughly described. We see that the end product of such interactions depends greatly on: the nature of the incoming particle, its mass, its charge state, its energy, as well as on the nature of the target material. In Chap. 10, the effects of radiation on semiconductor materials and devices characteristics are discussed. We see that the radiation-induced changes in material and device properties can be linked, either to ionization phenomena, or to displacement damage, or to both. At this point, it becomes obvious that the effects of radiation are of a complex nature and that the generation of defects is partially counterbalanced by the annealing behaviour of these very defects. In Chap. 11, some of the electrically active defects, both intrinsic and extrinsic, encountered in silica or at the Si-Si02 interface, and which play a role during and after irradiation, are reviewed. We see that the irradiation of a device leads to charge build-up (i.e. carrier trapping) in the insulating layers and to the generation of new defects in silicon, in silica and at the silicon-silica interface, through complex mechanisms which are beginning to be better understood. Finally in Chap. 12, we present another family of radiation-induced disturbances, which affect highly integrated circuits, called Single Event Phenomena. These are due to intense ionization phenomena occurring when single highly energetic particles (e.g. cosmic rays) pass through some sensitive part of a highly integrated device. We see that this disturbance, which can be modeled, can be either temporary and "easily" remedied, or destructive. These five chapters should give engineers and researchers alike, a good basis to understand the major aspects of radiation-induced instabilities in electronic components. For even more detailed descriptions of radiation-component and radiation-system interactions, the reader is referred to the following four recently published books. Ma and DressendorfeVy Ionizing Radiation effects in MOS Devices and Circuits, Wiley, 1989. Messenger and Ash, The effects of Radiation on Electronic Systems, Van Nostrand, 1992. Holmes - Siedle and Adams, Handbook of Radiation Effects, Oxford, 1993. Messenger and Ash, Single Event Phenomena, Chapman & Hall, 1997.

This Page Intentionally Left Blank

INSTABILITIES IN SILICON DEVICES Silicon Passivation and Related Instabilities G. Barbottin and A. Vapaille (Editors) © 1999 Elsevier Science B.V. All rights reserved.

525

CHAPTER 8

THE SPACE RADIATION ENVIRONMENT

byD.BRAUNIGd)

Key items Flux Fluence Dose Linear energy transfer Solar radiation Cosmic rays Van Allen belts Cut-ofF mechanisms Environment models Mission modeling

(1) Hahn-Meitner-Institut Berlin GmbH Department AT Glienicker Str. 100 14109 Berlin, Germany

526

D, Brdunig

Abstract of Chapter 8: The space radiation environment In many civilian and military applications, electronic components must operate in a radiation environment, and thus may experience instability phenomena. In Section 1 of this chapter, we introduce the parameters which enable us: to fully characterize the particles encountered in a radiation environment and to describe their effects on matter. We then describe the two basic constituents of the environment encountered in space: solar particles and cosmic rays. Particles can be emitted by the sun, either continuously (solar wind) or sporadically (solar flares). The rest of the galaxy behaves also as a continuous source of radiation (the cosmic rays). In Section 3 we show that there exists around the Earth, zones where particles are preferentially trapped (the so-called Van Allen belts). The Earth's magnetic field is responsible for this trapping. This field also shields our planet by filtering out most of the solar and galactic particles. In the last section we show that, given some hypotheses, the radiation environment of the Earth can be modeled. The models enable us to predict the fluxes and the energy spectrum of the particles that a spacecraft will encounter during a mission in space and thus help us compute the probability that a "Single Event Phenomenon" occur or that a component fail. We finally give a few examples illustrating the use of these models. Resume du chapitre 8 : Le rayonnement spatial Dans de nombreuses applications civiles et militaires, des composants electroniques sont amenes a fonctionner dans un environnement radiatif et peuvent devenir instables ou etre endommages. Dans la premiere section de ce chapitre, nous rappelons les parametres qui permettent de caracteriser : les particules rencontrees dans un environnement donne, et leur action sur la matiere. Nous decrivons ensuite les deux sources du rayonnement spatial : le soleil et la galaxie. Le soleil est a I 'origine de particules emises en continu (vent solaire) ou de maniere sporadique (lors des eruptions solaires). Le reste de la galaxie contribue a un fond continu de rayonnement (le rayonnement cosmique galactique). Dans la section 3, nous montrons qu 'il existe autour de la terre des zones de piegeage privilegiees pour les particules, encore appelees ceintures de Van Allen. Le champ magnetique terrestre est a Vorigine de ce piegeage. Ce champ joue par ailleurs le role d'un ecran protegeant la terre de la plupart des particules galactiques et solaires. Nous montrons dans la derniere section que, moyennant certaines hypotheses, I'environnement radiatif terrestre peut etre modelise. Les mode les permettent de predire les flux et les energies des particules qu 'un vehicule spatial va rencontrer et aident ainsi a chiffrer la probabilite qu 'un "evenement singulier" ou qu 'une panne se produise. Nous donnons enfin quelques exemples qui illustrent I 'application de ces modeles. Zusammenfassung zu Kapitel 8: Die Weltraumstrahlung In zahlreichen zivilen und militdrischen Anwendungen miissen elektronische Bauelemente in strahlungsbelasteter Umgebung arbeiten und dabei Instabilitdtsprobleme erfahren. In Abschnitt 1 dieses Kapitels werden die Parameter eingefuhrt, die es uns ermoglichen, sowohl die Eigenschaften der daran beteiligten Strahlungsspezies als auch ihre Wechselwirkung mit dem Material vollstdndig zu beschreiben. Anschliessend werden die zwei grundsdtzlichen Arten der im Weltraum anzutreffenden Strahlung beschrieben: die solare und die kosmische Strahlung. Teilchen konnen von der Sonne abgestrahlt werden, sowohl kontinuierlich (solarer Wind) oder sporadisch (SonnenausbrUche) oder der Weltraum selbst ist eine Quelle kontinuierliche Strahlung (kosmische Strahlung) Im Abschnitt 3 wird beschrieben, dafi im Umfeld der Erde Gebiete existieren, in denen geladene Teilchen vorzugsweise eingefangen werden (die sogenannten Van Allen-GUrtel). HierfUr ist das Erdmagnetfeld verantwortlich. Dieses Magnetfeld wirkt fUr einen grojien Teil der kosmischen und solaren Strahlung als Abschirmung der Erde. Im Abschnitt 4 wird gezeigt, dafi die Strahlungsumgebung der Erde, unter Beriicksichtigung einiger Hypothesen, modelliert werden kann. Diese Modelle gestatten die Vorhersage von FlUssen und energetischer Verteilung der Strahlung fur eine spezifische Mission und damit die Belastung der elektronischen Komponenten an Bord eines Raumfahrzeugs. Dies wird an einigen Beispielen demonstriert.

The Space Radiation Environment Chapter 8: The space radiation environment Table of contents List of symbols and abbreviations used 1. Introduction 2. Definitions and units 2.1. Definitions related to particle properties 2.1.1. Flux 2.1.2. Fluence 2.1.3. Energy and momentum 2.1.4. Species 2.2. Definitions related to particle-matter interactions 2.2.1. Exposure 2.2.2. Radiation-absorbed dose 2.2.3. Dose equivalent 2.2.4. Linear Energy Transfer 2.3. Additional definition 3. The space environment 3.1. Introduction 3.2. Solar radiation 3.3. Galactic cosmic rays 3.4. Trapped radiation in the Earth's magnetosphere 3.4. L A brief description of the Earth's magnetic field 3.4.2. The trapping and filtering properties of the magnetosphere 3.4.3. Some properties of the Van Allen Belts 3.4.4. Two anomalous regions: The SAA and the Horns 3.5. Cut-off mechanisms for protons and heavy ions 3.6. Role of the orbit characteristics 4. A survey of environment modeling and mission modeling 4.1. Modeling the Earth's radiation environment 4.2. Examples and mission considerations 5. Summary and conclusion Acknowledgements List of references

527

528

D. Brdunig

LIST OF SYMBOLS AND ABBREVIATIONS USED

/\

~

Atomic mass (e.g. for carbon, A = 12)

B

Tesla

Strength of the magnetic field

c

m.s-1

Velocity of light (c = 2.99792 x 108 m. s-1)

E

eV, keV, MeV

Energy

L

-

Mc lUwain's parameter

mo

kg

Rest mass of a particle

M

Tesla. cm3, A.m2

Momentum of the Earth's magnetic dipole

P

MV/amu

Rigidity of a particle

P

kg.m.s-1

Momentum of a particle

R(0)

cm, m

Distance away from the center of the Earth (measured in the plane of the magnetic equator)

R(X)

cm, m

Distance away from the center of the Earth (measured at geomagnetic latitude X)

R.

Unit of Earth's radius (Re = 6.371 10^ cm)

Z

Atomic number

X

m

Photon wavelength Geomagnetic latitude

0(E)

cm"2.s"^MeV-l

Differential flux of particles

0(>E)

cm'^.s'l

Integral flux of particles with energy greater than E

4)(E)

cm'2.MeV-l

Differential fluence of particles

0(>E)

cm'2

Integral fluence of particles with energy greater than E

amu

Atomic mass unit

LEO

Low Earth Orbit

LET

Linear Energy Transfer

SAA

South Atlantic Anomaly

The Space Radiation Environment

529

1. INTRODUCTION Pieces of electronic equipment are increasingly used in hostile environments, which may cause acute functionality or reliability problems. The most commonly encountered hostile environments, where radiation endangers electronics, are the following ones: Space. Nuclear reactors. Medical therapies. Material testing. Semiconductor processing (ion implants. X-ray lithography, plasma etching, etc. Nuclear waste processing (robotics). High-energy particle accelerators. Nuclear warfare. Of all these radiation environments only one will be described in some detail in this chapter, namely that encountered by spacecraft electronics. The reason we chose to treat only this example is that the application of electronics in space is one of the most demanding tasks in an engineering sense. Moreover, the way radiation and reliability aspects are dealt with for space applications can also be applied to other areas. Most particles encountered in space are also encountered in other environments: electrons, protons, photons, heavy ions, fission particles. Neutrons are very rare in space (beyond the upper atmospheric layers) and their effects will therefore only be mentioned very briefly in this chapter. We indicate next, in Tab. 8.1, for the types of radiation environments in which electronic components and equipment are currently used, the types of radiation (particles and photons) encountered, as well as their energy range. The ranges indicated are those of concem for hardened electronics but actual ranges may be much greater. The aim of this short chapter is mostly to provide the reader with an overview of the radiation environment encountered in space. More specialized chapters can be found in other chapters of this book. • How particles and photons interact with matter is reviewed in Chap. 9. • How radiation interacts with the materials making up silicon devices and how it affects device functioning is reviewed in Chap. 10. • Some of the defects (natural or radiation-induced) encountered in silica and the role they play in radiation-induced phenomena are described in Chap. 11. • Finally, how high-energy ions trigger so-called "Single Event Phenomena" in highly integrated silicon devices is detailed in Chap. 12.

D. Braunig

530

These five chapters should give engineers and researchers alike a good basis to understand the major aspects of radiation-induced instabilities in electronic components. For even more detailed descriptions of the natural radiation environment and of radiationcomponent and radiation-system interactions, the reader is referred to five recently published books [39-43]. Particular application in radiation environment Space electronics

Reactor engineering

1 Medical instrumentation 1 Material characterization 1 Semiconductor processing 1 Robotics

1 High-energy accelerators

1 Military equipment

Types of radiation encountered Electrons Protons Ions Quanta Fast neutrons Thermal neutrons Electrons X-Quanta X-rays Various types Various types Depends on application, (mostly X,-Quanta in reactor engineering) Electrons Protons Heavy ions 7-Quanta Compton electrons Fast neutrons

Energy range of concern 0.5-10 MeV 5-450 MeV up to a few GeV 0.1-22 MeV 0.1 to 14 MeV 0.026 eV 1 MeV (not significant) 0.1 to 10 MeV < 0.5 MeV From below 1 eV to 1 MeV From below 1 eV to 1 MeV

1

0.1 to 10 MeV 1 GeV and more 1 GeV and more 1 to 1000 MeV 1 MeV (average energy) From 1 keV to 1 MeV (not significant) From thermal to 14 MeV |

Tab, 8.1 - Radiation environments, types of radiation encountered and energy ranges of concern,

2. DEFINITIONS AND UNITS To be able to describe a given radiation environment and to quantify its effects on electronics, we must first introduce new sets of definitions and units specific to this field: • the first group of definitions is associated with the properties of the particle itself, • the second group describes the interactions of the particle with matter, • a third group describes the source of the particles. 2.1. DEFINITIONS RELATED TO PARTICLE PROPERTIES

2.1.1. Flux Flux O designates the number of particles or photons flowing through, or impinging upon a unit area per unit time. It is expressed in [cm'^.s'l].

The Space Radiation Environment

531

In the case of photons, the term flux is often called intensity. When the particles, or the photons, are distributed in energy, in other words, when there exists an energy spectrum, one distinguishes between integral flux O (> E) and differential flux O (E). The integral flux is the total flux of those particles whose energy is above a given energy level E, whereas the differential flux is the rate of change of the flux with energy, at a specified energy E. Therefore, the integral flux is obtained by integrating the differential flux above energy E, which can be written : 0{>E) = \0{E)'dE

(8.1)

E

Because of this definition, an integral flux is always a decreasing function of energy. Fluxes of space particles are usually described as "omnidirectional", (which means that particles often come from all directions) and are usually considered as isotropic. For isotropic fluxes, it is sometimes useful to introduce the concept of flux per unit solid angle dQ (expressed in steradian). The flux can then be expressed as a number of particles per unit area, unit time and unit solid angle. For isotropic fluxes, unit [cm-^.s-^] is equal to [471 cm-2.s"l.sterl]. In space, fluxes are generally expressed as an average over a period of time and over a given orbit rather than representing an instantaneous value. Let us note, however, that the electron and the proton fluxes of the Van Allen belts (see § 3.4.2) are not onmidirectional but spiral around the magnetic field lines (as illustrated in Fig. 8.8). This peculiarity can be very important in hardening satellite systems. 2.1.2, Fluence Fluence O is the number of particles flowing through, or impinging upon a unit area, over a longer period of time. It is a time-integrated flux and it is expressed in [cm-^]. Just as we did when defining fluxes, we distinguish between "integral", "differential" and "solid-angleresolved" fluences. In Fig.8.1 the differential and integral proton fluences encountered for a specific space mission have been plotted versus energy. 2.1.3. Energy and momentum The energy E of a particle or a photon is usually expressed in units of eV, keV or MeV. Another common expression is often used, namely energy per nucleon expressed in [MeV/amu], where amu is the atomic mass unit of the energetic particle (e.g. A(H) = 1, A(He) = 4, A(C) = 12). These definitions apply to the kinetic energy of the particle. For instance, 1 MeV expresses the kinetic energy an elementary charge gains in an electrostatic potential of 1 MV. Let us note that a particle should be considered as relativistic when its kinetic energy approaches the energy equivalent of its rest mass (e.g. electrons whose energy approaches 0.511 MeV or ions whose energy, expressed in GeV, approaches - A).

532

D. Braunig Integral and Differential Ruence (LEO,cinxilar,800kn%98^ 1.00E+13

1.00E+12 jDifferemiai hiuenoe in p^cnrr^zsmnev | ^

IH^^

1 '"^*.»^_^

1.00E+11 lU

^H

O 2 1.00E+10

^Kji

^^ "-^'^^^

1.00E-H)9

y-

—p^ 1.00E408

'—

\

Integral Ruenoe in p/an^2Br

1.00E+07 1.00E-01

I.OOE+OO

1.00E+01

1.00Ef02

PROTON ENERGY in MeV

Fig. 8.1 - The integral and differential proton fluences encountered for a circular orbit (800 km, inclination 98°), are plotted versus energy.

The momentum p of a particle is given by p=mv, where m is the mass of the particle and v its velocity. There exists a relativistic relationship linking energy and momentum, expressed as : P'C^^E'{E

+ 2'mo'C^)

(8.2)

where nio is the rest mass of the particle and c is the velocity of light. The energy of a photon is given by E = hv = hc/A., where h is Planck constant, v is the frequency of the photon and X is its wavelength. The momentum of a photon is given by: p = hv/c. 2.1A. Species The term "radiation species" includes photons and particles. Photons may differ in energy, whereas particles may differ in energy, mass and charge state. It is sometimes useful to identify a particle by its name, mass, number of charges within the nucleus and its charge state. For instance in expression 2 He

, He stands for Helium, A is the atomic mass (e.g. 4),

Z is the charge of the nucleus in units of elementary charge and 2+ indicates a doubly charged state. When an atom is totally ionized, and this is a common occurrence in space, then its charge Z is approximately equal to A/2 for all species except for Hydrogen, where Z/A equals 1. Some properties of particles commonly encountered in space are summarized in Tab. 8.2 below.

The Space Radiation Environment Species

Mass

Atomic mass

533 Rest mass

1 Electrons

9.1M0-31kg

0.000549

0.511 MeV

1 Protons

1.672-10-27 kg

1.007277

938.259 MeV

Neutrons

1.675-10-27 kg

1.008665

939.553 MeV

« 6.710-27 kg

4.0026

= 4GeV

1 Helium ions

Tab, 8.2 - Some properties ofparticles commonly encountered in space. 2.2. DEFINITIONS RELATED TO PARTICLE-MATTER INTERACTIONS

To properly describe how energy is transferred from an energetic particle to an absorbing material, intemational definitions have been introduced. Some of the definitions and units used in this chapter are briefly described next. A much more thorough description can be found in Chap. 9. 2.2.1. Exposure The exposure (E) describes the amount of ionization charges generated by a radiation species per unit mass of standard atmosphere. Exposure is expressed in units of Coulomb per mass [C/kg]. An older unit is the Roentgen (= 2.56-10-4 C/kg). 2.2.2. Radiation-absorbed dose The dose (D) is the energy absorbed per unit mass of the material being irradiated (e.g. silicon). A dose of 1 Joule per kilogram is called a Gray (Gy). A unit still commonly used in the literature is the rad, which is just 10"^ Gray. The nature of the material being irradiated should always be mentioned, e.g. 1 Gy(Si). For high-energy charged particles, most of the absorbed energy is consumed in ionization phenomen. There results that the terms "dose" and "ionizing dose" are sometimes used interchangeably. This approximation is of course not valid for neutral particles such as neutrons, or for low-energy ions. 2.2.3. Dose equivalent The dose equivalent (H) has the same meaning as the radiation-absorbed dose except that it introduces a qualifying and weighting factor q to account for the fact that human tissue responds differently to different ionizing radiation. The unit of dose equivalent is the Sievert (Sv). It has the same dimension as the radiation-absorbed dose since we can write: H = q.D, where q is equal: to 1 for electrons and y 's, to 10 for neutrons and protons and even to 20 for a's from radionuclides. The older unit of dose equivalent is the rem, which corresponds to an absorbed dose of one rad.

534

D. Brdunig

2.2.4. Linear Energy Transfer Other definitions are needed to express the amount of energy transferred per unit pathlength. The electronic stopping power dE/dx is a ratio which describes the energy which a charged particle loses through ionization phenomena when travelling through a material (e.g. silicon). The Linear Energy Transfer (LET) is just a different term for electronic stopping power with a dimension of MeV/|im. (The electronic stopping power is sometimes normalized to the specific mass of the absorbing material (i.e. dE/pdx), in which case it is expressed in MeV.cm^/g). The energy lost through ionization phenomena is calculated by using the well-known Bethe-Bloch equation. The slowing down due to ionization is accompanied by the generation of electron-hole pairs. The effects of such a generation will be covered in more detail in Chaps. 9, 10, 11 and 12. The LET value of a particle depends both on its atomic mass and on its energy. Thus, for a flux of various particles of various energies, we are led to define a LET spectrum, giving the number of ions corresponding to a given LET. Some preliminary examples of LET spectra will be given in § 4.2 of this chapter. 2.3. ADDITIONAL DEFINITION

Activity of a radioactive substance The activity (A) of a radioactive source is defined as the number of transitions occurring per second. The unit of activity is called the Bequerel (Bq) whose dimension is [s"l]. An older unit is the Curie (Ci), which equals 3.7-10^0 per second. 3. THE SPACE ENVIRONMENT 3.1. INTRODUCTION

The Earth is part of our Sun-dominated planetary system and it travels through the space of our galactic system. Due to its own magnetic field, the Earth can be considered, in a first approximation as a magnetic dipole. There exists, however, a number of interdependencies which link the Sun's activity, the galactic radiation and the shape and magnitude of the geomagnetic field. The Earth is, to a large extent, protected from outside radiation by its magnetic field. This field acts as a shield against the solar wind (see below) and creates a cavity called the geomagnetic cavity, illustrated in Fig. 8.2. The field deflects also the cosmic rays, i.e. energetic ions coming from outer space, as we shall see in § 3.5. Spacecrafts (satellites, launchers, space stations, space probes, etc.) are exposed to the following types of radiation: • • • •

solar radiation, mainly solar flare protons and solar wind particles, galactic cosmic rays, protons and electrons trapped in the radiation belts, Bremsstrahlung due to the scattering of energetic electrons in the spacecraft material.

The Space Radiation Environment

535

MAGNETOPAUSe

DAYSIDECUSP

DAYSIDECUSP

MAGNETOPAUSE CURRENTS

PLASMASPHERE

Fig. 8.2. - Illustration of the geomagnetic cavity (for more detail see [11]).

The origin of these contributions - except for Bremsstrahlung - will be discussed in the following paragraphs in more detail. Models currently used to quantify the amount of radiation received by a spacecraft will be presented in Sect. 4 and some examples will be given. 3-2. S O L A R RADIATION

The solar radiation encountered in space originates from the solar wind and from solar flare events. The solar wind is due to the constant emission, by the sun, of low-energy particles consisting of protons (91.2%), singly and doubly charged He ions and a very small amount of electrons whose energy is less than 500 eV. Because of the Earth's magnetic field, solar wind particles cannot come close to the Earth except through the polar regions [1], Solar Flares are bursts of radiation strongly correlated with the cycles of sun spot activity at the Sun's surface. Due to their large fluxes and high energies, the particles emitted during a solar flare constitute a severe problem for a spacecraft but on a probabilistic basis only. For instance, an intense period of solar activity occurred in March 1991 and triggered a sequence of major effects, including the generation of a second inner radiation belt around the Earth, functional anomalies in satellites, and power surges in electrical power grids on the ground [2]. The cycle of growing and vanishing sun spot groups on the Sun's surface has a duration of approximately 22 years, with a reversal of the magnetic fields at the Sun's surface every 11 years. During this cycle, fluctuations of the magnetic fields take place in the upper layer of the solar atmosphere. A consequence of these fluctuations is an outpouring of X-rays, radio waves and UV-radiation as well as an emission of solar wind plasma and energetic particles. These photons and particles are emitted during solar flares and solar storms and their fluxes vary over several orders of magnitude (see for instance [3]).

536

D.

Brdunig

There are anomalous large (AL) solar flares, which are rare, last for periods of up to 8 hours and contribute most of the high-energy solar particles. Ordinary (OR) solar flares occur very frequently, last for a few minutes and do not contribute significantly to the overall solar flux.

I

r

1955

n—r

1965

1980 August 1972

Fig..8.3 - Illustration of solar cycles. Both the number of sun spots (—) and the proton fluences due to solar flares (histograms) are represented (see text) [39].

Both AL events and OR events are illustrated in Fig. 8.3 for the last three complete cycles (19, 20, 21). The continuous line of Fig. 8.3 is a plot of the number of solar spots observed during these cycles. The peaks correspond to the fluence of emitted particles (mostly protons) observed during AL or OR flares. Seen from the vicinity of the Earth, one distinguishes between simultaneous and delayed solar events, depending on the velocity of the individual constituents. The first group (travel time 8.3 minutes) consists of visible light, radio waves, UV-light and X-rays, while the second group (travel time 20 minutes to 50 hours) consists of solar flare and solar storm particles. When entering the Earth's magnetosphere, the charged particles produce large disturbances of the geomagnetic field lines. The amount of exposure of a spacecraft to solar radiation is of course strongly dependent on the orbital parameters of the craft. The ranges in flux and energy of the particles encountered in the solar wind and in solar flares is illustrated in Fig. 8.11. 3.3. GALACTIC COSMIC RAYS

There exists a galactic cosmic radiation in deep space. It is distributed uniformly and is considered as omnidirectional, although for Low Earth Orbits (LEO), the shadow of the Earth plays a significant role in its distribution. The main constituents of this radiation are protons (85%), He ions (14%) and about 1% heavier nuclei. The abundance of heavy nuclei is similar to the universal distribution of elements.

537

The Space Radiation Environment

However, hydrogen and helium have a smaller relative abundance in the galactic cosmic rays whereas the nuclei of the iron group as well as lithium, beryllium, boron and other nuclei with an odd Z number are enhanced in flux, as visible in Fig. 8.4 [5].

o

> 0^

Element-atomic number Fig. 8.4 - Relative abundance of the elements contributing to cosmic rays compared to universal abundance.

I > Fig. 8.5 - The differential fluxes of the most abundant constituents of cosmic rays are plotted versus energy, (after [5]).

in

10^

10^

10^

Kinetic energy in [MeV/amu]

10^

538

D. Brdunig

The energy of cosmic rays extends over an extremely vast range, from 10 to 10^^ MeV. The differential energy spectra of the cosmic ray ions in the neighborhood of the Earth exhibit a maximum at 1 GeV/nucleon. Outside the geomagnetic field, the flux of cosmic ray particles is approximately 4 nuclei per cm^ per second, mainly consisting of protons [4]. Because of the interactions with the solar wind and with the interplanetary magnetic field, this flux is reduced at the lower energy end and its fluctuations are related to the solar activity. Figure 8.5 presents the differential spectrum of four of the most abundant nuclei [6, 7]. The reason for the increase in H and He ion fluxes at low energies is due to the spallation of heavy ions into lighter ones. The integral flux of cosmic rays is represented as a function of energy in Fig. 8.13. 3.4. TRAPPED RADIATION IN THE EARTH'S MAGNETOSPHERE

3.4.1. A brief description of the Earth's magnetic field In a first approximation, one can consider that the Earth acts a magnetic dipole (at least within a distance of about 5 Earth radii). The dipole momentum [M] expressed in [Tesla.cm^] can be written^^^: M = /?f • 0304 • 7 0 " "^ = 7M -10^^ T.cm^

(8.3)

where R^ is the Earth's radius, which equals 6.371.10^ cm, [8]. The magnetic field and the associated field lines can be described by the following set of equations using polar coordinates:

5a)=

M ^4-3cos^ (X)

• R{0f

and

(8.4)

cos^ (X)

2 R{X)----R(0)-cos (X)

(8.5 a)

or

L{X)^

R{X) Re

= Rio) ——cos 2(,^ U)

(8.5 b)

Re

Here B{X) is the magnitude of the magnetic field, which remains tangent to a field line, as a function of A., X is the geomagnetic latitude and R(0) is the distance at which the field line intersects the equatorial plane. This allows an R(A.) representation of the geomagnetic properties of the Earth, as illustrated in Fig. 8.6. Parameter L was introduced by McHlwain in his B-L space [9, 10]. L is a reduced form of the locus of the magnetic field lines and is equal to the geocentric distance at which the shell intersects the magnetic equator. It is measured in units of Earth radii Re. ^^^ In the MKS unit system, M = 8.27.1022 A.m^.

The Space Radiation Environment

539

North

0 1 South

2

3 4 5 Distance in Re

Fig. 8.6 - Illustration of the geomagnetic field lines and ofparameter used to describe them.

At constant L, the value of B varies from a minimum at the magnetic equator to a maximum where the field lines intersect the surface of the Earth. The B-L space is a fixed and idealized coordinate system which does not take into account any temporal change. 3.4.2. The trapping and filtering properties of the magnetosphere The shape of the magnetic field lines has several important consequences which we detail next [11, 12]: • the geomagnetic field acts as a filter for certain types of charged particles entering the Earth's magnetosphere, • there are allowed cavities where particles are trapped and, conversely, forbidden zones where particles of different properties are rejected, • the polar regions are more easily accessible than the equatorial plane for particles of identical properties, • the properties of the geomagnetic filter function enable electrons and protons to form a stable and structured radiation belt, where the abundance of these particles is significantly greater than outside the magnetosphere, • the same filter function rejects a large portion of heavy charged ions whose energy is insufficient to penetrate the inner regions of the magnetosphere (for more details see § 3.5),

540

D, Brdunig

• the stable trapping of electrons, protons and light ions results in a structured set of radiation belts (Van Allen belts), illustrated in Fig. 8.7, which is stationary and whose fluctuations in density and shape is mainly caused by variations in solar activities. Thanks to this trapping and filtering effect, the Earth is relatively protected from outside radiation phenomena. ^

Solar wind Geomagnetic tail

Radiation belts

Fig. 8.7 - Cross-sectional view of the geomagnetic cavity featuring: the solar wind and the associated shock wave, the magnetopause and the radiation (Van Allen) belts (after [42],

3.43. Some properties of the Van Allen Belts The shape of the geomagnetic field and especially the regions of maximum magnetic field strength near the geomagnetic North and South poles determine the motion of the trapped particles. The particles of velocity v are submitted to a force given by F = q v A B . They spiral around and move along the magnetic field lines and are reflected at "conjugate mirror points", as illustrated in Fig. 8.8. The location of these mirror points on a field line depends on the energy of the particle itself. Moreover, the particles drift in a direction perpendicular to the field lines. As a result of their opposite charges, electrons drift Eastward whereas protons drift Westward (azimuthal drift). Typical features of the motion of energetic particles at low altitudes are shown in Tab. 8.3. Particle

Gyration radius

Gyration period

Bounce period

Azimuthal drift period

velocity p=v/c

10 MeV protons

50 km

0.01s

0.5 s

4min

0.2

1 MeV electrons

0.6 km

10|LIS

0.1s

lOmin

0.9

Tab. 3 ' Some characteristics of the motion of particles trapped at low altitudes (^1.5 R^)

The Space Radiation Environment

541

Magnetic field line

Fig. 8.8 - Spiralling and bouncing behaviour of electrons and protons within the geomagnetic field.

The trapping zones are structured into an "inner" and an "outer" belt as illustrated by Figs. 8.9 a, b, c. Protons are entirely trapped within the inner belt and possess energies ranging from 0.5 MeV to more than 400 MeV. In the equatorial plane, their energy decreases conversely with the radial distance from the Earth as shown in Fig.8.9 a. Electrons have energies of up to 7 MeV in the outer belt with fluxes exceeding those of the inner belt (E < 5 MeV). Due to the action of the Sun we have to distinguish between the day and night sides. There are strong variations in shape and population of the belts including diurnal cycles and the 11-year solar cycle as shown in Tab. 8.4 for low altitudes. The outer Van Allen radiation belt typically extends from the plasmasphere to somewhat beyond the geosynchronous altitude, depending on the geomagnetic activity. SOLAR MAX

SOLAR MIN

1

Electron intensities

higher

lower

1

Proton intensities

lower

higher

Tab. 4 - Influence of the solar activity on low-altitudes particles fluxes.

3.4.4. Two anomalous regions: The SAA and the Horns For Low Earth Orbits (LEO) (typically above 500 km) there exist two important contributions to the overall radiation level due to the shape of the geomagnetic field lines: the South Atlantic Anomaly (SAA) and the polar Horns [11]. The SAA is due to the fact that the geomagnetic axis is titled by approximately 11° off the Earth's rotation axis and is displaced by about 500 km towards the Westem Pacific as illustrated in Fig. 8.10. This results in stronger field values at LEOs and correspondingly higher electron and proton fluxes in this geographic region (above Brazil). This is of particular significance for space electronics orbiting on an LEO with a large inclination since the radiation flux is larger by several orders of magnitude in this region compared to other regions of the mission. An illustrative example was given by the Hubble space telescope.

542

D . Brdunig Geostationary orbit Large space telescope ^4

•o

"£ o Q. LU

O "Q. O to 10

20

30

altitude in 10'km

a) electrons

geomagnetic axis

>so(Qr min ' solar max

protons

geomagnetic axis 4

b) Electrons with E > 1 MeV

c) Protons with E > 10 MeV

Fig. 8.9 - Illustration of the Van Allen belts, a) Schematic cross section of the Van Allen Belts in the equatorial plane. Several integrated fluxes of electrons and protons are plotted as a function of altitude. The proton distribution in the inner zone and the dual distribution of the electrons (inner and outer zones) are clearly visible. An LEO and a geostationary orbit are indicated (after [37]). b) Set of isoflux contours describing the trapping belts for electrons of energy > I MeV. c) Idem for protons of energy > 10 MeV.

The Space Radiation Environment

543

Before the 1993 retrofitting of the telescope electronics, every time the spacecraft went through the intense radiation belts of the SAA, the memories suffered from enhanced dark currents and their contents had to be corrected. The Homs at mid-latitude levels are tails of the outer electron belt coming very close to the Earth because of the geomagnetic field. Figures 8.9 a and b illustrate this feature very clearly as well as Fig. 8.12 based on the application of the AE-2 model [13].

Fig. 8.10 - Origin and illustration of the South Atlantic Anomaly (after [42]).

3.5. CUT-OFF MECHANISMS FOR PROTONS AND HEAVY IONS

The penetration of charged particles into the geomagnetic space, in particular in the case of solar flare protons and cosmic heavy ions, is hampered by the shielding properties of the Earth's magnetic field. The more energy a particle possesses, the closer to the Earth it can get. A quantitative description of these "cut-off mechanisms uses a specific term, the rigidity P, whose value determines how easily a charged particle is reflected by the geomagnetic field [8]. The rigidity P of a (relativistic) particle of energy E is given by:

P = pcA/Z

= —ylE^-\'2'm^'C^'E

(8.7)

In this expression m^ is the rest mass of the particle, A is the atomic mass unit (amu), Z is the charge of the nucleus and E is the energy of the particle expressed in MeV. The dimensions of P are [MV/amu]. In the case of protons, ratio A/Z equals 1. For heavier ions, A/Z equals 2 or is very close to it. For low-energy particles, the rigidity is proportional to E^^^ whereas in case of high energy it is proportional to E. We can calculate the distance (L) in units of Earth radii, at which an incoming particle of rigidity P (expressed in MV/amu) and moving in a meridian plane can come close to the Earth [42]. It yields: L=

15.9 10^

cos X

(8.8)

D. Braunig

544

The rigidity concept [14, 15] is used as well to describe the flux spectra of solar protons, for instance as: ^p{>P)

where Op

(8.9)

= ^Pf)-exp\

is the total proton flux for an event expressed in [# protons/cm^] and PQ is

characteristic of a particular solar event. As seen from Fig. 8.11, protons can reach a region corresponding to a geosynchronous orbit (i.e. L = 6 to 7) only if their energy exceeds 87 MeV (for ions 23 MeV/amu). Particles can reach Low Earth Orbits (LEO) only if their energies are greater than 3 GeV for protons, and 1 GeV/amu for ions. For LEO, in addition, atmospheric effects must be considered. But for a polar orbit of nearly 90° inclination, a much lower energy is needed to reach these regions. 12

III

10

H L 6

m\ IONS 10

a)

100

1000

Energy (in MeV for protons and MeV/amu for ions)

23 MeV/n 12 MeV/n

Fig. 8,11 - Illustration of the cut-off mechanism, a) illustrates the penetration depth of solar and cosmic particles in L coordinates (in units of Earth radii) as a function of energy (in units of MeV/amu (ions) and MeV (protons)), b) is a visualization of that cut-off effect giving the total energy required to penetrate the magnetosphere, (after [11]).

The Space Radiation Environment

545

3.6. ROLE OF THE ORBIT CHARACTERISTICS

Due to the shielding behaviour of the geomagnetic field, how satellite electronics will be affected depends on the orbit used. For instance, on a geosynchronous orbit (i.e. at an altitude of about 36 000 km), the main constituents of the encountered radiation are electrons in the 0.5 to 8 MeV range. Therefore, a complete shielding of the equipment is very difficult to achieve due to the generation of Bremsstrahlung by these high-energy electrons. Since the conmiunication satellites which are on such orbits have a mission duration of more than 7 years, the (total) absorbed dose can be high and the electronic components must be able to withstand these high accumulated dose values. Solar flares must also be taken into account on a statistical basis. For Low Earth Orbits (LEO), i.e. for altitudes ranging from 200 to 800 km, one must distinguish between equatorial and polar orbits. Because of the configuration of the geomagnetic field lines, particles encountered on polar orbits are primarily protons and highly energetic ions. Overall, the level of radiation encountered depends strongly on the altitude of the spacecraft since only a few hundred kilometers in altitude may cause large differences in flux due to the steep increase in proton flux at the tail of the inner Van Allen belt. Only a very accurate knowledge of the energy and flux distribution of the radiation species permits a reliable prediction of the radiation threat. Models currently available to describe the environment are discussed next. Let us note that an accurate prediction must also take into account the shielding effect of the equipment itself. 4. A SURVEY OF ENVIRONMENT MODELING AND MISSION MODELING The modeling of the radiation environment is important because it enables: 1) a calculation of the fluxes encountered by the spacecrafts, and 2) a forecast of the type of problems the electronic parts (especially the semiconductor components) will experience during a mission. 4.1.

MODELBSG THE E A R T H ' S RADIATION ENVIRONMENT

From the beginning of unmanned spaceflights, experimental data were gathered to get a comprehensive picture of the Earth's radiation belts. Due to limitations in measurement equipment and theoretical modeling, the description of the constituents of the Earth's environment and of their distribution had to be continuously improved. Today, the descriptions of the environment are still "stationary" ones, with a few exceptions, and for example do not illustrate the temporal changes due to variations in solar activities. Up to now, 8 models describing the Earth's environment have been successively established for electrons (AE-) as well as for protons (AP-). They are called AE-1, AE-2, AE-3, AE-4, AE-5, AE-5 projected (AE-5P), AE-6, AE-8 and AP-1, AP-2, AP>3, AP-4, AP-5, AP-6, AP-7, AP-8. Following the NASA-Publication NSSDCAVDC- A- R&S 91-29 by James I. Vette [13], a short tabular description of the individual models is given next (see Tab. 8.5). Figure 8.12 gives an illustration of data gathered in the AE-2 model.

546

D, Brdunig

The CREME model was developed at the Naval Research Lab to have a tool for predicting Single Event Upsets caused by cosmic rays. A series of reports [31 - 34] entitled "Cosmic Ray Effects on Microelectronics (CREME)" linked the Linear Energy Transfer (LET) of ions and its spectrum (number of ions versus LET) to the SEU sensitivity of individual integrated circuits. The CREME model describes the space environment and the radiation-component interactions leading to SEU and contains estimates of individual ion fluxes from protons up to Uranium^^\ It also takes into account reductions in flux intensity due to solar modulation, geomagnetic cut-off and the Earth's shadowing effect. The transport code includes heavy ion fragmentation and ionization losses for each element individually.

Fig, 8.12 - Illustration of the electron belts. Isoflux lines have been computed (using the AE-l model), for electrons of energy > 1 MeV.

90 80 70 60 50 40 30 20 K) 0 10 20 30 40 50 60 70 80 90 NORTH GEOGRAPHIC LATITUDE SOUTH

SOLPRO [35] is a simple statistical model predicting solar flares and is based entirely on satellite spectral measurements of the 20th solar cycle. Figure 8.13 sunmiarizes and illustrates the relative importance of each radiation species encountered in space.

(2)

Ions with atomic masses larger than that of Fe play no significant part.

The Space Radiation Environment

547

Van Allen electron belt Model

Range [Re]

Energy range [MeV]

AE-1

1.2-3

0.3-7

Omnidir. Integral Flux

[17]

AE-2

1.1-6.3

0.04-7

Solmax, SAA and Homs

[18]

AE-3

6.6

0.01-5

GEO, SOLMAX, SOLMIN

[19]

AE-4

3.0-11.0

0.04-4.85

Time var. SOLMIN, SOLMAX

[20-21]

1

AE-5

1.4-2.8

0.04-4

Inner zone, atmospheric cut-off

[22 - 23]

1

AE-6

1.2-11

0.04-5

Decay times, Starfish

[24]

No release

[25]

The most advanced model yet

[26]

AE-7 AE-8

1.2-4/3.011/2.4-3

0.04-7

Remarks

References

Van Allen proton belt Range [Re]

Energy range [MeV]

AP-1

1.17-3.15

30-50

Integral flux, solar cycle var.

[17]

AP-2

1.17-3.51

15-30

Integral flux, solar cycle var.

[17]

AP-3

1.17-2.9

>50

Integral flux, solar cycle var.

[17]

AP-4

1.17-4.6

4.0-15.0

Integral flux, solar cycle var.

[17]

AP-5

1.2-6.0

0.1-4

Variation, differential flux

[27]

1.2-4

4-40.0

Improved data

[28]

AP-7

1.15-3.0

50-500

Improved data

[29]

AP-8

1.15-6.6

0.1-400

Static model with solar cycle

[30]

Model

|AP-6

Remarks

References

Solar flares and cosmic rays I

Model SOLPRO

1CREME

Remarks

References

Solar Flares

[35]

Cosmic Rays

[31 - 34]

Tab. 8.5 - Models currently (1995) available describing trapped particles, solar protons and cosmic rays. 4.2.

EXAMPLES AND MISSION CONSIDERATIONS

To illustrate the possibilities of modeling, we present next three examples which have been calculated using a software called Space Radiation [36], based on the CREME model. These examples are: the geosynchronous orbit in the best and the worst-case parking position, the impact of solar activity for a circular LEO and the influence of orbit inclination on the LET spectrum for an LEO.

D, Brdunig

548

Solar wind protons 10

10

C/5

10

Trapped electrons

q

I—peak

Geostationary 10

Y Trapped Protons-peak

Solar protons Major flare

X! US

10

7-Year average

Galactic Cosmic rays

10-^

10^

10

10

1

10

10

10

10

Particle energy E [MeV] Fig. 8.13 - Integral spectra of particles encountered in space [37].

In Fig. 8.14 the electron fluence per cm^ and per day as a function of electron energy is shown for two locations, which represent the worst and the best-case conditions for a geosynchronous orbit. The best-case location is at L = 7,70° West, and the worst-case is found for L = 6.6, 160° West. The radiation exposures between the two locations differ by about one order of magnitude for intermediate energies (because of the altitude, the protons play no part and only electrons contribute to the absorbed dose).

The Space Radiation Environment

1.00E+13

^ -d
1.00E+12

e

1.00E+11

W A N

^

1.00E+10 1.00E+09 1.00E-I-08

J3

1.00E-I-07 1.00E+06 1.00E+05 c3 ;-4

<

1

geosynchronous Orbit

•e-

X

549

^

IN

^ ^

1

^ [

1 1

P

1

|WORSTCASE:160"W,L=6.6|

£>.>—

|BESTCASE:70*W.L=7|

I —

^

1

)

N

i

1.CX)E+04 2

3

4

Energy [MeV]

Fig. 8.14 - The (averaged) integral electronfluxesdetected on a geosynchronous orbits for best and worst-case parking positions^ versus energy (after [36]).

In Fig. 8.15 the daily averaged integral electron flux encountered on a circular orbit (600 km) with a 60° inclination, for low solar activity, is compared to the electron flux encountered for maximum solar activity. The electron integral fluence (per cm2) averaged over a period of one day shows a pronounced difference, particularly at low energies as already indicated in Tab. 8.4, because of an enhanced electron fluence for Solar Max periods. Finally, the dependence of LET spectra encountered for LEO's on the inclination angle of the orbit are indicated in Fig. 8.16 as an example which will be described in more detail in Chap. 10. Whereas the fluences for low (BO'') and medium (60°) inclinations are quite similar, the polar orbit (90°) exhibits much more particles per unit area and unit time due to the weaker shielding capabilities of the geomagnetic field at that location. The sharp cut-off at about 500 MeV.cm^/g reflects the strong contribution of protons in the low LET range, since their LET never exceeds this value. 5. SUMMARY AND CONCLUSION More and more items of electronic equipement are being used in space aboard spacecrafts. While in space, they are submitted to a wide array of particles, such as: electrons and protons of the Van Allen Belts, protons and heavy ions emitted during solar flares and protons and heavy ions which make up the cosmic rays. The performance of on-board electronic components and equipment may degrade quickly if precautions are not taken.

550

D. Brdunig

Fig. 8.15 Daily averaged integral electron flux encountered on a circular orbit (600 km, 60°) versus energy (after [36]).

• -e-

1E-^02 1E-02

lE-OI

lE-^OO

1E^01

Energy [MeV] 1.00E+07

q ^ W

90° 1.00E+06 60°

A

-eo

|30 ol

1.00E+05

13 ^S

N

1.00E+04 r r\ rVsh1- /en/ Pir OliOuiai v^i uii ^\j\M/wr\iiiy

Q 1.00E+03 1.00E+00

1.00E+01

1.00E+02

1.00E+03

LET [MeV.cm2.g-i] Fig.8. 16 Daily integralfluenceof particles encountered on a circular orbit (600 km) for different inclinations versus LET. (after [36]).

The Space Radiation Environment

551

The need for an accurate knowledge of the Earth's radiation environment has thus become imperative. Computer models of environment, such as AP-8 for protons and AE-8 for electrons, developed by NASA, have been widely used to predict the radiation threat for a given space mission. A severe disadvantage of these models is that they describe a stationary situation that does not correctly reflect the real situation. Therefore activities are underway at NASA and ESA to study the dynamic behaviour of our radiation environment and to improve the accuracy and the reliability of the predictions. ACKNOWLEDGEMENTS The author wishes to thank his colleagues at the Hahn-Meitner-Institut for fruitful discussions and the editors G. Barbottin and A. Vapaille for their thorough review. LIST OF REFERENCES [I] King J.H., J. Spacecraft 11, No. 6, (1974), p.401. [2] Shea M.A.,D.F. Smart, J.H. Allen and D.C. Wilkinson, "Spacecraft Problems in Association with Episodes of Intense Solar Activity and Related Terrestrial Phenomena During March 1991", lEEE-NS 39,6 (1992), p. 1754. [3] Adams J.H. Jr and A. Gelman, IEEE NS-31,6, (1986), p.l212. [4] Byrne F.N.," A Survey of Solar Flare Phenomena", Space Set. Rev. 3,(1964), p.319. [5] Petersen E.L., "Basic concepts on Single Event Upsets" lEEE-NSREC Short Course, July 1983, Gatlinburg/Tennessee. [6] Adams J.H. Jr., "The Natural Environment Inside Spacecraft", lEEE-NS 29,6, (1982), p. 2095. [7] Adams J.H. Jr., "The Variability of Single Event Upsets Rates in the Natural Environment", lEEE-NS 30, 6,(1983), p.4475. [8] Stormer C , Polar Aurora, Oxford University Press, London,1955. [9] Mclllwain C.E." Magnetic Coordinates" in Radiation Trapped in the Earth Magnetic Field, Ed. B.M. McCormac (Reidel,Holland), (1966), p. 45. [10] Mclllwain C.E., J. Geophys. Res. 66, No.ll, November 1961, p. 3681. [II] Stassinopoulos E.G., " Radiation Environments of Space", lEEE-NSREC: Short Course, Reno, Nevada, July 16, 1990. [12] Haffner J.W., Radiation and Shielding in Space, Academic Press, 1967. [13] Vette J.I.," The NASA/National Space Science Data Center Trapped Radiation Environment Model Program (1964-1991)", NSSDCAVDC-A-R&S 91-29, National Space Science Data Center, Greenbelt,Maryland, November 1991. [14] Rosen A., "The Dynamics of the Outer Zone", Space Science, Ed.D.P. Le Galley (Wiley, New York), (1963), p. 275. [15] Webber W.R., "Solar Flare Proton Data", Nucleonics 21, (1963),p. 154. [16] Nichols D.K., "Trends in Electronic Parts Susceptibility to Single Event Upset Space Station Environment", JPL D-2767, September 1985. [17] Vette J.I.,"Models of the Trapped Radiation Environment", Vol.1: Inner Protons and Electrons NASA SP3024, Vol.1, 1966. [18] Vette J.I., A.B.Lucero and J.A.Wright, "Models of the Trapped Radiation Environment", Vol.2: Inner and Outer Zone Electrons, NASA SP-3024, Vol.2, 1966. [19] Vette J.I., A.B. Lucero and J.A.Wright, "Models of the Trapped Radiation Environment", Vol.3: Electrons at Synchronous Altitudes, NASA SP-3024, Vol.3, 1966.

552

D.

Brdunig

[20] Singley G.W. and J.I. Vette, "The AE-4 Model of the Outer Radiation Zone Electron Environment", NASA GSFC National Space Science Data Center, NSSDC 72-06, August 1972. [21] Singley G.W. and J.I. Vette, "A Model Environment for Outer Zone Electrons", NASA GSFC National Space Science Data Center, NSSDC 72-13, December 1972. [22] Teague, M.J. and J.I.Vette, "The Inner Zone Model AE-5 ", NASA GSFC National Space Science Data Center, NSSDC 72-10, November 1972. [23] Teague, M.J. and J.I.Vette, "The Use of the Inner Zone Electron Model AE-5 and Associated Computer Programs", NASA GSFC National Space Science Data Center, NSSDC 72-11, November 1972. [24] Teague M.J., K.W.Chan and J.I.Vette "AE-6: A Model Environment for Trapped Electrons for Solar Minimum", NSSDCAVDC-A-R&S 76-04, National Space Science Data Center, Greenbelt, Maryland, March 1976. [25] Chan K.W., M.J.Teague, N.J.Schofield and J.I.Vette," Modeling of Electron Time Variations in the Radiative Belts", American Geophysical Union Geophysical Monograph 21, Quantitative Modeling of Magnetospheric Processes, June 1978. [26] Vette J.I.," The AE-8 Trapped Electron Model Environment", NSSDCAVDC-A- R&S 91-24, National Space Science Data Center, Greenbelt,Maryland, November 1991. [27] King J.H.," Models of the Trapped Radiation Environment", Vol.4: Low Energy Protons, NASA SP- 3024, Vol.4, 1967. [28] Lavine J.P. and J.I.Vette," Models of the Trapped Radiation Environment", Vol.5: Inner Belt Protons, NASA SP-3024, Vol.5, 1969. [29] Lavine J.P. and J.I.Vette," Models of the Trapped Radiation Environment", Vol.6: High Energy Protons NASA SP-3024, Vol.6, 1970. [30] Sawyer D.M. and J.I.Vette," AP-8 Trapped Proton Environment for Solar Maximum and Solar Minimum",NSSDC 76-06, National Space Science Data Center, Greenbelt, Maryland, December 1976. [31] Adams, J.H., R.Silberberg and C.H.Tsao, "Cosmic Ray Effects on Microelectronics",Part l:The Near Earth Particle Environment", NRL Memorandum Report 4506, August 25,1981. [32] Adams J.R.," Cosmic Ray Effects on Microelectronics", Part 4, NRL Memorandum Report 5901, December 31, 1986. [33] Adams J.H., J.R.Letaw and D.F.Smart," Cosmic Ray Effects on Microelectronics", Part 2: The Geomagnetic Cutoff Effects, NRL Memorandum Report 5099, May 1983. [34] Tsao C.H., J.H.Silberberg, J.H.Adams and J.R.Letaw," Cosmic Ray Effects on Microelectronics", Part 3: Propagation of Cosmic Rays in the Atmosphere, NRL Memorandum Report 5402, August 1984. [35] Stassinopoulos E.G., "SOLPRO: A Computer Code to Calculate Probabilistic Energetic Solar Proton Fluences", Rep. NSSDC No. 75-11, National Space Science Data Center, Greenbelt, MD, April 1975 [36] SPACE RADL\TION, Users Manual, DOS-Version 2.0,Trademark of Severn Communications Corporation, 1992. [37] Holme-Siedle A. and Adams L. The Radiation Design Handbook, ESA PSS-01-609, Draft, 1989 [38] McGuire at al. "Solar flare particle fluence during solar cycles 10-20 and 21", 18th Int. Ray Conf., Vol.4,1983, p.66 Recent books on the effects of radiation on electronic components [39] [40] [41] [42]

Ma and Dressendorfer, Ionizing Radiation effects in MOS Devices and Circuits, Wiley, 1989. Messenger and Ash, The effects of Radiation on Electronic Systems, Van Nostrand, 1992. Holmes - Siedle and Adams, Handbook of Radiation Effects, Oxford, 1993. Boudenot J.D., L'environnement spatial. Collection "Que sais-je ?", Presses Universitaires de France, 1995 (in French) [43] Messenger and Ash, Single Event Phenomena, Chapman & Hall, 1997

INSTABILITIES IN SILICON DEVICES Silicon Passivation and Related Instabilities G. Barbottin and A. Vapaille (Editors) © 1999 Elsevier Science B.V. All rights reserved.

553

CHAPTER 9

AN OVERVIEW OF RADIATION-MATTER INTERACTIONS

by W.R. FAHRNER (D

Key items Basic units Absorption cross section Scattering cross section Stopping power Range Displacement defects Ionization (phenomena) Electron-matter interactions Ion-matter interactions Photoelectric effect Compton effect Pair production Attenuation coefficient Neutron-matter interactions

(1) Fernuniversitat Gesamthochschule Fachbereich Elektrotechnik Bauelemente der Elektrotechnik D'58084 Hagen, Germany

554

WR, Fahrner

Abstract of Chapter 9: An overview of radiation-matter interactions Electronic components are increasingly used in terrestrial or space radiation environments. Inside these components, radiation gives rise to electrical phenomena which can only be understood and modeled if the basic physics of radiation-matter interactions is well understood. This physics is detailed in this chapter. We first indicate, in Section 2, the definitions and the basic units one uses to describe both the radiation sources and the irradiated material. In Section 3 we define the concept of interaction cross section, applied to the absorption or to the scattering of particles in matter, as well as the concepts of stopping power and range. Two types of "defects" are created by radiation: displacement damage and ionization phenomena. In Section 4 we describe how these defects are generated and how they recombine. We also describe two examples of radiation environments encountered by electronic devices during their manufacturing: ion implantation and lithography. Energetic electrons can interact elastically with the nuclei of the target atoms, or inelastically with their shell electrons. They can also generate Bremsstrahlung radiation when stopped by the target material. The first two mechanisms are described in Section 5. Energetic ions interact with matter in ways similar to electrons. We show in Section 6 that, by making suitable hypotheses about the shape of an "interaction potential", we can deduce expressions both for the interaction cross section of ions andfor their stopping power. Energetic ions can be encountered during device manufacturing and in space (cosmic rays). In Section 7 we describe the three basic mechanisms taking place when photons interact with matter: the photoelectric effect, the Compton effect, and pair production. Any of these three mechanisms can prevail depending on photon energy and on the atomic mass of the target material. We end this long chapter by describing (in Section 8) how neutrons interact with matter. Two mechanisms prevail: either the neutron collides with a nucleus or it is captured by the nucleus. In the first case the primary "knock-on atom" can generate a cascade of secondary collisions, while in the second case neutron capture is followed by the emission of particles which, in turn, can generate collisions. This leads us to define a "damage function" (useful for damage modeling). Resume du chapitre 9: Un apergu des interactions rayonnement-matiere Les composants electroniques sont de plus en plus utilises dans des environnements radiatifs terrestres ou spatiaux. Us sont dans ce cas le siege de phenomenes electriques qui ne peuvent etre compris et modelises que si les mecanismes physiques des interactions rayonnement-matiere sont bien connus. C'est le sujet traite dans ce chapitre. On commence par indiquer, dans la section 2, les definitions et les unites de base qui permettent de decrire aussi bien les sources de radiations que les cibles irradiees. Dans la section 3 on definit le concept de section efficace d'interaction (absorption ou diffusion) des particules dans la matiere, ainsi que les concepts de pouvoir d'arret et de profondeur de penetration. Deux categories de defauts sont generees par les radiations: les defauts de deplacement et les effets d'ionisation. On decrit dans la section 4 leur genese et lafagon dont ils se recombinent. On decrit egalement deux exemples d'environnement radiatif rencontres par les composants lors de leur fabrication : limplantation ionique et la lithographie. Les electrons energetiques peuvent interagir elastiquement avec les noyaux de la cible, ou inelastiquement avec le cortege electronique des atomes. Ils peuvent egalement generer un rayonnement de freinage (Bremsstrahlung) lors de leur deceleration dans la matiere. Les deux premiers mecanismes sont decrits dans la section 5. Les ions interagissent avec la matiere selon les memes mecanismes que les electrons. On montre dans la section 6 que moyennant certaines hypotheses sur la forme du "potentiel d'interaction", on peut en deduire des expressions pour la section efficace ^interaction et le pouvoir d'arret. On rappelle que Von rencontre des ions energetiques aussi bien lors de la fabrication des composants que lors de leur utilisation dans Tespace (rayonnement cosmique).

An Overview of Radiation-Matter Interactions

555

Dans la section 7 on decrit les trois mecanismes de base de I'interaction photon-matiere: Veffet photoelectrique, Veffet Compton et la production de paires. On montre que I'un ou I'autre de ces effets predomine selon Venergie du photon incident et le numero atomique de la cible. Ce long chapitre se termine par une description de Veffet des neutrons sur la matiere (section 8). Deux mecanismes predominent alors : la collision avec le noyau de Vatome cible, ou la capture par ce meme noyau. On montre que collision et capture sont suivies d'autres collisions secondaires qu'iI faut prendre en compte au travers d'une fonction "dommages" si Von veut mode User les effets. Zusammenfassung zu Kapitel 9: Eine Ubersicht der Wechsehvirkungen von Strahlung undMaterie Elektronische Bauelemente werden in zunehmendem Mafi in strahlungsreicher Umgebung aufder Erde oder im Weltraum benutzt. Diese Strahlung gibt Anlafi zu elektrischen Erscheinungen, die nur verstanden oder modellmdfiig beschrieben werden konnen, wenn die grundlegende Physik der Wechselwirkungen von Strahlung undMaterie gut verstanden ist Diese Physik wird in diesem Kapitel in Einzelheiten diskutiert. Zuerst fuhren wir in Abschnitt 2 die Definitionen und Grundeinheiten vor, die man sowohl fiir die Strahlungsquellen als auch die bestrahlten Materialien benutzt. In Abschnitt 3 definieren wir den Begriff der Wirkungsquerschnitte sowohl fiXr Absorption als auch Streuung von Teilchen inMaterie undweiter die Begriffe Bremsvermogen und Reichweite. ZweiArten von "Defekten" werden durch Strahlung erzeugt: Versetzungsschdden und lonisation. In Abschnitt 4 beschreiben wir, wie diese Defekte erzeugt werden und wie sie rekombinieren. Wir beschreiben auch zwei Beispiele strahlenreicher Umgebung, wie sie von elektronischen Bauteilen bei ihrer Herstellung angetroffen wird: lonenimplantation und Lithographie. Energiereiche Elektronen konnen mit dem Kern der Targetatome in elastische Wechselwirkung treten, bzw. in inelastische mit ihren Schalenelektronen. Sie konnen auch Bremsstrahlung erzeugen, wenn sie im Targetmaterial abgebremst werden. Die ersten beiden Mechanismen werden in Abschnitt 5 beschrieben. Energiereiche lonen treten in dhnliche Wechselwirkung wie Elektronen. Wir zeigen in Abschnitt 6, daJ3 wir aufder Grundlage geeigneter Annahmen fiber die Form eines "Wechselwirkungspotentials" Ausdriicke sowohl fUr ihre Wechselwirkungsquerschnitte als auch ihr Bremsvermogen ableiten konnen. Energiereiche lonen tauchen bei der Bauelementherstellung und im Weltraum auf (kosmische Strahlung). In Abschnitt 7 beschreiben wir die drei grundlegenden Mechanismen, die stattfinden, wenn Photonen mit Materie in Wechselwirkung treten: den photoelektrischen Effekt, den Compton-Effekt und die Paarerzeugung. Jeder dieser drei Mechanismen kann vorherrschenje nach Photonenergie und atomarer Masse des Targets. Wir beenden dieses lange Kapitel mit der Beschreibung (in Abschnitt 8) der Wechselwirkung von Neutronen mit Materie. Zwei Mechanismen herrschen vor: Entweder stofit das Neutron einen Kern oder es wird durch ihn eingefangen. Im ersten Fall sehen wir, daJ3 das primdr gestofiene Atom eine Kaskade von Sekunddrstofien erzeugen kann, wdhrend im zweiten Fall dem Neutroneneinfang eine Emission von Partikeln folgt, die ihrerseits Stofie erzeugen konnen. Diesfiihrt uns zur Definition einer "Schddigungsfunktion" (die niitzlich zur modellmdfiigen Beschreibung der Schddigung ist).

556

W,R. Fahrner

Chapter 9: An overview of radiation-matter interactions Table of contents List of symbols and abbreviations used 1. Introduction 2. Basic units and definitions 2.1. A first classification of the various interactions 2.2. The radiological units 2.2.1. Units characterizing a radiation source 2.2.2. Units characterizing the radiation target 2.3. Additional definitions and remarks 2.3.1 Relation between exposure and absorbed dose 2.3.2 The exposure rate of a point source of gamma rays 2.3.3 Biological effects versus energy deposition 2.4.Summary 3. Basic concepts related to interaction probability and energy exchange 3.1. Four types of interaction 3.2.The concept of interaction cross section 3.2.1. The absorption cross section 3.2.2. The differential scattering cross section 3.2.3. The total interaction cross section 3.3. Concepts related to the energy exchange 3.3.1. The energy transfer 3.3.2. The stopping power 3.3.3. Range and projected range 3.3.4. The nuclear and electronic contributions to the stopping power 4. An overview of radiation-induced defects and radiation environments 4.1. Displacement defects 4.2. Ionization phenomena 4.3. Some examples of radiation environments 4.3.1. The space environment 4.3.2. The (civilian) nuclear environment 4.3.3. The manufacturing environment 5. The electron-matter interaction 5.1. The sources of-electrons and the main interactions 5.2. Elastic interaction with the nucleus 5.3. Inelastic interaction with the shell electrons 5.3.1. Energy transferred to one shell electron 5.3.2. Energy transferred to all electrons 5.3.3. Energy loss per unit path length 5.3.4. Stopping power 5.3.5. Range, straggling (electrons)

An Overview of Radiation-Matter Interactions 5.4. Conclusion 6. The ion-matter interaction 6.1. Main origins and properties 6.2. The elastic interaction of ions with target nuclei 6.2.1. The approach used 6.2.2. The various interaction potentials and the associated cross sections 6.2.3. Calculation of the nuclear stopping power 6.3. The inelastic interaction of ions with shell electrons 6.4. Ranges, straggling (ions) 6.5. Conclusion 7. The photon-matter interaction 7.1. The origin and sources of photons 7.1.1. The physical origin of photons 7.1.2. Photon sources 7.2. The photoelectric effect 7.3. The Compton effect 7.3.1. Momentum and energy conservation 7.3.2. The momentum of the Compton electron 7.3.3. The shift in wavelength of the incident photon 7.3.4. The kinetic energy of the Compton electron 7.3.5. The relationship between the two scattering angles 7.3.6. Compton scattering in the relativistic case 7.3.7. Quantum and energy scattering 7.4. Pair production 7.5. The total linear attenuation coefficient. 8. The neutron-matter interaction 8.1. The general properties of the neutron 8.1.1. The neutron mass 8.1.2. The neutron charge 8.1.3. The neutron spin 8.1.4. The gyromagnetic ratio 8.2. An overview of neutron sources 8.2.1. Characteristic parameters of neutron sources 8.2.2. The various neutron sources 8.3. Neutron interaction with solids 8.3.1. The collision process 8.3.2. The capture process 8.4. CoUision process versus capture process 9. Conclusion Acknowledgements List of references

557

558

W.R. Fahmer

List of symbols and abbreviations used A A b c D D Dq Dq DN

E E E Ec Eion

Ed EG EN

Ekin EB

Etot

F h H I

J m mo niair Nj

P Pe q R R

Rp ARp

cm2 -

cm cm/s or m/s Gy or J/kg Gy/s or W/kg Sv or J/kg Sv/sorW/kg cm2 C/kg A/kg eV eV eV eV eV eV eV eV eV N Js J.s eV l/cm2s kg kg kg 1/cm^ kg-cm/s kg-cm/s C cm cm cm cm

Area Atomic mass Impact parameter Velocity of light (c=2.9979-10^ m/s in vacuum) Dose Dose rate Dose equivalent Dose rate equivalent Damage function (for neutrons) Exposure Exposure rate Energy Critical (threshold) energy Ionization energy Displacement energy Energy gap Neutron energy Kinetic energy Bremsstrahlung energy Total relativistic energy Force Planck constant (h = 6,626.10'^'^ J.s) Rationalized Planck constant (h = hlln) Average atomic ionization energy Flux Mass (of a particle or atom) Rest mass (of electrons) Mass (of air) Density of absorbing (or scattering) atoms Momentum (of a particle) Momentum of an electron Elementary charge (q=1.6.10-i^C) Total range Mean range Projected range Straggling

An Overview of Radiation-Matter Interactions

r

Yd

cm cm2.eV/kg cm2.eV/kg cm2-eV/kg eV eV s cm^ cm/s cm/s cm/s2 Vcm 1/cm^-s

Z

-

Zl Z2

-

S Sn Se

T, Tm t V V Ve.VN Ve

V(r) X

-

Ratio (p= v/c) Ratio(7 = (l-v2/c2)-i/2)

-

Deflection angles after a scattering event Absorption cross section (pair production) Wave length Free path length Total attenuation coefficient Number of atoms displaced by one neutron Density Cross section Absorption cross section Scattering cross section Differential scattering cross section Differential scattering cross section Interaction cross section (neutrons) Spheric angle Absorption cross section (photoelectric effect) Atomic mass unit, Arbitrary unit

*>>

7

K

cm2

X X \^

cm cm 1/cm

\)

-

P a

kg/cm3 cm2 cm2 cm2 cm2/J

^a ^sc 5as/dT da^/dQ a (En)

Distance Stopping power Nuclear stopping power Electronic stopping power Energy transferred. Average energy transferred Maximum energy transferred Time Volume Velocity (of a particle) Electron velocity, neutron velocity (resp.) Electron acceleration (deceleration) Potential Distance Rate of displaced atoms per unit volume Atomic number Charge state of the projectile Charge state of the target atom

cm^/ster cm2

n

-

xk amu, a.u.

cm2 -

559

560

W.R. Fahrner

FOREWORD This chapter is intended to provide the reader with the basic physics of how particles and quanta interact with matter. We have assumed that most electronics engineers have little experience in nuclear physics. We have restricted ourselves to those phenomena governing (solid state) device operation and failure. 1. INTRODUCTION This chapter is the second in a series of five devoted to radiations and to their impact on silicon devices. We saw in Chapter 8 that electronic components are increasingly used in radiation environments. We also described in detail the natural (radiation) environment surrounding our planet which poses a serious threat to increasingly sensitive large scale integrated circuits used in space. Radiations (photons and particles) can trigger two basic types of "defects" in silicon devices, namely displacement damage and ionization phenomena. These "defects" modify the electrical characteristics of the materials making up the device and thus can cause a parametric or a functional failure. This is well described in Chap. 10. Defects (natural or radiation-induced) exist also in silica or at the Si-Si02. interface They play an important role during and after irradiation in phenomena such as : charge build-up and interface states creation. The nature of defects encountered in silica and various charge buildup phenomena are examined in Chap. 11. When travelling through the silicon substrate of a device, highly energetic ions can ionize the material in such a way that the ensuing "photocurrent" is able to cause a logical "upset". This so-called "single event upset" (SEU) is now a well-identified threat to large scale integrated circuits. It will be described thoroughly in Chap. 12. However before we describe all these phenomena and in order to be able to quantify and model them, we must give the reader enough background material on radiation-matter interactions. This is what we attempt to do in the present chapter. To quantify the effects of radiation on matter, we need basic units and definitions. We present them in Section 2 of this chapter and we explain how these units and definitions fall into two categories depending on whether they characterize the radiation source or the irradiated target. Two concepts are vital to describe and model the effects of radiation on matter: the interaction cross section describes the probability that a particle interact with the material either through absorption or through scattering. The stopping power is used to quantify the amount of energy that a particle can exchange during its travel through the material. Given that the incoming particle can in most cases either interact with the electron shell of the target atom, or with its nucleus, or with both, two contributions to the stopping power can be distinguished. This is all described in Section 3, where we also show that the range of a particle, i.e. the distance that a particle travels inside a material, can be expressed as a function of stopping power.

An Overview of Radiation-Matter Interactions In Section 4 we give a brief overview of radiation-induced defects and of possible radiation environments. In solids, radiations can induce two broad categories of "defects": When the incoming particle collides with a lattice nucleus, it generates primary defects (interstitials and vacancies) which in tum combine to form secondary defects (vacancy clusters, A and E centers, etc...)- When the incoming particles (or quanta) interact with the electron shell, they can generate electron-hole pairs. In silicon ionization stops as soon as irradiation stops, and the generated carriers either recombine or are swept away by the electric field. The same occurs in silica, but in that case some carriers (predominantly holes) remain trapped which leads to the formation of a space charge and of interface states. The exposure of electronic components to radiation environments is becoming widespread. Apart from the military (nuclear) environments, devices may also be subjected to civilian (nuclear) environment and/or to space radiations. (Only the latter case will be dealt with extensively in this book.) During their manufacturing, devices are also subjected to radiations during such steps as: ion implantation and lithography. We give two examples of dose calculations in such cases in Section 4. Energetic electrons can interact with target atoms in several ways. They can collide elastically with the nucleus, or experience inelastic collisions with the shell electrons. Both cases are described in Section 5. (A third case, the generation of Bremsstrahlung, will be briefly dealt with in Section 7). In each case we can calculate the energy lost by the incoming electron and its stopping power. We show that the latter varies little with energy between 1 and 10 MeV and depends little on the target material. Wefinallyexplain why the concept of mean free path cannot be used for electrons because of large energy and range stragglings, and why we prefer instead to use the range concept. Energetic ions interact with matter in at least two ways. They either collide elastically with target nuclei or they collide inelastically with the shell electrons of the target atoms. We show in Section 6 that it is possible to derive an expression for the differential cross section and for the (nuclear) stopping power, in the case of elastic collisions, if we assume that the "interaction potential" takes a given form. For inelastic collisions the expressions of the stopping power are similar to those derived earlier for electrons. A third mechanism exists whereby energetic ions (especially protons above 10 MeV) can be captured by the target nuclei and trigger a nuclear reaction. All these effects are encountered when cosmic rays (made up of energetic ions) and especially energetic space protons strike components flown in space. Many results relative to ion-matter interactions had been already obtained in the past because ion implantation is so prevalent in the semiconductor industry, and experimental values for the projected range of ions in matter have been gafhered for a long period. Some examples are also given in Section 6. Electronic devices are also submitted to energetic electron fluxes during their fabrication and when they are used in space or in a "nuclear" environment. In Section 7 we first review the physical origin of energetic photons (UV, X-rays, 7-rays), and we describe their most commonly used sources. Photons interact with matter through at least three different mechanisms: the photoelectric effect, the Compton effect, and the pair production.

561

562

W.R. Fahrner

Each of these mechanisms can become predominant depending on the energy of the photon and on the nature of the material being irradiated. These three mechanisms are thoroughly described. Finally some data on photon attenuation coefficients in air, aluminium and lead are given. Neutrons are encountered naturally in space (in the upper atmosphere) or anywhere else as a byproduct of nuclear reactions. In Section 8 we first review the general properties of neutrons and we describe some of the most widely used neutron sources. Neutrons interact with matter in two ways: either through a collision process or through a capture process. In the first case, if enough energy is transmitted to the primary "knock on" atom, a cascade of displacement defects may follow. In the second case, neutron capture is followed by a nuclear reaction and an emission process. The emitted particles may also generate recoil atoms. In both cases, the modeling of neutron damage requires that a "damage function" be established. Large scale integrated circuits will be increasingly used in space and in terrestrial radiation environments. The effects of radiations on electronic devices will thus continue to be a dynamic field and some basic aspects of radiation-matter interactions may even have to be reexamined in the process. 2. BASIC UNITS AND DEFINITIONS When an electronic device is used in a radiation environment, the particles and quanta most likely to be encountered are : - neutrons - photons (UV, X-rays, gamma rays) - electrons -ions - protons (protons belong to ions, of course, but have gained such importance that they are mentioned separately). These various particles and photons interact with matter in many different ways and there exists several manners of classifying these interactions. 2.1. A FIRST CLASSIFICATION OF THE VARIOUS INTERACTIONS

The most widely used approach to classify interactions in the field of electronic materials is to look at the by-product of the interaction. - When a radiation removes an atom from its regular (lattice) position, a displacement damage has been created. - When a radiation creates an electron-hole pair, we say that ionization has taken place. This distinction between displacement damage and ionization phenomena is justified by the fact that these "interactions" have different consequences on the electronic properties of the materials, as described at length in Chap. 10. - Displacement damage leads to the creation of additional carrier traps and recombination centers in silicon; and to the creation of additional carrier traps in silica.

An Overview of Radiation-Matter Interactions

563

- Ionization leads to the creation of photocurrents in silicon whereas, in silica, it leads to carrier (mostly hole) trapping (carrier trapping in turn generates a charge build-up and interface states). Although, as we shall see later on, all particles generate (directly or indirectly) both displacement damage and ionization phenomena, one of these two effects usually predominates for a given material and a given energy range. It is therefore a useful and widely used approach to discuss these two effects separately. To be able to quantify these various interactions we first need to define a set of units. 2.2 THE RADIOLOGICAL UNITS

Two types of radiological units are used: those characterizing the radiation source, and those characterizing the (irradiated) target. 2.2.1 Units characterizing a radiation source: The activity. The activity. A, of a radionuclide or of an isomer containing N atoms at time t, is equal to the average value of the disintegration rate. According to the law of radioactive decay, A is equal to the product of the decay constant, X, and of N : A =

= X'N

(9.1)

The Sl-unit of activity is the Becquerel [Bq] : 1 Bq = 1/s. Most physicists still use the "Curie"-unit [Ci], 1 Ci = 3.7 IQio Bq . The activity of 1 g of 226Ra is 1 Ci. The fluence. The fluence, F, indicates the number of particles or quanta emitted by a source, an accelerator etc. per unit area.The fluence is usually expressed in [cm-^]. Another expression for fluence is "integrated flux". The flux. Theflux,(j), indicates the number of particles or quanta emitted by a source, an accelerator etc. per unit area and unit time.The flux is usually expressed in [cm"^ s-^]. Both fluence and flux are also used to describe the number of particles per cm^ (resp. per cm^/s) impinging on a target. 2.2.2 Units characterizing the radiation target: The exposure. The exposure, E, generated by an ionizing irradiation^ is given by ratio dQ/dm^ where dQ is the electric charge of the ions produced in an elementary volume of air (dVa) whose mass is dm^ (dm^ = pa dV^): E = dQ/dm^=(l/ pJdQ/dV^

(9.2)

Only positive or negative charges are added up to yield dQ ; the air is held at standard conditions. The exposure is usually expressed in [C kg-i] . However, most physicists still use the "Roentgen"-unit [R], 1 R = 2.58 10-4 C/kg. Unfortunately the same letter is used to designate both exposure and energy.

564

W.i?. Fahrner 9

The exposure rate. The exposure rate, E, is the time derivative of the exposure: E = dE/dt

(9.3)

In the SI system, the exposure rate is expressed in [A kg"i] . Most physicists still use the "R/h"-unit, lR/h = 7.17 10-8 A/kg. The absorbed dose. The absorbed dose, D, is the ratio of the amount of energy, dE, transferred to an absorbing material of volume dV, and of mass dm (dm = p dV): D = dE/dm

= (l/

p)'dE/dV

(9.4)

The Sl-unit of dose is the Gray [Gy]. 1 Gy = 1 J/kg . Most physicists still use the "rad"-unit [rad], 1 rad = lO-^ J/kg . Since the dose is absorbed by a specific material under test, say Si, Si02, etc., the unit is often written more precisely in the form of Gy(Si), Gy(Si02), etc. The dose rate. The dose rate, D , is the time derivative of the absorbed dose, D^dD/dt

(9.5)

The dose rate is usually expressed in [Gy S"^]. 1 Gy/s = 1 W/kg . Most physicists still use the "rad/h"-unit, 1 rad/h = 2.78 10-6 w/kg . The dose equivalent. The dose equivalent, Dq, is equal to the absorbed dose, D, multiplied by an appropriate modifying factor, q described next: Dq^Dq

(9.6)

The Sl-unit of Dq is the Sievert [Sv]. 1 Sv = 1 J/kg . Most physicists still use the "rem"-unit, 1 rem = 10"^ J/kg (rem = roentgen equivalent man). In the older standards, q is the inverse ratio of the dose required (from a given source) to provoke a given biological effect, to the dose required from a 200 keV X-ray source to provoke the same effect. In this case, q is termed the relative biological effectiveness (RBE). Factor q depends on the given radiation species and energy in a somewhat arbitrary way due to the arbitrary choice of biological effect. But in the majority of cases this is a handy and practical definition. For specific applications however, q is considered equal to the "quality factor" QF. The QF factor is related, on an empirical basis, to the Linear Energy Transfer (i.e the energy lost by a particle per unit path length) measured using water as an absorber. In Table 9.1, we present the quality factor, QF, as a function of the linear energy transfer.

565

An Overview of Radiation-Matter Interactions

QF

LET [keV/nm] <3.5 7 23 53 <175

1

1 2 5 10 20

Table 9.1: Quality factor vs. linear energy transfer (after [I])

In Table 9.2, quality factors are listed for various types of radiations: Type of radiation

QF

X-rays and 7-rays p-rays, E„ax > 0.03 MeV p-rays, En,ax < 0.03 MeV Natiarally occurring a-particles Heavy recoil nuclei Neutrons: Thermal to 1 keV 10 keV 100 keV 500 keV IMeV 2.5 MeV 5 MeV 7 MeV 10 MeV 14 MeV 20 MeV 1 Energy not specified

1 1 1.7 10 20 2 2.5 7.5 11 11 9 8 7 6.5 7.5 8 10

Table 9.2: Quality factors for various types of radiations (after [2])

The dose rate equivalent. The dose rate equivalent, Dq, is the time derivative of the dose equivalent, Dq. Da = dD^ / dt

(9.7)

In the SI system, Dq is expressed in [Sv s-i]. 1 Sv/s = 1 W/kg . Most physicists still use the "rem/h"-unit, 1 rem/h = 2.78 10-6 W/kg .

566

W,R, Fahrner

2.3 ADDITIONAL DEFINITIONS AND REMARKS

Some additional remarks and examples might be useful for a better understanding of the above definitions. 2.3.1 Relation between exposure and absorbed dose The convenience of the historical units is based on the fact that 7 /? <=» 0.87 rad

(for X- and ganmia rays in air), or

1R
(9.8)

Energy E is identified with EQ, the radiation energy (e.g. of a ganrnia ray flux) penetrating in the bulk of the substance of volume A dx (A is the area in this case) and of absorption coefficient |LI(X). For small values of dx we can consider that |LI(X) = const, so that dE/(p'A'dx) = '- EoH/(p'A)

(9.9)

The left term stands for the absorbed dose. For two different materials (e.g. human tissue, subscript t, and air, subscript a) we find D, =DJiii,/p,)/(iii,/pJ

(9.10)

The ratio (|LI/ pt)/(|ia/ Pa) has been measured to be 1.1. It follows that D^ = 0.956 10-^ J/kg for an exposure of 1 R .Thus an exposure of 1 R leads to an absorbed dose in a human tissue of 2:1 rad 2.3,2 The exposure rate of a point source of gamma rays We can try to link the amount of ionization generated in air per unit time and unit volume, to the activity of the nearby source. This exposure rate can be expressed as: E = rA/ r^

(9.11)

where r is the distance separating the air probe mass from the source, A is the source activity, and T is the specific gamma ray constant. T is expressed in [Cm^/kg] although most physicists still use: dim F = R m2/(h Ci) . For some common radionuclides we find the following F values.

An Overview of Radiation-Matter Interactions

Nuclide

137cs

r[Rin2/hCi] 0.31

567

60Co

192ir

24Na

226Ra

170Tm

1.30

0.50

1.77

0.80

0.002

Table 9.3: Specific gamma ray constants for various radionuclides.

From the above table we see that a crade approximation for T expressed in [Rm^/h- Ci] is r = 1 . It follows that, as a rule of thumb, the activity A of a source expressed in [Ci] produces an exposure rate expressed in [R/h] of the same value for a distance of 1 m, •

E

<^h{\m). 2.3.3 Biological effects versus energy deposition

Knowing that the dose lethal to man, is D^ « 500 rad = 5 Gy and assuming that a man weighs 70 kg and consists mainly of water, let us calculate the corresponding energy deposited. His body temperature rises after irradiation, AT, is given by Q = m c AT = m D j . Using c = Cwater = 1 kcal/(°K.kg) = 4.185 10^ J/(°K.kg), we find

AT = Dj/c^^,^^ =

[5/4J85'10^]K

- 10'^ ""K

The energy absorbed by this man is E = 70 kg-5 J/kg = 350 J . The combustion energy of wood is about 15,000 J/g . Thus a piece of wood with a mass

m^^^^=350J/15fi00(J/g)^0mg delivers the same amount of energy as the lethal radiation dose. This shows that the danger associated with radiations, for a human being, has nothing to do with the absorbed energy as such. 2.4 SUMMARY

We sunamarize below the important radiological parameters and units and how to convert them from the SI system to other often used systems.

W.R. Fahrner

568

Unit (in other system)

Unit (SI system)

Parameter Symbol

Name

Symbol

Dimension

Name

Symbol

Conversion Factor

Activity

A

Bequerel

Bq

s-l

Curie

Ci

lCi=3.7 lOl^Bq

Fluence

F

-

-

cm_2 ^

-

-

-

Flux

O

-

cm-7^-s-1^

-

-

-

Exposure

E

-

-

c.kg-1

Roentgen

R

1R=2.58 10-4c/kg

Exposure rate

• E

-

-

A.kg-1

Roentgen/ hour

R/h

lR/h=7.17 10-18 A/kg

Absorbed dose

D

Gray

Gy

J.kg-1

rad

rad

1 rad=10-2 J/kg

Dose rate

• D

Gray/s

Gy/s

W.kg-1

rad/hour

rad/h

lrad/h=2.78 10-6w/kg

Dose equivalent

Dq

Sievert

Sv

J.kg-1

rem

rem

1 rem=10-2 J/kg

Dose rate equivalent

Dq

Sievert/s

Sv/s

W.kg-1

rem/hour

rem/h

Name

1


o C/5

s

i rem/h=2.78 10-6 w/kg

Table 9.4: The important radiological parameters and units

3. BASIC CONCEPTS RELATED TO INTERACTION PROBABILITY AND ENERGY EXCHANGE We have defined in Section 2 the units which let us quantify the effects of radiations on matter. Let us now introduce and describe two additional concepts which will enable us to describe and model the matter-radiation interactions, namely: the interaction cross section and the stopping power. 3.1 FOUR TYPES OF INTERACTION

Particles or quanta can interact with the shell electrons or with the nucleus of a target atom, and this in an elastic or an inelastic manner. The possible interactions then fall into four categories

An Overview of Radiation-Matter Interactions i.

elastic scattering on shell electrons (e.g. Compton effect, Thomson scattering)

ii.

inelastic scattering on shell electrons (e.g. excitation, ionization)

iii.

elastic scattering on nuclei (e.g. Rutherford scattering, proton-proton scattering)

iv.

inelastic scattering on nuclei (e.g. nuclear resonance scattering)

569

The terms "elastic" or "inelastic" are defined according to the balance of kinetic energy. If the sum of the kinetic energies of the two scattering partners is the same before and after the scattering event, the process is termed "elastic", otherwise it is termed "inelastic". 3,2 THE CONCEPT OF INTERACTION CROSS SECTION

Originally introduced for the kinetic gas theory, the concept of cross section has found widespread applications wherever interactions at an atomic scale occur, as e. g. in nuclear physics, electrochemistry, and semiconductor electronics. When a beam of particles or photons strikes a target, the incoming radiation may be either absorbed by the target material, or scattered, or both. It is thus useful to define a cross section for either one of these interactions. 3.2.1 The absorption cross section The basic idea behind this concept is illustrated in Fig. 9.1. A flux j ^ of particles or quanta (dim JQ = cm-^s-i) penetrates the absorber. After going through the layer of thickness dx , only j(x) particles leave the absorber. The difference: dj = Jo-j(x) , is proportional to the incoming flux (the more incoming particles, the more absorption processes take place), and to the number of absorbing atoms per unit area Nj dx (the more target atoms, the higher the interaction probability). Flux difference dj can thus be written: dj = -a^'NT'j'dx

(9.12)

where the minus sign indicates a loss in flux intensity. The proportionality constant, a^ , has the dimension of an area, [cm^] and is called the absorption cross section. A conmion unit of cross section is the bam. 1 bam=10"^'^ cm^. In terms of statistics, dj/j^ is the probability that an absorption event take place. According to Eq. (9.12), this ratio can be rewritten as an area ratio, namely a^ x (number of absorbing atoms)/(total area). Thus, c^ x (number of absorbing atoms) must be the area of all atoms together (facing the beam) and a^ must be the (effective) area of a single atom, as shown in Fig. 9.1.

W,R, Fahrner

570

absorber j(x) Jo

particles, quanta

particles, quanta

dx

-H - •

X

0

Fig. 9.1: Attenuation of afluxof particles or quanta by an absorber

Let us note however that the geometrical and the effective cross sections can differ greatly. A simple example of such a discrepancy is the large Coulomb attraction of two particles as represented in Fig. 9.2. There the absorption cross section is vastly superior to the atomic dimensions of the Coulomb center. To derive Eq. (9.12) we tacitly assumed that the density of absorbing centers is small. This means that there is virtually no overlap of the target atoms after projection on a plane perpendicular to the incoming flux. Values of absorption cross section can be computed from macroscopic measurement data. When integrating Eq. (9.12), one obtains j(x)=Joe

-GaNjX

(9.13)

where factor GaNj can be identified with the absorption coefficient |ii from Lambert's law. It follows that ^a

^^i/Nj

(9.14)

An Overview of Radiation-Matter Interactions

571

Fig. 9.2: Trajectories of a particle in an attracting potential.

3.2.2 The differential scattering cross section Let us note that the absorption cross section is the result of a simple transmit/absorb decision. A one-dimensional description is thus sufficient. This is not true anymore, when scattering is considered. The experimental situation and the theoretical description become then more complicated as described next. In contrast to the absorption experiment (where the absence of the particles is recorded) the presence of particles is now a measure of the scattering cross section. The elementary flux dj of particles, whose trajectories, after scattering, are found between angle 'd and angle 'd + diJ (i.e. between the cones whose half sunmiit angles are '& and 'b + &b, i.e. inside solid angle dQ=27i: sin 'b && (see Fig. 9.3) is given by (9.15)

dj^^'dQ'NTJ(x)dx Ratio das(t2)/dQ is called the differential (scattering) cross section and

dG,(Q) dQ

dQ

is

defined as the probability to find a scattered particle between the cones of half angles ^ and iJ+di^.

Similarly (da3(T) / dT) dT is defined as the probability to find a recoil atom with an energy comprised between T and T+dT ( T stands for the energy transfer, as explained next in §3.3.1). Integrating J (das('d) / dQ) dQ or j (das(T)/dT)dT yields the total scattering cross section.

572

W,R. Fahrner

Ei-T

Fig. 9.3: Scattering of a positively charged particle by a positively charged center (The figure is still valid if both charge and center are negatively charged.)

The particles found inside the solid angle dQ = 271 sin ^ di>, have travelled - prior to scattering - through an annular surface of area 2K b db as indicated in Fig. 9.3. It is thus convenient to define dc^^ = (das(d)/dfll) dQ such that dc^^ is the portion of c^^ crossed by those ions recovered in dQ , i.e. da^^ =27tbdb

(9.16)

Thus da.

•dn = 2Kbdb

(9.17)

^dT = 2Kbdb dT

(9.18)

and similarly d(j

This last definition is often helpful, because expression b(T) potentials of the form V = V(r).

can be derived for many

An Overview of Radiation-Matter Interactions

573

3.2.3 The total interaction cross section When the differential scattering cross section, da/dQ, is integrated over the total solid angle (i.e. 47c), the total cross section, a^^, and thus the total number of scattered particles are obtained. The total number of particles removed from the incoming beam is given by the sum of the absorption and scattering cross sections. It follows that the total interaction cross section is given by: ^ =^a+^.c

(9.19) ->

In the textbooks, one starts with a given potential V (r) (usually simplified to V(r)) of the scattering atom and calculates the differential cross section dcJdQ . In practice, the cross section is measured (by measuring dj(Q), N^, j , dQ, dx) and the potential V(r) is deduced. The knowledge of V(r) is mandatory to confirm the structure models of the target atoms. 3.3 THE CONCEPTS RELATED TO THE ENERGY EXCHANGE

When an incident particle of kinetic energy Ei is scattered by a lattice atom, it transfers part of its energy to that atom. If we call T the transferred energy, the incoming particle possesses energy Ei - T after elastic scattering as illustrated in Fig. 9.3. If the transferred energy (also called recoil energy) exceeds the displacement energy (E^) of the lattice atom, the latter becomes a displaced (recoil) atom. 3.3.1 The energy transfer Since there exists a one-to-one relationship between scattering angle 'd and transmitted energy T, counting the (scattered) primary particles dj, comprised between angles "& and 'd+d'd, is equivalent to counting the secondary particles which have recoil energies between T and dT. We can thus write:

di»

d^

dT

dT

Expression i^(T) is given by the kinetics of the two-body collision, especially by the interatomic potentials. 'd(T) means that: if the primary particle is found at an angle 'd after the collision, it has transferred energy T to the scattering atom (i.e. to the nucleus and/or to its shell electrons). When the differential cross section das(T)/dT is known, the total cross section can be obtained by integration: Gsc = l(d(Js(T)/dT)'dT

(9.21)

T

We can define an average energy transfer by summing up all energy transfers (or rather all the products of particles times the energy they transfer) and dividing by the total number of scattered particles. It yields:

574

W.R. Fahmer

da

^^^ = ^7-^7df-

= ^ l^- ^-^^

(9.22)

dT 3.3.2 The stopping power A particle of energy Ej which undergoes v collisions loses overall an energy AEj given by AEj ^ - v. While undergoing these v collisions, the particle travels a distance AR given by AR = vX.. Length X is the free path length of the particle, i.e the distance it travels between two collisions. X may easily be linked to the scattering cross section. If we consider that the particle has a straight trajectory and that the probability of experiencing one collision (or one absorption) at the end of its free path is equal to one, we can write: 7 = A GNT

(9.23)

N j being the density of scattering (or absorbing) centers per unit area and product %G representing the volume of the cylinder in which the particle has travelled. This free path length X can thus be expressed as A= - ^

(9.24)

Using Eq. (9.14) and by analogy with an optical beam, we see that X plays a role identical to an "absorption length". We define the energy loss per path length as:

AEj (T) r da(T) L = ^-L = Nr \T'—'—— AR X ^^ dT

dT

(9.25)

This expression is meaningful only for lAEjl « E| . To get an expression independent of the target material, ratio AE/AR is normalized to the (mass) density of the material which yields the stopping power defined as S(Ej) = -(l / p)dEj / dR

(9.26)

3.3.3 Range and projected range Let us now call R{ the distance between two collisions. The particle will travel in the target material a distance R before stopping. This distance called the total range, and illustrated in Fig. 9.4, can be expressed as

An Overview of Radiation-Matter Interactions

575 (9.27a)

The total range R can also be calculated using the stopping power. It yields:

'

(9.27b)

pis(E)

ff the deflection angles T^ are small - which is true for energetic heavy ions - R is coUinear to the direction of the incident ions, and we can write R = Rp. Distance Rp is called the projected range (see Fig. 9.4 lower part), ff the deflections are important, then R » R p (see Fig. 9.4 upper part).

o o o o

o o of:o o o o o o o jo o o o O

Rr O yfO O

O

R ^^R^ » R

O

o 'o^ o ' o o o o o o o o o o o o o o

direction of the incident beam

RiOR^RaOR^O^ O

o o o oT — R„ — o o o o o o o o

R =X^Ri ^ R,

surface

Fig. 9.4: Particle scattering in a solid. Large angle scattering (top) and low angle scattering (bottom) are illustrated. Range R and projected range Rp are indicated.

W,R. Fahrner

576

Projected range and stopping power are accessible experimentally. Examples of projected range measurement techniques are: C-V profiling, radioactive implant tracing by sectioning, n-7 and p-a profiling, spreading resistance on a bevel, etc. The stopping power is determined via the energy loss, -dE, of particles going through a thin foil of thickness dx. 3.3 4 The nuclear and electronic contributions to the stopping power A charged particle may be scattered not only by a nucleus (nuclear contribution) but also by the electrons of the electronic shell (electronic contribution). The stopping power S , as defined by Eq. (9.26) is then the sum of two terms: S^ and S^ . As can be seen in Fig. 9.5, these two contributions vary with energy in quite different ways. S^ is large for low energies i.e. when the particle has lost most of its energy at the end of its travel in the target. S^ is large for large energies, i.e. when the highly energetic particle begins its travel. j (dE/dx) [MeV cm^/g] 3000 h

Ar 2000 h

r/

M "'

Fig. 9.5: Electronic (S^) and nuclear (S^) stopping powers for Ar and N {after[3]).

lOOOh N

0.01

01

Xv^ 1 1 ' 1 10 100 E[MeV]

The nuclear stopping power can be described by the classical Rutherford scattering of a projectile (mass m^ , charge qZj and energy E^ ) on a nucleus of the target (mass m2, charge qZ2 , at rest). The electronic stopping power is not as easy to describe although the Coulomb interaction used to derive it, has been improved by many authors: (i) One has to take into account that the collision involves an electron which is not free but bound to an atom. (ii) As a rule, electronic stopping is caused by many electrons at the same time (collective event).

An Overview of Radiation-Matter Interactions

577

(iii) Interactions of the electrons of the incident particle (in case the incoming ion is not fully stripped of its electrons) with the target electrons and atoms have to be included. (iv) At high energies relativistic effects modify the electric interactions; Bremsstrahlung and Cerenkov radiation are generated, and polarization occurs. In Sections 5 and 6 we will present an individual discussion of the stopping powers for some incident charged particles (electrons, heavy ions). 4. AN OVERVIEW OF RADIATION-INDUCED DEFECTS AND RADIATION ENVIRONMENTS In the two preceding sections, the interaction of an energetic particle with a single atom was considered. In the following, we extend this discussion to the interaction of a particle with a solid. As examples of solids, we take silicon (Si) and silicon dioxide (Si02). As already mentioned in Sect. 2 the interaction of a particle with a solid can result in two basic types of primary defects, namely: • a displacement of (lattice) atoms, and • ionization phenomena. interstitial

vacancy

Schottky-defect

oXoooloooioo rV-. o r"""::Q] o i ^ i o o o o o ' ro I

I

I

O O O O O i

ooT o o o

I

l O O O

"loollooo T

1

IQl

t

surface divacancy

Frenkel-defect

Fig. 9,6: Representation of some basic intrinsic defect structures, 4.1 DISPLACEMENT DEFECTS

An atomic displacement can be visualized as the result of a hard sphere collision: An impinging particle hits a lattice atom, in a manner similar to that shown in Fig. 9.3. If an energy greater than the displacement energy is transferred to the struck atom, the latter will be removed from its lattice position and a vacancy will be left behind as illustrated in Fig. 9.6. Some examples of displacement energy can be found in Chap. 10.

578

W,R. Fahrner

This primary event gives rise to secondary defects. First of all, the displaced atom must come to rest someplace. As a rule it does so in an interstitial position. • The combination vacancy-interstitial (sometimes separated by many lattice constants) is called a Frenkel defect. • If the rest position of the displaced atom is at the surface, the combination is called a Schottky defect. Defects have a tendency to agglomerate, since both vacancies and interstitials are mobile at room temperature. The simplest example of a complex "intrinsic" defect is the divacancy or the di-insterstitial. In semiconductor materials, the above list of secondary defects must be completed by including extrinsic constituents (doping atoms, impurities) and by the extended (cluster) defects. The doping atoms represent the most commonly encountered extrinsic point defects. They are known to occupy substitutional or interstitial positions, or both. The E-center (complex formed by a vacancy and column V element) and the A-center (vacancy-oxygen complex) combine both an extrinsic and an intrinsic defect. Their configuration is shown in Fig. 9.7:

Fig. 9.7: Representation ofE- and A-centers in doped silicon (after [4]).

During the thermal treatment of a vacancy-rich crystal, a single vacancy can "walk" (in fact, a neighboring lattice atom will jump into the location of the old vacancy and leave a new vacancy behind). Vacancies have a tendency to agglomerate until a microscopic void is formed. Other intrinsic extended defects are the edge dislocation and the screw dislocation. Their structure is illustrated in Fig. 9.8.

An Overview of Radiation-Matter Interactions

579

O-Q O-O I I O-O I I O-O I I o O

o O-O

I /

o+o-o

I/?

I O-bO-O O-O

O ' I/T I/?

O- O I \

O -O I /O / I / O

o - o - o- o Fig. 9.8: Representation of an edge dislocation (right) and of a screw dislocation (left).

Extrinsic cluster defects include also bubbles (e.g. if a void is filled with gas atoms), precipitates, agglomerations, striations, etc. The production probability and rate, the stability, and the interactions of all these defects depend on a lot of parameters. Among these let us mention: • the nature of the radiation source

• the post-irradiation temperature

• the radiation energy

• the annealing atmosphere

• the dose

• the annealing time

• the dose rate

• the target doping species

• the irradiation temperature

• the target doping density

A full treatment of the fate of a defect during and after irradiation is beyond the scope of this chapter. The interested reader is referred to some comprehensive books on this ample subject [ 5 - 9 ] . We will, however, examine how the presence of "secondary" defects due to displacement damage affects the electrical behavior of Si devices in Chap. 10. The physical and electrical nature of similar defects, but in Si02, will be described in Chap. 11. 4.2 IONIZATION PHENOMENA

An alternative way of depositing energy during irradiation is ionization. The incident particle or quantum transfers enough energy to a bound electron, to free it within the solid. Together with the remaining hole, an electron-hole pair is formed. The energy required to create such a pair is called the ionization energy, Ej^j^. Experimentally a relation between Ej^n and the energy gap of the material, EQ , is found, namely

2Ea<E,,,<3Ea

(9.28)

580

W.R. Fahrner

This relation has been explained by Shockley [10]: E^QJ^ is the sum of several energies:

^ion -

^ G + \^kin

/hole "^ \^kin

/el '^ ^ ' \^phon

/

(9.29)

In this expression <Ej^n>hoie ^^^ <Ekin>ei ^ ^ the average kinetic energies transferred respectively to the hole and electron. Each of these two kinetic energies is somewhere between zero and EQ-E (e « EQ ; for £ = 0 , a second electron-hole pair would be created). On average each carrier receives an energy EQ/2 , so that the sum of the two energies is <Ekin> ~ EQ . For the sake of momentum conservation, the lattice must be involved in the form of phonon generation. The product of n phonons generated (about 20) by the average phonon energy yields a third contribution of the order of EQ . Some experimental Ejo^-values are given below: Material

Si

Si02

GaAs

Ge

Eio„[ev]

3.6

18

4.8

2.8

If one assumes that the irradiation energy is consumed solely by ionization, by multiples of Eion ' w^ ^^^ calculate G^ the number of electron hole pairs created per cm^ and per gray. It yields: Gn =

1[Joule]

p[kgcm ^]

[kg]\Gy\

Ei^^[Joule]

For Si with p = 2.33 g/cm^ , we find G^ = 410i5/(cm3Gy(Si)) , and for p = 2.26 g/cm^ we get: G^ = 8- 10i4/(cm3.Gy(SiO2)).

(9.30)

Si02 : with

The above assumptions are valid to a large extend for UV, X-rays, gamma and a-particles. For higher energies and heavy ions, we refer the reader to Sections 6, 7, and 8. During the steady-state irradiation of an unbiased semiconductor material, the generation rate, U = G^- D , is balanced by the recombination rate (R = Ap/T) and by the trapping rate of the carriers. In an (n-type) semiconductor containing few traps, G^ D = Ap/x . It follows that the excess carrier density for steady-state irradiation conditions is given by Ap = GgT D

An Overview of Radiation-Matter Interactions

581

In this respect, irradiated silicon behaves as if it were optically excited; namely it displays photo-currents and solar cell characteristics. After switching off the irradiation source, the induced excess carrier density disappears exponentially with time. In silicon dioxide, however, the radiation-generated carriers (mostly the slowly moving holes) may get trapped in pre-existing, or in new radiation-induced centers created in the bulk of Si02 or at a Si02/Si-interface. This leads to the formation of a positive space charge (or oxide-trapped charge) and of interface states (Fig. 9.9). A detailed description of the dynamics of space charge formation is given in Chap. 11 whereas the process of interface states formation is described in Chap. 10.

hV

(krK

Si

Fig, 9.9: Representation of the generation of an electron-hole pair by a photon of energy hv > EQ(Si02), the trapping of a hole in Si02 , and the formation of an interface state.

w

Eo (SiO, ^

A special case of ionization process is the so-called single event upset. There, an energetic particle (e.g. a 5 MeV a) creates an ionized tubelike region around its track in the silicon. The dynamics of charge rearrangement and the impact of such a phenomenon on device performances will be discussed in Chap. 12. 4.3 SOME EXAMPLES OF RADIATION ENVIRONMENTS

If we omit the military environment, electronic devices can be exposed to high-energy radiations in the following cases: i.

when used in instrumentation for space and missions in the solar system

ii.

when used in instrumentation for nuclear power plants

iii. during the manufacturing process (of these very devices)

582

W,R. Fahmer

Besides, there exists also a few cases in medical equipments, and in electron and ion accelerators. Let us take a closer look at some of these environments. 4.3.1 The space environment Case (i) is the driving force for testing electronic devices prior to their use in a mission. The encountered radiation species and spectra and the required tolerance levels for a long term mission are discussed in Chaps. 8 and 10. 4.3.2 The (civilian) nuclear environment Case (ii) is less important, but is known for a spectacular event: In the days of Chemobyl, a robot was flown in to clean highly contaminated rooms. Unfortunately the developer of the robot had forgotten both to use radiation-hard devices and to shield them. The robot was inoperative after a short while. A similar experience is known to users of electron or ion accelerators: devices which must operate while standing near the target (preamplifiers, remote controls, etc.) do not usually have long operational lifetimes. 4.3.3 The manufacturing environment During device manufacturing, some process steps submit the device being manufactured to a radiation environment. These steps are: ion implantation, lithography, plasma deposition, plasma and reactive ion etching (RBE), and electron gun evaporation. I - Example of dose generated by ion implantation. Ion implantation effects depend on ion *'doses" and energies. Typical ion doses (fluences) range from lO^^ to 10^^ cm-^ ; energies used are between 30 and 300 keV, and in some cases up to lOMeV. As an example let us take Uj = 10^"^ phosphorus tons / cm^ implanted in silicon ( p = 2.33 g/cm^ ) with an energy of 100 keV. The projected range is found to be Rp = 0.1238 |im [11]. It is assumed that all the energy of the ion is deposited within Rp . The dose deposited is thus: D=^ni'E/(Rp'p) (9.31) = 5.54 10^ Gy 1238 • 10'^ • 2.33 • 10'^ This value should be compared to the typical irradiation dose in space during a mission, i.e. 10^ - 10^ Gy (see Chap. 8). However most of the damage effects occuring during implantation, are removed in a subsequent high-temperature annealing step.

An Overview of Radiation-Matter Interactions

583

ii - Example of dose generated by lithography. Irradiation sources in lithography steps are UV lamps, electron and ion accelerators, and synchrotrons. UV lithography does not harm an electronic device. For electron lithography, the typical resist sensitivity, S , is in the range of 10"^^ to lO-"^ C/cm^ [12] and the accelerator energy E^ =30 keV . An electron of this energy has a penetration depth of less than 6 |Lim in the thin resist layer and in the underlying silicon dioxide. Let us assume that S = 10"^ C/cm^. The electronic fluence necessary to sensitize the resist is at least: ^^=S/q

= 10~'^ /L6• 10"^^ -10^^ electrons/en?

(9.32)

Let us assume that the electron flux deposits most of the dose in the silicon dioxide below the resist layer. This dose is given by:

D = n,E^/R^'Psio = —^—;^—^ T-^ e a p HS1O2 16 10-1^ 6'10-4 '22

7 ^ 2 ' 10"^ Gy(SiO.) 10-^ ^

(9.33)

The result of (9.32) is within the range of typical electron fluences applied, namely 10^^ to lO^Vcm^ . The crude approximation of (9.33) is confirmed by more detailed calculations performed by Galloway et al. [13], who find a dose of 4-10^ Gy for the same conditions. A similar value ( 0 = 1 0 ^ Gy) is also reported in [14]. Ref. [13] gives data on the energy deposition for X-ray resists, namely 1 to 10^ J/cm^ . Assuming a sandwich structure of: 0.5 |im of resist, 0.7 |Lim of aluminium, and 50 nm of oxide, this reference shows that the dose absorbed in the Si02 layer is found to be between 103 and 106 Gy. Hi 'Example of dose generated by e-gun evaporation. Metallization is commonly carried out by electron gun evaporation. An electron beam is accelerated onto a cooled crucible filled with a metal of the desired species. Only the thin top metal layer can melt and emit atoms which will redeposit onto the wafer. The electron-metal interaction leads to the emission of Bremsstrahlung (see Sections 5 and 7). The spectral and directional distribution of this emission determines the dose absorbed by the wafers. This calculation has been carried out in [15] and the result for a typical evaporation time is D = 104 Gy. Let us note that in the above examples of irradiation during device manufacturing, the amount of energy transferred into Si, by a given particle at a given energy, may differ from that transferred into Si02, due to the difference in stopping power and penetration depth. However in a first order approximation, we can write that a dose of 1 Gy(Si) « 1 Gy(Si02).

584

W.R. Fahrner

5. THE ELECTRON-MATTER INTERACTION Now that the basic concepts and units have been defined, we can proceed to study how electrons (the most frequently encountered particles) interact with matter. 5.1 THE SOURCES OF ELECTRONS AND THE MAIN INTERACTIONS An electronic device may be subjected to electron irradiation in many cases: - For example during its manufacturing, a device is exposed to various electron fluxes (e.g. during electron beam lithography and during plasma-assisted process steps). - This is also the case when a device is used inside an equipment submitted to a radiation environment (e.g. in a spacecraft where typical electron fluxes encountered may be as high as 10^^/cm^ per day for Ee > 2 MeV [16]). The sensitivity of electronic components to electron damage is usually tested by exposing them to an accelerator beam. Typical beam energies are 30 keV (electron microscope), 1 MeV (industrial accelerators), and 1 GeV (national research institutions). Essentially three types of interactions^ between a charged particle (electrons, alphas, ions) and matter can occur, namely: i. elastic collisions with the nuclei ii. inelastic collisions with the shell electrons iii. inelastic collisions with the nuclei The fourth possible interaction process, i.e. elastic collisions with the shell electrons, can be neglected for energies above ~ 100 eV. We will deal in the following paragraphs with processes (i) and (ii); the discussion of process (iii) (Bremsstrahlung) will be postponed to Section 7 (photon-matter interaction). It should be kept in mind that for electrons, relativistic effects are visible even at moderate energies. Thus, the relativistic mass, energy, and momentum of an energetic electron of velocity v must be written: m = m^ /4^'P^

Etot = E^n ^E^=

(9.34) mc2 =m^c2/

^ T ^

(9.35)

^ In an elastic collision the sum of the kinetic energies of the various particles, before and after collision, is unchanged. In an inelastic collision, part of the kinetic energy is lost. It is used to excite either an electron or a nucleus into a higher energy level.

An Overview of Radiation-Matter Interactions p = mv = m^cP / ^I'P^

585 (9.36)

where c is the velocity of Ught, (c = 2.99793-10^ m/s in vacuum) and p = v/c The kinetic energy, Ej^^ , is the difference between the total energy , E^^t , and the rest energy ER. The latter is given by ER=moC^ (ER = 0.511 MeV for electrons):

Ekin = E^of^EK=(m-mJ

c^

(9.37)

Note: Normally, when one refers to electron energy one means its kinetic energy and not its total energy. The same rule holds for ions. The difference between "classic" kinetic energy E]QI|(C1) = msVl and relativistic kinetic energy E]Qn(rel) = (m-mo)c2 is 1% for electrons of 3.2 keV but reaches 50% at 312 keV. 5.2 ELASTIC INTERACTION WITH THE NUCLEUS

When electrons interact with target nuclei, the interaction process (the collision) is most frequently elastic. It can be described by the classical Rutherford formulae. The result of the interaction process is a strong deflection of the electron, but little energy is transferred to the nucleus. A special point of interest is the minimum (or "threshold") electron energy, E^j, required so that in a "head-on collision" the transferred energy equals the displacement energy E^j of the struck lattice atom, (subscript "d" stands for "displacement"). The calculations can be simplified by treating the collision as a hard sphere interaction (billiards balls). The incident particle (i.e. the electron) possesses a mass m^, a velocity Vj and an energy Ej while the target atom possesses a mass m2 and a velocity V2 = 0 . After the collision, the incident particle and the target atom have velocities v^', V2', and energies Ej', E2' respectively. For non-relativistic particles, the laws of energy and momentum conservation yield: E2 / Ej =:4 mjm2 / (nij + m2 f

(9.38)

For an electron (m2 » m^), this expression simplifies further into E2 /Ej

= 4mj /m2

(9.39a)

In the relativistic case, we find E2 /Ej

_ 4mj

(1 + 0 El 2 m2 zntjc

(9.39b)

586

W.i?. Fahrner

As an example, a 1 MeV electron transfers, in a head-on collision, an energy of 4.3 keV to a hydrogen atom, and only 69 eV to a copper atom. To observe this collision effect, a given material may be irradiated with electrons and the electron energy increased until displacements of lattice atoms are detected. The displacements can be observed either electrically, through a degradation in electrical properties (e.g. lifetime, hpE , solar cell efficiency degradation, resistance increase) or analytically (by Rutherford back scattering analysis). The value of the threshold energy, E^ , is in turn used for Ej in Eq. (9.39a) or (9.39b); and the resulting E2' value is identified with displacement energy E^. In silicon, E^j slightly depends: on beam direction with respect to crystal orientation and on doping level. Typical values are 15 eV < E^ < 25 eV , 195 keV < E^ < 325 keV. Only a small fraction of the electron energy is consumed in elastic collisions with the nuclei (e.g., 10-^ for electrons of 3 MeV in copper). On one hand this fraction is sufficient to create drastic electric changes in the irradiated material. On the other hand it is small enough that it can be neglected in stopping power calculations. 5.3 INELASTIC INTERACTION WITH THE SHELL ELECTRONS

Let us now consider a particle of charge Z^-q interacting with the shell electrons of a lattice atom and let us attempt to calculate: the energy transferred during such an interaction, and the ensuing stopping power and range. The calculations are quite intricate and require several steps given next. The discussion will be carried out for any charged particle in general.

Incident Particule Ziq, El, Vi

1 I b I

•--rCH Shell Electron

>^ ^2- ^2

Fig. 9.10: Scattering of a negatively charged particle by an electron - The interacting Coulomb force is repulsive.

An Overview of Radiation-Matter Interactions

587

5.3.1 Energy transferred to one shell electron When an energetic electron comes close to an electron bound to a lattice atom (i.e. a shell electron) a Coulomb interaction sets in between these two negatively charged particles. It follows that part of the momentum of the incoming electron is transferred to the other electron as illustrated in Fig. 9.10. Although this scattering event had originally been discussed for heavy particles, the obtained results also hold for electrons after a few modifications. They are given next. Let us call: F^, the Coulomb force (repulsive in this case), Zj the number of elementary charges carried by the incoming particle ( Zj = 1 for electrons), b the distance indicated in Fig 9.10, u a unit vector of distance OM and Ap the transferred momentum. Let us also suppose for the moment that the shell electron is "free". Ap can then be expressed as:

Ap= J F^.dt= J

!^ \ dt

(9.40)

The repulsive force Fc can be split into two components: a component F^x perpendicular to the original trajectory of the incoming electron and a component F^i parallel to that trajectory. As the incoming electron comes near the "target" electron, component F^n is first negatively oriented, and then becomes positively oriented. It follows that for velocities vj' « v^ = constant and for small deflections, J F^n dt = 0 , and the expression of Ap reduces to +00

+00

+00

Ap ^ ^F^_^-dt = ^F^ cosa dt = j F^ -r=

= dt b'

(9.41)

If we introduce velocity Vj = dx/dt we get Z ^ vj

7

bdx

^

J (x^+b^f^^

2Ziq^ vjb

The energy lost by the charged particle and transferred to the "target" electron of mass nig is given by

^E,=

i ^

=

'-i-j

(9.43)

588

W.R. Fahrner 5.3.2 Energy transferred to all electrons

The above loss holds for one shell electron with a given impact parameter b. To obtain the total loss we must first 1. sum over all the electrons (which have the same impact parameter b ) in the target along the particle path, and then 2. integrate over all impact parameters b. The first step yields AEi^j = Z2 Nj dx'AEi^

(9.44)

where N j is the concentration of target atoms; each atom being surrounded by Z2 shell electrons. The second step yields ^r^ f. , ^1 . r . dE = \27tb'db'AEi,T = •^ '

2Z?'q^'27t'Z2NTdx ^T^ ,, 1 —^—^ r-^—^^— Ib-db— ''e ^7 hmm m^'vj ^ b^

,^.., (9.45)

The energy loss per unit path length is thus given by: ^4

2

dE^ ^ 4KZi^q^'Z2NT dx m^ ' vj

^^ K^ In ^^^^^ b^i^

(9.46)

The natural limits bj^in = 0 » b^^^x "^"^ ^^^^ to a divergence of the above expression of dE/dx. The "real" bj^^ is derived from the observation, that in a classical "head-on collision", the maximum momentum transfer is m^Vj (for electrons) or 2mgVi (for heavy particles). In the textbooks, the derivation is mostly done for heavy ions, so that the general case can be written A p^^^x = 2a m^Vj, with a = 0.5 for electrons. From (9.42) we deduce that q^

2Zj

^Pmax =

7

= 2am,vj

(9.47)

^1 ^min

and thus that Zy q ^min

2

(9.48)

An Overview of Radiation-Matter Interactions

589

As to the upper limit bj^ax' l^t us recall that we have assumed a quasi-free shell electron. But in fact this electron is bound and can accept only discrete excitation energies or energies above the ionization energy. We define limit bj^ax ^s the largest impact parameter for which ionization occurs. We assume there is such a thing as an average atomic ionization energy^ I. If we disregard the excitation processes no energy can be transferred to the electrons unless AEi5 > I . This condition can be written

{Ap)\ 2mg

2Z]-q' .2

^ I

nig • v]b

(9-49)

which yields ^7

'^

2

b < b^„^ max =

J-

(9.50)

V

Relation (9.49) justifies the title of subsection 5.3, namely inelastic collisions. 5.3.3 Energy loss per unit path length Finally, the energy loss per unit path length can be calculated. It yields dE dx

4KZJ

•q^NjZ2

• [/n - U^e^l+lna\

(9.51)

nig • vj

Equation (9.51) is called the Bethe equation. The above expression of (9.51) had originally been derived for heavy particles. The relativistic correction expands the applicability of (9.51) to the high energy range which leads to Eq. (9.52) which is especially useful for electrons [17].

dx

ntj • Vj

with B, often called the stopping number, given by: B=

ln(2mic^r^ -(3 + 2/y-l/y^

)+ln(y-l)

+ (l/2)ln(y + l) )lnyf2+(l/16)-l/(8y)+9/(16y^)

and with 1

r = ^

4^^J7?

The average ionization energy I = Z211.5 eV is the generally accepted value.

W,R. Fahrner

590

5.3.4 Stopping power Instead of using ratio (-dE/dx) one often prefers to use the stopping power S(E) (defined in § 3.3.2 as - dE/pdx). Indeed quantity N T Z 2 / P varies little with Z2 . It follows that the S(E) curves for electrons in various materials will not greatly differ as visible in Fig. 9.11. The stopping power shows a broad minimum between 1 and 2 MeV. This is the reason why many irradiation experiments are carried out at this energy: even if the electron loses considerable energy, the stopping power can be assumed to be constant.

10^ r

10 o s

o

L

H2O

=^^J

d/

1 b

Pb

.s o

10" 1 10"

!

L_ULI

\

10''

LJJ.

1

I

I I I

\

L-uJ

10

10'

Electron energy [MeV]

Fig, 9.11: The stopping power of electrons vs. energy for several target materials ([3] and refs. quoted therein).

5.3.5 Range, straggling (electrons) When an energetic electron collides with a shell electron, it can lose up to one half of its original energy. This means that an originally monoenergetic beam - after going through a thin layer of matter - will display a broad spectrum of energies whose upper limit is given by the original energy (large energy straggling). In a thick absorbing layer, this energy straggling leads to a second dispersion, called range straggling. Another reason for the large range straggling is the elastic interactions with the nuclei which result in large angle deflections. Thus the usual definition of the mean path length Lof a particle given by

L= Li + L2 +...=

](—r^'dE

(9.53)

is not helpful for an electron, since the latter is subject to a zig-zag path (drunken man's walk) and its maximum penetration depth Rj differs strongly from L as illustrated in Fig. 9.12. We prefer instead to use the concept of range R defined as the depth at which the energy of the electron beam is only half its incident energy.

An Overview of Radiation-Matter Interactions

591

Fig, 9.12: Illustration of the mean path length (XLi), of the maximum penetration depth (Rj and R2) and of the range R of electrons.

10 D

•

gn

0

\ \

[—

^:>^

cu :^ P=:3

>--

2 1F 0.5 P 0.2 0.1 1 0.05

S-H

c=cq

0.02 0.01

p

^^^1

LIJ

3 3n

_i ^

%

0 ^^^^M

1

.1

0

0

H r!

r

^

L ^ tM

0.1 0.2 0.5 1 2

1 1 nn

LLL L

UL Li.

1 I 1

5 10 20 50 100 500 2000 10000 200 1000 5000

Range in aluminium R [mg cm

-2

Fig. 9.13: Comparison of ranges predicted by Eq. (9.54) (solid line) and experimental values (dots) obtained for electrons in aluminium (after [18], slightly modified).

As a rule of thumb, R = L/2 . An analytical (empirical) expression for the range is: 'R(g/cm^) = 0.543 • Ej( MeV ) - 0.160 The validity of this expression is demonstrated in Fig. 9.13 for the case of aluminium.

(9.54)

592

W,R. Fahrner

5.4 CONCLUSION

Although high-energy electrons do interact with target nuclei in a detectable manner and can cause displacement damage, the fraction of energy thus consumed is very small. Most of the energy, lost by a beam of electrons in matter is due to inelastic scattering on shell electrons. An analytical expression of the stopping power of any charged particle interacting with matter in such a way can be derived (and adapted when the charged particle is an electron). Predicted and experimental values agree quite well. 6. THE ION-MATTER INTERACTION Energetic ions being charged particles, behave in matter in a manner somewhat similar to that of electrons. Their heavier mass introduces however important differences. 6.1 MAIN ORIGINS AND PROPERTIES

An electronic device can be subjected to ion irradiation in (at least) two cases: during the manufacturing process itself and when used in a spacecraft. (i) during the manufacturing process During the ion implantation steps, ions of a selected species are accelerated towards the semiconductor target, in which they penetrate and act either as doping atoms or as reaction partners to form an insulating layer, such as Si02 or Si3N4 . The useful implantation energies range from 30 keV up to 20 MeV, and the so-called implanted "ion doses" (i.e. fluences) range from lO^^/cm^ up to lO^^/cm^. (ii) in a spacecraft Ion masses between 1 amu (H) and 56 amu (Fe) are found as constituents of the cosmic rays, with a maximum flux between 300 and 1000 MeV/amu . These particles endanger unshielded devices (e.g. solar panels) as well as shielded components (a 1 GeV proton can penetrate an Al layer 1.50 meter thick!). Just like for electrons, the stopping of energetic ions in matter is based on two mechanisms, namely: elastic collisions with the nuclei and inelastic collisions with the shell electrons. However at least two more mechanisms can take place: A third mechanism can occur beyond a critical energy (called Coulomb threshold), which depends on the ion-atom combination: the ion is captured by the atom, and forms a metastable compound nucleus, which in turn decays into various fragments while emitting p particles and gamma-quanta. The threshold for such a mechanism in silicon is about 10 MeV. The discussion of a fourth mechanism, namely Bremsstrahlung (which occurs especially for light ions) is postponed to Section 7 dealing with photon-matter interaction.

An Overview of Radiation-Matter Interactions

593

6.2 THE ELASTIC INTERACTION OF IONS WITH TARGET NUCLEI

It is possible to derive an expression for the energy transferred during the elastic interaction (scattering) of an ion with a nucleus if we assume that the "interaction potential" possesses a given form. 6.2.1 The approach used Four steps are necessary to derive an expression for the transferred energy. 1. From classical mechanics, and knowing the potential to which the incident particle is submitted, due to the presence of the nuclei, we can link the impact parameter b to the deflection angle 1^, i.e. obtain a b(i^) relationship (parameters b and '& have been defined in Fig. 9.3). 2. We then use Eq. (9.17) to link da/dQ to b . 3. Mechanics considerations let us link the transferred energy T to the deflection angle '& which yields T(iJ) and thus ^(T). 4. From the above three steps, the cross section a can be expressed as a function of T , using the expression a(b('d(T))). Finally, we can calculate the stopping power using the expression T

S^iNj/p)

JT(J(T)dT

(9.55)

0

6.2.2 The various interaction potentials and the associated cross sections A crucial aspect of the above calculations is the choice of a correct V(r) interaction potential. The following useful approaches have been tried: • hard core potential (core radii r^ , V2), V(r) = 0 for r > R = ri+r2 , V(r) = ©o for r < R • Coulomb potential, V(r) ©c r^ • inverse square potential, V(r) oc r^ • Bom-Mayer potential, V(r) ©c e-^^^ • Screened Coulomb potential, V(r) oc r^-c^^^ • Thomas-Fermi potential, V(r) oc ri.(|)(r/a) 3

• Moliere potential, V(r) oc r ^ - ^

A^cai^

594

W.R. Fahrner

In these expressions V is the above-defined "interaction potential", r is the distance away from the nucleus center, and R is the sum of the nucleus and particle radii. Each of these expressions yields different results. Below are some examples of differential cross sections thus obtained. i. the "hard core potential" yields dGh,c, ^(R^

/4)dQ

(9.56)

ii. the "Coulomb potential" (Rutherford scattering) yields: const dOcb = . . . A . . . d^ 16 • sin^ ^/2

(9.57)

For a given potential, the energy T transferred to the recoil atom can be ascribed to the scattering angle of the primary ion, i.e. T = T(1J). This means that the differential cross section for elastic scattering can be expressed as a function of 'b and thus of T. We give next three examples of such cross sections. i. the "hard core" cross section da^^ = — - dT;

with0
(9.58)

ii. the "Coulomb potential" cross section const dT d(ycb = ^f—-2; m

withO
(9.59)

J-

iii.the "inverse square potential" cross section (simplified) /— dT dCi^ = const' ^T^ ' —jjj;

with0
In all cases, the expression of the maximum energy which can be transferred corresponds to a head-on collision and is thus identical to that given by (9.38), namely T^=4mj m2 Ej / (nij + m2 f From these expressions, the total cross section is obtained by integrating:

> d«

'

dT

(9.60) (Tj^^)

(9.61)

An Overview of Radiation-Matter Interactions

595

6.2.3 Calculation of the nuclear stopping power The next step consists in inserting the above listed cross sections in Eqs. (9.25) and (9.26) which yields the nuclear stopping power: Sn = S(Ei) = (Nj/p) JT (da/dT) dT. If the nuclear interaction process were the only energy loss mechanism, R = (-1/p) j dE/Sn(E) would yield the total path of the particle. One of the most successful approaches used to calculate the range of implanted ions was given by Lindhard and his co-workers [19]. They used a Thomas-Fermi potential of the form:

V(r) =

r

^^q'

(9.62)

with . ry2/3 J/2 ap =0A7A'' /(Zf' 2/3 +Zl'' )

A straightforward treatment yields a nuclear stopping power, which can be written (after a minor simplification, [20]) ln(kj Ej ) ^red ' ^n = ^^^^^ '

TAQ^

(9.63)

In this expression kj = (apm2)/(ZiZ2 q^(mi+m2)) is a material constant. Product x^-^^.S^ is a function of a reduced energy, 8^^^^ = kj.E^. In the same way we introduce a reduced length coordinate Xj.^^ = k2 x (with k2 = N j 471 ap^ mim2/(mi+m2)^ ). Then Eq. (9.63) becomes ^ d£,,d ^

ln£,,d

^^^4^

This is the universal nuclear stopping power for all ion-solid combinations. This curve is plotted in Fig. 9.14 using reduced units. For comparison purposes, the (deYQd/dxj;^^^)^ curve computed using the inverse square potential has also been plotted in Fig. 9.14. In this last case we note that T

^n = (^T / p) JTdc 0

T

= const • -j= ^^'"

J T~^^^ dT = const 0

W,R. Fahrner

596

X •s

I

A

0.6 0.5 0.4 0.3 0.2 0.1 0

U—1k—

inverse square potential

tzj

Lindhard et al.

t—\ t—^

0

3

8^' Fig, 9.14: The universal nuclear stopping power for ions in solids is plotted vs. energy using reduced units [5]. 6.3 THE BSELASTIC INTERACTION OF IONS WITH SHELL ELECTRONS

The interaction of an ion with shell electrons is described by the same (Bethe-) equation as in the case of electron irradiation (i.e. Eq. (9.51)). The specific irradiated matrix is taken into account by means of additional terms. The energy loss per unit path length (due to this interaction) is given by dE_ ^

dx

4KZJ -q^ 7^2^T

m^

vf

(9.65)

(In ( I

C

C

^0

(In accordance with the textbooks, this equation has been written in electrostatic units. For MKS-units one should replace q by q/(47C£)l/^ ). Cj^ is a correction factor which depends on energy and on Z2 , with 0 < Cj^ < 1 . The dependency of -dE/dx on energy Ej^^ (in units of m^c^ , m^ = particle mass) is shown in Fig. 9.15. For particles supplied by an accelerator, Ej^^ is the product of the charge Zj q by the accelerator voltage V. A discussion and measurement data for dE/dx can be found e.g. in [5]. For the discussion it is helpful to transform Eq. (9.65) by using (Vi/c)2=l.l/(l+Ekin/mic2)2.

An Overview of Radiation-Matter Interactions

I

597

I

;:xq X

^5001

3mjC 2

E kin Fig, 9.15: The electronic stopping power of ions in solids is plotted versus incident energy (after [5]f 21]),

We note on Fig. 9.15 that, at low energies, the curve is controlled by the behavior of the (In Ekin)/Ekin"term , i.e. a fast rising branch below 500 I and a fast falling 1/Ej^n branch for 500 I < ^kin - ^1^^ • ^t high energies, a very slight increase due to the relativistic terms occurs, and thus a broad minimum between 2 to 3 m^c^ is observed. Figure 9.16 represents the stopping power of various charged particles in air: 0,050 o >

0,040 0,030 0,020

LUlx

•O|T3

0,010 I02

10^

©-»

Energy IMeV]

Fig. 9.16: The electronic stopping power of various charged particles in air is plotted versus incident energy (after [22]).

W,R. Fahrner

598

The ionization density of the irradiated medium is a direct measure of the electronic stopping power. An example (the number of molecules ionized in air by a particles) is reproduced in Fig. 9.17. In this representation, E can be understood as the energy of the alpha particle during its path through the absorber. Referring to Fig. 9.15 this means that we start somewhere at the higher energy end of the 1/E branch. When the particle loses energy, we move from right to left on the curve, -dE/dx increases up to a maximum and so does the ionization phenomenon, showing the so-called Bragg peak.

2.5

2.0

1

1

Residual range [cm] 1.5 1.0 0.5

1

1

1.5

csi

"S •2 0.5

1

u^ r>

1.0

1

1

1

L

y 3j 1 J

o GO

0

0

0

a-Particle energy E^ [MeV] Fig. 9.17: The specific ionization of a-particles in air is plotted vs. energy (lower scale) or range (upper scale) (after [23]). The particle penetrates in air with energy 4 MeV (left) and stops when its energy is nil (right). 6.4 RANGES, STRAGGLING (lONS)

When travelling through matter, an ion is slowed down both by elastic collisions with the nuclei and by inelastic collisions with the shell electrons. The range of the ion is given by Eq. (9.27) which we recall below:

R(Ei) = - (1/ p) ]

dE

Sn^S,

Technically the range of the ion is of interest in two cases

(9.27)

An Overview of Radiation-Matter Interactions

599

(i) for the shielding of components and circuits. For this purpose the shield (absorber) thickness must by far exceed the range of the incoming particles. (ii) for ion implantation. The depth distribution of implanted ions follows a law given by :

N(x)=N^exp-(

42 AR,

r

(9.66)

Rp being the mean projected range, ARp its straggling. During implantation the ions are scattered statistically by the atoms and penetrate into the semiconductor following different paths and with different depths. A typical experimentally-observed distribution is shown in Fig. 9.18. Curves of this type have been gathered for a long time in the fields of nuclear and now solid state physics (and still are). An example for boron implantation in silicon is given in Fig. 9.19. damage [%]

120

UO

depth [(am] Fig, 9.18: Optical reflectivity (as a measure of ion range) vs. depth after a 55 MeV boron implantation. The measurements were performed on a bevel; the three curves stand for three measurements at different positions on the bevel ([24]).

For practical usage, there exist some helpful tables giving values of range, straggling, third and fourth moments (parameters describing deviations from the Gaussian distribution), electronic and nuclear stopping powers. Among these, we present two examples: one in the low energy range (table taken from [11]) and one in the high energy range (graph taken from [26]). It should be noted, that the above data apply to ion distributions in an amorphous matrix. If the real structure of the crystal is taken into account, the crystal offers tube-like openings in the main crystal directions. It is obvious, therefore, that a far-reaching penetration of the ions along these channels will occur. This effect is called (axial) channelling. A similar channelling can occur between lattice planes. Axial and planar channelling will not be discussed here in more detail.

600

W.R. Fahmer

Q^

10*

10

10

-1

10

10'

10'

10'

10'

10'

E [eV Fig. 9.19: The range of boron in silicon is plotted versus energy. Experimental (-) and theoretical (—) data are compared (after [25]). 6.5 CONCLUSION

Ions, whose kinetic energy is below a few MeV, lose energy in matter through basically two mechanisms : elastic interaction with the nuclei and inelastic interaction with the shell electrons. Both the nuclear stopping power and the electronic stopping power can be modeled and computed if a number of assumptions are made. The relative weight of each mechanism depends on the nature, charge and energy of the ion as well as on the nature of the irradiated matrix, as illustrated in Fig. 9.5. Theoretical and experimental results agree quite well in the case of amorphous substrates.

Z >

CB

a. te tnmm K ItfO Z

«

u uic z

tu « « A * *

ee > U X .i ^ r — o a VI «•- z «^' o o < « z ^ o

o z

•J c a w» < a •- Z a < »- O u« o « «c ¥- Z ^ U «i < > • VI O «•

• I H>ttfZ

a » - o I« z —< •- t/ii- s K O OL •Z «A lU O O «/> V < »- C y j u < ac

"n z •-<-» u « >•-• cc i» uj z cv «/> O w

z

-*

w> Z

z o Q: o o

««i

•J

ee

o u •w

Q OC

oe oti. u

lO

»m» »^« < »• v» Ul

< «<

u z w>

An Overview of Radiation-Matter Interactions

OO O O O O W C * 0 0 0 O O O OOOOCf I O O O O O O O O O O O C 9 0 0 0 o o o o o o o o o o o tti W4IMttlM'UIU'tt«IW lU aU UJ IM IM U« lUIMIUIUIMaMMIUItt'lWlU tt<«L'iMuiwuiiuiutt.*uru*«i<;iuuitt.u*uiiuiw

Aim««o»«Dm««»«-tiN>m•m<MO^«mo^»mo ^Mm^«m«f^^>«BO'

»ooooo oooo O O O O O O O O O O O

O O O O O O O O O O O

moo*ino*cD«-««o»«v«i

UllViy III Ml IM l u lU III III III 00'«^<Mn<-«W>«pry|«C\<M

OOOOOOOOOOO

oooooocioooooooooooo 1 ooooooooo oooooo oeooooooooo (MM«VrMCMfM<MflMri<MiMI>l(MMlV«Mf«lt^<M I

rrt«>«^«OOCMCMO'MOlM<0«0«r

OOCfOOOOOOOOOOOOOOOO I OOOOOOOOO 0 0 00C»0 iOO» <M«i(MaD^ocbinrsiiof>tf\o*-««\f^r»

U#l|IIM(UUIIttllfUll0UIU>lUlUUIUflllllllllU« i

o o o e o e

^ « Ci* «•« «i« ^ « *i« ^ * ^•«ii« ^ « «>• v ^ «»• «i4 ^

o o O O O O O O O O O O O O O O O O O I OOOOOOOOO

co»«m«Drt«o««n^(rin« •Otor•^-«9«D«BO'0> o » o o o * « * 4

^f««iuo»«oi^aD mcD M«o c m «rM^»•««>»«D9' mmmmmmmmm mmmmmm o o o o o o o o o e o o o o o o o o o i O O O O O O O O O o o o o o o o o O O O O O O O O O O O o o o o o o I OOOOOOOOO o o o o o o I fn04>of^mO»i««>«r«B«0(^co<Mnfn <MOf^«rw«f*'««fn««mo«fM
O O O O O O O O O O O O O O o o o o o I O O O O O O O O O 0^^«>««^«^ fnoma>o*o«fl0^mofri«ocM o «r r>» «i4^ ^•^#i«^•<nomcDfsl^>••« i iv»«De«o«^iMMf<)fn«r ^ m m < o 4 i I «r*«B«o o» o> oo»i« ai^M «^iM mm m ^ m m « 4 ^* «<• «
«M «^ <M <^ M (M c^ <w i n m en I I I I I I 1 I I I I

«r ^cr ^ o m o«-«o asm o <#^«o Okm« io r» «B «B o» o» o o ^ •*« rn «%i M m^m««^*«D<^oo«-« I I I I I I I I I I I I I I I

OOOOOOOOOOOI

I (nO«0*«f>lfMOh>^0flaO'0'0<-**««>ifMimm^««^>^»^*f>>«9 «oaoaaasa o o o o o o o o o o o o o o o o o o o o o o v i o o v o o o o o oo o oo o o I o o o o o o o o o o oo o o e

«Mifym

!*• «i*«D «>mm f^fMu* a-Af* f* t>i m o croocrr<»<«>o«omflo*^^ <^
m«Mf*fM«»«n«om««t^ai«r*
Ul (M

iT

m m

(^•

o» OQ oCD

<

O Z Z

O Q CO

i ••

Z

m «^

•>!

m Z U

Z

1^ M •

oc C 3R

u Z ••

2

Ul

ui«/> - 1 ^ mil..

ee KZ uui

§

u.

I

«>« #14 ••« Vi* «« •-• »4 ••4 #4 • « «i4 I

III

o o

fM

o

•4

»N III

m M

o0 *

^

o Ul

• i «

o m

m

l«»

««

<M

IT 0»

«n o•

2 £

11.

o o o o o o o o o o o o o o o o o o o I o o o o o o o o o o o o o o ^

o0 « o

• 01 (M

«r o•

Ul 1/1

z G

•-

O O O O O O O O O O O o m o m o m o m o m o mm»r«cBaao«o»o

^ *4

0(M OOOOIo^^O •4Cll(n<^m^r»40o^o•-•<Mfnt,rm^f«>ca<^ • iM<M<MfM(Mininmfnm«r<^'^^^

z u Q

•• ««
o• u* ""^ v» a. Ul

o

OOOO'^OOOo'SOOoOTJOOOO I - ^ o o o o o o o o o o o o o o

M

Ul

«m ^ z « Of

a< III ¥" U.

< ^ t/» (0

o• oe N» o «Z

Fig, 9.20: Range data for the implantation of boron in silicon (excerpt from [11]).

601

602

W.R. Fahrner

Si(14)

TARGET

4-<-«-

Atom Density « 4.978 x 10^2 A