Materials for Electronic Packaging

Materials for Electronic Packaging

This Page Intentionally Left Blank

Materials for Electronic Packaging Edited by Deborah D. L. Chung

Butterworth-Heinemann Boston Oxford

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Copyright 9 1995 by Butterworth-Heinemann. A member of the Reed Elsevier group All rights reserved.

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Library of Congress Cataloging-in-Publication Data Materials for electronic packaging/edited by Deborah D. L. Chung p. cm. Includes bibliographical references and index. ISBN 0-7506-9314-2 1. Electronic packaging--Materials. I. Chung, Deborah D. L. TK7870.15.M38 1995 621.381'046--dc20

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94-49204 CIP

Contents

Contributors Preface xiii

xi

PART I Overview Overview of Materials for Electronic Packaging D. D. 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9

L. Chun9 Introduction 3 Printed Circuit Boards 16 Substrates 19 Interconnections 27 Die Attach 30 Encapsulation 31 Interlayer Dielectrics 33 Heat Sinks 34 Electromagnetic Interference Shielding References 36

35

PART I I Joining Solderability Fundamentals: Microscopic Processes J. A. 2.1 2.2 2.3 2.4 2.5 2.6

43

Clum, T. J. Singler Introduction 43 Background 44 A Microscopic Mass Transfer Model 48 Observations of Limiting Mass Transfer 50 Solder Alloy Selection and Process Design 54 Conclusion 55 References 56

vi

Contents

Determining the Damaging Strains which Cause Failure in Pb-Sn Solders 57 A. I. A ttarwala, B. C. Hendrix, J. M. Sanchez 3.1 Introduction 57 3.2 Test Methodology and Data Analysis 58 3.3 Deformation Behaviour of Pb-Sn Solders under Static and Cyclic Loading 64 3.4 Effect of Anelastic Strains on Accelerated Test Results 70 3.5 Lifetime Predictive Equation for Pb-Sn Solders 70 3.6 Summary 75 Acknowledgment 75 References 76

Fluxless Soldering for Microelectronic Applications D. R. 4.1 4.2 4.3 4.4 4.5

79

Frear, F. M. Hoskin9, D. M. Keicher, H. C. Peebles Introduction 79 Fluxless Laser Soldering 81 Activated Acid Vapor Fluxless Soldering 86 Laser Ablative Fluxless Soldering 93 Summary and Examples 101 Acknowledgments 102 References 103

The Effect of Microstructure on Fracture of Metal/Ceramic Interfaces 105 Ivar E. Reimanis 5.1 Introduction 105 5.2 Fracture Behavior 107 5.3 Grain Distributions in the Metal Layer 5.4 The Interface Pore Distribution 115 5.5 Interface Roughness 119 5.6 Summary 123 Acknowledgments 123 References 123

110

III Composites The Future of Advanced Composite Electronic Packaging Carl Zweben 6.1 Introduction 127 6.2 Status of Composite Packaging Materials 6.3 Applications 135

128

127

Contents

6.4 Future Directions 139 6.5 Summary and Conclusions References 142

142

Low Thermal Expansion Composite Materials for Electronic Packaging 145 D. D. 7.1 7.2 7.3 7.4 7.5

L. Chun9 Introduction 145 Heat Sinks, Backboards, and Substrates Brazes and Solders 149 Die Attach 150 Interconnections 152 Acknowledgment 152 References 152

147

Conducting Polymer-Matrix Composites 153 D. D. 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9

L. Chung, Lin Li Introduction 153 Particles as the Filler 155 Flakes and Fibers as Fillers 156 Three-Dimensional Networks as Fillers 161 Slug as the Filler 164 Effect of the Polymer Viscosity 164 z-Axis Conductors 165 Electrically Insulating but Thermally Conducting Composites Conclusion 169 Acknowledgment 170 References 170

P A R TI V Metal Films Thick Film Technology 175 Renb E. Cotb 9.1 Introduction 175 9.2 Overview of Materials and Processes 9.3 Resistors 178 9.4 Conductors 185 9.5 Dielectrics 194 9.6 Vehicles 199 9.7 Thick Film Processing 202 9.8 Conclusion 220

175

168

vii

viii Contents 10 Electroless Copper for Micropackaging and Ultralarge-Scale Integrated Circuit Applications 221 Y. Shacham-Diamand

10.1 10.2 10.3 10.4 10.5 10.6 10.7

Introduction 221 Electroless Copper Deposition 224 Copper Nanoline Processing 227 Electrical Properties 233 Electroless Copper Oxidation 235 Hydrogen in Electroless Copper 236 Conclusions 239 Acknowledgments 239 References 240

11 Vacuum Metallization for Integrated Circuit Packages 241 K. J. Blackwell, P. C. Chen, A. R. Knoll, J. J. Cuomo 11.1 Introduction 241 11.2 Vacuum Processes 241 11.3 Coating Vessels 246 11.4 Physical Vapor Deposition by Evaporation 247 11.5 Evaporation Methods and Sources 251 11.6 Sputtering 254 11.7 Heat Transfer in Physical Vapor Deposition Processes 11.8 Roll Coater Metallization 265 11.9 Coating Material Properties 266 11.10 Evaluating Deposited Films 267 11.11 Conclusions 276 References 277

263

PARTV Polymers and Other Materials 12

Silicone-Based Polymers in Electronic Packaging

281

C. P. Wong

12.1 12.2 12.3 12.4 12.5 12.6 12.7

Introduction 281 Why Do Devices Need Encapsulation? 281 General Chemistry of Silicones (Elastomers and Gels) Results and Discussion 286 Temperature Humidity Bias (THB) Testing 288 Temperature Cycle Testing 288 Conclusion 289 References 289

284

Contents ix 13 Dielectric Films for High Temperature, High Voltage Power Electronics 291 Javaid R. Layhari, Jayant L. Suthar 13.1 Introduction 291 13.2 Experimental 292 13.3 Results and Discussion 295 13.4 Summary 300 Acknowledgment 301 References 301

14 Electrically Conducting Polymers and Organic Materials 303 M. J. Naughton 14.1 Introduction 303 14.2 Organic Conductors and Superconductors 305 14.3 Conducting Polymers 312 14.4 Potential Applications of Conducting Polymers 314 References 315 15 Diamond in Electronic Packages 319 D. J. Pickrell, D. S. Hoover 15.1 Introduction 319 15.2 Background on Diamond 319 15.3 Chemical Vapor Deposition of Diamond 321 15.4 Fabrication of Electronic Substrates 331 15.5 Package Design Considerations 333 15.6 Conclusion 335 References 335

PARTV l Materials Testing 16 Measurements of Properties of Materials in Electronic Packaging Joseph A. Carpenter, Jr. 16.1 Introduction 341 16.2 Electrical Properties 344 16.3 Thermal Properties 346 16.4 Mechanical Properties 352 16.5 Physical Properties 355 16.6 Manufacturability Properties 355 16.7 Summary 356 Acknowledgments 357 References 357 Index

361

341

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Contributors

A. I. Attarwala Strategic Materials R&D Laboratory The University of Texas Austin, Texas

Ren6 E. Cot6 DuPont Electronics Fort Worth, Texas

K. J. Blackwell

IBM Technology Products Endicott, New York

J. J. Cuomo IBM Research Yorktown, New York

Joseph A. Carpenter, Jr. Ceramics Division National Institute of Standards and Technology Gaithersburg, Maryland

D. R. Frear Center for Solder Science and Technology Sandia National Laboratories Albuquerque, New Mexico

P. C. Chen IBM Technology Products Endicott, New York Deborah D. L. Chung Department of Mechanical and Aerospace Engineering State University of New York at Buffalo Buffalo, New York J. A. Clum Department of Mechanical Engineering Watson School of Engineering and Applied Science State University of New York Binghamton, New York

B. C. Hendrix Strategic Materials R&D Laboratory The University of Texas Austin, Texas D. S. Hoover Diamonex, Inc. Allentown, Pennsylvania F. M. Hosking Center for Solder Science and Technology Sandia National Laboratories Albuquerque, New Mexico xi

xii

Contributors

D. M. Keicher Center for Solder Science and Technology Sandia National Laboratories Albuquerque, New Mexico A. R. Knoll IBM Technology Products Endicott, New York Javaid R. Laghari Department of Electrical and Computer Engineering State University of New York Buffalo, New York Lin Li Department of Mechanical and Aerospace Engineering State University of New York Buffalo, New York M. J. Naughton Department of Physics State University of New York Buffalo, New York H. C. Peebles Center for Solder Science and Technology Sandia National Laboratories Albuquerque, New Mexico D. J. Pickrell Diamonex, Inc. Allentown, Pennsylvania

Ivar E. Reimanis Max Planck Institut fiir Metallforschung Stuttgart, Germany J. M. Sanchez Strategic Materials R&D Laboratory The University of Texas Austin, Texas Y. Shacham-Diamand School of Electrical Engineering Cornell University Ithaca, New York T. J. Singler Department of Mechanical Engineering Watson School of Engineering and Applied Science State University of New York Binghamton, New York Jayant L. Suthar Department of Electrical and Computer Engineering State University of New York Buffalo, New York C. P. Wong AT&T Bell Laboratories Princeton, New Jersey Carl Zweben GE Astro Space Division King of Prussia, Pennsylvania

Preface

Electronic packaging refers to (1) the packaging of integrated circuit chips (dies); (2) the interconnections (both on and off the chips) for signal transmission, power, and ground; (3) the encapsulations for protecting the chips and interconnections from moisture, chlorides, and other species in the environment; (4) the heat sinks or other cooling devices needed to remove heat from the chips; (5) the power supply; and (6) the housing for electromagnetic interference (EMI) shielding. Semiconductor technology has made tremendous progress in the last few decades, and the present problems in the electronics industry lie mainly in electronic packaging, which is critical to the reliability and performance of electronic systems. The technology behind electronic packaging involves both systems and materials considerations. Systems considerations pertain largely to the packaging schemes, whereas material considerations pertain to the development of improved materials that allow more demanding packaging schemes to be possible. An example is the development of materials of high thermal conductivity for dissipating heat from the package. Another example is the development of materials of low thermal expansion for avoiding failure due to thermal stresses during thermal cycling. Yet another example is the development of conducting adhesives to replace solders, which are undesirable due to the ozone-depleting tendency of the defluxing chemicals. Although materials play a critical role in electronic packaging, the vast majority of attention has been given to the systems aspect. This situation is partly due to the fact that the training of most workers lies in electrical engineering rather than materials science/engineering. Another reason is that most materials experts shy away from the field because they feel that they do not know its needs well enough. Most advanced materials have been developed for structural applications rather than electronic packaging applications. A goal of this book is to alleviate this situation by viewing the field from a materials perspective. This perspective is in contrast to the systems perspective offered by other books on electronic packaging. In contrast to conference proceedings, this book consists of self-contained chapters which are review or tutorial in nature and are broad in scope. The 16 ooo

xm

xJv

Preface

chapters are grouped into six parts: (1) overview, (2)joining, (3) composites, (4) metal films, (5) polymers and other materials, and (6) materials testing. The chapters are contributed by a variety of active researchers from industrial, academic, and governmental sectors. This book is suitable for use as a textbook or a reference book for students (senior undergraduate or graduate) or professionals interested in electronic packaging. Although it adopts a materials perspective, the book requires only basic knowledge of materials science at the junior undergraduate level. It assumes no knowledge of electronic packaging and only a small knowledge of electronics. The subject matter is relevant to materials scientists/engineers, electrical engineers, mechanical engineers, physicists, and chemists. With the exception of Chapter 9, each chapter contains a list of up-to-date references. I hope this book will help increase research into electronic packaging materials, a field full of scientific excitement and technological relevance. Deborah D. L. Chung

PART I

Overview

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CHAPTER

1

Overview of Materials for Electronic Packaging D. D. L. Chung

1.1 Introduction Electronic packaging refers to (1) the packaging of the integrated circuit chips (dies); (2) the interconnections (both on and off the chips) for signal transmission, power, and ground; (3) the encapsulations for protecting the chips and interconnections from moisture, chlorides, and other species in the environment; (4) the heat sinks or other cooling devices needed to remove heat from the chips; (5) the power supply; and (6) the housing for electromagnetic interference (EMI) shielding. Its conventional hierarchy has the following levels [1], which are illustrated in Figures 1.1 [-1] and 1.2 [2]: Level O" bare chip as removed from the finished wafer. Level 1. bare chip mounted on a chip carrier (or substrate) and encapsulated as a packaged chip (category I of level 1); bare or packaged chip(s) mounted on a module, called multichip module (MCM), together with discrete components (category II of level I). Level 2" printed circuit board (or card) with packaged chips, modules, and other components. Level 3: backplane (or mother board) into which printed circuit boards (or cards) are inserted. Level 4: electronic module formed by integration of backplane and power supply with an outer housing. Level 5: system formed by integration of electronic module. During the last 20 years, most of the attention of the electronic industry was directed to level 0, which constitutes the heart of the electronics. This effort, which was centered on semiconductors, resulted in a rapid increase in the packing density of devices on a chip, as indicated by the rapid miniaturization of electronics in the last 20 years. However, this miniaturization is accompanied by large increases in the amount of interconnections associated with each chip and in the amoun! of heat generated by each chip. Therefore, the key to further miniaturization currently lies on levels 1, 2, and 3. The immediate goal is to package the chips

4

MATERIALS FOR ELECTRONIC PACKAGING

Wafer

Level 0

Level 1

\

/ (

I il /

V

/ Y

i

'\ llllllllllllllllllll

Level 4

Level 3

i

Level 2

Figure 1.1 Hierarchy of electronic packaging. (Reprinted by permission of Chapman & Hall Ltd. from W. Eakin, K. Gardiner, and J. Nayak, Journal of Electronics Manufacturing 1, 13-22 (1991).

2

Scale of

Electronic Equipment [C Card and Ultra Small Size

I (Daughter Board )

3rd Level

!

I

Board _] (MotMer Board,Back Board )

I

[

4th L e v e l

~

5 t h Level .

,,

(EM)

1

~

'~

Medium Size Large Size Large Size

!Equipment L

Small Size

System

Ultra Large Size

Figure 1.2 Printed circuit board mounting classes and scale of equipment. (Reprinted by permission from K. Takagi and S. Yasufuku, IEEE Electrical Insulation Magazine 7(2), 9-16, 19-27 (1991) 9 1991 IEEE.)

Overview of Materials for Electronic Packaging

5

and the associated interconnections in a compact way that allows for sufficient heat removal, that can withstand the thermal cycling associated with the turning on and turning off of the electronics, that protects the electronics from environmental attack, and that allows the electronics to operate at high speeds. As the power of electronics increases, the heat dissipation problem becomes even more difficult. As the speed of electronics increases, the signal delay caused by the capacitive effect of dielectric packaging materials becomes more intolerable. It is anticipated that levels 4 and 5 will start to dominate the picture in about 10 years. This book is mainly concerned with levels 1, 2 and 3, which are of current importance. The solution of the electronic packaging problem involves the devising of packaging schemes and the use of advanced materials. Both aspects of the work are important and must take place coherently. Materials are intimately tied to processing, which is directly affected by the packaging scheme. Certain packaging schemes may not be possible unless advanced materials are used. For example, a packaging scheme may require so much heat dissipation that an advanced thermal conductor must be used. Although materials play an important role in electronic packaging, most of the work on electronic packaging is concerned with packaging schemes rather than materials. Examples of packaging schemes are wafer-scale integration (WSI) [3]; power hybrid packaging [4]; three-dimensional interconnection [5]; high density interconnect (HDI), which uses an interconnect overlay [6,7]; and others [8,9]. This book therefore focuses on materials for electronic packaging. The actual applications of materials in electronic packaging include interconnections, printed circuit boards (Figs. 1.3 [10], 1.4 [2], and 1.5 [ 11]), substrates (Fig. 1.5), encapsulations (Figs. 1.6 [2] and 1.7 [12]), interlayer dielectrics, die attach, electrical contacts, connectors, thermal interface materials, heat sinks, solders, brazes, lids, housings, and so on. In general, the integrated circuit chips (dies) are attached to a substrate or a printed circuit board on which the interconnection lines have been written (usually by screen printing) on each layer of the multilayer substrate or board. In order to increase the interconnection density, another multilayer involving thinner layers of conductors and interlayer dielectrics may be applied to the substrate before attachment of the chip. By means of soldered joints, wires connect between electrical contact pads on the chip and electrical contact pads on the substrate or board. The chip may be encapsulated with a dielectric for protection. It may also be covered by a thermally conducting (metal) lid. The substrate (or board) is attached to a heat sink. A thermal interface material may be placed between the substrate (or board) and the heat sink to enhance the quality of the thermal contact. The whole assembly may be placed in a thermally conducting (metal) housing. There are numerous variations to the packaging described above. In the most conventional variation, one or more chips are attached to a ceramic substrate via soldered joints, while the substrate is in turn mounted via soldered joints to a printed circuit board (also known as a card). In another variation, the chip is attached directly on the card, resulting in a direct chip attach module (DCAM).

b MATERIALSFOR ELECTRONICPACKAGING

Figure 1.3 Printed circuit board shown in cutaway to reveal inner-interconnection layers and vias; a surface mount device (left) and a through-hole device (right). Surface mount devices can be mounted on both sides of the board and do not consume valuable inner layer space with the through-hole. From [10]. Via Hole Interstitialvia 1 hole(~uried)

Interstitialvia hole(Blind)

Componentlead Insertiinhole

[== L,., .......

l== Figure 1.4 Structure of plated-through hole multilayer board (eight layers). (Reprinted by permission from K. Takagi and S. Yasufuku, IEEE Electrical Insulation Magazine 7(2), 9-16, 19-27 (1991) @ 1991 IEEE.) In yet another variation, the chip is attached via a cardlet, one of many small cards, attached to a large card, resulting in a multichip module laminate (MCML). An M C M L obviates the need for a sophisticated mother card, allows denser packaging than DCAM, and is less expensive than a multichip module involving ceramic substrates. The conventional packaging process involves putting the interconnections on a flat substrate before putting on the chips--a process known as chip last. A new process, chip first, saves the total number of processing steps by putting the chips in wells of chosen depths in a substrate before putting the interconnections on the plane of the welltops.

Overview of Materials for Electronic Packaging

1.700 SQ

.O32-.050 "]w AIRFLOWv ~

e~

7

6061, Aluminum

~-.soo --~ "

l:

9176

Epoxy 2 mil thick

t-- .030

--T-

t__.o5o

.095 .015 PC Board

.550 SQ _ _ ~

A!203 90%

;ilicon

,800 9 SQ

Figure 1.5 Cutaway view of a pin grid array (PGA) package. (Reprinted by permission from R.J. Schnipke, D. Hayward, and J.G. Rice, in Proceedings of the 5th IEEE Semiconductor Thermal and Temperature Measurement Symposium, 1989, pp. 81-87 9 1991 IEEE.)

A printed circuit board (Figs. 1.3-1.5) is a sheet for the attachment of chips, whether mounted on substrates, chip carriers, or otherwise, and for the drawing of interconnections. It is a polymer-matrix composite that is electrically insulating and has conductor lines (interconnections) on one or both sides. Multilayer boards have lines on each inside layer so that interconnections on different layers may be connected by short conductor columns called electrical vias (Figs. 1.3 and 1.4). Printed circuit boards (or cards) for the mounting of pin-inserting-type packages (Fig. 1.6(a)) need to have lead insertion holes punched through the circuit board (Fig. 1.3, right; Fig. 1.4, right). Printed circuit boards for the mounting of surface-mounting-type packages (Fig. 1.6(b)) need no holes. Surface-mounting-type packages, whether with leads, leaded chip carriers, or without leads, leadless chip carriers (LLCCs), can be mounted on both sides of a circuit board (i.e., a card), whereas pin-inserting-type packages can only be mounted on one side of a circuit board (Fig. 1.3). In surface mounting technology (SMT), the surfaces of conductor patterns are connected together electrically without employing holes. Solder is typically used to make electrical connections between a surface-mounting-type package (whether leaded or leadless) and a circuit board. A lead insertion hole for pin-inserting-type packages is a plated-through hole, a hole on whose wall a metal is deposited to form a conducting penetrating connection. After pin insertion, the space between the wall and the pin is filled by solder to form a solder joint. Another type of plated-through hole is a via hole (Fig. 1.4, left), which serves to connect different conductor layers together without the insertion of a lead. Holes become difficult to drill and plate as the ratio of board thickness to hole diameter, called the aspect ratio, increases. Via holes that do not go all the way through a circuit board are called interstitial via holes (IVHs), which include buried holes and blind holes (Fig. 1.4, center). A buried hole connects the internal conductor layer

8

MATERIALS FOR ELECTRONIC PACKAGING

Name

Appearance

Remarks Material

Lead Pitch, etc

DIP

DUAL INLINE PACKAGE

P C

2.54 mm (100 mil) Lead Pin No. 4 --- 64 Pin

S-DIP

SHRINK DIP

p

1.778 mm (70 mil) Lead Pin No. 4 --- 64 Pin

SKINNY

SKINNY DIP

P

2.54 mm (70 mil) Widthwise Pitch 1.2 Size Lead Pin No. 8 --- 28 Pin

PGA

PIN GRID ARRAY

2.54 mm/1.27 mm (100 mil)/(50 mil) Lead Pin No. 64 --- 240 Pin

(a) Pin Inserting Type Package

Name SOP

SMALL OUTLINE PACKAGE

QFP

QUAD FLAT PACKAGE

LCC

LEADLESS CHIP CARRIER

PLCC

PLASTIC LEADED CHIP CARRIER

SOJ

JBEND SOIC

PGA

PIN GRID ARRAY

Appearance

Remarks Material

,,,~r ~

Lead Pitch, etc 1.27 mm (50 mil) Two-way Lead 16 --- 36 Pin 1.0mm

0.65ram

9

Four-way Lead 20 --- 128 Pin 1.27 mm (50 mil) 1.00 mm (40 mil) 0.975 mm (30 mil) Contact No. 16 --- 36 Pin

/ ~ ~

j-/~",,,~ ~

1.27 mm (50 mil) J-Shaped Lead 16 --- 124 Pin

~

1.27 mm (50 mil) Two-way Lead 16 --- 124 Pin

,,,,c~~ ~-'~<'f "",>""-,~ ~ y

P C

1.27 mm Lead Pin No. 100 --- 500 Pin

Note P = Plastics C = Ceramics

(b) Surface Mounting Type Package

Figure 1.6 Integrated circuit package types: (a) pin-inserting-type package and (b) surface-mounting-type package. (Reprinted by permission from K. Takagi and S. Yasufuku, IEEE Electrical Insulation Magazine 7(2), 9-16, 19-27 (1991) 9 1991 IEEE.)

Overview of Materials for Elecfronic Packaging

Die

Epoxy B Molded ,

Surface Encapsulant, If Used

9

Bump-Tape Inner Lead Frame

Outer Lead Frame

Figure 1.7 Molded package showing encapsulation and molded body (Reprinted by permission of ASME from C.P. Wang, Journal of Electronic Packaging 111(2),97-107 (1989).)

I Pol~mer I

I Fibers I ! Patte rned meta foils

I Prel "egs I

I

rCuring

I Lam'nate I ~Orilling ! Laminatewithholes I ~Plating Laminatewith plated-throughholes Figure 1.8

Fabrication process for printed circuit boards.

patterns together; a blind hole connects the surface layer pattern and an internal layer pattern together. Figure 1.5 illustrates the insertion of pins from a substrate (or chip carrier) called a pin grid array (PGA) to a printed circuit board. The pin grid array is one of the styles of pin-inserting-type packages (Fig. 1.6(a)). The main ingredients in a printed circuit board composite are the polymer matrix (e.g., epoxy) and reinforcing fibers (e.g., glass, Kevlar). The conventional method of fabricating a printed circuit board involves the lamination of fiber prepregs, as illustrated in Figure 1.8. In addition to the interconnections, metal layers and columns (Fig. 1.9 [13]) can be embedded in a board for the purposes of restraining the thermal expansion and heat dissipation; such metal columns are called thermal vias.

10

MATERIALS FOR ELECTRONIC PACKAGING LCCC

THERMAL VIAS PCB

a

HEAT SINK LCCC b

j:./i:. :i: .i.i:!.i:7.-:.!.i:."i:!:i:::::i:.:::::i:iiii:iii!i ..:i!J

CONSTRAINING METAL CORE

LGCC

1

:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: CONSTRAINING

C Figure 1.9

Cross sections of printed circuit boards with heat sink and metal core foils.

From [-13]. A substrate, also called a chip carrier (Fig. 1.5), is a sheet on which one or more chips are attached and interconnections are drawn. In the case of a multilayer substrate, interconnections are also drawn on each layer inside the substrate, such that interconnections in different layers are connected, if desired, by electrical vias. A substrate is usually an electrical insulator, although, with the use of a dielectric film on the surface, an electrical conductor can also be used. Substrate materials include ceramics (e.g., AI20 3, A1N, mullite, glass ceramics), polymers (e.g., polyimide), semiconductors (e.g., silicon), and metals (e.g., aluminum). The most common substrate material is A120 3. The fabrication of a multilayer A120 3 substrate with typically W or Mo interconnections is illustrated in Figure 1.10. As the sintering of A120 3 requires temperatures greater than 1 000~ the metal interconnections need to be refractory, such as W or Mo. The disadvantage of W or Mo lies in the high electrical resistivity compared to copper. In order to make use of more conductive metals (e.g., Cu, Au, Ag-Pd) as the interconnections, ceramics that sinter at temperatures below 1 000~ (low temperature) can be used in place of A120 3. The competition between ceramics and polymers for substrates is increasingly keen. Ceramics and polymers are both electrically insulating; ceramics are advantageous in that they tend to have a higher thermal conductivity than polymers; polymers are advantageous in that they tend to have a lower dielectric constant than ceramics. To decrease the dielectric constant, ceramics with pores are being developed, but their brittleness and roughness and low thermal

Overview of Materials for Electronic Packaging

Ceramic powder + vehicle + binder I

Metal powder + glass frit + vehicle

I u

Mixing

Mixing

Sl "ry[

{ Slurry1 I

11

Slip casting (Doctor Blade Hethod)

{Green sheet I

I Punching L

~ Screenprinting , ....

Greensheetwith conductor lines

t

hor pressing

I Greenlaminate i Heating in air

Greenlaminate ' out 1I with organics burnt t Sintering wq.th

cofiring of metal lines

Multilayer ceramic substrate Figure 1 . 1 0

Fabrication process for multilayer ceramic substrates.

conductivity are undesirable. A high thermal conductivity is attractive for heat dissipation; a low dielectric constant is attractive for a smaller capacitive effect hence a smaller signal delay. Metals are attractive for their very high thermal conductivity compared to ceramics and polymers. An interconnection is a conductor line for signal transmission, power, or ground. It is usually in the form of a thick film of thickness > 1 ~tm. It can be on

12

MATERIALS FOR ELECTRONIC PACKAGING

a chip, a substrate or a printed circuit board. The thick film is made by either screen printing or plating. Metals are mostly used for interconnections. The choice of a metal depends on the need for withstanding air oxidation in the heating encountered in subsequent processing, which can be the firing of the green thick film together with the green ceramic substrate (a process known as cofiring, Fig. 1.10). It is during cofiring that bonding and sintering take place. Copper is an excellent conductor, but it oxidizes readily when heated in air. The choice of metal also depends on the temperature encountered in subsequent processing. Refractory metals, such as tungsten and molybdenum, are suitable for interconnections heated to high temperatures ( > 1 000~ for example during A1203 substrate processing. An interlayer dielectric is a dielectric film separating the interconnection layers, such that the two kinds of layers alternate and form a thin film multilayer. The dielectric is a polymer, usually spun on or sprayed; or a ceramic, usually applied by chemical vapor deposition (CVD). The most common multilayer involves polyimide as the dielectric and copper interconnections, plated, sputtered, or electron-beam deposited. A less common multilayer uses SiO2 (CVD) as the dielectric and aluminum as the interconnections. The multilayer sits on a ceramic multilayer substrate, usually A1203, with tungsten interconnections. The use of both types of multilayers together is because the A1203/W multilayer is a much coarser structure, both vertically and horizontally, than the polyimide/Cu multilayer due to the difficulty of controlling the shrinkage during the cofiring of the A1203/W multilayer. The configuration of the two multilayers in a multichip module is illustrated in Figures 1.11 and 1.12 [14]. A thin film multilayer is usually limited by stress and/or cost constraints to two orthogonal signal layers, but there is no limit to the number of interconnection layers in a cofired ceramic multichip module. Signal layers are available in the ceramic module in X, Y, and diagonal directions. This alone can make a 30% shorter signal route in the ceramic, when diagonal corners of a multichip module are connected. The distance an electrical signal travels can be a much greater contributor to signal delay than the difference in dielectric constant [ 15]. Although the thin film multilayer enhances the packing efficiency of the interconnections, its presence makes it impossible to connect the chips mounted on opposite sides of a substrate (a multichip carrier) directly. The indirect connection between the chips on opposite sides of the substrate can be seen in the middle of Figure 1.13(a).

Chip

i

,..,i" i

i

m

i

Cu/polyimide (multil ayer)

i

W/A1203 (multil ayer)

Figure

1.1 1

Structure of a typical multichip module.

Top

metall ization

Overview of Materials for Electronic Packaging

13

CHIP

SIGNAl.

POLYIMIDE ti"'

CERAMIC

l

l

,

I

C

]

Figure 1.1 2 Thin film multilayer on a cofired ceramic multichip module developed by NEC. (Reprinted by permission from NEPCON West 1989 Proceedings, Anaheim CA, p. 655 ~ R. Wayne Johnson and the Reed Exhibition Companies.)

!~~.!

W ir ~ . . I j r nte grated Bond ,~ ~x-x~x~x,~,x~,C ire uits !.x~,,~

nterconnect Metallization

Thin Film Multilayer S truc ture /

. . . . . . Loz]rea Leram]c '

'--"

(a)

Interfaces Integrated Circ u i t ~

Wire ,~'.~~! B o n d ' ~ ~

i

Cofired Ceramic K,...k~~i., ....,..1

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!

Interconnect Metallization

~N~.~ (b)

~]'~~Thermal Interface

Figure 1.13 (a) Thin film multilayers on a double-sided, cofired ceramic carrier. (b) Double-sided multichip module using the cofired ceramic as the interconnection. (Reprinted by permission of the Society for the Advancement of Material and Process Engineering from B. Hargis and K. Weidner, in Proceedings of the 6th International SAMPE Electronics Conference, 1992, pp. 220-232.)

14

MATERIALS FOR ELECTRONIC PACKAGING

The connection is indirect since the interconnection has to go through the thin film multilayer horizontally before going through the substrate vertically. Figure 1.13(b) illustrates the direct connection between the two middle chips when a thin film multilayer is absent [15]. A packaging scheme that takes advantage of both the thin film multilayer and the multilayer substrate involves laser ablating the thin film multilayer under the chip so it is mounted directly onto the substrate. This scheme enhances heat dissipation and allows both power and ground capabilities to be provided directly by the substrate. Moreover, since no signal is routed under the chips, the capacitive charge of the lines with respect to the ground is reduced [5]. A die attach is a material for joining a die (a chip) to a substrate. It can be a metal alloy (a solder paste), a polymeric adhesive (a thermoset or a thermoplast), or a glass. Die attach materials are usually applied by screen printing. A solder is attractive in its high thermal conductivity, which enhances heat dissipation. However, its application requires the use of heat and a flux. The flux subsequently needs to be removed chemically. The defluxing process adds cost and is undesirable to the environment (the ozone layer) due to the chlorinated chemicals used. A polymer or glass has poor thermal conductivity, but this problem can be alleviated by the use of a thermally conductive filler, such as silver particles. A thermoplast provides a reworkable joint, whereas a thermoset does not. Furthermore, a thermoplast is more ductile than a thermoset. Moreover, a solder suffers from its tendency to experience thermal fatigue due to the thermal expansion mismatch between the chip and the substrate and the resulting work hardening and cracking of the solder. In addition, the footprint left by a solder tends to be larger than the footprint left by a polymer, due to the ease of the molten solder to flow. Figures 1.14 and 1.15 [ 16] illustrate the use of solder versus adhesive for die attachment. An encapsulation (Fig. 1.7) is an electrically insulating conformal coating on a chip for protection against moisture and mobile ions. Figure 1.7 shows a dual in-line package (DIP), which is one of the styles of pin-inserting-type packages (Fig. 1.6(a)). An encapsulation can be a polymer (e.g., epoxy, polyimide, polyimide siloxane, silicone gel, Parylene, and benzocyclobutene), which can be filled with SiO2, BN, AIN, or other electrically insulating ceramic particles for decreasing the thermal expansion and increasing the thermal conductivity. The decrease of the Chip Carrier

Low Expansion

Stressed Solder Joints

Substrate

Figure 1 . 1 4

High Expansion

Solderjoint stress due to thermal expansion mismatch between the chip carrier and the substrate. (Reprinted by permission of the Society for the Advancement of Material and Process Engineering from W.-F.A. Su, J.D.B. Smith, and A.H. Long, S A M P E Journal 24(6), 27-32 (1988).)

Overview of Materials for Electronic Packaging

15

Electrically

Conductive Adhesive

Nonconductive Adhesive

Figure 1.1 5 A leadless chip carrier mounted to a printed circuit board using conductive and nonconductive adhesives. (Reprinted by permission of the Society for the Advancement of Material and Process Engineering from W.-F.A. Su, J.D.B. Smith, and A.H. Long, SAMPE Journal 24(6), 27-32 (1988).)

thermal expansion is needed because a neat polymer typically has a much higher coefficient thermal expansion than a semiconductor chip. An encapsulation can also be a ceramic (e.g., SiO 2, Si3Ni4, silicon oxynitride). In the process of electronic packaging, encapsulation is a step performed after both die bonding and wire bonding, and before the packaging using a molding material, as shown in Figure 1.16 [12]. The molded body is illustrated in conjunction with the encapsulation in Figure 1.7. The molding material is typically a polymer, such as epoxy. However, it can also be a ceramic, such as Si3N 4, cordierite (magnesium

Material

Wire bond sequence

Wafer

I Waferseparation i

i Solder preform Polymeradhesive Alwire

Auwire

Piece part

so l

I Die b~

Leadframe

ceramicpackage

lWireb~ I I

Conformal

coating material Metal preform Polymersealant

Lid

Molding compound

1.16 Flow charge of integrated circuit packaging. (Reprinted by permission of ASME from C.P. Wong, Journal of Electronic Packagin9 111(2), 97-107 (1989).) Figure

16

MATERIALS FOR ELECTRONIC PACKAGING

r - i / o PIN WIRE BOND

SIG 2

J,

/r

,

Figure 1.17

1

~

~

KOVAR CAN

[-. 51G

\

,,,

ALUMINA SUBSTRATE FRAME

Cross section of a multichip module of General Electric Company. From [ 10].

silicate), SiO2, and so on. A ceramic is advantageous (compared to a polymer) in its low coefficient of thermal expansion and higher thermal conductivity, but it is much less convenient to apply than a polymer. Figure 1.6 shows the availability of polymer and ceramic molding materials for various styles of packages. A lid is a cover for a chip for physical protection. The chip is typically mounted in a well in a ceramic substrate and the lid covers the well, as illustrated in Figure 1.5, where the well is upside down. A lid is preferably a metal because of the need to dissipate heat. It is typically joined to the ceramic substrate by soldering, using a solder preform (e.g., Au-Sn) shaped like a gasket. Due to the low coefficient of thermal expansion of the ceramic substrate, a metal with a low coefficient of thermal expansion (e.g., Kovar, 54Fe-29Ni-17Co) is used for the lid. For the same reason, Kovar is used for the can (housing or enclosure) in which a substrate is mounted (Fig. 1.17 [ 10]). Although Kovar has a low coefficient of thermal expansion (5.3 x 1 0 - 6 ~ 1 at 20-200~ it suffers from a low thermal conductivity of 17 W m-x K-~. A heat sink is a thermal conductor that serves to conduct (mainly) and radiate heat away from the circuitry. It is typically bonded to a printed circuit board. The thermal resistance of the bond and that of the heat sink itself govern the effectiveness of the heat dissipation. A heat sink that matches the coefficient of thermal expansion of the circuit board is desirable for resistance to thermal cycling. This chapter reviews the status of materials for each of the above applications in electronic packaging.

1.2 Printed Circuit Boards Printed circuit boards, also called printed wiring boards or simply cards, are fabricated by either an additive process or a subtractive process. An additive process is one in which patterns are formed by copper plating. A subtractive

Overview of Materials for Electronic Packaging

17

process is one in which the patterns are formed by etching away the copper foils selectively. The subtractive process is the traditional one (Fig. 1.8). It uses a copperclad laminate as the starting material and suffers from the problem of disposing the etching waste and the undercutting that occurs during etching. The undercutting makes it difficult to control the thickness of the etched line and puts a practical limit of 0.127 mm (5 mils) on lines and spaces [17]. Figures 1.18 through 1.20 [ 17] illustrate an additive process in which a temporary substrate is electroplated to add circuitry and posts. The posts are for electrically connecting adjacent conductor layers. Table 1.1 lists the typical specifications for a high density, multilayer printed circuit board [2]. Table 1.2 summarizes the circuit board requirements and various considerations regarding design, materials, and processes [2]. Table 1.3 lists the materials that are used for the three basic ingredients of a printed circuit board, namely the fabric, the resin, and the metal foil. Although continuous woven fibers are usually used, short fibers can be used instead [18]. Glass fibers are most commonly used for the reinforcement, but Kevlar fibers are increasingly used because Kovar has a low coefficient of thermal expansion (CTE) [18]. A low coefficient of thermal expansion makes Kovar highly effective for lowering the thermal expansion of the circuit board to match the thermal expansion

I i TemporarysubstrateI I I Applyphotoresisti L.,

j

+

I,magecircuitry]

+

L . . . . . . . . . . . . . . . . . .J. . . . . . . . . . .I. .Electr~ ..

+

I'a~ I Figure 1.18

+ ;

I

! i

Circuit carrier with circuitry and posts. (Reprinted by permission of D.R. King and Westinghouse Electric Corporation.)

18

MATERIALSFOR ELECTRONIC PACKAGING I Drill "B" Stage

I f!]

I Prepare Surfaces

I I Lll .!~i~ .................

+

I!~!!~!i~!+ii i ~i !l I

ii~ij I~i!!iiii!iii!!ii~!ii!~l I

I Laminate L'ayers

I

I

I Remove Carriers Figure 1.19 Circuit carrier first lamination. (Reprinted by permission of D.R. King and Westinghouse Electric Corporation.)

IDrill "B" Stage

I t l Ii i iill

I Prepare S!rfaces

I I "'

I

f l

I~i~ ~ ~+1

'[i-i~/:I.............

fiiiiiiiiiiii~iii!ii!it tliill I

!

, ,,;;

;

,!

,I

Laminate Layers

Remove Carriers

Figure 1.20 Circuit carrier second lamination. (Reprinted by permission of D.R. King and Westinghouse Electric Corporation.)

Overview of Materials for Electronic Packaging 19

Typical specifications for a high density, multilayer printed circuit board, from [2]. Table 1.1

Requirement Signal conductor width (mm) Conductor space (mm) Land dimension (mm) Lead insertion hole Via hole Width of footprint (mm) Space of footprint (mm) No. of Signal Layers Signal layer-to-layer space (mm) Signal-ground layer space (mm) Tolerance of layer-to-layer space (mm) Board thickness (mm) Hole diameter before plating (mm) Lead insertion hole Via hole Aspect ratio before plating Misalignment external-to-internal layer (mm) Misalignment hole-to-land (mm) Board size (mm) Grid (mm) No. of traces between grid (line/G)

Specifications <0.13 0.01-0.15 1.0 <0.6 0.25 0.15 2-15 0.05-0.1 0.2-0.3 0.05 0.5-8 0.9 <0.6 2-20 0.05 0.05 500 x 600 2.54; 2.5; 0.5; 0.05; 0.625 > 2(1.27) > 4(2.54)

of the chip or the chip carrier. Epoxy is most commonly used for the resin, but polyimide is increasingly used because of its superior temperature resistance. Copper is most commonly used for the metal foil, but it suffers from a high coefficient of thermal expansion; metal composites of low thermal expansion (e.g., copper-clad Invar, copper-clad molybdenum, and molybdenum-copper composites) are increasingly used [13]. Printed circuit boards suffer from failure upon temperature or humidity cycling. Debonding occurs at the fiber-matrix interface, especially in the part of the board near plated-through holes (PTH) (see Figure 1.4). Another problem is due to the tendency for copper ions from the copper PTH to move along the fiber surface, causing an electrical short between the PTH and a conductor line or even between one PTH and another PTH via the conductor line in between. Copper filaments form on the fiber surface as a result of the copper migration.

1.3 Substrates A substrate, also called a chip carrier, provides one surface or two opposing surfaces for chip(s) to be mounted and for interconnections to be drawn. A substrate usually consists of multiple layers of a dielectric on which interconnections are

20

MATERIALS FOR ELECTRONIC PACKAGING

Table 1.2

Printed wiring board requirements and design/manufacture considerations,

from [2]. Requirements

Materials and process considerations

Design considerations

Electrical properties

Wiring dimensions:

Tolerances

Low conductor resistance High insulation resistance Characteristic impedance Low crosstalk Electromagnetic shielding

Fine line width Small line space Large conductor Small grid dimension Small hole diameter Large layer-to-layer spacing

Line width Line space Layer-to-layer spacing Hole position Pattern-to-hole position Layer-to-layer position

Wiring capability

Construction of board

Materials

Enlargement of wiring volume High density wiring

Large thickness High count of layers Large board size Landless PTH Interstitial via hole

High heat resistance laminate Adhesion stability Dimension-stabilized laminate Low CTE laminate Metal core/base material High resolution photoresist Photosensitized solder resist

Physical and chemical properties

Wiring of package

Process technology

Solderability Solder temperature resistance Warp and twist Dimensional stability Low coefficient of thermal expansion Flame retardation Thermal conductivity

Short length wiring Control of parallel wiring Oblique wiring Surface mounting Double-side mounting

Exposure by collimated light Vacuum lamination Multistep and multibit drilling Desmearing and cleaning Highthrow plating High physical property of plating

Table 1.3

Basic ingredients of a printed circuit board.

Fabrics

Resins

Foil layers

E-glass S2-glass Quartz Kevlar

Polyimide Epoxy Teflon Cyanate ester

Copper Copper-Invar-copper Mo-30Cu

Overview of Materials for Electronic Packaging

21

drawn. When more than one chip is mounted on a substrate, the substrate is called a multichip module (MCM). Ceramics are predominantly used for substrates. The fabrication of a ceramic substrate (Fig. 1.10) involves (1) casting (or tape casting) of a ceramic powder slurry (with a polymeric binder and a plasticizer) using a doctor blade to form a green sheet; (2) drying the sheet; (3) punching the sheet to form via holes; (4) screen printing a metal powder slurry (with a glass binder) on the sheet to form interconnection lines and via fill metallizations; (5), hot pressing a stack of such sheets to form an unfired laminate, a monolith; (6) heating in air to burn out the organic components; and (7) sintering the ceramic with simultaneous firing (cofiring) of the metal lines to form a multilayer ceramic substrate. An example of the ceramic slurry formulation is shown in Table 1.4 [19]. The ceramic slurry (also called a slip) is usually cast onto a support film by a doctor blade or related process and dried with heat to remove the solvents, leaving behind a flexible dielectric tape [20]. The mean pore diameter of a green tape decreases as the laminating pressure increases. As a consequence, the shrinkage of the tape during subsequent sintering decreases as the laminating pressure increases; see Figure 1.21 [20]. The difficulty in controlling the shrinkage during cofiring is a major problem that limits the dimensional precision of the interconnection patterns in a cofired multilayer substrate. The problem is most severe when the substrate area is large. The typical shrinkage tolerance is about _+0.2%. For example, a 127 mm x 127 mm (5 in. x 5 in.) substrate with a shrinkage tolerance of _+0.2% would have a linear inplane true position location error of _+360 ~m ( ~ _+ 14 mils) from points at either end of the substrate diagonal [20]. Areas of high conductor metal density often lead to warping and flaw generation during firing, since the metal densities at different temperatures and rates than the surrounding ceramic [21]. When unlike materials are combined, homogeneous densification is difficult

Table 1.4

Materials and milling procedure for the slurry for casting A1203 tapes for substrates, from [16]. Process step

Material

Function

Alumina powder Magnesium oxide

Substrate material Grain growth inhibitor

Menhaden fish oil Trichloroethylene or ethanol Polyvinylbutyral Polyethyleneglycol Diocytylphthalate

Deflocculant Solvent

Parts per weight

100.0 0.3

Mill for 24 h

Add to above and mill for 24 h

Binder Plasticizer Plasticizer

1.7 54.0 4.0 4.3 3.6

22

MATERIALS FOR ELECTRONIC PACKAGING

12.2

,-, 12.0

~, 11.8

._c

--__+

_t.-- 11.6 CO I

X 11.4 11.2 i.

[ 2.0

! 2.5

; 3.0 Laminating

1 3.5 Pressure

t 4.0

1 4.5

1 5.0

(kpsi)

Figure 1.21 Linear shrinkage during firing of a dielectric tape as a function of lamination pressure. (Reprinted by permission of the American Ceramic Society from T. Sawhill, Ceramic Engineering Science Proceedings 9(11/12), 1603-1617, (1988).)

to achieve [21]. Unlike materials are combined when high dielectric constant materials and low dielectric constant materials are used to create buried capacitors, or when layers of resistor materials are used to create buried resistors. One way of alleviating densification problems is to have the shrinkage limited to the direction perpendicular to the laminate. This can be achieved by applying a pressure in the direction perpendicular to the laminate during sintering--pressure assisted sintering--or by adhering a constraining layer to each side of the laminate and sintering under constraint without pressure--pressureless constrained sintering [21]. Table 1.5 [22] lists the ceramic materials used for substrates. The current material is almost exclusively alumina, which is available at different levels of purity. A higher alumina content (the balance is mainly SiO2), makes for a higher dielectric constant, a higher thermal conductivity, and a higher thermal expansion. Compared to other ceramics, such as most of those listed as future materials in Table 1.5, alumina suffers from a low thermal conductivity and a high dielectric constant. Another disadvantage of alumina is its high sintering temperature (above 1 000~ this means that any cofired interconnections must be refractory metals, such as W or Mo, which are relatively high in electrical resistivity. The use of Cu, Au, and other more conductive but lower temperature metals requires a ceramic substrate that sinters below 1 000~ Tables 1.6 and 1.7 list the low temperature ceramic materials produced by a number of companies, together with their firing conditions and properties [20]. Many of these low temperature ceramics have the additional advantage of a low dielectric constant (Table 1.7). One of the low temperature ceramic systems of Table 1.6 is NEC's lead

Overview of Materials for Electronic Packaging 23

Table

1.$

Ceramic materials for substrates, from [19].

Ceramics

Current 96% alumina, 4% glass 92% alumina, 8 % glass 55 % alumina, 45% glass

Dielectric

Thermal conductivity

constant

(Wm -1K -l)

Thermal expansion coefficient (10 -6 ~ -1)

Strength (MPa)

Delay time (10 -9 s/in.)

10.2

20.9

7.1

276

0.27

9.5

16.7

6.9

315

0.26

7.5

4.2

4.2

296

0.24

260 33.5 340 10

4.4 3.0 3.1 4.5

276 586 400 165

0.23 0.21 0.21

10

1.6

103

0.21

Future AIN 8.8 Si3N4 6.0 SiC 40 Mullite 6.2 (3A1203"2SIO2) Cordierite 6.0 (2MgO. 2A1203. 5SIO2)

borosilicate glass filled with alumina particles. It is formed by sintering at 900~ a mixture of the glass powder and the alumina powder. The resulting composite is known as a glass ceramic. The properties of the sintered substrate material are listed in Table 1.8. The geometry of the multilayer substrate, together with Au interconnections and vias, is described in Table 1.9 [23]. Instead of Al20 3, cordierite or quartz glass (SiO2) may be used as fillers in the borosilicate glass matrix (Table 1.6) to provide composites of lower dielectric constants [24]. Since air has a dielectric constant of 1, a porous ceramic has a low dielectric constant and therefore is attractive for use as a substrate. However, the porosity causes problems with conduction line integrity and thermal conductivity [25]. Besides a low dielectric constant, a substrate requires a high thermal conductivity. As shown in Table 1.5, A1N and SiC have much higher thermal conductivity than alumina (A1203). In particular, A1N has an added advantage of a coefficient of thermal expansion (4.4 x 10 -6 ~ -1) that is close to silicon (4.1 x 10 -6 ~ Small concentrations (0.5 wt.%) of CaCO3 may be added to A1N as a sintering aid, so the sintering temperature can be ~< 1 650~ [26]. The CazSiAI20 v phase should be avoided in A1N due to its detrimental effect on the thermal conductivity [26]. Because A1N of high thermal conductivity has few grain boundary phases, metallizations which involve ingredients adhering to the grain boundary phases in the substrate need to be modified from the A1203 case to the A1N case [27]. Silicon is also used as a substrate of relatively high thermal conductivity; it exhibits perfect CTE match with silicon chips.

G,

Table 1.6

Chemistries and firing conditions of low temperature ceramic systems, from [17].

B

Firing temperature Supplier

Matrix

Asahi Glass Du Pont Fujitsu Hitachi IBM

BaO-aluminoborosilicate Aluminoborosilicate Borosilicate Pb-aluminoborosilicate Cordierite 8-Spodumene

Matsushita Murata Narumi NEC

Mg0-Ca0-aluminoborosilicate

NGK Taiyo Yuden Toshiba

BaO, SiO,, A1,03, CaO, B 2 0 3 CaO-aluminoborosilicate Pb-borosilicate

ZnO+ordierite AI,03, CaO, SiO,, MgO, B 2 0 3 BaO, SnO,, TiO,, B 2 0 3

Fillers

AI2O3, forsterite Proprietary A1203 A1,03, CaZrO, None None AI2O3 None A1203

Cordierite SiOz None None None

("c) 85Ck900 850 900 850 925-1050 85Ck990 1000 95&1000 880 900 900 900 9OCk1000 90Ck1000 85Ck1050

rn r

Atmosphere

Air Air Reducing Air Airlneutral Girlneutral Reducing Reducing Air Air Air Air Air Reducing Air

rn

9 w

e

n

9

n

2

0

6

Overview of Maferials for Electronic Packaging 25

Table 1.7'

Properties of low temperature ceramic systems, from [17].

Supplier Asahi Glass Du Pont Fujitsu Hitachi IBM Matsushita Murata Narumi NEC

NGK Taiyo Yuden Toshiba

Dielectric constant 5.0-6.5 7.8 5.6 9-12 5.3-5.7 5.0-6.5 7.1 6.1 7.7 7.8 5.0 3.9 5.2-5.5 6.7 7-13

Tan 6 (%)

Thermal expansion coefficient (10 -6 ~ )

0.08-0.2 0.2

Shrinkage (%)

3.8-6.8 7.9 4.0

0.1-0.3

12 16 16

Shrinkage tolerance (%) +_0.2

2.4-5.5 2.0-8.3 0.25 0.07 0.03 0.3 0.5 0.3 0.1 0.1 0.05-0.08

8 5.5 4.2 7.9 1.9 1.5-3 4.8

13.5 16 13 13.7 13.9

<0.3 <0.3 <0.3

10.2 <20

Table 1.8 Properties of an NEC glass ceramic substrate, from [20]. Sintering temperature Sintered density Flexural strength Camber Roughness average Dielectric constant (1 MHz) Dissipation factor (1 MHz) Insulation resistance (50 V DC) Leakage current (20 V DC) Thermal expansion coefficient Linear shrinkage Shrinkage tolerance

900~ 3.15 g/cm 3 3000 kg/cm2 300/tm/225 mm 0.3/~m 7.8 <0.3% > 10 x4 ~ cm <1 /tA 4.2 • 10 -6 *C- t 13.0% <0.3%

BeO has a high thermal conductivity of 370 W m - 1 K - x [28], but it is toxic. On the other hand, diamond (ideally of thermal conductivity 2 000 W m - 1 K-1) is now available in freestanding, large area films, as prepared by chemical vapor deposition (CVD). The thermal conductivity of CVD diamond is 1300-1 500 W m - 1 K - 1 ; the dielectric constant is 5.6; the thermal expansion coefficient is 2.0 x 10 -6 ~ at 100~ [29]. D i a m o n d is also available as a CVD film on a substrate, such as AI20 3 or an aluminum-matrix composite [30].

2b

MATERIALS FOR ELECTRONIC PACKAGING

Table 1.9

Specifications for a glass ceramic multilayer substrate, from [20]. Substrate Size Thickness Line width Via hole diameter Number of layers Conductive layers Conductor Material Resistivity Green sheet thickness I/O pin Number Pitch Bonding strength

225 mm • 225 mm 5.5 mm 200/~m 200/~m 78 13 Au 3.0 #f~ cm 110 t~m 11 540 1.8 mm > 3 kg

Metals are not widely used for substrates because they are electrical conductors; when metals are chosen it is for their high thermal conductivity. Metals are mainly used in high power electronics, where heat dissipation is particularly significant. Aluminum is the commonest metal substrate; copper is sometimes used because it has a higher thermal conductivity than aluminum, but it suffers from a high density. A disadvantage of both aluminum and copper is a high thermal 24 r20

o

0

'~~'~'~'~,~.~

v toO ~ ffl em X m

e0 I0

=,==.

I 0

0

0

1

5

1_

10

11

I1

15

1

20

. a ~I

25

~r L

30

_j.._ . I 35

40

. 1

.

45

.

.

.

.

I

50

1

55

SiC content (vol.%)

Figure 1.22

Coefficient of thermal expansion (10 -6 ~ of silicon carbide particle reinforced aluminum as a function of SiC volume fraction. (Reprinted by permission of the Society for the Advancement of Material and Process Engineering from C. Thaw, R. Minet, J. Zemany, and C. Zweben, S A M P E Journal 23(6), 40-43 (1987).)

Overview of Materials for Electronic Packaging 2 7

200

-

180 160, '~

140 =

120k .z ~

100 L | j

o'-

80 ~-

E

60,

to

,-

l

Iu

~

40 ~

ti

20 ? i 0

~--

0

x

i

5

10

__L~

15

: J

20

:

'

..1,

l

1

25

30

35

40

.....

1

45

9

1

50

55

1

SiC content (vol.%)

Figure 1 . 2 3 Thermal conductivity (W m-1 K-1) of silicon carbide particle reinforced aluminum as a function of SiC volume fraction. (Reprinted by permission of the Society for the Advancement of Material and Process Engineering from C. Thaw, R. Minet, J. Zemany, and C. Zweben, S A M P E Journal 23(6), 40-43 (1987).)

expansion coefficient, undesirable for tight dimensional control of microwave interconnections and for tolerance to thermal cycling. This problem can be alleviated by the addition of low thermal expansion fillers to the metals to form metal-matrix composites of low thermal expansion. The fillers can be in the form of particles, short fibers or continuous fibers. Silicon carbide (SIC) particles are most commonly used as a filler for aluminum. Although the addition of SiC particles decreases the coefficient of thermal expansion (Fig. 1.22), it also decreases the thermal conductivity (Fig. 1.23) [31]. By using A1N particles in place of SiC particles, a slightly higher thermal conductivity can be obtained, although the A1/AIN composite still has a lower thermal conductivity than A1. Other fillers are SiC whiskers and Si particles [32]. For copper as the matrix, continuous carbon fibers are used as the filler for decreasing the thermal expansion coefficient. Highly graphitic pitch-based carbon fibers have thermal conductivities exceeding that of copper, so their use in copper results in a copper-matrix composite that is even more conductive than copper.

1.4 Interconnections Interconnections constitute the communications bottleneck of electronic digital systems. The two main types of interconnections are electrical and optical. At present all interconnections are electrical, but optical interconnections are under

28

MATERIALS FOR ELECTRONIC PACKAGING

development because of their potentially high communication rate and low power dissipation [33]. Electrical interconnections are electrical conductors. Metals are almost exclusively used as the conducting material, although silicides, superconductors [33], conductor-filled polymers, and conducting polymers are being developed for interconnections. The metal conductor can be in the form of a thin film, a thick film, or a bulk material, depending on the application. On-chip interconnections are thin films; chip-to-chip interconnections are thin or thick films; chip-to-card, card-to-card, and card-to-backplane interconnections are bulk materials. Thin films are deposited by plating, sputtering, evaporation, or CVD. Thick films are usually glass-metal composites formed by screen printing of a paste. The paste mainly contains metal particles, glass particles (frit), and a vehicle. The vehicle consists of a polymer (e.g., ethyl cellulose) and a volatile solvent (e.g., terpineol or isobutyl alcohol). The glass (a silicate) is the binder, which serves to bond the film to the substrate and to bond the metal particles together. After firing (sintering of the metal and flow of the binder), the glass mainly resides at the interface between the film and the substrate. Fingers of the glass extend to the film surface, which is mainly the metal. The metals can be Au, Ag, Pd, Pt, W, Mo, Cu, Ni, and so on. For example, Ag-Pd (in the ratio 8.65:1) is commonly used [34]. The Pd in Ag-Pd serves to reduce the silver migration, which occurs in response to voltage and humidity. Due to the presence of glass, which is insulating, the resistivity of a thick film is between two and four times the bulk metal resistivities [35]. The removal of the glass is thus desirable. This can be achieved by using, instead of a metal-glass paste, a silver-based titanium-containing alloy particle paste (without glass) that is typically used as an active brazing alloy paste for ceramic bonding. The reaction between titanium in the film and the ceramic substrate provides good film-substrate bonding. The film-substrate adhesion is much stronger for the all-metal (no glass) film compared to the metal-glass film. Moreover, for the all-metal film, the electrical resistivity is lower and the porosity is much lower [36]. Plating [37], sputtering and evaporation can also be used to form all-metal films, but their processing is not as simple as the screen printing of a paste. The different metals differ in their firing conditions, solderability, resistivity, and coefficient of thermal expansion. For example, a typical Ag-Pd thick film has a resistivity of 10-20 m~/sq, and a fired film thickness of 15 #m; it needs a peak firing temperature of 850~ and the paste is thixotropic, with a viscosity ranging from 1700 to 5230 P [38]. The solderability is of concern because leads (e.g., tinned copper wires) are soldered on to the thick film conductor. The strength of the soldered joint decreases upon aging at 130~ as in the case of Sn-Pb solder in conjunction with Ag-Pd thick film. This degradation is related to the formation of intermetallic compounds (Pd3Sn, PdzSn, Pd3Sn2, PdSn, Pd3Pb, AgsSn, and Ag3Sn) [34]. The width of a thick film conductor line made by screen printing is typically 100 #m or more. In order to have a smaller width, the line may be thin film etched by coating the thick film with a photoresist. To obtain an even coating of

Overview of Materials for Electronic Packaging

29

photoresist, the thick film must have a smooth surface, which may be obtained by using monodispersed spheroidal metal particles as the conductor. Such etchable thick films typically have a line and space resolution of 20/~m and a fired thickness of 3-4/~m [39]. For dense films of thickness less than 2/~m, the use of metal particles is not feasible. Instead of metal particles, organometallics containing no particles may be used. Organometallics such as organogold compounds decompose on firing to give a metal film. Organometallic inks are screen printable like particulate inks. Films as thin as 0.5/~m or less, with conductivities better than 40 mf~/sq, and line resolutions of 10/~m, have been achieved using organometallics [38]. Chip-to-card, card-to-card, and card-to-backplane interconnections can be soldered joints (usually applied by screen printing), conducting adhesive joints (applied by screen printing), or pressure contacts. Soldered joints are most commonly used, but they suffer from thermal fatigue associated with work hardening [40-42]; it is convenient to separate the joined components; the joints need to be heated to melt the solder; and the defluxing chemicals present an environmental hazard [43,44]. Thermal fatigue may be alleviated by polymer fillings (e.g., epoxy) in the space between adjacent joints of a solder array, but this makes the interconnections less reworkable and heat dissipation is less efficient. Most solder alloys contain lead. Due to the hazardous nature of lead, no-lead solders are rapidly gaining importance, but there is not much information on them and this hinders their practical use. Conducting adhesive joints are increasingly used as a result of the relatively high processing cost associated with soldering, but like soldered joints, they do not allow the joined components to be separated conveniently. Furthermore, the electrical resistivity of conducting adhesives is high compared to solders and the high conducting filler volume fraction (e.g., 40%) in the conducting adhesive makes the adhesive brittle. Thus, if a conducting adhesive is used in place of a solder, the mechanical integrity of the interconnections must be enhanced by the use of an encapsulation (a polymer), which covers the joined components and acts like a binder that helps to hold the joined components together. On the other hand, the use of an encapsulation will render the interconnections not reworkable. Without the encapsulation, the joined components (e.g., a chip on a card) tend to debond upon thermal cycling, which leads to thermal fatigue due to the thermal expansion mismatch between the components. With encapsulation, fatigue failure is replaced by warping, which is less troublesome than debonding. For separable connections, pressure contacts are used. A pressure contact material can be in the form of a springy metal wire button (made from randomly intertwined wires) [45,46], or a metal-filled elastomer [47,48]. The main drawback of these separable connection materials lies in their large dimensions, which make them unsuitable for small contact pads. For example, wire buttons of diameter 0.020 in. are located on a 0.050 in. pitch [45]. This problem can be alleviated by the use of anisotropic (z-axis) elastomeric conductors which allow conduction only in one direction (i.e., the z-axis perpendicular to the film) [49]. By using a single piece of an anisotropic conductor, a large number of interconnec-

30

MATERIALS FOR ELECTRONIC PACKAGING

tions can be made. A similar advantage can be reached by using an anisotropic (z-axis) conducting adhesive [50,51]. Another drawback of pressure contacts lies in the need to have a clamp or similar device for the application of pressure. Corrosion [52] is a problem for interconnections in general, especially when the contact resistivity is important. Corrosion can be oxidative corrosion (e.g., Cu) or fretting corrosion (e.g., Sn [53]).

1.5 Die Attach A die (chip) is attached to a substrate by using a solder, a polymeric adhesive, or a glass. Depending on the configuration of the attachment, the die attach material may be electrically insulating or electrically conducting. In either case, a high thermal conductivity in the die attach is preferred for heat dissipation. The conducting filler volume fraction of a thermally conducting adhesive is low compared to that of an electrically conducting adhesive used as interconnections. This means the mechanical properties of a thermally conducting adhesive are superior to the mechanical properties of an electrically conducting adhesive. Nevertheless, a compliant (low modulus) die attach is preferred (especially for large area dies) in order to minimize the interfacial stress, which can cause die cracking [48,54-56]. A solder is a eutectic alloy, such as Au-Si. A die attach alloy is either a solder paste amenable to screen printing, or a solder preform (sheet). The main problem with the use of a solder is the die stress due to the thermal expansion mismatch among the die, the solder, and the substrate. Furthermore, the high solidification temperature of Au-Si (365~ aggravates the stress problem. Nevertheless, solders are widely used for die attachment. The addition of carbon fibers to a solder preform serves to decrease the thermal expansion of the solder preform, thus alleviating the mismatch problem [57]. The use of rapidly solidified solder foils having a fine, homogeneous microstructure also improves the resistance to thermal fatigue failure [58]. Improvements in the creep resistance and stress fatigue resistance of solder alloys can be obtained by dispersion strengthening using particles (formed in situ by rapid solidification of ternary solder alloys) of size 0.1-1.0/~m [59,60]. Higher soldering temperatures create more severe thermal stresses after cooling. One way to have a low bonding temperature and a high bond reflow temperature is low temperature transient liquid phase (LTTLP) bonding, which occurs when parts of the members to be joined dissolve in the solder alloy and cause isothermal solidification of the bond. The bonding temperature by LTTLP is 60-160~ [61]. A polymeric adhesive for die attach can be a thermoset (e.g., epoxy) or a thermoplast (e.g., polyimidesiloxane). It has the advantage of low processing temperature and low cost, but it suffers from low thermal stability. Moreover, an adhesive in paste form suffers from voids, due to the solvents and binders. In contrast to thermosets, thermoplasts [62,63] have the advantage of providing reworkable joints. Reworkability is particularly important for multichip modules,

Overview of/Haferials for Elecfronic Packaging

31

in which defective chips need to be removable for replacement due to the high cost of the module compared to the chips. The rework temperature should be less than the solder reflow temperature (180~ for 63Sn-37Pb). Since no curing is involved with the use of a thermoplast, processing time is a few minutes, compared to hours with epoxies. However, the curing time of a thermoset (e.g., epoxy) can be decreased to ~ 10 s by the use of ultraviolet (UV) radiation [ 16,64]. Adhesives are available in the form of a paste or a film. The advantages of a film, as opposed to a paste, include precision placement and dimensioning of the adhesive, easy placement of the adhesive, and less mess. However, film adhesives are used mainly in large area substrate attachment rather than die attachment [54], and are used for heat sink attachment to a printed circuit board [65]. In order to enhance the thermal conductivity, polymeric die attach adhesives are filled with thermally conducting particles that are electrically insulating (e.g., A1203, BeO, BN, mica, and diamond) or those that are electrically conducting (e.g., Ag and Ni). A glass adhesive works by the reaction of the glass (e.g., lead borate) in the paste with the die backside [66,67]. The glass is typically filled with silver particles for thermal conductivity. After drying and organic burnout, the silver-glass material is completely inorganic, consisting of approximately 80 wt.% silver and 20 wt.% glass. In contrast, the wet paste consists of 66.4 wt.% silver, 16.6 wt.% glass, 1 wt.% resin and 16 wt.% solvent. The organic burnout helps to avoid outgassing, moisture problems, and the thermal decomposition that occurs with polymeric adhesives at elevated temperatures [66].

1.6 Encapsulation The following properties are preferred for an encapsulant: 9 high dielectric strength 9 high electrical resistivity 9 high thermal conductivity 9 low dielectric constant 9 low loss tangent 9 thermal stability 9 low thermal expansion coefficient 9 good adhesion to the chip 9 conformability 9 low tensile modulus 9 solvent resistance 9 low moisture absorption 9 high purity Both polymers and ceramics are used as encapsulants. Ceramic encapsulants (e.g., SiO 2 and SiaN4) typically have higher dielectric strength, higher dielectric constant, higher thermal conductivity, superior thermal stability, lower thermal expansion coefficient, higher tensile strength, higher tensile modulus, and lower ultimate elongation than the polymeric encapsulants. Since ceramic encapsulants

3

3 rn w

Table 1.I0

?

Encapsulants, from [69].

V,

Disadvantages

s! 71

Muterials

Application

Advantages

rn P

Epoxies

Normal dispensing

Good solvent resistance Excellent mechanical strength

Not repairable Marginal electrical performance

2

Polyimides

Normal dispensing (spin coat)

Good solvent resistance

High temperature cure

Pn

Thermally stable

Not repairable High stress

n

Good solvent resistance

Thin film only

Conformal coating

Not repairable

Polyxylylene (Parylene, Union Carbide)

Thermal deposition (reactor)

Silicone-polyimides

Normal dispensing

Less stress than polyimide Better solvent resistance than silicone

High stress Thin film only

Silicones (RTV gel)

Normal dispensing

Good temperature cycling Good electrical properties Very low modulus

Weak solvent resistance Low mechanical strength

Benzocyclobutene

Normal dispensing

Good solvent resistance Low moisture absorption Low dielectric constant Low modulus

High temperature cure

2

6

Overview of Materials for Electronic Packaging

T a b l e 1.1 1

33

R o o m t e m p e r a t u r e coefficient of t h e r m a l

expansion (CTE) and modulus of unfilled polymeric encapsulants, from [68]. Encapsulants

CTE (ppm/~

Epoxy Polyimide Parylene Silicone-polyimide Silicone gel Benzocyclobutene

~40-80 ~ 3-80 ~ 35-40 ~ 5-100 --~200-1000 ~ 65

Modulus (psi) -,~ 1-5 • 10 6 ~ 1 x 10 6 --~0.4 x 106 ~ 0.4 x 106 -~0--400 -,~1 x 106

are not 100% free of pinholes or cracks, a polymeric conformal coating is usually used as the encapsulation [68]. The polymers used for encapsulation include thermoplasts (e.g., polyimide siloxane and Parylene) and thermosets (e.g., silicone and polyimide). The advantages and disadvantages of various polymers are listed in Table 1.10 [69]. A low coefficient of thermal expansion (CTE) and a low modulus help reduce the thermal stress. Table 1.11 [68] shows that silicone has a high CTE, polyimide has a relatively low CTE, and polyimide siloxane (a copolymer of silicone and polyimide) [70-72] has an intermediate CTE. However, within each type of polymer, the polymer can be tailored chemically so that its CTE can be judiciously chosen to have a value within a large range [73,74]. Although silicone has a high CTE, the thermal stress remains sufficiently low because of silicone's low modulus; it is available in the form of a heat-curable gel or a room temperature cure elastomer [69,75]. Due to its softness, silicone cannot provide mechanical protection.

1.7 Interlayer Dielectrics The material property requirements of an interlayer dielectric are similar to those of an encapsulant, but also relevant are the degree of planarization, the patternability, and the thin film electrical properties. To get the interlayer dielectric to surround the interconnections and form a multilayer, either (1) the interconnection layer is patterned before the dielectric is deposited, or (2) the dielectric layer is patterned before the interconnections are deposited. The patterning of an interlayer dielectric is achieved by reactive ion etching, plasma etching, or laser etching. The use of a photosensitive polymer simplifies the process by obviating the need for a photoresist [76-78]. Photosensitive polymer methods (e.g., photosensitive polyimide) rely on the effect of ultraviolet light on the solubility of the polymer (before or after polymerization) in a certain solvent. Ultraviolet light is shone through a mask to project the desired pattern onto the appropriate surface; the pattern is subsequently revealed by solvent treatment. An interlayer dielectric is most commonly a polymer, such as polyimide [73,79,80] and polyimide siloxane [70]. Polyimide is attractive because of its high thermal stability (Tg > 400~ low dielectric constant (e ~ 3.2) and ease of planarization. However, polyimide suffers

34

MATERIALS FOR ELECTRONIC PACKAGING

from a high processing temperature and a high modulus. Therefore, polyimide siloxane is being considered as a compromise. To further decrease the dielectric constant of a polymer, hollow glass spheres or pores (10-100 nm, obtained from a thermally decomposing polymer particulate phase) can be incorporated in the polymer. Polymer films tend to exhibit CTE anisotropy, due to the preferred orientation of the polymer chains in the film. The degree of anisotropy varies with the curing conditions. Because an interlayer dielectric is used together with metal interconnections in a multilayer, the adhesion between a dielectric and a metal is relevant [81,82]; in most cases the adhesion is poor. It may be improved by surface treatment (e.g., plasma treatment) of the polymer and by judicious choice of the functional groups in the polymer.

1 . 8 H e a t Sinks Material requirements for heat sinks include the following: 9 high thermal conductivity 9 low coefficient of thermal expansion (CTE) 9 low density (for aerospace electronics) Copper is the traditional heat sink material, but it suffers from a high CTE and a high density. Aluminum is also a traditional heat sink material, but it suffers from a high CTE and it is not as thermally conductive as copper. Composite materials are increasingly being used because they provide properties which most

Table

1.12

Properties ofcomposite heat sink materials compared to conventional metals.

Composite

85Mo-15Cu 60AI-40Si Cu-Invar-Cu a Cu-Mo-Cu a Cu/Cf b

Thermal conductivity ( W m -1 K -1)

0.44 0.3 164 208 737-750

CTE (10 -6 ~

7.0 13.0 6.4 5.7

Density (g/cm 3)

Reference

10.01 2.53 8.40 9.84 5.6

83 83 85 85 85

1.78-1.82 1.78-1.82 1.8 8.96 2.70

84 84 85 85 85

C/Cf: b

x-direction z-direction PI/Cf Cu A1

400-483 46-50 550 400 220

16-17 22-24

"Sandwich composite. bTwo-dimensional laminate with carbon fibers (Cf)of thermal conductivity 1 100 W m -1 K-1.

Overview of Materials for Electronic Packaging 35

single-component materials cannot provide. Composite heat sink materials include metal-matrix composites (e.g., Cu-W [83,84], C u - M o [84-1, and AI-Si [84]), carbon-matrix carbon fiber composites [85], and polymer-matrix carbon fiber composites [86]. Carbon fibers are an attractive filler because highly graphitic fibers exhibit a thermal conductivity as high as 1 100 W m-~ K-~, while having a low CTE and a low density. Table 1.12 lists the properties of some composite heat sink materials. Some of these composites exhibit thermal conductivities exceeding that of copper, while having densities much lower than that of copper. Better even than composites, diamond's outstandingly high thermal conductivity (2 000 W m-~ K-~) finds it a number of electronic applications [87,88-1, but its high price does limit their number. The thermal contact resistivity between the heat sink and the circuit board should be small. This is achieved by the use of a thermally conductive adhesive, a thermal grease, or an elastomeric conductor at the interface. For this purpose, it also helps to use a heat sink material that is not covered by an insulating film (e.g., an oxide). Metals are usually covered with an insulating oxide film, whereas carbon is not. This gives another benefit for the use of carbon fiber composites for heat sinks.

1.9 Electromagnetic Interference Shielding With the increasing sensitivity and abundance of electronics, electromagnetic interference (EMI) shielding is receiving more attention. The shielding material is an electrical conductor used in the form of an enclosure or housing for a module or a system, and in the form of a lid for a chip package. Metals in the form of sheets (e.g., A1) or plated coatings (e.g., Ni and Cu [89,90]) are traditionally used for enclosures. However, metals are not easily moldable, in contrast to polymers. Leaks in the shielding may occur at the joints between the metal sheets. Coatings are prone to damage by scratching and wear. Therefore, electrically conducting polymer-matrix composites are increasingly used for enclosures [91]. By using metallized ceramic microballoons as a conductive filler in a polymer, the composite has the added attraction of a very low density [92]. In general, the conductive filler can be in the form of particles, flakes, short fibers, or continuous fibers. Long fibers are more effective than short fibers. Metal fillers (e.g., A1 and Cu) are most commonly used [93-95], but metal-coated carbon fibers are increasingly used [96]. The mechanism of shielding includes absorption and reflection; it depends on the material and the frequency of the radiation. Increasing the volume fraction of the conductive filler the shielding effectiveness of the composite. However, a high filler content may result in a low tensile strength in the composite, so there is a compromise between its electrical and mechanical properties [97]. For the lid of a chip package, low thermal expansion alloys are used for the purpose of shielding. The most commonly used alloy is Kovar, which has a low coefficient of thermal expansion compatible with the low coefficient of the chip.

36

MATERIALS FOR ELECTRONIC PACKAGING

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MATERIALS FOR ELECTRONIC PACKAGING

60. C.G. Kuo, S.M.L. Sastry, and K.L. Jerina, in Proc. 1st Int. Symp. Microstructures and Mechanical Properties of Aging Materials, 1993, pp. 417-424. 61. J.W. Roman and T.W. Eagar, ISHM S),mp. Proc., Oct. 1992, pp. 1-6. 62. A.A. Shores, in Proc. 39th Electronic Components Cop!f., IEEE, 1989, pp. 891-895. 63. C.J. Lee and J. Chang, in Proc. 1991 hit. Symp. Microelectronics, ISHM, Reston VA, 1991. 64. C.J. Lee and K. Sherman, in Proc. 6th Int. SAMPE Electronics Conf., 1992, pp. 500-507. 65. C. Dominic, Electronics 33(4), 48-49 (1987). 66. E. Razon and Y. Tal, Hybrid Circuit Technol. 6(12), 17-20 (1989). 67. N.M. Davey and F.W. Wiese, Jr., Proc. 1986 Int. Symp. Microelectronics, ISHM, Reston VA, 1986, pp. 665-674. 68. C.P. Wong, J. Mater. Res. 5(4), 795-800 (1990). 69. C.P. Wong, J.M. Segelken, and J.W. Balde, IEEE Trans. Components, Hybrids, and Manuf. Technol. 12(4), 421-425 (1989). 70. C.J. Lee, G. Fabinowski, R.J. Jaccodine, S.P. Murarka, and F. Sun, in Microelectronic Packagin9 Technology, Proc. 2nd A S M Int. Electronic Materials and Processing Congress, Philadelphia PA, Apr. 1989, edited by W.T. Shieh, ASM International, Materials Park, Ohio, 1989, pp. 359-367. 71. C.J. Lee, in Proc. 39th Electronic Components Conf., IEEE, 1989, pp. 896-900. 72. C.J. Lee, in Proc. 6th Int. SAMPE Electronics Conf., 1992, pp. 521-527. 73. T.G. Tessier, G.M. Adema, and I. Turlik, in Proc. 39th Electronic Components Cot!f., IEEE, 1989, pp. 127-134. 74. B.T. Merriman, J.D. Craig, A.E. Nader, D.L. Goff, M.T. Pottiger, and W.J. Lautenberger, in Proc. 39th Electronic Components CoJ!f., IEEE, 1989, pp. 155-159. 75. C.P. Wong, in Proc. 6th Int. SAMPE Electronics Conf. 1992, pp. 508-520. 76. K.K. Chakravorty, C.P. Chien, J.M. Cech, L.B. Branson, J.M. Atencio, T.M. White, L.S. Lathrop, B.W. Aker, M.H. Tanielian, and P.L. Young, in Proc. 39th Electronic Components Conf., IEEE, 1989, pp. 135-142. 77. H.S. Cole, Y.S. Liu, R. Guida, and J. Rose, in Proc. SPIE, hit. Soc. Opt. Eng., g77 (Micro-Optoelectron. Mater.), 92-96 (1988). 78. T. Studt, R&D Magazine, Aug. 1992, pp. 30-34. 79. A.W. Lin, in Proc. 39th Electronic Components Conf., IEEE, 1989, pp. 148-154. 80. W.C. Shumay, Jr., Adv. Mater. Proc., Feb. 1989, pp. 42-47. 81. S.T. Chen, F. Faupel, and P.S. Ho, in Microelectronic Packaoin9 Technology, Proc. 2nd A S M Int. Electronic Materials and Processing Congress, Philadelphia, PA, Apr. 1989, edited by W.T. Shieh, ASM International, 1989, pp. 345-350. 82. A.L. Ruoff, E.J. Kramer, and C.-Y. Li, IBM J. R&D 32(5), 626-630 (1988). 83. P.H. Dawson, GEC Rev. 2(3), 168-170 (1986). 84. Sumitomo Electric Industries brochure on CMSH. 85. W.H. Pfeifer, J.A. Tallon, W.T. Shih, B.L. Tarasen, and G.B. Engle, in Proc. 6th Int. SAMPE Electronics Conf., 1992, pp. 734-747. 86. A.M. Ibrahim, in Proc. 6th Int. SAMPE Electronics Conf, 1992, pp. 556-567. 87. H. Eisele, Solid-State Electronics 32(3), 253-257 (1989). 88. J. Doting and J. Molenaar, in Proc. 4th Annual IEEE Semiconductor Thermal and Temperature Measurement Symp., IEEE, New York, (1988), pp. 113-117. 89. B. Chuba, Platin9 and Surface Finish#79 76(9), 30-33 (1989). 90. F. Matsui, T. Okada, T. Kawkubo, and T. Otaka, in Proc. AESF Annual Tech. Conf. 1990, pp. 1391-1403. 91. D.S. Dixon and J.V. Masi, SAMPE J. 25(6), 31-37 (1989). 92. D.W. Radford and B.C. Cheng, in Proc. American Socieo'for Composites, 6th Tech. Conf, Technomic Publishing, Lancaster, 1991, pp. 430-439.

Overview of Materials for Electronic Packaging

39

93. Z. Osawa and S. Kuwabara, Polymer Degradation and Stability 35, 33-34(1992). 94. T. Takatani and Y. Saito, Sumitomo Keikinzoku Giho/Sumitomo Light Metal Technical Reports 28(3), 39-43 (1987). 95. N. Hayashi and K. Tanaka, Sumitomo Keikinzoku Giho/Sumitomo Light Metal Technical Reports 29(2), 56-63 (1988). 96. J.J. Glatz, R. Morgan, and D. Neiswinger, in Proc. 6th hTt. SAMPE Electronics Conf., 1992, pp. 131-145. 97. L. Li and D.D.L. Chung, Composites 25(3), 215-224 (1994).

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Joining

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CHAPTER2

Solderability Fundamentals: Microscopic Processes J. A. Clum, T. J. Singler

2.1

Introduction

In the microelectronics industry the packaging of components is a multidisciplinary exercise requiring that electromagnetic, manufacturing, materials, mechanical, and thermal analyses be integrated to produce a cost-effective reliable product. The interconnections between components and circuitry represent an interesting microcosm of these varied concerns. Yet for nearly all joining of electronics packages we place our solders and soldering, mere modifications of materials and processes invented centuries ago [1]. And even after hundreds of years still there are many who study the behavior of solder and the control of soldering [2,3]. Especially useful and comprehensive books about solders and soldering, full of applications, are Klein Wassink [4] and Lea [5]; Lea focuses on surface mount technologies. As indicated in the excellent analysis of research directions in the physical metallurgy of soldering, presented by Romig et al. [6-1, most of the analytical work has fallen into two general categories. One group of workers has emphasized the relationships between laboratory measures of empirically related process control parameters: contact angle measurements and wetting force measurements as indicators of solderability [2,3,6]. Another emphasis has been on microscopic analyses of soldering reactions [5,7-12] including intermetallic formation kinetics, elemental redistributions between solder and substrate, and most recently the application of high resolution, in situ observations of solder spreading rates and reactions. We intend to argue that microscopic analyses are central to developing a fundamental understanding of solderability. Furthermore, we will attempt to show that development of a suitable solderability model will allow for selection of solder alloys to deal with certain soldering process problems, reduction of the use of unnecessary soldering reagents (lead, fluxes, environmentally undesirable cleaning agents) and/or controlling soldering reactions at the submicron scale for improved fine-pitch joining reliability. 43

44

MATERIALS FOR ELECTRONIC PACKAGING

2 . 2 Background The fundamental problem in solderability has often been expressed [4] in the simplest analytical terms as being the interfacial energy relation for spontaneous wetting, 7LV "~- ~SL - - ])SV < 0

(2.1)

where 7LV,7SL,and 7sv are the liquid-vapor, solid-liquid, and solid-vapor interfacial energies, respectively. Equation (2.1) is a special case of Young's equation, 7LV COS 0 + 7SL = 7SV

(2.2)

where 0 is the contact angle. Equation (2.2) can be derived by minimizing the energy of a system comprised of a liquid and vapor in contact with a solid in a state of equilibrium. Each 7 in equation (2.2) may be considered as a thermodynamic property provided that the effects of curvature on the interfacial energies are negligible. Comparison of equations (2.1) and (2.2) suggests that as the value of the contact angle tends to zero, spontaneity of wetting is approached. Consequently, the emphasis on attaining "good" wetting translates into observing a small contact angle. Similarly the relationship between wetting force and contact angle as expressed in [4] shows that the force is maximized as 0 tends to zero: Force = (TSL)(COS0)(specimen periphery)

(2.3)

However, the implication of the value of the contact angle is rather more illusory when one factors it into a wetting process model. The liquid solder components generally react strongly with the substrate to form a variety of intermetallic products, e.g., MxNy,where M = Au, Cu, or Ni; and N = In or Sn. So should the contact angle be expected to remain constant while the interfacial compositions are changing? For an example of the complexities which these reactions present consider the case of Pb-Sn solder on Cu substrates. In the case of a low Sn solder, for example 95Pb-5Sn, the only intermetallic product observed [13] is Cu3Sn. However, with higher Sn content we have observed Cu3Sn next to the Cu surface and Cu6Sn 5 next to the solder [7]. The latter observation is not unique [4-6], but we have noted [7] that the relative amounts of the two intermetallics change with time. This indicates a diffusional process normal to the original soldersubstrate interface, a process that alters ~'SL. This noted variability of the Cu-Sn intermetallics with Sn content of the solder follows a pattern similar to the observations of Yost [15] for Pb-In solders on Au. In that case the Au-rich phase (Au9In4) was found to dominate when there was an excess mass of gold ("... thin solder or thick gold...") [15] as was the case in the low Sn solder which produced only the Cu3Sn, copper-rich phase [13]. By analogy the observations of a preliminary Cu6Sn 5 layer followed by formation of a Cu3Sn layer can be rationalized as being due to an effective Sn deficiency at the Cu-Cu3Sn interface. Subsequent formation of Cu3Sn occurs only by consumption of Cu6Sns, due to kinetic diffusion control [16]. We might suppose the same behavior occurs in the

Solderabilitu Fundamentals: Microscopic Processes 4 5

analogous case of Pb-In on Au, reported by Yost [15]; we might even suppose it is a general phenomenon that affects the 7SL parameter. Furthermore, there is evidence on the microscopic scale [5,7,8,11,14,15] that, during spreading, transients in the wetting front morphology develop that may be attributed to a variation in solder composition, hydrodynamic instability, or to chemical heterogeneity of the solid surface, and which might induce similar transients in contact angle. These occurrences are manifest during a period in which most contact angle measurements are not recorded due to the perceived morphological variations. Such variations appear to be quite common, and are displayed by a wide variety of material systems undergoing wetting [17,18]. In particular, Williams [17] has shown morphological instabilities for organic fluids spreading on AI thin films, and they are very similar to our observations for solder films on Au [-8] (Fig. 2.1). The frequent incidence of wetting front morphological variations strongly suggests the possibility that contact angle measurements will also exhibit variability dependent on phenomena not accounted for in the derivation of equation (2.2). These two considerations dealing with changes in the substrate and the solder composition during soldering certainly imply that the 7SL term is likely to vary during spreading. Moreover, Lea has argued [5] that the 7LV term also varies as the overall solder composition varies during spreading. In that regard Lea notes that in the presence of fluxes there can be a significant reduction (~ 20%) in 7LV. The results of Shipley [12] on spreading time variations with and without flux for various solder compositions can be rationalized on the same basis. However, we would argue that near the substrate where dissolution of metallizations occurs, for example, Au or Cu, the 7LV effect can be counteracted. In the case of 63Sn-37Pb solder on an Au substrate, the surface energies, ~'LV in mJ/m 2 are 550 (Sn), 460 (Pb), and 1360 (Au). And only a small amount of Au dissolution results in a significant increase in the surface tension of tin or lead [8]. Lea [5] reports a particular observation of elemental surface segregation Auger analysis of a Pb-Sn-Cu wetting interaction. This is in general agreement with our own observations [7,8] as well as those of Prack [9,14] and Marshall [ 11]. However, Lea's conclusion that a Pb-rich film leads to the spreading process is not in agreement with our observations on precursor solder films [7,8]. We have observed the behavior for Pb-Sn, Pb-In, and Sn-In solders and we believe that In forms a precursor in Pb-In and that Sn forms a precursor in Pb-Sn and Sn-In. We also believe these precursor films spread preferentially along the substrate grain boundaries (Figure 2.2). It is worth noting here that the environmental scanning electron microscope (ESEM) micrograph of Figure 2.2 is remarkably similar to the observations reported by Marshall [11] (see Figs. 6-51 through 6-57 in that paper) of SEM examinations of reaction products taken postwetting for solder on A u. Rather than support the hypothesis for Pb-rich films created by 7LV effects, we would argue that the Pb-rich films are a residue from the Sn-Cu reactions which cause a Sn depletion to occur at the periphery of the spreading solder with the Sn actually being enriched in a peripheral reaction product. Such a notion is

46

MATERIALS FOR ELECTRONIC PACKAGING

Fig.re 2.1

Morphology of 63Sn-37Pb solder after spreading on Au film (on Cu substrate) at 300~ in air, no flux: (a) general morphology with evidence of precursor film and (b) higher magnification view of distinct precursor film from the upper center portion of (a).

Solderobi/ify Fundomenfo/s: Microscopic Processes 4 7

Figure 2.2 (a) ESEM micrograph at ambient temperature (25~ after flow experiment of 63Sn-37Pb on Au foil at 250~ 7.1 torr H20. Upper left shows unreacted Au; lower right shows Pb-rich primary crystals; the interface region is approximately AuSn (6) intermetallic mixed with primary Pb crystals. (b) ESEM of 50In-50Pb on Au foil taken at 90~ 6.6 torr H20, during cooldown from 250~ Au region at left; the shapes seen protruding from the solder mass on the right are crystals of approximately Auln2 (6) intermetallic composition and are growing up from the substrate through the solder mass.

48

MATERIALS FOR ELECTRONIC PACKAGING

consistent with the observations by Marshall [11], by Prack and Raleigh [14], and in our work [7,8] where a peripheral reaction product of the Sn (or In) intermetallic is observed with Pb-rich primary crystals remaining upon solidification in a subperipheral region (Figure 2.2).

2 . 3 A Microscopic Mass Transfer Model In order to rationalize these observations, a simple geometrically based kinetic model can be employed (Fig. 2.3). The conceptual model is based on a collapsing/ spreading disc of constant solder volume. The constraint of constant solder volume provides a relationship between the increment in solder/substrate contact in the x-direction and the decrement of disc height in the negative y-direction. During this solder rearrangement, diffusion of substrate material takes place mainly in the y-direction. The relationship between the height decrement, (Yo- dy), and the spreading front increment, dx; is expressed by g(R2)yo = z~(Ro + dx)2(yo - dy),

(2.4)

where R o is the initial disc radius and Yo is the initial disc height. The model is related to experimental observation through measures of the spreading rate, dx/dt. Additional information needed for the model implementation

Bulk Front ~

~

PrecursorFilm

Liquid

t

Y

Subst-rate

Adsorption Oxide Layer Cheatcal R~action

Volume Diffusion

Dissolution

Figure 2 . 3

Schematic geometry for solder wetting.

SolderabilityFundamentals.. Microscopic Processes 4r

is the diffusivity of substrate material in the molten solder and the composition of intermetallic(s) formed. For example, in the case of the P b - S n - C u reactions the Cu6Sn 5 phase is equivalent to 55 at.% Cu and the Cu3Sn phase is equivalent to 75 at.% Cu. The diffusivity of Cu in solder, Dcu, is of the order of 10-xo cm2/s at about 700 K (425~ or about 10-12 cm2/s near 500 K (225~ [13]. If we use a simple one-dimensional, constant surface concentration model for solute (Cu) diffusion [19] for this case, we can write

Ccu(y, t ) = Ccu(O)[1 -erf[y/(2(Dt)I/2)]]

(2.5)

Application of this model takes place in the following steps. First, we examine the time needed to achieve Ccu(Y, t)/Ccu(O)= 0.55 at y = 1.0 nm, that is the time to build an initial intermetallic layer at the interface. Note that the interface Cu concentration is Ccu(0)= 1.00--pure Cu. Second, using that increment of time, dt55, we evaluate the distance increment, dyol, for the location where Cc,(dyol, dt55) = 0.01. This location is arbitrarily chosen as a position where the Cu diffusion front may be detected. Third, using equation (2.4), with dy = dyol, we estimate the incremental distance of spread, dx55, that has occurred in the time increment dr55. Then if the measured dx/dt is greater than dx55/dt55 we can expect that unreacted Sn will be found at the spreading periphery. Alternatively, the Sn may be at least partially combined as intermetallic due to diffusion of Cu normal to the spreading direction. This simple analysis nominally ignores any diffusional mixing of Sn in the spreading solder as well as any convective transport of Cu in the direction of the spreading liquid. We assume the spreading solder liquid is translated from the unreacted portion of the solder disc. For T = 700 K (425~ Ccu and Dcu values noted above, an initial disc diameter of 1.0 mm, and an initial disc height of 1.0 mm, the first calculation yields dt55 = 1.397 x 10- 4 s. The second calculation yields dyo 1 = 4.3 x 10- 7 cm and the third yields dx55 = 1.065 x 10-Scm. The resulting dx55/dt55 is then 7.62 x 10-2 cm/s (762 #m/s). If the temperature is reduced to about 500 K (225~ the calculated spread parameter, dx55/dt55, decreases to 7.61 x 10 -4 cm/s--a reduction by two orders of magnitude (Dcu has decreased to about 10-12 cmZ/s). If the temperature is raised beyond 700 K, dx55/dt55 increases and the reactive solder component may be sequestered by the diffusing substrate material, as discussed below. Our high resolution ESEM observations suggest that spreading rates of the precursor films are on the order of micrometers per second. Consequently, this simple model would predict that Sn may be found at the spreading periphery. We have frequently observed Sn and In at the periphery for spreading on Au substrates in ESEM experiments [7]. However, for tests run using optical, hot-stage microscopy in air, with no flux, Pb was often found at the periphery [8]. The differences between these results are still being evaluated in terms of the experimental pressure variable, which distinguishes the ESEM from the optical hot-stage tests. ESEM has the capability to utilize a variety of atmospheres [7,9,14,20,21], albeit at total pressures lower than atmospheric. Work on a model to calibrate for these pressure effects is proceeding [21].

50

MATERIALS FOR ELECTRONIC PACKAGING

2 . 4 Observations of Limiting Mass Transfer This simple mass transport model is also applicable to two other behaviors we have observed in solder spreading experiments. One is a process which might be called dewetting [4,7]. In our observations of this behavior we have varied the thickness of Au films on glass. If the Au film is below a critical thickness for a given mass of solder, the solder will spread only a finite distance and upon solidification the solder will contract into globular shapes with minimum substrate contact and with the surrounding region of glass being scavenged of Au (Fig. 2.4). The solder will spread some distance consuming Au as it spreads by Au diffusion into the solder. If the mass of Au available is insufficient to saturate the solder~insufficient to form the Au-Sn or Au-In intermetallic--all the Au will be dissolved leaving no Au with which to bond. The glass is not wetted by the solder. This case represents the behavior where dx/dt is greater than dX~M/dt~M,the reference spreading rate for a particular intermetallic (IM), and where an unreacted solder component, such as Sn, is available for continued reaction at the spreading periphery but the Au supply has been exhausted. Another observation that may be rationalized by this simple model is the reaction between solder and substrate with insignificant spreading. In these observations the solder essentially melts through the substrate (pure Au foil) and little or no spreading is seen (Fig. 2.5). Such results imply a very high diffusive flux of substrate material (Au) into the solder; this effectively ties up the reactive solder component and reduces the spreading reactivity driving force. Using our simple model, the difference between these two behaviors might be rationalized on the basis of the diffusivity of substrate material in the liquid solder. A decrease of Dc~ of nearly two orders of magnitude occurs for a temperature drop from about 700 K to 500 K (425~ to 225~ The estimated dX~M/dt~M decreases by two orders of magnitude as the temperature decreases. But based on a A7 driving force, the spreading rates, through d(AT)/dT, are less sensitive to temperature. So dT/dT is about the same for each term in equation (2.1), and the spreading rates are still expected to be in micrometers per second. Nevertheless, higher temperatures could result in sufficiently high fluxes of substrate material into the solder to reduce the solder reactivity. There is an important geometrical effect in this model which was a factor in our observations of the melt through phenomenon. In those tests solder cylinders were placed base down on the substrate to provide a large area of contact throughout the temperature rise. Solder spheres have a reduced contact during the period of spheroid collapse and this greatly reduces the total flux of substrate material relative to the rate of spreading. Based on these simple arguments the observations noted above might be rationalized in terms of the temperatures used. For the case of "thin" substrates it is doubtful that a low enough temperature can be found to prevent dewetting in all cases. However, the model implies that the minimum thickness to prevent dewetting should be a direct function of soldering temperature, an important but often ignored process design consideration. At the other extreme it may also be prudent to avoid excessive temperatures as the diffusive flux into the solder can

$olderability Fundamentals: Microscopic Processes 51

Figure 2.4

SEM micrographs of 50Pb-50In flowed on Au substrates for 10 min at 250~ (a) solder on thin (0.5/~m) Au on pyrex, the solder mass has dewet and resolidified into a nearly spherical shape, the surrounding glass is almost free of Au except at the distance periphery (dark upper region); and (b) solder on 0.2 mm Au foil, the solder wetting is greater than in (a).

52

MATERIALS FOR ELECTRONIC PACKAGING

~"~~'!~IsilT~i~'i!i!!i!i!i!i!!!i i~/i~i~3i!iiii!qi,li!i!i!i!ii iiii~iiiiiiii!i!:!iii:~

....zAu ......................:;ii{ii

ii~iYi'~~

,

.......

iii!)ii;ii!ii:ii/!iiil ii!~il;i~:iii;ii}i~;;;i~!~!

~"~il i iiiiiili:i~:yii:~!84 ....

~

ii:~i~i~i!!iil/i~!~i~i!ii! il !i ) ..... ,.,..,

i:i~ii!ii:iii!iii!!:!:!i

Figure 2.5 ESEM micrograph of 63Sn-37Pb on Au foil taken at 100~ 1.2 torr N2, during cooldown from 300~ Original solder mass at left has melted through foil with some precursor film shown as darker stain regions emanating to the right from the solder mass. X-ray spectra show Sn and Pb in all regions of stain. A strong Au signal is seen in all regions, even within the solder mass.

also apparently retard wetting. Another important factor at higher temperatures is the possible oxidation of solder, partly responsible for retarded wetting. In the worst cases an oxide skin encloses the solder mass (Fig. 2.5). Obviously this very simple model needs to be expanded to account for the more intricate details of fluid mixing and general fluid force distributions. But more elaborate modeling requires more extensive data on both wetting behavior (e.g., precursor film spreading rates and composition) and fluid properties (e.g., 7Lv, density, viscosity) as functions of temperature and composition. We have begun computational model development in conjunction with our experimental work on precursor films [21]. The dynamics of precursor films and their role in wetting are not completely understood. As late as 1974 [22], the existence of precursor films for certain liquid-solid systems was apparently in question. And as late as 1980 [23], there was little understanding of the role of precursor films in the wetting process of liquid-solid systems for which the existence of precursor films had been established. But significant understanding of the precursor film dynamics has recently developed [24a,b]; this understanding includes their genesis, their flow, and their role in wetting, with the tacit assumption that every wetting event involves precursor films. It is a theory that links the observable macroscopic wetting phenomena with the physicochemical submicroscopic phenomena of thin films. However, this theory

Solderabi/ity Fundamentals: Microscopic Processes 53

is not yet entirely satisfactory, and quantitative discrepancies between theoretical predictions and some wetting data are documented [24b]. The theory has, moreover, been developed for smooth surfaces and applies to liquids which are chemically inert. The term precursor film is a descriptive term for thin films which form and flow in advance of the macroscopic (bulk) wetting front. We can distinguish between primary thin films and secondary thin films. Primary thin films, or simply thin films, have thicknesses on the order of a few molecular diameters. Secondary thin films, or thick films, can be as thick as several micrometers. The two types of films spread by different mechanisms. The substrate is initially wet by the primary film. For volatile liquids, primary film spreading occurs by evaporation and condensation, for nonvolatile liquids, film spreading occurs by surface diffusion. Spreading of the secondary film can effectively be interpreted as the thickening of the primary film. This phase of the wetting process can be driven by both the disjoining pressure and surface tension gradients. The effect of the precursor film in wetting processes involving inert liquids is essentially to cover an otherwise dry solid surface with a thin liquid film, over which the bulk liquid eventually flows; one purpose of the theory is to predict the thicknesses of these films and the rate at which they spread. The rate of spreading of the precursor film can be the rate-limiting factor for bulk wetting. The current understanding of precursor film dynamics cannot be directly applied to the physicochemical systems that occur in soldering processes; this is because there are chemical reactions and their attendant bulk diffusion and because the liquid-fluid interface and the solid substrates undergoing soldering have nonideal surface properties (Fig. 2.3). All these factors are likely to influence the spreading mechanisms referred to above. While the low vapor pressures of molten alloys at typical soldering temperatures make surface diffusion the likely mechanism of primary film spreading, the diffusive driving force is probably augmented by the increased chemical potential gradient due to the high reactivity of the most reactive constituent of the alloy with the substrate. Verification of this assertion needs to be made in the reduced total pressures of the ESEM environment. The liquid-vapor and liquid-solid boundaries of the wetting flow are reactive surfaces. In particular, for oxidizing atmospheres, the liquid-vapor boundary is oxidized and the resulting oxide layer alters the character of the flow boundary condition at the surface. The oxide layer has characteristics of both solid and liquid interfaces; it appears capable of deforming in a direction normal to the interface without exhibiting relative tangential motion. It is clear that it suppresses to some extent internal motion within the wetting front. Because of the very low partial pressure of oxygen required to form an oxide layer, oxidation will likely be present in all commercial soldering systems. The liquid-solid boundary moves with time in a way determined by the local mass transfer driven by dissolution and modulated by chemical reaction, specifically the formation of intermetallics. While the thickness of the intermetallic layer remains small over the wetting timescale, the mass transfer coefficient at the boundary is significantly altered by the reduction in magnitude of the diffusion coefficients of the substrate metal and reactive component in the intermetallic. For

54

MATERIALS FOR ELECTRONIC PACKAGING

example, Yost [25] has shown that this mechanism greatly reduces the scavenging of Au substrates (coatings) by alloys containing In as compared to alloys containing Sn. The possibility of simultaneous oxide and intermetallic layer formation in the precursor film region greatly complicates the wetting front physics. The implications for the trailing bulk flow are very significant because the interfacial energies of intermetallics are in general higher than those of the unreacted substrate. If dissolution is not significantly attenuated before the substrate species is distributed throughout the bulk by volume diffusion, the presence of this higher free energy species will affect the surface tension. If as a result of nonuniform distribution of such species a concentration gradient arises at the interface, the associated surface tension gradient will induce Marangoni motions. In the precursor film region, particularly in surface capillaries (grain boundaries, where the large surface area to volume ratio amplifies dissolution effects) which intersect the film contact line, such Marangoni motions have been postulated to enhance the wetting process [8]. Obviously, a great deal of work remains to be done in order to clarify the physics of reactive wetting fronts.

2.5 Solder Alloy Selection and Process Design Now we are ready to propose a solder composition-solderability process design paradigm. As expressed in equations (2.1) through (2.3), the various surface energy terms appear to play nearly equal roles in the soldering process. However, it has become apparent to us that the VSLparameter is the major factor in controlling solderability. Nonetheless, in a typical analysis of the application of the energetic equations to soldering ~'SLis treated as an unknown, adjustable parameter. For example, in a practical process design one starts with the assumption of an oxidized surface (low Vsv) which is to be converted to higher 7sv by the action of fluxing reagents on the substrate, for example the breakdown of oxide films by chloride anions. By default the choice of a Pb-containing solder, with alloy liquids of typically low 7LV allows for the extension of the liquid-vapor surface required to achieve the desired spreading geometry of low contact angles. (Refer again to Lea [5] for the arguments regarding alloy surface segregation, i.e., adsorption, and the effect of flux on lowering 7LV.)Finally, 7SLis fitted into the energetics, mostly as an unknown, adjustable parameter to satisfy the observed wetting constraints of equations (2.2) and (2.3). However, we prefer to follow the arguments about the importance of controlling 7SL, before the fact, as put forth by Klein Wassink [26]. In that paper the author showed the need to separate the role of 7LV and 7SL in evaluating solderability. For example, in the case of solder spreading on a free surface the improvement of wetting with increasing Pb content occurs at the 60Sn--40Pb alloy composition, since at that composition reduction in VLV by increasing the Pb content begins to be outweighed by the increase in VSLby increasing the Pb content.

Solderability Fundamentals: Microscopic Processes 5 5

However, for the spreading of solder in a capillary, where 7LV plays little or no role, the best results occur with the most reactive Pb-Sn alloyml00% Snmand the role of Pb as a diluting carrier component is clearly seen. Our arguments not only support Klein Wassink, they go further. We say it is possible to compose solder alloys based on separate considerations of components' roles in 7LV and '~SL. We can construct an argument for replacement of Pb in solder alloys, if that is environmentally desirable, by choosing substitutions in terms of 7LV and ~'SL effects. Imagine a Pb substitute for Pb-Sn and Pb-In alloys; on solderability grounds we are drawn to consider Bi. Bi is chosen for other applications where Pb liquid and solid Cu interact, for example machinability of Cu alloys [27]. The value of 7LV is about 100 mJ/m 2 lower for Bi than for Pb; 7LV for Pb is 450 mJ/m 2 [27]. Compared to Pb there are no significant differences in the phase equilibria between the solder alloy components and Bi, and no significant differences in the solubility of Bi in substrate materials (Au and Cu) [28]. Consequently, as a first approximation we would expect solderability of Bi-Sn and Bi-In alloys to be equivalent to the corresponding Pb-Sn and Pb-In compositions, perhaps even slightly better for free surface applications. Preliminary results from tests with such materials shows this to be the case in simple binary alloys and Pb-Bi-Sn ternaries [21]. Results from more complex Bi-containing alloys do not appear as promising, although they do show large variations in the measurements [29]. Klein Wassink provides results on the doping of nonwetting liquid metals with reactive components, such as liquid Ag doped with Pd, in order to wet solid Fe. The concept they reflect evolved from an analysis similar to this chapter; it emphasizes the importance of solubility and reactivity between the solder components and the substrate for controlling solderability. The importance of this concept is also recognized for tailoring brazing alloys [30]. We believe it may be extended to the development of solder alloy systems which have reduced flux requirements; there we emphasize cation effects instead of anion effects on the creation of bonding on oxidized surfaces [21].

2 . 6 Conclusion

We have presented some observations from solder spreading experiments to illustrate our need for a more comprehensive and, we hope, more predictive model of the soldering process. Much work has been done on measurements of such parameters as contact angle, intermetallic growth kinetics, and wetting force but a few reports [-4,5,6] have attempted a unifying analysis, even qualitatively. Now that analytical tools such as ESEM can be used to make real-time, high resolution measurements of chemical changes in representative environments, we advocate the expansion of efforts to develop a more quantitative understanding of the liquid-solid interactions exemplified by soldering and brazing.

56

MATERIALS FOR ELECTRONIC PACKAGING

References 1. M.F. Ashby and D.R.H. Jones, Engineering Materials, Vol.2., Pergamon Press, Oxford, 1986, pp. 31-33. 2. D.R. Frear, W.B. Jones, and K.R. Kinsman (eds.). Solder Mechanics." A State of the Art Assessment, TMS-EMPMD Monograph Series, No. 1, Warrendale PA, 1991. 3. J.H. Lau (ed.), Solder Joint Reliability: Theory and Applications, Van Nostrand Reinhold, New York, 1991. 4. R.J. Klein Wassink, Soldering in Electronics, 2d ed., Electrochemical Publications, Ayr, Scotland, 1989. 5. C. Lea, A Scientific Guide to Surface Mount Technology, Electrochemical Publications, Ayr, Scotland, 1988. 6. A.D. Romig, Jr., Y.A. Chang, J.J. Stephens, D.R. Frear, V. Marcotte, and C. Lea, in Solder Mechanics." A State of the Art Assessment, edited by D.R. Frear, W.B. Jones, and K.R. Kinsman, TMS-EMPMD Monograph Series, No. 1, Warrendale PA, 1991, Ch. 2. 7. J.A. Clum and T.J. Singler, in New Technology in Electronic Packaging, Proc. 3rd A S M Electronic Materials and Processing Congress, San Francisco, 1990, pp. 175-186. 8. T.J. Singler, J.A. Clum, and E.R. Prack, ASME Winter Annual Meeting, Atlanta, GA, Dec. 1991, ASME Paper 91-WA-EEP-37. pp. 1-10, 1991. 9. E.R. Prack, in Proc. IEEE C H M T (1991). 10. D.R. Frear, F. M. Hosking and D. M. Keicher, this volume, pp. 79-103. 11. J.L. Marshall, in Solder Joint Reliability: Theory and Applications, edited by J. J. Lau, Van Nostrand Reinhold, New York, 1991, Ch. 6. 12. J.F. Shipley, WeMing Res. Suppl., pp. 357s-362s, Oct. 1975. 13. D. Grivas, D. Frear, L. Quan, and J.W. Morris, Jr., "The Formation of Cu3Sn Intermetallics on the Reaction of Cu with 95Pb-5Sn Solder," Lawrence Berkeley Lab., LBL-19416. 14. E.R. Prack and C.J. Raleigh, Ultramicroscopy 37 (1990). 15. F.G. Yost, Gold Bull. 10 (1977). 16. U. Gosele and K.N. Tu, J. Appl. Phys. 66, 2619-2626 (1989). 17. R. Williams, Nature 266, 153-154 (1970). 18. W.W. Mullins and R.F. Sekerka, J. Appl. Phys. 35, 444 (1964). 19. P.G. Shewmon, Diffusion in Solids, 2d ed., TMS, Warrendale PA, 1989, pp. 22-23. 20. N. Baumgarten, Nature 341, 81-82 (1989). 21. T.J. Singler, J.A. Clum, and E.R. Prack, unpublished research. 22. W. Radigan, H. Ghiradella, H.L. Frisch, H. Schonhorn, and T.K. Kwei., Colloid Interface Sci. 49(2), 241-248 (1974). 23. A. Marmur and M.D. Lelah, J. Colloid Interface Sci. 78(1), 260-265 (1980). 24(a). P.G. de Gennes, Reviews in Modern Physics 57, 827-863 (1985). (b) G.F. Teletzke, H.T. Davis, and L.E. Scriven, Chem. Eng. Commun. 55, 41-82 (1987). 25. F.G. Yost, Proc. Int. Soc. Hybrid Microelectronics, 1978, pp. 61-66. 26. R.J. Klein Wassink, J. Inst. Metals 95, 38-43 (1967). 27. J.T. Plewes and D.N. Loiacono, Adv. Mater. Proc. Oct. 1991, pp. 23-27. 28. A S M Metals Handbook, Vol. 8, 8th ed., Metallography, Structures and Phase Diagrams, ASM, 1973. 29. F.M. Hosking, P.T. Vianco, and D. R. Frear, in Materials Developments in Microelectronic Packaging." Performance and Reliability Proc. 4th A S M Electronic Materials and Processing Congress, Montreal, 1991, pp. 365-371. 30. R.R. Kapoor and T.W. Eagar, Metall. Trans. 20B, 919-924 (1989).

CHAPTER

3

Determining the Damaging Strains which Cause Failure in Pb-Sn Solders A. I. Attarwala, B. C. Hendrix, J. M. Sanchez

3.1 Introduction Solder joint reliability is an important concern in surface mount packages since the joints have to provide not only a good electrical connection but also a good mechanical connection. An electronic package is made of different materials which have different coefficients of thermal expansion. During operation, the thermal expansion mismatch between the chip carrier and the board subject the solder joints to cyclic stresses. The thermal cycles are caused by power on/off cycles, diurnal temperature variations, and seasonal temperature changes. Although thermal expansion mismatch between board and chip carrier can be reduced by matching their coefficients of thermal expansion, during power on/off cycles thermal gradients exist between them, therefore some mismatch is always present. Many approaches are being undertaken to predict how long a given solder joint will last before it fails under a certain set of conditions [1-26]. Testing has been performed on actual test packages, joint type specimens, and bulk solder material. One of the most common approaches used in industry is thermal cycling of test packages. The advantage of this approach is that it can provide good data for life prediction for that particular package. Most factors which interact to cause a solder joint to fail are taken into account, such as thermal gradients across the chip carrier and the board, warpage of the board, and thermal expansion mismatch between the carrier and the board. However, this approach is time-consuming and expensive since it requires extensive testing to develop every new package. The main drawback of this approach is that the data relates to the behavior of the individual package so the results are not universally applicable. Another approach for life prediction is to model the joint response based on constitutive equations [28-32]. Subhramanyan et al. [30,31] have developed a constitutive equation for solder subjected to thermomechanical cycling. Their life predictive equation is based on a fracture mechanics approach to model the propagation of a single crack through the solder joint. A different approach has been developed by Fox et al. [10] and Knecht et al. [32]; they use a constitutive 57

58

MATERIALS FOR ELECTRONIC PACKAGING

equation to separate the different strain components during each cycle. Their failure criteria is based on the accumulation of certain components of strain. Although this approach promises to decrease the effort expended on testing during package development, it lacks well-defined constitutive equations and failure criteria. Mechanical behavior of joints [-23-27], joint type specimens [10-12,22], and bulk specimens [8,9,13-20] are being studied by a number of researchers to establish a relation between the number of cycles to failure--the amount of damage being stored per cycle, and the loading condition. For example, Roger Wild [24,25] has done an extensive study of plated-through-hole solder joints, lap joints, and butt joints. He recognized that deformation behavior of solder depends on temperature and time through variables such as strain rate and frequency. Solder joints were tested under various conditions by Solomon [ 11,12], who has attempted to separate the plastic strains from the total strains and to relate them to the number of cycles to failure. Fine and Vaynman [8,9] have tested bulk solder specimens and have related the plastic strains to the number of cycles to failure. Extensive work on the characterization of the deformation behavior of eutectic Pb-Sn solders has also been carried out by Tien et al. [ 13-21 ]. These authors have shown that the presence of anelastic strains can suppress the storage of nonrecoverable creep strains during accelerated cycling. The microstructural evolution of solder material under mechanical loading has also been the subject of several investigations [33-43]. The aim of the microstructural studies is to understand how microstructure and microstructural changes affect the deformation and failure characteristics of solder. For example, Frear [39,40], Frost [36,37], and Raman [42,43] have focused on the effects of microstructure and dynamic recrystallization. Life prediction analysis requires knowing not only what processes are causing the deformation and failure but also how to measure the damage accumulation leading to failure. Although, a considerable amount of work has been done on studying the deformation behavior of solder under mechanical loading, there is still no consensus on what processes are primarily responsible for failure. Due to th~..,, cyclic ..~.n~ture of th~_,, ~'vv''~'~'""~nnl~'~ ti,-,n of stresses, many researchers characterize failure in terms of fatigue parameters, cycles to failure and plastic strain range. However, our work on bulk Pb-Sn solders tested under isothermal conditions at temperatures as low as - 4 0 ~ and at a frequency of 0.5 Hz show that failure occurs primarily by accumulation of damage due to creep. The sections which follow describe the deformation of Pb-Sn solder under static and cyclic loading conditions. This behavior is then related to the more tangible concepts of loading conditions and life.

3.2 Test Methodology and Data Analysis All tests were performed on bulk specimens cast from different compositions of lead and tin. Most of the specimens were tested in the as-cast condition but some were aged or directionally solidified to study the effects of different grain structures. Details of the specimen preparation and geometry can be found elsewhere [21].

Determining the Damaging Strains which Cause Failure in Pb-Sn Solders 59

Tests were performed on a computer-controlled servohydraulic testing machine with a feedback loop control system. The cyclic tests were conducted under uniaxial. tensile, load-controlled conditions. It is important to note that all of our tests were performed under load-controlled conditions as opposed to the more commonly used strain-controlled conditions. Under load-controlled conditions it is easy to separate and measure the contributions of the different strain components present during cycling.

3.2.1 Separation of Strains Four types of strain are stored during a cycle: elastic strain, anelastic strain, athermal plastic strain, and creep strain: (3.1)

~T--8el + ~an "[- 8pl + eerp

Anelastic strain and creep strain are time dependent; elastic strain and plastic strain are time independent. Elastic strain and anelastic strain are recoverable; creep strain and plastic strain are nonrecoverable and damaging. Table 3.1 shows the different types of strains. Figures 3.1 and 3.2 respectively show schematics of the strain response of a single load-controlled cycle and the stress response of a strain-controlled cycle. In the load-controlled cycle, the time-indepedent strains, which are the elastic and plastic strains, occur immediately the stress is applied during square wave cycling. The time-dependent strains, which are the anelastic and creep strains, are stored during the hold time on load. When the load is released, the elastic strain is recovered immediately, whereas the anelastic strain is recovered over a period of time. An example of actual anelastic strain storage and recovery is shown in Figure 3.3, which shows the strain versus time response of solder in a load-controlled test. Notice that during the off-load period, elastic strains are recovered immediately and then some more strain is recovered with time. This time-dependent recovered strain is the anelastic strain. The stress response of a strain-controlled cycle is more complex. During the ramp-up time, the stress is due to the sum of the elastic and instantaneous plastic strains. During the hold time at the maximum strain, some of the elastic strains get transformed into anelastic and permanent creep strains with a corresponding drop in load. During the ramp-down time, a compressive load has to be applied to bring the specimen to zero strain because of the time-dependent strains stored at the hold time at maximum strain. During the time at zero strain, the compressive load again relaxes toward zero as anelastic and creep relaxation occur. Table 3.1

Different components of the total strain.

Recoverable Nonrecoverable

Time independent

Time dependent

Elastic Plastic

Anelastic Creep

60

MATERIALS FOR ELECTRONIC PACKAGING

I

I

I

I

I

I I

I

-

,

I

I

I

I

I

I

I

J

,

I

I

I

I

I

I

I

I

I I

,k,

j

y

TIME

I

v

TIME

Figure 3.1 Schematic showing a load-controlled cycle and the corresponding strain response. It is possible to separate the contributions of the different components of strain to the total strain.

I II

&

I

=

An+Crp-el*

I

I

I

I~

I

I

I

I~ i , I

I

I

I

lel-el*)+ el (comp) i PI (comp)

,,mn~

' "- T I ~

I An (c...._e~.,(Comp)+ Crp (comp) I I

I

I

I

I

I

I

I TIME

I I

I i

I I

I I

el* = elastic strain which is converted to creep strains and anelastic strains during the hold time.

Figure 3.2 Schematic showing a strain-controlled cycle and the corresponding stress response. It is difficult to separate the different strain components because the driving force, the stress, is continually changing due to stress relaxation.

Determining the Damaging Strains which Cause Failure in Pb-Sn Solders 61

30

f C z_

--

28

27 592

594

5 6

598

600

Time (sec) Figure 3.3 Strain response of a load-controlled cycle. There is a large strain recovery during the off-load hold time.

The important advantage of the load-controlled test is that it allows each of the strain components to be measured separately in each section of the load cycle. 3 , 2 . 2 The Envelope Strain Curve The curve obtained by plotting the maximum strain seen during each cycle as a function of time spent on load is called an envelope strain curve. The envelope strain curve shows the average rate of storage of nonrecoverable strains, creep strain plus athermal plastic strain, obtained for a given loading condition. Figure 3.4 shows schematically how an envelope strain curve is obtained from the strain response during load-controlled cycling. Figure 3.5 shows actual test data of the strain response during load-controlled cycling and Figure 3.6 shows the envelope strain response of a cyclic load-controlled test. The envelope strain curve is similar to that observed during creep; each curve has primary, secondary, and tertiary strain regions. 3 , 2 . 3 Measurement of Nonre:overable Strain p e r Cy:le The creep strain curve and the envelope strain curve are direct measures of the accumulated nonrecoverable strains, the plastic and creep strains but not the elastic and anelastic strains. Thus, the strain rate for each curve gives a measure of the rate at which nonrecoverable strain is being stored in the specimen under a given set of conditions. Most of the time during load-controlled test is spent in the secondary region, as the strain rate in this region will be used to characterize the damage storage rate for a given set of conditions.

62

MATERIALS

FOR

ELECTRONIC

0

PACKAGING

"envelope" strain strain as a function of time

----

h.._

Time

Figure 3.4 Schematic representation of how an envelope strain curve is obtained from the strain response of a cyclic test. 0.12

-

~

'

.

.

.

.

.

.

.

.

.

.

t

0.11

/

/,

/ 0.10

/ /.

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/

/

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.

f

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,'

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,'

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Time (sees) Figure 3.5 Strain response of a 63Sn-37Pb specimen subjected to cyclic loading between 0 and 12 MPa at 24~ and 0.002 Hz. In most creep situations, the minimum creep rate in the secondary region is used to characterize the secondary strain rate. In some of the solder materials we tested, the primary creep lasted less than one cycle and the strain rate varied during the secondary creep region, as shown in Figure 3.7. In cases where a minimum strain rate could not be characterized or the strain rate was varying during the secondary region, an average of the secondary region strain rate was used to characterize the response of the material.

Determining the Damaging Strains which Cause Failure in Pb-Sn Solders

63

0.3

region Secondaryregion = Tertiary region

A = Primary B = C

0.2 I

0.1

0.0

0

10000

2000

Time (secs) Figure 3 . 6 Envelope strain curve of a eutectic specimen cycled at - 4 0 ~ between 0 and 45 MPa at a frequency of 0.5 Hz. The envelope strain curve shows the three distinctive creep regions primary, secondary and tertiary which are characteristic of a creep curve. 10-4

10 - 5 o

O3

10-6.

10-7

0

_.2... ~*

9

i

10000

9

/

20000

9

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30000

9

I

40000

9

50000

Time (sees)

Figure 3 . 7

Envelope strain rate response of a 90Pb-10Sn specimen cycled at 160~ between 0 and 8 MPa at a frequency of 0.002 Hz. The characteristic secondary strain rate, ~s, whether m i n i m u m or average, is multiplied by the time on load per cycle, th, to arrive at the nonrecoverable strain stored per cycle, enr: ~;nr =

~s t h

(3.2)

The strain per cycle, enr, can then be used to correlate the cyclic life of a specimen to the testing conditions.

64

MATERIALS FOR ELECTRONIC PACKAGING

3 . 3 Deformation Behavior of Pb-Sn Solders under Static and Cyclic Loading Deformation of materials due to creep processes is a function of time, temperature, and the applied stress. The dependency of the deformation on the various parameters is illustrated in the creep equation given below: g, = Aa" e x p ( - Q/k T)

(3.3)

where A is an experimentally determined constant, n is a stress exponent with a value between 3 and 5, Q is the activation energy, and k is Boltzmann's constant. Solder used in microelectronic applications experiences a wide range of operating temperatures, from 0.4 Tm to 0.75 Tm, where Tm is the melting temperature in kelvins. Figure 3.8 shows the operating temperatures experienced by the packages used in different applications. It is generally accepted that creep or thermally assisted deformation becomes significant at homologous temperatures, T/Tm > 0.5. Even at -0.40~ eutectic solder has a homologous temperature close to 0.5.

Homologous P b P nase

433K-rir-160~

i

0.9

i

_ 0.8

.0,6

333K-1-1-+60.C 313K-F-F+40"C

Environments

.0,7

373K-I-1-100,C 353K-FI--+80oc

Eutec "ic Pb-Sn

Typical Use

..O,8

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Temperature

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_>

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_.

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Figure 3.8 Operating temperatures seen by solder in different applications.

Determining the Damaging Strains which Cause Failure in Pb-Sn Solders b5

Failed eutectic solder joints that have experienced temperature cycling from - 4 0 ~ to some high temperature would be expected to show creep damage as an important contributor to the total damage accumulation. In fact, the results of a number of different experimental tests indicate that creep plays the dominant role in the deformation behavior of Pb-Sn solders [18,19]. Figure 3.9 [18] shows the tensile behavior of eutectic solder at different strain rates. The stress at a given amount of strain is higher for tests performed at higher strain rates. Because creep processes are thermally activated and time dependent, the higher strain rates allow less creep strain to be stored, hence the material appears stronger. To identify whether deformation was being controlled by creep processes or fatigue processes, tests were run at different mean stresses and between different stress ranges [18,19]. Figure 3.10 shows the strain rate has a strong correlation with effective mean stress but only a weak correlation with the stress range. The effective mean stress is used to characterize a cyclic test because the deformation is a result of two stress levels. The effective mean stress is defined by equation (3.4):

O'nax)/2

Gef f = (Gnin --]-

(3.4)

Typically, a strong correlation with stress range or strain range indicates that fatigue is controlling the deformation, whereas a strong correlation with mean stress indicates creep is dominating the deformation. 50

9 strainrate 3.26 e-5

9 strainrate 8.34 e-4 A

40

9 strainrate 1.65 e-3

AA 30

20

9

T,

9 9

0

&A

l

D

I

10

9

.O

I

20

S~ain (%)

9i

30

9

I

40

9

50

Figure 3 . 9 Results of tensile tests performed on eutectic solder at different strain rates at 25:~C. Because of creep processes the resistance to deformation increases with increasing strain rate.

66

MATERIALS FOR ELECTRONIC PACKAGING

10 2

(a)

10

q=

0

10 0

13 Mean Stress=6.9 MPa. 3 s e c

10 -1

9

Mean S t r e . = 1 0 MPa, 100 sec

9 Mean S~ress=10.5 MPa, 3 sec o

Mean S~reu=13.8 MPa, 3 sec

10 -2

I

25

10

Stress Range (MPa) 10 3

10 2

.=

(b)

n

Sums range = 5 MPa, 100 ser

9

Sa'ess range = 10 MPa, 100 s e c

9

Su'ess range = 13.8 MPa, 100 sex

0 r~

::L

101

o

03

10 0

13

9

10"1 13

10"2 2.5

Q a !

5

I

10

I

20

40

Effective Mean Stress (MPa) Figure 3.10 There is a strong correlation between strain rate and effective mean stress but only a weak correlation with stress range, indicating that deformation is controlled by creep processes.

The importance of temperature in the cyclic deformation behavior of solder is seen in Figure 3.11, where the strain rate response is seen to follow the Arrhenius law of activated processes. The specimens were subjected to a square wave cycle with equal on-load and off-load hold times. The minimum stress was 0 MPa while the maximum stress was 27 MPa. The effective activation energy at a hold time of 3 s was found to be 0.95 eV/K, while at the 100 s hold times it was equal to 0.86 eV/K. The thermal activation energy, which corresponds well to the activation energy for self-diffusion in solder, will cause the strain rate at a given stress to change between 10 and 20% for each I~ change in temperature [18,19]. Because

Determining the Damaging Strains which Cause Failure in Pb-Sn Solders 6 7

103!

102 927.6 MPa o 10.0 MPa

rO or) 101 r

r-

"~ 100 0 0

10-1

10-2

3.1e-3

0 o

I 3.2e-3

I 3.3e-3

I 3.4e-3

I 3.5e-3

I 3.6e-3

I 3.7e-3

1/T

Figure 3.1 1 Strain rate of cyclic test data as a function of temperature for 100 s hold time tests at 10 MPa, and 3 s hold time at 27.6 MPa. of the significant role played by thermally activated creep processes in determining the mechanical properties, it is important to use test parameters such as mean stress, strain rate, and temperature to characterize the behavior of solder. 3 . 3 . 1 Creep at - 4 0 ~

in Eutectic Solder

The homologous temperature, T/Tm, of eutectic solder at - 4 0 ~ is 0.51, so deformation due to creep processes was expected to be active at - 4 0 ~ But experimental confirmation has come only recently, and only recently have investigations shed any light on the change in failure behavior when a eutectic solder is subjected to cyclic loading. Figure 3.12 compares the strain and the envelope strain response of Pb-Sn eutectic alloys at - 4 0 ~ that were, respectively, creep tested at a constant load of 45 MPa and cycled between 0 and 45 MPa. The deformation in both cases is characteristic of behavior controlled by creep processes. A number of cyclic tests were also performed at different hold times. In general it is observed that strain rates of the cyclic tests decreased with decreasing hold times. These decreases in strain rate under cyclic loading are apparently due to the storage and recovery of anelastic strains, although strain hardening effects cannot be ruled out entirely. In order to identify changes in the failure behavior, fracture surfaces of specimens which had failed by a creep test were compared with specimens which had failed under cyclic loading conditions. Figure 3.13 compares the fracture surface of a eutectic alloy subjected to a creep test at a load of 45 MPa and a eutectic specimen cycled between 0 and 45 MPa at a frequency of 0.5 Hz. Failure in both

68

MATERIALS FOR ELECTRONIC PACKAGING

0.3 A = Primary region B = Secondary region C = Tertiary region

0.2

03

0.1

c # e , I ,v-

0.0

9

I

100

"

I

200

Time (sees) 0.3

(b) A = Primary region

region region

B = Secondary C = Tertiary

0.2 -J

0.1 A

0.0

0

~

B

C

10000

20000

Time (secs) Figure 3.12 (a) Creep curve of eutectic Pb-Sn at a stress of 45 MPa and a temperature of -40~ (b) Envelope strain curve of a eutectic specimen cycled at -40~ between 0 and 45 MPa at a frequency of 0.5 Hz.

specimens occurred due to void growth and coalescence. No difference in the fracture surface is discernible between the specimen subjected to a creep test and the specimen subjected to a cyclic loading test. Close examination of the fracture surface of the cyclic test did not reveal any signs of river lines or fatigue striations, which would indicate low temperature crack propagation.

Determining the Damaging Strains which Cause Failure in Pb-Sn Solders 6 9

Figure 3.13(a) Fracture surface of a eutectic Pb-Sn alloy which failed under a constant load (creep) test at - 4 0 ~

Figure 3.13(b) Fracture surface of an eutectic Pb-Sn alloy which failed under cyclic loading conditions at - 4 0 ~

70

MATERIALS FOR ELECTRONIC PACKAGING

3 . 4 Effect of Anelastic Strains on Accelerated Test Results During cyclic loading, anelastic strains are stored along with creep strains during the time spent on load [19-21,44,45]. If the hold time in the accelerted cycle is shortened to the extent that a significant portion of the total strain stored during the on-load hold time is anelastic, then the overall damage storage rate will decrease rather than increase. The decrease in the damage production rate occurs because the anelastic strains stored during the on-load hold time are recovered during the off-load hold time and have to be stored again during the next cycle. Therefore, a significant portion of the time on load is spent storing recoverable strains, which effectively reduces the envelope strain rate as the frequency of cycling is increased. At hold times significantly greater than the anelastic relaxation times, creep strains dominate the deformation behavior and the strain rate approaches that of a creep test. Thus, accelerating tests by decreasing the hold times beyond the point where creep strains are suppressed results in a decrease in the damage production rate, clearly defeating the purpose of the test. Furthermore, extrapolating results of tests done at high frequencies to real-life situations, where the loading rates are very slow, will result in a non'conservative estimate of lifetimes. The influence of anelastic strains during cycling can be measured by normalizing the strain rates of a cyclic test using a static creep test. The stress at which the creep test is performed is equal to the maximum stress used under cyclic loading conditions. If the normalized strain rate is close to one, then the hold times are long enough for storage and recovery of anelastic strains not to suppress the creep strains significantly. If the normalized strain rate is much less than one, the creep strains have been suppressed. Figure 3.14 shows that anelastic strains suppress creep at high frequencies in Pb-Sn solders of different compositions and at different temperatures. The presence of anelastic strains imposes a cutoff frequency beyond which the creep strains are significantly suppressed, indicated by a sharp decrease in the normalized strain rate. Accelerating tests beyond the cutoff frequency will result in nonconservative estimates of lifetimes. The methodology described in Section 3.3 allows us to separate the influence of the anelastic strains and to.measure only the nonrecoverable strains stored per cycle. In particular, the envelope strain curve of tests performed even at very high frequencies is a measure of only the nonrecoverable strains stored in the material. Hence, by using load-controlled cycling data the deformation response of the material can be studied even over frequencies where the storage and recovery of anelastic strains has a pronounced effect on the envelope strain rate.

3 . 5 Lifetime Predictive Equation for Pb-Sn Solders When the nonrecoverable strain per cycle, enr, is plotted against the number of cycles to failure for each of the various systems investigated, it is seen that the data in each case follow a simple relationship between the nonrecoverable strain stored per cycle and the number of cycles to failure. It is surprising to see how

Determining the Damaging Strains which Cause Failure in Pb-Sn Solders 7 1

1.0

o 63/37, 0-13.8 MPa, T=24~ m 63/37, 0-45MPa, T=-40~

9 63/37, 0-9MPa, T=100*C

0.8

9 81/19, 0-13.8 MPa, T=24"C 13 90/10, 0-8 MPa, T=160*C 9 90/10, 0-13 MPa, T=24"C

0.6

ecyclic ~creep

0.4

0.2

0

o

9 Q

0.0

0-2

. . . . . .

"1

10-1

9

9

9 ....

J~

10 0

.

.

.

.

.

.

.

.

I

101

13

13 9

9

9

. . . . .

I

10 2

9

9

9

9 "'"

10 3

Hold time (sec) Figure 3.14 Pb-Sn solders of different compositions subjected to load-controlled cycling at temperatures ranging from -40~ to + 160~ show suppression of creep strains by anelastic strains.

the data from all the systems fit the same straight line [46]. Figure 3.15 shows the result of plotting all the data points together. The equation of the line which fits the above data is a Coffin-Manson relationship [47,48] and is given below: enrN~ ~ = 0.15

(3.5)

where enr is the sum of the plastic and creep strain per cycle and Nf is the number of cycles to failure. The most important aspect of the above set of data is that it seems to be correlated by a single equation, even though the materials had different compositions, different initial microstructures, and were tested at frequencies ranging from 1.67 Hz to 0.00167 Hz at temperatures varying from - 4 0 ~ to + 160~ 3.5. I Failure Criterion: Damaging Strain Stored in the Secondary Region of the Envelope and Creep Strain Curve To understand why the data seem to be following a single equation over widely varying conditions, it is important to characterize what is being measured and used as the failure criterion. The Coffin-Manson exponent in equation (3.5) is very close to 1, and this agrees with our observation that creep is the primary

72

MATERIALS FOR ELECTRONIC PACKAGING

10 0

I 9 Pure Pb, As cast, 0-5MPa, T=24~

= 90/10, As cast, 0-13 MPa, T=24~

10"1

9 90/10, DS*, 0-13 MPa, T=24"C

10-2

9 90/10, AS cast, 0-8 MPa, T=160~

13

9 90/10, Aged, 0-8 MPa, T=160*C

10"3

9 81/19, AS cast, 0-13.8 MPa, T=24~ []

10-4

63/37, AS cast, 0-27.6 MPa, T=24~

9 63/37, AS cast, 0-13.8 MPa, T=24~ 9 63/37, As cast, 0-45 MPa, T=-40C

10-5

I

DS* = Directionally Solidified

[] 10-6 10-7 10-8

0 "1 .... 10'13 '

'

'

9 '

.... 10' 1" ..... 10'~; .

.

.

.

.

.... 10' 3 .

..... 10'4'

10 5

9 "'"'"1

'

"""'I

"

10

""'

1

Nf Figure 3.15

Pb-Sn solders of different microstructures and compositions tested under various conditions show similar deformation and failure behavior.

failure mode in these systems. Furthermore, taking the exponent to be equal to 1, the equation is seen to suggest a linear accumulation of damaging strain per cycle up to a critical value at which the material fails. That is to say, the critical amount of damaging strain stored in the secondary region before a material fails is a constant and is equal to 0.15 (15%). Hence, the nonrecoverable strain stored in the secondary region is apparently responsible for causing the damage which leads to failure in the solder joints. However, as will be shown in the following section, the critical amount of secondary strain is not constant over all conditions.

3 , 5 . 2 Effect of Hold Times and Temperature on the Creep Strain Stored in the Secondary Region The data for various compositions under varying conditions were analyzed to check for differences in the permanent strain stored in the secondary region. The data were separated and analyzed on the basis of composition, temperature, and hold times. No significant differences were observed between data sets separated on the basis of composition. However, the data separated on the basis of hold

Determining the Damaging Strains which Cause Failure in Pb-Sn Solders 7 3

0.20 [] 63/37, 0-13.8 MPa, T=24"C 9 63/37, 0-27.6 MPa, T=24"C

0.16

9 81/19, 0-13.8 MPa, T=24"C

0.12

0.08

O

0.04 []

0.00 10"1

9

[]

9

9

9

,=|w

I

10 0

9

9

9 = w w n

I

101

9

9

9

===n

I

10 2

9

9

9 ==1=

10 3

Hold time (sees) Figure 3,16

The permanent strain stored in the secondary region increases with longer

hold times.

times and temperatures show that the total secondary strain to failure is dependent on hold times and temperatures. Figure 3.16 shows the secondary strain to failure for the eutectic and the 81Pb-19Sn compositions cycled under load-controlled conditions at room temperature. At short hold times, the total secondary strain to failure lies between 2 and 5%, whereas at long hold times it varies between 10 and 16%. In the 19Pb-10Sn system the trend towards increasing secondary strain to failure with increasing hold times is equally evident; the strain to failure at the 1 s hold time is around 3%, whereas at longer hold times it lies between 8 and 15%. Figure 3.17 separates the data on the basis of temperature and hold times. The data at 24~ comprise tests done on eutectic, 81Pb-19Sn, and 90Pb-10Sn compositions; the data at 160~ are for 90Pb-10Sn. The strain to failure at 24~ is less than the strain to failure at 160 ~ Also, at 24~ the samples experiencing long hold times have a greater strain to failure. Clearly, the secondary strain to failure is a function of the temperature of testing and the hold time onload during each cycle. However, the secondary strain to failure is a weak function of the temperature and the hold time onload; it varies between 2 and 18% over the wide range of test conditions. If the failure criterion established in Section 3.5.1 is used, the behavior of the system can be described by /3nrNf

=

f(z, T)

(3.6)

where z is the time on load during each cycle and T is the temperature. Considering

9'4

MATERIALS FOR ELECTRONIC PACKAGING

~

~

O Holdtimes> I0 sccs,T=160~ [] Hold tbn.es > 10 sex.s,T=24~

-4 OJ

-5

9

I

0

9

1

I

9

I

2

9

3

I

9

I

4

9

5

I

9

6

Log (NO Flgure 3 . 1 7 to failure.

Plot showing temperature and frequency effects on the number of cycles

OJ

o.

10

2

'

I

0

'

I

2

'

i

4

'

I

6

Log (Nf) Figure a.18

All the data can be bounded by equations (3.7a) and (3.7b).

Determining the Damaging Strains which Cause Failure in Pb-Sn Solders 75

that f(~:, T) is a weak function varying between 2 and 18%, all the data can be bound by the following equation: e,r Nf = 0.02

(3.7a)

e,r Nf = 0.18

(3.7b)

Figure 3.18 clearly shows that all the data points do fall within the bounds of equations (3.7a) and (3.7b). Although the above data do show a definite dependence of the secondary strain to failure on r and T, more work needs to be done to characterize this dependency.

3.6 Summary The Pb-Sn system has time-dependent recoverable and nonrecoverable strains which have a complex relationship with time, temperature, stress, and composition and are therefore difficult to model. The presence of these strains makes it difficult to identify an experimental parameter which could be used as a measure of the damaging strains within the solder. Most of the work involved in relating the number of cycles to failure with the "plastic" strain stored per cycle is based on strain-controlled cycling data. Measurements of damaging strains based on the hysteresis loop generated during cyclic strain-controlled tests are not accurate because it is not possible to separate the effects of time-dependent recoverable anelastic strains. The error in the measurement of the damaging strains becomes more acute when the percentage of anelastic strains is higher. By using load-controlled cycling data it is possible to separate and measure the sum of just the damaging strains. Figure 3.15 shows that the methodology used to calculate the damaging strains gives a measure of the damage which can be correlated over a wide range of conditions. Once the complicating effects of anelastic strains are removed, the failure criterion for the Pb-Sn solders is seen to be simply a critical amount of secondary strain, betwen 2 and 18% depending on temperature and frequency. The fact that all the data points can be correlated over such a wide range of conditions confirms that failure is primarily caused by strain due to creep processes. Equation (3.6) shows that failure in the system occurs by the linear addition of a known amount of damage until a critical sum is reached. Hence, the methodology used to calculate the damaging strains and the failure criterion used to correlate the damage clarify that creep strains are responsible for the damage leading to failure in solder and provide a criterion truly representative of the damaging strains in the solder.

Acknowledgment We acknowledge the work done and guidance provided by the late Professor John K. Tien.

76

MATERIALS FOR ELECTRONIC PACKAGING

References

1. J. Lau, R. Subrahmanyan, D. Rice, S. Erasmus, and C. Li, J. Electronic Packaging 113(2), 128-148 (1991). 2. W.T. Cooley and A. Razani, J. Electronic Packaging 113(2), 156-163 (1991). 3. J. Lau, S. Gowalkar, S. Erasmus, R. Surratt, and P. Boysan, J. Electronic Packaging 114(2), 169-176 (1992). 4. W. Engelmaier, in Proc. 14th Int. Electronics Packaging Conf., Baltimore MD, Oct. 1984. 5. W. Engelmaier, IEEE Trans. Components, Hybrids, and Manuf. Technol. 6(3), 232-236 (1989). 6. W. Engelmaier, Circuit Worm 11, 61-69 (1985). 7. W. Engelmaier, A.I. Attarwala, IEEE Trans. Components, Hybrids, and Manuf. Technol. 12(2), 284-296 (1989). 8. S. Vaynman, M.E. Fine, and D.E. Jeannotte, Based Solder, Metall. Trans. 19A 1051-1059 (1988). 9. S. Vaynman and M.E. Fine, in Solder Joint Reliability: Theory and Applications, edited by J.H. Lau, Van Nostrand Reinhold, New York, 1991, pp. 225-265. 10. L.R. Fox, J.W. Sofia and M.C. Shine, IEEE Trans. Components, Hybrids, and Manuf. Technol. 8, 275-282 (1985). 11. H.D. Solomon, Brazing and Soldering 11, 68-75 (1986). 12. H.D. Solomon, in Low Cycle Fatigue of 60/40 Solder-Plastic Strain Limited vs. Displacement Limited Testing, Electronic Packaging Materials and Processing, edited by J.A. Sortell, ASM International, Materials Park, Ohio, 1986, pp. 29-49. 13. A.I. Attarwala, J.K. Tien, G.Y. Masada, and G. Dody, J. Electronic Packaging 114(2), 109-111 (1992). 14. R.C. Weinbel, E.A. Schwarzkopf, and J.K. Tien, Scripta Met. 21 1165-1168 (1987). 15. J.K. Tien, B.C. Hendrix, and A.I. Attarwala, IEEE Trans. Components, Hybrids, and Manuf. Technol. 12(4), 502-505 (1989. 16. B.C. Hendrix, 1989, "The Interaction of Creep and Fatigue in Lead-Tin Solders," Ph.D. Thesis, Columbia University, New York, 1989. 17. R.C. Weinbel, J.K. Tien, R.A. Pollak, and S.K. Kang, J. Mater. Sci. 22 3901-3906 (1987). 18, B.C. Hendrix, J.K. Tien, S.K. Kang, and T. Reiley, in Effects of Load and Thermal Histories, edited by P.K. Lau, TMS, Warrendale, PA, 1987, p. 139. 19. J.K. Tien, B.C. Hendrix and A.I. Attarwala, J. Electronic Packaging 113 115-120 (1991). 20. J.K. Tien, B.C. Hendrix, and A.I. Attarwala, in Solder Joint Reliability: Theory and Applications, edited by H. Lau, Van Nostrand Reinhold, New York, 1991, pp. 279-305. 21. A.I. Attarwala, "A New Methodology to Measure the Damaging Strains in Lead/Tin Solders," Ph.D. Thesis, University of Texas, Austin, 1992. 22. N.F. Enke, T.J. Kilinski, S.A. Schroeder, and J.R. Lesniak, in Proc. 39th Electronic Components Conf., 1989, pp. 264-272. 23. N. Nir, T.D. Dudderar, C.P. Wong, and A.R. Storm, J. Electronic Packaging 113(2), 92-101 (1991). 24. R.N. Wild, Welding Res. Suppl. Nov. 1972, p. 521. 25. R.N. Wild, "Some Fatigue Properties of Solder and Solder Joints," IBM No. 74Z000481, presented at INTERNEPCON, Brighton, UK, Oct. 1975. 26. P.M. Hall, Solid State Technol. Mar. 1983, pp. 103-107. 27. K.C. Norris, and A.H. Landzberg, IBM J. R&D, 13(3), 266-271 (1969). 28. B.P. Kashyap, and G.S. Murty, Mater. Sci. Eng., 50, 205-213 (1981). 29. A. Dasgupta, C. Oyar, D. Barker, and M. Pecht, J. Electronic Packaging 114(2), 152-160 (1992).

Determining the Damaging Strains which Cause Failure in Pb-Sn Solders

77

30. J.R. Wilcox, R. Subhramanyan, and C. Li, Microelectronic Packaging Technology, Proc. 2nd A S M Int. Electronic Materials and Processing Congress, Philadelphia PA, Apr. 1989, pp. 203-211. 31. R. Subhramanyan, J.R. Wilcox, and C. Li, Microelectronic Packaging Technology, Proc. 2nd A S M E Int. Electronic Materials and Processing Congress, Philadelphia PA, Apr. 1989, pp. 213-221. 32. S. Knecht and L.R. Fox, IEEE Trans. Components, Hybrids, and Manuf. Technol. 13(2) 424-433 (1990). 33. M.M Ahmed and T.G. Langdon, J. Mater. Sci. Lett. 2, 337-340 (1983). 34. R. Arrowood and A.K. Mukherjee, Mater. Sci. Eng. 92, 33 (1987). 35. F.A. Mohamed and T.G. Langdon, Acta Metall. 23, 697-709 (1975). 36. H.J. Frost, L.R. Patrick, and S.D. Lutender, "Microstructure and Mechanical Properties of Lead-Tin Solder Alloys," presented at the ASM Conference on Electronic Packaging, Minneapolis MN, Apr. 1987. 37. H.J. Frost and G.J. Stone, in Microelectronic Packaging Technology, Proc. 2nd A S M Int. Electronic Materials and Processing Congress, Philadelphia PA, Apr. 1989, pp. 121-127. 38. D. Grivas, K. Murty, and J.W. Morris, Acta Metall. 27, 731-737 (1979). 39. D.R. Frear, D. Grivas, M. McCormack, D. Tribula, and J.W. Morris, "Fatigue and Thermal Fatigue of Pb-Sn Solder Joints," Conference on Electronic Packaging, Minneapolis MN, Apr. 1987. 40. D.R. Frear, D. Grivas, and J.W. Morris, J. Met. June 1988, pp. 18-22. 41. Z. Mei, J.W. Morris, and M.C. Shine, J. Electronic Packaging 113(2), 109-114 (1991). 42. P.J. Greenwood, T.C. Reiley, V. Raman, and J.K. Tien. Scripta Met., 22, 1465-1468 (1988). 43. V. Raman and T.C. Reiley, Metall. Trans. 19A, 1533-1546 (1988). 44. J.K. Tien, B.C. Hendrix, and A.I. Attarwala, in Proc. NEPCON West, Anaheim CA, 1990, pp. 1353-1360. 45. J.K. Tien and A.I. Attarwala, M R S Symp. Proc. Mechanical Behavior of Materials and Structures in Microelectronics, Vol. 226, Nov. 1991, pp. 15-22. 46. A.I. Attarwala and J.K. Tien, Scripta Met. 26(12) (1992). 47. S.S. Manson in Fatigue at Elevated Temperatures, A S T M STP 520, ASTM, 1973, pp. 744-782. 48. S.S. Manson, Thermal Stress and Low Cycle Fatigue, McGraw-Hill, New York, 1966.

This Page Intentionally Left Blank

CHAPTER

4

Fluxless Soldering for Microelectronic Applications D. R. Frear, F. M. Hosking, D. M. Keicher, H. C. Peebles

4.1 Introduction Solder joints form the interconnections between the various levels of an electronic package; they are made between solderable metallized surfaces such as Cu, Ni, or Ni plated with Au. These metallized layers are typically heavily contaminated with metal oxides, carbon compounds, and other materials due to extended exposure to the manufacturing environment. A metal surface contaminated by these materials cannot be wet by solder. However, once this surface contamination is removed the solder wets the metallization and forms a metallurgically sound solder joint which will both hold the various electronic components in place and pass electrical signals. Historically, oxides have been removed from metallized surfaces during solder processes by the application of liquid fluxes. Flux (from the Latin 'to flow') is applied to a surface to assist in wetting by the solder. A flux consists of active agents dissolved or dispensed in a liquid carrier. The carrier for flux is typically alcohol-based with varying concentrations of acids or salts as activators. The function of the activators is to reduce base metal oxides. The acids most commonly used in fluxes are abietic acid (also present in the resin itself), adipic acid, and hydrochloric acid. Zinc chloride is a salt commonly found in inorganic fluxes. A schematic illustration of a flux in action is shown in Figure 4.1. It has four purposes: (1) to remove the oxide from the metallization, (2) to remove the oxide on the molten solder to reduce the surface tension and enhance flow, (3) to inhibit subsequent oxidation of the clean metal surfaces during soldering, and (4) to assist in the transfer of heat to the joint during soldering. In fact, to remove contamination and create a sound metallurgical joint only steps 1 and 3 are critical. For a more in-depth review of liquid fluxes see [1-5]. Fluxes can be applied by a variety of techniques. For electronic applications the fluxes are brushed or sprayed onto the assembly. Often the flux has a low viscosity so that it can readily flow into gaps where solder joints are present and coat the entire assembly. After a solder joint is formed, a flux residue remains. The residue consists of the 79

80

MATERIALS FOR ELECTRONIC PACKAGING

Figure 4.1 Schematic illustration of the oxide removal process of flux during soldering. The wetting angle is defined as the angle between the tangent to the surface of the solder and the substrate. carrier (resin) that has not evaporated, acid or salt deposits, and the removed oxides. The residue can bedeleterious to the long-term reliability of an electronic package if it is not removed. The resin can absorb water and become an ionic conductor which could result in electrical shorting and corrosion. Over a period of time the residual activator can corrode the soldered components and cause electrical opens. Furthermore, the flux residue, which still covers the entire assembly, is present not only on the surface but also underneath the components where inspection is difficult and the residue is hard to remove. Current practice is to remove flux residue using solvents that the flux, and its by-products, are soluble in. Many solvents are chlorofluorocarbons (CFCs); the most common is CFC-113. The solvent is applied by spraying or dipping in a bath. This solvent works well in removing flux residue but has recently been found to be environmentally hazardous. Molina and Rowland [6] found that CFCs deplete the stratospheric ozone layer. International concern over the depletion of the ozone layer led to the enactment of the Montreal Protocol. Initially signed in 1987 by 24 countries, it restricts the production and consumption of ozone-depleting chemicals. The protocol was later found not to be sufficiently restrictive, so the London amendment to the Montreal Protocol was signed in 1990 by 92 countries. Under this new amendment, CFCs will now be completely phased out by the year 2000 in developed countries and 10 years later in the entire world. In the United States, the Clean Air Act was amended to contain provisions pertaining to the Montreal Protocol and stratospheric ozone protection. Excise taxes are applied on chemicals that deplete the ozone layer. By 1995 the tax base amount on CFC-113 procurement will be $3.10/1b and it will increase by $0.45/lb every year thereafter [7]. In a typical surface mount soldering process on a printed circuit board, an average of 0.5 lb of CFC-113 is consumed per board. Therefore, there are strong economic and environmental incentives to develop alternative cleaning processes that do not use ozone-depleting chemicals or preferably to develop a soldering process that uses no flux and eliminates the need for hazardous solvents. Whatever the process, the solder joints need to be metallurgically sound and have at least the same cleanliness as those made with

F/ux/ess Soldering for/Hicroe/ectronic Applications

81

traditional flux and solvent cleaning procedures. Solvent substitution processes are being actively explored and are summarized in depth elsewhere [8-10]. This chapter presents fluxless soldering alternatives that have been explored at the Sandia National Laboratories (SNL) Center for Solder Science and Technology: fluxless laser soldering, activated acid vapor fluxless soldering, and laser ablative fluxless soldering (LAFS). The manufacturing process is described for each along with experimental details. The chapter concludes with electronic packaging applications where each process can be an attractive alternative to traditional flux soldering.

4.2 Fluxless Laser Soldering Laser soldering typically involves the melting of a preplaced, or fed, solder preform with a directed CO2 or Nd:YAG laser beam [11,12]. Rapid heating and cooling of the solder joint produces a very fine microstructure with reduced intermetallic formation. The process is highly automated and offers improved process control. Higher strength solder joints are possible since the localized heating of a laser allows the use of solder alloys with higher melting temperatures without damaging nearby materials. Solder mixing with other solder joints of different alloy compositions can also be avoided because of this localized heating effect. This paper will discuss the SNL development of fluxless laser soldering [ 13]. Fluxless laser soldering enhances product reliability by eliminating entrapped, corrosive flux residues within a sealed package.

4.2.1 ExperimentalProcedure When developing the working limits of the laser soldering process, it is necessary to first characterize the energy distribution of the laser beam. The effect of the base surface on the absorption of the laser energy is also important and determines where the laser beam is focused. For example, Au surfaces are highly reflective at the fundamental wavelength of an Nd:YAG laser and are difficult to heat quickly to the desired temperature. This condition consequently presents a problem when soldering Au-plated components. Since solder alloys typically have better absorption properties than Au, the solution is to direct the laser beam on the solder alloy and conduct heat from the solder to the base surface. A 100 W, continuous wave (CW) Nd:YAG laser was used to determine the wetting behavior of fluxless laser soldered joints. The Nd:YAG laser emits light at a wavelength of 1.06 ~tm and is ideal for soldering because of the relatively high absorption of the laser energy by solder alloys. The laser system was equipped with a computer controlled x-y directional stage and a heating platform for preheating of the test samples. The system also had a coaxial video monitor to assist in alignment of the laser beam relative to the target area and for viewing of the immediate region around the laser heated zone. A schematic of the system is shown in Figure 4.2. A parametric test matrix was designed to show the feasibility of laser soldering

82

MATERIALS FOR ELECTRONIC PACKAGING

Laser Beam Solder Joint Heating Stage Electronic Device X-Y Stage

Figure 4.2

Process schematic for laser soldering, 100 W CW Nd:YAG.

Au/Ni plated Kovar closure joints. Kovar (nominally 53Fe-29Ni-17Co-0.5Mn, wt.%) is generally very difficult to directly wet with solder unless a very aggressive, corrosive flux is applied. Since most active fluxes are not permitted during electronic soldering, Kovar is typically electroplated with a 5.0/tm (200/tin.) layer of Ni followed by a 1.2/tm (50/tin.) overplating of Au to enhance its solderability. This metallization scheme is also critical to the success of this fluxless laser soldering process and was used throughout the study. The noble Au surface prevents oxidation of the underlying metal before and during soldering. Two solder alloys were evaluated; 80In-15Pb-5Ag and 63Sn-37Pb. The 80In-15Pb-5Ag alloy has a melt range of 142-149~ while the 63Sn-37Pb alloy is a eutectic and melts at 183~ Solder preforms nominally 0.76 mm (0.030 in.) wide and 0.125 mm (0.005 in.) thick were prepared from commercially supplied stock. Two flat Au/Ni Kovar plates of different thicknesses were fixtured perpendicular to each other (L-joint) with a 45 ~ taper on the thicker of the two mating surfaces to accommodate the placement of the solder preform. The base plate thicknesses were 0.76 mm (0.030 in.) and 1.78 mm (0.070 in.). The fixtured samples (with preforms) were preheated to l l0~ before soldering. Soldering was done without fluxing in a protective reducing gas cover of 3-5 vol. % hydrogen in argon. Laser power, laser beam focused spot diameter, and part travel speed were the experimental variables. The laser power was 30-100 W, the laser spot diameter was 0.38-0.88 mm (0.015-0.035 in.), and the part travel speed was 2-17 mm/s (5-40 in./min). The experimental midpoint was 65 W, 0.88 mm (0.035 in.), 9.5 mm/s (22.5 in./min). The specific test conditions are listed in Table 4.1. The soldered samples were visually inspected for solder wetting and flow. The joints which exhibited satisfactory wetting were then metallographically characterized. 4 . 2 . 2 Results a n d Discussion

Previous experiments [ 11] revealed that the reflective properties of Au plating would inhibit the absorption of the laser energy into the base Kovar parts. Au has a relative absorption factor of 0.012 while the 63Sn-37Pb and 80In-15Pb-5Ag

Flux/ess Soldering for/Hicroe/ectronic App/icotions

Table 4.1

83

Laser processing conditions for soldering Ni-Au plated Kovar.

Laser power (W)

Laser beam spot size (mm)

Travel speed (mm/s)

30 30 30 30 65 100 100 100 100

0.38 0.38 0.88 0.88 0.88 0.38 0.38 0.88 0.88

2.0 17.0 2.0 17.0 9.5 2.0 17.0 2.0 17.0

alloys have an absorption factor of 0.28, a nominal absorption increase of over 20. The closure joint was consequently designed to utilize the absorption properties of the solder to conduct the laser energy to the solder joint region. Solder preforms with a 0.76 mm x 0.125 mm cross-section were placed into the tapered joint just before soldering with the 0.125 mm side facing the laser beam. To promote solder wetting without fluxing, a slightly reducing, controlled atmosphere was introduced over the fixtured parts to protect the base and solder alloy surfaces during heating. The cover gas prevents oxidation in air of the underlying Ni layer; oxidation would prevent wetting of this surface by the molten solder alloy. Thermodynamic data suggest the higher temperatures of laser soldering in an inert or reducing atmosphere can significantly enhance the reduction of most metallic oxides (eg. Cu, Ni, Fe, Sn, and Pb) [ 14,15]. This effect is especially noticeable above 350~ Since the laser heated region is very localized, the process is ideal for fluxless soldering. The Au/Ni plated Kovar solder joints were visually inspected to assess the quality of solder wetting/spreading. The wetting results for the 80In-15Pb-5Ag and 63Sn-37Pb alloys are summarized in Figure 4.3. Wetting was qualitatively ranked from poor to good and was dependent on the degree to which the gap of the joint was filled by solder. Wetting was generally observed to be better with 63Sn-37Pb than with 80In-15Pb-5Ag. The results were consistent with the wetting behavior normally expected during conventional soldering of these alloys on Au with a flux. Good solder joints were obtained at the higher laser power setting for both solder alloys. Poor wetting generally occurred at the lower 30 W power level with very irregular to negligible solder flow. The higher power input generally contributed to greater heating and could potentially degrade heat-sensitive components if they were located next to the joint. The objective, therefore, was to adjust the heating parameters such that an acceptable joint is produced without damaging the performance of the device. There were two exceptions to the general trends noted above. The first was that the 30 W, 0.38 mm, 2.0 mm/s, 63Sn-37Pb samples gave adequate wetting.

84

MATERIALS FOR ELECTRONIC PACKAGING 6

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Figure 4.3 Relative wetting of 63Sn-37Pb and 80In-15Pb-5Ag solder alloys on Au-Ni plated Kovar with laser heating in a dilute hydrogen-argon reducing gas. Ranking order: poor (1) < spotty (2) < partial (3) < adequate (4) < good (5).

The smaller, laser focused spot and the slower travel speed concentrated the laser energy at the lower laser power setting and effectively heated the 63Sn-37Pb preforms. Similar wetting was not achieved with the 80In-15Pb-5Ag alloy. This result can be accounted for by the difference in interfacial tension between the base surface and the two solders. The second observation was that both solder alloys gave spotty to partial wetting with the 100 W, 0.88 mm, and 17 mm/s test parameter. The larger spot size and faster travel speed produced less heating and poorer wetting, even at the higher laser power value. After visually inspecting each laser soldered joint, samples were chosen from those exhibiting adequate or good wetting for metallographic analysis. Figure 4.4(a) shows an Au/Ni plated Kovar and 63Sn-37Pb solder joint made at 100 W with 0.88 mm spot size and 2.0 mm/s travel speed. The joint exhibited 9ood wetting with a very fine textured microstructure and small Au-Sn and Ni-Sn intermetallic precipitates dispersed throughout the joint. Similar results were observed with the 80In-15Pb-5Ag solder alloy, although wetting was not as extensive as with the 63Sn-37Pb alloy. Figure 4.4(b) shows a 100 W 0.38 mm spot size, 17.0 mm/s travel speed, 80In-15Pb-5Ag sample. Excessive intermetallic growth can result during laser reflowing of a solder joint since the process typically requires longer dwell times to remelt the joint. If the dwell time (or heat input) is too long, melting of the base metal can occur. The resulting microstructure is significantly altered and can drastically affect the joint properties. A reflow experiment demonstrating this problem was conducted on Au/Ni plated Kovar and 63Sn-37Pb joints by making multiple passes over a previously laser soldered sample. Electron probe microanalysis revealed that a

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narrow band of the remaining metallized layer and underlying Kovar was melted during the reflow experiment. Wavelength dispersive X-ray spectrometry identified AuSn 4 precipitates throughout the joint and a substantial quantity of feathery (Ni, Fe, Co)3Sn 2 precipitates in the solder where the base surface was melted. The AuSn 4 precipitates formed during the initial soldering operation and would affect the as-soldered joint properties. The (Ni, Fe, C0)3Sn2 precipitates formed on reaction between the base Kovar and Sn-Pb solder alloy and could influence the properties of the reflowed joint. 4 . 2 . 3 Summary

Laser heating can be applied to fluxless soldering of Au/Ni plated Kovar. Higher laser power, smaller laser beam focused spot size, and slower travel speed give the best wetting results. Some advantages of fluxless laser soldering are (1) higher joining temperatures and potentially stronger joints, (2) elimination of entrapped corrosive flux residues, (3) compliance with environmental restrictions on hazardous solvent use, and (4) automated processing and process control. Some disadvantages of laser soldering are (1) inhibited absorption of the laser energy by highly reflective materials, (2) conventional geometries may not be compatible with the process, and (3)overheating can produce unsatisfactory joint properties.

4.3 Activated Acid Vapor Fluxless Soldering Activated acid vapor fluxless soldering is a process in which liquid flux is replaced by a dilute solution of a vaporized acid in an inert carrier gas. By a strict definition, the acid v~/por is a flux in that its function is to reduce surface metal oxides in order to enhance solderability. However, the acid vapor leaves little residue that requires cleaning, as long as the acid concentrations are low. The process of acid vapor soldering involves passing the carrier gas and acid vapor over the metallized surface to be joined. The acid chemically attacks the surface oxide as the metal is heated, removing the oxide from the surface. In this way the surface is activated for wetting by the solder. The solder is introduced while the acid vapor flows across the joints and this protective atmosphere prevents reoxidation of the metallized surface. The process nominally involves the use of solder preforms but it can be applied to wave soldering, where assemblies are dragged through a molten solder bath. The parameters influencing the formation of solder joints using acid vapors have been investigated. Wetting was evaluated as a function of acid type and acid vapor concentration. The experimental techniques and solderability results discussed here show that acid vapor fluxless soldering is a promising production process.

Fluxless Soldering for/Hicroelectronic Applications

87

4.3.1 Experimental Procedure

4.3.1.1 Wetting Experiments Wettability here is defined as a measure of the degree to which a solid substrate can be covered by a molten metal (in this case solder). A way to quantify wettability is to measure the contact angle, 0, between the solder and the substrate. The angle 0 is defined in Figure 4.1. For a given volume of solder, the smaller the value of 0 the greater the extent of wetting. A straightforward way of measuring wetting is the sessile drop area-of-spread experiment. A small amount of solid solder, in the form of a sphere, is placed on a metallized substrate and heated to above the melting temperature of the solder. As the solder melts, the molten droplet spreads across the metallized substrate. The greater the amount of spreading the lower the wetting angle and the better the wettability. If the droplets are small their shape can be approximated as a spherical cap. If a solder drop is too large, gravity will flatten the top and the droplet will no longer be spherical. A numerical technique derived by Bashforth and Adams [ 161 can be used to determine droplet shape. The solder droplets in this study were kept small ( < 9 mg) so as to avoid the effects of gravity. An analytical solution for 0 can be derived geometrically. In a sessile drop, the area of spread of the molten droplet of solder can be used to calculate 0 using equation (4.1):

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V = volume of solder drop = mass/density A = area of spread of drop For this work V = (0.009 g)/(8.5 g/cc). The volume of the drop is known, and constant, and by measuring the area of spread the contact angle can be estimated. Additional data that can be derived from a sessile drop experiment are the wetting rate and the time to wetting. The wetting rate describes how quickly the solder droplet spreads and can be related to the metallurgical reaction between the solder and the substrate. The time to wetting is the time interval from solder melting to the onset of spreading. The time to wetting is a measure of how fast a surface oxide can be removed in a reducing (acid vapor) atmosphere, assuming no spreading occurs until all surface oxides are removed.

88

MATERIALS FOR ELECTRONIC PACKAGING

4.3.1.2 Fluxless Soldering Chamber A soldering chamber was used to evaluate the acid vapor soldering process and is shown schematically in Figure 4.5. The chamber had gas inlet and outlet ports along with a glass-covered viewing port. Evacuation was performed using a mechanical pump. Specimens were heated using a resistive plate inside the chamber. The temperature was controlled by digital feedback electronics. The sessile drop experiments were performed inside the vacuum chamber and viewed through the glass port. The spread of the sessile drop was recorded on videotape. The video images were digitized and analyzed for area of spread (which gives the wetting angle) as a function of time at temperature. 4.3.1.3 Acid Vapors To perform acid vapor fluxless soldering three requirements must be met: 1. The acid must be able to reduce the relevant surface oxides in a vaporized form at soldering temperatures (~ 220~ manufacturing concern. 2. The acid vapors must react quickly, on the order of a few seconds, manufacturing concern. 3. The vapors must be reactive enough to reduce metal surface oxides but without causing corrosion on any part of the soldered assembly, reliability concern. The reducing agents that best satisfy these requirements are shown in Table 4.2. Formic and acetic acids were chosen because they boil at low temperatures, which allows them to be in gas form during solder processing.

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Figure 4.5 Schematic diagram of vacuum chamber configuration used for 60Sn-4OPb sessile drop wettability tests.

Flux/ess Soldering for/Hicroe/ectronic Applications

Table 4 . 2

89

Characteristics of reducing agents used for acid vapor fluxless soldering.

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Concentration (vol.%) Meltingpoint (~

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Hydrogen is gaseous at room temperature and can be easily introduced into the vacuum chamber for solderability tests. The acetic and formic acids had to be introduced via a bubbler. The inert carrier gas is aerated through a bath of formic or acetic acid. While passing through the bath the inert gas and the acid intermix to form a vapor. The concentration of the acid varies as a function of the vapor pressure which, in turn, is temperature dependent. Therefore, by varying the acid bath temperature, the acid vapor concentration varies. The acid vapor concentrations used are also listed in Table 4.2. The acid vapors pass over the heating stage and sessile drop specimen. Heating the stage and sample also heats the vapors; this increases the reactivity of the acid, which increases the oxide reduction rate and extent of reaction. Sessile drop tests were performed with 60Sn-40Pb solder in the vacuum chamber to explore the effect of time to wetting and wettability as a function of acid type, concentration, and metallization. The soldering temperature used was 220~ The metallizations characterized were plated layers of Ni, Cu, and Au/Ni on A1 coupons that had dimensions of 0.95 cm x 0.95 cm. 4 . 3 . 2 Results a n d Discussion

No wetting was observed in tests with forming gas. At 220~ hydrogen has a low reaction rate for reducing metal oxides and is consequently not suitable for soldering. At higher temperature (> 350~ the hydrogen reduces metal oxides rapidly but these temperatures could damage electronic components. Therefore, forming gas is not a suitable option for in situ fluxless soldering. However, if the metallized surfaces were cleaned by some other method prior to soldering, the forming gas could act as a blanket that displaces oxygen in the chamber and prevents oxidation during soldering. The formic and acetic acids provided better wetting on the Au/Ni and Cu metallizations. In the concentrations studied, the Ni metallizations could not be wet by formic acid vapor or by acetic acid vapor. The following is a discussion of test results for time to wetting, a measure of the reduction rate, and area of spread, a measure of the degree of wetting.

4.3.2.1 Time to Wetting The time to wetting results for formic acid are shown in Figure 4.6, and those for acetic acid vapor are shown in Figure 4.7. The data show the time between the solder melting and the onset of spreading recorded as a function of acid vapor concentration.

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Plot of the time to wetting as a function of acetic acid vapor concentration for Au/Ni and Cu metallizations.

The formic acid vapor allowed the immediate wetting of the Au/Ni substrate by 60Sn-40Pb solder. This indicates that surface contamination on the Au is very thin and is easily removed. The oxide layer on the Cu is substantial and rapid wetting is observed only in acid vapor concentrations greater than 4%. At vapor concentrations less than 4%, there is insufficient acid to allow wetting. The results of time to wetting with acetic acid vapors exhibit similar behavior for both the Cu and Au/Ni metallizations, Figure 4.7. With increasing acid vapor concentration, the time to wetting decreases to a minimum at a concentration of 1.5% then increases as concentrations increase above 1.5%. Both Au/Ni and Cu have this minimum at an acid concentration of 1.5%, but the time to wetting for Au/Ni is an order of magnitude shorter than for Cu. This behavior can be explained as a two-stage process. At concentrations below 1.5%, there is insufficient acid vapor present to rapidly reduce the metal oxides. Above 1.5%, the acid vapors reduce the surface oxides rapidly but then recombine with the pure metal to form what appear to be acetates. The acetate layers are inhibitors that slow both wetting and oxide formation. However, as shown in the contact angle results, the acetate only influences time to wetting, not the degree of wetting.

Fluxless Soldering for/Hicroelectronic Applications

91

4.3.2.2 Wetting Rate The wetting rate is an indicator of the extent of metallurgical reaction between the molten solder and the oxide-free metal surface. This rate is measured as the area of spread per unit time. The wetting rates for the acid vapors and metallizations studied were similar and independent of vapor concentration. This indicates that once the surface oxide is removed (and before the acetate is deposited in the case of acetic acid) solder spreads at the same rate on both Au/Ni and Cu. 4.3.2.3 Contact Angle Contact angle is a measure of the degree of wetting. A small contact angle corresponds to a large area of spread and good wettability. Plots of contact angle as a function of acid vapor concentration are shown in Figure 4.8 for acetic acid and Figure 4.9 for formic acid. These measurements were made after 60 s at 220~ for all samples. For acetic acid, Figure 4.8, there is little change in wetting angle as a function of acid vapor concentration. The Au/Ni metallization was found to show slightly

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Figure 4.10 Optical macrographs of 60Sn-40Pb solder wetting Cu for: (a) 1.5% acetic acid, (b) 4% formic acid, and (c) with RMA flux.

better wetting than Cu. All metallized samples soldered with acetic acid vapors have low contact angles and this indicates good wetting. Contact angles do not appear to be influenced by the formation of acetates. The contact angle results for formic acid vapors are shown in Figure 4.9. Similar to the acetic acid results, the Au/Ni metallization had better wetting than did the Cu metallization. For both metallizations, the contact angle was high (poor wetting) with less than 2% formic acid. Above 2% the contact angle decreased to a minimum of less than 10~ for both metallizations. The higher contact angles at lower acid concentrations are due to insufficient oxide reduction for the times tested. With longer times even the lower concentration of formic acid would result in contact angles of around 10~ The macrographs in Figure 4.10 show good wetting for a Cu metallized sample soldered in: (a) a 1.5% acetic acid atmosphere, (b) a 4% formic acid atmosphere, and (c) a sample soldered with rosin-based, mildly activated (RMA) flux. The acid vapor samples have wetting behavior similar to the RMA fluxed sample, but without the subsequent need for a cleaning step in the process. Figure 4.11 is a metallographic cross section of a Cu metallized sample soldered with formic acid. This micrograph shows there is a good metallurgical bond between the solder and the metallizations, as evidenced by the intermetallics at the interface.

4.3.3 Summary Acetic acid and formic acid can be used to reduce metal oxides of Cu and Au/Ni to form fluxless solder joints. The acid vapor reduces the oxide at soldering temperatures and leaves no residue that requires subsequent cleaning. Above a concentration of 1.5 % acetic acid vapor, metal acetates form that increase the time to wetting without degrading the final contact angle (after 60 s at 220~ Acetic acid concentrations below 1.5% do not reduce metal oxides rapidly enough. The

Fluxless Soldering for/Hicroe/ectronic Applications

93

Figure 4 . 1 1 Optical micrograph of the interface between 60Sn-40Pb solder and Cu fluxlessly soldered with formic acid vapors.

optimum concentration of formic acid is 4% on Cu metallizations and 1.6% on Au/Ni metallizations. Below these concentrations, the metal oxides do not reduce rapidly. At optimum formic acid and acetic acid vapor concentrations, metallurgically sound solder joints are formed with suitably small contact angles.

4.4

Laser A b l a t i v e Fluxless Soldering ~

Laser ablative fluxless soldering (LAFS) involves the use of very short pulses of high peak power laser radiation to remove metal oxides and other contaminants from joining surfaces [ 17]. The laser ablative cleaning step can induce wetting of copper, nickel, Kovar, and aluminum substrates by tin-based solders. Laser ablative cleaning and the subsequent joining process must be performed under a noble gas environment in a glove box or other type of controlled atmosphere chamber to prevent oxidation of the heated surfaces. A schematic diagram of the cleaning process is shown in Figure 4.12. A Q-switched, pulsed laser beam is mechanically scanned across each joining surface. The very short ( ~ 10 ns) pulses of laser radiation rapidly heat and vaporize very thin layers (10-500 nm) of surface material. The vaporized material rapidly condenses on contact with the cooler ambient gases above the substrate surface to form submicrometer solid particles. These particles are carried away from the ablated surface by a flowing stream of the inert gas. All particles are removed from the inert gas stream by filtration and aA disclosure of invention covering the process of laser ablative fluxless soldering has been filed with the US Department of Energy.

94

MATERIALS FOR ELECTRONIC PACKAGING

Figure 4.12

Schematic diagram of laser ablative cleaning.

disposed of as solid waste. Joint formation can be accomplished by solder tinning and reflow in the same inert gas environment. LAFS exhibits some very attractive process characteristics. No reactive chemicals of any type are required in the formation of a solder joint. As a result, there is no possibility that LAFS will leave any type of residue on the surface that could accelerate corrosion or any other form of material degradation. The incident laser energy can be adjusted to allow selective removal of the metal oxide film without significantly overetching the metal substrate. Etching terminates at the interface between the oxide film and the substrate due to the high surface reflectivity of the metal [18]. Because etching is limited to the oxide film, the waste generation rate of the laser ablative cleaning process is extremely small. For an oxide film formed on a copper surface in air at room temperature (typically 10 nm thick), the waste generation rate for the ablation step in this fluxless soldering process will be roughly 60 mg of metal oxide per square meter of surface cleaned. The following experimental results show that oxygen-free high conductivity (OFHC) copper can be wet by 60Sn-40Pb solder following removal of the surface oxide and other contamination by laser ablation. 4.4. I Experimental Procedure All substrates used as wettability test specimens in this study were 1 cm square coupons of O F H C copper 0.3 mm thick. Each substrate was oxidized by heating in air at 220~ for approximately 2 min until the surface exhibited a uniform brown tint. This surface tint corresponds to an oxide thickness of 20-40 nm [19]. The oxide film thickness normally encountered on air-oxidized copper solder pads in commercial electronics manufacturing is normally less than 10 nm thick.

Fluxless Soldering for Microelectronic Applications

95

Consequently, the oxidized substrates used in this study represent a conservative test of the cleaning step in the laser ablative fluxless soldering process. The laser ablative cleaning of copper substrates and subsequent wettability tests were performed in a stainless steel chamber under an atmosphere of noble gas. A schematic diagram of the chamber is shown in Figure 4.5. The copper substrates were placed in the chamber on a hot plate. The chamber was closed and evacuated to 0.1 torr to remove the ambient air. The chamber was then backfilled with noble gas to an absolute pressure of 625 torr. This evacuation/ backfill cycle was executed twice more to ensure that all the oxygen and nitrogen gas in the chamber had been removed. The noble gases used in this study were either 99.999% pure helium or 99.999% pure argon. Nitrogen gas cannot be used in the laser ablative cleaning step due to the very high gas temperatures (3 000-10 000 K) generated by the laser ablation process in the region just above the substrate surface. These temperatures are high enough to dissociate diatomic nitrogen resulting in rapid nitridation of the substrate surface. Laser ablative cleaning of copper substrates was accomplished by scanning a pulsed laser beam across the surface of the substrate. The coupon was maintained at a temperature of 220~ during the cleaning process. Any circulation of the noble gas in the chamber was due entirely to convection. The laser used for ablative cleaning was a Q-switched Nd:YAG laser with an output wavelength of 1.064 ~m a pulse length of l0 ns, and a pulse repetition frequency of l0 Hz. The irradiance profile of the laser beam was near gaussian in shape with a diameter between 1/e 2 intensity points of 5.9 mm. The pulse energy of the laser was 850 mJ. The laser beam was scanned across the substrate surface at a linear rate of 5 mm/s with a 5 mm separation between adjacent scan tracks. The beam was directed onto the copper substrate through a UV grade quartz window located in the top of the chamber. The beam was incident on the substrate surface at an angle of 2 ~ with respect to the surface normal to prevent optical feedback into the laser cavity. No beam focusing element was employed. The wettability of the laser-cleaned copper substrates was measured using the sessile drop method described earlier in this chapter. This wettability test measures the contact angle of the solder with the substrate under near equilibrium conditions. A decrease in contact angle corresponds to an increase in surface wettability. All wettability tests were conducted at a substrate temperature of 220~ Solder was placed in contact with the laser-cleaned substrate surface up to 1 min after completion of the laser ablative cleaning step. The solder was deposited on the substrate surface in the form of a small sphere using a pair of needle nose tweezers mounted on the end of a wobble stick. The tweezers were loaded with sufficient compressive force to hold the solid sphere but would release the ball once the solder became molten. The tips of the tweezers were oxidized to prevent the adhesion of molten solder. Each solder sphere contained 9 mg of solder composed of 60Sn-40Pb. The solder contained no chemical flux. The solder was allowed to equilibrate on the substrate surface at 220~ for 2 min then rapidly cooled to room temperature. The area of spread of the solder drop was measured at room temperature by planimetry from magnified optical photographs of the

96

MATERIALS FOR ELECTRONIC PACKAGING

copper substrates. The area of spread was converted to wetting angle using equation (4.1). 4 . 4 . 2 Results and Discussion

Four oxidized copper substrates were cleaned by laser ablation under a helium inert gas environment and six substrates were cleaned under an argon environment. The results of surface wettability tests on these substrates for 60Sn-40Pb solder are summarized in Table 4.3. The substrates cleaned under the two different gases show a remarkable difference in surface wettability. The area of spread obtained on a substrate cleaned under argon gas (sample # 8) is shown in Figure 4.13. The solder on this substrate formed a nearly spherical cap with an approximately round base. This result was typical of all solder droplets formed on copper substrates cleaned under argon gas. The solder contact angles calculated from the area of spread of the solder on these substrates ranged from 12 ~ to 22 ~ As a baseline for comparison, the contact angle measured for 60Sn-40Pb solder on O F H C copper in air using Alpha 611 flux (Alpha Metals Incorporated) was 23 ~ [20]. This is an RMA flux widely used in electronics manufacture. Figure 4.14 shows a scanning electron microscope (SEM) image of the interfacial region between the solder and the copper substrate at low magnification for a sample cleaned under argon gas (sample # 2). The dark region in the lower portion of the SEM image is the copper substrate. The lighter region in the upper portion of the image is the solder. The interfacial boundary on this sample is very fiat. No large gaps, voids, or cracks were observed between the solder and the substrate at any position along the interface. An optical micrograph of the interfacial region at higher magnification is shown in Figure 4.15. The surface of the sample has been etched with ASTM E407 # 26 ferric chloride to reveal the microstructure of the interface. The light region in the lower portion of the micrograph is the copper substrate. The dark region in the upper portion of the micrograph is the Toble 4.3

Summary of contact angle measurements for OFHC copper substrates cleaned by laser ablation under argon or helium gas. Sample #7 #9 # 13 #21 # 1 #2 #3 #4 #8 # 16

Inert gas

Area of spread (cm 2)

Contact angle (deg.)

He He He He Ar Ar Ar Ar Ar Ar

0.69 0.74 0.85 0.87 0.085 0.078 0.106 0.072 0.104 0.092

0.75 0.68 0.55 0.53 17 19 12 22 13 15

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Figure 4.13 Nine milligram 60Sn-40Pb solder droplet of OFHC copper substrate cleaned by laser ablation under argon gas. The graduations on the lower edge of the figure are spaced at 0.5 mm intervals.

Figure 4 . 1 4 Scanning electron microscope image of the copper-solder interface on a copper substrate cleaned by laser ablation under argon gas. The dark region in the lower portion of the image is the copper substrate. The lighter region in the upper portion of the image is the solder.

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Figure 4.15 Optical micrograph of the copper-solder interface for a copper substrate cleaned by laser ablation under argon gas. The surface of this sample received a standard ferric chloride etch. The light region in the lower portion of the micrograph is the copper substrate. The dark region in the upper portion of the micrograph is the solder.

solder. A thin intermetallic layer is clearly visible between the substrate and the solder. The intermetallic layer is composed of fingerlike projections whose growth appears to originate at the copper boundary and extend into the solder. These intermetallic grains exist in a range of sizes up to 5 pm in length and 2 pm in width and cover the entire interface between the substrate and the solder. The composition of the intermetallic layer measured by electron microprobe is 52 at.% Sn and 43 at.% Cu. The atomic ratio of tin to copper is a very close match to Cu6Sn 5. The reaction of tin with the copper substrate is thought to be necessary for the wetting of copper by tin-based solder alloys, and is a good indicator of strong metallic bonding between the solder and the substrate [21]. The area of spread obtained on a copper substrate cleaned under helium gas (sample #9) is shown in Figure 4.16. On this sample, the 9 mg solder ball has spread out to cover almost the entire surface of the copper coupon. Similar results were obtained for the other three copper substrates cleaned under helium gas. The area of spread of the solder on these surfaces was typically 7 to 12 times larger than the area of spread observed on surfaces cleaned under argon gas. This indicates the contact angle of 60Sn--40Pb solder on surfaces cleaned under helium is much smaller than the contact angle on surfaces cleaned under argon. The actual values calculated in Table 4.3 for the contact angle of 60Sn-40Pb solder on the substrates cleaned under helium gas are all less than 1~ However, these values are not

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Figure 4.16 Nine milligram 60Sn-40Pb solder droplet on OFHC copper substrate cleaned by laser ablation under helium gas. The graduations on the lower edge of the figure are spaced at 1.0 mm intervals.

expected to be very accurate because the geometric form of the solder droplet on the substrate surface does not approximate a spherical cap, and because the surface topography of the substrate is not planar. An SEM image of the interfacial region between the solder and the copper for a substrate cleaned under helium gas is shown in Figure 4.17 (sample # 13). The dark region in the upper portion of this SEM image is epoxy mounting medium. The lighter region in the lower portion of the image is the copper substrate. The solder is present as the bright layer directly above the copper. The boundary between the copper substrate and the solder on this sample is highly convoluted when compared to the boundary observed in Figure 4.14 for the copper substrate cleaned under argon gas. The maximum depth of the convolutions in Figure 4.16 is 50/~m. The solder has spread out into a very thin layer on this substrate as indicated by the area of spread value listed in Table 4.3. At all positions examined along the substrate surface, just sufficient solder is present to fill the depth of the convolutions. Examination of regions of the substrate surface on sample # 13 that

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Figure 4 . 1 7 Scanning electron microscope image of the copper-solder interface on a copper substrate cleaned by laser ablation under helium gas. The dark region in the upper portion of the image is the epoxy mounting medium. The lighter region in the lower portion of the image is the copper substrate. The solder is present as the bright layer directly above the copper.

were not covered by solder show the same degree of convolution. This indicates the convolutions were caused by the laser ablative cleaning process, not by reaction of the copper substrate with the elemental components of the solder. The transformation of the substrate surface to a highly convoluted state during laser ablative cleaning under helium gas dramatically increases the exposed surface area of the copper substrate. Based on the magnitude of the convolutions present in Figure 4.17, the surface area of sample # 13 is estimated to be greater than the surface area of sample # 2 by a factor of 10. The difference in surface topography between copper substrates cleaned by laser ablation under helium gas compared to substrates cleaned under argon gas explains the observed difference in apparent surface wettability between these two cases. The convoluted surface topography on the substrates cleaned under helium gas forms a densely packed, interconnecting network of grooves on the surface of the substrate. Each groove contains just enough solder to fill its depth. Very little solder is observed on top of the hills between the grooves. The confinement of the solder to the grooves on the surface indicates that capillary forces played a dominant role in the spreading of solder on these surfaces [22]. The enhanced spreading of solder observed on the copper substrates cleaned under helium gas is due primarily to this capillary effect. The copper substrates cleaned under argon gas show a much smoother surface topography. Consequently, the geometric effect of capillary forces on these surfaces is greatly reduced and less solder spreading is observed.

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4 . 4 . 3 Summary

The data listed in Table 4.3 indicate that the wettability by 60Sn-40Pb solder of OFHC copper surfaces cleaned under argon or helium gas by laser ablation equals or exceeds the wettability obtained on this substrate using a common RMA flux in air. Wettability tests are a strong indicator of whether or not a soldering process is capable of forming a functional solder joint with a given solder alloy-base metal system. However, the microstructure of the interface between the solder alloy and the base metal also has a strong influence on the strength of the solder joint. For copper substrates cleaned under argon gas, a cross section of the solder-copper interface reveals the presence of a Cu6Sn 5 intermetallic layer between the copper and the solder. No voids between the copper and the solder are observed. The presence of the Cu6Sn 5 intermetallic layer at the interface indicates that a good metallurgical bond has been formed between the solder and the substrate. Copper substrates cleaned by laser ablation under helium gas show a highly convoluted surface topography. The increased apparent surface wettability induced by laser ablation of the copper substrates under helium gas is the result of enhanced spreading of the solder over the laser-roughened surfaces as a result of capillary forces.

4.5 Summary and Examples The three techniques discussed in this chapter show that it is possible to produce metallurgically sound solder joints without using flux. None of the procedures will work under all conditions of soldering. However, there are applications where one of the procedures described can replace an operation that involves fluxing and subsequent cleaning. Some examples are discussed below.

4.5. I Hermetic Sealing of Lids

There are applications, specifically radar packages, where an electronic package needs to be hermetically sealed. The need to perform rework on the electronic components inside the package demands a removable lid, therefore soldering is the best choice. Typically the soldering operation is carried out using flux and soldering irons to provide the heat. Concerns over entrapment of flux inside the package, and possible related corrosion problems, make this application a candidate for fluxless soldering. Fluxless laser soldering has been performed effectively on Ni/Au plated lids for the hermetic sealing of radar packages. The laser procedure provided localized heat and minimized possible damage to the electronics.

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4 . 5 . 2 Surface Mount Technology

Acid vapor fluxless soldering could be commercially applied to the manufacture of surface mount technology (SMT) packages. SMT solder joints are usually made either by reflow of preforms or wave soldering. Fluxless soldering with acid vapors can be used in a reflow operation by running the reflow in a vacuum chamber with formic acid or acetic acid vapors. The heat can be applied by a hot plate or infrared light. Acid vapor fluxless soldering has already been commercially applied to wave soldering applications. The SEHO Company of Germany makes the Nitrogenius soldering machine, which uses formic acid vapors as a flux. The formic acid vapor is injected over the molten solder bath to help reduce oxides on the melt and on the metallizations of the printed wiring boards and components to be soldered. The great advantage of acid vapor fluxless soldering for SMT joints is that no flux can be trapped under packages, later to degrade long-term reliability. The use of acid vapors reduces reliability concerns and eliminates cleaning difficulties. LAFS can be performed with very high spatial resolution, complete control of beam size and position allows selective removal of surface oxides over complex surface patterns. Since the solder will not wet surfaces from which the oxide has not been removed, a simple mechanism is available for the control of solder spreading. The Q-switched laser also exhibits a very short duty cycle. As a result, the time-averaged laser power absorbed by the ablated surface is small, resulting in minimal heating ofjoining surfaces or adjacent structures. This allows application of the process on or near thermally sensitive components. The combination of high spatial resolution and low thermal impact makes LAFS an attractive process for SMT. 4 , 5 . 3 Solderability Restoration

Plated leads for electronic packages can lose their solderability if stored for long periods in aggressive environments (e.g., atmospheres containing sulphur or high humidity). Surfaces can become so contaminated that flux will not make them solderable. To avoid scrapping the packages, the solderability of the leads can be restored by removing the contaminated surface. Using the laser ablative cleaning process the contaminated layer can be removed and solderability restored without the need of flux.

Acknowledgments The authors acknowledge the microanalytical support of Alice Kilgo, Paul Hlava, Fred Greulich, and Nelda Creager; the technical input of Jim Jellison, A1 Romig, Fred Yost, and John Stephens; and the program support of Joan Woodard and Barry Granoff of the SNL Environmental and Manufacturing R&D Programs Directorate, and Clyde Frank of the DOE Office of Technology Development.

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References 1. R.J. Klein Wassink, Soldering in Electronics, Electrochemical Publications, Ayr, Scotland, 1984, Ch. 5. 2. J.F. Shipley, Welding Res. Suppl. 54, 357 (1975). 3. W. Rubin and B.M. Allen, Trans. Inst. Metal Finish 50, 133 (1972). 4. W. Rubin, in Molten Salt Technology, edited by D.G. Lovering, Plenum, New York, 1982, Ch. 8. 5. W. Rubin, Welding J. 61, 39 (1982). 6. M.J. Molina and F.S. Rowland, Nature 249, 810 (1974). 7. Department of Treasury, Ozone Depleting Chemicals, IRS publication 510. 8. M.C. Oborny, in Proc. 3rd Interagencv Cleaning and Control Seminar,1988. 9. M.C. Oborny, E.P. Lopez, and D.R. Frear, in Proc. Int. Conf. on Pollution Prevention." Clean Technologies and Clean Parts, Washington, D.C., 1990. 10. M.C. Oborny, E.P. Lopez, D.E. Peebles, and N.R. Sorensen, Solvent substitution for electronic assembly cleaning, in Solvent Substitution for Pollution Prevention, Noyes Data Corp., Park Ridge, NJ, 1993, pp. 142-146. 11. J.L. Jellison and D.M. Keicher, microsoldering and microminiature welding with lasers, in International Symposium on Microjoining, Welding Institute, Abington, Cambridge, UK, 1988, pp. 99-108. 12. C. Lea, Soldering & S M T 2, 13 (1989). 13. F.M. Hosking and D.M. Keicher, paper presented at the Spring 1991 Materials Research Society Symposium, Anaheim CA, 1991. 14. D.R. Milner, Br. Welding J. 90 (1958). 15. N. Bredzs and C.C. Tennenhouse, Welding Res. Suppl. 86, 189s-193s (1970). 16. F. Bashforth and J.C. Adams, Attempt to Test the Theories of Capillary Action, Cambridge University Press, 1883. 17. H.C. Peebles et al., in Proc. Int. Congress on Applications of Lasers and Electro-Optics, San Jose CA, 1991. 18. H.C. Peebles, N.A. Creager, and D.E. Peebles, in Proc. 1st Int. Workshop on Solvent Substitution, Phoenix AZ, 1990, p. 1. 19. U.R. Evans, The Corrosion and Oxidation of Metals." Science Principles and Practical Applications, St. Martin's Press, New York, 1960, p. 56. 20. P.T. Vianco, F.M. Hosking, and D.R. Frear, in Proc. Electronics Materials Processing Congress, Montreal, Canada, 1991. 21. F.G. Yost and A.D. Romig, Jr., Mater. Res. Soc. Syrup. Proc. 108, 385 (1988). 22. G.L. Bailey and H.C. Watkins, J. Inst. Metals 80, 57 (1951).

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CHAPTER5

The Effect of Microstructure on Fracture of M e t a l / Ceramic Interfaces Ivar E. Reimanis

5.1

Introduction

5. 1. I Motivation

Metal-ceramic interfaces are found in two principal areas in electronic packaging. Firstly, interconnections frequently require a metal wire or metal film to be bonded to a ceramic substrate. Secondly, composite materials are prime candidates for packaging materials [1], because of their ability to transfer heat and their high strength to weight ratio. The debonding of internal interfaces can control the overall mechanical properties of the composite [2], so it is of great importance to understand the fracture behavior of metal-ceramic interfaces. Ultimately, I believe tailorable interfaces will allow us to adjust the mechanical properties of composites, and to achieve interconnections of the minimum required strength. Fundamental understanding of metal-ceramic interface fracture is required for the development of new composites and material systems. Consider A1N; in recent years it has replaced A1203 as a packaging material for a variety of applications, due to its superior properties in transporting heat. However, the full application of A1N in electronic packaging requires its bonding to metals, for example through metallization [3]. Properties such as high thermal conductivity across the interface, low resistivity in the metal, and high AIN dielectric constant must be achieved while maintaining a strong bond. Presently, AIN is bonded to metals through the use of a glass frit [3] whose microstructure and chemistry determine the bond strength. By direct bonding it may be possible to eliminate processing steps as well as enhance the electrical and thermal properties of the interface. A better understanding of how metals are bonded to ceramics would help in designing such a direct bond. Despite the importance of metal-ceramic interfaces in the overall performance of the interconnection or composite, there has been very little work reported on the fundamental mechanisms of bonding and debonding. While mechanically interlocked interfaces may be responsible for producing strong bonds between 105

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MATERIALS FOR ELECTRONIC PACKAGING

A1N and metals [4], for example, the very rough interfaces result in undesired effects, such as increased electrical resistivity [3]. Ultimately a relatively fine microstructure may be desired, which would have significant topography to help increase the fracture resistance [5], but would not adversely affect the electrical properties. The search for an adequate interface requires fundamental understanding of bonding and the effects of features such as interface roughness on the resistance to bonding. 5~ 1.2 /Hicrosfrucfure and Fracture Energy

Many mechanical studies on material systems used in electronic packaging incorporate strength tests, such as the pull test or the steel ball drop test [6], which do not necessarily bare any relation to the fracture energy. While these strength tests may be simple and useful in choosing a particular material system for an application, they are usually not useful for explaining the mechanism by which the microstructure affects the overall strength. The fracture energy, on the other hand, can be directly related to the modifiable microstructural parameters. The fracture energy refers to the energy required to propagate an existing crack. Of the various factors which determine the fracture energy of metal-ceramic interfaces [7], the most basic is the thermodynamically reversible work of adhesion, Wad,

(5.1)

Wad -- ~c q- ~m - - ~i

where 7r ~m, and ~i are the free energies associated with the ceramic surface, the metal surface, and the interface, respectively. Wad represents the theoretically lowest possible value of the fracture energy. Irreversible factors such as chemical segregation, phonon dissipation, and plastic deformation contribute to Wad [7-9]; typical fracture energies for metal-ceramic interfaces are several orders of magnitude higher than Wad, due to plastic deformation in the vicinity of the crack tip. A few metal-ceramic systems are listed in Table 5.1 where Wad has been experimentally measured. The interface roughness also may contribute to the fracture energy depending on the state of stress; if a large enough shear stress component is present then asperity contact will shield the crack tip from the applied stress, thereby toughening the interface. Microstructural features considered here refer to the physical structures including the grain distribution, flaw populations, and interface topography at the

Table 5.1

Nb-A120 3 Au-A120 3 Cu-A12O 3

Metal-ceramic interfaces.

Wad(Jim 2)

Interface fracture energy, ['i (J/m2)

Reference

0.8 0.3-0.5 0.4-0.7

10-200 10-150 30-200

32, this work 9 37,38

The Effect of Microstructure on Fracture of Metal/Ceramic Interfaces

107

interface. Although chemical reactions involving particle inclusions and phase formation at the interface frequently control fracture behavior [10-1, I focus on metal-ceramic interfaces where no chemical reactions have taken place. Considering the large variety of interface microstructures this paper is by no means a broad overview; instead I have selected some specific topics related to problems in packaging situations. To discuss the effect of microstructure on fracture behavior in metal-ceramic interfaces, it is essential to know which parameters govern fracture; the microstructure in turn affects these parameters. The next two sections review interface fracture mechanics and modes of interface fracture before some specific microstructural effects are discussed.

5 . 2 Fracture Behavior 5 . 2 . I A R e v i e w o f Basic Interface Fracture Mechanics

This review is intended for those not well versed in fracture mechanics. It is confined to linear elastic fracture mechanics (LEFM) because LEFM can be used to describe the metal-ceramic interface problems considered here. Consider the crack tip in Figure 5.1 for a crack at an interface between materials 1 and 2. Under a normal applied load, the crack tip experiences a stress singularity and its amplitude is the stress intensity factor, K: ~ i j m_

(5.2)

Kf o~O)/x~ rcr

where trij is the stress at the crack tip, r is the distance from the crack tip and s is a geometric function. K may be separated into two components K~ and K., whose values depend on the state of stress. Thus, for loading which is purely normal to the crack plane (mode I loading), K may be characterized by K~ alone (K. = 0). However, the state of stress in bimaterial interface problems in engineering situations (eg., thin film decohesion or debonding of internal interfaces in composites) is typically mixed mode (both mode I and mode II loading) [11].

at ,r

crack tip

9 9 -r

Figure 5.1

A crack at a bimaterial interface.

Interface

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MATERIALS FOR ELECTRONIC PACKAGING

100

N3

t~

...................../....iii.................... I

Mode Mixity, Ig (= tan l K II/K l)

Figure 5.2

g/2

Fracture energy as a function of phase angle ~.

The mixture of mode I and mode II stresses at a crack tip in plane strain is characterized by the mode mixity, ~, where tan O = K , , / K ,

(5.3)

Thus, ~ = 0 ~ for K~I = 0, and ~ = 90 ~ for K~ = 0. When the crack advances, it does so when K is equal to a critical stress intensity, Kc, which is a material property dependent on temperature and sometimes the surrounding environment [12]. For a mode I crack (Kn - 0, ~ - 0 ~ in plane strain, the critical stress intensity factor Kc is also termed the fracture toughness, K~c. The critical stress intensity factor of a crack loaded in plane strain may be related to the release of elastically stored energy in the system during crack propagation through the critical energy release rate, Gc: Gc = K 2 E / ( 1 - v2)

(5.4)

where v is Poisson's ratio. Gc provides a measure of the fracture energy,Fi. In most cases F i is not the same for different values of the mode mixity, ~ [13-153. The fracture energy of interfaces typically increases with increasing ~ as shown in Figure 5.2. Thus, cracks loaded under shear exhibit a higher fracture energy than cracks loaded under normal loading. Knowledge of F i as a function of ~ (Fig. 5.2) is necessary to fully characterize the fracture behavior of an interface. Furthermore, the mode mixity as defined by equation (5.3) is also a function of properties of the system such as elastic modulus mismatch and thermal residual stress across the interface [16,17]. Even when the externally applied load is normal (mode I, - 0 ~ the elastic mismatch across the interface and the thermal residual stress changes the stress state at the crack tip such that ~ is nonzero. The next section shows how the value of ~ may determine the crack trajectory. For more detail on these effects the reader is refered to [16].

The Effect of A4icrostructure on Fracture of Metal~Ceramic Interfaces

109

5 . 2 . 2 Modes of Fracture in Metal-Ceramic Systems

In homogeneous materials, the state of stress always determines the crack trajectory: the direction of crack growth will always be such that the mode II stress intensity factor is zero (K. = 0) [17,18]. However, at bimaterial interfaces, crack growth may occur along the interface, even when K . 4: 0, if it is more energetically favorable than crack growth out of the interface. The two situations are illustrated schematically in Figure 5.3 where a metal-ceramic interface crack experiences mixed mode loading. The fracture energy of the interface is designated by 1-"i while that of the substrate is F s. When the interface is weak (FJF s smaller than a critical value), fracture occurs along the interface. For stronger interfaces (Fi/F s larger than the critical value) it is more energetically favorable for the crack to kink into the substrate, where it propagates along a K . = 0 path (Fig. 5.3(b)). Thus, the ratio of the interface fracture energy, I"i, and the substrate fracture energy, F~, is paramount in determining the crack trajectory [19]. Given a specific ratio, Fi/F~, for a metal-ceramic interface, whether or not a kink cracks out of the interface is determined by the mode mixity, ~. For many materials, even when the fracture energy of the substrate is approximately twice that of the interface (Fi/Fs ,~ 0.5), the mode mixity must be greater than about ~, ~ 40 ~ for crack kinking into the substrate [ 19]. Furthermore, the elastic modulus mismatch, the residual thermal stress, and the applied load determine the mode mixity, ~. Thus, failure of a metal-ceramic interface may occur by a number mechanisms depending on the energetics of different crack trajectories, as well as the microstructural features which may deflect cracks [13]. Different crack trajectories at interfaces are discussed in more detail by Hutchinson and Suo [16] and specifically for thin films by Thouless [13]. Most of the situations described here are confined to the case when the crack runs along the interface.

(a)

t

t (b)

~[~] ] ceramic !.".. 9

'Weak' Interface Figure 5.3

Crack trajectories for different situations.

. ....

,

'..".

.......:.:,

'Strong' Interface

I

9 I

1 10

MATERIALS FOR ELECTRONIC PACKAGING

Figure 5.4

Schematic of a ductile fracture surface.

5 . 2 . 3 Interface Fracture

Fracture along a metal-ceramic interface may occur in three basic ways [20]. First, fracture may occur by void formation and growth in the metal but ahead of the crack tip. The fracture surfaces from ductile interface fracture appear similar to fracture surfaces from homogeneous ductile metals; dimples from cup and cone features (Fig. 5.4) are indicative that fracture has occurred by void nucleation and growth. AI-AI20 3 is an example of an interface which fails in this way [20]. The second way a metal-ceramic interface may fracture is in a brittle manner, whereby decohesion at the crack tip occurs (eg., Mo-AI203 [21]). Brittle fracture does not necessarily preclude plasticity: dislocations may still be emitted while the crack advances. Fracture surfaces from brittle fracture are clean in the sense that no metal exists on the ceramic side. Thirdly, in some metal-ceramic systems void growth occurs ahead of the crack tip accompanied by brittle debonding (eg., Au-A1203 [9]). Criteria for the different fracture mechanisms depend on a complex variety of parameters, including the microstructure, the geometry, and the chemistry of the interface as well as the mechanical properties of the constituents. In some cases the microstructure may even determine whether crack propagation occurs in a brittle or ductile manner [10]. Whether or not a void growth condition is satisfied depends on the microstructural barriers to dislocations near the crack tip as well as the flaw distribution along the interface. All the interface fracture scenarios discussed in the following sections fall into one of these three categories.

5.3 Grain Distributions in the Metal Layer 5.3. I Yield Strength and Fracture Energy

The emission and subsequent mobility of dislocations at or in the vicinity of a crack tip determines the degree of plastic deformation during the crack's continued propagation. Thus, microstructural features which alter the behavior of

The Effect of Microstructure on Fracture of Metal/Ceramic Interfaces

111

dislocations and dislocation configurations near an interface have a strong effect on the fracture behavior and fracture energy. The details of physical mechanisms responsible for impeding dislocation motion and emission during the fracture of deformable solids [23, 23] or at interfaces [24] are complex and not yet developed well enough to be useful for someone attempting to tailor interfaces for packaging materials. However, some insight can be gained by looking at the effect of macroscopic mechanical properties, such as the yield strength, on the fracture energy. Consider the following analysis of the effect of plasticity on fracture of metal-ceramic interfaces. For a ductile layer bonded between two elastic layers, a nondimensional parameter, ~, governs the amount of plastic dissipation during crack propagation [7]: = Ero/o2h

(5.5)

where E is the elastic modulus, a r is the yield strength of the metal, and h is the thickness of the ductile layer. F o represents an energy which is linearly related to the work of adhesion, Wad, but also represents the chemical segregation at the interface as well as thermodynamically irreversible processes related to reconstruction of the surfaces after fracture (eg., phonon dissipation). Thus, Fo is a fundamental quantity with relatively small values compared to the fracture energy. While the relation between the plastic dissipation, r and the fracture energy, Fi, is not explicitly known, it is believed to be linear when crack growth occurs by brittle decohesion at the tip [7]. In this case, equation (5.5) tells us the plastic dissipation, hence 1-"i, is multiplicative with Fo and therefore multiplicative with Wad. As the interface Wad is increased by removal of embrittling segregants, for example, the fracture energy would be expected to increase correspondingly. On the other hand, the relation between r and Fi might be nonlinear; this is true when another mechanism dominates, such as void growth ahead of the crack tip. Then the relation between F i and Fo would not be expected to be linear. Examples of both of these cases are given in Section 5.3.3. The main point is to obtain the relation between the fracture energy, Fi, and the yield strength. With this information one can begin to develop the function between ~ and Fi. There exist a few explicit empirical relations between the fracture energy and the yield strength [8, 9, 24, 25], but there has been no precise experiment reported where the yield strength of a metal is altered systematically without changing other parameters influencing the fracture energy. Such experiments are easy enough to imagine--vary the content of O, N, or H in certain metals [26], make an alloy, or change the grain size [27]--but they are plagued with difficulties which in the end significantly affect other parameters. However, it is still useful to consider how some aspects of microstructure affect the yield strength of a metal. For example, the well-known Hall-Petch relation for metals describes the influence of grain size on the yield strength: try = ao + ky/d ~

(5.6)

where a o is the average yield strength of a single grain, ky is a parameter

1 12

MATERIALS FOR ELECTRONIC PACKAGING

relating to the effectiveness of the grain boundaries as dislocation barriers, and d is the average grain diameter. Equation (5.6) must be considered separately for thin films and for thicker films and foils. First, consider yield strength changes in thin films. 5 . 3 . 2 Yield Strength in Thin Films

In thin metal foils and films the diameter of the grains generally does not grow beyond the foil thickness [27], thus, fully annealed metal foils have a fixed grain size for a given thickness. One would therefore expect smaller metal layer thicknesses to exhibit yield strength increases according to the Hall-Petch relation (5.6). However, for metal layer thicknesses less than about 1/~m [28] the increase in yield strength with decreasing metal layer thickness has been measured to be much larger than may be explained by the Hall-Petch relation. In fact, there exists an inherent increase in o-r attributed to the constraint of dislocation motion by the substrate to which it is bonded, or in some cases by the thin native oxide layer [28]. Models of substrate constraint for given geometries have been developed [28]. Furthermore, the dislocation arrangements for very thin films may also be different from those in thicker films. For example, in certain situations in multilayer structures there is even a critical layer thickness below which misfit dislocations are no longer stable [29]. Although theoretical models that allow predictions of a r for thin films have not been fully developed, the yield strength of thin films on substrates can be measured using a nonoindenter or any other devices recently designed for this purpose. Observations of the high yield strengths in thin films indicate that thin film metal-ceramic interfaces exhibit much different fracture characteristics from thicker films and foils. In particular, a more brittle fracture behavior is expected. 5.3. 3 Yield Strength in Thick Films and Foils

Consider interfaces which fracture by brittle decohesion at the crack tip. For metal layer thicknesses > ~ 1/~m the fracture energy varies linearly with the layer thickness [20-1, assuming the grain size remains the same and is large with respect to the plastic zone size. Figure 5.5 shows data for two metal ceramic interfaces which fail by decohesion at the crack tip accompanied by plasticity. Due to the relatively high fracture energies in Figure 5.5, the calculated plastic zone size is much greater than the layer thickness. The linear relation between fracture energy and layer thickness is simply because the plastic zone size increases approximately linearly with layer thickness, as illustrated in Figure 5.6(a) and (b). This linear relation between fracture energy and layer thickness would only exist when the plastic zone size is large compared to the layer thickness, unlike the situation depicted in Figure 5.6(c). On the contrary, when the plastic zone size encompasses several grains, as shown in Figure 5.6(d), the yield strength is effectively increased according to the Hall-Petch relation (5.6) because dislocations emitted from the crack tip encounter

The Effect of Microstructure on Fracture of Metal/Ceramic Interfaces

1 13

6O ~ ~

50 40

I-i

~

3o 20

U

c~ [-~

lO

/•u/A1203 I l

20

I i

,9

60

I i

I

I

100

'

120

Metal Layer Thickness (lam) Figure 5.5(a) Fracture energy as a function of metal layer thickness for two different metals. The A u - A 1 2 0 3 w a s tested in H 2 0 . (Reprinted from A.G. Evans, A. Bartlett, J.B. Davis, B.D. Flinn, M. Turner, and I. Reimanis, Scripta Met. 25, 10003 (1991) with kind permission from Pergamon Press Ltd., Headington Hill Hall, Oxford OX3 0BW, UK.)

80 70

50

40

a0

20

60

100

120

Metal Layer Thickness qn'n) Figure 5.5(b)

Fracture energy as a function of metal layer thickness for Au-A120 3 tested in dry N 2. (Reprinted from I.E. Reimanis, B.J. Dalgleish, and A.G. Evans, Acta Metall. 39(12) 3133 (1991).) grain boundaries. Assuming the fracture mechanism does not change, and still occurs by brittle decohesion at the crack tip, the plastic zone size will decrease, thereby decreasing the fracture energy. The extreme case is when the yield strength of the metal is increased until no plasticity occurs and the fracture energy is minimized. From this type of reasoning it is clear that the fracture energy is in principle tailorable through adjusting the metal grain size as depicted in Figure 5.6.

1 14

MATERIALS FOR ELECTRONIC PACKAGING

crack tip NN~

ceramic

ceramic

!!!ii!i Iiii I metal layer

ceramic

!i!iii!ii!il iiiii!i!!iii!! ceramic

(a) ceramic

ceramic

ceramic . . . . . . . . . . . . . . . . . . . . . . .

............................................................................

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iiiiiiiiiiiiiiiiiiiiiii!!iii!iiiiiiii, li iii!!~ill ,~i ~i~ ~i~i ~iil~ii!i !iii!i~i!~,i

iiiiiii!iiiii!i!ii!ii! ii!ii!i!li!i!i!iii!ii i!iiiliii!!!ii!i!ii!iiii!i!i ceramic

(c)

(d)

Figure 5.6 Schematic of plastic zone size at a crack tip for (a-c) different metal layer thicknesses and (d) different metal grain size.

Another situation may arise when fracture occurs by void growth ahead of the crack tip. Consider the same Au-AI203 interfaces now tested in a dry N2 atmosphere in which crack growth is not susceptible to stress corrosion [9]. Because the interface is stronger (Fo is higher) in the absence of water, more blunting of the crack tip occurs and an entirely different fracture mechanism involving a great deal more plasticity is observed; the interface fractures by void nucleation ahead of the crack tip. In this case the relation between the fracture energy and metal layer thickness is not linear (Fig. 5.5(b)). Also, it appears that for different metal layer thicknesses, the mechanism of void growth changes [9]. And some degree of brittle decohesion accompanies void growth so the situation is quite different from ductile void growth in metals. The work of adhesion and yield strength must be coupled together as in equation (5.5). 5 . 3 . 4 Residual Stress

Variations in grain size and film thickness will also produce variations in the elastic modulus, E, and the thermal residual stresses, ar [28]. For example, thin films formed by nonequilibrium growth processes such as deposition may result

The Effect of Microstructure on Fracture of Metal/Ceramic Interfaces

115

.....

:.'"

. , :~" ~ 9

.....

,...}= .. . . . . . i '~;~ "~'~'~:":*~"~"

TalTi)

Branch

cracks

~, :~. .i . .",~~ :~ :

1 pm

Figure 5.7 Cross-sectional optical micrograph showing crack branching due to residual stress. (Courtesy A. Bartlett.)

in residually stressed microstructures [28]. E and ar in turn affect the mode mixity [16, 17], which has a very strong influence on the fracture behavior. The effect of ~rr on influencing ~ at bimaterial interface cracks has only been recently considered [16, 17] and has not been considered for metal-ceramic interfaces where plasticity plays a dominant role in determining fracture behavior. Metalceramic systems where thermal stress has been dominant include the (Ti, Ta) alloy-Al203 system. Because the thermal expansion coefficient of Ti (or Ta) is higher (or lower) than that of A1203, alloys of these metals may be created which have tailorable thermal expansion coefficients. Thus, one may study the influence of residual stress on fracture behavior while maintaining similar chemistry at the interface. Because the phases formed at the alloy-Al203 interface are brittle, any changes in the yield strength with chemical composition may be neglected. Results of this study showed that the crack trajectory could be controlled by varying the alloy composition (i.e., the residual stress at the interface). In particular, when the expansion coefficient mismatch was positive (0~alloy < ~ceramic) the crack branched periodically into the brittle metal layer, as shown in Figure 5.7. 5 . 4 The I n t e r f a c e Pore Distribution

Interface flaws produced during processing, such as residual pores (Fig. 5.8) or local areas of high impurity concentration, may be sources for crack initiation. The influence of these flaws on fracture energy is largely dependent on the type of fracture. For example, it has been observed that a distribution of residual pores

1 16

MATERIALS FOR ELECTRONIC PACKAGING

............................................................9...... i;i~iii:ii~i~!i ............. i.~

: . ==================== ....============

w m ~ ~

:'~:":i;i!:..... :i: i

~ii::; ii'~il::: :/:~ :,:~::~:-

Figure 5.8 Scanning electron micrograph of Au side of fracture surface showing residual pores in Au. The white bands are slip lines resulting from fracture.

(3-10 pm in diameter) along an interface has no effect on the fracture behavior when fracture occurs in a brittle manner [9]. However, when fracture occurs by the growth of voids or microcracks ahead of the crack tip, then the distribution of pores plays an important role [-9, 24]. Specifically, the spacing of the flaws is an important parameter for predicting the fracture energy [24]. It has even been observed that the fracture behavior may be controlled and increased significantly by the introduction of specific types of flaws [25]. Oh et al. have characterized the fracture behavior of Cu-glass interfaces in the geometry shown in Figure 5.9(a). By photolithographically placing flaws along desired locations at the top and bottom interfaces, the propagating crack alternates from one interface to another, resulting in the situation shown in Figure 5.9(b), where metal ligaments remain behind the crack tip, increasing the fracture resistance of the interface by a factor of up to 80 over "flawless" interfaces. 5.4. 1 The Au-AI20a Model Interface System Another example of this type of alternating crack behavior has been seen in the Au-AI20 3 interface with the testing geometry shown in Figure 5.10. Residual pores at the interface exist as a result of processing (Fig. 5.8). In a dry N 2 atmosphere fracture along the Au-AI20 3 interface occurs by void growth ahead of the crack tip, as may be seen from in situ crack growth experiments where the crack front is shown for three levels of applied load (Fig. 5.11). The residual pores act as nucleation sites for the voids. In the Au-AI20 3 system there may be two mechanisms for crack propagation by void growth depending on the pore spacing [9]. To

The Effect of/Hicrostructure on Fracture of Metal/Ceramic Interfaces

•::!:i:i.i•i:i;ii•i)i!ii•ii;i•i•:•}::i:.:!:i••ii.i•i!;:.iili:i:ii:i:i:iiiii~:;:i~i::i:..:i:i;:;:i~~:i:i:i:::. i:;:.;i:.•:. :::::::::::::::::::::::::::::' :.:. i:.i:;:.!:.;.!.i:;~::~:::.~~~~: :::~~:~:~i.::.:: :~::~:~~:~:~;i:.i:::::i ............................................................................................................. i : i :i:!!:i!ii!iiii!i!iiiiiii!.i!!iiiii!i!iiii!:iii!!: 'metal

1 17

i

Figure 5~ Flaw distribution at a metal-ceramic interface introduced through photolithography.

"////d ,ramie r/~

Figure 5.9(b) The fracture behavior of an interface with this microstructure.

Delamination specimen ~c = 6M 2/EH 3

metal layer

Figure 5.10 Testing geometry for mixed mode fracture of metal-ceramic interfaces. (Reprinted from T.S. Oh, J. R6del, R.M. Cannon, and R.O. Ritchie, dcta Metall. 36, 2083 (1988) with kind permission from Pergamon Press Ltd., Headington Hill Hall, Oxford, OX3 0BW, UK.)

1 18

MATERIALS FOR ELECTRONIC PACKAGING

Figure 5.1 1 Optical micrographs of crack fronts at the Au-AI203 interface for three applied loads. The micrographs were taken by viewing through the top layer of transparent sapphire shown in Figure 5.8. The crack was initially grown in H20 by stress corrosion then loaded in a dry N 2 atmosphere.

understand why the pore spacing is important, one must first consider the constraint of the metal layer imposed by the surrounding ceramic. In the presence of a crack tip the effect of this constraint is to induce a high level of hydrostatic stress far ahead (several metal layer thicknesses) of the crack tip, as shown in Figure 5.12. Thinner layers generally result in a higher degree of constraint [24]. If the maximum hydrostatic stress achieves a critical level, a void will spontaneously cavitate provided there exists a flaw. The void may grow, and if the void is far enough from the crack tip, it may remain isolated from the crack tip (Fig. 5.11) [9]. A second mechanism may occur when the flaws are spaced much more closely. Voids which nucleate at flaws nearer to the crack tip coalesce into the tip before the critical hydrostatic stress far ahead of the tip is achieved. This second mechanism is similar to crack propagation in ductile metals; voids which nucleate at flaws directly ahead of the crack tip coalesce back into the crack tip. These two mechanisms~void growth far ahead and void growth near the crack tip---result in two very different fracture behaviors and fracture energies. Specifically, void growth far ahead of the crack tip occurs at a much higher energy. Furthermore, when crack growth occurs by void growth far ahead of the crack tip, intact regions which are still bonded are left behind the crack tip. These intact regions shield the crack tip from the applied load, toughening the interface [9] in a manner similar to Figure 5.9(b). The criteria determining which of these two

The Effect of Microstructure on Fracture of Metal/Ceramic Interfaces

1 19

KI

7.0 I

KI/0'o~

5.0

-

L

" "---....Iz7"'-. . "........

40 f

00.0

----.

1.'0

210

310

'4.0

x/h Figure 5.12 Mean stress normalized with the uniaxial yield strength as a function of distance ahead of the crack tip normalized with the metal layer thickness.

mechanisms occurs depend on two main parameters: the thickness of the metal layer, h, which dictates the level of constraint, and the spacing of the flaws, Xo. It has been found that for relatively large flaws spacings (Xo/h > 0.1), void growth far ahead of the crack tip occurs, and vice versa [9, 24].

5.5 Interface Roughness The size of topographic features at an interface may vary between 1 nm and 10000 nm, depending on the materials and the processing conditions. Generally, very rough interfaces on the order of several 1 000 nm are not desired in electronic packaging because (1) the roughness tends to degrade properties such as electrical conductivity [3]; and (2) limited space dictates that many features in electronic packaging must have a size of less than 1 000 nm. At the other end of the spectrum, crystallographic facets and steps on the order of 0.1 nm frequently are present in metal-ceramic interfaces [5]. However, in metal-ceramic interface fracture where plasticity dominates the fracture energy, these microsteps probably do not influence the fracture energy [7]. This section focuses on interface roughness features smaller than 1 000 nm but larger than crystallographic facets and steps. The main effect of interface roughness may be best understood by considering Figure 5.13. The contact of asperities behind the crack tip shields the crack tip from

120

MATERIALS FOR ELECTRONIC PACKAGING

A opening O stress

I

T~shearstressI:

surface )

lastc~ p~

crack

KL

interface

f Figure 5.13(a)

Asperity contact model.

•G'•1"~ r

~

x = EH2/LG~

/" /

Nb/A1203

10 1

H = 0.2 - 0.4 j.tm L = 5 - 50 ~m E = 100 GPa ~o = 70 J/m2

Mode Mixity, 14/(= tan ~ KII/K i)

Figure 5.13(b) Increase in fracture energy as a function of mode mixity plotted for various values of Z. Also shown are measured values of interface roughness for the Nb-AI20 3 system. (Reprinted from A.G. Evans and J.W. Hutchinson, Acta Metall. 37(3), 909 (1989) with kind permission from Pergamon Press Ltd., Headington Hill Hall, Oxford, OX3 0BW, UK.)

applied stresses so that a higher applied load is necessary to propagate the crack [5]. As can be seen in Figure 5.13(a), the contact of asperities behind the crack tip will only occur when there is a shear displacement of the upper surface relative to the lower surface (ie., a nonzero phase angle, ~). Because in most engineering situations bimaterial interface cracks experience mixed mode loading [11], it is of extreme importance to account for the interface roughness. The effect of interface

The Effect of/Hicrostrucfure on Fracture of Metal/Ceramic Interfaces

121

roughness on the fracture energy during mixed mode loading of bimaterial interfaces cracks has been modeled by Evans and Hutchinson [5] using several geometries of interface roughness, and has been experimentally observed for elastic bimaterial interfaces by several researchers [13, 14, 30]. The governing parameter which quantifies the roughness is [5] Z = EH2/LFo

(5.7)

where E is the elastic modulus of the substrate, H is the asperity amplitude, L is the wavelength of asperities, and Fo is the nominal mode I (q~ = 0 ~ fracture toughness. The value of 7~ gives an indication of when the crack tip shielding is significant. Figure 5.13(b) shows the fracture energy as a function of the mode mixity ~ for different values of ~ (from [5]). Rough interfaces (~ > ~ 1) exhibit a large increase of Gc with ~, whereas smooth interfaces are relatively insensitive to changes in ~. The situation is somewhat different for cracks at metal-ceramic interfaces. For very large crack-opening displacements, for example when much plasticity is present during fracture, the two surfaces (Fig. 5.13) may be too far apart for significant asperity contact. The value of the nominal mode I fracture energy Fo in equation (5.7) reflects this crack-opening displacement [31]; one must be careful in applying the model to metal-ceramic interfaces with high values of F o. Whether or not F o is considered high depends on the relative values of H, L and F o. During fracture at a metal-ceramic interface the asperities may plastically yield upon contact, thereby lowering the amount of shielding predicted by the theory when the asperities are perfectly elastic. Even then, some shielding would be predicted, the exact amount most likely dictated by the yield strength of the metal. 5.5. I The Nb-AI~ Oa Model Interface System

As an example, consider the relatively rough interface between polycrystalline Nb and single crystal A1203, made by diffusion bonding. The interface roughness of Nb-AI20 3 varies considerably with the processing conditions [32, 33]. During diffusion bonding of the interface the initially smooth single crystal A120 3 replicates the rough Nb surface (Fig. 5.14). Even grain boundary grooves in the Nb are replicated in the A120 3 surface, resulting in an interface roughness where asperities may be as high as 200 nm [32, 33]. These interfaces were tested by using fracture geometries with two different mode mixities. The details are discussed elsewhere [34]. The first specimen was machined in a standard chevron notched beam geometry [35] where the crack experienced a nominally mode I state of stress. An elastic mismatch between Nb and A120 3 has the effect of increasing ~ to a value of about 5 ~ [32]. The second specimen geometry is shown in Figure 5.8 in which the crack is in a mixed mode state of stress where ~ is 45 ~ (approximately equal amounts of mode I and mode II) [11]. The specimens tested in mixed mode (~ = 45 ~ showed higher fracture energies (Gc > 100 J/m 2) than the mode I specimens (Gc ~ 70 j/m2). An estimate of the

122

MATERIALS FOR ELECTRONIC PACKAGING

Figure 5.14 Optical micrograph of an A1203 fracture surface from fracture of the single crystal A12Oa-Nb. Compare the smooth area, which was not bonded to Nb, with the rough area, which is a replica of Nb features such as grain boundaries.

parameter Z in equation (5.7) for these interfaces was made by measuring heights and distributions of asperities on the fracture surfaces using an optical interference technique. H and L were measured to be 0.2-0.4/~m and 5-50 ~m respectively. Also, a value of F o = 70 J/m 2 was used for the nominal mode I fracture energy. Values of g = 1-45 were obtained, predicting strong shielding of the crack tip for mixed mode cracks according to Figure 5.13. The measured difference in Gc between the two specimen geometries (AGc > 30 J/rn 2) is consistent with the AGc predicted by the shielding model (Fig. 5.13). Unfortunately, it is difficult to control the interface roughness during processing. For this reason it was not possible to obtain a smooth interface with which the rough interface could be compared. The critical experiment is to vary H and L and to observe how AGc changes. One of the questions still unresolved in the above experimental results concerns the magnitude of plastic deformation experienced by the asperities and its effect on reducing the crack tip shielding. Measurements on the fracture surface did not indicate that asperity deformation had occurred, but it may not be detectable using conventional fracture surface characterization techniques such as the scanning electron microscope. An important consideration is that asperities in the Nb-AI203 system are expected to contain high amounts of oxygen [36], thereby increasing the yield strength to a value above the bulk foil [27]. It is possible they behave elastically, though it remains to be shown.

The Effect of Microstructure on Fracture of Metal/Ceramic Interfaces

i

123

,

5.6 Summary Specific microstructural effects on the fracture energy of metal-ceramic interfaces have been discussed. When plasticity dominates the fracture energy, microstructural features may govern the degree of plastic dissipation or may alter the mechanism of fracture. Thus, a characterization of which microstructural features exist in a specific metal-ceramic interface is essential for predicting the fracture behavior. There still remain many fundamental problems in understanding the mechanism of fracture at interfaces and the parameters which govern them.

Acknowledgments The author acknowledges the insight ofDrs. R. M. Cannon and S. Schmauder. This chapter was written in Stuttgart, Germany, and funded by the Max Planck Society through a fellowship.

References 1. Electronic Materials Handbook, Vol. 1, Packaging, senior editor C.D. Dostal, ASM

2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22.

International, Materials Park, Ohio, 1989. A.G. Evans, A S T M STP 1020, 1989, p. 267. G.W. Prohaska and G.R. Miller, Mater. Res. Soc. Symp. Proc. 167, 215 (1990). Y Kurokawa, C. Toy, and W.D. Scott, J. Am. Ceram. Soc. 72(4), 612 (1989). A.G. Evans and J.W. Hutchinson, Acta Metall. 37(3), 909 (1989). R.R. Tummalla and E.J. Rymaszewski, Microelectronic Packagin9 Handbook, Van Nostrand Reinhold, New York, 1989. A.G. Evans, M. Riihle, B.J. Dalgleish, and P.G. Charalambides, Metall. Trans. A 21, 2419 (1990). M. Cannon, V. Jayaram, B.J. Dalgleish, and R.M. Fisher, in Materials Science Research, Vol. 21, Ceramic Microstructures 86, Edited by J.A. Pask and A.G. Evans, 1987, p. 959. I.E. Reimanis, B.J. Dalgleish, and A.G. Evans, Acta Metall. 39(12), 3133 (1991). A. Bartlett, A.G. Evans, and M. Riihle, Acta Metall. 39(7), 1579 (1991). P.G. Charalambides, J. Lund, A.G. Evans, and R.M. McMeeking, J. Appl. Mech. 56, 77 (1989). D.Broek, Elementary Engineerin9 Fracture Mechanics, 4th ed., Martinus Nijhoff, 1986. M.D. Thouless, Thin Solid Films 181, 397 (1989). H.C. Cao and A.G. Evans, Mech. of Mater. 7, 295 (1989). K.M. Liechti and Y.S. Choi, J. Appl. Mech., 58(3), 680-687 (1991). J.W. Hutchinson and Z. Suo, Advances in Applied Mechanics 29, 63-191 (1991). G. Dreier, M. Meyer, S. Schmauder, and G. Elssner, Acta Metall. 40, suppl., $345-$353 (1992). M.S. Hu, M.D. Thouless, and A.G. Evans, Acta Metall. 35, 1302 (1988). M. He and J.W. Hutchinson, J. Appl. Mech. 56, 279 (1989). A.G. Evans, A. Bartlett, J.B. Davis, B.D. Flinn, M. Turner, and I.E. Reimanis, Scripta Metall. 25, 1003 (1991). J. Davis, H.C. Cao, G. Bao, and A.G. Evans, A cta Metall. 39(5), 1019-1024 ( 1991). I.H. Lin and R.Thomson, Acta Metall. 34(2), 187 (1986).

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MATERIALS FOR ELECTRONIC PACKAGING

23. P.M. Anderson, J.S. Wang, and J.R. Rice, "Thermodynamic and Mechanical Models of Interfacial Embrittlement," paper presented at the 34th Sagamore Army Materials Research Conference, Lake George NY, 1987. 24. A.G. Varias, Z. Suo and C.F. Shih, J. Mech. Phys. Solids, 41(5), 835-861 (1993). 25. T.S. Oh, J. R6del, R.M. Cannon, and R.O. Ritchie, Acta Metall. 36, 2083 (1988) 26. E. Fromm and G. H6rz, International Metals Reviews 5/6, 269 (1980). 27. G.E. Dieter, in Mechanical Metallurgy, McGraw-Hill, New York, 1976. 28. R.E. Nix, Metall. Trans. A 20, 2217 (1989). 29. J.P. Hirth and X. Feng, J. Appl. Phys. 67(7), 3343 (1990). 30. J.S. Wang and Z. Suo, Acta Metall. 38(7), 1279 (1990). 31. J.R. Rice, J. Appl. Mech. 55, 98 (1988). 32. B. Gibbesch, Ph.D. thesis, University of Stuttgart, Dusseldorf, Germany, 1991. 33. I.E. Reimanis, Acta Metall. 40 suppl., $67-$74 (1992). 34. I.E. Reimanis, Scripta Metall. 27(12), 1729-1734 (1992). 35. A S T M Special Publication E399-83, 1989, p. 487. 36. M. Rfihle and A.G. Evans, Mater. Sci. Eng. A 107, 187 (1989). 37. M. Nicholas, J. Mater. Sci. 3, 571 (1968). 38. J.S. Wang and Z. Suo, Acta Metall. 38(7), 1279 (1990).

,~,, III Composites

This Page Intentionally Left Blank

CHAPTER6

The Future of Advanced Composite Electronic Packaging Carl Zweben

6.1 Introduction Key trends in the electronics industry are driving major changes in packaging technology: 9 increasing packaging density 9 increasing reliability requirements 9 increasing use of large, solid-state phased array antennas 9 more severe environments 9 stringent weight restrictions for airborne and other systems ~ cost constraints To meet the needs arising from these issues, packaging materials must have several attributes: 9 low, tailorable coefficient of thermal expansion 9 high thermal conductivity 9 low cost 9 low density for weight-critical systems Conventional materials do not satisfy all these requirements [1,2]. One approach to meet these needs is to create new composite materials with properties tailored specifically for electronic packaging. We are in the early stages of a packaging materials revolution, in which composite materials will play a key role. A composite is a material consisting of two or more constituents, each of which maintains distinct properties and regions. According to this definition, alloys are not composites. The most common composites consist of a matrix material reinforced with continuous or discontinuous fibers, whiskers, or particles. The four key classes of composites are polymer-matrix composites (PMCs), metal-matrix composites (MMCs), ceramic-matrix composites (CMCs) and carbon/carbon (C/C) composites. In addition, there are composites in which the phases have amorphous geometries. For example, some circuit breaker contacts are made by infiltrating silver into a

127

128

MATERIALS FOR ELECTRONIC PACKAGING

porous preform made by sintering tungsten particles, in essence a metal/metal composite. This chapter reviews the status of composite electronic packaging materials and examines future trends.

6.2 Status of Composite Packaging Materials Polymer-matrix composites, in the form of glass fiber reinforced polymer (GFRP) printed circuit boards (PCBs), are well-established packaging materials. New composites, commonly called advanced composites to distinguish them from GFRP, have been developed in recent years. They provide unique combinations of properties which make them outstanding candidates for packaging applications: tailorable coefficient of thermal expansion, extremely high thermal conductivity (sometimes higher than copper), high stiffness, high strength, and low density. These materials are being applied to a variety of components, including electronic and microwave packages, PCB heat sinks, and electronic enclosures or chassis. Order of magnitude thermal conductivity increases and weight reductions as high as 80% have been demonstrated. Composites also offer significant potential cost reductions in some cases. Materials used to package electronic devices must satisfy a number of requirements, many of which are specific to the application. However, in almost all cases it is desirable, if not essential, that their thermal conductivities are high and their coefficients of thermal expansion (CTEs) are similar to those of the ceramic substrates or electronic devices attached to them [1]. An additional consideration for weight-sensitive applications, such as aircraft, spacecraft, and mobile electronic systems, is low density. In many components, mechanical properties, such as strength and stiffness, are also important. Electronic packaging can be divided into four levels (Fig. 6.1). First comes the package level. Second comes the PCB assembly or package mounting plate. Third comes the entire electronic subsystem, which typically includes a chassis or enclosure, often referred to as a black box. And fourth comes the support structure. Issues of thermal control, thermal expansivity, and weight cut across all levels. Strength and stiffness are important at all levels but the first. A large and increasing number of fiber, whisker, and particle reinforcements is available. When combined with the wide variety of existing metal, polymer, and ceramic matrices, they provide a virtually limitless array of potential new materials. From this broad spectrum, a number of materials have emerged as the early leaders for packaging applications. The key reinforcements at this time are ultrahigh modulus carbon (graphite) fibers and silicon carbide particles. Leading matrix materials are aluminum, copper, and epoxy. Two other commercial composites are beryllia particle reinforced beryllium, (BeO)p/Be, and aluminum infiltrated graphite foam, Gr/A1. Experimental carbon fibers made by chemical vapor deposition (CVD) have been produced which have reported thermal conductivities of 2 000 W m-1 K-1, five times that of copper [3]. Commercial pitch-based carbon fibers are available

The Future of Advanced Composite Electronic Packaging 1 2 9

Level I 9

Level II 9Printed Circuit Board 9P a c k a g e S u p p o r t Plate

Heat Sink (Cold Plate)

Level III 9S u b s y s t e m (Box)

Level IV 9S u p p o r t S t r u c t u r e

Figure 6.1

Electronicpackaging levels.

with a reported thermal conductivity of 640 W m-1 K-1 over 50% greater than copper, and a modulus of 830 GPa, 12 times that of aluminum [4,5]. Another key characteristic of these unique materials is that they have negative CTEs. By combining these low density reinforcements with polymer and metal matrices in an appropriate way, it is possible to construct lightweight composites with tailorable expansion characteristics combined with high thermal conductivity, stiffness and strength. Materials with isotropic inplane (x-y) CTEs as low as 1.7 x 10 -6 K-1 have been obtained. Figure 6.2 shows how thermal conductivity varies with electrical resistivity for metals and for carbon fibers derived from petroleum pitch, carbon fibers derived from polyacrilonitrile (PAN), and carbon fibers made by CVD. Silicon carbide particles are relatively low cost reinforcements which combine high stiffness, low coefficient of thermal expansion, good thermal conductivity, and low density [6]. When used with aluminum matrices, SiC particles produce a unique family of isotropic, low density composites with CTEs tailorable from about 6 x 10 - 6 K-1 t o about 24 x 10 - 6 K - 1 high thermal conductivities, excellent stiffness, and excellent strength. In pure form, SiC crystals have a thermal conductivity of 490 W m-1 K-1 compared to about 400 W m-1 K-1 for copper [7]. Consequently, aluminum reinforced with silicon carbide particles, (SiC)p/AI, potentially could have a much higher thermal conductivity than monolithic aluminum (about 200 W m- 1 K- 1). The primary advantage of the composites discussed in this chapter is that they combine relatively high thermal conductivities with tailorable CTEs and densities which are significantly lower than those of low CTE, monolithic packaging metals like Kovar, Invar, molybdenum, and tungsten. And carbon fiber reinforced

130

MATERIALS

FOR

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10 4

PACKAGING

K (CF) K (Cu) sc.

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,

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~

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10 o

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~

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I 10 0

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, 10 2

Electrical Resistivity (microhm-m)

Figure 6.2

Thermal conductivity and electrical resistivity of carbon fibers and metals.

copper offers significantly higher thermal conductivities than any of the conventional metallic packaging materials cited above. At present, the leading composites of interest for applications such as heat sinks and packages are carbon fiber reinforced epoxy (C/Ep), carbon fiber reinforced aluminum (C/A1), carbon fiber reinforced copper (C/Cu), boron fiber reinforced aluminum (B/A1) and silicon carbide particle reinforced aluminum ((SiC)p/A1) [ 1,15]. Other commercial materials cited earlier are (BeO)p/Be and Gr/A1 [8,9,16]. Fiber reinforced composites are strongly anisotropic; their properties depend strongly on fiber direction. In contrast, monolithic and particle reinforced metals tend to be isotropic; their properties are the same in every direction. Mechanical and physical properties of fiber reinforced materials can be tailored over wide ranges by selection of fiber, matrix, fiber volume fraction, and fiber orientations. At this stage of development of composite packaging materials, we lack an extensive data base of measured properties. This situation is common to most materials in the early stages of development. To overcome this problem, analytical property predictions based on what are commonly called micromechanical models are used. Experience has shown that, given reliable constituent property data, the better analytical models provide reasonably good property estimates. The properties presented in this article are based on analytical predictions supplemented by experimental data where available [1,14]. Figure 6.3 shows how the isotropic inplane CTE of copper reinforced with a variety of pitch-based carbon fibers varies with fiber volume fraction. Note that by varying fiber volume fraction, Vf, it is possible to match the CTE of virtually all materials of interest, including silicon, gallium arsenide, alumina, beryllia and aluminum nitride. Figure 6.4 shows how the inplane thermal conductivities of C/Cu composites

The Future of Advanced Composite Electronic Packaging

1 31

20

15

Inplane Coefficient of Thermal Expansion (IO-e/K)

Fiber

Experiment

PlO0 P120 P130

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40

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Carbon Volume Fraction (~)

Figure 6.3

Variation of inplane (isotropic) coefficient of thermal expansion with fiber volume fraction for carbon fiber reinforced copper (0/90) laminates. 600

500

Fiber

Experiment

PIO0 P120 P130

§

~P130 9 9

400

Inplane Thermal Conductivity (W/mK)

P120

300

4"

"4"

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200

100

o

I

I

0

20

I

I

40 60 Carbon Volume Fraction (%)

I

1

80

100

Figure 6.4 Variation of inplane (isotropic) thermal conductivity with fiber volume fraction for carbon fiber reinforced copper (0/90) laminates.

vary with Vf. Note they are much higher than those of conventional packaging materials with low CTEs. Through-thickness conductivities are also high. Figures 6.5 and 6.6 show how the CTE and thermal conductivity of carbon fiber reinforced aluminum vary with fiber volume fraction. Composites made by reinforcing aluminum alloys with silicon carbide particles are another important class of packaging materials [10-13-1. Most of the

132

MATERIALS FOR ELECTRONIC P A C K A G I N G

24

....

20

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Fiber

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12

--

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--

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__

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P100 P120 P130

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I

0

10

I

20

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P120/6063

30

I

40

I

,,

I,

50

60

70

80

C a r b o n V o l u m e F r a c t i o n (~)

Figure

6.5 Variation of inplane (isotropic) coefficient of thermal expansion with fiber volume fraction for carbon fiber reinforced aluminum (0/90) laminates.

400 Fiber

350 300 Inplane Thermal Conductivity

(W/mK)

--

Experiment

Pl00 P120

-!9

~

P140/AI P120/AI

250 200 150

PIOO/AI " ~ ~~

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.

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10

20

30

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60 C a r b o n V o l u m e F r a c t i o n (%)

I

I

70

80

......

Figure 6 . 6 Variation of inplane (isotropic) thermal conductivity with fiber volume fraction for carbon fiber reinforced aluminum (0/90) laminates.

composites to date have used low purity SiC particles made for commercial abrasive applications. These reinforcements have the important advantages of high production volume and low cost. However, high purity particles have much higher thermal conductivities. Figure 6.7 presents predicted and experimental values of CTE for (SiC)p/A1 composites; these materials are isotropic. Observe how the analytical and measured values are in reasonably good agreement. For particle volume fractions, Vp, in the

The Future of Advanced Composite E/ectronic Packaging

25.0

Aluminum

Experiment

9 6061 9 6063 9 LMI

Prediction

20.0

Cop.p_er Coefficient of Thermal Expansion (IO-S/K)

15.0

10.0

5.0

1 33

- - Berylium - - Titanium, Stainless Steel Alumina

--

Silicon

0.0

I

I

I

I

I

0

20

40

60

80

~

I 100

Particle Volume Fraction (%)

Figure 6.7 Variation of coefficient of thermal expansion with particle volume fraction for silicon carbide particle reinforced aluminum. 260 Prediction

220

"*",,,,q,,, Thermal Conductivity (W/mK)

180

Experiment

I 6061 ......... 6 0 6 3 _v~ 2 1 2 4

9 6061 9 6063 9 LMI

m

~

~

% .............'*,,,,

9--- High Purity Particles

140

,,

-

100

60

I

0

I

20

I

40

I

60

I

80

I

100

Particle Volume Fraction (%)

Figure 6.8 Variation of thermal conductivity with particle volume fraction for silicon carbide particle reinforced aluminum.

range 65-70% it is possible to obtain CTEs similar to those of alumina and other ceramic substrates. Figure 6.8 presents predicted and measured thermal conductivities of (SiC)p/A1 composites. For composites made from commercial abrasive particles, conductivity decreases with Vp. However, there is one experimental value for high purity silicon carbide particles that is in the range of high conductivity, monolithic

134

MATERIALS FOR ELECTRONIC PACKAGING

25

,,,

,,

,

,

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20

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,,

,,

,,

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,

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,

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o

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,,.

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200 400 600 Thermal Conductivity (W/rnK)

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Figure 6.9 Thermal conductivity and coefficient of thermal expansion of electronic packaging materials. 25 20

SiCp/A -

15

A~

~

:'i,~':'i!i~'!~'i

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-

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80 120 160 200 Conductivity Sp'ec'ific G'rav'ity (W/mK)

240

280

Figure 6.10 Specific thermal conductivity (conductivity divided by specific gravity) and coefficient of thermal expansion of packaging materials.

135

The Future o f A d v a n c e d Composite Electronic Packaging

aluminum alloys. Although the conductivity of these particles is unknown, it is probably far lower than 490 W m-~ K-~ measured for high purity single crystals [7].

A convenient way to compare packaging materials is to plot CTE as a function of thermal conductivity, as in Figure 6.9. The figure demonstrates that for packaging materials which have CTEs in the range required to match devices and ceramic substrates, between 4 x 10 -6 and 8 x 10 -6 K -1, composites have thermal conductivities equal to or significantly better than those of conventional low CTE metals. Weight is increasingly important in many applications. One way to make weight comparisons is to use specific properties, obtained from dividing the absolute values by density or specific gravity. Specific gravity is dimensionless and that is what we shall use. Figure 6.10 presents specific thermal conductivity as a function of CTE for composites and conventional packaging materials. The high values of the composites clearly illustrate the advantages of these materials for weightsensitive applications.

6.3 Applications Figure 6.11 shows typical gold-plated microwave carriers. The carrier machined from (SiC)p/A1 [10] is one of the first composite packaging components ever made. It is about 65% lighter than its Kovar counterpart and has over seven times the thermal conductivity. Newer materials have even higher thermal conductivities. Figure 6.12 shows microwave module housings or packages machined from the same materials [10] and having similar advantages. A number of processes are available that allow fabrication of components requiring no machining (net shape) or a small amount of machining (near-net shape). Figure 6.13 shows a complex multichip package incorporating pedestals

I

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Figure 6.1 1 Kovar and silicon carbide particle reinforced aluminum microwave carriers. (Courtesy Martin Marietta Astro Space.)

136 MATERIALSFOR ELECTRONICPACKAGING

NICROHAVEC I R C U I T .

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.

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.

.

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BTU HR~- ~

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Figure 6.12 Kovar and silicon carbide particle reinforced aluminum microwave packages. (Courtesy Martin Marietta Astro Space.)

Figure 6.13 Silicon carbide particle reinforced aluminum multichip electronics module made by infiltration pressure casting. (Reprinted by permission of Aluminum Company of America.)

and cooling fins made by a net shape process in which aluminum is infiltrated under pressure into a particulate preform. This type of process has the potential to make low cost packages in high production volumes. The greatest range of CTEs and thermal conductivities is achieved with ultrahigh modulus, pitch-based carbon fiber reinforced composites. To obtain

The Future of Advanced Composite Electronic Packaging

137

isotropic inplane CTEs, typically required for PCB heat sinks, package bases, and lids, crossplied laminates are used having an equal number of layers oriented at 0 ~ and 90 ~ Carbon fiber reinforced copper is particularly attractive for applications with high heat loads, as it offers higher thermal conductivities than molybdenum or tungsten, combined with a CTE that can be tailored to match virtually any device or ceramic substrate. And although it is more dense than aluminum, it is less dense than monolithic copper, molybdenum, and tungsten. Carbon fiber reinforced copper is a truly unique material. Figure 6.14 shows an experimental package for applications having high heat dissipation [1]. It consists of a P-100 carbon fiber reinforced copper base attached to a Kovar lead frame. The lid is made of(SiC)p/A1. All components are gold plated. One of the critical aspects of packaging design is thermal management. To assure reliable operation of electronic and microwave components, junction temperatures must be kept within specified limits. As a rule, the problem is one of cooling, as failure rates increase dramatically with increasing temperature. Heat sinks, also called cold plates, are commonly used to transport heat dissipated by devices to a heat exchanger, or to spread it over a larger surface area to facilitate cooling by radiation or convection. To minimize thermal impedance, the heat sink

a

e e

D

Figure 6.14 Experimental multichip package with a P-IO0 carbon fiber reinforced copper base, silicon carbide particle reinforced aluminum lid, and Kovar lead frame. (Courtesy Martin Marietta Astro Space.)

138

MATERIALS FOR ELECTRONIC PACKAGING

typically is adhesively bonded or soldered to the component it supports, this may be one or more devices, a ceramic substrate supporting the devices, or a multilayer circuit board I-1]. Failures resulting from differential thermal expansion between surface mounted ceramic components and PCB assemblies is leading to increasing use of expansivity control. Typically, this requires use of low CTE heat sinks. At present the most widely used are laminated metal sandwiches consisting of two layers of copper bonded to a central constraining layer of Invar or molybdenum. For simplicity we refer to these heat sinks as copper/Invar/copper and copper/moly/ copper. The CTEs of these laminates can be controlled by adjusting the relative thicknesses of the copper and constraining layers. Both copper/Invar/copper and copper/moly/copper have two major limitations; they have high effective densities and their thermal conductivities are in the range of aluminum alloys, relatively good but not high enough for some applications [ 13. To overcome these deficiencies, a number of composite materials are being used in production or are being evaluated, including boron fiber reinforced aluminum, carbon fiber reinforced aluminum, carbon fiber reinforced copper, silicon carbide particle reinforced aluminum, beryllia particle reinforced beryllium,

Figure 6.15 Printed circuit board assembly with a boron fiber reinforced aluminum heat sink. (Courtesy Martin Marietta Astro Space.)

The Fufure of Advanced Composife Elecfronic Packaging

139

Figure 6.16 Silicon carbide particle reinforced aluminum subscale electronics enclosure segment made by pressureless infiltration. (Courtesy Lanxide Electronic Components.)

and aluminum infiltrated graphite foam [1,2,9,15]. Another approach combines layers of aluminum or copper and carbon fiber reinforced epoxy [17]. Figure 6.15 shows a PCB assembly which has a B/A1 heat sink. Composites also offer considerable weight savings in enclosures. Figure 6.16 shows a subscale prototype (SiC)p/A1 enclosure made by pressureless infiltration. And Figure 6.17 shows a carbon fiber reinforced epoxy enclosure which has a powder metallurgy (SiC)p/A1 card guide. EMI shielding is provided by nickel-coated carbon fiber embedded in the C/Ep. The card guide requires a material with high stiffness and good inplane and through-thickness thermal conductivity. The through-thickness conductivity requirement probably rules out polymer-matrix composites for these components. Figure 6.18 shows an avionics rack structure made of extruded (SiC)p/AI extrusions. The few examples presented in this section are intended to illustrate the great potential for composites at all levels of packaging.

6 . 4 Future Directions We are still in the early stages of a packaging materials revolution in which composites undoubtedly will play a key role. The greatest benefits will come from composites developed specifically to meet the unique requirements of electronic

140 MATERIALSFOR ELECTRONICPACKAGING

9

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.

Carbon fiber reinforced epoxy electronics enclosure (air transportable

rack) with powder metallurgy silicon carbide particle reinforced aluminum card guide.

(Reproduced by permission of SPARTA, Inc.) packaging. This provides great opportunities for new materials and processes. Once again, key properties are high thermal conductivity, low and tailorable CTE, and for avionics, low density. Cost is critical and depends on the application. This section considers future directions in materials, processes, and applications. Although we chart likely directions, experience has shown that new, unanticipated materials and processes undoubtedly will emerge. Continuing development of new materials is anticipated at all packaging levels. New and improved processes, such as pressure infiltration, pressureless infiltration, and investment casting, will reduce component cost, making composites more competitive with traditional materials [12,16,18,19]. Key particulate reinforcements are likely to be high purity silicon carbide, aluminum nitride, and beryllia. The well-known toxicity of BeO is likely to restrict its use. Because of their high thermal conductivity and low density, diamond particles also are attractive potential reinforcements. Their high cost at present is an obvious deterrent to their use. But there may be some instances where the unique benefits they offer could justify the expense. If new processes are found that reduce the cost of diamond particles, their use could expand dramatically. In the near future, the leading fiber reinforcements are likely to be pitch-based

The Future of Advanced Composite Electronic Packaging 141

Figure 6 . 1 8 Avionics rack made of powder metallurgy silicon carbide particle reinforced aluminum extrusions. (Courtesy DWA Composite Specialities.)

carbon. In the more distant future, carbon fibers made by chemical vapor deposition may well take on an important role. Theoretically, it should be possible to make fibers of aluminum nitride and silicon carbide that have high thermal conductivities. Depending on their cost, they too could be attractive reinforcements. Dominant metallic matrix materials are likely to be thermally conductive alloys of aluminum and copper. Beryllium may well be used in some cases, but toxicity problems and high cost undoubtedly will restrict its use. Epoxy is likely to remain the dominant matrix polymer for some time, but poiyimides, and electrically conductive polymers, and others seem certain to play their part. In recent years, there has been an increasing amount of work on composite solders and brazes [23,24,25]; primary benefits are improved strength, improved

142

MATERIALS FOR ELECTRONIC PACKAGING

creep resistance, and reduced CTE. Eventually, improved thermal conductivity may well be another advantage over monolithic materials. Ceramic-matrix composites have not yet been explored as a class of materials for electronic packaging. CMCs have the potential for significant improvements over monolithic ceramics: tailorable CTEs, higher thermal conductivities, tailorable dielectric properties, and higher fracture toughness, resulting in greater strength and resistance to thermal and mechanical shock.

6.5 Summary and Conclusions Advanced composites have had a revolutionary impact on structures [20,21,22], and their influence in electronic packaging may be equally dramatic. This chapter reviewed key current materials and applications and attempted to chart likely future directions. There can be little doubt of the importance of electronics in modern industrial society. Electronic packaging will play an increasingly important role in future electronic systems. We are witnessing the birth of a new industry in which multifunctional composite materials are created to meet the special needs of these systems.

References 1. C. Zweben and K. A. Schmidt, in Electronic Materials Handbook, Vol. 1, ASM International, Materials Park, Ohio, 1989. 2. C. Zweben, JOM (July 1992). 3. B. Nysten, L. Piraux, and J.-P. Issi, in Proc. 19th Int. Thermal Conductivity Conf., Plenum Press, New York, 1985. 4. B. Nysten and J.-P. Issi, Composites 21(4), 339-343 (1990). 5. J. P. Heremans et al., in Proc. 19th Int. Thermal Conductivity Conf., Plenum Press, New York, 1985. 6. K. A. Schmidt and C. Zweben, in Thermal and Mechanical Behavior of Metal Matrix and Ceramic Matrix Composites, A S T M STP 1080, edited by L. M. Kennedy, H. H. Moeller, and W. S. Johnson, ASTM, Philadelphia PA, 1989. 7. G. A. Slack, J. Appl. Phys. 35(12) 3460-3466 (1964). 8. Brush Wellman product data. 9. X. Dumant, Investment Cast Metal Matrix Composites for Microelectronics Packaoing, Cercast Group product brochure, May 3, 1991. 10. C. Thaw et al., SAMPE J., 23(6), 40-43, 1987. 11. "Breakthrough in Microwave Packaging Material," Materials and Processin9 Report, Jan. 1987, p. 5. 12. D. White et al., "New High Ground in Hybrid Packaging," Itybrid Circuit Technology, Dec. 1990. 13. J. Browne, "GaAs FET AMP Launches 16W for Space Station," Microwaves and RF, Feb. 1991, p. 114. 14. C. Zweben, in Encyclopedia of Materials Science and Engineering, edited by M.B. Bever, Pergamon Press, Oxford, 1986. 15. D.C. Packard, SAMPE J. (Jan.-Feb. 1984). 16. X. Dumant, S. Kennerknecht, and R. Tombari, "Investment Cast Metal Matrix Composites," SME Paper EM90-441, 1990.

The Future of Advanced Composite Electronic Packaging 143

17. K.A. Schmidt and C. Zweben, in Proc. 3rd SAMPE Int. Electronic Materials Conf. Los Angeles, 1989, scheduled. 18. A.J. Cook and P.S. Werner, Mater. Sci. Eng. A 144, 186-206 (1991). 19. M.K. Premkumar, D.I. Yun, and R.R. Sawtell, "Aluminum Composite Materials via Pressure Casting," paper presented at the TMS Annual Meeting, San Diego, CA, Mar. 1992. 20. C. Zweben, Learn from the Masters Lecture Series, Paper No. 81-0894, AIAA, 1981. 21. U.S. Congress, Office of Technology Assessment, Advanced Materials by Design, Report OTA-E-351, Government Printing Office, Washington, D.C., 1988. 22. Engineered Material Handbook, Vol. 1, Composites, ASM International, Materials Park, Ohio, 1987. 23. R.S. Clough, et al., in Proc. NEPCON West 1992, Cahners, Des Plaines IL, 1992, pp. 1256-1265. 24. S.M.L. Sastry et al., in Proc. NEPCON West 1992, Cahners, Des Plaines IL, 1992, pp. 1266-1275. 25. M. Zhu and D.D.L. Chung, "Carbon Fiber Silver-Copper Laminates as a Composite Brazing Material for Metal-Ceramic Joining," paper presented at Materials for Electronic Packaging, State University, Buffalo, NY, Aug. 1991.

This Page Intentionally Left Blank

CHAPTER

7

Low Thermal Expansion Composite Materials for Electronic Packaging D. D. L. Chung

7.1

Introduction

Accompanying the miniaturization and increasing power of integrated circuits is the problem associated with the heat generated by the electronics. The heat causes temperature increases. The turning of the electronics on and off then causes temperature cycling. In order for the electronic package to survive under this situation, the materials adjacent to one another in an electronic package need to have similar coefficients of thermal expansion (CTEs). Thermal expansion mismatch is a major source of failure in microelectronic structures involving metals, ceramics, and polymers. Examples of interfaces plagued by thermal expansion mismatch are copper-polyimide, where copper is the interconnection and polyimide is the interlayer dielectric; silicon-polyimide, where silicon is the chip and polyimide is the die attach adhesive; copper-alumina, where copper is the interconnection and alumina is the substrate; aluminum-alumina, where aluminum is the heat sink and alumina is the substrate; solder-alumina, solder-silicon, solder-Kovar; and braze-alumina. The thermal expansion mismatch leads to thermal fatigue failure. This problem can be alleviated by the use of composite materials, which allow the tailoring of the thermal expansion coefficient. Most of the problems of thermal expansion mismatch are associated with the high thermal expansion of a metal or a polymer. For example, the siliconpolyimide interface suffers from mismatch due to the high thermal expansion of polyimide compared to silicon; the copper-alumina interface suffers from mismatch due to the high thermal expansion of copper compared to alumina; the solderalumina interface suffers from mismatch due to the high thermal expansion of the solder compared to alumina. Examining ways to overcome the problem, this chapter focuses on metal-matrix and polymer-matrix composites of low thermal expansion. Their applications include heat sinks, backboards, substrates, soldering, brazing, die attach, and interconnections. To achieve a composite material of low thermal expansion with a high thermal expansion matrix, one needs a low thermal expansion filler at a large 145

146

MATERIALS FOR ELECTRONIC PACKAGING

volume fraction (up to 70%). As particles can be packed more densely than whiskers or short fibers, particulate fillers are usually used. Such high particulate filler volume fractions are usually associated with a low ductility; this is acceptable for heat sinks and substrates but undesirable for solders, brazes, and die attach adhesives. Thus, for solders, brazes, and die attach adhesives, it is important to minimize the filler volume fraction by improving the filler-matrix bonding. The use of a low thermal expansion joining material and the use of a compliant joining material are two different ways of alleviating the thermal expansion mismatch problem. No individual material has both a low CTE and a high compliance; this chapter considers only CTE. In order for the filler to be effective in lowering the thermal expansion of the composite, the filler-matrix bonding must be sufficiently strong. This bonding can be enhanced by the use of a coupling agent, such as silane in the case of a polymer matrix, the use of a coating on the filler, or the use of an alloying element in the case of a metal matrix. Criteria for the choice of a filler for low thermal expansion composite materials for electronic packaging include the following: 9 low CTE 9 strong bonding with the matrix 9 high thermal conductivity 9 low density High thermal conductivity stems from the need to dissipate heat generated by the electronics; low density applies mostly to aerospace electronics, where weight saving is important. Some ceramics, silicon, graphite, molybdenum, and tungsten are the main candidates for fillers, as they have low CTEs; their properties are listed in Table 7.1. Graphite is particularly attractive because of its combination of low thermal Table 7.1

Properties of filler materials, a

Material

CTE (10 -6 K -1)

A1203 SiC A1N Si Graphite c-axis a-axis Mo W

6.5 3.7 4.5 2.6 26 - 1 4 4

Thermal conductivity ( W m -1 K -1)

Density (g/cm 3)

30 270 320 150

4.0 3.2 3.3 2.3

6 2 000 130 150

2.2 2.2 10 19

"Graphite data from B.T. Kelly, Physics of Graphite, Applied Science Publishers, London, 1981. All other data from Materials for High-DensiO' Electronic Packaging and Interconnection, National Materials Advisory Board, National Research Council, National Academy Press. 1990.

low Thermal Expansion Composite Materials for Electronic Packaging 1 4 7

expansion, high thermal conductivity, and low density. Fillers in the graphite family include graphite flakes, carbon fibers, and carbon filaments.

7 . 2 H e a t Sinks, Backboards, and Substrates Heat sinks, backboards (motherboards to which cards or daughterboards are inserted), and substrates require materials of high thermal conductivity, so metals are suitable. However, the ceramic chip carrier attached to the heat sink, the card attached to the backboard, and the silicon chip attached to the substrate exhibit lower thermal expansion than most metals, including copper and aluminum. Metals or alloys that exhibit low thermal expansion (e.g., molybdenum, tungsten, and Kovar) happen to be high in density, so they are not suitable for aerospace electronics. Aluminum is a light metal, so low thermal expansion aluminum-matrix composites are particularly attractive for heat sinks, backboards, and substrates in aerospace electronics. Due to the galvanic couple formed by graphite in contact with aluminum, graphite is not a very suitable filler for aluminum. Molybdenum and tungsten are not suitable due to their high density. Suitable fillers include SiC, A1N, and Si, because of their appreciable thermal conductivity compared to AI20 3. Among SiC, A1N, and Si, A1N is particularly attractive because of its nonreactivity with aluminum, whereas SiC reacts with aluminum, and Si dissolves in aluminum. The nonreactivity of A1N with aluminum results in increases in the temperature resistance, ductility, and shear strength compared with the SiC composites [1]. Furthermore, A1N has a high thermal conductivity. Table 7.2 shows the CTEs at 35-200~ for A1N, SiC, and Si particulate composites with pure A1 and various A1 alloys as matrices [1,2]. The CTEs are similar for AIN and SiC composites of similar volume fractions (~ 55%). The use of AI-20Si-5Mg instead of pure AI as the matrix lowers the CTE due to the inherently lower CTE of AI-20Si-5Mg compared to pure A1. The low CTE value of 7.6 x 10 - 6 ~ - x attained by A1-20Si-5Mg containing 55.9 vol.% AIN is particularly attractive for applications as heat sinks, backboards, and substrates. Coefficient of thermal expansion (CTE) of aluminum-matrix particulate composites at 35-200~ from[I,2].

Toble 7 . 2

Matrix

Filler (vol.%)

CTE (10 -6 ~

A1

None A1N (58.6) SiC (55.0)

22.8 10.6 11.3

A1-20Si-5Mg

None A1N (55.9) SiC (55.0)

17.8 7.6 9.1

A1-30Si- 1Mg

None Si (50.0)

17.4 8.0

1)

148

MATERIALS FOR ELECTRONIC PACKAGING

For nonaerospace electronics, copper is a suitable matrix in spite of its high density, because of the high thermal conductivity of copper compared to aluminum. Graphite is an appropriate filler for copper because of the absence of a reaction or a galvanic couple between graphite and copper. Silicon carbide is also attractive; SiC whiskers are particularly attractive because of the superior mechanical properties in the resulting composite compared to the SiC particle counterpart. Molybdenum and tungsten are suitable fillers in spite of their high densities. The CTE of a copper-matrix composite containing 60 vol.% Mo particles is 7.5 • 10 - 6 ~ at 35-150~ [3]. Even for nonaerospace electronics, aluminum-matrix composites are more commonly used than copper-matrix composites. This is because of the high cost of fabricating copper-matrix composites compared to aluminum-matrix composites. Due to the low melting point of aluminum, aluminum-matrix composites are fabricated by liquid aluminum infiltration (either with or without pressure) into a porous preform consisting of the filler and possibly a small amount of a binder. Pressureless infiltration requires the use of an A1-Mg alloy rather than pure AI. Liquid metal infiltration is a near-net shape process, so shaping is conveniently achieved by machining the preform rather than the composite. The high melting point of copper means that liquid copper infiltration is not as common. Copper-matrix composites are commonly fabricated by powder metallurgy, a time-consuming and expensive process. Conventional powder metallurgy involves hot pressing a mixture of copper powder and the filler. Use of the mixture limits the maximum filler volume fraction to 40-60%. On the other hand, powder metallurgy involving hot pressing of a copper-coated filler allows the maximum filler volume fraction to reach 50-70%. The higher volume fraction is needed for obtaining a low CTE. Furthermore, the coated filler method results in composites with less porosity, superior mechanical properties, and slightly lower CTE than the conventional admixture method [3]. Because the metal matrix (Cu or A1) has a higher thermal conductivity than the ceramic filler (even A1N), the thermal resistance of the filler-matrix interface needs to be minimized in order for the composite to exhibit a high thermal conductivity. For the case of Al-matrix composites fabricated by liquid metal infiltration, the thermal resistance of the filler-matrix interface depends on the preform preparation conditions. For example, for the case of A1N particles as the filler, the preform should be heat treated in a vacuum (rather than air) and at the lowest possible temperature; the heating is required by the drying of the binder solution, but causes the formation of AI20 3 or aluminum oxynitride (of low thermal conductivity) on the surface of the A1N [4]. Table 7.3 lists the thermal conductivity of various aluminum-matrix composites. Carbon-carbon composites (carbon fiber carbon-matrix composites) are also attractive for heat sinks because of their low CTE (even lower than those of metal-matrix composites) and high thermal conductivity. However, their fabrication cost is extremely high, due to the need for multiple cycles of pitch/resin impregnation and carbonization/graphitization. Furthermore, for achieving a high thermal conductivity, continuous carbon fibers with a graphitic structure are

Low Thermal Expansion Composite Materials for Electronic Packaging 1 4 9

Table 7.3 Thermal conductivity of A1 and Al-matrix composites, as obtained via laser flash thermal diffusivity measurement and specific heat measurement, from [4]. Material

Thermal conductivity ( W m - 1 K - 1)

Density (9/cm 3)

212 157 134 126

2.7 3.0 3.0 3.0

A1 A1 with 59 vol.% A1Na A1 with 60 vol.% A I N b A1 with 55 vol.% S i C b a Preform heat treated in vacuum. bPreform heat treated in air.

necessary. Such fibers are extremely expensive. By using continuous graphitic pitch-based fibers (Amoco's K-1100), thermal conductivities of 400-483 and 46-50 W m-1 K - 1 have respectively been attained in the x- and z-directions of two-dimensional carbon-carbon composites [4]. The K-1100 fibers themselves have a thermal conductivity of 1180 W m - l K -1 and are the most advanced pitch-based carbon fibers. Slightly less advanced are Amoco's P-120 fibers (also pitch-based), which have a thermal conductivity of 600 W m -1 K-1. A twodimensional carbon-carbon composite made with P-120 fibers exhibits thermal conductivities of 349-412 and 24-47 W m -1 K -1 in the x- and z-directions respectively [5]. Carbon fiber polymer-matrix composites are also attractive for heat sinks. Although their thermal conductivity is lower than those of carbon-carbon composites, their fabrication cost is much lower. For achieving a high thermal conductivity, continuous carbon fibers with a graphitic structure are necessary. Because the polymer matrix is thermally insulating (in contrast to carbon and metal matrices), carbon fiber polymer-matrix composites suffer from a low thermal conductivity in the direction perpendicular to the fiber layers. A unidirectional epoxy-matrix composite made with Amoco's P-120 carbon fibers exhibits thermal conductivities of 365 and 1.9 W m-1 K - 1 in the x- and z-directions respectively [6]. Sandwich composites involving Mo or Cu as the outer layers and Invar or a carbon fiber polymer-matrix composite as the inner layer are used for backboards. The sandwiching is due to the relatively low thermal conductivity of Invar and of carbon fiber (not graphitic) polymer-matrix composites. Graphitic carbon fibers are high in thermal conductivity but they are very expensive. 7.3

Brazes a n d Solders

Brazes and solders conventionally in the form of alloys suffer from a high CTE compared to silicon or ceramics in the electronic package. This problem is aggravated in brazed joints because of the high temperatures used during brazing.

150

MATERIALS FOR ELECTRONIC PACKAGING

Although soldering is performed at relatively low temperatures, the large number of soldered joints in an electronic package makes the reliability of each soldered joint critical to the reliability of the overall assembly. Furthermore, the proximity of soldered joints to the die (chip) causes soldered joints to experience thermal cycling as the electronics are turned on and off periodically. Though the temperature excursion may be small, this thermal cycling causes fatigue in the soldered joint because solders melt at low temperatures. The problems associated with brazes and solders can be alleviated by the use of composite brazes or solders which contain a filler of low CTE. Graphite is a suitable filler for alloys typically used for brazing and soldering, such as silver-based braze alloys and tin-based solder alloys. Carbon fibers have been successfully used as a filler for both brazes [7,8] and solders [9], though metal-coated carbon fibers are necessary for enhancing the wetting of the liquid solder/braze on the carbon fibers, unless an active (titanium-containing) brazing or soldering alloy is the matrix. When an active alloy is used, the titanium in the alloy segregates at the alloy-fiber interface, whether the fiber is metal-coated or bare, thereby enhancing the wetting of the fibers. This segregation is due to the reaction between Ti and C to form TiC. On the other hand, reaction between Ti and A1203 causes Ti segregation at the alloy-A1203 interface, thereby enhancing the wetting of the A1203 substrate. The presence of carbon fibers in the brazing material thus causes a reduction in the thickness of the reaction layer at the alloy-A1203 interface. This reduction is attractive as the reaction product is brittle. The CTE decrease, reaction layer thickness reduction, and strengthening resulting from the fiber addition contribute to the observed increase in the strength of the brazed joint [8]. Either short or continuous carbon fibers can be used. Short fibers are needed if the solder or braze is to be applied in the form of a paste. Continuous fibers are more effective than short fibers in decreasing the CTE, but they cannot be in a paste form and are thus limited to applications in solder/braze preforms. By using 29 vol.% continuous, unidirectional, copper-coated carbon fibers in a tin-based solder, the CTE is decreased from 24 x 10 -6 ~ 1 to 8 x 10 -6 ~ 1 at 25-105~ in the direction parallel to the fibers [9]. The variation of the CTE with fiber volume fraction, temperature, and direction is shown in Table 7.4. By controlling the fiber volume fraction, the CTE of the composite can be tailored.

7 . 4 Die Attach Polymers are used as adhesives for attaching a die to a substrate. Due to the low CTE of the die and the substrate, a low CTE is desired for the adhesive. A filler of low CTE can be added to the polymer for this purpose. Because of the need to dissipate heat from the die and because polymers are in general thermal insulators, the filler is preferably a thermal conductor. Graphite and A1N are thus suitable fillers (see Table 7.1). As the strength of the filler-matrix bonding varies greatly with the choice of the combination of filler and matrix, the most suitable

Low Thermal Expansion Composite Materials for Electronic Packaging

1 51

Coefficients of thermal expansion (CTEs) for solder-matrix composites containing various volume fractions of copper-coated carbon fibers, in directions parallel (11)and perpendicular (2_) to the fibers, from [11]. Table 7 , 4

CTE (10 - 6 ~ Vol.% .fibers

Direction

25

35

45

at the given temperature (~ 55

65

75

85

95

105

8.2

II 2.

10.42 18.32

11.37 12.16 13.09 14.23 15.10 15.94 16.23 16.98 19.47 20.11 21.42 22.37 22.90 23.42 24.78 25.32

17.12

It 2.

8.43 17.39

8.90 9.24 9.79 10.21 11.80 12.72 13.41 14.10 18.00 18.47 19.41 20.83 21.74 22.71 23.62 24.83

29.42

II 2.

4.31 16.80

4.90 5.70 6.92 7.91 8.42 9.53 10.43 11.84 17.80 18.32 19.11 20.52 20.99 21.43 22.84 24.12

42.37

II 2.

0.62 15.93

0.74 0.92 1.10 1.14 1.20 1.27 1.36 1.47 16.24 17.32 18.42 18.99 19.92 21.11 22.10 23.8

54.1

II

-0.89

Table 7 . 5

-0.80

-0.64

CTE (30-100~

-0.64

-0.64

0 4.1 8.7 17.1 27.7 36.5

-0.60

-0.62

-0.62

of A1N particle filled polyimide siloxane. CTE (10 -6 ~

Vol. % A1N

-0.62

1)

Without coupling agent

With coupling agent

101.5 83.2 74.0 52.9 21.3 20.1

NA 49.0 34.7 w

NA = not applicable.

filler depends on the polymer. When bonding is poor, a coupling agent may solve the problem. Table 7.5 shows the CTE of A1N particle (4/tm) filled polyimide siloxane (Occidental Chemical Company, SIM-2030MO) for the cases with and without a silane coupling agent (PCR Incorporated, Prosil-9215). The CTE is greatly reduced by the use of the coupling agent, so a lower filler volume fraction is possible when the coupling agent is used. Solders in the form of solder pastes [10] compete with polymeric adhesives for use as screen printable die attach. The attraction of solders lies in their high thermal conductivity, but their defluxing chemicals can harm the environment. Like polymeric adhesives, solders suffer from a high CTE. Solders suffer in particular because they are fatigued by thermal stresses arising from CTE mismatches. Use of an active (titanium-containing) solder together with a low CTE filler (such as molybdenum particles) alleviates CTE mismatch but it makes the solder less ductile.

152

MATERIALS FOR ELECTRONIC PACKAGING

7.5

Interconnections

Thick film interconnections are screen printed as a metal-glass paste (glass as the binder) on ceramic green sheets and subsequently cofired with the ceramic to form a multilayer substrate (chip carrier). Due to the low CTE of the ceramic, the thick film conductor material for the interconnections should also have a low CTE, and this is helped by the presence of glass in the thick film. The glass concentration is highest at the film-ceramic interface and this provides a CTE graded junction. For the case of A120 3 as the ceramic, Mo or W are used for the interconnections because of the high sintering temperature of A120 3. These refractory metals have low CTEs, so there is no thermal mismatch problem even if glass is not considered. But in low temperature (< 1 000~ cofired ceramics, which use Cu or Au interconnections (better electrical conductors than Mo or W), the high CTE of the metal compared to the ceramic makes the glass more important. This problem can be further alleviated by the use of a mixture of Cu and Mo particles in the thick film paste, or for more effective sintering, by the use of Cu-coated Mo particles. Interconnections may be formed by screen printing on a sintered ceramic substrate using a metal-polymer paste, in which the polymer serves as the binder. Because of the high CTE of the polymer in contrast to the low CTE of glass, the CTE mismatch is significant, especially in the case of high power electronics, and it requires a low CTE conducting filler, such as graphite, Mo, or Cu-coated Mo. In some high power electronics, interconnections (e.g., Cu) are deposited on a sintered ceramic substrate by plating. The high CTE of the metal interconnection compared to the ceramic substrate is a problem, but it can be alleviated by plating composite interconnections. For example, a low CTE filler can be dispersed in the electrolyte solution during electroplating for incorporation into the film formed by plating. The filler can be ceramic particles such as A120 3.

Acknowledgment This work was supported by the Defense Advanced Research Projects Agency of the Department of Defense and the Center for Electronic and Electro-Optic Materials of the State University of New York at Buffalo.

References 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

S.-W. Lai and D.D.L. Chung, J. Mater. Sci., in press. Y. Chen and D.D.L. Chung, J. Mater. Sci., in press. P. Yih and D.D.L. Chung, in press. S.-W. Lai and D.D.L. Chung, J. Mater. Sci., 29, 3128-3150 (1994). W.H. Pfeifer, J.A. Tallon, W.T. Shih, B.L. Tarasen, and G.B. Engle, in Proc. 6th Int. S A M P E Electronics Conf., 1992, pp. 734-747. A.M. Ibrahim, in Proc. 6th Int. S A M P E Electronics Conf., 1992, pp. 556-567. J. Cao and D.D.L. Chung, Weldin9 Res. Suppl. 71(1), 21-24 (1992). Mingguang Zhu and D.D.L. Chung, J. Am. Ceram. Soc., in press. C.T. Ho and D.D.L. Chung, J. Mater. Res. 5(6), 1266-1270 (1990). L.T. Shi, R. Saraf, and W.S. Huang, Processin9 Adv. Mater. 3, 57-62 (1993).

CHAPTER8

Conducting Polymer-Matrix Composites D. D. L. Chung, Lin Li

8.1

Introduction

Electrically conducting polymer-matrix composites are used in electronic packaging as die attach adhesives and electromagnetic interference (EMI) shielding materials. They are preferred to solder because they reduce heating, they have a smaller footprint, and they need no defluxing, which is costly and can damage the environment. If a thermoplast-matrix composite rather than a thermoset-matrix composite is used, the die attachment is reworkable. The use of conducting polymer-matrix composites in place of metal (e.g., aluminum) sheets for EMI shielding is attractive because they are easy to shape by molding and most have a low density. Metal coatings for EMI shielding suffer from degradation of their shielding effectiveness caused by scratching or wear. The market for EMI shielding materials is growing due to the increasing sensitivity and abundance of electronics. Composites that are resilient as well as conducting are used for electrical contacts. Separable connectors consist of resilient, conducting buttons inserted through holes in a buttonboard, an insulating sheet that facilitates electrical connections between printed wiring boards. Electrical connections are also made along the z-axis of three-dimensional electronic packages. Silver particles are widely used as a filler in conducting polymer-matrix composites because of their low electrical resistivity and superior oxidation resistance compared to copper. But they do suffer from silver migration and face competition from less expensive particles such as solder and nickel, which is more electrically resistive but more oxidation resistant than copper. For EMI shielding, the volume of material usage is large compared to that for die attach adhesives, so cost becomes a more important factor. Nickel particles and aluminum flakes are increasingly popular for EMI shielding. The choice of a filler is also governed by the composite processing method. When screen printing is the method employed, the filler is preferably in the form of fine particles of size less than 25 ~m. This requirement for a small size rules out aluminum flakes as well as short conducting fibers. But when composites are injection molded or extruded this requirement does not apply, and both flakes 153

154

MATERIALS FOR ELECTRONIC PACKAGING

and short fibers are possible fillers. The attraction of flakes and fibers compared to particles lies in the large aspect ratio, which makes it possible for the composite to achieve a low resistivity at a relatively small filler volume fraction. For the case of a composite made by injection of a polymer liquid into a porous preform consisting of the filler (possibly together with a small proportion of a binder), a filler in the form of a three-dimensional network is possible. The attraction of a three-dimensional network lies in the essential absence of a contact resistance within the network. In contrast, for particles, flakes, or short fibers as the filler, a contact resistance exists between adjacent particles/flakes/fibers even if the particles/flakes/fibers touch one another and the polymer matrix separating the adjacent particles/flakes/fibers gives rise to additional resistance. A composite containing a conducting network achieves a low resistivity at a filler volume fraction even lower than for flake or short fiber fillers. A stiff conductor network is inappropriate for a resilient composite, but soft conductor networks have recently been developed for this situation There has been much progress in the area of three-dimensional networks, and we examine it in Section 8.4. Addition of a second filler in small proportions can greatly decrease the resistivity of a polymer-matrix composite. The key to this effect lies in the ability of the second filler to melt during the composite processing and for the molten second filler to wet the solid first filler. The effect is particularly large when the first filler is in the form of short fibers rather than particles. Because it connects to the first filler, the second filler offers in situ production of a three-dimensional conductor network out of initially discontinuous materials amenable to injection molding, extrusion, and other composite processing methods. The in situ production of a conducting network using a single filler, initially in the form of particles, can be achieved by hot pressing, provided the filler melts while the polymer matrix is a viscous solid. Instead of forming a network in situ, a conducting particulate filler may melt, coalesce, and form a slug in situ, such that the polymer resides in the periphery of the slug and entraps some filler particles there. Whether a network or a slug is formed in situ depends on the viscosity of the thermoplast melt and the processing temperature and pressure. The slug form is associated with a high filler volume fraction (> 50 vol.%), whereas the network form is associated with a low filler volume fraction (< 50 vol.%). An increase in the filler volume fraction generally decreases the resistivity of the composite, but it also decreases the ductility (elongation at break), unless the filler is very ductile, like solder. Although high strength is not necessary for most electronic applications, brittleness is not desirable. Therefore, for the sake of ductility and low cost, a low filler volume fraction is desirable, except for the case of a slug composite. By resistivity, we have so far been referring to the volume resistivity. For applications in electrical contacts, the contact resistivity is also of concern. Compared to metals, conducting polymer-matrix composites containing discontinuous fillers suffer from a high contact resistivity due to the presence of a polymer film on the surface of the composite. However, a composite containing

Conducting Polymer-Matrix Composites 1 S S

a continuous filler (such as a three-dimensional network) that is not strongly bonded to the polymer matrix can have the filler slightly and cleanly protruding from the surface of the composite; in this case the contact resistivity can be low. Although the weak filler-matrix adhesion causes a loss of the mechanical properties, the loss is limited because the conductor network and the polymer matrix can be mechanically interlocked. A low contact resistivity provides an added benefit for using a composite containing a conductor network. The presence of a filler in a polymer generally causes the coefficient of thermal expansion (CTE) to decrease. This side effect is desirable, as the neat polymer suffers from a high CTE compared to the CTEs of surrounding components. A matched CTE helps the durability of the package under thermal cycling. A polymer-matrix composite that is electrically conducting in one direction only is called a z-axis conductor, in contrast to an isotropic conductor. A z-axis conductor allows multiple electrical contacts to be made parallel to one another with a single piece of material, the z-axis conductor. It can replace a solder bump array in surface mount technology, thereby saving processing costs. It can be in the form of a resilient conductor or an adhesive. 8.2

Particles as t h e Filler

For metal particle filled polymers, two configurations of packing metal particles in a polymer matrix have been observed. They are known as random and segregated arrangements [1]. In the random arrangement, continuity relies strictly on the chance contact between contiguous sites, as governed by percolation theory. Both metal and polymer particles are similar in effective size and shape, and each may occupy any site in the packing arrangement. In contrast to the random arrangement, the segregated arrangement is associated with network formation governed by restricting the occupiable volume for each metal particle; instead of the entire field, each metal particle has only the interproximal contacts or the interstices of the polymer particles. Therefore, the metal particles are segregated into a reticulated structure. Generally speaking, composites with the random arrangement are amenable to injection molding or extrusion techniques, whereas composites with the segregated arrangement are normally processed by compression molding. As a result of the geometric arrangement, a critical volume loading of metal particles is needed to achieve continuity in the composite. The critical volume fraction can be determined by using the relative particle size ratio (radius of the polymer particles, Rp, to the radius of the metal particles, Rm). The relationship between the critical volume fraction and the particle size ratio, Rp/Rm, was established by Kusy [2]. Using his model, the segregated arrangement is preferred for a large particle size ratio, whereas the random arrangement is preferred for a small particle size ratio. Gusland [3-1 showed that, in a composite with the random arrangement, the critical volume loading required for continuity was 35-37% (effective Rp/R m ,~ 2), whereas Kusy and Turner [4-1 showed that only 6 vol. % was needed (Rp/R m -- 30) for a composite with the segregated arrangement.

156

MATERIALSFOR ELECTRONIC PACKAGING

Table

8.1

Resistivity of conducting powder filled SIM-2030M composite materials. Filler content

Filler

Particle size (ILm)

Wt.%

Vol.%

Resistivity (f~ cm)

Silver

0.8-1.35

10 20 30 40 50

1.3 2.9 4.9 7.4 10.7

2.42 x 108 2.12 • 108 0.131 2.26 X 10 - 3 9.76 • 10 -4

(_ 0.28 • 108) ( ___0.21 • 108) (+0.021) (+0.17 x 10 -3) (+0.75 • 10 -4)

Nickel

1-5

10 20 30 40 50

1.6 3.4 5.7 8.7 12.4

7.53 • 5.34 • 0.155 6.75 • 2.31 •

(+0.30 • (+0.04 • (+__0.005) (__+0.74• (+0.14 •

108 108 10 -3 10 -3

108) 108) 10 -3) 10 -3 )

Examples of the electrical and mechanical properties of conducting particulate polymer-matrix composites are given below. The competition between silver particles and nickel particles is shown in Tables 8.1 through 8.3 in terms of the electrical resistivity, EMI shielding effectiveness, and tensile properties, respectively, of composites with polyimidesiloxane (Occidental Chemical Corporation, SIM2030M) as the matrix [5]. The properties of the neat polymer and the fillers are shown in Tables 8.4 and 8.5, respectively. Silver particles provide a lower resistivity in the composite than nickel particles at a similar volume fraction, but the difference is not large (Table 8.1). On the other hand, silver particles provide much poorer EMI shielding effectiveness than nickel particles, as measured by the coaxial cable method at 1-2 GHz (Table 8.2). The origin of the poor shielding effectiveness of silver is not clear. Silver particles decrease the tensile strength when their volume fraction exceeds 1.3 %, but nickel particles decrease the tensile strength when their volume fraction exceeds 8.7% (Table 8.3). Thus, the mechanical properties of the nickel composite are superior to those of the silver composite. This is because of the smoother surface and poorer filler-matrix bonding for the silver particles, as revealed by fracture surface examination. 8.3

F l a k e s a n d Fibers as Fillers

Competing types of flakes and short fibers for EMI shielding include carbon fibers (bare and metal-coated), nickel fibers, stainless steel fibers and aluminum flakes. The status of this competition should be evaluated by considering (1) the minimum filler volume fraction for achieving at least a given level of EMI shielding effectiveness, and (2) the maximum filler volume fraction for maintaining sufficient mechanical strength and ductility. For any filler the shielding effectiveness increases monotonically with increasing filler volume fraction, while the tensile strength usually increases with increasing filler volume fraction below a certain filler volume

Table 8.2

EM1 shielding effectiveness (dB) of nickel powder filled and silver powder filled SIM-2030M composite. EM1 slzie/ding effectiveness (dB) at the given frequencj9 ( G H z )

Filler corrtent Filler

Wt.%

Vol.%

Nickel, 1-5 {tm

30 40

5.7 8.7

Silver 0.8-1.35 ltm

30 40

4.9 7.4

Tl~ickness (mm)

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.85 2.95

42.5 50.0

40.5 >SO

39.0 >50

37.5 >50

38.5 >50

37.5 >50

39.0 >50

41.5 >50

43.2 >50

45.0 >50

44.0 >50

2.82 2.85

2.6 8.7

3.2 8.2

2.7 7.4

1.9 6.2

0.9 5.8

1.4 6.2

0.7 7.3

0.5 9.2

0.5 10.5

0.4 12.1

1.2 12.5

3

Q

3P B

Q

$

158

MATERIALS FOR ELECTRONIC PACKAGING

Table 8 . 3

Mechanical properties of conducting powder filled SIM-2030M composite

materials.

Filler content Density Tensile strength Wt.% Vol.% (9 cm3) (MPa)

Filler

Modulus (GPa)

Elongation (%)

Nickel, 1-5/~m

0 10 20 30 40 50

0 1.6 3.4 5.7 8.7 12.4

1.25 1.39 1.52 1.65 1.88 2.19

39.5 (+2.0) 40.2 (+0.8) 45.4 (+ 1.9) 49.9 ( + 1.5) 51.2 (+ 1.5) 45.4 (+3.0)

2.11 (+0.11) 2.27 (+0.10) 2.46 (+0.06) 2.67 (+ 0.04) 2.98 (+0.03) 3.54 (+0.15)

2.10 (+0.13) 1.94 (+0.11) 2.05 (+0.19) 2.28 (+ 0.06) 2.08 (+0.09) 1.60 (+0.19)

Silver, 0.8-1.35 ktm

0 10 20 30 40 50

0 1.3 2.9 4.9 7.4 10.7

1.25 1.35 1.48 1.64 1.91 2.19

39.5 (+2.0) 49.6 (+ 1.7) 47.5 (+0.7) 46.7 (+ 1.4) 42.5 (+0.8) 39.5 (+ 1.9)

2.11 (+0.11) 2.31 (+0.10) 2.39 (+0.03) 2.42 (+0.05) 3.14 (+0.11) 3.16 (+0.09)

2.10 (+0.13) 2.55 (+0.12) 2.28 (+0.11) 2.10 (+0.06) 2.01 (+0.07) 1.91 (+0.07)

Table 8 . 4

Properties of SIM-2030M polymer.

Density Particle size Tensile strength Tensile modulus Elongation at break Electrical resistivity Coefficient of thermal expansion

Table 8 . 5

1.25 g cm 3 50-100 #m 39.5 + 2.0 MPa 2.1 + 0.11 GPa (2.1 + 0.13)% > 10 ~~ f~ cm 74.4 • 10 -6 K -1 (30-100~ 86.4 • 10 -6 K-1 (30_150oc)

Properties of conducting powders.

Material Silver Nickel Graphite flakes

Particle size (l~m)

Density (9/cm 3)

0.8-1.35 1-5 78-127 25.4

10.49 8.80 2.25

Electrical resistivity (~ cm) 1.49 6.14

X 10 - 6 X 10 - 6

5.0 x 10- 3

CTE at 30-100~ (10 -6 K -1) 19.2 12.7 27.3 ( c )

-0.5 (_L c) fraction then decreases with further increase in the filler content. The stronger the filler-matrix bonding the greater the filler volume fraction above which the strength decreases with increasing filler volume fraction. This second consideration depends on the polymer used. Table 8.6 shows the minimum filler volume fractions to exceed 50 dB shielding effectiveness at 1.5 GHz for a polyether sulfone (PES) thermoplast matrix filled

Conducting Polymer-Matrix Composites 1 59

with bare carbon fibers, nickel fibers, stainless steel fibers, and aluminum flakes. The carbon fibers were based on isotropic pitch as the precursor and were of length 200 ~tm or 400/~m and diameter 10/~m, as provided by Ashland Petroleum Company. The nickel fibers were of length 1 000 /~m and diameter 20 /~m, as provided by National-Standard Company. The stainless steel fibers were of length 1 590 /~m and diameter 30-56 /~m, as provided by International Steel Wool Corporation. The aluminum flakes were of size 1.2 mm x 1.0 mm x 0.03 mm, as provided by Transmet Corporation. Table 8.6 shows that nickel fibers and stainless steel fibers are more effective than aluminum flakes for EMI shielding, and that carbon fibers (200/~m or 400 #m long) are the least effective of all four [6]. It should be noted that carbon fibers are available in various lengths and the shielding effectiveness increases significantly with increasing fiber length, as shown in Table 8.7 for a fixed filler volume fraction of 20%. Nevertheless, carbon fibers of length 3 000/~m are still not as effective as nickel fibers of length 1 000/~m or stainless steel fibers of length 1 590/~m, as shown in Table 8.7. Table 8.7 also compares bare carbon fibers (10/~m diameter) and nickelcoated carbon fibers. The nickel coating was deposited by electroplating; its thickness was about 0.34/~m. The electrical resistivity of a nickel-coated carbon Table 8 . 6

Minimum filler volume fraction for EMI shielding effectiveness > 50 dB.

Filler

Volume fraction ( % )

Carbon fibers (200, 400 tLm) Ni fibers Stainless steel fibers A1 flakes

40 20 20 30

Table 8 . 7

EMI shielding effectiveness of PES containing 20 vol.% of various fillers. Filler (20 vol. % )

C fibers (bare) 100 ~m 200 ~tm 400 stm 800/~m 3000 ~Lm Ni fibers Steel fibers A1 flakes C fibers (Ni-coated) 400/~m

E M I shieldin9 effectiveness at 1.5 GHz (dB)

5.1 14.4 14.8 19.5 41.8 > 50 > 50 35.2 16.0

160

MATERIALS FOR ELECTRONIC PACKAGING

fiber was 7.4 x 10-5 ohm cm, compared to 3.5 x 10-3 ohm cm for a bare carbon fiber. Table 8.7 shows the nickel coating only increases the shielding effectiveness from 14.8 dB to 16.0 dB. Although nickel fibers and stainless steel fibers are very effective for EMI shielding, they suffer from weak bonding with polyethersulfone (PES). The tensile strength of PES-matrix composites decreases with increasing filler volume fraction when the content of nickel or stainless steel fibers exceeds just 10 vol.%. On the other hand, the tensile strength of PES-matrix composites decreases with increasing filler volume fraction when the content of carbon fibers of length 200 #m or 400 #m exceeds 30 vol.%. For carbon fibers of length 100 #m and for aluminum flakes, the tensile strength increases monotonically with increasing filler volume fraction up to a filler content of at least 40 vol. %. Thus, consideration of both the electrical and mechanical properties indicates that aluminum flakes are most attractive for the case of PES as the matrix. In particular, a PES-matrix composite containing 40 vol.% aluminum flakes exhibits an EMI shielding effectiveness exceeding 50 dB at 1-2 GHz, a volume resistivity of 7 x 10 -5 ohm cm and a tensile strength of 67 MPa. Furthermore, the resistivity of the aluminum flake composite is not affected by heating in air at 140~ for up to at least 144 h [6]. The superior mechanical properties of PES-matrix aluminum flake composites compared to PES-matrix composites containing nickel fibers, carbon fibers, or stainless steel fibers at the same filler volume fraction is related to the low wetting angle between PES and aluminum, as shown in Table 8.8. Electronic components are now so tiny that composites of small dimensions are attractive for electronic packaging. The small dimensions are particularly important for thick films rather than bulk composites. Small composites require comparable fillers; carbon fibers are typically 10 #m in diameter, but carbon filaments (catalytically grown from carbonaceous vapor) are typically 0.1 #m in diameter. Fibers and filaments of given length and volume fraction have very different aspect ratios. The large aspect ratio of the composite filaments causes them to exhibit lower electrical resistivity and higher EMI shielding effectiveness than the corresponding composite fibers. However, the filament composite is associated with a much larger filler-matrix interface area, and in the case of poor filler-matrix bonding it exhibits inferior mechanical properties at a given filler volume fraction; PES matrices are a case in point [7]. The most common methods for fabricating polymer-matrix composites

Table 8 . 8

Wetting angles of PES with different filler materials.

Filler material

Wetting angle (deg.)

Tensile strength at 20 vol.% filler (MPa)

AI Ni Carbon Stainless steel

105 133 145 150

65 51 64/62/61/58/51 44

Conducting Polymer-Matrix Composifes 1 i l l

containing flakes or short fibers involve extrusion, in which the filler and the polymer liquid are mixed under shear by means of screws. The shear helps prevent nonuniform distribution of the filler due to the difference in density between the filler and the polymer liquid. However, this method is limited to low filler volume fractions, as the viscosity of the slurry increases with increasing filler content. For fabricating composites with a high filler volume fraction, an alternative is to inject the polymer liquid into a porous agglomerate of the filler, a filler preform. Success depends greatly on the quality of the preform, particularly the uniformity of the filler. The shape of the final composite can be controlled by controlling the shape of the preform. Short fibers are more suitable for preform preparation than flakes. For example, a cylindrical preform of short nickel fibers was prepared by spreading the fibers to form a blanket and then rolling the blanket into a cylinder [8]. 8 . 4 T h r e e - D i m e n s i o n a l N e t w o r k s as Fillers

Three-dimensional networks can be ex situ or in situ. Ex situ networks are created before incorporation in the polymer matrix; in situ networks are created within the polymer matrix during composite fabrication. The three-dimensional network structure is generally more completely formed in ex situ networks, so for a given volume fraction they are usually more effective at lowering the electrical resistivity and increasing the EMI shielding effectiveness. Their superior mechanical integrity allows mechanical interlocking between the filler and the matrix and significantly enhances the mechanical properties of the composite. In the case of poor filler-matrix adhesion, ex situ networks allow part of the filler to protrude from the surface of the composite for the purpose of lowering the contact resistivity. In situ network fillers can be incorporated in the polymer matrix using processing techniques that are typically used for particulate, flake, or short fiber fillers, ex situ network fillers cannot. In other words, in situ network fillers can be used in the form of a slurry containing the polymer liquid; ex situ network fillers cannot. An ex situ network can be formed into a desired shape, a preform, then injected with the polymer liquid to form the composite. 8 . 4 . 1 Ex Situ N e t w o r k s

An ex situ network composite can take the form of a network embedded in a polymer matrix, akin to fibers embedded in a polymer matrix. It can also take the form of two interpenetrating networks, namely the filler network and the polymer network. The filler material and the network structure determine the stiffness of the network; a soft filler creates a soft network and interconnected springs create a resilient network. A resilient network is needed to make a resilient composite. In a conductor network all materials, including the interconnections, must be electrically conducting. An example of an embedded composite is a three-dimensionally interconnected metal spring network in a silicone matrix. Spiral or C-shaped copper springs are interconnected by tin-lead solder. Spiral springs are much larger than

162

MATERIALS FOR ELECTRONIC PACKAGING

C-shaped springs, so C-shaped springs are more suitable for composites of small dimensions, as required for the buttonboard application. However, spiral springs result in a network that is more completely interconnected. Composite fabrication involves injection of the polymer liquid into the spring preform. Table 8.9 shows the volume resistivity of silicone-matrix spiral spring composites. A resistivity of 5 • 10 -4 ohm cm was achieved at a filler volume fraction of 6% [9]. In contrast, this low level of resistivity requires a filler volume fraction of 35% if silver particles are used as the filler [10]. Table 8.9 also compares the measured and calculated values of the volume resistivity. The calculated values were obtained from a model that uses the rule of mixtures and assumes the conducting filler is continuous and unidirectional. The ratio of the measured resistivity to the calculated resistivity is around 3 for all filler volume fractions, indicating the network is indeed threedimensionally interconnected. Figure 8.1 shows that a contact resistivity of

Table 8.9

Volume electrical resistivity of composites with solder. Resistivity (m~ cm)

Total filler vol. %

4.17 4.90 5.56 6.00

Cu vol. %

Solder vol. %

2.10 2.30 2.70 3.10

2.07 2.60 2.86 2.90

Measured

0.814 0.765 0.613 0.535

+ + + +

Calculated

Resistivity ratio (measured/calculated)

0.294 0.253 0.222 0.203

2.77 3.02 2.76 2.63

0.010 0.010 0.015 0.010

0.04 eq U

d 4J ","4 > "4

3.1 vol.% Cu + . . solder

003

0.02

o~ 4J

0.01

4J 0 U

O0 ....

i ....

I ....

i ....

l

0.025 0.050 0.075 0. i00 Pressure

(MPa)

Figure 8.1 The contact resistivity as a function of pressure for a silicon-matrix composite containing 3.1 vol.% Cu and 2.9 vol.% Sn-Pb in contact with a copper sheet (e) before and after ( x ) immersion in water for 7 days.

Conducting Polymer-Matrix Composites 163 0.018 ohm cm 2 is obtained for a spring network composite with 6 vol.% total filler in contact with a copper sheet at a contact pressure of 0.025 MPa. This low contact resistivity is because the spring wires slightly and cleanly protrude from the surface of the composite. In contrast, conventional polymer-matrix composites are covered by a layer of polymer at the surface. The copper springs are coated by the tin-lead solder, though the solder is concentrated at the spring interconnections. The oxidation resistance of the spring network composite is very good and the electrical properties of the composite are not affected by heating in air at 130-150~ for 7 days or by immersion in water for 7 days. An example of an interpenetrating composite is a tin-silicone [11] made by injecting silicone into a tin foam. The tin foam is created by infiltrating liquid tin into an NaC1 preform later washed away with water. The tin-silicone composite contains 14 vol.% tin and exhibits a volume resistivity of 5 x 10 -4 ohm cm. Although tin is quite soft, the tin network is far less resilient than the copper spring network, so the tin-silicone composite is not highly resilient. 8 . 4 . 2 In $itu Networks

In situ networks can be formed using two methods. One method uses a second filler that melts during composite fabrication. The molten second filler interconnects the first filler, still solid and preferably in the form of fibers [12,13]. Both fillers must be electrically conducting. The second method uses a single particulate filler that melts while the polymer matrix is a viscous solid. Hot pressing this liquid-solid composite causes the melt to flow and form a three-dimensionally interconnected flake network upon subsequent solidification [14]. The first method allows the use of the conventional polymer processing temperature, as long as it is above the melting point of the second filler. But the second method does not allow the use of the conventional polymer processing temperature because the polymer has to be a liquid instead of a viscous solid. Processing below the conventional polymer processing temperature degrades the mechanical properties of the resulting composite. The first method is suitable when the first filler is short nickel-coated carbon fibers (20 vol.%), the second filler is tin-lead particles (2 vol.%), and the matrix is polyethersulfone (PES) [9]. Addition of the second filler (only 2 vol.%) reduces the volume resistivity by a factor of 2000 and increases the EMI shielding effectiveness at 1 GHz from 19 dB to 45 dB. The metal coating on the carbon fibers is necessary for the molten tin-lead to wet the fibers. The second method is suitable when the filler is tin-lead particles, prior to hot pressing and the polymer matrix is PES. After hot pressing uniaxially so the tin-lead is molten and the PES is a viscous solid with a complex viscosity of 1.24 MPa s, the filler becomes a three-dimensionally interconnected flake network. With 15 vol.% tin-lead, the PES-matrix in situ composite, hot pressed at 240~ and 6.5 MPa, exhibits lower volume resistivity and higher EMI shielding effectiveness than a PES-matrix composite containing 15 vol.% aluminum flakes not in the form of a network [14].

164

MATERIALS FOR ELECTRONIC PACKAGING

An in situ thermally conducting (but electrically insulating) network composite has not yet been developed. But akin to an in situ thermally conducting network composite is a composite containing a mixture of thermally conducting particles and thermally conducting short fibers (or whiskers). One example contains AIN particles and SiC whiskers. The whiskers are not bonded to the particles, so the composite is not a true network composite. Nevertheless, the proximity of the whiskers and particles results in a bridging effect, similar to a true network but less dramatic. Even though the SiC whiskers have poorer thermal conductivity than the A1N particles, the substitution of one-quarter of the A1N particles by SiC whiskers increases the composite's thermal conductivity from 1.76 W m-~ K to 2.23 W m-~ K-~ for the case of a fixed total filler content of 50 vol.% and a polyimide matrix. A further attraction of this substitution is the increase of the flexural toughness from 7.7 MPa mm to 10.7 MPa mm; the only disadvantage is the increase of the dielectric constant at 100 kHz from 7.1 to 11.1 [15].

8.5 Slug as the Filler A slug is a solid piece of filler. When a slug bonds two surfaces, it should stretch from one to the other. And when the bond is viewed edge on, the periphery of the slug composite is lined with the particulate form of the filler entrapped in a polymer. The slug is formed by melting the filler particles so they coalesce in situ during composite paste processing. As the slug is a solid metal (a solder), the electrical resistivity is low, e.g., 10 -5 f2 cm in the case of a Bi-Sn slug (83.9 vol.%) in polyimide siloxane [ 16-1.

8.6 Effect of the Polymer Viscosity Although the polymer matrix is electrically insulating (except in the case of a conducting polymer), the electrical properties of a polymer-matrix composite can depend on the polymer. Specifically, the dependence is on the viscosity of the polymer during composite fabrication. For a thermoplast, viscosity decreases with increasing temperature. Other polymers have other viscosity-temperature behaviors and the composite fabrication method also comes into play. For a composite fabricated via a slurry of the filler in a liquid polymer (either molten or dissolved in a solvent), the viscosity of the polymer at the processing temperature affects the uniformity and quantity of the filler. The greater the density difference between the filler and the polymer liquid, the greater the need for a high viscosity to avoid the filler sinking or floating. On the other hand, the greater the viscosity, the smaller the maximum possible filler volume fraction, as the addition of the filler further increases the viscosity. The viscosity of a polymer not only determines the maximum filler volume fraction, it also affects the electrical properties of the polymer-matrix composite. The critical volume fraction of the conducting filler was found to increase with increasing viscosity or melt viscosity of the polymer [17-19], though this effect only applies to the case of the filler in the random arrangement.

Conducting Polymer-Matrix Composites 165

Conversely, a high polymer viscosity helps when fabricating a composite by hot pressing a dry mixture of a discontinuous filler and a polymer powder. If the filler is in the form of particles, as long as they are smaller than the polymer particles, a high polymer viscosity helps to maintain their percolation arrangement before hot pressing [20]. If the filler is in the form of short fibers, a high viscosity polymer is unable to enter the fine spaces between them and adjacent fibers touch. Hence, whether the filler is particulate or fibrous, a high polymer viscosity during composite fabrication helps to enhance the electrical properties. Table 8.10 shows that resistivity increases and EMI shielding effectiveness decreases with increasing composite fabrication temperature for a PES-matrix nickel particle composite [20]. This is because the viscosity of the polymer decreases with increasing temperature. The penetration of the polymer into the fine spaces between fibers is enhanced by increasing the temperature or the pressure during hot pressing. The higher the processing temperature or pressure, the higher the electrical resistivity and the tensile strength of the composite. This means that a low electrical resistivity is accompanied by poor mechanical properties, a veritable dichotomy. A solution is to create an in situ network in which adjacent fibers are locally connected, so the polymer film does not interfere with electrical conduction. This way a high processing temperature or pressure produces an in situ network composite of low electrical resistivity and high tensile strength. As an example, consider the effects of processing temperature and pressure on a carbon filament filler (0.1 ~tm diameter, > 100 ~tm length)in PES, a thermoplast with a glass transition temperature of 220~ Hot pressing at 293~ and 6.9 MPa resulted in a resistivity of 30 ~ cm for a composite containing 5 vol.% bare carbon filaments. Hot pressing at 310~ and 28 MPa resulted in a resistivity of 106 ohm cm for a composite containing 5 vol.% nickel-coated carbon filaments (0.3 ~m in diameter with the coating). The use of 5 vol.% nickel-coated carbon filaments, 2 vol.% tin-lead filler particles, and hot pressing at 310~ and 28 MPa created an in situ network composite of resistivity 0.09 ohm cm. (The tin-lead particles melt to form the in situ network [7].) Thus, high temperatures and pressures are detrimental the electrical properties, unless an in situ network composite is formed. 8 . 7 z-Axis Conductors

Solder bump arrays are increasingly important for chip-to-substrate connections and for surface mount devices. In these applications, a z-axis conducting film can replace a whole array of solder joints, aving on processing costs and making the interconnection easily separable. Whether resilient or adhesive, the film is electrically conducting along its short (z) dimension and electrically insulating in all other directions. Resilient films are used for separable connectors. In the elastomeric (silicone-matrix) conductive separable interconnection material developed by AT&T Bell Laboratories [21], conducting columns made by magnetic alignment of conductor particles are distributed in an irregular manner throughout a polymer sheet with the columns oriented in the z-direction of the sheet.

rn r rn

rl Electrical resistivity and EM1 shielding effectiveness of PES/Ni particle composite (9.4 vol.% Ni) fabricated at different temperatures above T, (220°C).

Table 8.10

Fabricutior~ renzperuture ( =CI

Electrical resistioit.~ (n c m )

Thickness

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

Z

-u

Sl~ieldingeffectiveness ( d B ) at the given frequent-v ( G H z ) 1.0

5 A

1.9

2.0

(mmi

L

II

67

Conducting Polymer-Matrix Composites 167

Conducting columns, 400 #m thick, are separated by 180 #m. By applying and maintaining a constant pressure, the film conducts along the z-direction only. The pressure requirement and their large dimensions limit the applications of z-axis conductors; they are currently used as printed wiring board connectors, device testing connectors, and thermal interface materials. Two state-of-the-art z-axis conductors have been developed by 3 M Corporation [22,23]. Metal particles are totally embedded as a single layer in a polymer matrix. During use the polymer matrix melts, flows, and becomes much thinner. This allows the metal particles to be almost uncovered, causes the polymer matrix to essentially vanish, and means the film is not reusable. In the other type, clusters of metal-coated polymer particles are embedded in a polymer matrix such that each cluster extends across the whole thickness of the film. Probably made by magnetic alignment of nickel-coated polymer particles, each cluster serves as a conducting path in the z-axis; there is no need for the polymer film to recede in order to expose the ends of each conducting path. The layer configuration is attractive because it has a high conducting path density, since there is only one conducting particle per path, but it suffers because it is not reusable. And although the cluster configuration is reusable, there may be as many as 12 conducting particles per path, so it suffers from a low conducting path density. The advantages of both are combined in a z-axis film [24], having only one conducting particle per path, each particle extending across the whole thickness of the film. The polymer matrix has no need to recede, so the film is reusable. 3M's film technology [22,23] may be superior to AT&T's [21-1, working at interconnection pitches down to 100 #m. But, another z-axis conductor was developed by AIT Inc. [25-1, though details are scarce. The z-axis conductor of [24] can be used as an adhesive film or a resilient film. It uses metal-coated particles of thermoplastic (3M uses thermoset particles) and a thermoplastic matrix. Thermoplastic particles can be easily deformed under pressure, thereby resulting in easy formation of a good electrical contact. The fine metal-coated polymer particles are uniformly and randomly distributed in a single layer and adjacent particles do not touch each other in the x - y plane. This forms an electrically conducting path in the z-direction only. The particles protrude from both sides of the film. The inplane electrical resistivity exceeds 10 ~~ ohm cm; the z-axis resistivity is 2 ohm cm for the whole film, or 5 x 10 -2 ohm cm for a conducting path. The thickness of the film is determined by the size of the metal-coated polymer particles. It can be as thin as 50 pm and only a small amount of pressure (,~ 1 kPa) is necessary to obtain a good electrical contact. A schematic of this z-axis film is shown in Figure 8.2. Because the conducting particles are uniformly distributed in the x - y plane, the volume fraction of the conducting particles in the film is as high as 25%. Therefore, this z-axis conductive film can be used as a high density interconnection to replace traditional solder arrays (about 50 #m between adjacent conducting particles or 2 x 104 conducting paths per cm2). In addition, the film exhibits negligible stress relaxation and a low modulus of 1.67 GPa at room temperature. A z-axis conductor may also provide encapsulation of the active face of a

168

MATERIALSFOR ELECTRONIC PACKAGING

E

Conducting particle

0

Figure 8.2

A schematic of the z-axis film of [24].

chip, giving at the same time good z-axis thermal conductivity. Using a wire filler, z-axis conductors can be obtained with macroscopic distances between the conducting paths. The wire can be in the shape of the letter Z, so the two parallel sides are perpendicular to the z-axis and protrude from the surface of the composite in order to serve as contact pads. Conductor strips plated on polymer sheets, another form of a wire filler, are put together by lamination. Such z-axis conductors are usually made resilient by a silicone matrix.

8.8 Electrically Insulating but Thermally Conducting Composites Polymers are used in electronic packaging as encapsulations, interlayer dielectrics, and die-attach adhesives because of their high electrical resistivity and processing ease. However, they suffer from a low thermal conductivity and a high CTE. A high thermal conductivity is needed for the dissipation of heat from the electronic package; a low CTE close to those of silicon, copper, and other materials adjacent to the polymer in the electronic package is necessary in order to avoid thermal fatigue. Used with fillers, polymer-matrix composites are an effective means for alleviating these problems; the fillers provide high electrical resistivity, high thermal conductivity, and low CTE. Among the ceramic fillers are A1203, AIN, BN Si3N 4, and BeO; diamond and AIN have particularly attractive thermal conductivities.

Conducting Polymer-Matrix Composites 169

Monolithic ceramics can more closely meet the thermal requirements than neat polymers but their higher dielectric constant, poorer processability, and higher cost are major problems. Polymer-matrix composites containing thermally conductive ceramic fillers provide a good compromise. Many ceramic particles and fibers, such as alumina [26], mica [27], boron nitride [28], aluminum nitride [29,30], diamond [30], glass fibers [31], and other ceramic fibers [32], have been used in polymer matrices in order to improve the required thermal properties. Composites containing high concentrations of the filler are needed in order to obtain high electrical or thermal conductivity. The high filler content usually results in poor mechanical properties, such as a high modulus and a low ductility, which worsen the thermal fatigue problem. One solution involves interconnecting the originally discontinuous filler to form a three-dimensional network [13]. The in situ network allows the conductivity to be high at low filler volume fractions. Bridges are another solution. Instead of a true network, bridges are formed between adjacent conducting particles via whiskers or any filler with a large aspect ratio, but the two fillers are not directly bonded. Bridges are better suited to thermally conducting but electrically insulating composites, networks to electrically conducting composites. Networks are far more effective at improving the conductivity of the composite, and low melting point metals are available to form electrically conducting interconnections. An example of the bridging approach is the use of AIN particles and SiC whiskers as mixed fillers in polyimide [ 15]. Together A1N particles and SiC whiskers enhance the formation of more continuous thermally conductive paths, and the whiskers increase the toughness of the composite because they have a large aspect ratio. The disadvantage of SiC whiskers is they increase the dielectric constant. For a composite with 50 vol.% total filler, the highest thermal conductivity corresponds to a volume ratio, A1N particles:SiC whiskers, of 3:1, at which the thermal conductivity is 2.23 W m-1 K-1 (compared to 0.128 W m-x K-1 for the neat polyimide), the CTE is 12.8 x 10 - 6 ~ (compared to 81 x 10 - 6 ~ W m - 1 K - 1 for the neat polyimide), and the dielectric constant is 11.1 at 100 kHz (compared to 3.3 for the neat polyimide). Although diamond in its perfect form has an outstanding thermal conductivity compared to other electrical insulators, the use of diamond powder as the filler is not as effective as the use of AIN powder as the filler in increasing the thermal conductivity of the polymer-matrix composite [33].

8 . 9 Conclusion Conducting polymer-matrix composites use conducting fillers in the form of particles, flakes, fibers, or networks. This chapter summarized recent developments in design, fabrication, and properties for each of these categories. It introduced the concept of ex situ and in situ networks and showed how the filler and the polymer matrix affect the electrical properties of the composite. Guidelines were suggested for achieving a composite of low volume resistivity, low contact resistivity and high EMI shielding effectiveness. For composites that are electrically

170

MATERIALSFOR ELECTRONIC PACKAGING

insulating but thermally conducting, the choice of filler is relatively limited although bridges help to increase the thermal conductivity.

Acknowledgment

This work was supported by the Defense Advanced Research Projects Agency of the U.S. Department of Defense and by the Center for Electronic and Electro-Optic Materials of the State University of New York at Buffalo.

References

1. 2. 3. 4. 5. 6. 7.

S.K. Bhattachasya, Metal-Filled Polymers, Marcel Dekker, New York, 1986, p. 27. R.P. Kusy, J. Appl. Phys., 48(12), 5301 (1977). J. Gusland, Trans. Metall. Soc., AIME 236, 642 (1966). R.P. Kusy and D.T. Turner, Nature 229(2), 58 (1971). L. Li and D.D.L. Chung, Composites 22(3), 211-218 (1991). L. Li and D.D.L. Chung, Composites, 25(3), 215-224 (1994). X. Shui and D.D.L. Chung, in Proc. 38th Int. S A M P E Symp. Exhib., 1993, pp. 1869-1875. 8. M. Zhu and D.D.L. Chung, J. Electronic Packaging 113, 417-420 (1991). 9. M. Zhu and D.D.L. Chung, Composites 23(5), 355-364 (1992). 10. M.A. Lutz and R.L. Cole, in Proc 39th Electronic Components Conf., IEEE, 1989, pp. 83-87. 11. M. Zhu and D.D.L. Chung, Composites 22(3), 219-226 (1991). 12. Japan Kokai, JP 85-83817, May 1985. 13. L. Li, P. Yih, and D.D.L. Chung, J. Electron. Mater. 21(11), 1065-1071 (1992). 14. L. Li and D.D.L. Chung, Polym. Composites 14(5), 361-366 (1993). 15. L. Li and D.D.L. Chung, in Proc. 38th Int. S A M P E Symp. E.,chib., 1993, pp. 47-52; J. Electron. Mater., 23(6) 557-564 (1994). 16. L.T. Shi, R. Saraf, and W.S. Huang, Processing Adv. Mater. 3, 57-62 (1993). 17. M. Sumita, H. Abe, H. Kayaki, and K. Miyasaka, J. Macromol. Sci. Phys. B25(1/2), 171-184 (1986). 18. F. Carmona, Physica A 157, 461-469 (1989). 19. K. Miyasaka, K. Watanabe, E. Jojima, H. Aida, M. Sumita, and K. Ishikawa, J. Mater. Sci. 17, 1610-1616 (1982). 20. L. Li and D.D.L. Chung, Polym. Composites,14(6), 467-472 (1993). 21. J.A. Fulton, D.R. Horton, R.C. Moore, and W.R. Lambert, in Proc. 39th Electronic Components Conf., IEEE, 1989, pp. 71-77. 22. P.B. Hogerton, J.B. Hall, J.M. Pujol, and R.S. Reylek, Mater. Res. Soc. Symp. Proc., 154, 415-424 (1989). 23. S.F. Tead, DARPA Physical Electronic Packaging 1992 Program Review, DARPA, Arlington VA, 1992. 24. L. Li and D.D.L. Chung, J. Electronic Packaging, in press. 25. K. Chung, G. Dreier, P. Fitzgerald, A. Boyle, M. Lin, and J. Sager, in Proc. 41st Electronic Components Conf., 1991, p. 345. 26. T. Ouellette and M. de Sorgo, in Proc. Power Electronics Desiyn Col!f., 1985, p. 134. 27. R. West, Electronics, 31(1), 28 (1985). 28. P. Bujard, in Proc. lnterSociety Conf. on Thermal Phenomena in the Fabrication and Operation of Electronic Components, 1988, p. 41.

Conducting Polymer-Matrix Composites 171 29. P. Bujard and J.P. Ansermet, in Proc. 5th IEEE S E M I - T H E R M Symp., 1989, p. 126. 30. L. Li and D.D.L. Chung, in Proc 4th Int. S A M P E Electronic Materials and Processes Conf., 1990, p. 236. 31. S.D. Mclvor, M.T. Danby, G.H. Wostenholm, B. Yates, L. Banfield, R. King, and A. Webb, J. Mater. Sci. 25, 3127 (1990). 32. J.D. Bolt and R.H. French, Adv. Mater. Proc., 134(1), 32 (1988). 33. L. Li and D.D.L. Chung, Composites, in press.

This Page Intentionally Left Blank

~

IV

M e t a l Films

This Page Intentionally Left Blank

CHAPTER9

Thick Film Technology Ren~ E. Cot~

9.1 Introduction For more than 40 years, thick film materials have been used to manufacture a variety of resistor networks, hybrid integrated circuits, and discrete components (resistors, capacitors, and inductors). Thick film hybrid circuitry used surface mount technology and was used to produce multichip modules before these terms became part of the electronic packaging vocabulary. Thick film hybrids and resistor networks have been used in all segments of the electronics industry. Although many factors have contributed to the rapid and sustained growth of thick film technology, advances in thick film materials and processing were essential. This chapter reviews some of the important advances for microcircuit applications with sections covering resistors, conductors, dielectrics, and the organic vehicles that make the compositions printable. Much of the materials technology is proprietary but details are provided where possible. The chapter is intended as an introduction furnished with appropriate historical perspectives.

9 . 2 O v e r v i e w of Materials and Processes Thick film compositions are dispersions of inorganic oxide, ceramic, glass, or metal powders in organic fluids. The compositions can also be described as having three parts: a functional phase, a binder, and a vehicle system. The functional phase can be metal or semiconducting oxide powders for resistor compositions; metal powders for conductor compositions; or glass and/or ceramic powders for dielectric compositions. The binder serves to adhere the fired film to a substrate. The vehicle is made up of resins and solvents. The resins serve as temporary binders to hold the unfired film together, give it green strength and make it adhere to the substrate. The solvents reduce viscosity and make the compositions screen printable. Most thick film compositions exhibit pseudoplastic or thixotropic behavior. Their viscosity is an inverse function of shear rate. Thick film compositions are used to produce conductors, resistors and other passive circuit elements on appropriate substrates such as 85-99% aluminum oxide (alumina). In special

175

176

MATERIALSFOR ELECTRONIC PACKAGING

applications, aluminum nitride, berylium oxide, or barium titanate substrates have also been used. The substrates are usually 0.5-1.0 mm thick with length and width dimensions of 1-10 cm. Circuit patterns are produced by screen printing with automatic and semiautomatic machines. In principle, the process is similar to the silk screening process used to print shirts or posters. The screen printable compositions, pastes, or inks are forced through a screen with a rubber or plastic squeegee. A portion of the screen, generally stainless steel or nylon filament, is dammed or masked so the screen openings form the desired printed pattern. The thick film composition is forced through these openings and deposited on the underlying substrate to reproduce the pattern. The printing process is fast; modern equipment with in-line feeding and transferring equipment can pattern 2000 substrates per hour. Throughput can be increased significantly when multiple circuits are printed on a single substrate. The printed patterns are dried at temperatures below 200~ then fired through a conveyor belt furnace set to provide reproducible time-temperature profiles. Total firing time is of the order of 20-60 min at peak firing temperatures between 600~ and 1 000~ Thick film processing is illustrated schematically in Figure 9.1. Most thick film compositions have a wide firing latitude and, within relatively broad limits, the precise shape of the profile is not critical. However, once a firing schedule has been set, it is important to maintain it as invariant as possible to insure the reproducibility of the performance characteristics of the fired films. Conductors and resistors are sequentially printed and fired to produce resistor networks. The attachment of leads completes these passive circuits. When used as stand-alone devices, the resistor networks are usually conformally coated or molded. The addition and interconnection of active devices to a resistor network produces hybrid integrated networks. The addition of printed capacitors, monolithic capacitors, and other discrete components produces hybrid integrated circuits or multichip modules. The thick film technique can also be used to produce complex multilayer

[~P~-~IPI1

Thick Film Processing States Wet Print

Driedt l \P\r\i\n\ \ _ \ \ \ \ . \ ~ \ \ \ \ . \ \ \ l

0 conductive particle II glass particle Figure 9 . 1

Fired Film t\\\\\\\\\\\\\\\\\\\\\\\\\.~\?,n

Thick film processing states. (Courtesy DuPont Electronics.)

Thick Film Technology 1 7 7

circuits with several layers of printed conductor lines separated by layers of insulating dielectric. The dielectric is patterned with through-holes, called vias, for connection of conductors lines on different levels. Tape dielectrics are available to make this process less process dependent. The tape material is usually formulations of thick film compositions to which a plasticizer has been added for green strength. A thick film circuit production line requires low investment and is very versatile. It is ideal for long production runs of similar or like parts, and because the turnaround time is short--the changing of the screens is simple and rapid--it is effective for prototypes or short run production of many different part types. Thick film microcircuits provide an enormous range of functionality in relatively small sizes, particularly compared to printed circuit boards. Also, substrate requirements are less stringent than those for thin film circuits, and the overall investment in equipment is lower. In many applications, thick film technology is a versatile, low cost, size efficient method for producing all types of electronic interconnections. Figure 9.2 is a simplified flowchart of the formulation of thick film microcircuit compositions. Metals, metal oxides, solvents, resins, and other raw materials are converted to intermediates, such as metal powders, glass powders, and vehicles by chemical and mechanical processes. The intermediates are combined or formulated to produce thick film compositions. This process is basically a mechanical process. The key to producing compositions reproducibly is the control of the intermediates, and back-integration to intermediates from readily available raw materials is very important. Conversion to reproducible compositions is much more straightforward with reproducible intermediates of controlled high quality. Table 9.1 is a review of the major components of thick film compositions. Each usually contains three basic parts: a functional phase, a permanent binder phase, and a vehicle system. Functional phases for conductors are usually precious metals or mixtures of precious metals and alloys. However, nitrogen-fireable compositions use copper conductors. Air-fireable, nickel-based material systems are also available. The functional phase of early thick film resistors was Pd/PdO/Ag, but today most resistor systems contain highly conductive oxides such a s R u O 2 or Bi2Ru207. Typical dielectric functional phases are ferroelectric crystalline oxides such as barium titanate, glasses, glass ceramics, and mixtures of these materials.

Raw materials Solvents Resins Metal Metal oxide

Figure 0 . 2

Chemical process

._ I Intermediates Glass powders Metal powders Vehicles Modifiers

Mechanical process ,._I Thickfilm "- I composition

Composition quality

~ Every batch assigned a lot number ~ Retainer sample ~ Quality tests physical & functional

Thick film composition manufacture flowchart. (Courtesy DuPont Electronics.)

178

MATERIALS FOR ELECTRONIC PACKAGING

9.1 Typical major components of thick film compositions.

Table

Functional Phase Conductor: Au, Pt/Au; Ag, Pd/Ag; Cu, Ni Resistor: RuO2, Bi2Ru2OT, LaB6 Dielectric: BaTiO 3, Glass, Glass/ceramic, AI20 3 Binder Glass: borosilicates, aluminosilicates Oxides: CuO, CdO Vehicle Volatile phase: terpineol, mineral spirits Nonvolatiles: ethyl cellulose, acrylates

Historically, permanent binders have been glasses such as aluminosilicates and borosilicates. There are many types of glasses that are effective in binding functional phases to alumina or other substrates. In addition, mixtures of crystalline oxides have been found to work well and, in some systems, oxides are more effective than glasses, particularly at low vol.%, producing very dense fired films. Some compositions are formulated with mixtures of oxides and glasses to produce mixed-bonded compositions. Vehicle systems typically contains two components: a volatile solvent and a nonvolatile resin. The function of the vehicle is to be the carrier for the particles of functional phase and binder and allow them to be screen printed. Dispersing and stabilizing agents may also be added to affect viscosity stability, printability and shelf life. During the firing cycle the volatile portion of the vehicle evaporates, then decomposition and combustion of the nonvolatile phase take place at temperatures between 200~ and 400~ With increasing temperature, many important reactions begin to occur. The permanent binder begins to flow and/or react with the substrate. It may react with the functional phase and will certainly influence the sintering kinetics of the functional phase. An understanding of the essential elements of these reactions is important in the development of materials with complex combinations of performance characteristics needed for high precision, reliable circuits and networks. 9 . 3 Resistors Thick film compositions contain many components, and their development requires an understanding of the interaction of these components during the firing process. Perhaps the most complex are resistor compositions. Table 9.2 shows a partial list of material variables that impact resistivity, temperature coefficient of resistance (TCR), and resistor stability. Early resistor compositions were formulated with mixtures of palladium (Pd)

Thick Film Technology 179

Toble 9.2

Variables affecting resistivity and temperature coefficient of resistance. Functional phase 9 partial size 9 resistivity 9 thermal expansion 9 sinterability 9 purity 9 thermal stability 9 partial size distribution 9 chemical reactivity 9 same as above 9 wetting properties 9 chemical reactivity 9 surface texture

Binder 9 softening point 9 viscosity Substrate 9 thermal expansion 9 purity

and silver (Ag). When Pd powder is heated in air it oxidizes to palladium oxide (PdO). The relative amount of oxide increases until, at temperatures near 800~ a rapid 10ss of oxygen occurs and the oxide reverts to metallic Pd. The kinetics of this process are influenced by the amount of Ag present. Fired films contain mixtures of P d O and PdAg. Resistivity is a function of the relative amounts of the conductive alloy and the semiconducting oxide present in the fired film. Since this is a chemically dynamic system, process control is critical. The ratio of phases, and hence the part-to-part resistivity, will vary widely unless a given time-temperature profile is maintained within very narrow limits. Resistivity change, evenin slightly reducing atmospheres, limited resistivity range, and high TCRs are other shortcomings. Resistors with functional phases based on ruthenium oxides were developed to overcome these problems. The broadest family of conductive phases based on ruthenium compounds is the pyrochlore crystal family. These have a cubic structure with each ruthenium atom surrounded by six oxygen atoms, forming an octahedron (Figure 9.3(a)). Each oxygen atom is shared with one other octahedron to form a three-dimensional

I

(a) Pyrochlore

A2B206.7 Bi2Ru207

CaNa (Nb. Ti) 2 0 s (F. OH)

I

(b) Rutile

A02

RuO 2

TiO 2

Figure 9 . 3 Comparison of ruthenium-based (a) pyrochlore and (b) rutile structures. (Courtesy DuPont Electronics.)

180

MATERIALS FOR ELECTRONIC PACKAGING

network of RLI2O 6 stoichiometry. Holes within this framework are occupied by large polarizable cations and additional anions to form a second sublattice of A20'x (0 ~< x ~< 1) stoichiometry. The resulting pyrochlore structure of the general formula AzBzO6+ x permits a great deal of chemical latitude. For example, the mineral pyrochlore contains Nb, Ta, and Ti in the B site; Ca and Na in the A site; and a mixture of O, OH, F, and vacancies sufficient to maintain electrical neutrality in the O' sublattice. Pyrochlores which behave like metals, semiconductors, or insulators can be produced through controlled and reproducible substitution in the available crystallographic sites. The ability to alter the functional phase via chemical substitution provides a broad latitude for the adjustment of resistivity, TCR, and other electrical and physical resistor characteristics. Many current pyrochlore-based thick film resistors contain functional phases of bismuth ruthenate (BizRU2OT) and its chemical variants. The chemistry of the binder strongly influences resistor composite properties and current systems are the result of detailed studies of glasses. Other thick film resistors are based on ruthenium dioxide (RuO2). Its rutile crystal structure is similar to the pyrochlore structure in that each ruthenium atom is surrounded by six equidistant oxygen atoms, forming an octahedron (Fig. 9.3(b)). However, while in the pyrochlore, each network oxygen atom is shared by two octahedra, in the rutile structure, each oxygen is shared by three octahedra, and the octahedra share edges. The result is a very complex three-dimensional network. Substitutional chemistry of ruthenium is very limited, and important approaches to resistor property adjustment include models based on the nature of barriers between particles of functional phase, the effect of secondary phases, and the oxides' solubility and recrystallization in glass binders. A parallel investigation of composites containing rutile and pyrochlore functional phases indicated no basis for functional phase selection because of the intrinsic stability of the oxides. Each system provides different sets of trade-offs. For example, pyrochlores have lower TCRs, better power handling capability and better stability to reduction. However, RuO 2 has a lower resistivity and is available in much finer particle size, which may confer better laser trim stability. Also, it is important to recognize that resistor systems based on the same functional phase do not necessarily exhibit equivalent performance. The nature of the other solids and their interaction with the functional phase are very important to fired film performance. For example, both pyrochlores and RuO 2 will react with certain glass compositions to form other pyrochlore phases during firing. The two most important functions of a resistor are to provide a resistance value within the design tolerance and to maintain that value throughout the projected life of the circuit. The following two sections focus on these key points. 9 . 3 . 1 Resistance Value

The ends of thick film resistors are usually overprinted onto the ends of prefired conductors, with overlaps of about 250/~m. Printed and fired films between the overlaps are about 10-25/~m thick. Films as small as 1-2 mm long and wide

Thick Film Technology I $ I

are common in high volume production of high reliability parts, consistent with the trend toward small, high density circuits. Thick film resistor compositions are usually produced in decade resistance values (1, 10, 100, 1 000, 10000, etc.); and materials are available that provide a very wide range of sheet resistance values--from 1.5 f~/sq, to 10 Mf2/sq., meaning that resistors of square geometry, such as 1 mm long by 1 mm wide, can have a resistance from about 1.5 to 10 7 ohms. The major determinant of the resistivity is the amount of conductive phase versus the amount of insulating glass in a composition. The technology is versatile in that specific resistance values can be obtained easily through a variety of techniques: by a change in resistor geometry, by blending or mixing compositions, and by physically cutting or trimming away part of the resistor~usually by a laser cut--to increase the resistance value. A change in the length-to-width aspect ratio of a resistor film will provide resistance values as low as 1.5 f2, as high as 10 MfL or any intermediate resistance value between these upper and lower limits. For example, a 10 kf~/sq, composition used to produce a 5 mm long by 1 mm wide resistor will give a resistance value of 50 kf~. Composition blending is a technique widely used to obtain resistance values between two of the decade values. For example, 100 f~/sq, and 1 kf~/sq, compositions can be mixed in all proportions to produce compositions with an infinite number of intermediate values of sheet resistance. The mixing procedure is simple but requires care, cleanliness, and the proper equipment. Usually, blending has a minimal effect on TCR, described shortly. The third method for altering resistance is trimming or cutting away part of the fired resistor film thereby increasing its resistance by varying its length to width ratio. Laser trimming is the most common technique for high volume production of precision resistors. Properly programmed, laser trimmers can routinely trim high performance fired resistor films to a precision better than 0.2% of the target value. The trimming process is fast and a circuit containing as many as 25 resistors can be trimmed and measured in approximately 2.5 s. Adding parts-handling equipment, about 1 000 circuits can be trimmed and measured (tested) in 1 h. Detailed studies of the effect on resistor stability of machine parameters such as cutting speed, power and pulse frequency have been performed. Figure 9.4 represents resistor cross sections for bad and good cuts. Deep penetration into the substrate is evident in Figure 9.4(a). This actually causes microcrack formation at the resistor-substrate interface, and crack propagation into the resistor causes significant resistance change (drift) with time. Conversely, cuts that do not completely penetrate through the resistor and into the substrate, Figure 9.4(b), will cause resistance drift also. Figure 9.4(c) illustrates the degree of substrate penetration needed to produce a clean resistor cut (kerf), to minimize drift, and to yield a highly reliable resistor. TCR is illustrated in Figure 9.5. Generally, TCR is defined as a fractional change in resistance over a given temperature range, expressed in parts per million per degree Celsius (ppm/~ The reference temperature is 25~ and two TCR

182

MATERIALS FOR ELECTRONIC PACKAGING

V (a)

Resistor

J

Substrate (b)

(c) Figure 9.4 SEMs of cross sections of laser trimmed resistors. (Courtesy DuPont Electronics.)

R2.~ .

l

-55

TCR = AR

R25AT

!

25 Temperature (* C) ~, 106 = (RT--- R2S) R2~ ( T T - - T25 )

,

1

125

--

~ 106

Figure 9.5 Resistance versus temperature behavior of thick film resistors. (Courtesy DuPont Electronics.)

values are usually specified: hot TCR values for 25-125~ and cold TCR values for - 5 5 ~ to 25~ The values determined between these temperature ranges are expressed as averages. Over these ranges, the highest quality thick film resistors exhibit values of ___50-100 ppm/~ For reference, a resistor with a TCR of 100 ppm/~ will exhibit a change in value of 1% over a temperature excursion of 100~

Thick Film Technology

| 83

9. 3. 2 Stability and Reliability Both accelerated tests and long-term performance data have shown that end-of-life tolerances of 1-2% are easy to achieve and that tolerances of 0.5% or less are within expectation with proper circuit design, resistor design, and processing. Figure 9.6 is an illustration of the distribution of resistor values through the main stages of processing. The horizontal axis is an arbitrary resistance scale with values increasing from left to right. The vertical axis represents the number of resistors tested. The bell-shaped curve shows the distribution of resistance values just after firing of a large number of resistors of the same geometry and the same nominal sheet resistance. Typically, the spread around the mean value is about 10-15%, primarily due to the variation of printing and firing process conditions. Resistors should be designed to insure that all resistance values in the as-fired distribution are lower than the trimmed target values. The distribution of resistance values, after trimming, is shown m the center of the figure. To reach the trimmed target values, fired films with low resistance values--at the left of the as-fired distribution~require more extensive trimming than the resistors with mean or higher values. Resistors made using high performance thick film materials can be trimmed 1.5-2 times their as-fired value with no adverse effect on stability; and the mean trimmed value can have a precision of about 0.1% with a distribution around the mean of under 0.5%. The increase in the mean resistance value from the trimmed condition to the final or packaged target value reflects changes that occur during subsequent processing to complete the circuit, such as active device interconnection by soldering or wire bonding, attachment of leads, and encapsulation with organic materials. Current thick film compositions and machine technology permit the trimmed target value to be programmed to well within 0.5% of the final packaged target value. Finally, the tailin9 of the packaged distribution to higher resistance reflects changes that occur during testing and normal circuit operation. The testing of resistors or complete circuits is usually carried out under extreme or accelerated Target

,+, iii III iii iii Ill

lit i ! i I

,! I

As Fired

I

Trimmed Packaged

Figure 9.6 Processing resistors to target value, distribution of resistance values. (Courtesy DuPont Electronics.)

184

MATERIALS FOR ELECTRONIC PACKAGING

conditions of temperature, humidity, and electrical load, often in conformance with appropriate military specifications. Although the stability of thick film resistors is dependent on many factors, including substrate quality and trimming parameters, the information presented below is considered typical for bismuth ruthenate resistors processed within a band of normal industry conditions. However, it is important to recognize that regardless of the intrinsic stability of a thick film resistor, there are always process limits beyond which any material will exhibit instability. In particular, laser machine parameters cannot be selected casually. Published guidelines should be followed. Posttrim circuit fabrication may include the bonding of active devices or die to the substrate and the interconnection of the die to thick film conductors with aluminum and gold wire, or beam leads via ultrasonic, thermocompression, or thermosonic techniques. Alternatively, discrete packaged devices may be soldered to the conductors. Other discrete components, such as multilayer capacitors, may be attached similarly. Leads or connector pins are attached to conductor pads at the substrate edges, usually by one of several methods, including selective deposition and reflow of solder compositions. Resistance changes resulting from soldering procedures typically will be 0.1-0.2% or less. Encapsulation of the entire circuit using an organic coating is often a final circuit packaging step which has little or no effect on resistance values. Common stability criteria measure resistance change after long-term storage under accelerated conditions of 150~ and/or 40~ and 90% relative humidity. Depending on resistor size, type of conductor termination, type and extent of laser cut, modern, high performance thick film resistors will exhibit maximum resistance changes of less than 0.75% and often less than 0.2%. Many circuit manufacturers elect to encapsulate resistors with a printable glass before trimming; and glass encapsulated resistors will generally exhibit lower resistance changes than bare films. In an effort to project long-term reliability, bismuth ruthenate resistors were subjected to electrical load cycles for 20000 h in tests designed to simulate typical process and use conditions. The small, 1 mm x 1 mm, resistor size and single plunge laser cuts represent relatively severe conditions. Tests were carried out with 100 l'~/sq, and 100 kfl/sq, resistor compositions. Resistor surface temperature varied from 75~ to 125~ There were no catastrophic failures after more than 3.5 million component testing hours and at power loads of 160 mW/mm 2. The average resistance change was usually less than 0.2%. The maximum change exhibited by any single resistor was less than 0.5%. Over a range of 40-320 mW/mm 2, only the behavior of resistors made with the 100 k~a/sq, composition was dependent on power loading. Data from further tests of resistors made with this composition to power levels of 800 mW/mm 2 show its behavior to be rational without catastrophic failure, even when overpowered excessively. The rate of resistance change was 0.6% per 10 years, so a total change of 3% after 10 years can be presumed. Since most current hybrid circuits and resistor networks operate at power loadings well below 160 mW/mm 2 (100 W/in. z) of resistor area, the data indicate that a high degree of long-term reliability is to be expected using thick film resistors.

Thick Film Technology 185

9.3. 3 Special Applications

There are a number of circuits, such as television focus controls and telecommunications surge arrestors, that require sheet resistance values of 1-10 Mf~/sq. and performance under very high, pulsed voltage stress. Compositions for these applications are based on technology that minimizes points of usually high voltage gradient within the resistor composite. The optimization of particle size and morphology and the inclusion of intermediates with semiconductive phases have been important approaches. Typically, resistance change under constant load of 400 V/mm (10000 V/in.) is negligible, and less than 0.1% under repeated 2 ms voltage pulsing at 3 kV/mm (75 kV/in.). Thick film resistors are also widely used to produce trimmers and precision potentiometers, as discrete components, and as part of certain thick film circuits. In contrast to resistor elements of wire-wound potentiometer, thick film resistors provide advantages in stepless resistance resolution, a wide range of resistance values and adaptability to miniaturization. Advances in materials technology have led to TCRs of _+50 ppm/~ and significant improvements in surface smoothness and uniformity. This has been a consequence of new glass chemistry and control of particle morphology to provide an optimum trade-off in surface and bulk characteristics. For example, even very high resistance, fired films, which usually contain a high vol.% of glass, have a sufficient surface density of functional phase that a single 125 Ftm wide wiper finger will make positive contact with conductive areas in traversing the potentiometer track. Thus, with simple fivefinger metallic wipers, contact resistance variations (CRVs) of + 1% are achieved over a range of 1.5 ~/sq. to 1 M~/sq.

9.4 Conductors In thick film hybrid circuits, conductors function primarily as the interconnection between discrete active and passive devices and the printed elements, leads, or pins of the package. Key performance requirements are low resistance, compatibility with other printed circuit elements, ease of producing solder or wire interconnection bonds with good electrical and mechanical integrity, and good adhesion to the substrate when subjected to peel and pull forces. Both the functional phase and the binder contribute to fired film performance and conditions of substrate surface porosity and chemistry can have important effects on initial and aged adhesion. 9.4. I Solderable Conductors

Most air-fireable thick film microcircuit conductors are based on gold (Au), silver (Ag), and binary or ternary alloys of gold, silver, platinum (Pt), and palladium (Pd). Sheet resistance values range from about 3 m~/sq, for Au and Ag (about two to four times their bulk resistivities) to 150 m~/sq, for some of the Pt-Au formulations. Although Au may be soldered with special lead-indium (Pb-In)

186

MATERIALS FOR ELECTRONIC PACKAGING

solders, it is usually thought of as nonsolderable because of its rapid dissolution into common tin-lead (Sn-Pb) solders. Conductors containing mixtures of Ag and glass, developed during the first stages of the technology, were used as electrodes for mica and barium titanate ceramic capacitors. As the technology moved toward fabrication of microcircuits in the 1950s, it was evident these conductors frequently did not provide sufficient resistance to leaching (dissolution) by Sn-Pb solders. The development of conductors containing mixtures of precious metals resulted. Pt-Au mixtures maximize resistance to solder leaching. The solid solution of these metals, formed on firing, provides a good trade-off between the solder resistance of platinum and the solder acceptance of gold. Novel glass binders contribute to performance by assuring adhesion over a broader range of firing temperatures and improving resistance to corrosive solder fluxes. The first Pd-Au and high palladium content Pd-Ag conductors were routes to lower costs. Both were very resistant to leaching by a variety of solder alloys. However, the adhesion of the soldered metallizations was found to decrease substantially during storage or agin9 at temperatures of 125~ and higher. Extensive penetration of tin from the solder into Pd-Au composites occurs with the formation of intermetallic PdAuSn3. Volume expansion within the composite presumably disrupts the glass-metal network, and bond failure occurs between the upper, metal-rich layer of the composite and the lower, glass-rich layer adjacent to the substrate. The relative amounts of glass and precious metal, the distribution of the glass within the composite (influenced by the firing schedule) and the nature of the original palladium alloy were found to affect intermetallic formation and failure rate. Subsequently, particularly working with Pd-Ag systems, it was learned that the chemistry of the binder dramatically influences aged adhesion. The Ag-Pd weight ratio of many early conductors was low, on the order of 2:1. Later, Ag-Pd conductors with ratios of 6:1 and higher performed well, and continue to be used routinely. This is primarily due to advances in binder (glass-oxide) chemistry. Providing that silver containing solder is used (e.g. 62% tin-36% lead-2% silver), they are very resistant to leaching and exhibit good long-term aged adhesion. In the late 1970s, the price of palladium metal rose abruptly from approximately $1/g to more than $3/g, close to the price of platinum. This spurred the investigation of cost-performance trade-offs of platinum and palladium in silverbearing conductors and resulted in the development of a number of Pt-Ag and Pt-Pd-Ag conductor compositions. In some systems, depending on the binder chemistry, partial or complete replacement of palladium with much smaller amounts of platinum yielded equivalent performance with silver-containing solder. Today, a large number of metallurgies are available with a broad spectrum of costperformance characteristics. The potential utility of any of these has to be viewed in the context of the specific requirements of each circuit. Concerns regarding the potential for migration of silver between adjacent electrically biased conductors in humid ambient conditions have diminished with

Thick Film Technology 1 8 7

the realization that this phenomenon can be decreased, and even eliminated, by proper circuit layout. In some instances, selective encapsulation with special glasses and/or location of the conductor over a preprinted and fired dielectric layer is required. Experiments have shown the migration of lead and tin can be more rapid than the migration of silver. In one study, the performance of soldered Pt-Au conductors was compared to that of unsoldered Pd-Ag conductors. Parallel conductor lines were printed and fired on alumina separated by 250/~m. A drop of water was placed across the adjacent soldered Pt-Au conductors, across the Pd-Ag, and both were biased with 6 V. The adjacent soldered lines shorted first and the metal dendrites which spanned the lines were analyzed. The dendrites were found to be mainly lead. Dendrites of tin were present but did not completely span the lines before shorting of the lead dendrites. Obviously, a circuit is not expected to perform under water, but this accelerated test shows that even solder can be a problem under certain unusual conditions. Soldered conductors of all types have been used for many years with, at worst, a few isolated failures reported. Proper circuit design is important in successfully avoiding failure, and silver-containing conductors have proliferated into a large number of high reliability circuit applications. So far the discussion has focussed on conductor metallurgy, but some of the most important advances in performance have come from developments in binder chemistry. Many of the first thick film conductors contained relatively simple glasses. The bonding of these glasses to alumina is believed to be largely the result of mechanical interlocking with substrate surface grains augmented, to some extent, by the interdiffusion of ions. Significant diffusion of aluminum into binder glass has been reported, but its effect on adhesion is not clear. During the early stages of conductor development, the importance of bismuth oxide was recognized. When heated to a liquid above 800~ it forms a low contact angle with alumina and readily combines with many glasses, altering flow and sintering behavior. This oxide, or flux, has been found to improve the adhesion and solder acceptance of many conductor systems. In the early 1970s, it was found that certain transition metal oxides improved adhesion of certain glass-bonded conductors, mainly a consequence of the reaction with alumina to form crystalline spinels. During the same period, materials containing binders of copper and cadmium oxide were developed. The formation of copper aluminate was the driving force for binder-substrate interaction. The fired films were referred to as chemically bonded, as well as oxide bonded; they were very dense and had high adhesion, but they required firing temperatures generally above 950~ a major drawback in many cases. Although their use was limited, the early crystalline oxide binder technology represented a significant advance in the bonding of thick film metallizations to substrates. Continued development led to more complex oxide binders and new mixed oxide-glass systems that were effective at firing temperatures below 900~ A glass-bonded composite usually contains a metal-rich upper layer, a glassrich lower layer, and the volume concentration of glass is typically 20-30%.

188

MATERIALS FOR ELECTRONIC PACKAGING

Fingers of glass extend to the metal surface throughout the structure. However, the detailed structure of any glass-metal system is a function of sintering, flow, and component interaction during any given firing schedule. For example, overfiring of some systems can produce very large surface grains of metal with attendant large areas of glass on the surface of the composite. Oxide-bonded conductors usually contain a low volume concentration of binder, often under 5%, conducive to the formation of dense metal surfaces. The vol.% binder in mixed-bonded conductors covers a broad range and depends on the specific chemistry of the system. A representation of silver conductor fired film surfaces, shown in Figure 9.7, illustrates the extremes of surface structure. Many large areas of glass appear on the surface of the glass-bonded film. The oxide-bonded composite, containing a very low volume concentration of binder, has a very dense silver metal surface, Oxide Bonded

(Top View)

(a) ......

---~:i::::::.:i A

.......

.:...:.:.:~::.:i:.:i..:.:i.i:i:i..:.::::::..::....,

i,

- -

,

1

Substrate (Side View) Glass Bonded

(b)

lass

Substrate (Side View)

Figure 9 . 7

SEMs of fired film surfaces of silver conductors. (Courtesy DuPont Electronics.)

Thick Film Technology 189

relatively free of voids and binder. The presence of surface glass is not in itself bad, providing the areas are not so large nor so high in concentration that they impede solder acceptance or wire bonding. No adverse consequences have been associated with the surface structure of many high performance, glass-bonded Pd-Ag conductors. These have been successfully used in a variety of applications for many years. The surface structure of many of these conductor systems consists of a relatively low concentration of very small areas of glass. However, a very dense metal surface is important to the performance of very high silver content conductors in reducing the rate of solder leaching and the subsequent loss of thermal aged adhesion. The chemistry of the binder and the chemistry of the solder alloy are equally important. Table 9.3 is an abbreviated comparative list of some key performance characteristics of modern solderable conductors. The list of materials is in descending order and reflects the increasing concentration of silver relative to the other metals. The point is that, in some respects, very high silver content materials perform as well as those containing higher contents of the more precious metals. A great many circuits containing silver instead of more precious metals have been and are still being designed, produced, and used successfully. The key is the detailed assessment of performance characteristics against specific property and process needs for each circuit type. The solder interconnection of lead frames, discrete passive elements such as capacitors, and packaged and passivated active devices is common. However, solderable conductors and bare active devices are interconnected by one of several wire bonding techniques: thermocompression bonding of gold wire, thermosonic bonding of gold wire, and ultrasonic bonding of aluminum wire. Although it is beyond the scope of this chapter to discuss each one in detail, thermocompression--the combined use of heat and pressure to create a metallurgical bond between the gold wire and the thick film conductor--is used routinely to produce strong, reliable bonds. Attachment of aluminum wire to solderable conductors is used, but less frequently. Thermosonic attachment of gold wire is presently the preferred method, simultaneously using thermal and ultrasonic energy.

Table 9.3

Performance comparison of solderable conductors. Solder leach adhesion resistance

Metalluryy

Wt.% A9 (fired film)

Sheet resistivity (mf2/sq. per 25 I ~ m )

Pd-Ag Pd-Pt-Ag Pd-Ag Pd-Ag Pt-Ag

64 67 71 86 99

30 25 15 8 2

150~

18 24 18 29 27

No. of cycles

10 11 10 9 8

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MATERIALS FOR ELECTRONIC PACKAGING

Finally, a few words about solderable conductors as terminations for thick film resistors. Thick film resistors are usually overprinted onto prefired conductors, with an overlap of about 250 #m. The chemical and mechanical structures of the overlap region affect the behavior of the resistor, expecially when its size is small. During resistor firing, there are interactions with conductors that work to either increase or decrease resistance within and around the overlap. This often causes a nonlinearity of resistance as a function of resistor length, particularly at lengths near 1 mm. For any given resistor-conductor system, resistance versus length behavior is reproducible and is usually defined by published design curves. Although the reaction during high temperature firing does not imply system instability or continued reaction during circuit function, some resistor-conductor combinations are incompatible. Incompatibility is usually manifested by bubbles at the terminations and, less frequently, by transverse cracks in the resistor at the ends of the underlying conductor. A second cause of resistance nonlinearity is coefficient of thermal expansion mismatch at the conductor-resistor-substrate junctions and the topology of the resistor at the region where it begins to ride up onto the conductor. The resistor tends to be thicker here than along the rest of its length. Provided the printing process is controlled, so that nonoverlapping resistor and conductor thicknesses are held reasonably constant, the effect on resistance is sufficiently reproducible. However, excessively thick resistor areas at the ends of too thick conductors can cause resistors to be unstable, particularly very small resistors. Instability is observed as a significant increase in the resistance value with time after laser trimming. This phenomenon is a consequence of strain relief through the propagation of microcracks. In this regard it is important that conductor thickness be controlled so that printing errors are in the direction of thinner prints. 9 . 4 . 2 Gold Conductors

Traditionally, the use of thick film gold conductors has been reserved for very high reliability applications such as military and telecommunications circuits, because of their resistance to corrosion and to reaction in many ambient conditions. However, gold is not completely benign, and certain gold-containing metallurgical systems have resulted in problems. Also, as with the solderable conductors, the binder system is an important contributor to most aspects of performance, and the development of binders for gold and the other functional phase metals have occurred more or less in parallel. For example, early glass-bonded gold conductors usually had low optical density with large areas of glass on the surface. At high firing temperatures, uncontrolled sintering produced an excessive enlargement of the gold grains and the glass areas. Many of the modern oxide and mixed-oxide gold systems have overcome the deficiencies of low optical density and insufficient process latitude, and now exhibit much better adhesion than the early gold conductor compositions. Historically, gold conductors and bare active devices have been interconnected by chip and wire techniques: the thermocompression bonding of gold

Thick Film Technology 191

wire and the ultrasonic bonding of aluminum wire. Automated thermosonic bonding for gold wire has been developed and is now common in the industry. Beam lead bonding, pioneered and widely used by Bell Laboratories and Western Electric for many years, is used to interconnect gold beams extending from passivated semiconductor chips. Manual thermocompression gold wire bonding has been one of the most reliable bonding techniques in terms of bond strength and yield. Most gold thick films, even the earliest glass-bonded materials, perform well because of operator discretion in selecting bond sites. However, for each conductor, its processing conditions, and its substrate combination, certain machine parameters, such as temperature, pressure, time, and wire grade, need to be tested to define the proper bonding window. A need to increase the production rate led to the development of thermosonic wire bonding machines, designed to automate the wire bonding process. Throughput is high due to the preprogrammed rapid sequential bonding of many sites following the initial manual indexing. Yield is a function of bonding conditions, accuracy of site programming, and conductor properties. The latter is important in providing high bond yields, even when marginal bond sites are encountered. A gold conductor for automatic wire bonding should have a smooth surface, free of large areas of inorganic binder phase. Ideally, its cross section should be symmetrical with minimal curvature to provide the maximum effective bonding surface. Ultrasonic aluminum wire bonding is a technique commonly used for interconnecting active devices to thick film gold conductors. However, the exposure of the bonds to elevated temperatures during accelerated life tests or high temperature process sequences often cause metallurgical reactions to occur at the A1-Au interface that adversely affect bond integrity. Literature reports on AI-Au systems cite the formation of intermetallic phases and the development of porous regions due to Kirkendall diffusion as reasons for the loss in bond strength and the increase in electrical resistance. Laboratory studies of a state-of-the-art mixed-bonded thick film gold conductor-aluminum wire couple showed that during exposure at 250~ for 500 h, adverse changes in the mechanical and electrical properties are consistent with the void formation within the gold metallization, presumably due to Kirkendall diffusion. This work led to the finding that the addition of certain elements that alloy with gold will preclude the formation of voids and yield bonds with good mechanical and electrical integrity.

9.4.3 Copper The copper material system (CMS) consists of conductors, resistors, and compatible dielectrics. The CMS system is fired in nitrogen and is meant for use in hybrids, resistor networks, multilayer interconnects, microwave devices, replacements for Mo-Mn substrate metallizations, and even porcelain enamel steel substrates. Two nitrogen furnace designs are shown in Figure 9.8. The CMS system is dried at lower temperature, 120~ instead of 150~ and

192

MATERIALS FOR ELECTRONIC PACKAGING

Assumptions: 9Belt width 30 cm (12 in) 9Fully loaded belt Total nitrogen to furnace: 9380-475 liters/minute 9800-1000 cubic feet/hour

r

Entrance ~s0/0

Burnout ,~O/o

1

1

Firing 20%

()

Exit 15%

J T'III] J_

1

. . . . .

(a)

Entrance

Exit

Assumptions: * Belt width 30 cm (12 in) 9Fully loaded belt Total nitrogen to furnace: 9380-475 liters/minute 9800-1000 cubic f e e t / h o u r

Entrance ]5%

_

]1111 r

9

t

Entrance

~_~

Burnout 5O%

Firing 20%

_~.~

,

Exit 15%

j

l

ll'l'TTJ_

Jr

~

Will scale for larger or smaller furnaces

9

(

Exit

(b)

Figure 9 . 8

Schematic of two nitrogen firing furnaces: (a) typical furnace with recommended flow rate; (b) optimized furnace with improved flow in burnout section. (Courtesy DuPont Electronics.) is fired at 900-925~ in a nitrogen atmosphere with an oxygen content of less than 15 ppm. The firing profile is shown in Figure 9.9 and the flow of nitrogen is adjusted so that 29% is at the entrance curtain, 22% is in the burnout section, 32% is in the firing zone and 17% is at the exit curtain. The total flow is dependent on the muffle width. Copper oxidizes readily, so it is important the drying temperature is not too high and the exit temperature of the copper is made as low as possible to prevent oxidation when the parts exit the furnace. The resistivities of several thick film conductors are given in Figure 9.10. Copper is second only to silver and is not prone to migration. The CMS system is ideally suited to multilayer interconnect applications where lead resistance is an important consideration and gold is too expensive.

Thick Film Technology

90o 8oO 700

~

6oo

ling

5OO

~

4oo

~-

300 20o 100

0

1

0

l

10

1

20

1

30

1

40

50

Time (re,n) Figure

9.9 Nitrogen firing temperature profile. (Courtesy DuPont Electronics.)

~

Silver

~

Copper

l~i i i~iPlatinum-Silver il ~ Gold IZiiiiiYiiiCi iiiiiliiNic ii ~e' IFFijiiiii iiiiiiiii iiiiiloozierI~,r-,irea~,e,

li !iiiii i!iiiiiiii !i i]

Aluminum

lii iii!il I ~a''~'um-~''v~

! :~:i~:Platinum-Gold ":i!

03

I

1

I

3

I

10

I

30

I

100

I

300

I

1000

mD/square Figure

9.10

Resistivitiesof thick film conductors. (Courtesy DuPont Electronics.)

193

194

MATERIALS FOR ELECTRONIC PACKAGING

Because of its high conductivity, low and stable price structure, and excellent availability, use of copper and CMS can be expected to increase rapidly. Difficult materials development problems and other factors have limited the rate of acceptance, but they are being overcome. Among them are the changeover from air firing to nitrogen firing; development of cleaner-burning organic polymers for vehicles, which can be removed effectively in very low oxygen (ppm) environments to prevent carbon entrapment in the dielectric; development of highly conductive phases for resistors, which are so stable that they cannot be reduced in the hydrocarbon-rich burnout and oxygen-poor firing atmospheres; and much more careful control of the trade-offs in dielectrics, where high glass content, to insure hermeticity, must be balanced by enough porosity to permit evolution of the last traces of organics that could blister and bubble in the molten glass.

9.5 Dielectrics Thick film dielectric compositions fall into three functional classes: crossovers and multilayers, capacitors, and encapsulants. Crossover dielectrics electrically isolate two conductor lines, one of which crosses over the other. Dielectrics for multilayer circuits perform a similar function, isolating layers of printed conductors, however, communication between layers is generally done through vias and the dielectric layer generally covers most of the previous conductor layer. Both dielectric types were developed to increase circuit density through more efficient use of the substrate area, and both are used routinely in circuit manufacturing. The development of tape dielectrics has further advanced the state of the art and made thick film multilayer circuits more producible and cost-effective for certain applications. Dielectrics for screen printed capacitors have not been used broadly in the past due to a lack of hermeticity and low capacitance density (15 nF/cm 2) compared to discrete monolithic chip capacitors. Improvements, coupled with an increased penetration of thick film circuitry into the home entertainment market, led to opportunities for the thick film capacitor. Of particular significance are television tuner circuits with as many as 60 screen-printed capacitors manufactured in large volumes using thick film capacitor dielectric. Glass encapsulants are used routinely to protect thick film circuit elements from hostile environments. 9.5. I Crossover/Mulfllayer Dielectrics

The primary function of crossover and multilayer dielectrics is to electrically insulate conductive layers. Crossover dielectrics require a low dielectric constant (K), low electrical loss, high insulation resistance, high dielectric breakdown voltage, environmental stability and cofireability with top electrodes. Multilayer dielectrics need all these properties plus thermal expansion matched to the substrate, good via resolution, smooth surface, and high thermal conductivity. Three types of materials have been developed to meet these needs: glasses, crystallizable glasses, and crystal-filled glasses.

Thick Film Technology 195

The first crossover dielectrics were based on high melting, single phase glasses with low temperature coefficients of viscosity. Although these performed well electrically, processing was often a problem because of the need for a hierarchy of firing temperatures. All firings subsequent to the firing of the glass had to be done at temperatures lower than the glass softening point. This was necessary to prevent conductors printed on top of the glass from moving laterally across the crossover or even from sinking into the glass. This movement often led to electrical shorting and impaired solderability. To avoid the deficiencies of the singlephase glasses, crystallizable glasses with low dielectric constants were developed. During the firing process, these undergo chemical change during which one or more crystalline phases precipitate and a new glass is formed. To illustrate this a differential thermal analysis (DTA) scan of a crystallizable glass which precipitates BaA12Si208 is shown in Figure 9.11. The nucleation and precipitation of the crystalline phase give rise to exotherms, and their rates are functions of the time-temperature profile. The dispersed crystals strengthen the matrix glass and retard its flow during subsequent firing steps. In a well-designed glass, crystallization is complete at relatively low temperature, approximately 800~ This permits conductors to be separately fired or cofired on the dielectric at 850~ a common thick film firing temperature, without conductor movement or sinking. Crossover dielectric systems have also been used successfully to fabricate simple multilayer circuits. However, for large area, multilayer circuits with more than three metal layers, most crystallizable glass have thermal conductivities which are too low, and thermal expansion coefficients that are either too high or too low. Expansion mismatch with alumina substrates can cause the substrates to bow (Figure 9.12), and thus create problems in close tolerance packages subject to large thermal excursions. Also, systems stressed by large mismatches may fracture too readily when shocked thermally or mechanically. The need for better multilayer dielectrics led to the development of crystalfilled glass systems which provide greater latitude for physical design. For example,

iii

II

I II

ii

850 ~

Temperature

Figure 9.1 I DTA scan of a crystallizable glass dielectric composition. (Courtesy DuPont Electronics.)

196

MATERIALS FOR ELECTRONIC PACKAGING

Dielectric TCE Too Low Dielectric TCE Too High Dielectric TCE Matched Correctly

[I

Dielectri......_..~c TCE 5.0_x. 10-6/~ ] Substrate TC 6.8 x 10-6/oC - - ~

TCE 9.0 L.~ .Substrate TCE 6.8 x

10-6/~

[ Dielectric TCE 6.3 x 10-6/~

[

Substrate TCE 6.8 x

..J

I

10-6/~

Figure 9.12 Thermal expansion coefficients of components of a thick film capacitor, effect on substrate bowing. (Courtesy DuPont Electronics.)

to a good approximation, the thermal expansion coefficient of a composite (Jr'c)can be calculated from the expression jr" = ~iYiVi where Jr"i is the thermal expansion coefficient of component i and V~is the volume fraction of this component in the fired film. Thus, through the selection of suitable matrix glasses and crystalline fillers, the composite thermal expansion coefficient can be adjusted to the desired value. The functions of the major components of this kind of dielectric thick film composition are illustrated in Table 9.4. In developing a multilayer dielectric composition, a high quality factor, low K glass was chosen for the matrix. Two crystalline fillers were selected to obtain a composite with the desired combination of high thermal conductivity and close thermal expansion match with the alumina substrate. Although the above equation was sufficient to qualitatively determine the level of filler addition, final levels were determined experimentally via substrate bowing measurements. The thermal expansion coefficient of the composite was then designed to be slightly lower than the coefficient of the alumina substrate, placing the fired dielectric under slight compressive stress for.maximum strength. Table 9.5 gives typical bowing data for the crystal-filled dielectric and for a crystallizable dielectric as a function of the number of dielectric layers. The

9.4 Substrate bowing (%) after firing pairs of dielectric layers at 900~ a

Table

Number of dielectric layers Dielectric type

2

4

6

8

Crystal-filled Crystallizable

0.6 1.6

0.9 5.5

1.2 -

2.4

1% bowing, 1"= 0.006 mm (0.25 mil) deflection from flatness, as measured from the center of a 5 mm (0.2 in.) substrate.

a

Thick Film Technology 1 9 7

Table 9.5

Chemical composition of 96% aluminia substrates. 96% A1203, alumina 2.5% SiO2, silica 0.75% MgO, magnesia 0.25 % CaO, calcia Li20, lithia Na20, soda 0.50/0 K20 , potassia Impurities ZrOz, zirconia Fe20 3, ferric oxide TiOz, titania

advantage of minimal bowing for the crystal-filled dielectric is readily apparent. The measured thermal conductivity of the filled dielectric is 2.0 W m-1 K-1, a factor of 3 higher than the matrix glass and a factor of 2 higher than many crystallizable dielectrics. Thick film compositions were used to make low layer count multilayer ceramic circuits for a number of years. However, because of the demand to increase density and still retain restrictions on size and weight, thick film began to reach its limit on the number of layers that were practical without paying the high costs associated with labor and yield. So a low temperature cofire system was developed to combine the positive attributes of the thick film and the high temperature cofired alumina. The low temperature tape system consists of a dielectric cast into tape, compatible conductor compositions for printing lines and filling vias, and compatible thick film compositions (resistors and conductors) that can be postfired onto the cofired structure. The tape system technology provides high density, hermeticity, thermal expansion match, low dielectric constant, design and production flexibility, and the ability to form cavities. The basic shortcoming of the system is thermal conductivity, and even this has been overcome by circuit design and the use of thermal pipes to manage power dissipation. 9.5.2 Capacitor Dielectrics A thick film capacitor is produced by three sequentially printed layers, two electrodes separated by a dielectric material. Usually, the composition for the bottom electrode is used to simultaneously print the conductor wiring for the entire circuit. Depending on performance and cost considerations, electrodes span the range from gold metal to high silver content alloys. The capacitor dielectric may be glasses, glass ceramics, ferroelectric crystalline oxides, and combina-' tions thereof. Dielectric constants of 10-1 500 can be obtained with current technology.

198

MATERIALS FOR ELECTRONIC PACKAGING

This results in capacitance densities of 175 pf/cm 2 to about 26 nF/cm 2. Crossover dielectric compositions with K = 10-15 are used for low value capacitors. Capacitors fabricated with dielectric materials having K > 50 are usually porous and require encapsulation for protection in humid environments. Dielectrics with K ~> 100 contain refractory ferroelectric oxides, such as barium titanate (BaTiO3), and small amounts of binder to aid sintering. Although extensive sintering does not occur at normal thick film firing temperatures (850950~ K > 1 000 can be achieved easily. Generally, these systems contain a reactive glass binder. For higher K values, the binder is more critical. It must enhance sintering without the formation of low K dielectric phases. Newer high K dielectrics contain reactive crystalline binders that maximize K. These can be used in relatively high concentrations, leading to more effective sintering. The composition of the binder within the conductor also influences dielectric performance. Chemical reaction with the dielectric can result in low K phases which lower the overall capacitance value. Also, conductors containing crystalline oxides that react chemically with ~the alumina substrate to promote adhesion may contribute to low capacitance density and poor electrical performance. For example, conductors with too high a content of copper oxide can react with the dielectric and result in high dissipation factors or may lead to capacitor shorting. Performance of a screen-printed capacitor system is primarily determined by the thick film materials, but the printing procedures and firing sequences are also very important. Experiments have repeatedly shown that pinholes in the dielectric are minimized and the breakdown voltage is maximized when the dielectric layer and the top electrode are cofired. Also, two layers of dielectric printed with a double wet pass, in the same or opposite direction, decrease the probability of pinholes. A soft squeegee with a hardness of about 60 durometer or a flexible squeegee with an attack angle of 60 ~ insures uniform paste deposition. The fired thickness of the dielectric should be 38-50 #m. Using a process identical to blending thick film resistors, two dielectrics are frequently blended to achieve a desired capacitance.

9.5.3 Encapsulant Oielectrics The primary purpose ofencapsulants is to protect circuit elements from hostile environments. Both organic and inorganic (glass) coatings have been used for this purpose. Glass encapsulants were originally developed to protect the Pd/PdO/Ag resistors, which were inherently unstable when subjected to any hostile environment, including humidity. These encapsulants were based on low softening point lead borosilicate glasses, which could be fired at a peak temperature of approximately 500~ The low firing temperature was essential to minimize changes in the values of the resistors when retired during encapsulant processing. With the development of more stable ruthenium-based resistor systems, the need for encapsulants was not as great. Nevertheless, the encapsulation of resistors is still common, particularly for applications demanding high reliability or subjected to hostile environments.

Thick Film Technology 199

The fired thickness of an encapsulant layer should be no greater than 10-15/~m; at greater thicknesses the removal of the underlying resistor in the laser trimming operation becomes quite difficult. Any debris left in the laser kerf will ultimately result in resistor instability. This is especially important for low value resistors, where the combined resistor-encapsulant thickness approaches 32/~m. Encapsulants have found a niche in protecting silver-bearing conductors from potential metal migration. More encapsulant is used for this purpose than for encapsulating resistors. Another use is as a solder dam or solder mask. Encapsulants are also important to the performance of screen printed capacitors. Only the very low K films are sufficiently dense and impervious to moisture after firing so as not to require encapsulation. An encapsulant must interface simultaneously with the electrode, the dielectric, and the substrate, so it must have only a minimal adverse effect on capacitor electrical properties. For optimum stability, the thermal expansion of the encapsulant should be lower than the thermal expansion of the capacitor. This places the encapsulant in compression and minimizes the possibilities for stress cracking. There are limitations to this approach since too wide a difference in coefficient of thermal expansion (CTE) will still produce cracking. Thus, a glass encapsulant with a very low CTE, lower than the substrate, will tend to crack. The problems resulting from the large CTE differences were resolved by using two separate encapsulant layers. The first layer is a crystal-filled glass with a CTE greater than alumina but lower than the dielectric. This places it in compression over the printed capacitor. The second layer is a glass with a CTE slightly lower than alumina; it seals defects in the first layer and places it in compression over the capacitor and alumina. The resulting structure is similar to a graded seal. The presence of printed capacitors on a substrate places constraints on the location of resistors. The thickness of an encapsulated capacitor is approximately 75-100 ~tm. Thus, when a resistor is located close to a capacitor, it is difficult to print it to uniform thickness. Generally, resistors close to capacitors will be excessively thick, difficult to trim, and usually unstable. 9 . 6 Vehicles

The vehicle component of thick film compositions (Figure 9.13)is the medium in which the inorganic particulates are dispersed and which makes the compositions screen printable. Both the vehicle and the dispersed phases contribute to composi-

Resins i~ Solvents

"~

Vehicle

Modifiers

Figure 9.13

Vehicle manufacture. (Courtesy DuPont Electronics.)

200

MATERIALS FOR ELECTRONIC PACKAGING

tion flow characteristics, but the chemical and, usually, the particle size distribution and morphology of the solids are fixed by fired film performance needs. Thus, the vehicle is the key variable to producing suitable printing characteristics. In addition, it determines the drying rate of the composition on the screen and the print, it determines the change in flow properties with temperature, and it helps to form a temporary bond between the dried film and the substrate before firing. Unless it burns smoothly and cleanly during firing, the vehicle system can adversely affect the electrical properties and the cosmetics of the fired film. Many of the early vehicles, such as simple mixtures of terpineol solvents and cellulose resins, continue to perform well with multiple solid systems in a variety of printing environments. However, requirements for fine line resolution (approximately 125 #m widths) and high part throughput stimulated the development of new organic vehicle systems, some containing multiple solvents and resins, a significant departure from the early materials. Viscosity is the most widely used parameter for assessing a composition's flow behavior. Viscosity is the internal resistance exerted by a fluid to the relative motion of its parts and can be expressed in units of pascal seconds (Pa s). It is defined as shear stress divided by shear rate; where shear stress is the force in pascals applied to a viscous fluid to cause its movement and shear rate is the rate of travel of two parallel, fluid-separated plates divided by the distance between them---(cm/s)/cm = s-1. Shear rates to squeegee a composition on to a screen, and for composition transfer through the screen, are estimated in the literature to be about 1-10 s -1 and 100-1 000 s-l, respectively. Composition settling of the patterned substrate is estimated to be less than 1 s-1. Figure 9.14 illustrates four ways in which fluids can respond to shear. Since viscosity is shear stress divided by shear rate, the viscosity of a newtonian fluid

Shear Rate

oplastic

Shear

Figure 9 . 1 4

f

Dilatant

Stress

Response of fluids to shear. (Courtesy DuPont Electronics.)

Thick Film Technology 201

is independent of shear rate, and a dilatant fluid becomes more viscous as the shear rate increases. These characteristics usually do not contribute positively to the printability of a thick film composition. Most thick film compositions are formulated to exhibit pseudoplastic or thixotropic flow behavior; they respond to shear with a decrease in viscosity and return to a high viscosity when the shear ceases. However, a thixotropic material exhibits hysteresis; viscosity at a given shear rate is usually higher with an increasing shear rate than a decreasing shear rate. This behavior tends to permit the leveling of screen mesh marks on the print surfaces but is also conducive to line spreading; the degree of thixotropy is important in balancing these phenomena. There are two ways in which the printing operation can influence parts throughput. First, through the simultaneous printing of several identical circuits on a single substrate followed by fracturing the substrate along scribed lines to produce multiple individual circuits. Second, through an increase in the speed of squeegee traverse from about 10 cm/s to over 25 cm/s. Under conditions of rapid printing, compositions tend to pull away from the print as the squeegee passes across the screen pattern and the screen snaps away from the substrate. This behavior often produces prints that contain voids and/or composition deficient areas. Compositions that produce such prints are said to exhibit too much tack. Research led to the understanding that low viscosity at high shear rate is important in reducing tack, and to the development of complex vehicle systems with which viscosity at low and high shear rates can be adjusted independently. Figure 9.15 shows rheograms of two Pd-Ag conductor compositions, one formulated with an older, standard vehicle, the other formulated with a new, high speed

20118

.=_

.L212'

~..) 11

High printing

ard

speedvehicle

le

6

4 2 0

100

300

I 500

I 700

I 900

Shear stress (dynes/cm 2) multiplier 200

Figure

9.1 $ Rheology of Pd-Ag conductors. (Courtesy DuPont Electronics.)

202

MATERIALS FOR ELECTRONIC PACKAGING

High Printing Speed Vehicle

Standard Vehicle

~ :it .~ .

~:.,~~1~

-~-":.~5~

Printing Conditions adjusted to promote "pull-up" of composition; high squeegee speed, small gap.

Figure 9.16

Optical photomicrographs of Pd-Ag conductors, dried surfaces. (Courtesy DuPont Electronics.) vehicle. At a shear rate of 100 s-1, the viscosity of the standard vehicle is about twice the viscosity of the high speed vehicle. Figure 9.16 shows optical photomicrographs of the surfaces of dried prints produced with each of these materials. Printing conditions were adjusted to promote void formation: very high squeegee speed and small gap or snapoff distance between the screen and the substrate. The print of the conductor formulated with the vehicle for high speed printing exhibits the smoother surface, free of imperfections evident in the standard print. Thick film technology is important in the production of a broad spectrum of hybrid integrated circuits, networks, and discrete passive components. Parallel trends toward high reliability, high volume production, circuit miniaturization, and low cost were the impetus for the accelerated development of high performance materials. Materials development moved from a formulation art to a base of greater understanding, an understanding of the relationship between materials chemistry and the details of electromechanical performance.

9.7 Thick Film Processing Before discussing thick film processing, it is important to realize the importance of the substrate. The standard substrate for the thick film industry has been 96% alumina (A1203). This substrate has excellent electrical characteristics, high thermal conductivity, good dimensional stability, excellent mechanical strength, can withstand the firing temperatures required to process thick films, and is considered to be chemically inert. In addition to all of the technical attributes, it is relatively low in cost and available in large quantities at excellent quality. With all of these attributes, users have generally specified only mechanical properties, such as length, width, and thickness tolerances; surface characteristics, such as roughness and integrity; and other physical properties, such as camber.

Thick Film Technology 2 0 3

The composition of 96% alumina is shown in Table 9.5. In addition to the 2.5% silicon dioxide, the 0.75% magnesium oxide, and the 0.25% calcium oxide, which are there by design, there is also approximately 0.5% of impurities. Impurities include oxides of lithium, sodium, potassium, zirconium, iron, and titanium and appear in very small quantities; they arise from the natural clays used in the formulation of the powders or slurries from which the substrates are produced. The analysis shown is for the composition of the bulk material, however, impurities can concentrate on the surface of the substrate and lead to unanticipated problems, often attributed to other causes. The substrate interacts with thick film conductors and resistors both mechanically, through surface roughness and porosity, and chemically, due to the interaction of glasses in the compositions and alkaline oxide fluxes in the substrates. Figure 9.17 shows the concentration profiles of the dissolution of alumina into a typical thick film resistor and the diffusion of PbO into the substrate. The Pb diffuses to a depth of approximately 4 pm. We can conclude that the bulk properties of the substrates are not of great importance in the thick film process, but surface chemistry and surface condition are. As a result, the sophisticated user should be concerned with functional properties on a lot-to-lot basis, as well as the normal physical and mechanical properties that are currently specified. Tests, such as conductor adhesion and solderability, as well as resistor value and TCR measurements should be performed on each new lot of substrates. Lot control should also be maintained. This should assure the thick film process is more reproducible and isolate process problems from those caused by chemical reaction of the thick film compositions with various surface impurities.

. -9- - S u b s t r a t e - . - . . _ .

a) -_>- 1 0 0 - % A I

&

.,,-.-Apparent interface Res4sto~r ,,

%Pb

80"

c

~

60

~

40

r

--~

20 6 5 432

1 01 234

/am - - - D i s t a n c e in Substrate Figure

56 7 8

i

/am I Distance in R e s i s t o r - - -

9.17 Concentration profiles showing dissolution of A1203 in a resistor and PbO diffusion into a substrate. (Courtesy DuPont Electronics.)

204

MATERIALS FOR ELECTRONIC PACKAGING

9.7. 1 Printing Process

It is important to define some terms before discussing the printing process:

Snapotf: the

distance between the screen and the surface being printed.

Attack angle: the angle between the printing face of the squeegee and the surface being printed.

Downstop: the mechanical limit of squeegee travel onto the screen. Flood: the spread of ink over the screen before the printing stroke. Peel: the release of the screen from the composition after printing. Durometer: the hardness of the squeegee.

Squeegee travel: the length of the print stroke. Emulsion: the coating on the screen used to define the pattern being printed and used as a gasket between the screen and the surface of the printed part. Mesh count: the number of wires per inch of screen fabric. A distinction is made between the surface being printed and the surface of the substrate. As more and more layers are printed, the surface of the substrate and the surface being printed are quite different. In complex multilayers, the surface being printed can be double the thickness of the substrate and, therefore, the snapoff distance must be changed for each layer. As a rule of thumb, the ratio of the screen diameter to the snapoff distance should be 200:1. Figure 9.18 shows typical snapoff distances for a variety of common screen sizes to produce equal peel force on the screen as it releases from the composition after printing. The printing process requires the composition being printed to be transferred from the screen onto the substrate being printed. Figure 9.19 shows three different attack angles in common use for printing thick film compositions. The most common squeegee attack angle is 45 ~. As the squeegee travels across the screen, a force is exerted in the horizontal and vertical directions. The magnitude of the force increases as the attack angle decreases, so the thickness of the print obtained with a squeegee having a 30 ~ angle will be greater than the thickness obtained with a 45 ~ angle, itself greater than the thickness obtained with a 60 ~ angle. This is illustrated in Figure 9.20.

F////////A

.

.

F .

1 Figure 9.1 8

.

(Snap-Off) .

.

.

.

.

.

.

.

.

.

.

.

.

7' _ r/2//#///~

V////z~/?//////z

Screen Size

Snap-Off (Normal Range)

Screen Diameter 200:1

5x 5 8 x 10 12 x 12

.02-..03 . 0 3 - .04 .04 -- .06

.025 .04 .06

Snapoff distance. (Courtesy D u P o n t Electronics.)

Thick Fi/m Technology 2 0 S

/

Print T h i c k n e s s : t30 o > t450 ;> t60* Figure 9 . 1 9

Attack angle versus controls transfer mechanism. (Courtesy DuPont

Electronics.) 28

-

27

Resistor 1 Mfl/ll~ Squeegee Speed 20em/see (8 in/see) Squeegee Stroke 10cm (4 in)

26 E =1.

24

cn

22

(1) r

-~ o r.-o

(1)

:-

23 22 21 20

I 30 ~

I

Attack Figure 9.20

I

45 ~

60 ~

Angle

Attack angle versus thickness. (Courtesy DuPont Electronics.)

Downstop is important to the printing process to prevent such problems as coining, stretching, puncturing of the screen mesh and to prevent poor print resolution. The proper downstop should be 125-175/~m below the surface of the substrate being printed. Screen peel is the release of the mesh from the wet print and can lag behind the squeegee edge 0-5 cm depending on the tackiness of the composition being printed, the squeegee speed, the mesh count, the tension, the condition of the screen mesh, and the snapoff distance. It is important the squeegee speed is adjusted

206

MATERIALS FOR ELECTRONIC P A C K A G I N G

to insure the screen releases as close to the squeegee edge as possible. This means the squeegee must be slowed in some instances. Failure to do so may result in poor print quality, especially pinholes and pullouts. The best way to accomplish this is by observation. One should observe how the screen is releasing from the composition during the printing cycle and make proper adjustments to insure the print speed is right for the composition being printed and the screen peels immediately behind the squeegee edge. The screen printing process is basically a volume transfer of the composition to the surface being printed. The mechanism is controlled primarily by the screen mesh and the thickness of the emulsion. Figure 9.21 illustrates the percentage open area for various common screen meshes. Table 9.6 details the effect of screen mesh on print thickness assuming that a composition has been calibrated to yield a 25/~m dried print using a 200 mesh screen with 53 /~m (2.1 x 10 -3 mil) stainless steel wire diameter. The primary factors that affect print thickness are the percentage solids content of the composition, the screen mesh count, and the screen emulsion thickness. The percentage solids content is optimized by the thick film paste manufacturer and should not be altered by the user through the addition of excess solvent or vehicle. The reason is that most vehicle systems are complex and balanced

I I I

b

.

.

-t % open =

a

1_ - I ~ I--

Figure

9.21

I I I

200 m e s h

a = 1/200 = 0.005" b = 0.0021" or 0.0016"

b = 0.0021" b = 0.0016"

% o p e n = 3 3 .6 4 % % o p e n = 4 6 .2 5 %

250 m e s h b = 0.0014"

% o p e n = 4 2 .2 5 %

325 m e s h b = 0.0011"

% o p e n = 4 1 .2 8 %

Screen mesh selection. (Courtesy DuPont Electronics.)

(a-b) 2 a2

x 100

Thick Film Technology 2 0 7

Table

Mesh

200 200 250 325

9.6

Screen mesh versus thickness? B (pm)

% Open

Print thickness (llm)

53 41 36 28

33.6 46.2 42.3 41.3

25 26 21 16

Assumptions: 200 mesh (B = 53/~m) yields 25/~m dried print; any given composition has been normalized to give 25/~m at a given solids content with 200 mesh screen. a

for resin-to-solvent ratio. Improper or excessive dilution can cause separation of the vehicle and the inorganic solids, which at worst destroys the integrity of the films or at best causes rheology and printing problems. The best way for a user to alter print thickness is by the proper selection of screen mesh and emulsion thickness. Secondary factors which affect print thickness are attack angle, snapoff distance, squeegee durometer, squeegee pressure, squeegee speed and downstop. These factors are sometimes used to make minor adjustments in print thickness. It is very important to avoid excessive wiping of the screen. If a solvent is used to wipe the bottom of the screen it should be compatible with the composition being printed. It is usually desirable to use the solvent recommended for thinning the composition being printed. Emulsion wear, screen tension, and the general condition of the screen should be monitored. These directly affect both the thickness and the definition of the films. Paste should never be allowed to dry on the lid, and care should be taken to avoid composition drying on the lip of its container. Clogging of the screen mesh and void formation can result if dried paste particles inadvertently fall into the wet paste. The thick film screen printing process involves many variables which must be controlled for optimum results. The capabilities of the thick film composition play a key role in obtaining high production yields. Process control will be more effective if a high performance thick film composition is used properly. 9. 7. 2 Firing Process

During the drying and firing processes, the solvent evaporates at 25-150~ The polymer decomposes at 150-500~ the glasses begin to melt and other phases begin to sinter at 600~ and above. It is important to have adequate ventilation and exhaust during the evaporation phase. During the polymer decomposition phase, a sufficient amount of air is required to totally convert the organic polymer to gaseous phases which, coupled with a properly located exhaust, will totally remove the organics from the firing atmosphere. The rate of temperature rise from 300-600~ is typically limited to 50-85~ to assure that no carbon entrapment occurs. Thicker prints

208

MATERIALS FOR ELECTRONIC PACKAGING

require slower rates. The amount of air required for adequate burnout can be calculated from (9.1)

V = PLA WS

where V is the volume of airflow required in liters/min or standard cubic feet (SCF) per minute depending on whether metric or English units are used in the calculation; P is the ratio of printed paste area to total substrate area; L is the ratio of total substrate area in the furnace to total belt space area available; A is a constant representing the amount of air needed per unit area of printed paste being processed to completely burn out the polymer in the thick film composition (0.4 liter/cm 2 or 0~1 SCF/in.2); W is the belt width in cm or in.; and S is the belt speed in cm/min or in./min. For example, for a substrate which is 33% covered with paste, fired in a furnace which is 75% loaded, having a belt width of 20 cm (8 in.) at a belt speed of 10 cm/min (4 in./min) the required volume of burnout air is V = 0.33 x 0.75 x 0.4 x 20 x 10 = 20 liters/min (50 SCF/min)

(9.2)

The typical profiles used in firing most thick film compositions are shown in Figures 9.22 and 9.23. The airflow arrangement for a typical air-firing furnace is shown in Figures 9.24 and 9.25. Alternate air flow arrangements are shown in Figure 9.26. The location of the exhaust is very important. Ideally, the exhaust should be at 500~ to avoid passing any of the burnoff products over the fired films at higher temperatures, which could cause reduction of some of the glasses or oxides. Forcing of the burnoff products over cooler parts can cause precipitation of the organics or carbon; this may lead to entrapment later in the firing cycle. For the profiles shown, temperature should be controlled within __+2-3~ for a peak time of 9-11 min in all cases, except for encapsulant firing. For encapsulants the total cycle time is 20 min to a peak temperature of approximately 500~ with minimum soak time at peak temperature.

lOOOl-

90018OO O 70O 6OO 5OO E 4OO I--- 300 200 100 / 0 Figure 9 . 2 2

Riserate ..-50oC/min

/

Enlry 10

10min 850~

~

\

IBelttrav~I ~-20 30 40 Time(minutes)

Descent rate o~ %

1%Ex,t 50 60

Recommended firing profile, 60 min cycle. (Courtesy DuPont Electronics.)

Thick Film Technology 2 0 9

~l

--

900

10 M i n u t e s at Peak ~

.- I

850 ~ C Peak

800

700

600 A

oo v

I.U rr :::)

I--

<

n-

D e s c e n t Rate 100~ 700 ~ - 300o0

500 Rise Rate - 100~ 3 0 0 ~ . 500oc

400

u.I n

=Z UJ

300

I--

200

-Ent

200

Exit

me

Belt Travel

I

I

0

5

I

10

I

15

I

I

20

I

25

30

TIME (Minutes)

Figure 9.23

Recommended firing profile, 30 min cycle. (Courtesy DuPont Electronics.)

Exhaust vent (TSL)'"I Burnout air .................... direction

Alternate I ' 1~ v e n t - p r o f i l e :Ill alignment (QA)

Ill

,,#_I #i ~-,._~ Firing air ........... !.................. ,....................................................................................... ,Be!:!:.:.d!:rec!:!on............................... ~: ...................................... d!mc.!:!0n:............................................................

,,

\

Muffle

I

1000

I

800 oC

600 400 200 0

Burnout

~3~176176 I I~ to 450oc

Figure 9 . 2 4

Time --).Firing >600~

Annealing

~1 ~7~176176 to 400~

Furnace airflow arrangement. (Courtesy DuPont Electronics.)

\

Belt

210

MATERIALS FOR ELECTRONIC PACKAGING

ii Da0er

Exhau

\m0er

I I

~ Q

Entrance--~air I Q ~ e e) curtain I Burnoutair

I

100~ (~

Firing air / (~ ~

I

400~

I

100oc

Air in Air flow direction 1. Burnout air PLAWS 2. Firing air 1.3 x PLAWS 3. Adjust exhaust vent damper

Figure 9.25

I

400oc

850~

Exit air curtain

4. Smoke test at exit 5. Set exit curtain to block room air 6. Smoke test at exit

Furnace air flow. (Courtesy DuPont Electronics.)

~.

Burnout Air Supply

Exhaust Venturi

Burnout Air Rake i( r

~,~ I , ] k l ' ~ % . ~ . ~ ~ ~ l ~ h ~ Firing Air Direction . . . . . . . . . . . --"---"-. . . . . . . . . . . . . . . . . . . . . . _-1-_e_.._______/ B t___D r____e i i___o_n____-~ ct . . . . . . =-.-----=-,

i

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Burnout Air Direction

~ ~l.._Exhaust Venturi

Burnout Air Supply

Im

ia

m

Im

m

m

m m

m m

a m

m

r m

m

Baffle Duct

e m

in

IBm

~ m l a m

m

1 m

m

Belt

i

m

m

m m

m

m

m

Direction m m

m

m

m m m

Firing Air Direction m m

m

m

m

m

m

m e

m m

ml

Burnout

J

Vent Stack l

Air Direction Burnout& Firing Air Direction

|__l__l__m.~im~l__l)__llm~l__l__l__l__l.~m__l__l__l)i

Figure 9 . 2 6

i

m.~l.._mmmm~

Alternate airflow arrangement. (Courtesy DuPont Electronics.)

Thick Film Technology 21 1

From 700-300~ on the descent slope of the profile, the glasses solidify and anneal. The rate of descent should be kept at 50-85~ to prevent stresses from accumulating in the fired films. These are most critical in resistor films since they can seriously affect stability and temperature coefficients of resistance. This has been a brief description of what happens during air firing. The precise shape of the profile is not important; it may vary from furnace to furnace. But most important is that once a profile has been established it must be duplicated as closely as possible to obtain the best and most reproducible results. The copper material system is fired in nitrogen. Its processing has already been covered briefly in the section on materials. Nitrogen firing is most common for the CMS systems, but other atmospheres and dopants have been found effective and in some cases superior to pure nitrogen. 9. 7. 3 Laser Trimming

Thick film resistors are usually printed and fired to values below the desired final value, with a fairly wide as-fired distribution. The resistors are then adjusted to value using a cutting process which usually reduces the width of the resistor, causes the resistance to increase, and the distribution to decrease. Laser trimming is a widely accepted method of adjusting resistors to their final value using a high intensity light beam which rapidly heats the resistor material and causes it to vaporize. The speed at which resistors can be laser trimmed increases in importance as more emphasis is placed on the high volume manufacture of resistor networks and hybrid circuits. Before beginning a discussion of laser trimming and faster processing, it is worthwhile to review some definitions, to examine specifications differences between laser trimming systems, and to establish some guidelines. A basic laser trimming system consists of a laser element, a computer control system, a resistor probing and measuring system, and a mechanism to move the laser beam from point to point across the substrate surface. Most of the trimming systems used in thick film processing are solid-state lasers using neodymium-doped yttrium aluminum garnet (Nd:YAG) laser rods. The rod is placed in a gold-plated, elliptical cavity with a DC krypton arc lamp. Normally, the laser produces a continuous wave of moderate to low power. To achieve the high peak power necessary to vaporize thick film resistors, giant pulse operation is required. This is achieved by adding an acoustic Q-switch to the system. A Q-switch is an electrically driven acousto-optical quartz block that interrupts the laser beam and causes large amounts of energy to build up. When the Q-switch is in phase with the laser beam path, it allows large energy pulses to be released at a frequency controlled by the RF power supply used to drive it. Pulses with peak power in excess of 25 kW can be produced at pulse rates of 1-50 MHz. A comparison of two commonly used lasers is given in Table 9.7. A block diagram of a laser system is shown in Figure 9.27; a cross section of the laser cavity is shown in Figure 9.28. The elliptical shape assures all the light emitted from the arc lamp will be concentrated on the laser rod for maximum

21~

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MATERIALS FOR ELECTRONIC PACKAGING

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Thick Film Technology 21 3

Table9 . 7

Comparison of two common lasers.

Average multimode power (W) Average TEMoo power (W) Multimode beam diameter (mm) Repetition rates (kHz) Rod size (mm)

Laser A

Laser B

30 4 4.0 1-50 4 x 50

50 6-8 4.0 1-50 4x50

Figure9.28 Cross section of elliptical laser pumping cavity; all light emitted from the lamp will focus on the rod. (Courtesy DuPont Electronics.)

TEMoo

TEMol

TEMol

TEMo3

TEMo4

8b TEMo2 Figure 9.2 9

Laser spot shapes.

efficiency. When the krypton arc lamp current is kept at reasonably low levels (16-18 A), the spot shape of the laser beam remains in its fundamental mode, TEMoo. Its diameter is 1.5-2 mm. Increasing the lamp current causes the beam to diverge into multimode operation TEMol, TEMo2, and so on. This increases the diameter of the beam and lowers its intensity. Figure 9.29 shows some of these laser spot shapes. The preferred mode of operation is TEMoo. In this mode the

214

MATERIALSFOR ELECTRONIC PACKAGING

energy of the beam has a Gaussian distribution. Although successful trims have been made using multimode operation, TEMoo mode is recommended for maximum control and precision. Two process variables have been introduced: lamp current influences average power produced by the laser beam and acoustic Q-switch frequency dictates pulse frequency or the number of pulses per second which will be produced. These are two of the three variables controlled during the laser trimming process. Figures 9.30 through 9.33 show the relationship of peak power, average power, and pulse width as a function of pulse frequency for 30 W and 50 W lasers. The 30 W laser produces approximately 4 W of TEMoo power and it decreases rapidly with increasing pulse frequency. Laser trimming thick film resistor material requires Peak Pulse Power

Peak Pulse Power 10.0

Pulse Width

Average Power

" (nsec)

(kW)

8.0 6.0

i ~ -

4.0

" q ~ Pulse Width

,.

2.0

9.30 Electronics.)

Figure

(W) 5.0

- 400

4.0

300

3.0

- 200

2.0

100

1.0

-

1.0 2.5 5.0 10 15 20 Repetition Rate kHz 30 watt laser, TEMo.o

Average Power

25

Repetition rate for 30 W laser, 2-10 kW peak power. (Courtesy DuPont ~~

~.~.s.

60 "~/.//"

50 L (D

~176176176

Average p~

- 600

30

1 500

25

40

400 "~ 20 ~,.. i"/ \

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300 .~_ 15 ~

200.= lo~

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100 I

1.0

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2.5

I

5.0

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10

I

15

I

20

5

25

Repetitionrate kHz 30 watt laser,multimode Figure 9 . 3 1

Electronics.)

Repetition rate for 30 W laser, 10-50 kW peak power. (Courtesy DuPont

Thick Film Technology

Peak Pulse

21 '3

Pulse Average

Power (kVO

Average Power

Inset) (W)

10.0

50O 8.0

8.O

4O0 6.0

6.0

300

4.0

4.O

200

2.0

2.0

100

1.0

1.0 2.5 5.0 10 15 Repetition Rate kHz

20

25

50 watt laser, TEMo,0

Figure 9.32 Electronics.)

Repetition rate for 50 W laser, 2-10 kW peak power. (Courtesy DuPont

Peak

Pulse Power (kW) -

50 _ 40

~

Pulse Average l WK:IIh Power "1 (nsec) (W)

Peak Pulse ~ " Power

Average Power

500

50

400

40

300

30

30 20

Pulse Width

200 20 100

10 1.0 2.5 5.0 10 15 Repetition Rate kHz

20

10

25

50 watt laser, multimode

Figure 9.33 Electronics.)

Repetition rate for 50 W laser 10-50 kW peak power. (Courtesy DuPont

high peak power. For maximum resistor stability, the peak power should be maximized and the average power minimized. This assures that most of the energy is used to vaporize and remove the resistor material and less energy is lost in undesired heating of adjacent resistor and substrate material. Once the pulses exit the laser, they must be directed to the surface of the substrate. They must then be moved into position to adjust the resistors and cross the substrate from resistor to resistor. Two main methods are presently used. One method uses galvanometer driven x and y mirrors, very responsive and capable of

216

MATERIALS FOR ELECTRONIC PACKAGING

accelerations up to 1960 m / s 2 (2009). The other method uses linear accelerators which are directly coupled voice coil actuators; they have very high positional accuracy and repeatability, but since they also have considerably more mass their acceleration is approximately 196 m/s 2 (209). The galvanometer driven mirror system is therefore capable of higher trimmin9 speed, the third process variable. Incorporated into the beam positioner is a focusing device to concentrate the beam energy at the surface of the substrate. The focusing lens for thick film trimming optics has an optical rating equivalent to an f/30 setting on a camera lens. This allows the laser beam to be focused to a minimum theoretical waist of 30 #m. The practical minimum spot size achieved is 50 #m in diameter. The depth of field for these optics is approximately 400 #m. It is therefore important to keep the beam in sharp focus and to re-focus when changing from one substrate thickness to another. An aperture is generally used to filter the beam as it exits the laser; this facilitates focusing. The most commonly used aperture diameter is 1.5 mm. Focus and aperture are two setup variables of the laser trimming process. Producing clean laser cuts begins with proper processing of the thick film resistors to be cut. Film thickness is particularly important. Laser trimming is a physical process. Material is removed by vaporization. The thicker the film, the harder it is to vaporize cleanly with the available energy. If the film is too thin, resistance is difficult to control and the results are excessive resistance value distributions and erratic TCRs. In addition to the thickness of the resistor film, the film interacts with the substrate to a depth of 4-6 #m. This interaction zone must also be removed to achieve maximum resistor stability. The integrity of the remaining film and the stability of its resistance value are dependent on the cleanness of the kerf and the amount of damage which has been done. Excessive damage occurs when too much power, at less than vaporization level, is allowed to affect a given area. It is therefore important to optimize the peak energy for each pulse and the speed at which the pulses travel across the surface of the material being trimmed. Figure 9.34 illustrates the mechanics of the laser cutting process. The two conditions shown may be produced by trimming speed and/or pulse frequency. Figure 9.34(a) shows a cut with 50% overlap. Figure 9.34(b) shows a cut using less than 10% overlap. With less than 50% overlap, a ragged, irregular cut of insufficient depth often results. The minimum overlap should be 50%. Overlap is also important for accurate adjustment of thick film resistors. With 50% overlap and a focused pulse of 50 #m in diameter, each pulse takes a 25/~m bite out of the resistor. At this rate of removal, it is quite possible to overtrim a resistor. In Figure 9.35, two resistor geometries are compared. One is 2.5 mm x 2.5 mm and the other 1 mm • 1 mm. When the 1 m m 2 resistor is raised to a value 1.4 times its fired value, one extra pulse of 25 #m in length raises its value an additional 3.6%. Its value is increased 2.5 times its fired value, one extra 25 #m bite would raise its value an additional 10%; the overlap must be much less than 50% to achieve close tolerances. Bite sizes of 2.5-7.5 #m are most common in the industry. For this discussion, a maximum bite size of 8.25 #m or 120 pulses/mm is recommended.

Thick Film Technology

(a)

1

-----

Bi" S"e--I I--

?

9

!

--,.,.-,-

.

I

i

9

.

~

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"

"

;

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9

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(b)

".gg.~ K.r,

8"'S"'

;I I--

I ! 1 1 I I J I l~aserPu'ses Figure 9.34

Mechanics of the laser cut. (Courtesy DuPont Electronics.)

W 0-

%

0:4

,, t,.

o

3

1=

u. 2.5 . IE vr ra

2

(1 X 1 m i n i t -~R.2"8% lx 1 msy/~s,,- - - (2.5 X 2.5 ram)

A R = 3.6% "(1 X 1 ram) ! ~R=1"4%

C

/

0

/

.5 X 2.5 mm -,-i;-2-L..~X = 25/~ -d i (2.5: 2.5ram

(2.s x 2.5 mm).,t/"

r 1.4 7 - 4 - . - - - -

T

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.~X =

2s~,

(1 X 1 r a m )

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0

25 50 66 75 80 8S'.7 Percent of Resistor Penetration ( W 0 / ~ / 0 X 100)

N 88'.9 100

Figure

9.35 Trim characteristics of plunge cuts on one square resistor. (Courtesy DuPont Electronics.)

There are several ways of cutting resistors. Figure 9.36 illustrates six methods of trimming square or rectangular geometries. The single plunge cut is the fastest and the most often used for reasonable accuracy and stability. When greater initial precision is required the L cut is preferred. For maximum precision and stability, multiple cuts are recommended with a delay between the first and second cuts. The usual way to achieve the delay is to make all the first cuts on the circuit then all the second cuts. The first cut is made to 98% of value and the second cut to the desired cutoff value, usually the low tolerance of the final resistance value.

218

MATERIALS FOR ELECTRONIC PACKAGING

Plunge C u t "

Double Plunge Cut "L"-Cut. With Vernier '

"L"-Cut

t

!

I I

I I

Double "L"Shaped Cut

Serpentine Cut

I !

I I

ununU n Figure 9.36

Laser cutting techniques. (Courtesy DuPont Electronics.)

The process control variables of speed, power, and frequency can be related by defining a new term, cutting power. It encompasses all three process variables and allows us to achieve maximum stability by relating the experimentally determined cutting power to speed, power, and frequency: P = average beam power in Q-switched mode Q = pulse frequency S = trimming speed

P/S = linear energy density (LED) (in J/mm) Q/S = linear pulse density (LPD) in pulses/mm Cutting power(CP) = LED • LPD in J pulses/mm 2 In a study using high reliability thick film resistor compositions, low ohm material (100 ~/sq.) and high ohm material (10 k~/sq.) were cut at various average beam powers, pulse frequencies, and trimming speeds. A 1 mm 2 resistor was cut completely through and insulation resistance (IR) was measured at 200 V. It was determined that an initial IR greater than 2 G ~ was necessary to produce cuts which would be stable after 100 h storage. Results of the study are shown in Figures 9.37 and 9.38. For the 100 ~/sq. material, a cutting power of 10 J pulses/mm 2 is necessary to produce stable resistors. The 10 ~/sq. material requires a cutting power of 6 J pulses/mm 2. Using the recommended 120 pulses/mm for linear pulse density and the cutting power determined experimentally, it is possible to calculate the pulse frequency and the average power necessary for any desired trimming speeds. Tables 9.8 and 9.9 show examples of these calculations. Laser trimming of thick film resistors requires an understanding of the

Thick Film Technology 2 1 9

_.

-"

I I

Kerf I.R. <2 x 109~

0.4--

0.3 tr-

<~ 0.2 0-.9.

ximum % AR

Average% AR

0.1 0 1

Figure 9 . 3 7

10 Cutting power

100

Parametric trim study, 100 f~/sq. (Courtesy D u P o n t Electronics.)

0.7

-

0.6-

Kerf I.R. <2 x 10913 Maximum % AR

0.5-

\,

w <~ 0.4 .o o~

0.3 _ Average%hR

0.2 0.1

10 Cutting Power

1

Figure

9.38

Table 9 . 8

100

Parametric trim study, 10 kf~/sq. (Courtesy DuPont Electronics.)

Calculation of laser trimming parameters.

Power ( W ) Speed (mm/s) 10 50 100 500

Frequency (kHz)

CP = 6

CP = 10

C P = 15

1.2 6 12 60

0.5 2.5 5 25

0.83 4.15 8.3 41.5

1.25 6.25 12.5 62.5

Cutting power (J/s)= LPD x LED = Q/S x Pavg/S (1) Q (Hz)= 120S (2) Pavg(W) = 0.05S at cutting power of 6 0.083S at cutting power of 10 0.125S at cutting power of 15

220

MATERIALSFOR ELECTRONIC PACKAGING

Table 9.9

Calculation of laser trimming parameters. Power ( W)

Speed (mm/s)

Frequency (kHz)

CP = 6

CP = 10

C P = 15

0.4 2 4 20

1.5 7.5 15.0 75.0

2.5 12.5 25.0 125.0

3.8 18.8 37.5 187.5

10

50 100 500

Cutting power (J/s)= LPD x LED = Q/S x Pavg/S (1) O (Hz) = 40S (2) Pavg(W) = 0.15S at cutting power of 6 0.25S at cutting powder of 10 0.375S at cutting power of 15

trimming systems and resistor compositions presently available. The laser system must be capable of achieving the peak pulse power and pulse frequency required to remove material cleanly and the beam positioner must be capable of achieving the desired acceleration and running speeds. The substrate must be designed and processed to make the process feasible and the resistor compositions must be capable of performing to expectations. 9.8

Conclusion

This is by no means an exhaustive and comprehensive treatment of the subject of thick film materials and processing. Rather, it is an attempt to cover the subject in enough depth to give the reader an appreciation for the technology. Thick film technology continues to be a dynamic area of study and more information is generated daily. Thick film technology has definitely become an established method for efficiently producing cost-effective microelectronic circuitry. With the advances made to date, it is no longer so mysterious. The sophistication of thick film compositions and processing equipment continues to increase. Considerable knowledge has been obtained regarding the many interactions which occur during the processing of these complex, nonequilibrium systems. Degradation mechanisms are better understood. Outstanding stability over many years has been extensively documented. The technology, which was considered transient when first introduced, is withstanding the test of time.

Electroless Copper for Micropackaging and Ultralarge-Scale Integrated Circuit Applications Y. Shacham-Diamand

10.1

Introduction

Selective electroless copper deposition (SED) is used to produce well-defined metal lines with 100 nm line width, vertical sidewalls, and an aspect ratio greater than 4:1 (height:width). This technique can be fully planarized and, therefore, is suitable for multilevel metallization for both interchip and intrachip networking. Due to the high selectivity of the deposition technique it can be useful for micropackaging, packaging with minimum interconnect dimensions of 5-25 #m. Copper has long been the dominant conducting material in printed circuit boards. Recently, it has been investigated as a potential replacement for aluminum and aluminum alloys in very large-scale integration (VLSI). Copper can be used as the solderable material and as the conductor in multilayer copper-polyimide structures for VLSI packaging [1]. It can also be used as the interconnect and via contact filling material for integrated circuit applications [2]. Compared to aluminum, copper has lower specific resistivity, lower electromigration vulnerability, and the option of selective deposition technologies. Copper bulk conductivity is 1.67 • 10 - 6 ohm cm [3] and its thin film resistivity can be as low as 1.7 x 10 - 6 ohm cm using chemical vapor deposition (CVD) [4], 2.1 • 10 -6 ohm cm for electroless deposition [5], and 3.0 • 10 - 6 ohm cm for sputter deposition in argon plasma [5]. Copper lines are more suitable for deep submicrometer technologies where lower interconnect resistance and higher maximum current density are required to increase the operating speed of integrated circuits [4]. Interconnect reliability is a major concern as critical dimensions are scaled down. Failures due to the increasing current density in metal lines and contacts may limit aluminum based metallization for technologies with critical dimensions less than 0.35 ~m. The critical current for metallization is significantly higher for copper than aluminum. Recent results for sputtered copper indicate that it has 221

222

MATERIALS FOR ELECTRONIC PACKAGING

the minimum time to failure (MTTF) at 300~ as aluminum at 225~ for similar lines [6]. Electroless copper was also characterized; for example, 0.6 #m wide and 2 mm long electroless copper wires passivated with Si3N + studied at 215~ under J -- 8 • 106 A/cm 2 had a MTTF of 400 h and an activation energy of 0.85 + 0.05 eV. Copper technology has also its specific problems. Copper reacts with silicon, silicides, and other metals common to VLSI metallization and packaging [7-10]. Silicon dioxide, the common interlevel dielectric, is not a good barrier because copper is found to drift through it under high electric fields [11,12]. Copper mobility in thermally grown silicon dioxide was studied by electrical measurements and secondary ion mass spectroscopy (SIMS) profiling of MOS capacitors after bias thermal stressing (BTS) [11]. Copper segregates from the silicon dioxide into the silicon [11], diffuses very fast in silicon [11, 12-1 and forms deep energy-level centers in the semiconductor's forbidden energy gap [13]. The deep energy levels provide a mechanism for excess minority carriers to recombine with the majority carriers according to the Shockley-Read-Hall (SRH) [14] model. This model also suggests copper will induce generation-recombination (GR) leakage currents in p - n junctions and hence will jeopardize the performance of bipolar and field effect transistors (FETs). The deep-level enhanced recombination might decrease the minority carrier lifetime in the base of bipolar junction transistors, reducing the transistor current gain, ft. Copper-induced leakage currents limit the performance of quantum light detectors (e.g., charge coupled devices (CCD), charge injection devices (CID), photodiodes) that convert photon flux to charge packet or electric current. High concentrations of copper near the silicon-SiO2 interface can result in high concentrations of slow and fast surface states [11]. Copper also oxidizes at relatively low temperatures, at about 180~ [15]. The oxidation starts as a copper oxide nucleation-limited process and may be followed by a diffusion-limited mechanism, most probably due to the low diffusivity of oxygen in copper oxides. The oxidation of electroless copper was compared to that of evaporated copper [ 15-1that shows similar oxidizing behavior. The oxidation rate of electroless copper was found to be about 10 nm/s at 200~ and increased with temperature with an activation energy of 0.45 + 0.1 eV. Transmission electron microscopy (TEM) of the oxidized copper indicates the formation of CuO at low temperatures (below 200~ and Cu20 at higher temperatures. The problems of copper penetration into the intermetal dielectrics, oxidation, and reaction with silicon and other metals can be overcome with the use of barrier layers. For example, silicon nitride can be used as an insulating barrier [11], titanium nitride and titanium can be used as conductive barriers. However, the use of barriers may create other reliability hazards due to stress effects on the metal integrity during thermal processing and under electromigration stressing. Copper deposition and patterning is also critical. Copper layers can be evaporated, sputtered, or created by CVD from the gas phase [16], and deposited from the ionic solution by electroplating or electroless plating [17]. All these techniques can blanket-deposit a good quality thin film. Such deposition is typically combined with an underlying "glue" metal layer, like titanium or chromium, to improve copper adhesion to the interlevel dielectrics. Negative patterning of copper by wet etching may be used for wide lines, in

Elecfroless Copper for/Hicropackaging and Integrated Circuit Applications 2 2 3

the range of several micrometers and more. The resolution of wet etching is limited by the anisotropic nature of such a process. Submicrometer metal lines should be delineated by an anisotropic etching. Dry etching of copper in chlorine-based plasma has been demonstrated [18,19]. Due to the low vapor pressure of copper chlorides, the wafer temperature should exceed 350~ during the etch. In this high temperature range, copper may react with other components of the interconnect scheme and penetrate into the silicon substrate. Also, assuming a high temperature, reactive ion etching system for copper, etching is technologically feasible only if the etch mask can withstand the etching conditions. An alternative technique is to use plasma etching with metal organic compounds, the inverse of the copper deposition process [20]. Blanket-deposited copper can be positively patterned by liftoff to produce single lines as narrow as 100 nm and below. Liftoff has severe manufacturing problems when it comes to the formation of highly dense, multilevel metal networks. Improved liftoff techniques, such as LOPED [21], which use edge detection, may yield better interconnect quality but the trade-off is higher process complexity. In another approach, the metal is selectively deposited after the patterning; this allows optimization of patterning and deposition in two separate steps. CVD and electrolytic metal deposition methods can be selective; deposition may occur on one type of surface but not on another. High density interconnects for integrated circuits are made of conductors and insulators which are processed in a sequential order. There are many possible combinations for the layering order, as discussed in [21]. This chapter looks at two possible metallization schemes which require a selective and self-planarizing process such as electroless copper deposition [21-24]. In this process, copper ions in an aqueous solution are neutralized by electrons supplied by an appropriate reduction reaction in the liquid. The pioneering work of P.L. Pai et al. [21] demonstrated 0.8/~m wide copper lines made by electroless deposition using optical lithography and standard VLSI processing tools. The process presented here is based on similar principles and shows that electron beam lithography can be used to produce 0.1 ~m copper lines that might be useful for integrated circuit interconnection. The electroless copper deposition rate is a strong function of the pH of the solution. Typically, strong bases such as sodium hydroxide (NaOH) or potassium hydroxide (KOH) are used to provide the high concentration of O H ions. However, the presence of Na + or K + ions may be a hazard to the reliability of the integrated circuits. The alkaline ions may reach the silicon interface and affect device characteristics. It was found that tetramethylammonium hydroxide (TMAH) can replace the alkaline bases and be used to deposit copper films comparable to those prepared using sodium hydroxide [24]. This chapter presents basic models to describe the electrochemical processes occurring during deposition followed by a process description for submicrometer and micropackaging lines. Finally, it discusses measurement of some material and electrical properties of the copper lines, for example, forward recoil emission spectroscopy (FRES) is used to determine the hydrogen content in the metal, and a capacitance technique can be used to measure the penetration of copper into the interlevel dielectrics.

224

MATERIALS FOR ELECTRONIC PACKAGING

10.2 Electroless Copper Deposition In an electroless process copper is deposited from copper ions in solution following an electrochemical reaction without any external electrodes. In this reaction copper ions are neutralized by electrons from another chemical reaction. Electroless deposition is the result of two simultaneous processes. First, the generation of electrons by an anodic reaction: reducing agent, Ro -~ oxidized Ro + n electrons

(10.1)

Second the reduction of the metal ions, metal+": metal + " + m electrons --. metal ~

(10.2)

Thus, the overall reaction can be written as: metal + " + Ro ---, metal ~ + oxidized Ro

(10.3)

The reactions are reversible, they can take place in both directions. However, during deposition, the overpotential, the difference between the actual electrode potential and the equilibrium potential, becomes so large the reversible reactions are typically negligible compared to the forward oxidation (10.1) and deposition (10.2). The deposition kinetics were modeled by M. Paunovic [17-] using the mixed potential theory [25-27]. This theory assumes the electrochemical description of the total reaction (10.3) can be separated for the two processes, (10.1) and (10.2). Each reaction, when separated, may reach its detailed balance and achieve its equilibrium potential, Eeq,i , where the forward and reverse reaction rates are balanced. However, when the reactions are coupled and copper is being deposited, there is an electron transfer from the reducing agent to the metals and the reactions deviate from equilibrium. Since both reactions take place in the same medium they reach the same steady-state potential, Ess. The deviation from equilibrium establishes an overpotential: AEovp,i =

Ess

-

Eeq,i

(10.4)

which depends on the reaction rates. At steady state we assume the electron transfer rate to the metal ions is equal to the electron generation rate by the oxidation reaction of the reducing agent. This is true for depositions after the initial transient that depends on both the reaction thermodynamics and kinetics. But, the electron transfer rate is not necessarily constant with time because deposited metal and any precipitates can change the overall reaction rate. However, as long as the reaction rate changes are slow enough, the use of the concept of overpotential is meaningful. The forward reaction rate depends on the overpotential as:

Rif-Rioexp

-

~nqAEovp,i] ~-~ _J

(10.5)

where Rio is the equilibrium reaction rate, ~ is the transfer coefficient, n is the

Electroless Copper for/Hicropackaging and Integrated Circuit Applications 2 2 5

number of electrons transferred, q is the electron charge (1.602 • 10-x9 C), k is Boltzmann's constant (1.38 x 10 -23 eV C/K), and T is the temperature in kelvins. The reverse reaction rate is:

~176

Rio expl (1 -

'Ai~ .-- JtxiOl2 I/at/;?,.ifl - 1/at

(10.6)

and the net reaction rate is:

R=

Ri~ =

Rif-

Rill1 - ( R i o / R i f ) x/~

(10.7)

The above convention assumes the forward direction of a reaction is the reduction direction, so for the ith reaction the forward direction is: Ox~ + n~ electrons ~ Red~

(10.8)

Therefore the metal ion reduction (10.2) is mostly in the forward direction, (R 2 - Rf2), whereas the reducing agent oxidation is mostly in the reverse direction

(R1 = Rrl). The index 1 is referring to reaction (10.1) and the index 2 to reaction (10.2). Both reaction rates are equal at steady state, Rf2 = Rrx , or more explicitly: R2o exp -

~-~

j

Rio exp

kr

(10.9)

From equation (10.9) we can extract the steady-state potential: E~s =

(1 - ax)Eeq.X + ~2E~q,2 + - - In 1 -ai

nq

+a2

and the total deposition rate is: R = R o exp

[ q. ol

kT _]

(10.10)

(10.11)

where Ro and Eo are given by: Ro = (RloR2 ~2 1 ~- ~l)l/(1 -~l +~2) E 0 = ~2(1 - (~l)(Eeq'2 - Eeq'l) = (Xeq(Eeq,2 -- Eeq, 1 ).

(10.12a) (10.12b)

1-~x +~2

Eo can be interpreted as the effective activation energy of the deposition process when it is reaction limited. The effective activation energy depends on the equilibrium potentials of the reactions and on ~eq which is the harmonic average of the two transfer coefficients, ~2 and (1 - ~1). Note that the transfer coefficients can be a function of the temperature, the concentration of the various components, and the catalytic effects of the surfaces. Ro is the preexponential factor and is also a weighted average of Rox and Ro2. This model assumes the reactions are limited by thermodynamic principles

226

MATERIALS FOR ELECTRONIC PACKAGING

that relate reaction rates to the deviation from an equilibrium point. In real deposition systems there are other factors that may affect the deposition rate. One important factor is the mass transfer to the deposition site of the various species in solution, typically dominated by diffusion in the solution's neutral zones. It is also possible that built-in potential in the solution transition region near the deposition site may retard or enhance the mass transport of ionic species. Electroless deposition can therefore be electrochemically controlled, when the reaction rate is the dominant factor, or it can be mass transport controlled. In both cases the reaction rates depend upon the concentration of the reactants in solution. However, in the mass transport controlled case, the deposition rates also depend on the relative motion of the solution over the deposited surface. The deposition reaction may be followed or preceded by other reactions. It is also possible these reactions limit the deposition reaction by controlling the concentration of the initial reactant components or by limiting the formation rate for products. In this case we define the deposition reaction as chemically limited. The electroless deposition also depends on the catalytic properties of the deposition surfaces before the initial deposition, and of the deposited metal after the initial stage. The solutions that are described in this work deposit copper only on certain catalytic surfaces under normal conditions (i.e. deposition temperature Tdep < 80~ Typically palladium or gold are used for heterogeneous catalysis, where the reaction takes place at the catalyzed surfaces and not in the solution volume or on the uncatalyzed surfaces. The effect can change from initial metal catalysis to deposited metal catalysis, important for this work because we are concerned with palladium catalysis of a formaldehyde-based deposition. The effect of palladium catalysis on formaldehyde oxidation is known to be much less than the effects of deposited copper catalysis. Therefore the catalysis effect increases as copper is deposited and the deposition rate increases as the copper is formed. A typical electroless deposition solution contains other additives that are not directly involved in the deposition chemistry. For example, an electroless copper solution for submicrometer metal line formation contains a large amount of surfactant. This surfactant is required to ensure the complete wetting of the silicon dioxide and palladium surfaces. There are also complexing agents that affect the reaction rate and the crystalline structure of the deposited copper. These compounds and others affect the solution deposition reaction either directly, by affecting the kinetic parameters, or indirectly, by modifying the solution pH, by changing the electrode surface properties, or by changing the effective electrode area. Electroless deposition has been used intensively for printed circuit board (PCB) applications. It was used for interconnects and via contact filling, it was modified for VLSI technology for minimum line widths near 1 /~m. [28], and it was used for depositing copper lines with minimum line widths of around 100 nm [291. Further scaling-down is under investigation and it seems that selective copper deposition can produce even narrower lines where the minimum dimension is limited by lithographic capabilities. We now move on to copper nanolines, their integration into a network, and their reliability.

Eiectroless Copper for/Hicropackaging and Integrated Circuit Applications

10.3

227

C o p p e r N a n o l i n e Processing

C o p p e r lines with a m i n i m u m width of 100 nm [36] were fabricated by selective electroless copper deposition. Two different patterning a p p r o a c h e s are described here. The first produces standing lines over a surface and the second produces copper lines buried in the insulator (Fig. 10.1). The copper was deposited from an aqueous solution in a heated bath. First a stock solution was m a d e according to the information in Table 10.1 or Table 10.2. To activate the solution,

(Non-planar metal lines )

( Fully planar metal lines )

_m _m

s

Dielectric substrate w

Figure 10.1 10.1

Table

Dielectric substrate

Nonplanar (left) and fully planar electroless copper line processing procedures.

Electroless copper stock solution.

Compound

Quantity

pH

Comment

CuSO4.H20

25 g

5

Add to 1 liter of deionized water at 90~

EDTA

12.5 g

6

Not all dissolved

NaOH

40 g

~ 13

EDTA dissolved Light royal blue

KCN

10 mg

13

EDTA = Ethylenediaminetetraacetic acid NaOH = Sodium hydroxide KCN = potassium cyanide

Table 10.2

Compound

Alkaline-free electroless copper stock solution.

Quantity

pH

Comment

CuSO45H20

25 g

5

Add to deionized water at 90~

EDTA

12.5 g

6

Not all dissolved

TMAH

40 g

~ 13

EDTA dissolved Light royal blue

TEAC

15 mg

13

EDTA = Ethylendiaminetetraacetic acid TMAH = tetramethylammonium hydroxide TEAC = tetraethylammonium cyanide

228

MATERIALS FOR ELECTRONIC PACKAGING

Table 1 0 . 3

Ingredients added to activate the stock solution.

Compound

Quantity

HCOH (37%)

10 c m

Temperature

3

Comment

Room temperature

Add slowly Changes the pH

Surfactants

Variable

Room temperature

Hydroxide

Variable

20-22~

Adjust pH

the reducing agents and other additives were added just before deposition (Table 10.3). Typically, the hydroxide was added to adjust the pH to some calibrated value; this slightly affected the oxidation-reduction potential (ORP) as measured by the standard platinum electrode. Therefore it is possible to iterate and add small amounts of H C O H and hydroxide alternately to bring the solution to standard conditions. The pH of the solutions decreased with temperature, and Figure 10.2 shows this for an alkaline-containing solution (ELS) and an alkaline-free solution (AF-ELS). The pH versus 1/T curves have different slopes for the two solution types; they can be interpreted as two different activation energies associated with each reaction. The O R P is also a function of temperature, as shown in Figure 10.3 for an alkaline-free solution. This measurement was made during heating of the solution, when the temperature was increasing at a rate of about 4~ There is a very small change in the absolute value of the O R P for temperatures up to about 45-50~ The deposition process starts in this temperature range and copper is also deposited on the platinum electrode. This results in a fast increase in the absolute value of the negative O R P to about - 8 0 0 mV. Above that temperature the absolute value of the O R P increases with temperature.

14 r Q.

,//-~

13-

::~:::':~ ~,0.~.**'0

......

uL

,///pall/Ill/ .~..~r_

"I-

Q.

12=

~j-

!_ *

I.

D

*f"

0.028

,i".~...........

........:.... ,..::.~::~:::~:::fi'

~,r162 ~::fl

~,~,~.~ ,

" .

0.030

.

.

a. A F - E L S ,

initial

b. A F - E L S ,

final

c. E L S , i n i t i a l

.

0.032

.

0.034

1/T [K'll 10.2 pH versus lIT of two electroless copper deposition solutions: (a) alkaline-containing (see Table 10.1) and (b) alkaline-free solution (see Table 10.2). Fig.re

Electroless Copper for Micropackaging and Integrated Circuit Applications

229

-400

13

-450 12.5

-500

-550

=

-600

o

-650

0 Q

-700

11.5

-750 11

-800

0.003

0.0031

0.0032

0.0033

0.0034

0.0035

1/T [K ~1 Figure 10.3 Oxidation-reduction potential (ORP) versus 1/T of an alkaline-free electroless copper deposition solution.

The solution should be heated to the deposition temperature, between 50-70~ The solution temperature and its pH are monitored continuously using the Orion SA250 pH meter. This system is equipped with a solution temperature sensor and automatically compensates the pH reading at temperatures different than the calibration standard (21~ A standard pH 10 buffer solution was used to calibrate the meter before the deposition. The pH of the solution was adjusted to be about 13 at room temperature; it dropped to about 12.1-12.2 at 55~ and to 11.5-11.6 at 65~ The ORP of the solution was also monitored by a standard platinum electrode using an AgC1 (0.1 M) reference solution. Typical ORPs were around - 4 2 0 mV before deposition solution and - 8 0 0 mV after the copper was deposited on the platinum electrodes. The copper was removed from the platinum electrodes between depositions using FeC13-HC1 copper etchant. The solution deposited copper on palladium, gold, and copper but not on organic or inorganic insulators. To take advantage of this property, we devised the following two selective copper deposition processes.

10,3.1 Nonplanar Technique A thin film of the metal base was deposited on the substrate using a nonplanar technique (Fig. 10.1) [36]. The best results were achieved with Pd-Ti or Au-Cr bases, where the Pd and Au serve as the deposition seeding, and the Ti and Cr serves as the adhesion. The base metal was deposited by electron beam evaporation and the final thickness of the base metal was 30-50 nm. The wafer was coated with an electron beam resist, polymethyl methacrylate (PMMA), and cured at 170~ for 1 h. Several resist thicknesses were investigated, in the range 250-900 nm. The patterns were exposed by electron beam lithography using the Jeol 5DIIU

230

MATERIALS FOR ELECTRONIC PACKAGING

I

,...... ......................

ifi

,~iiiiii!ii ilii

i!ili!ii!i =.~iii!!:.~!:. iii: iil

~!ii;:

Figure 10.4

Nonplanar copper nanolines on a silicon nitride membrane, W = 100 nm, h - 400 nm, S = 400 nm. system. The electron energy was 50 keV and the dose was 200-300/,tC/cm 2. For the very fine lines, a single scan was used and the dose was 2-4 nC/cm. The resist was developed in a 1:1 mixture of methyl isobutyl ketone (MIBK) and isopropyl alcohol (IPA), rinsed in IPA, and dried. A short descum process in an oxygen plasma was applied to remove any resist residues on the exposed metal surfaces. The developed samples were inserted into the copper deposition bath and copper was deposited only on the exposed metal regions where the resist had been removed. Following deposition the remaining resist was removed by acetone or methylene chloride and the samples were rinsed in methanol followed by deionized water. Typical copper nanolines made by the nonplanar technique are presented in Figure 10.5. The substrate of the samples presented in Figure 10.4 is a thin silicon nitride membrane. In this picture we present 100 nm wide copper lines with aspect ratio of 4:1. Figure 10.5 presents similar results for a silicon substrate. Nonplanar electroless deposition produces lines with steep sidewalls. This is also observed in Figure 10.6 which demonstrates the ability of the nonplanar technique to define very narrow spaces. The upper surface topography of the nanolines was found to depend on the line width and the sample cleaning procedure. That surface roughness reflects the polycrystalline nature of the copper. The size of the copper grains in the 100 nm lines was of the same order as the line width. The grain size increases with the line width up to 400-500 nm, then remains constant with increasing line width; in some cases it even begins to decrease with increasing line width.

Electroless Copper for/Hicropackaging and Integrated Circuit Applications

Figure 10.5

Nonplanar

h - 400 nm, S -

Figure 10.6 S = 100 n m .

231

c o p p e r n a n o l i n e s o n a silicon s u b s t r a t e , W - 200 n m ,

100 n m .

Nonplanar

c o p p e r n a n o l i n e s o n silicon nitr ide , W = 4 0 0 n m , h = 4 0 0 n m ,

232

MATERIALS FOR ELECTRONIC PACKAGING

1O, 3 , 2 Fully Planar Technique

In the fully planar technique [36] the base metal is added after the patterning step. The exposure and development steps were identical to those described in the previous section. The electron beam resist was spin cast on a CVD oxide layer designed to be thicker than the expected copper layer thickness. After exposure, development, and descum the oxide was etched in an Applied Materials reactive ion etcher. Two gas systems were investigated, CF4 and a mixture of CHF3 and 02. The etching pressure was 30 mT, the power density was 0.25 W/cm 2 and the plasma bias referenced to the wafer was about - 6 0 0 V. The etch rate of SiO2 was about 30 nm/min and the trench depth was 80-300 nm. The electron beam resist erosion in CFr was too high for it to be useful in forming 100 nm wide trenches. Better results were achieved with C H F 3 and 02, where the etch selectivity of SiO 2 to P M M A is about 1. Using an initial 250 nm thick resist, 270 nm deep trenches with a minimum width down to 100 nm at the top were successfully made. Since the oxide to resist etch ratio under the conditions described was about 1, the deepest trench was limited by resist thickness. The lateral etch of the P M M A was between five and seven times slower than its vertical erosion, assuming the trench slope is only due to the vertical etch (Fig. 10.7). The base metal (15-25 nm of Au-Ti or Pd-Ti) was evaporated on the etched wafer and was lifted off. The wafer was slightly etched in O2 plasma to remove any scum and was inserted into the deposition bath. Copper was deposited on the base metal inside the trenches by the electroless deposition solution. Total deposition time ranged from 1 min to 1 h at 45-65~

....

Figure 10.7 Cross section of the 100 nm wide trench in Si02 before the base metal deposition step.

Electroless Copper for/Hicropackaging and/ntegrated Circuit Applications 233

Figure 10.8 Copper lines, 150 nm wide, after electroless copper deposition onto the trenches as shown in Figure 10.7.

The good aspect of slightly sloped sidewall trenches is they allowed copper deposition solution to penetrate all the trenches in the silicon dioxide and there were no observable wetting problems or trapped air bubbles near corners or trenches. On the other hand, the growth of copper from the sidewalls causes the copper filling of the trench to be thicker near the sidewalls than at the center. Figure 10.8 shows how the electroless copper was deposited to form fully buried nanolines. The upper topography of the lines shows a vague structure in the center. A closer look indicates a dip in the upper topography which separates the line into two halves. The next word is crucial to this sentence The nonplanar technique was also tested on submicrometer lines in the range 0.5-2/~m and on wider lines of 5/~m and more. Figure 10.9 shows 5 k~m wide, 4 /tm deep copper lines embedded in an SiO 2 insulator. Following the copper deposition the upper surface was mechanically polished to remove the copper structures on the shoulders of the trench. The cause of this problem is the same as the cause of the dip in the upper topography of the 100 nm lines. Base metal layers were deposited on the trench bottom but also on the trench sidewalls. The seeding of the copper on the sidewalls resulted in copper growth, as shown in Figure 10.10. This problem can be solved in the future by forming an overhang resist structure before the base metal deposition.

10.4 Electrical Properties The electrical properties of electroless copper were measured on both uniformly deposited layers and on patterned lines. The sheet resistance, R~, of electroless copper was measured by four-point probe on the uniform layers. The

234

MATERIALS FOR ELECTRONIC PACKAGING

,99149 9149149

9 9

.....

9:.., :, .:

~.:..3

Figure 10.9

Fully planar copper lines embedded in SiO2 after mechanical polishing, nominally W = 5 ILm, H = 5 #m and S = 5 l,m.

Copper

Growth

~.:~,~~..~~:~i~,i,~zi.i~!:i,~i~,.t,.:.;l !.~.~,~.~:~,~,,~:.:~.~!..~..~1 !~ii~, ~i ~,~'eli .~.~~,~,~. !i:~.:':~:!~!i .!1 ,~:~:i~,~.i~i,17~:~ayer:. ,. ~m:imet~..~ .~..i.i..ili:,~:i.i~:

I,

(a) Normal

9

:.': :"

Growth

Shoulder

';~:.i.i:.::.11'. '.:i.i '~ '~ " .

i::~:~.E:,~_i ~:~.i~;i:,.:~,.':~: : ::::~ ,~.,:,,~..:. "Z.:,.:, ..... :...~.....~, (b) Figure 10.10 Fully planar copper deposition: (a) ideal structure; (b) structure affected by sidewall seeding.

Electroless Copper for A4icropackaging and Integrated Circuit Applications 2 3 5

specific resistance of the uniformly deposited copper was found to be about 2.1 _+ 0.2 l~fl cm given the layer thickness, d, determined by an Alpha-step profilometer. The resistivity of patterned electroless copper lines was measured by the van der Pauw technique [30]. In both cases the copper specific resistivity was 2.1 +_ 0.3/~fl cm. That value of resistivity was characteristic for copper deposited from both alkaline-free and alkaline-containing baths. Metal oxide semiconductor (MOS) devices with Cu-Pd-Ti-SiO2-Si were tested under bias thermal stress up to 350~ and 1 MV/cm. The results indicate there is no sodium in the system, since we used an alkaline-free solution. And titanium was a good barrier, no copper penetration was detected even after 24 h of stress.

10.5

Electroless C o p p e r O x i d a t i o n

The layer resistivity was measured as a function of time under dry room ambient (Fig. 10.11). SEM and TEM studies of the lines suggest the increase in resistance of the layers is due to the growth of copper oxides [36]. The oxidation rate increases as a function of the temperature. The sheet resistance of those copper layers, Rs(t), is assumed to be proportional to the remaining unoxidized copper:

Rs(t ) Rs(t = 0 )

d(t = O)

(10.13)

d(t)

where Rs(t = 0) is the initial sheet resistance, d(t = 0) is the initial thickness, and d(t) is the copper thickness at time t. The copper oxide thickness, dox(t), is

0.5 Electroless Cu on Pd annealed in air 0.0

0000 rl,rY

-0.5

o

I

vc- -1.0 -1.5 -2.0

o

212o0

,,"~.~'~"~225~ +~t~\250oc

7

8 In[mime(sec)]

9

10

Figure 10.1 1 Normalized resistance of electroless copper film as a function of the annealing time in dry air.

236

MATERIALS FOR ELECTRONIC PACKAGING

20

15 0

o/

~10 oi

,

0.0

,

,

I

~

0.2

~

,

I

0.4

,

,

,

I

,

,

0.6

TIME (sec.) Figure

Xr

,

I

0.8

,

,

,

1.0

xlo'

1 0 . 1 2 Log(Xr) versus log(time) for electroless copper (see Figure 10.11). - (1 - 1/R) where R is the normalized resistance.

proportional to the copper thickness that is oxidized: dox(t) = K[d(t = 0 ) - d(t)]

(10.14)

dox(t) can be normalized and described as a function of the measured resistance: dox(t) = K I I _ d(t = O)

d(t))1 =K[1 Rs(t=0) 1 d(t Z O Rs(t )

(10.15)

Figure 10.12 plots l o g l o [ 1 - Rs(t = O)/Rs(t)] versus logxo(t). The graph is linear with time until most of the copper is oxidized. Only at the lowest temperature, 200~ does the oxidation become nonlinear with time and behaves as t p where p is about 0.5. This behavior is also found to be characteristic for sputtered copper [15]. The oxidation rate increases with temperature at an exponential rate, with an activation energy of 1.2 eV. The oxidation rate was the same order of magnitude for the sputter-deposited copper. At lower temperatures, below 200~ the copper oxide thickness initially increases linearly with time and becomes a function of t 1/2 for longer times until all the copper is fully oxidized. Therefore we may assume the initial rate-dominating factor of the copper oxidation is the nucleation rate of copper oxide. At lower temperatures the nuclei may cover the surface and the process becomes limited by the diffusion of oxygen in the copper oxide film.

10.6 Hydrogen in Electroless Copper Electroless copper film may include hydrogen that evolves during the electrochemical reaction [31-34]. The hydrogen concentration in the copper was found to be 0.05-1.3 at%. Gas incorporation could be in H 2 form or as a molecule

Electro/ess Copper for Micropackaging and Integrated Circuit Applications

237

such as HzO; it forms voids that lower the metal ductility because they coalesce as cracks during stressing. And gas pressure in the void can also contribute to poor film ductility; hydrogen affects the metal microstructure by inhibiting grain growth and making it more brittle. It is suspected the hydrogen content in the copper may affect the reliability of the copper metallization for micropackaging and integrated circuit applications. Therefore, a technique to measure hydrogen in copper is desirable for process monitoring. The hydrogen content in electroless copper was measured by forward recoil emission spectroscopy (FRES) [3]. Hydrogen atoms were ejected from copper layers bombarded by helium ions that hit the surface at a shallow angle. The number of recoils depends on the hydrogen concentration and their energy depends on their location in the film. The hydrogen concentration was measured for electroless copper grown on two substrates: Pd-Cr-SiO2-Si and Au-Ti-SiO2-Si. The thickness of the seed metal layers is minimal, 5-10 nm, and the oxide thickness is 100-300 nm. The palladium substrate has a catalytic effect on the hydrogen, generates atomic hydrogen, and prevents bubble formation. Gold does not have such a catalytic effect so the hydrogen will appear as a molecule near the metal. On the other hand, palladium adsorbs a large amount of hydrogen and can serve as a source

Energy [MeV] 0.6 2501

'

I

0.8 '

'

'

'

1.0 '

'

'

I

1.2 '

'

'

1.4

I

'

'

'

I

1.6 '

'

'

I

'

~E = 3.0 M e V conv=

200

6.2, 210 (est.)

~ f f i 1.18 O = -70 ~

150

o

= 153 ~ Straggle = 7

o

F W H M = 60

-

lOO

o

u

i

O

o

D in SiO2

5~F

.i.si

:

[.inCu

P ~ - - T - 150 200

250

Channel Figure 10.13

FRES spectra of deuterium recoil from electroless copper.

300

238

MATERIALS FOR ELECTRONIC PACKAGING

Energy [MeV] 40

1.5

1.55

1.60

1,65 E = 3.0 MeV c o n v = 6.2, 210 (est.l f l = 1.18

30

Q = -70" Y = 153" Straggle = 7

O

0.016 D in Cu

20

10

F W H M - 60

No D in Cu 9

275

280

285

290

9

9

295

300

Channel Figure 1 0 . 1 4 Magnification of channels 275-300 of Figure 10.13. This energy distribution indicates the presence of deuterium in the metal layer.

for hydrogen that may diffuse into the copper layer. Hydrogen can also be incorporated into the copper layer by charging electrolytically in a D 2 0 -k- D z S O 4 (0.05 M) at 2 mA/cm 2 for 90 min. A typical FRES spectrum of recoiled hydrogen atoms due to helium atoms that hit the layer at a shallow angle of 7~ is shown in Figure 10.13. That sample had Cu (63 nm)-Pd (15 nm)-Cr (4.5 nm)-SiO2 (580 nm)-Si and was electrolytically charged in D2SO4 (0.05 M). This spectrum was fit to a model that assumes 1% Hz and 1.6% D2 in the copper film, 20% HE and 55% D2 in the palladium, 3% H2 and 21% D 2 in the SIO2, and none in the chromium. The hydrogen and deuterium peaks due to the palladium and oxide layers were much stronger than that due to the copper. Figure 10.14 shows the spectrum of the deuterium atoms that recoiled from the copper. Comparing it to the model we obtain a better fit by assuming 1.6% D2 in the copper film. Results on uncharged electroless copper film indicated that layers on Pd-Cr have about 0.3% D 2 whereas layers on Au-Ti have only 0.15% D2. These layers were grown in a deuterated formaldehyde (DCOD) so the deuterium is definitely from the electroless deposition reaction, indicating the reliability of electroless

Electroless Copper for/Hicropockoging and Integrated Circuit Applications 2 3 9

copper metallization may depend on the type of seeding metal. The FRES technique was found to be simple to use with about 0.05% atomic resolution. Not only does it yield depth profiles of hydrogen, it can be used for layers as thin as 68 nm, it is nondestructive and it provides on-wafer characterization and process monitoring. More information on hydrogen in copper and the FRES technique can be found in the literature [35,36].

10.7 Conclusions Electroless copper is a highly selective process that can be used for micropackaging and integrated circuit applications. Copper lines, down to 100 nm wide, can be deposited with a thin film specific resistivity of around 2.1 x 10 - 6 ohm cm. A fully planarized technique has been demonstrated, both for micropackaging and for ULSI. This technique is especially good for multilevel metallization, where the metal lines are embedded in the interlevel dielectric and the via contacts are made by the same positive patterning procedure as the lines themselves. The electroless copper includes hydrogen characterized by FRES, a technique that offers simple, nondestructive monitoring and analysis. Electroless copper was found to be oxidized at a significant rate near 200~ The oxidation is characterized by a random nucleation of copper oxides that decreases the copper line conductivity, therefore copper lines should be passivated to block the interaction with oxygen or water. The copper can also be isolated from the substrate by its own base layer. For example, a 7.5 nm layer of titanium was found to be a good barrier against copper penetration of silicon dioxide. In summary, the electroless copper process offers an economical solution to the selective deposition of good quality copper for interconnecting very narrow lines and for micropackaging. The success of this technique depends upon the development of a uniform and large area deposition system that can produce the same quality material silicon wafers of 8 in. or larger.

Acknowledgments The work was supported by the Semiconductor Research Corporation, grant #91-SC-069. Thanks to Dr. R. Bielski, the Chemistry Department, Cornell University, for preparing the deposition solutions. Thanks to Mr. R. Tiberio for the electron beam lithography. Thanks to the staff of the National Nanofabrication Facility at Cornell University. Thanks to Dr. R. Wistrom, the Department of Material Science and Engineering for his FRES analysis. Thanks to Mr. Jian Li for his help with the oxidation study and to Professor J.W. Mayer, the director of the Silicon Based Nanoelectronics Program at Cornell University. Thanks to Mr. A. Dedhia for his help with the bias-stress measurements, the electromigration testing, and with the manuscript. Finally, thanks to Mr. K. Bhaumik for proofreading the manuscript.

240

MATERIALS FOR ELECTRONIC PACKAGING

References

1. L.J. Freed, J.S. Lechaton, J.S. Logan, G. Paal, and P.A. Totta, IBM J. R&D 23, 362 (1982). 2. P.L.Pai and C.H. Ting, IEEE Electron. Dev. Lett. 10, 424 (1989). 3. J.W. Mayer and S.S. Lau, Electronic Materials Science: for Integrated Circuits in Si and GaAs, Macmillan, New York, 1990. 4. A. Kaloyeros et al., in Proc. ULSI Metallization Conf. AT&T, Murray Hill, 1991, 111-112. 5. J. Li, Y. Shacham-Diamand, J. Mayer, and E.G. Colgan, Proc. VLSI Metallization for Integrated Circuits (VMIC) Conf. San Jose, 1991. 6. A. Kaloyeros et al. in Proc. Adv. Metallization for ULSI Conf., AT&T, Murray Hill, 1991. 7. S. Russsell, J. Li, A. Khan, P. Revesz, and J.W. Mayer, Mater. Res. Soc. Syrup. Proc. 15g (1990). 8. J. Li, S.Q. Wang, J.W. Mayer, and K.N. Tu, Phys. Rev. B 39, 12367 (1989). 9. J.W. Cahn, J.D. Pan, and R.W. Balluffi, Scripta Met. 32, 29 (1984). 10. J. Li, Y. Shacham-Diamand, J.W. Mayer, and E.G. Golgan, Proc. VLSI Metallization and Interconnect Conf. ( VMIC), San Jose, 1991. 11. Y. Shacham, A. Dedhia, D. Hofftetterand, and J.W. Oldham, Proc. VLSI Metallization and Interconnect Conf. ( VMIC), San Jose, 1991. 12. J.D. McBrayer. Ph.D. Thesis, Stanford University CA, 1984. 13. A.G. Milnes, Deep Impurities in Semiconductors, Wiley New York, 1973. 14. W. Shockley and Read, Phys. Rev. 87, 835 (1952). 15. Y. Shacham-Diamand, J. Li, J.O. Olowlafe, S. Russel, Y. Tamou, and J.W. Mayer, Proc. 9th Biennial University Government Industry Microelectronics Syrup. ( UGIM) 1991, Melbourne, Florida, 1991. 16. A. Kaloyeros, A. Feng, J. Garhart, K.C. Brooks, A.K. Ghosh, A.N. Saxena, and L. Buehrs, J. Electronic Materials, 271 (May 1990). 17. M. Paunovic, Plating, 1161 (Nov. 1968). 18. G.C. Schwartz and P.U. Schaible, J. Electrochem. Soc. 130, 1777 (1983). 19. K. Ohno, M. Sato, and Y. Anita, Jpn. J. of Appl. Phys. 28, L1070 (1989). 20. Proc. ULSI Metallization Conf. AT&T, Murray Hill, 1991. 21. P.L. Pai, Ph.D Thesis, University of California, Berkeley CA, 1987. 22. J. Duffy. L. Pearson, and M. Paunovic, J. Electrochem. Soc., 130, 876 (1983). 23. See papers in IBM J. R&D 28 (1984) dedicated to materials and packaging. 24. Y. Shacham-Diamand and R. Bielski, Alkaline-free electroless deposition, U.S. Patent 5,240,497 (1993). 25. M. Saito, J. Metal Finish. Soc. Jpn, 17, 14 (1966). 26. C. Wagner and W. Traud, Z. Electrochem, 44, 391 (1938). 27. S. Haruyama and Izumi Ohno, in Proc. Symp. Electroless Deposition of Metals and Alloys, edited by M. Paunovic and I. Ohno, Electrochemical Society, 1988, Vol. 88-12, p. 20. 28. C. Ting, in Proc. Symp. Electroless Deposition of Metals and Alloys, edited by M. Paunovic and I. Ohno, Electrochemical Society, 1988, Vol. 88-12, p. 244. 29. Y. Shacham-Diamand, J. Micromech. Microen9. 1, 66(1991). 30. D. Schroder, Semiconductor Measurement Techniques, Wiley, New York, 1990. 31. S. Nakahara, C.Y. Mak and Y. Okinada, J. Electrochem. Soc. 138, 1421 (1991). 32. S. Nakahara, J. Electrochem. Soc. 136, 1120 (1989). 33. S. Nakahara and Y. Okinaka, Acta Metall. 31, 713 (1983). 34. Y. Okinaka and H.K. Stratchil, J. Electrochem. Soc. 133, 2608 (1986). 35. R. Wistrom, Ph.D. Thesis, Cornell University, 1991. 36. Y. Shacham-Diamand, private communication.

11

Vacuum Metallization for Integrated Circuit Packages K. J. Blackwell, P. C. Chen, A. R. Knoll, J. J Cuomo

1 1.1

Introduction

This chapter is intended to introduce the reader to some of the vacuum processes presently being used by the electronics packaging industry. It is not intended to give the reader a thorough knowledge of vacuum processing. There are very good books that give more detail on vacuum fundamentals, vacuum process fundamentals, and vacuum equipment. Two electronic packages currently utilize vacuum metaUization: ceramic packages and tape automated bonding (TAB). Plastic flat packs, hybrid flexible cables and other packaging schemes are beginning to take advantage of vacuum processing. Ceramic packages conventionally utilize sputtering or evaporation for depositing 8 /~m (0.0003 mil) thick copper coatings for circuitry. TAB uses sputtering to deposit a thin layer of copper to provide an electrical path for subsequent plating up to 35.5 nm thick copper (1.4 mils). In both cases, a thin layer of chromium is deposited onto the ceramic or polyimide surface just before copper deposition. The chromium is a bonding layer between the substrate surfaces; the copper acts as an adhesive layer and a corrosion inhibitor. The ceramic and the polyimide are electrical insulators but they also mechanically couple the circuit board and the silicon chip. To provide reliable connections these packages attempt to reduce thermomechanical stresses between the chip and the board connections. In the case of the ceramic, it is common to deposit a second layer of chromium on top of the copper. This top chrome layer is used as a solder mask. Figure 11.1(a) shows a photo of a ceramic substrate and Figure 11. l(b) shows a schematic cross section. Figure 11.2(a) shows a photo of a TAB and Figure 11.2(b) shows a cross section of the seed layer. 1 1 . 2 V a c u u m Processes

Vacuum deposited materials cover a large range of commercial and industrial applications. In the electronics industry, vacuum process are used to deposit the metallurgies for semiconductor circuits and for etching these coatings into fine-line 241

242

MATERIALSFOR ELECTRONIC PACKAGING

Figure 1 1 .l(a)

Metallized ceramic substrate.

CHROME - 8 0 0 ANGSTROMS COPPER - 8 0 , 0 0 0 ANGSTROMS CHROME - 8 0 0 ANGSTROMS

CERAMIC - 2 mm

I

Figure 11.1(b)

Cross section of a metallized ceramic substrate.

Vacuum/Hetallization for Integrated Circuit Packages

Figure 1 1.2(a)

A TAB chip carrier.

COPPER CHROME

- 6,000 - 250

POLYIMIDE

CHROME i

Figure 1 1.2(b)

243

COPPER

ANGSTROMS ANGSTROMS

- 50

- 250 - 6,000

MICRONS

ANGSTROMS ANGSTROMS

Cross section of a plating seed layer.

wiring with micrometer widths. Electronic packaging fans out the circuitry from these minute dimensions to widths compatible with electrical connectors and printed circuit boards. Most electronics companies are using some form of vacuum processing. 11.2.1

Vacuum Pressure

Atmospheric pressure is 760 mm Hg or 760 torr at sea level. The pressure at 10 km (32 800 ft) above the earth is 210 torr; this is an altitude for typical commercial air travel. At 90 km (295 200 ft), the pressure is 1.9 x 10 -3 torr. At 130 km (426400

244

MATERIALS FOR ELECTRONIC PACKAGING

INLET

~,~] GAS FROM VACUUM CHAMBER

~_~ROOTS BLOWER ~,

OIL

,== !

AUST

GAS ~

Figure 1 1.3

Mechanical rotary pump.

ft), the pressure is 1.5 • 10 -5 torr [1], comparable to the pressure outside a space station. The two basic vacuum processes used in electronic packaging are etching and deposition. Polymer or metal etching is performed between 5 • 10-1 and 5 • 10-3 torr. Deposition processes are performed at pressures between 10-3 and 10 - 6 torr. Attaining these pressures requires special pumping configurations. Since electronic packages range from large area circuit boards to 35 mm ceramic substrates, the vacuum chamber sizes vary greatly. Vacuum chambers can be as small as a desk or as large as a two-story building. Air and water vapor are pumped from these chambers by various methods but most commonly a roughing pump is followed by a midrange pump (roots blower) then a high vacuum pump. The roughing pump can be a mechanical rotary pump (Figure 11.3) with a roots blower located between the mechanical pump and the vacuum chamber. The mechanical pump evacuates the chamber to around 1 torr. The roots blower engages and continues evacuation down to 10-1 torr. At this pressure, the high vacuum pump is engaged and continues to pump the chamber down to some base pressure between 10- 4 and 10- 6 torr. I 1 . 2 . 2 Bose Pressure

The base pressure is the lowest pressure the system will reach in a given time. The process cleanness determines this pressure. For deposition processing, the base pressure is usually between 10 -6 and 5 x 10 -6 torr, but etching processes

Vacuum A4efallizafion for Integrated Circuit Packages 245

don't require as clean a chamber, and base pressures are normally 10 -3 torr. The base pressure is governed by minute vacuum leaks in the system seals, by the amount of residual water vapor condensed on the walls of the chamber, by the size of the chamber, its materials of construction, and by outgassing of the substrate. For efficiency, the engineer must balance pumpdown time to reach base pressure with the actual requirement for the end product.

! 1 . 2 . 3 Residual Gases a n d Leaks

An evacuated vessel will contain some small amount of residual air and water vapor. Depending on the process, the concentration and amount of residual gases can be very difficult to control. Water vapor desorbing from metal surfaces or air leaking into the chamber can severely contaminate metal coatings. Virtual leaks, such as threads on a bolt, are sources of gas but are not actual conductances between the vacuum and the atmosphere. Nevertheless, they are still a source of undesired gas. Substrates themselves commonly contain absorbed gases such as water. Polyimides can hold 2-4 % of their bulk weight in absorbed water. When evacuated, this water diffuses from the plastic. The time required to reach base pressure increases due to this additional gas load. Preheating the vacuum chamber and the substrate can reduce the pumping time significantly. Therefore, the residual gases can come from many sources other than air. Fingerprints and residual vacuum pump oil provide oil vapors. Cleaning solvents vaporize. Even the coating materials themselves, such as metals used for evaporation, can be a source of gases. Cleanliness is imperative when using vacuum equipment.

1 1 . 2 . 4 Gas Flow u n d e r Various Pressure Regimes

The three basic gas flows in vacuum processes are viscous, transition, and molecular. These flow regimes vary over a range of pressures, depending on the diameter of the conducting dimensions. In viscous flow, gas atoms and molecules are very close together, so collisions dominate the flow behavior. Atoms move in a stream, bumping each other along. This internal friction can be laminar, where atoms move parallel to each other, or turbulent, whereatoms flow in various directions, such as around obstructions. In transition flow (Knudsen flow), atoms move in a complex pattern, a combination of viscous and molecular flow. In molecular flow, there is a low probability of one gas atom colliding with another gas atom. Most interactions between gas atoms are with the walls of the chamber. An understanding of gas flows is important. In a large chamber, nonuniform flow patterns could be found across large substrates where the process is in a viscous flow regime. This could result in a thickness variation, for example, in a copper coating from one side of the substrate to the other. A thickness variation would drastically affect the resistivity and the quality of the product.

246

MATERIALS FOR ELECTRONIC PACKAGING

1 1.2.5 Vacuum Pumps

There are three categories of pumps. The first is the mechanical pump referred to as a roughing pump. This provides vacuum pressures between atmosphere pressure and 0.1 torr. The second is another mechanical pump called a blower, which provides very high gas pumping speeds and typically is used between 10 and 0.1 torr. The third is the high vacuum pump, which provides pressures between 0.1 and 10-1 o torr. Currently, the three most widely used high vacuum pumps are the cryopump (cryo), the oil diffusion pump, and the turbopump. The cryo is a cryogenically cooled pump that traps atoms and molecules by condensation. It is a very good pump for reactive gas but does not pump some inert gases, such as helium, as well as the other two types. Oil diffusion pumps operate by creating an oil vapor envelope and trapping gas atoms once they pass through it. The oil vapor leaves a jet at a very high velocity and at a downward angle. Gas atoms, which might diffuse into the pump and collide with an oil atom, are driven toward the bottom of the pump. Three envelopes are normally staggered from top to bottom inside the pump so there is a low probability of a gas atom diffusing back out the top of the pump. A roughing pump is connected to the base of the pump to remove the trapped atoms. The turbomolecular pump is a turbine. Blades inside the pump rotate at an extremely high velocity. Any gas atoms that diffuse into the top of the pump and collide with the blades are forced downward. There are multiple sets of blades located at various positions from top to bottom, and as before, there is a low probability of a trapped gas atom diffusing out the top of the pump. Again, a roughing pump is connected to the base of the turbopump to remove trapped atoms and molecules.

1 1.3 Coating Vessels Vacuum metallization can be performed by batch processing, in-line processing, or roll processing. In batch processing, substrates for coating are loaded into the system and coated all at once. After coating is complete, all substrates are removed and another batch is coated. Evaporation of chrome-copper-chrome onto ceramics, discussed later, is performed using this type of processing. In-line processing is more commonly used with sputtering, discussed later. The in-line method normally consists of a set of vacuum chambers separated by gate valves. Each valve opens to allow substrates to enter and then closes for processing. In-line processing allows many processes in one system. Figure 11.4 shows a system in which substrates are evacuated, surface treated, coated and then vented without cross-contamination. The load-lock and vent chambers maintain the vacuum in the processing chambers; this reduces contamination and processing time. Once the substrates are evacuated, they move from the load-lock chamber into the surface treatment or etch module, where the surface can be treated to enhance coating-to-substrate adhesion or where etching can be performed to

Vacuum Metallization for Integrated Circuit Packages 2 4 7

Figure 11.4

In-line sputtering system.

remove material. After the substrates have been processed, they are transferred into the coating chamber. After coating, they are moved into the vent chamber, where they are returned to atmospheric pressure. Conventional roll coaters can be either sputtering or evaporation systems and are being manufactured as batch coaters. Roll coaters are covered later in this chapter.

1 1.4 Physical Vapor Deposition by Evaporation Physical vapor deposition (PVD) is beginning to find its way into the production of flexible cables and even plastic flat packs. The two most common PVD processes are DC planar magnetron sputtering and electron beam evaporation. Sputtering is more commonly used to coat rolls of plastics with thin copper layers for use as plating strike layers in TAB and thick blanket layers of copper on ceramics. Evaportion is more commonly found in the metallization of ceramics. I 1.4. I H i s t o r y

The earliest records of thin layer deposition appear to be those of Faraday in 1857 [3]. Faraday was experimenting with very thin layers by explosively evaporating metal wires in an inert atmosphere. Film thickness is very difficult to control using this method. In 1912, Pohl and Pringsheim [3] evaporated metals at vacuum pressures. This provided conditions for material property control such as thickness and purity. Edison had been given credit for discovering vacuum evaporation, since he had observed carbon deposits on the glass walls of incandescent carbon lamps, but little literature supports this [3]. By heating materials at low pressures, it is possible to cause a material to change phase, from a solid to liquid then into a gas. In the electronic packaging

248

MATERIALS FOR ELECTRONIC PACKAGING

industry, it is common to heat copper to its boiling point under vacuum. The evaporating atoms of copper leave the surface of the molten pool and traverse space until they impinge on a surface of lower temperature, where they condense to form a film. Similarly, water condenses from steam onto a bathroom mirror. Most work involving evaporation during the nineteenth and early twentieth centuries was in the area of research. Toward the middle of the twentieth century, the capability of vacuum equipment had evolved to a point where vacuum coating was implemented as a manufacturing process. As the twenty-first century approaches, vacuum evaporation is commonly used in industries, ranging from decorative coatings such as bottle labels to multiple layers in the fabrication of integrated circuit (IC) chips. Thin metals are commonly deposited onto rolls of plastics and papers for thin film capacitors. Millimeter thick ceramic blocks are coated with copper, circuitized and used as IC packages. Thin layers of chromium are evaporated onto plastic headlamp lenses. The food industry is using thin metal films for candy wrappers and metal oxides for microwaveable food packaging. Antireflection coatings are used to coat review mirrors, eyeglasses, sunglasses, lenses for microscopes, telescopes, and cameras. There is an extensive list of evaporated coatings, many of them used in electronic packaging. 1 1.4.2 Background

Evaporation is performed at pressures nine orders of magnitude lower than atmospheric pressure. In this low pressure range, atoms travel long distances before colliding with other atoms. The material to be evaporated is heated to a temperature where its vapor pressure is high enough to allow atoms to enter the vapor phase. Once an atom leaves the surface of the melt, it travels in a line of sight from that surface with little or no collisions. When the atom reaches a surface at a lower energy, for instance at room temperature, it condenses and forms a film on that surface. The properties of the film are similar to the properties of the original solid. 1 1.4.3

V a c u u m a n d Gas A t o m M e a n Free Path

The vacuum levels used in evaporation typically range between 5 • 10 -4 and 5 x 10 -6 torr. In this range, the mean free path of gas atoms and molecules is on the order of 10-100 m. Mean free path is the average distance traveled by a gas atom between collisions with other gas atoms [5] and is calculated from )~ = k T / P y r , 6 2 s 1/2

(11.1)

where 2 is the mean free path, k is Boltzmann's constant, T is temperature (K), P is pressure, and s is the diameter of the molecule or atom of the gas. It is clear from equation (11.1) that the mean free path depends on atom size and thus is different for various gases. The distance between the source of evaporant and the surface to be coated is to prevent scattering of atoms. Also, a lower background pressure produces a clean environment at the condensing surface, preserving the integrity and cleanness of the material being deposited. Therefore, it is important to

Vacuum A4etallization for Integrated Circuit Packages 2 4 9

understand the nature of the residual gas in the vacuum chamber and to maintain the lowest possible pressure during evaporation of pure materials. 1 1.4.4 Impingement Flux

The rate at which atoms and molecules strike a surface has two very important aspects. The higher the arrival rate of coating atoms, the faster a film is deposited and the shorter the process time. But impingement of nonevaporant gas atoms can contaminate the film if their flux is similar to the coating rate. An approximate impingement rate per unit area and per unit time [5] is given by N =

P

(2rcmkT) x/2

(11.2)

where N is the number of molecules, P is the gas pressure, k is Boltzmann's constant, T is temperature and m is the mass of the molecule. The ratio of N for various gases, such as residual water vapor, nitrogen, and oxygen, to the coating atom deposition rate can be helpful when setting up a process. It can be adjusted by decreasing the system base pressure, reducing system leak rates, and increasing the deposition rate. Increasing the deposition rate not only changes this ratio but also provides a process known as gettering. Gettering occurs when coating atoms react with a residual gas atom or molecule and the combination condenses on a chamber surface. This results in a decrease in the number of residual gas atoms and often there is an observable pressure decrease after the initial deposition. In the evaporation of aluminum in roll coating, stray evaporant commonly getters oxygen, forming aluminum oxide deposits on the vacuum vessel walls, thereby reducing the residual oxygen gas pressure. Aluminum coatings are much purer when the deposition rate is high. 1 1,4,5 Deposition Rate

The arrival rate of coating atoms governs the process time. For economy, the process should be as short as possible so deposition rates are normally set as high as possible. The simplest expression for calculating the deposition rate is to divide coating thickness by coating time. For a dynamic coating system, this becomes slightly more complicated because coating time is a function of the substrate speed and the length of the deposition zone. Figure 11.5 shows a cross section of a roll coating evaporator used to deposit copper onto plastic. The plastic passes the window at a constant speed, with a set zone width, and a constant deposition rate. All process parameters are set to provide a desired copper thickness. The simple equation is deposition rate =

thickness • substrate (roll) speed zone length x number of zones

(11.3)

Deposition rate is a function of the amount of energy supplied to the evaporation

250

MATERIALSFOR ELECTRONIC PACKAGING

View

To Vacuum P~mp

_ [

.

. ~

.

.

.

.

Zone

Figure 1 1.5

Cross section of a roll coating evaporator.

source (this directly relates to the evaporant temperature), the material being evaporated, the source-to-substrate distance, and the vacuum system pressure.

! 1.4.6 Coating Distribution and Uniformity Evaporating atoms leave a source and arrive at a surface according to Knudsen's cosine law of emission, which is a gas kinetic analogy to Lambert's law of illumination [3]. It is important to understand this phenomenon in order to manipulate surfaces and sources for engineering coating thickness and distribution. Consider three vapor sources used in industry. The first is a point source, which is much smaller than the distance from the source to the surface intended for coating. The point source is assumed to be an emitting sphere with a uniform surface temperature. Evaporation is considered to occur uniformly in all directions. Deposit thickness, t, can be calculated using t = (m/4rcp)(cos 0 cos r

2)

(~ 1.4)

where m is the deposition rate, p is the density of the material, and r is the distance between the source, $1 and the surface SE being coated. Figure 11.6 shows the geometry. This equation 1-3] shows the inverse effect of source-to-substrate distance on deposit thickness distribution and the effect of substrate surface angle on total thickness. If the deposition rate were to be calculated from deposited thickness and deposition time, even though source rate monitoring would show a constant rate, a decreasing rate would be calculated (if the experiments included increasing r). In many cases in the electronics packaging industry, the substrates are adversely affected by temperature. Since a molten pool of metal emits infrared, r

Vacuum/Hetallization For Integrated Circuit Packages 251

Y r

dS 2

z

~> X

Source

Figure 1 1.6

Surface

- S

Geometry of the deposition thickness distribution.

is typically increased to decrease maximum temperatures. This requires higher powers at the source to account for the r 2 effect on deposition rate. Varying angle q~also varies the coating thickness. Substrates used in electronic packaging can include surface recesses such as vias or through-holes. Coating these profiles results in thickness distributions along the recess walls that can drastically affect the electrical characteristics of the final circuitry. Compared with the top, the base of the recess can have a smaller coating thickness, hence a smaller cross-sectional area. In the case of an electrically conductive coating, the resistance at the base of the recess may be too high for adequate signal processing. Surface coating uniformity is another aspect requiring attention. Electronic packages, such as circuit boards, are quite large. Even IC packages that enable fanout of the chip to a circuit board are processed in large areas. If a point source were used, the thickness across the surface would vary greatly along both the length and width of the substrate. A long source can be used to increase the uniformity in one direction. It is common for evaporation systems to simulate a long source by using multiple small sources with overlapping deposition envelopes. Uniformity in the other direction can be obtained by moving the substrate at a constant speed.

1 1.5 Evaporation Methods and Sources As discussed above, the source used for evaporation can significantly affect the resultant coating properties. The economy of each source varies according to its maximum deposition rate but is also a function of the equipment investment. Even though the fastest processing time (highest deposition rate) seems to be the most economical, there is a trade-off--the highest equipment costs are associated with the highest deposition rates. Four basic methods are used to heat materials:

I

252

MATERIALS FOR ELECTRONIC PACKAGING

radiation, resistance heating of a wire or crucible, induction by RF, and electron bombardment. 1 1 . 5 . 1 Radiation

Radiant heating is used mostly for deposition of zinc and materials with low melting points. A trough is filled with enough evaporant to perform the entire deposition. The resulting coatings can be uniformly deposited if the trough length is longer than the web width and the web is passed by the trough at a constant speed. This method cannot be used for metals with high reflectivity in the infrared nor can it be used for depositing insulators with low absorption in the infrared. Sources usually consist of a heater and a trough for the evaporant. 1 1 . 5 . 2 T h e r m a l Resistance

Resistance boats (Fig. 11.7) are commonly made from boron nitride and are used for aluminum evaporation onto rolls of polycarbonate and polyester. When electricity flows through the boat it heats the resistive material. Evaporation rates for aluminum are extremely high, and coated rolls are usually 6 ft wide by 10000 ft long. Aluminum wire is constantly fed into the boat so it never runs out. The distance between each boat governs the coating uniformity across the web (material). If a single boat were used, an extremely nonuniform coating would result. The coating would be thickest just above the boat and would decrease rapidly according to the previous equations. This method is not used in the electronics packaging industry since copper reacts with the boron nitride boat at evaporation temperatures, resulting in contamination of the deposited film. 1 I . 5 . 3 RF Induction

Radio frequency (RF) induction is conventionally performed using a graphite crucible (Fig. 11.8). High power RF energy is coupled from RF coils, through the thermal insulation and crucible, into the evaporant. The crucible is usually charged with enough material to coat the entire web. This eliminates the need for moving parts inside the vacuum system for evaporant feeding. Thickness distribution is

~.

I Figure 1 1.7

- -

MOLTEN POOL

BOAT

Resistance boat evaporation source.

~//

Vacuum Metallization for Integrated Circuit Packages

\

253

/

\

\

\\

\

Evaporating Atoms

,,

\\

..............

/

\

\ 2,

,'

/

]

,/

.

,

l

.............

,.,,.,.

............

RF Coil EVAPORANT

-

I Crucible

Figure 1 1.8

Graphite crucible for RF induction evaporation.

similar to the resistance boat. Multiple sources are required to deposit a more uniform coating. I 1 . 5 . 4 Electron B e a m

A very efficient method, electron beam evaporation focuses a stream of electrons at the surface of the evaporant. On impact the electrons transfer their kinetic energy into thermal energy of the evaporant. Heating is concentrated on a small spot in the center of the crucible; little heat is lost to the water-cooled crucible liner. Electron beam evaporation reduces the possibility of the crucible being attacked by an active evaporant. Manufacturers water-cool the crucibles to keep them at a much lower temperature than the evaporant. In some cases, when depositing copper, the crucible is water-cooled copper. The copper evaporant is melted into a pool. Heat transfer, beam power, and beam contact area regulate the size of the pool and skull. The skull refers to the solidified evaporant that surrounds the molten pool. But a water-cooled copper crucible is not efficient because significant heat is lost from the pool. An insulating crucible liner, such as carbon, is more efficient but is more likely to result in deposited film contamination. Cooling of the carbon-lined crucible is a compromise between excess heat loss and contamination. Commercial electron guns are either transverse beam (Fig. 11.9) or straight beam (Fig. 11.10), commonly known as the Pierce type. Figure 11.9 shows the transverse beam is bent 270~ this configuration was developed to eliminate shorting of the emitter by falling debris. The beam is bent by magnetic fields. The transverse beam is typically used for low power applications (15-200 kW), whereas the Pierce type is more often used for large applications and where precise beam patterns are required. The advantage of using a transverse beam is that coatings of various material can be subsequently deposited. It is possible to deposit coatings with multiple layers by using the transverse beam source with multiple hearths

254

MATERIALS FOR ELECTRONIC PACKAGING

.......

_

Electrons

Crucible

Figure 11.9

/

/

,

........ "" .,.""

E-Gun

r

....

................... ...........

Transverse electron beam evaporation source. Pierce Type Gun Electron -B 9 eam

Crucible Figure 11.10

Pierce electron beam evaporation source.

(crucibles). Each hearth can be charged with a different material. When each coating reaches the correct thickness, the hearth is rotated to expose the next crucible. But there is a disadvantage of the transverse beam; to provide reasonable uniformity, multiple sources are required. The Pierce gun can be used to provide coatings with good uniform thickness across wide substrates such as a web. The beams can be oscillated in various patterns and multiple beams are common. Roll electron beam evaporators are being produced to coat uniformly across webs 6 ft wide; their hearths are commonly 8 ft wide. One drawback of the Pierce gun is that it requires differential pumping (a high vacuum pump located at the gun) if operated for long periods of time. Another drawback is that single hearths can only deposit one film composition. However multiple hearths can be employed to create films of various layers. In either case, straight or transverse beams can be employed to deposit metals, insulators, and multilayer films

1 1.6 Sputtering Cathodic sputtering was discovered independently by Grove in 1852 and by Pluker in 1858. They observed the wall of a glow discharge tube had become coated by a metallic film in the region of the negative electrode. A very early reference to the use of this observation for film deposition is that of Wright [3].

Vacuum Metallization for Integrated Circuit Packages 2 5 5

Sputtering, unlike evaporation, is a momentum transfer process. Gas atoms or molecules are ionized into cations and attracted to a surface that is negatively charged. The most commonly used sputter gas is argon, as it is nonreactive and inexpensive compared to other noble gases. Sputtering occurs when the kinetic energy of the bombarding atoms exceeds the threshold energy level of the target material being bombarded. These sputtered (dislodged) atoms traverse some distance and condense onto a surface having lower energy than their own. With the arrival of additional atoms, nucleation and film growth occur. Sputtering may be best understood by starting with glow discharge, and that is what we shall do.

I 1.6.1 Collision Processes

The first collision process to consider in sputtering is electron ionization. A thermal electron impacting an atom will result in an elastic collision; no kinetic energy can be transferred from the electron: E~

Ea

=

4M,,Ma

(] ~.5)

(Me + Ma) 2

where E~ is the kinetic energy of the electron, E~ is the kinetic energy of the atom, M~ is the mass of the electron (9.1 x 10 -31 kg), and M a is the mass of an atom. The fraction of energy transferred from an electron to a hydrogen atom is 0.0331, which is insignificant for the smallest atom. At vacuum pressures, electrons are very mobile and can travel long distances before colliding with another particle. Since they have little mass, they can have extremely high velocities compared to a gas atom. Figure 11.11 shows an electron with high kinetic energy approaching an atom. If this electron has sufficient energy and comes close enough to an orbiting electron, or if the two collide, there is an inelastic collision and an exchange of energy. The orbiting electron can change direction, leaving the atom's orbit to create an ion: e- + He ~ He § + 2e-

(11.6)

/

/

/

Impa

Figure

1 1.1 1

Schematic representation of ionization by electron impact.

256

MATERIALSFOR ELECTRONIC PACKAGING

m

Vacuum Chamber T , Anode ' 1

J

ir PLASMA

,, Cathode

]

wer

! II,

~ply

Figure 1 1.12

jP

Diode plasma system.

This is electron impact ionization. If both electrons are traveling through an electric field, they can be accelerated so that further ionization can occur. If each of the two electrons dislodges another electron, a cascading effect occurs and allows a glow discharge to be sustained. Figure 11.12 shows a vacuum system with a cathode and an anode. As the free electrons travel through the gas, creating ions, an avalanche occurs. Ions become attracted to the negatively charged electrode. As the ions bombard this electrode, electrons are emitted (secondary electrons). These electrons create additional ions, which in turn are attracted to the negative electrode. A glow discharge is sustained when there is equilibrium between the ions and the electrons that create them. The discharge appears as a glowing cloud. It is commonly referred to as a plasma. Plasma is typically used when discussing radio frequency or alternating current discharges, and glow is typically used when describing direct current discharges. In any case, once the glow is established by ionization, it consists of ions, electrons, excited atoms, recombining atoms, relaxing atoms, and intense radiation.

1 1 . 6 . 2 Excitation

Excitation of an atom occurs when a free electron, with lower energy than the ionization energy of the atom, collides with an atom electron. The atom electron does not leave the atom, instead it jumps to a higher energy level corresponding to the quantum of energy absorbed.

Vacuum A4etallization for Integrated Circuit Packages 257

1 1 . 6 . 3 Relaxation

Excited atoms are unstable and have a short life. The electron will relax to a lower energy state. This may consist of multiple quantum level drops before it is completely relaxed. As the electron decays in energy, photons are emitted in correspondence to the energy of these states. The visual glow observed when looking into the plasma results from this phenomenon. It is possible to gain information on the gases and their concentrations by analyzing the emission spectrum with an optical analyzer. 1 1.6.4 Recombination

Similar to the atom and electron interactions, recombination also occurs between gas atoms as two nitrogen atoms recombining to form N z molecules. When recombination of an electron with an ion or two atoms occurs, photons are emitted and the spectra can be analyzed optically to determine their identity. 1 1.6.5 Glow Discharge

Figure 11.13 shows a schematic representation of a glow discharge with voltage distributions. Once the avalanche begins, secondary electrons leave the cathode surface and attain high velocities due to repulsion by the negative charge at the cathode surface. There is a very well-defined sheath just above the cathode surface. Known as the cathode dark space, it emits no light as there are few interactions between gas atoms and electrons. The electrons are traveling at much higher velocities than the slower, less mobile ions that are being attracted to the cathode. This results in a predominant population of ions. The thickness of the cathode dark space is inversely proportional to system pressure. In the corresponding electric field distribution (Fig. 11.13) most of the potential is dropped across the cathode dark space. The mean free path of the

Cathode

Anode

Sheath I Voltage

Vr,,.L -600 + Vp

~'I .................?"

*,-'~

~176 ........./ ...................................................... "4.... I

-600

,/

I/' /

Sheath ~' Voltage

Volts D C - Figure 1 1.13

iVp

Schematic representation of a glow discharge.

258

MATERIALS FOR ELECTRONIC PACKAGING

electrons limits the probable distance they will travel before colliding with a neutral atom. This is governed by the system pressure. As electrons begin colliding with gas atoms they produce another region, the region of negative glow. Here, electrons lose kinetic energy because they are colliding and because the electric field is weaker. Ionization, excitation, relaxation, and recombination create an observable intense glowing cloud. For negative glow, the net electric charge is positive and because there are equal numbers of electrons and ions the potential is the same across the glow. The net electric charge is called the plasma potential. There are additional glow regions and sheaths for various plasma system configurations, but in most sputtering systems, only the cathode dark space and negative glow exist. The ions and electrons in the negative glow region are not affected by the cathode electric field. Their motion is random and follows Fick's first law [6]:

dn J

=

--D a --

(11.7)

dx where Da is the ambipolar diffusion coefficient and dn/dx is the local gradient of the charged species concentrations for the ion or electron. Both ions and electrons must diffuse together (ambipolar diffusion). This may not be apparent since electrons are moving at much higher velocities than ions, but consider the effect of electrons leaving the plasma at a higher rate than ions. The result would be an increasing positive charge that would impede the electron migration. Both electrons and ions will diffuse out of the plasma to grounded surfaces where they complete the electrical circuit. They can also reach surfaces that are electrically isolated (floating). Typically, since electrons are much faster, surfaces at floating potential will charge negatively to a few electronvolts until there is an equilibrium between arriving and departing electrons. The ions and electrons also diffuse to the sheath region. When this occurs, electrons are repelled by the cathode, and ions are attracted to it. Debye length, 2d, is a theoretical length describing the maximum distance an electron will be influenced by the electric field of a positive ion [1]: 2d = 743

cm

(11.8)

where T~ is the electron temperature and ne is the electron density. A glow cannot exist in a space less than 2d, an effect known as Debye shielding. Debye shielding is important in glow system design and plasma diagnostics. 1 1 . 6 . 6 B o m b a r d m e n t a n d Ejection

Ions reaching the dark space sheath become attracted to the negative charge applied to the cathode. Argon ions increase in velocity as they traverse the dark space. When they impact the cathode, kinetic energy is transferred into the crystal

Vacuum Metallization for Integrated Circuit Packages 2 5 9

Sputter Gas Ion Reflected Sputter Gas Atom

Ejected Target Atom

@ i

,c :

Photon

9

'.,,,,, !/. ...~

Secondary Electron |

Impact .

" 9 '...

~ : ::

TARGET

..

@. ..

9.

9

. .@

.............

|

..

. . . . . ?"

h i f t s in L a t t i c e .:.!

Figure 1 1.14

E n e r g y transfer m e c h a n i s m for sputtering.

lattice at the surface of the target material. Lattice spacings shift until an atom is ejected from the target surface (Fig. 11.14). And there are other processes resulting from this bombardment. Secondary emitted electrons and sputtered atoms, along with the working gas atoms, can be implanted into the target or reflected back into the system. Implantation of the sputter gas atom is less probable at the low voltages (300-700 V) used in most magnetron sputter systems, but it still occurs. Billiards is a common analogy for sputtering. The cue ball is the sputter gas or working gas. The billiard balls are the target atoms. Once the cue ball impacts the closely packed billiard balls, the resulting scatter sends some of the billiard balls back toward the player. Although this generalization is very simple, it is a useful description, and only consideration of interactions between closely spaced atoms is needed [2]. I 1 . 6 . 7 Sputter Yield

The sputtering yield, S, is defined as the number of target atoms (or molecules) ejected per incident ion [2]. This is an important aspect as it determines the erosion rate of a target and partially determines the deposition rate of the sputtered material. Increasing ion energy results in an increase in yield (for ion energies under 1 keV). Above 1 keV, the yield becomes relatively constant. It appears that higher energy is distributed over the volume of the target, not just the surface [2]. The energy used at the surface to produce sputtering seems to saturate, and above this region, increasing energy is transmitted into the bulk of the target.

260

MATERIALS FOR ELECTRONIC PACKAGING

140 t-~

z

120

u~

100

0 C) L.IJ (/')

o Qs u~ (.9 Z

80

"'

60

r~ z

o

40

I--,_.., 0 13_

uJ

20

123

0 0

2

4

6

8

10

12

CATHODE POWER (KW)

Figure 1 1.1 5

Deposition rate as a function of cathode power for (,) chromium and

( x ) copper.

Yield is also a function of the mass of the sputter gas atom and the mass of the material being bombarded. Although it is not thoroughly understood, S varies by a factor of 100 for increasing sputter gas mass but only by 10 for increasing target material mass [4]. In practice, if we know the deposition rate at an applied target power for a specific material, we can estimate the deposition rate for a new material at the same power setting. To estimate the deposition rate for the new material, multiply the deposition rate for the existing material by the ratio of the yields. Figure 11.15 shows deposition rates for both chromium and copper as a function of varying magnetron cathode power, at an argon pressure of 2 x 10-3 torr.

1 1.6.8 Mognetron Sputtering In the early 1960s Thornton and Penfold were experimenting with magnetic fields and rare gas plasmas. In the late 1960s F. Werner's work with sputtering interested Penfold and led to the application of a magnetic field to a sputtering cathode [7]. The purpose of the magnetic field was to trap secondary emitted electrons escaping from the target surface. The path of the trapped electrons was increased by changing their direction. Instead of leaving the target surface and traveling to ground, the electrons were forced to travel in a helical path above the target surface. Figure 11.16 shows a schematic representation of a planar magnetron.

Vacuum/Hetallization for Integrated Circuit Packages

261

MagneticFlux Lines ~[ .N ~

r!

'. N

Figure 1 1.1 6

...

S

Schematic representation of a planar magnetron sputtering target.

Erosion Groove Profile at 100 Amps

-,<

Target

"x~

Figure I 1.17 Cross section of a planar magnetron sputtering target showing the erosion grooves at l0 A electromagnetic current.

Erosion Groove Profile at 25 Amps

'.,.._j

Target

Figure 1 1.1 8 Cross section of a planar magnetron sputtering target showing the erosion grooves at 25 A electromagnetic current.

The increase in path results in an increase in the probable number of ionizing collisions before the electrons finally escape to a grounded surface. Since the number of ionizing collisions increases and thus the number of ions increases, the sputter pressure can be decreased. This leads to very high deposition rates and very pure deposits. Currently, both permanent and electromagnets are used to create the magnetic field. Typically, the magnets are positioned behind the target. The magnetic field is elliptical and causes electrons to travel in a spiraling "racetrack" pattern (Fig. 11.16). The maximum density of ions occurs at the maximum density of electrons. This results in a similar pattern etched into the target. The shape of the etched groove can be varied by varying the magnetic field strength. Figure 11.17 shows a cross section of an eroded target using an electromagnet current of 100 A. Figure 11.18 shows a similar cross section using 25 A. The high

262

MATERIALS FOR ELECTRONIC PACKAGING

current results in a very strong magnetic field that seems to confine the electrons to a very narrow region and consumes less target material. The target in Figure 11.17 would have to be replaced sooner than the target in Figure 11.18.

1 1.6.9 Deposition Rate The deposition rate in a sputter system can be determined empirically using equation (11.3). The deposition rate for sputtering or evaporation can be directly correlated to the applied power. In sputtering, for experimental purposes, the deposition rate is directly proportional to the cathode power. A doubling of cathode power will result in an approximate doubling in thickness if speed (residence time) remains constant. However, for statistical process control, target erosion can reduce the rate by approximately 10% over the life of a target, even though the power remains constant (Fig. 11.19). This change in rate with erosion is not fully understood, but it can be compensated by simple power adjustments, either manual or automatic.

1 1.6.10 Coating Uniformity The racetrack pattern of the electrons means coating thicknesses are greatest at the edges of the substrate. The actual deposition zone at the edge is an integration of all the deposition rates along the "turn" region of the target erosion pattern. 7000 6800

E

6600

O +'

6400

ET~ C

u) 03 w z,x,C) I--OE W El._ Q_ 0

o

6200 6000

k

5800 5600

5400 5200

5000

I

I

0

I

10

I

20

L _ _ _ _ L

30

40

I

50

I

60

,

.

t

70

,

I

80

i

90

I

100

% Target Erosion

Figure 1 1.19

Plot of target erosion effect on deposition thickness (deposition rate • time).

Vacuum A4etallization for Integrated Circuit Packages 2 6 3

Therefore the actual deposition zone is longer than the two zones which make up the center portion of the erosion pattern (Fig. 11.16). It is common practice to shield the substrate from the racetrack ends to create a more uniform thickness distribution. Most sputtering systems used for production pass a substrate beneath the target at a constant velocity. This produces a uniform coating along the length of the substrate.

1 1.7 Heat Transfer in Physical Vapor Deposition Processes Energy transfer occurs when the depositing atom arrives at the substrate surface; kinetic energy is converted into thermal energy. The substrate temperature will change if the flux of energy occurs at a higher rate than the substrate can absorb or transfer. If the substrate has a large heat capacity, the temperature change can be kept low; if the substrate has a small heat capacity, it will rapidly increase in temperature. During sputtering, maximum temperatures of a substrate can easily reach 400-500~ Few substrates can withstand this level without decomposing. In a vacuum, heat transfer is dominated by a radiation exchange between two bodies or by conduction. Conduction is very limited since no gas molecules are available between surfaces. Contact between two surfaces can be increased to improve heat transfer by coating the surfaces with vacuum grease or by forcing the surfaces together. The use of force is an industry standard for substrates in a roll coater format. Consider the case where a substrate, such as a web of material, is passed under an infrared (IR) lamp at vacuum pressure. The heat flux into the web will follow [1, 9] q = a A e (T4w -

T4h)

(11.9)

where q is the net exchange of energy, a is the Stefan-Boltzmann constant, A is the area, e is the material's emissivity, Tw is the initial temperature of the web, and Th is the heater temperature. In this case, the heat flux into the web is from the IR heater. Now consider the web passing through a sputtering zone with atoms arriving with energies of 5-10 eV. If the arrival rate of the atoms is faster than the web can radiate heat, the web temperature will rise. If the rate of rise to a damaging temperature is faster than the deposition time, the web will overheat. If the rate of deposition is kept low, the process speed will be low. This does not lend itself to the economic processing of thin substrates; overheating is not a problem for substrates with adequate heat capacities. Figure 11.20 shows a plot of a 1 mm thick ceramic being deposited with 8 000 nm of copper at a deposition rate of 10 nm/s. The copper atoms had an average energy of 14 eV. Figure 11.20 also shows the same deposition conditions and a 0.05 mm polyimide web. Although both substrate materials can withstand 400~ the polyimide is subject to severe dimensional changes that cause

264

MATERIALS FOR ELECTRONIC PACKAGING

450 400

350 3oo

250 D

200 150 100

50 0

0

1'

2I

3

;

;

TIME(MINUTES)

6j

7=

8

9I

10'

Figure 1 1 . 2 0 Plot of heating rates for (O) polyimide and ( x ) ceramic, two substrates with very different heat capacities.

creases. The substrate temperature with only radiation cooling follows [5]

dT~ dt

-

KER TpCp

+ 2ae (T4w - T~*.)

(11.10)

where t is time, z is the thickness of the substrate, n is the substrate density, Cp is the substrate specific heat, K is a constant of proportionality, E is the atom energy, R is the deposition rate, and Tch is the temperature of the surrounding chamber. KER is the heat flux into the substrate and, for sputtering, is comprised of the energetic coating atoms, reflected electrons, reflected sputter gas atoms, infrared radiation from the source, and ultraviolet radiation from the plasma. Evaporated atoms are not as energetic, but the radiation from the source is much greater than that for a sputtering source. Heat flux due to radiation is minimized by reducing the view factor. To minimize or control the substrate temperature, it is a common practice to reduce heating. It is also a common practice to provide a means of cooling other than radiation. By replacing radiation exchange cooling with conduction, equation (11.10) becomes [8,9]

KER =

TW -- Tsur

z/k f A + 1/o~

(ll.ll)

where Tsu r is the temperature of the contacting surface, k I is the thermal conductivity of the substrate, and ~ is the heat transfer coefficient for the two contacting surfaces. The contact coefficient is a function of surface roughness, contact force, material hardness, thermal conductivity of the two materials, and any absorbed gases that

Vacuum/Hetallization for Integrated Circuit Packages 265

K x E x R = (T 2 - T1)/'T7'k f x A+I/O~ Polymer Surface T2

. . . . . . Drum S u r f a c e

[1

L__

Figure

1 1.21 Schematic representation of a heat transfer mechanism between two surfaces in a vacuum.

would outgas into the "gap" during deposition (Fig. 11.21). Roll coaters are designed specifically to force contact between two surfaces and to control the temperature of a cooling surface.

1 1.8 Roll Coater Metallization Although this technology is about 30 years old, roll coater metallizers, have not been used extensively in the electronics industry. Recently, with the advent of TAB, these systems have been employed to provide a plating strike layer, as previously described. A roll coater metallizer can be either an evaporation system or a sputter system. The heat of deposition is transferred from the substrate to a cooled surface, a rotating drum cooled by a chilled fluid (ethylene glycol). Material contacts the drum during deposition for cooling and transport; the drum is used to drive the web. Contact force is provided by wind and unwind rollers that have torque applied in opposite directions. This opposing torque forces the material onto the chilled drum surface (Fig. 11.22). Figure 11.23 shows thermal profiles for 0.05 mm polyimide web. With good contact there was good heat transfer and the polyimide was cooled. But when 150 nm of copper were deposited onto the polyimide surface, good contact was lost and with it went the cooling effect. Contact force, F, is a function of the chilled drum diameter and the tension applied to the wind and unwind rollers; it can be calculated from F = 2 T cos(~/2)

\

/ T

Figure 1 1 . 2 2

Diagram of the contact forces between a web and a roller.

(11.12)

266

MATERIALS FOR ELECTRONIC PACKAGING ,360

, 0 ............ 4~........... .&,,,,,

,-, 320 ! 280 o

~

I~

"U

"~

~

tel

240

200

/

L

80

"0-. "'%

,/

,

/

L

/

"-.% l)

/ /,/

r~ Q_

""N

9

160 LJ 120

9

0"

/

/ --

--

/

/

/

/

/

/

/

/

/

0"

/

/

~____---x 5

,5'

x

x

x---"-'*~"---x--~

2;

3;

TIME (seconds)

Figure 1 1.23 Plot to show the effects of ( ~ ) heat transfer for 0.05 mm thickness polyimide.

3;

40

contact and (...... ) loss of contact on

where c~ is the contact angle (Fig. 11.22) and T is the applied tension. A small contact angle will require less applied tension for the same force. The contact force and temperature of the chilled drum are the two easiest variables to change in attempting to control the contact parameter. The contact parameter is very comlzlex since it consists of surface roughness and material properties such as moisture content. It is usually determined through experimentation for various material sets. Another problem found in roll coating is handling. Since no air is available, smooth material surfaces will make adequate contact so that no slippage occurs. Rolls of material have a tendency to telescope. If the material is not aligned correctly and not allowed to slip when it travels over the drum, one side of the web will lift away from the drum surface and overheat. A telescoped roll or a roll wrapped under varying tension will result in this problem. Many manufacturers of polymer webs provide a slip additive in the material. This reduces material contact and/or friction and reduces static charge.

1 1.9 Coating Material Properties The adhesion of the deposit to the substrate is probably the most important property. Many companies subject these materials to harsh environments in an attempt to accelerate aging. The data resulting from these accelerated tests is then used to predict the product life in the field. One of the most common tests is to subject electronic circuitry to high temperatures at high humidities for long times and then to perform peel tests at various intervals.

Vacuum A4etailization for Integrated Circuit Packages 2 6 7

The resistivity of the film is another critical attribute. If the film is used as an electroplating seed, the resistivity has to be low for current flow. Likewise, if the entire thickness of the film is used as a conductor, the resistance must be low; this is critical for multilayer devices. Any interconnecting vias or through-holes must have sufficient current-carrying capabilities and should not adversely affect the circuit reactance.

1 1.10 Evaluating Deposited Films Engineering of vapor-deposited coatings requires evaluation of properties such as adhesion of the film to the substrate, resistivity of the metal film, optical properties, and purity. Once a process and film have been defined, manufacturing requires further monitoring and control. Since our focus is on electronic packaging, we limit our discussion to electrical circuitry and the plating of seed layers. 1 1. I 0 . 1 Adhesion M e a s u r e m e n t

There are many measurement techniques for evaluating the adhesion of a thin coating on a substrate. The method selected can depend on the thickness and brittleness of the coating and the rigidity of the substrate. Among the available tests are 90 ~ and 180 ~ peel tests, tape pull tests, scratch tests, and acoustic tests. The tape method is as simple as pressing a strip of tape onto the coated substrate. The tape is peeled and observed for any film that may have been removed. Although this is crude, it is very useful for initial qualitative information. The scratch test is also qualitative. Under a varying load, a stylus with a small radius is moved across the film. The adhesion strength is determined by the minimum load required to cause the film to separate from the substrate. This

'['T ~--AI----~ I I

...... T

....

AI

.......................~~! " ,' .... Substrate

'

~A

Line

I

I

Figure 11.24

Schematic representation of a 90 ~ peel test.

268

MATERIALS

FOR

ELECTRONIC

PACKAGING

1+~ I

0

140--I

E

=

16.9

gm/mm !

120o

E E E

100-

9.7

80--

60-

40-

3.7 o

20-

i 0

1.9 I

I 10

t

Figure 11.25(a)

1

-

STRIP

i 20

i

THICKNESS

I 30

-

1

! 40

I

~m

Plot showing effect of peeled line thickness on measured peel strength.

technique does not lend itself to elastic and soft substrates. The results obtained using the scratch test usually have a high degree of scatter. The peel test is probably the most popular for semiquantitative analysis. Figure 11.24 is a schematic drawing of a 90 + peel test used in evaluating circuitry-to-substrate adhesion. A circuit line or line segment is fabricated then bent at 90 ~ starting at one end. This line is connected to a tensile tester load cell. A varying load is applied and the force required to cause peeling is observed. This force is generally reported in force per unit width. Since force per unit width is equivalent to energy per unit area, the bond energy is analogous to the surface tension of a liquid. This energy is not just the adhesive energy necessary to break

Vacuum A4etallizafion for Integrated Circuit Packages

269

35.01

32.

7.6

30.

27.

25.

22.

20.

17. 17.8

15.

Z C] bJ 7"

~.~. 4

12.

f

10.

7.5

t O

I

I

P

Figure 11.25(b)

I

40

I

I

I

80

-

PEEL

STRENGTH

120

-

I

I

I

160

I 200

gm/mm

Plot showing true adhesion energy as a function of peel strength.

the bond, but it includes the elastoplastic energy that goes into the strip itself. In Figure 11.24 the dotted line represents the position at a later time interval. The adhesive bond energy constitutes only a portion of the measured energy; the rest goes into elastoplastic energy of the system. Detailed experiments and " theoretical analysis to determine the relationship between peel strength and interface adhesion were performed [10] for an electrodeposited copper line on a polyimide substrate. Figure 11.25(a) shows the results of analysis for the effect of strip thickness of peel strength for 0.76 mm wide copper strips at four levels of true interface adhesion. Figure 11.25(b) shows the adhesion energy density as a percentage of peel strength plotted against peel strength for the four copper strip

270

MATERIALS FOR ELECTRONIC PACKAGING

thicknesses obtained from the modeling. These figures demonstrate that peel strength is a nonlinear function of the copper line thickness, depending on the true nature of the interface bond strength. The fraction of peel energy (bonding energy) going into the interface to cause separation during the test can range from 10% to 30%, depending on the line thickness and bond strength. The use of the peel test is limited to films at least as thick as 8 000 nm and therefore requires a thick deposit or some form of buildup such as plating. Consequently the peel test is not easily applicable to thin or brittle films. In these cases, the tape or scratch test may be useful. 1 1 . 1 0 . 2 Interface Analysis

Understanding the bonding mechanisms that create good film-to-substrate adhesion is essential. Auger electron spectroscopy (AES), electron spectroscopy for chemical analysis (ESCA), secondary ion mass spectroscopy (SIMS), and Rutherford backscattering spectrometry (RBS) can provide detailed elemental information and interface structure. As the complexity of materials increases, they become more important for the determination and monitoring of composition. All surface analysis techniques work on a similar principle. A probe particle (electron, photon, or ion) is injected into the sample, causing a reaction. This results either in backscattering of the injected particle or emission of particles from the sample. The mass, energy, and wavelength of these emitted or backscattered particles are generally characteristic of the elements in the sample. By analyzing the mass of an emitted ion, the type of element can be identified. If the sample is etched by sputtering while being analyzed, the film composition can be analyzed through its bulk. In AES, this is commonly referred to as a depth profile. Figure 11.26 shows a depth profile of a 25 nm chromium film and 300 nm copper sputtered film on polyimide. Auger uses a microamp electron beam to excite elemental characteristic electrons; ESCA and X-ray photo electron spectroscopy (XPS) use an X-ray beam to excite primary electrons; SIMS uses an ion beam to etch a surface and perform mass spectrograph analysis. RBS bombards the sample with helium ions then measures the energy loss of the backscattered helium. The general characteristics of these techniques are summarized in Table 11.1; detailed information is available in the literature. The contribution of these analytical tools in understanding adhesion problems lies in their ability to probe the interface composition and obtain information as a function of depth. When the interface composition is defined and optimized by a material set and a deposition process, interface analysis can be used to obtain a reference. When the interface structures change, due to subsequent process contamination or problems during deposition, interface analysis can be used to identify the composition differences from the original data. This comparison can aid the investigator in identifying the origin of the problem. One example is the loss of adhesion between a chromium-copper seed layer and polyimide used for TAB products. Circuit lines were plated to the proper thickness and the copper

Vacuum Metallization for Integrated Circuit Packages 2 7 1

100

F

oLy

T

~

o

~ /

C

c

0

.

7o

.: :" ..-"

6o

N C 50 ~_ E

NT

R A

s

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."

-

i

-

/~

.

.

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~."

30 L

.-

.

-

40 ,L_

..

-

~

1"i

i-2

:

'o.

I 0 20 ~ N 9

0

1

2

3

4

5

6

"I

~

9

10

13

SPUTTER TIME ( r a i n . )

14

15

16

17

18

19

Figure 1 1.26 Auger depth profiles of a 600 nm copper/25 nm chromium film sputter deposited onto a polyimide web: (---) N1, (- 9-) C1, ( - - . - - ) O1, ( - - ) Cu l, (...... ) Cr 2.

Table

11.1

Surface analysis summary.

Area (#m) Depth (#m) Information Depth profile Destructive Sensitivity (%)

ES

ESCA

SIMS

RBS

3 2 A,B yes not usually 0.1

200 2 A,C yes no 0.1

0.01 0.3 A,B,C,D yes yes ppm

1 000 10 D,E,T yes no 0.01

A = e l e m e n t a l analysis B = m a p p i n g of e l e m e n t s C = c h e m i c a l b o n d i n g studies D = q u a l i t a t i v e analysis E = s t o i c h i o m e t r y analysis T = layer t h i c k n e s s d e t e r m i n a t i o n

seed was etched using an FeC13 solution; the c h r o m i u m was removed using K M N O 3 solution. Two hours after etching, the parts were visually inspected. The c h r o m i u m - p o l y i m i d e interface was observed by looking through the polyimide. It was apparent by a color change that the c h r o m i u m was being attacked. At further time intervals, the parts were inspected, and after 24 h, it was apparent that all the c h r o m i u m had changed color. Figure 11.27 shows a circuit line observed

20

272

MATERIALS FOR ELECTRONIC PACKAGING

Figure 1 1 . 2 7

The back of a circuit line (through the polyimide web) showing chemical attack of the chromium seed layer.

through the polyimide; the dark area is pure chromium, the lighter area is contaminated chromium. Figure 11.28 shows the same line after 24 h of exposure; no dark area is observable, indicating all the chromium is contaminated. The line was separated from the polyimide surface for interface analysis. ESCA was used on the polymer, and AES was used on the back of the metal line. AES detected a high level of chlorine in the chromium layer and ESCA detected a high level of chloride at the polyimide surface. Further investigation into the process of forming the lines showed the parts required longer water rinse times after the copper etch process. In general, similar information is generated by all techniques. For example, a picture of the element type and distribution can be obtained with either AES, ESCA, SIMS, or RBS. But they do have fundamental differences in operation and may lend themselves to the analysis of different materials. AES uses sputter etching for depth profiles. As polymers preferentially sputter etch, AES is not very useful for analyzing polymers. ESCA provides more detailed chemical state information than any other technique and SIMS is more sensitive to low concentrations.

Vacuum/Hetallization for Integrated Circuit Packages 2 7 3

/

/

1

F

Contamination Figure 1 1.28

Po lyimide

The circuit line shown of Figure 11.27 after 24 h elapsed time.

77,,70.3 Film Stress

Intrinsic stress is one of the most important elements that affect the adhesion and dimensional stability in thin film composite material. Thin film metal deposited onto a substrate can induce high stress at the interface because of differences in thermal expansion coefficient (thermal stress). The stress can also be induced by the way the thin film metal grains grow (intrinsic stress). A flat substrate can curl during metallization, due to stress. The stress can easily be estimated by measuring the amount of the substrate curvature according to (11.13)

a = t/2r

where r is the radius and t is the thickness of the composite. When the substrate is not initially flat equation (11.13) is not valid. Using the layer removal technique a modified equation [11] has been developed to calculate the residual stress for a thin film in this situation: cr=~

6

Ah

+ --

(11.14)

274

MATERIALS FOR ELECTRONIC PACKAGING

where h is the thickness of the remaining layer, Ah is the thickness of the removed layer and has negative values, E is the Young's modulus of the remaining layer, r is the radius of curvature of the remaining layer, and A(1/r) is the curvature change before and after layer removal. Residual stress can also be measured by X-ray diffraction as long as the film is thick enough to diffract the intensity for peak position measurements. Peak position can be calculated from the X-ray intensity profile by fitting the profile to a Gaussian function with Lorentz polarization and absorption corrections. The residual stress is obtained from the slope of the peak position 23 versus sin 2 7~ curve, where g is a tilt angle of 0 ~ 15~ 30 ~ 45 ~ and 60 ~ Residual stress of a sputtered 600 nm copper layer with a sublayer of 25 nm of chrome deposited onto a 50/~m polyimide was measured at the copper (4 2 0) using copper K~ radiation or measured at the copper (3 1 1) using chrome K~ radiation. It was found that the obtained residual stresses by copper K~ (e.g. - 2 4 ksi) and chrome K~ (e.g. - 2 3 ksi) agree very well. Stress of copper measured using the layer removal method agreed very well with the copper stress measured by the X-ray method. This agreement leads to the advantage that the stress of a very thin chrome layer, which does not diffract enough X-rays, can be determined using this layer removal technique. It has been explicitly determined that some chrome stress is exceedingly high (> 100 ksi) for the sputtered copper-chrome-polyimide composite, but the measured adhesion is independent of the chrome stress in the film. Further studies have confirmed that the adhesion of a chrome-copper layer on polyimide does not correlate with the stress in the composite. It seems the polyimide is compliant and stress does not affect adhesion.

1 I. I O. 4 Coating Thickness and Coverage

There are many ways to measure coating thickness: magnetic induction, eddy current, profilometry, interferometry, ellipsometry, spectrophotometry, beta-ray backscatter and X-ray fluorescence. These techniques are essentially nondestructive to the sample being measured. Other techniques such as sectioning are also used. However, the five most common techniques used to measure metal films are cross-sectioning, beta backscatter, profilometry, X-ray fluorescence, and ellipsometry. Their use also depends on substrate roughness, film thickness and so on. For very thin metal films (e.g. less than 20 nm) on nonrigid and somewhat rough substrates, X-ray fluorescence is most popular [ 12]. X-ray fluorescence (XRF) film thickness measurement uses an incident X-ray beam to bombard the surface of the film then monitors the energy and intensity of the fluroescence X-rays. Each atom of a specific element emits an X-ray having a characteristic energy at a specific wavelength. Material identification is possible by monitoring the energy of the fluorescence X-rays; the intensity provides information on the amount of material present. Various manufacturers, such as Seiko Instruments, Fisher Technology, and Portaspec, provide XRF instruments. And for the purpose of

Vacuum/Hetallization for Integrated Circuit Packages 275

thickness calibration, Rutherford backscattering spectroscopy has been employed to obtain refined results [12]. The profilometer technique is very popular for measuring thicker metal and organic layers. This is a convenient technique but does require some method of providing a step. It is common either to deposit through a mask or to etch away some of the deposited film from the substrate. AES has been used for estimating the coverage of a thin film onto a substrate and to determine the continuity of the film [13]. Chromium thin film coverage of copper surfaces [13] was monitored as a function of the chromium thickness. The critical thickness of the chrome onto a copper surface was obtained by extrapolation of the copper AES intensity.

1 1 , 1 0 , 5 Ductility

Ductility is a measurement of the amount of energy a material absorbs before rupture and indicates the material's ability to contain plastic deformation. There are many ways of testing ductility: a tensile test, a mechanical bulge test, a low cycle fatigue test, and a bend test. Normally the metal film, including the substrate, is tested as a composite and the results are quoted for the composite. If the ductility of the deposit is much lower than the substrate ductility, the value obtained for the composite can be close to the deposit ductility because the deposit is expected to fracture well in advance of the substrate. The deformation process for a depositsubstrate composite is far more complex than for the deposit alone. But for process control it is convenient and practical to treat the composite ductility as the film deposit ductility. Tensile testing requires special sample preparation. Sample configurations and careful setup for the test are imperative. Standard deviations in the results are commonly high, especially when the deposit is very thin. Bend testing the thin film composite using a mandrel can accurately derive the elastic limit [14] but the ductility is not easy to deduce. Fatique testing using a low cycle fatigue tester [15] can be used to estimate ductility by extrapolation. Samples are flex cycled using various diameter mandrels. These samples are flexed back and forth over the mandrel surface until the material fractures. This test is very time-consuming for ductile materials, and the data is sometimes inconsistent with the ductility measured using the tensile test. This is sometimes due to work hardening of the sample. Overall it is believed the mechanical bulge test offers many advantages over the other test methods. From the mechanical bulge tester (Fig. 11.29), ductility measurements are conducted by slowly pushing a steel ball against a specimen, rigidly held at the edges by two metal plates. The plates have a circular opening in their centers. The ball is forced against the back of the specimen until it fractures. The distance, d, is the displacement from the point where the ball initially contacts the back of the specimen to the point where the material fractures. This distance is converted into percent elongation, E (ductility). From simple geometrical

276 MATERIALSFOR ELECTRONICPACKAGING Bolts

~

S p e c i m e n Holder

pherical Anvil

/' Figure 11.29

~Micrometer 117

/

- i I/V/

Schematic representation of a mechanical bulge tester.

_

-

Figure 1 1.30

//

-

.

.

D

~

r" .............

""-"''""--'--"--''

.

A

..............

:~

Geometry of the mechanical bulge test.

consideration, E is defined as follows: E =

L-

Lo

x 100

(11.15)

Lo where L and Lo are defined in Figure 11.30.

1 1.1 1 Conclusions As electronic packaging is driven to smaller dimensions, vacuum processes will become more readily utilized. Vacuum metallization in electronic packaging provides high adhesion of circuitry to substrates and is used for interconnection metallurgy. Increasing use of TAB and flexible circuits seems inevitable as electronic devices are reduced in size and their performance is increased. Increased utilization of roll coaters for metallization also seems likely. The roll coater can combine polymer surface treatment and metallization into one process, reducing labor and capital expenses. The coatings offer high adhesion performance and do not have environmental contamination concerns, unlike many wet processes. Roll coating also reduces handling of many small parts, as hundreds of parts can be contained in one roll. This reduced handling significantly reduces the possibility of handling damage.

Vacuum A4etallization for Integrated Circuit Packages 277

This chapter leaves out some topics and barely mentions others; adhesion promotion could easily fill a chapter on its own. Much work is being done to investigate plasma and ion beam surface treatment of polyimides. Oxygen, nitrogen, and argon seem to be the gases most widely used, but the gas choice and process parameters depend on the substrate. There are various polyimide films available for use as substrates, and their chemical compositions are not always the same. Nevertheless, surface treatment is critical to achieving the appropriate reaction with the deposited metal. The combination of surface treatment and metallization can result in an electronic package capable of long lifetimes in typical environments for computers. Since computers are increasingly being placed in more hostile environments, creating packaging that will withstand these conditions may be the most challenging aspect for the electronics industry of the 1990s. References

1. R.C. Weast, editor-in-chief, CRC Handbook of Chemistry and Physics, CRC Press, Boca Raton, 1987. 2. B. Chapman, Glow Discharge Processes, Wiley, New York, 1980. 3. L. Holland, Vacuum Deposition of Thin Films, Chapman and Hall, London, 1966. 4. L.I. Maissel and R. Glang (eds.), Handbook of Thin Film Technology, McGrawHill, New York, 1983. 5. D.P. Seriphim, R. Lasky, and C.Y. Li (eds.), Principles of Electronic Packaging, McGraw-Hill, New York, 1989. 6. J.L. Shohet, The Plasma State, Academic Press, New York, 1971. 7. A.S. Penfold, Thin Solid Films, 171, 99 (1989). 8. K.J. Blackwell and A.R. Knoll, in Proc. 34th SVC Tech. Conf., 1991, p. 169. 9. W. Schwartz and W. Wagner, in Proc. 28th SVC Tech. Conf., 1985 p. 28. 10. P.C. Chen, K.J. Blackwell, and W.T. Pimbley, in Proc. 33rd SVC Conf., 1990 p. 205. 11. P.C. Chen and Y. Oshida, in Proc. 33rd SVC Tech. Conf., 1990 p. 200. 12. A.R. Knoll, L.J. Matienzo, and K.J. Blackwell, in Proc. 34th SVC Tech. Conf., 1991, p. 247. 13. H. Lefakis and P. Ho, Thin Solid Film 200, 67 (1991). 14. K.J. Blackwell, P.C. Chen, and Y. Oshida, in Proc. 34th SVC Tech. Conf., 1991, p. 175. 15. Standard Method for Ductility Testing of Metallic Foil, A S T M E796, ASTM, Philadelphia, 1981.

This Page Intentionally Left Blank

PARTV

Polymers and Other

Materials

This Page Intentionally Left Blank

12 Silicone-Based Polymers in Electronic Packaging C. P. Wong

12.1 Introduction Modern electronic devices are complex three-dimensional structures; they consist of millions of components densely packaged in many layers. This imposes stringent requirements on their design, fabrication, and encapsulation (Fig. 12.1). Over the past two decades, the number of components per chip has doubled every 18 months. Ultralarge-scale integration (ULSI) has reduced propagation delays, and advanced devices now operate at 50 MHz or faster, they consume more power, and they dissipate more heat during operation [1]. Low stress encapsulants are the preferred choice to ensure long-term reliability of microelectronics in hostile environments, including extreme temperature cycling. AT&T has been using silicone-based materials to encapsulate dipolar, MOS, and hybrid ICs since 1969, and they appear to have a good record of reliability. This chapter describes the general chemistry of silicones, their reaction mechanism, their electrical performance, and their applications to electronic packaging.

12.2 W h y Do Devices N e e d Encapsulation? The purposes of encapsulation are to protect electronic devices and to prolong their life. Moisture, mobile ions (such as sodium, potassium, chloride, and fluoride), radiation (such as ultraviolet, visible, and alpha-particle), and hostile environmental conditions can degrade performance and reduce lifetimes. At the final stage of fabrication, a thin passivating layer is normally deposited onto the finished, fragile IC. Silicon dioxide, silicon nitride and silicon oxynitride are common passivation layers; they are excellent barriers to moisture and mobile ions, although silicon dioxide is inferior to silicon nitride as a barrier to sodium ions. Doped with a few wt.% of phosphorus, silicon dioxide becomes a much better barrier to mobile ions. A thin layer, 1-2/~m thick, is uniformly deposited on the finished device. On the bond pad areas, the passivating material is etched out for interconnection bonding. Passivated ICs experience edge effects after wire bonding interconnection, and the bond pads provide important protection. Unfortunately, passivation layers are '281

MATERIALS FOR ELECTRONIC PACKAGING

282

10 8

1960

0

10 6

A MOS MEMORY zx BIPOLAR MEMORY

1990

2000

~

9 MOS LOGIC [] BIPOLAR LOGIC (A)

or.9 105 n,. uJ a. 04 Z ul 103 Z O a. r

7

1980

1

m

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1970

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E =t. 10 3 -rICg Z 102 LU .J

Ii- 1

102

LU rr

10

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I-<

LU

10

1

ld.._.___l._..___l~I~__l~ 1960

1970

1980

1990

"""""---..

10.1

2000

_z

YEAR Figure 12.1

Trends in IC technology.

T a b l e 12.1

Modulus and coefficient of thermal expansion (CTE) for some potential encapsulants. Encapsulants

CTE (10 -6 ~

Epoxy Polyimide Parylene Silicone-polyimide Silicone gel

40-80 3-80 35-40 5-100 200-1 000

Modulus (psi) 1-5 • 106 1 • 106 0.4 x 106 0.4 x 106 0--400

not entirely free from pinholes or cracks, so a conformal coating of organic encapsulant is usually applied. Epoxies, polyimides, polyxylylene (Parylene), silicone-polyimide, and silicones, (elastomers and gels) are usually used for this application. Typical properties, advantages, and disadvantages are listed in Tables 12.1 and 12.2 [2-4]. Epoxy molded devices have shown excellent reliability, and they are well-documented in the literature [5,6], but recent developments in hermetically equivalent packaging have centered on soft silicone gel. Table 12.2 presents advantages and disadvantages of six promising encapsulants. Two important properties, coefficient of thermal expansion, ~, and modules of elasticity, E, give rise to thermal stress, a, according to the relation cr = k

EA~dT

(12.1)

IF +-" 1

where k is a constant, and T] and T2 are the two extremes of a temperature cycle.

Silicone-Based Polymers in Electronic Packaging

283

Table 12,,2 Overview of potential encapsulants.

Encapsulants

Application

Advantages

Disadvantages

Epoxies

Normal dispensing or molding

Good solvent resistance Excellent mechanical strength

Not repairable High stress Marginal electrical performance

Polyimides

Normal dispensing (spin coat)

Good solvent resistance Thermally stable (~ 500~

Not repairable High stress

Polyxylylene (Parylene, Union Carbide)

Thermal deposition (reactor)

Good solvent resistance Conformal coating

Thin film only Not repairable

Siliconepolyimide

Normal dispensing

Less stress than polyimide Better solvent resistance than silicone

Higher CTE than polyimides Thin film only

Silicone-{RTV gel)

Normal dispensing

Good temperature cycling Good electrical properties Very low modulus

Poor solvent resistance Low mechanical strength

0rganic I I L0w Thermal aterials| / Expansion I r~176 I Thermal / Polyimide ~ _ ~ I Expansion 4 6/8 ~ ~ . 8 10-s ! _~ 4 Coefficient SiO~ Fe

s,~, ! !,. ~ _ 1

[inorganic"l

I MaterialsI . . . . Figure 12.2

.

I _AuIICAg I -I

AIN, Si,.SiC I ] Alumina

"

Thermal expansion coefficients of various materials used in IC fabrication.

In Table 12.1, compare the modulus of elasticity for silicone gel with some of the other materials. Althoug the coefficient of thermal expansion (CTE) is higher for gels, the resulting stresses are substantially lower. Figure 12.2 presents a spectrum of materials used in fabricating IC circuitry accompanied by their CTEs. According to recent studies, high performance silicone gels in plastic packaging could replace conventional ceramic packaging. General Motors (Delco) has used silicone gels for over 10 years, so has British Telecom. Their simple low cost packages gave better reliability than epoxy molding compounds until the

284

MATERIALS FOR ELECTRONIC PACKAGING

development of low stress, ultrapure epoxies with improved reliability [11]. The new epoxies are cheaper and allow surface mounting of packages on simple epoxy-glass circuit boards. Reliability performance with silicone gels and elastomers has been extensively studied by AT&T Bell Laboratories [2,12-18] and by Hitachi [9]. The corrosion protection results have been quite exciting. Hitachi has used gel-encapsulated devices in supercomputer systems. IBM and Burroughs (UNISYS) have reported good results for gel performance. But widespread commercial use is hindered by the performance of the molded plastic and by poor customer understanding of silicone materials. The Computer Packaging Technical Committee of the IEEE Computer Society is attempting to remedy this lack of knowledge through the activities of a special task force. As well as searching for reliable combinations of materials and processes, the task force is developing standard test procedures. Though far from conclusive, its results to date suggest that, properly cleaned and processed, silicone gels can achieve the reliability of ceramic hermetic packing [7,8,10,19]. Perhaps the real strength of silicone gel encapsulation lies in multichip module (MCM) packaging. MCM packaging is becoming essential to meet high operation speeds and to improve system integration [20,21], especially in large, lightweight packages. Ceramic technology is finding it hard to keep up with increases in package, size and complexity. It is difficult to provide hermetic packages at reasonable cost; matching the lid and substrate CTEs is also demanding. Ever increasing size, up to 4 in. square, makes pressure seals very expensive and technically difficult, if not impossible, to produce. Silicone gel or elastomer can be a simple solution. Plastic molding is not desirable when chips must be changed, either to repair faults or to alter performance. The ability to change or salvage a package is worth far more than any extra costs incurred by silicone-based gels. Rockwell's recent packages appear to use gel encapsulants instead of ceramic packaging [20]. For postmolded packages, silicone gel VLSI chip passivation could provide a stress-relief buffer coating hermetically equivalent to ceramics. The use of multichipping instead of wafer-scale integration will have an important impact on silicone-based gel encapsulation [20-24].

12.3 General Chemistry of Silicones (Elastomers and Gels) Commercial production of silicones is based on hydrolysis of chlorosilanes to the unstable disilanols, which condense to form siloxane oligomers and polymers. Depending on the reaction conditions, a mixture of linear polymers and cyclic oligomers is produced. The cyclic components can be ring-opened to linear polymers of commercial importance (Fig. 12.3). The linear polymers are typically liquids of low viscosity, unsuitable for use as encapsulants. They must be cross-linked (or vulcanized) to increase their molecular weight. Two methods are used: condensation cure and addition cure. For electronic applications the only suitable encapsulants are room temperature vulcanized (RTC) silicone, cured by

Silicone-Based Polymers in Elecfronic Packaging 2 8 5

(A) FORMATION OF SILICON: SiO2 § C (SAND) Coke

Si

'-~ Cu

§

CO 2

(B) FORMATION OF CHLOROSILANES: CH3CI

-t-

A

Si

CH3SiCI3 -I- (CH3)2 SiCI2 + (CH3)3SiCI

Cu

plus "Heavies" and "Lights"

(C) FORMATION OF SILOXANE POLYMERS (CH3)2SICI2 + H20

,===~ (CH3) 2Si(OH)2 § 2HCI[

ICondensation -H20

Figure

12.3

----->- Siloxanes § (Linear or Cyclic)

Commercial preparation of silicone.

c., o~i io;./os,,o o .. c.,>+c.,osi,

~L

CHdfl oi

s.,/ os,oc.,.

~LCHd

CH3

n

o

i CH3

I

i/H/1////////// / // /////////I// // / /////,

*'c.,ic~,lc,,

Substrata

', io-~,/-o' -

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0

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]

l////lli///////////// / / /l l l l l / / / / / / // Figure 1 2.4 Room temperature vulcanized (RTV) silicone: condensation cure mechanism and reaction with coated substrate mechanism.

alkoxide condensation, and heat cured silicone produced by platinum catalysis of a vinyl/hydride addition system. The curing of RTV silicone elastomer is moisture initiated and catalyst assisted. RTV silicone is one of the most effective encapsulants for temperature cycling and moisture protection of IC devices (Fig. 12.4). They have since been adapted for use in the electronics industry [2-4]. Ionic materials, whether from the device surface, encapsulation materials, or

286

MATERIALSFOR ELECTRONIC PACKAGING

the environment, affect the electrical reliability of encapsulated ICs. For this reason, the silicones are subjected to intense purification. The concentrations of Na+, K+, and CI- mobile ions are less than a few ppm, and alpha-particle emission is less than 0.001 cm -2 h -x. Thus it offers excellent alpha-particle shielding for eliminating soft error in dynamic random access memory devices, such as 64K, 256K, and megabit chips. The drawbacks of RTV silicone as an IC encapsulant are its poor solvent resistance and its weak mechanical properties. Highly fluorinated, alkyl substituted siloxanes have shown an improvement in solvent resistance. However, a recently developed silicone material with high cross-linking and high filler loading system seems to significantly improve the solvent resistance of the silicone encapsulant [24]. 12.4

Results a n d Discussion

12.4. I Cure Study of RTV Silicone

RTV silicone is a typical product of a condensation cure system. The moisture-initiated process is assisted by a catalyst, such as organotitanate or tin dibutyldilauranate, and generates water or alcohol by-products which could cause outgassing and voids. But careful control could achieve a very reliable encapsulant. Since the silicone has a low surface tension, it tends to creep and run over the encapsulated ICs. Thixotropic agents, such as fumed silica, are usually added to the encapsulant to improve its storage modules, G', loss modules, G", and dynamic viscosity, r/*. Filler-resin and filler-filler interactions are important in obtaining a well-balanced and controlled encapsulant (Fig. 12.5). Rheologically controlled material tends to flow evenly in each circuit edge. It tends to cover all the underchip area and prevents wicking and runover of the circuits, so critical to coating effectiveness. Opacifiers such as carbon black and titanium dioxide are usually added to protect the light-sensitive devices. Organic solvents such as xylenes and Freons are added to control the viscosity. Table 12.3 shows a typical RTV silicone system used by AT&T to protect its bipolar, MOS, and hybrid ICs for over 20 years. No device failure has yet been attributed to RTV encapsulation. ! 2 . 4 . 2 Cure Study of Heat-Curable Silicone

Heat-curable silicone (either elastomer or gel) has become an attractive device encapsulant as it cures much faster than RTV silicones and its thermal properties are slightly better. Silicone gel's jelly-like intrinsic softness (very low modulus) makes it attractive for encapsulating large, wire bonded devices. The two-part, heat-curable system contains vinyl and hydride functional groups and the platinum catalyst provides a fast cure with no by-products (Fig. 12.6). Usage of solventless, heat-curable gels has increased in electronic applications [7,24-27]. A low modulus silicone gel is formulated from a vinyl-terminated polydimethylsiloxane with a moderately low viscosity, from 200 to a few thousand centipoise (cP), and a mono- or multifunctional, hydride-terminated polydimethylsiloxane with a low viscosity (2-100 cP). The low viscosity hydride resin usually

Silicone-Based Polymers in Electronic Packaging

GOODMATERIAL

Io'

287

BADMATERIAL

103 -

ll

G

i

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lit

'7"

i~z

/ / G '

tb I0 ~

f

|

i

i

i,

0.1

Figure 12.5

i||1

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i

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r RAD/SEC

I

I

I

ililil

IO.O

|0 0

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i

i

I

iilili

O.I

i

1.0

i

I iilili

~ RAD/SEC

I0.0

I

I

i

i ,,,,J.

I00

Viscoelastic properties of good versus bad RTV silicones.

oH, LCH:CHdCH'(.~)"Pt"&% CH, LCH, /CH,

-~,lo-~T-~,_o

I

cH, L

i_~,_o

CHair" CH:

LCH:

_o ~,_o ~

icH:

m-n

m > n

( C U R E D G E L ) - (I) * *

Figure 12~

Table 12.3

Excess Hydrides Reactive "Pr' Calalyst

Heat-curable silicone: hydrolyzation additional cure mechanism.

RTV silicone formulations.

hlgredients Base polymer: OH-terminated siloxane Crosslinker: (OMe)sSiMe Catalyst: titanate Filler(s): SiO 2

TiO2 Carbon black Solvent: xylenes

Concentration (PHR)

Impact on properties

100 8-12 0.5

Mechanical properties Mechanical properties Curing, shelf-life

10-12 2-5 0.2-0.4 50-100

Rheological control Light screening Light screening Rheological control

288

MATERIALS FOR ELECTRONIC PACKAGING

blends in with the higher viscosity vinyl resin to achieve a desired mixing ratio of part A (only vinyl portion) and part B (hydride plus some vinyl portion). The key to formulating a low modulus silicone is the deliberate undercross-linking of a silicone system with low reactive functional groups. A few ppm of a premixed platinum catalyst system (platinum coordinated with 2-methyl-3-butyn-2-ol) is used to formulate a one-component silicone gel that requires less mixing.

12.5 Temperature Humidity Bias (THB) Testing Temperature humidity bias (THB) testing was performed with a triple track resistance measurement. I grounded the two outer tracks, biased the center track, and measured the leakage current change of the center conductor line. Good encapsulants show very low leakage over long testing times. Typical test conditions were 85~ 85% relative humidity, and 10-180 V bias. Of all the tested encapsulants, silicone had one of the best THB electrical performances. However, other high purity encapsulants, such as silicone-polyimide, benzocyclobutene (BCB), polyimide, and Parylene, also have relatively good electrical performance (Fig. 12.7).

12.6 Temperature Cycle Testing To be an effective encapsulant, a material must possess excellent temperature cycling properties. The siloxane backbone of the silicone provides good thermal stability (continued use temperature ~ 150~ among all potential elastomers. ---

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Silicone-Based Polymers in Electronic Packaging 2 8 9

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Temperature cycling test results of modified silicone elastomers over the temperature range -40~ to 130~ with a 20 min dwell time.

Polyimides, silicone-polyimide, and BCB have better thermal stability than silicone, but their modulus of elasticity is larger. With their intrinsic low modulus, silicone-based polymers have shown excellent performance in temperature cycling. Silicone samples cycled from - 4 0 ~ to 130~ with 20 min dwell time at each extreme show excellent results among potential encapsulants, see Figure 12.8 [24]. 12.7

Conclusion

I believe silicone-based polymers provide excellent IC protection and have the potential to replace hermetic ceramics. Even without hermeticity, reliability could be achievable with high performance silicone encapsulants [7,8]. But the real future may be a combination of multilayer inorganic passivating materials and polymeric organic coatings [27]. References

1. R.R Tummala and E.J. Rymaszewski (eds.), Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York 1989. 2. M.L. White, Proc. IEEE 57, 1610 (1969). 3. C.P. Wong, in Polymers for Electronic Applications, CRC Press, Boca Raton FL, 1989, Ch. 3. 4. C.P. Wong, J. Electronic Packaging 111, 97 (1989). 5. L.T. Manzione and D.J. Lando, A T&T Tech. J. 69(660) (1990). 6. N. Kinjo, M. Ogata, K. Nishi, and A. Kaneda, Adv. Polym. Sci. 88, 1 (1989). 7. C.P. Wong, J.M. Segelken, and J.W. Balde, IEEE Trans. Components, Hybrids and Manuf Technol. 4, 419 (1989). 8. J.W. Balde, IEEE Trans. Components, Hybrids, and Manu. Technol. 14(2), 352 (1991).

290

MATERIALS FOR ELECTRONIC PACKAGING

9. K. Otsuka, H. Ishida, Y. Utsumi, T. Miwa, and Y. Shirai, A CS Syrup. Ser. 407, 240 (1989). 10. C.P. Wong, J. Mater. Res. 5(4), 795 (1990). 11. T. Yamada et al., in Proc. Int. Syrup. Electronic Packaging, Orlando FL, 1986. 12. R.G. Mancke, IEEE Trans. Components, Hybrids, and Manuf. Technol. 4(4), 492 (1981). 13. D. Jaffee and N. Soos, IEEE Proc. Electronic Components Conf. 213 (1978). 14. C.P. Wong, Int. J. Hybrids and Microelectronics, 4(2), 315 (1981). 15. C.P. Wong and D.E. Maurer, in Semiconductor Moisture Measurement Technology, Special Publication 400-72, National Bureau of Standards, 1982, p. 275. 16. C.P. Wong, ACS Syrup. Set. 184, 171 (1982). 17. C.P. Wong, ACS Org. Coat. Appl. Polym. Sci. Proc. 48, 602 (1983). 18. C.P. Wong and D.M. Rose, IEEE Trans. Components, Hybrids, and ManuJl Technol. 6(4), 485 (1983) and references therein. 19. L.E. Gates and T.G. Ward, in Proc. 41st Electronic Components and Technology Conf. IEEE, 1991, p. 198. 20. J.K. Hagge, in Proc. 38th Electronic Components Conf., IEEE, 1988, p. 282. 21. C.A. Neugebauer, IEEE Trans. on Components, Hybrids, and Manuf. Technol. 10(2), 184 (1987). 22. K.L. Tai and C.P. Wong, in Proc. 6th Microelectronic Conf. Tokyo, 1990, p. 26. 23. C.P. Wong, A CS Syrup. Set. 407, 220 (1989). 24. A.W. Lin and C.P. Wong, in Proc. 41st Electronic Components and Technology Conf., IEEE, 1991, p. 820. 25. C.P. Wong, A CS Syrup. Set. 407, 220 (1989). 26. C.P. Wong, Mater. Res. Soc. Proc. 154, 195 (1990). 27. C.P. Wong (ed.), in Polymers for Electronic and Photonic Applications, Academic Press, New York, 1992, Ch. 4.

13 Dielectric Films for High Temperature, High Voltage Power Electronics Javaid R. Laghari, Jayant L. Suthar

13.1

Introduction

Dielectric materials are used not only in conventional energy storage and transport systems but also in high voltage power electronics; revolutionary improvements are essential to keep up with the demands of terrestrial and space systems [1,2]. To increase energy storage, dielectric materials often have a high permittivity, but in microelectronics [3] they serve as passivation layers and packaging material, so they have a low dielectric constant to minimize Signal propagation delay, interconnect capacitance, and crosstalk [4]. They are also required to have high impedance (volume resistivity) to reduce the power loss, usually heat, at high voltage and sometimes at high frequency [5]. In spacecraft, materials for multikilowatt power systems need to cope with this joule heating of the dielectric. Heat is also generated by power processing devices, such as nuclear reactors [6]. To meet the high power demand of space systems it has become necessary to use nuclear reactors as the prime power source [7]. Despite their long lifetime, good reliability, and cost-effectiveness, they place a great burden on the thermal management of the space system due to their compactness and their low waste heat rejection [6]. Spacecraft reactors are likely to run at much higher temperatures than terrestrial reactors [8]. In the area of power sensors and controls, these temperatures may well be above 250~ [7]. A single point failure in the dielectric system, such as in cables and capacitors, may very well prove catastrophic for the whole mission or part of the system [9]. To ensure smooth and reliable operation it is important to characterize all dielectric films used in capacitors, cables, microelectronics, and power electronics near to or surrounding high temperatures and voltages [8]. Polyimide (Kapton) is the most commonly used dielectric at high temperatures in space systems, but has been reported to arc-track and crack under high temperatures and humidity [10,11]. In a number of circumstances, Kaptoninsulated systems are also susceptible to fire hazard due to intense and repeated 291

292

MATERIALS FOR ELECTRONIC PACKAGING

Table

13.1

Key properties of the dielectric films. PFA

PPX

PBI

310 260

420 260

>600 315-370

Relative permittivity Dielectric loss Dielectric strength (V/#m)

2.0 0.0002 157-196

2.65 0.002 275

4.4-16.2 0.024-0.57 157-275

Tensile strength (10v N/m 2) Density (g/cm3)

2.7-4.8 2.2

4.68 1.2

Melting point (~ Maximum service temperature (~

11.7-18.6 1.2

arc-tracking [12]. Therefore, there is a need to find alternative high temperature dielectric films, which can maintain physical integrity and dielectric properties, as well as offer reliability over the wide range of temperature applications. Three high performance films, Teflon perfluoroalkoxy (PFA), poly p-xylylene (PPX), and polybenzimidazole (PBI), were selected for further high temperature, high voltage evaluation after a detailed literature search. PFA is similar to Teflon (PTFE) but has superior electrical and mechanical properties [13]. PPX is used for some low voltage terrestrial microelectronics, such as coating printed circuit boards and barrier protection [-14]. PBI has been mainly used as a thermal blanket for missile applications [15], but so far has not been employed for high voltage power electronics. Some key properties of these dielectric films are listed in Table 13.1 [13,14,16], but very little information is available on high voltage dielectric characterization at high temperatures. The experimental investigations included dielectric properties for PFA and PPX, such as permittivity and dielectric loss, measured in the frequency range 0.05-100 kHz and at temperatures up to 200~ The AC dielectric strength was obtained in the high temperature regime to 250~ Since PBI allows higher maximum service temperature, its dielectric properties were obtained at temperatures up to 250~ and the dielectric strength was comfortably measured at temperatures up to 300~ Confocal laser microscopy was performed to diagnose voids and microimperfections within the film structure. The physicochemical changes at high temperature were investigated using X-ray diffraction and IR spectroscopy. The results obtained are presented in a comparative fashion. The investigation carried out in this chapter is best oriented to give an experimental evaluation as well as a general assessment of the high voltage performance of PFA, PPX, and PBI films at high temperatures.

13.2 Experimental The electrode assemblies employed for dielectric characterization and breakdown studies are illustrated in Figure 13.1. The details of the electrode assemblies are given in [ 17]. PFA and PPX films, 25.0 #m thick, and PBI film, 37.0 #m thick,

Dielectric Films for High Temperature, High Voltage Power Electronics 2 9 3

(a)

~ l l i l l l l

l

HV

l J

t t t t t

t t t t t t

t

t / I t ' / d

(b) Figure 13.1 (a) Electrode assembly for dielectric measurements: (U) upper electrode, (C) center electrode, (R) ring electrode, and (G) ground electrode; the diameter of the center (active) electrode is 25.4 mm. (b) Electrode assembly for breakdown studies: (HV) high voltage end and (GND) ground or low voltage end; electrode diameter is 25.4 mm.

were used in this work. The properties that were measured include the permittivity and dielectric loss as a function of frequency, and ~the dielectric strength at 60 Hz. The permittivity and dielectric loss were measured at room temperature using a GenRad 1689 Precision RLC Digibridge at eight different frequencies in the range 0.05-100 kHz. This is the frequency range of interest for users of high power electronic components, and covers the frequency spectrum from power frequency to switching surges. The surfaces of PPX and PBI specimens were coated with silver-loaded paint, whereas the smooth, nonadhesive surface of PFA film was deposited with 100 nm thick aluminum electrodes to ensure good contact for all dielectric measurements. These properties were further characterized under high voltage, high temperature conditions using a Tettex Instrument precision measuring system, type 2822. The Tettex system is a high voltage, high temperature bridge calibrated for power frequency. The measurements were performed at temperatures up to 250~ using 200 V, 60 Hz. The breakdown voltages of the films were obtained by employing a Hipotronics AC dielectric test set, model 7100-20A. A bath of silicone fluid 210H, a high temperature dielectric oil supplied by Dow Corning, was used along with a temperature controller to obtain the desired test temperature within _+2~

294

MATERIALS FOR ELECTRONIC PACKAGING

During each breakdown test, the specimen was sandwiched between the two cylindrical stainless steel electrodes, in accordance with standard ASTM-D149, and the voltage was raised at a rate of 500 V/s until the sample failed. The values reported for breakdown are the average of seven data points. A BioRad MRC-500 unit was used to carry out confocal laser microscopy on the samples. The film sample was heated at 250~ in silicone oil for 5 rain before scanning to simulate the effect of high temperature on film structure. An argon ion laser having 25 mW power capability, 488 nm and 514 nm wavelengths, was utilized to scan layers of the microstructure. The confocal microscope employed a Nikon Fluor 40x lens with a numerical aperture of 1.3. The sample was placed on an aluminum slide fixture. The film surface to be scanned was covered with Zeiss Immersionsoel (ne = 1.518) to get sharp images of the microstructure. X-ray diffraction studies were carried out using a GE XRD-3 diffractometer employing copper K~ radiation and symmetric reflection geometry. A nickel filter was used to isolate the copper K~ radiation (2 = 0.154 nm). The sample size used in the X-ray diffraction was 3.0 cm x 2.5 cm. The scattering angle (20) was scanned from 5 ~ to 40 ~ To detect temperature-induced chemical changes, IR spectra of the preheated films were obtained on a Perkin-Elmer spectrometer. The samples were scanned in a wavenumber range from 500 cm-~ to 2000 cm-~. 80

23

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Dielectric Films for High Temperature, High Voltage Power Electronics 29S

1 3 . 3 Results and Discussion The dielectric properties of polymers are often a direct consequence of their physicochemical state, therefore the physicochemical analysis is reported first, followed by the dielectric properties. All three films have similar physicochemistry, so only the PFA results are presented. The X-ray diffraction technique, in reflection mode, was used to monitor different peaks on different films. The X-ray diffraction pattern shown in Figure 13.2 illustrates the intensity curve for PFA film at three different temperatures. It can be seen from the figure that the wt.% crystallinity changes very little at high temperatures as the peak at 21 ~ decreases slightly for the high temperature sample. This implies the morphology of the material does not experience any noticeable alteration near its maximum operating temperature. The IR spectra of the PFA film are shown in Figure 13.3. No significant changes appear in the chemical groups of PFA film. Absence of the carbonyl group ( C - - O ) near 1700 c m - ~ can be seen in the high temperature sample; this is primarily because the film was preheated in the silicone oil. Similar results were also observed for the PPX film. The presence of microvoids within the film structure can greatly affect high voltage dielectric properties of polymer film [18,19] so their determination is 100

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Figure

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296

MATERIALS FOR ELECTRONIC PACKAGING

(a)

(b) Figure 13.4 Confocal laser microscopy assessment of PFA film at 10 pm depth from the specimen surface: (a) 23~ specimen and (b) 250~ specimen.

Dielectric Films for High Temperature, High Voltage Power Electronics 2 9 7

crucial. Microvoids in PFA and PPX were identified by confocal laser microscopy. Confocal images of PFA (Fig. 13.4) obtained at 10 pm below the surface confirmed the presence of submicrometer voids that expanded when the film was preheated to 250~ The growth in size of voids could contribute to a higher dielectric loss at high temperatures, as voids are usually the major reason for partial discharge inception and failure in dielectric materials [19]. 1 3 . 3 . 1 Electrical

Nondestructive dielectric characterization included relative permittivity and dielectric loss measurements as a function of frequency and temperature; destructive characterization included dielectric strength measurements at 60 Hz. Repeated measurements showed very little deviation, so for greater clarity in Figures 13.5 through 13.8 we report only a single data point at each frequency and temperature. Conversely, the statistical deviation of the breakdown measurements leads us to report the mean of seven data points. The variation in relative permittivity of the specimens with increasing frequency at room temperature is shown in Figure 13.5. It can be seen that none of the materials exhibits any noticeable change in its relative permittivity with frequency. Figure 13.6 shows the effect of temperature on the relative permittivity of the three films. PFA displays good stability with temperature but the other films exhibit modest changes in their permittivity. The permittivity of PBI seems to increase initially then to remain constant with increasing temperature. The permittivity of PPX remains unchanged up to 100~ then undergoes a slight

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RelativepermittivityofPFA,PPX, andPBIasafunctionoffrequencyat22~

298

MATERIALS FOR ELECTRONIC PACKAGING

4.2

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Temperature (oC) Figure 13.6 Dependence of relative permittivity of PFA, PPX, and PBI on temperature while stressed at 200 V, 60 Hz.

10 0

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Frequency (Hz) Figure 1 3 . 7 Comparison of dielectric loss of PFA, PPX, and PBI as a function of frequency at 22~C.

Dielecfric Films for High Temperature, High Voltage Power Elecfronics 2 9 9

10 0

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Figure 13.8 Dielectric loss of PFA, PPX, and PBI as a function of temperature while stressed at 200 V, 60 Hz.

increase as the temperature is further raised. Polymers in general tend to soften at high temperature and could undergo some degradation which may, in turn, contribute to a change in permittivity [18]. The presence of electrical stress might have contributed to the variation in this property [19]. The dielectric loss of the films as a function of frequency is plotted in Figure 13.7. PBI demonstrates the highest dielectric loss of the three films tested, but is found to be the most stable over a wide frequency range. The dielectric loss of PFA increases by about one order of magnitude with increasing frequency. And the dielectric loss of PPX decreases as the frequency rises to 10 kHz, then beyond this value it starts to increase modestly. The influence of temperature on the dielectric loss is shown in Figure 13.8. PPX displays the largest change in its dielectric loss with an increase in temperature, whereas PFA and PBI exhibit only slight increases. PBI shows the greatest loss of the three materials, whereas PFA exhibits the lowest loss at high temperatures. The increase in the dielectric loss is generally attributed to an increase in free carrier concentration, which often accelerates the breakdown phenomenon [20]. And, when the film is preheated, some of the voids expand and grow in size up to a few micrometers (Figure 13.4(b)). The presence of voids is also believed to be responsible for an increase in the dielectric loss at high voltages [21]. So for any film, the presence of voids appears to increase the dielectric loss at high voltages and high temperatures. The dependence of dielectric strength on test temperature is shown in Figure 13.9. The breakdown sites were randomly distributed over the surface of the test

300

MATERIALS FOR ELECTRONIC PACKAGING

300

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200

-

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-

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100

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300

350

Temperature (oC) Figore 1 3.9 Temperature dependence of AC dielectric strength of PFA (25.0 l~m), PPX (25.0 ltm), and PBI (37.0 ltm). specimen at all temperatures. The data obtained show that PFA in particular undergoes a significant reduction in its breakdown voltage with an increase in temperature. The reduction in dielectric strength of PFA is about 50% at 250~ compared to its strength at room temperature; PPX and PBI do not exhibit such a large change. Most often, the decrease in dielectric strength can be attributed to the softening of the polymers when exposed to high temperatures [22]. A plausible explanation for the negative temperature dependence goes like this. When the applied voltage is raised, more energy is stored in the sample and more dielectric loss is converted into heat. This heat raises the sample temperature which cannot be dissipated outside due to the higher surrounding temperature. Consequently, at one instant, the so-called critical temperature, the leakage current increases rapidly and leads to the breakdown of the sample [23]. Therefore, thin dielectric films used in microelectronics are susceptible to runaway thermal breakdown. 1 3.4

Summary

The results obtained from the present studies on the three films (PFA, PPX, and PBI) indicate few changes in their key properties at high temperatures and high voltages. Their permittivities remain unaffected when the frequency is increased to 100 kHz. PBI displays the highest relative permittivity, 3.4, and PFA shows the lowest permittivity, 2.1. The permittivities of PPX and PBI films exhibit a modest positive temperature dependence when the temperature is raised. In comparing dielectric losses of the materials as a function of frequency,

Dielectric Films for High Temperature, High Voltage Power Electronics 301

PFA shows an increasing trend and PPX exhibits a little decrease. On the other hand, the dielectric loss of PBI remains constant when the frequency is increased, but its dielectric loss is the highest. Nevertheless, all three materials display different increasing trends for dielectric loss with temperature. The dielectric loss of PPX increases by one order of magnitude; and for PFA and PBI, it goes up by approximately half an order of magnitude. In PFA, dielectric strength, a key property for high voltage applications, shows strong negative temperature dependence. But in PPX and PBI, dielectric strength remains relatively stable with an increase in temperature up to 250~ It is interesting to note that PBI exhibits a higher dielectric strength than the other two materials at any test temperature in the temperature range 23-250~ Good dielectric properties, especially with a lower dielectric loss, could make PFA film more viable for low voltage, high temperature applications. However, the stability of the dielectric strength of PPX and PBI at high temperatures could make them more useful for high voltage, high temperature, power applications on earth and in space.

Acknowledgment This work was supported by the NASA Lewis Research Center under grant NAG3-1019.

References 1. A.K. Hyder, Jr., P.J. Turchi, and H.L. Pugh, in Proc. AFOSR Special Conf. Prime Power for High-Energy Space Systems, Norfolk IrA, 1982. 2. E. Sugimoto, IEEE Electrical Insulation Mag. 5(1), 15-23 (1989). 3. R.J. Jensen, in Chemical Engineering in Electronic Materials Processing, edited by D.W. Hess and K.V. Jensen, ACS, Washington, 1988. 4. S.D. Senturia, in Polymers for High Technology, edited by M.J. Bowden and S.R. Turner, ACS, Washington, 1987. 5. E. Kuffel and M. Abdullah, High Voltage Engineering, Pergamon Press, New York, 1981. 6. V.C. Truscello and H.S. Davis, IEEE Spectrum, Dec. 1984, pp. 58-65. 7. H.W. Brandhorst, "Power Technology DivisionBAn Overview of Industrial Reviews," a workshop at NASA Lewis Research Center, Cleveland OH, Feb. 1988. 8. A.N. Hammoud, E.D. Baumann, I.T. Myers, and E. Overton, in Trans. 1st International High Temperature Electronics Conf., Albuquerque NM, 1991, pp. 11-16. 9. F.M. Ott, S.P.S. Yen, and R.B. Somoano, IEEE Trans. Electrical Insulation, 20(1) 47-54 (1985). 10. F.J. Campbell, NRL Review, July 1989, pp. 117-118. 11. J. Van Laak, "Kapton Wire Concerns for Aerospace Vehicles, Wiring for Space Applications," a workshop at NASA Lewis Research Center, Cleveland OH, July 1991. 12. "Aircraft Wire Hazard Reported," Chicago Tribune, July 25, 1988. 13. "Teflon PFABFluorocarbon Resins," DuPont Properties Bulletin E80419, Dec. 1986.

302

MATERIALS FOR ELECTRONIC PACKAGING

14. "Abrasion Resistance of Parylene and other Conformal Circuit Board Coatings," Nova Tran, Wisconsin, Bulletin NTC#400-0114-00, 1986. 15. J.F. Jones, J.C. Waldrop, and R. Fountain, in Proc. 29th National SAMPE Symp., 1984, pp. 777-783. 16. E.J. Powers and G.A. Serad, in High Performance Polymers: Their Origin and Development, edited by R.B. Seymour and G.S. Kirshenbaum, Elsevier, New York, 1986. 17. J.R. Lagari et al., IEEE Electrical Insulation Mag. 2(6), 16-20 (1986). 18. P.J. Phillips, in Engineering Dielectrics, Vol. IIA, ASTM, 1983, Ch. 2. 19. R. Bartnikas, in Engineering Dielectrics, Vol. IIA, ASTM, 1983, Ch. 1. 20. J.L. Suthar and J.R. Laghari, in Proc. Electrical Insulation and Dielectric Phenomena Conf., Leesburg VA, 1989, pp. 495-502. 21. R. Bartnikas, in Engineering Dielectrics, Vol. I edited by R. Bartnikas, ASTM, 1979, Ch. 1. 22. J.L. Suthar, J.R. Laghari, and W. Khachen, Proc. Electrical Insulation and Dielectric Phenomena Conf., Knoxville TN, 1991, pp. 244-249. 23. J.J. O'Dwyer, The Theorv of Electrical Conduction and Breakdown in Solid Dielectrics, Oxford University Press, London, 1973.

14 Electrically Conducting Polymers and Organic Materials M. J. Naughton

14.1

Introduction

Organic and polymeric substances are no longer thought of simply as electrically insulating materials. In fact, some of the most exciting and innovative research in physics, chemistry, and materials science can be found in the fields of organic, molecular, and polymeric conductors. In the past few decades, there has been a steady increase in the number of highly conducting, synthetic organic materials, highlighted in 1980 by the discovery of superconductivity in the quasi-one-dimensional charge transfer salts (TMTSF)2X. Since then, organic conductors have been shown to possess an astonishing variety of electronic, magnetic, and optical properties, including some not observed in any other solidstate material. This chapter considers recent advances in the organic conductors and looks at several families of organic superconductors. As well as their novel electric and magnetic properties, organic systems essentially exhibit all the basic conducting states recorded for inorganic materials (elements, alloys, and compounds); organic systems can be insulating, dielectric, semiconducting, semimetallic, metallic, superconducting, and so on. We distinguish here between polymeric and organic conductors because most of the organic materials we discuss are crystalline dimer salts (charge transfer salts), and their conduction processes are more conventional. There has also been progress in the conducting properties of formal polymers, for example, the room temperature conductivity of doped polyacetylene, [CH]x, now approaches that of copper. As yet there are no polymer superconductors, but polymers are generally recognized to hold more promise than molecular crystals, as their properties can be tuned by doping and they are much easier to process. We include in the general category of conducting organic and molecular materials two forms of carbon known to be electrically conducting: intercalated graphite and buckminsterfullerene (buckyballs). In suitably doped forms, both systems are known to superconduct, and fullerene transition temperatures exceed 30 K. 303

304

MATERIALS FOR ELECTRONIC PACKAGING

In microelectronics and thin film technology, organic and polymeric conductors still lag behind their inorganic counterparts like gallium arsenide. Sensing the potential for significant contributions, theorists and experimenters are hard at work. The interested reader can find several volumes of various conference proceedings on low dimensional conductors, superconductors, organics, and polymers, and more recently, molecular conductors. Perhaps the most informative sources are the ongoing series from the International Conferences on Synthetic Metals, held biannually [ 1]. These conferences are evenly split between the physical properties of conducting polymers and the physical properties of conducting organic crystals. Other useful sources are the monographs and edited collections listed at the end of this chapter [2]. Several thousand years ago, the Greeks were aware that certain nonconducting materials could hold electrostatic charge. Many of these materials were in fact organic polymers, such as amber, from which the word electron was later derived. This characteristic of organic polymers remains the norm, as we all know from the many plastics we encounter and use in everyday life. There has traditionally been a rather clear distinction between conducting and nonconducting materials: metals do and plastics don't. A computer keyboard is made of little plastic keys in a plastic molded case. Every time you type a letter, this nonconducting key is pressed down to activate a switch, with information transmitted (in the form of electrons) to the central processor via metallic wires, probably copper. You don't get electrocuted when you type because the plastic exterior of the keyboard is electrically insulating. We now understand why an insulator holds a charge, rather than moves a charge; it has no available free electrons for motion. While metals have plenty of free electrons (on the order of 1022 per cubic centimeter), insulators can have 10-20 orders of magnitude fewer. This insulating property of organic polymers is exploited in your computer and countless other situations. So, organic polymers such as rubbers and plastics are most familiar to us as nonconductors of electricity; they usually have the ability to store electric charge, but not to move it. Such is not always the case. Early attempts at making polymers conduct electricity involved mixing metallic material with insulating polymer fibers, forming composites. Some polymers were found to have ionic properties, but none could be considered electronically conducting. Then in 1973 polysulfurnitride (SN)x was found to be metallic [3] and two years later superconducting [4], discoveries which played important roles in promoting efforts toward the creation of useful conducting polymers. Most of the successful materials are polyenes, in particular polyacetylene, the polymer of acetylene. Other related systems include polyphenyleni~, polypyrrole, and the polyimides. There is now a very large effort throughout the world in basic and applied research on conducting polymers, research which requires the combined efforts of chemists, physicists, materials scientists and, in many cases, biologists. The combined effort to develop polymeric conductors is many times larger than to develop organic crystals, due mainly to the perceived technological advantages and versatility of polymers.

Electrically Conducting Polymers and Organic Materials

305

14.2 Organic Conductors and Superconductors Some of the first reports of electrical conduction in organic solids appeared in the late 1940s. Semiconducting behavior was observed in the phthalocyanine molecule [5,6] and in aromatic carbon structures (perylene) [7]; photoelectric conduction was observed in organic dye films [8]. Since then, we have reached just about one milestone each decade: synthesis of TCNQ in the 1960s, synthesis of TTF in the 1970s, discovery of organic superconductivity in the 1980s, and the first organic superconductor with a transition temperature above 10 K in the 1990s. Though a landmark in its own way, polysulfurnitride is inorganic. The organic content in a large number of present-day organic conductors is a sulfur- or selenium-based donor molecule (cation); electrocrystallization with an appropriate anion acceptor forms a charge-transfer salt, which may be organic or inorganic. In contrast to polymers, which form large macromolecules, these molecular solids retain as building blocks their original donor molecules. In general, electrical conduction results from g-electron molecular orbital overlap along near-neighbor Se or S sites, rather than involving directly the C ~ C or C ~ C bonds (i.e. single or double carbon bonds). The delocalized orbitals are arranged along stacks (quasi-one-dimensional, quasi-l-D) or in planes (quasi-twodimensional, quasi-2-D), leading to anisotropic conductivity, conductivity that depends on measurement direction. In the past 20 years, starting with the salt TTF-TCNQ (tetrathiofulvalenium-tetracyanoquinodimethane), many organic salts with partially filled conduction bands, responsible for their large electrical conductivity, have been synthesized. The building blocks for all these organic conductors have long chemical names, which are routinely abbreviated for common usage. The best-known molecules are depicted in Figure 14.1. These salts can be rather easy to grow. With relatively inexpensive equipment, respectable quality (i.e. millimeter to centimeter size) single crystals can be synthesized in about a week. But there are difficulties with the exploitation of organic conductors for electronic packaging and other applications. It has proven quite difficult to design a route toward the fabrication of a processible material, such as a thin film. The nucleation process in the electrocrystallization is very poorly understood, and some methods employed for polymer films, such as the LangmuirBlodgett technique, have yielded little success. This is one obstacle which requires a concerted, interdisciplinary effort to overcome. To date, there are only a handful of families, or basic molecules, from which highly superconducting organic materials are synthesized. These are based on the donor molecules TMTSF, tetramethyltetraselenafulvalene; BEDT-TTF, bisethylenedithiotetraselenafulvalene, DMET, dimethyl(ethylenedithio)diselenadithiafulvalene, MDT-TTF, methylenedithio-tetrathiafulvalene, and the acceptor system M(dmit)2, metal-bis(dimercaptodithiolethione). The terms donor and acceptor refer to electron transfer, hence charge transfer salts. The first four of these molecules .form conducting solids by acting as electron donors (the cation), with an anion species acting as the acceptor. Collectively, there are nearly 50 organic supercon-

306 MATERIALSFOR ELECTRONICPACKAGING HC ~

:c

H/CXs/

/S\c/H

H2C C \

_/S\ / S

/Se"c/

~s/C\H

HL'C\s/C\ /

Xk~/C\cH 3

TTF

CH3

DMET

H\Cc /~S e / Sex /H

/Sxc/S~

/S\c/H

H/Cxs/

\s/C\/

Xs/C\ H

\se/C\ H TSF

MDT-TTF

H3Cc/S\ \ II

S\ ./0-4 3

"c= / ~" TMTTF

s/ \CH3

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!1

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NC\

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\c

/CN

~/C\ / C : C~ / ::=C\ ~e CH3 NC H/~,:,:CXH CN

TMTSF

HL~/S\c/S~

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/S\c/S \

CH2 I II e---c II I HL'Cs/C\ ', S/ Xs/C\s/CH,

TCNQ

BEDT-TTF (ET) Figure 14.1 The building blocks of organic conductors and superconductors, from [2(b)].

ductors. There are several other organic-based materials which are not such good electrical conductors, instead they have special magnetic properties such as ferromagnetism. An example is a molecular magnet based on the TCNE (tetracyanoethylene) molecule [9]. A common property of all organic conductors is their low dimensional structure. For this reason, they have been a boon to both experimental and theoretical scientists, providing physicists with real physical systems in which to test existing theories concerning electron motion confined to one and two dimensions, encouraging chemists to experiment with bond arrangements in the molecular structure in order to obtain favorable physical or chemical properties, and enlisting materials scientists to consider the mechanical and processing properties of the new materials. Like nearly all endeavors in materials science, an interdisciplinary effort has developed in the recent past, and indeed is desperately needed in the immediate future, for the study and exploitation of organic conductors.

Electrically Conducting Polymers and Organic Materials 3 0 7

14.2.1 TMTSF Compounds The world's first organic superconductors were found in the TMTSF family, discovered almost two decades after William Little's 1964 prediction [10] of a mechanism for high temperature superconductivity in polarizable quasi-l-D polymers. This family of organic metals was first synthesized in 1980 by a Copenhagen team under Klaus Bechgaard [11] and the salts now bear his name. They are quasi-l-D, 2:1 charge transfer compounds, with (TMTSF)2 + combining with a monovalent anion such as AsF6-, PF6-, C104-, ReO4-, NO3-. In these crystals, the TMTSF molecules stack up like poker chips, providing a more or less linear path for n-orbital conduction along the selenium atoms. A n-orbital is a way of describing the shape of the electron trajectory (actually its probability density) with respect to the molecule. The nomenclature has to do with the angular momentum of the molecular orbital, which itself is formed from individual atomic orbitals. The n-orbitals in the TMTSF system look like airplane propellers projected out of the plane of the TMTSF molecule. If a portion of a propeller near molecule A overlaps with that near an adjacent molecule B, then the electron in orbital A can move to orbital B, and so on. In these materials, the overlap along the stack direction is large enough to facilitate metallic conduction in this direction (in fact, these n-orbitals form what are called a-type overlap, in that the propeller arms touch end to end, rather than side to side). The orbital overlap in the two perpendicular directions is significantly reduced compared to the stacking direction, hence the quasi-l-D description. However, one of these two perpendicular directions has approximately 10 times the conductivity of the other, as a result of significantly smaller Se-Se contact distances, so these materials can also be considered as quasi-2-D (the molecular stacks along the a-direction form sheets with repeat units along the b-direction, yielding 2-D a-b planes). This is an important consideration when these metals are placed in a large magnetic field at low temperature, where most of the interesting physics is observed. The overall conductivity anisotropy is given by aa:ab:ac= 105:103:1, which means that electrons flow 10000 times more easily along the a-axis than along the c-axis. While the room temperature conductivity of single crystals of the (TMTSF)2X conductors is metallic (103 to 104 S/cm, which is about a thousand times less conducting than copper), many members (i.e., salts of different anions X) undergo metal-to-insulator transitions at cryogenic temperatures, in the range 10-100 K. This is due to their quasi-l-D character, which leaves the system susceptible to electronic instabilities such as charge density waves or spin density waves. Known as Peierls transitions, they can be described rather naively by considering a real one dimensional chain. If you break one link in a chain, the continuity is lost. If each link represents a molecule, breaking a link is like breaking a bond; it prevents electrons hopping from one molecule to the next and it produces an insulator. In a two-dimensional lattice structure, several bonds or links can be broken before continuity is lost at a percolation threshold. It was only after increasing their 3-D character by the application of large hydrostatic pressure, on the order of several thousand bars (atmospheres), that Peierls transitions were suppressed and super-

308

MATERIALS FOR ELECTRONIC PACKAGING

C

4-

44Figure 14.2 The a - c plane and unit cell of (TMTSF)2CIO 4, the first ambient pressure organic superconductor.

conductivity was discovered in (TMTSF)2PF6 [ 12]. This significant discovery, also in 1980, occurred at Orsay, in the laboratory of Denis Jerome. The superconducting transition temperature (T~) was 1.3 K at 6 000 bar. The highly anisotropic crystal structure of this material is shown in Figure 14.2. Since that seminal discovery, which finally demonstrated the possibility of organic superconductivity, half a dozen other TMTSF superconductors have been found. All have superconducting transition temperatures in the vicinity of 1 K, but this is far from the original prediction of T~ near room temperature (~ 300 K). As it has turned out, the existence of superconductivity may not even be the most interesting property of the Bechgaard salts; they exhibit many other electronic and magnetic phenomena, all of them due to low dimensionality. (TMTSF)EPF 6 and (TMTSF)2CIO4 are the first and only bulk, crystalline materials to exhibit the quantized Hall effect, elsewhere observed only in very thin, in fact two-dimensional, artificially grown semiconductor systems such as GaAs and Si metal oxide semiconductor field effect transistors (MOSFETs). As it produces such constant plateaux in the Hall resistance of these semiconductors, the quantized Hall effect is now used as the world standard for resistance, the ohm, as well as for the most accurate determination of the fine structure constant ~, which plays an important role in the quantum theory of matter. Unique to TMTSF conductors, and perhaps their most interesting phenomenon, is the so-called magnetic field-induced spin density wave (FISDW). Similar to when a normal metal changes into a superconducting metal, this is an electronic phase transition induced by a large magnetic field aligned perpendicular to the highly conducting quasi-l-D chains and along the least conducting c-direction. The magnetic field causes a complete destruction of the nonmagnetic, metallic Fermi surface, yielding an antiferromagnetic SDW state of alternating spin alignment, T$ T~T$ T,L. In a low magnetic field the spins are oriented randomly, so the system is nonmagnetic. The field strengths for this transition are on the

Electrically Conducting Polymers and Organic Materials

309

(TMTSF)2C104 m

metal

5

i

-I

4

t

FISDW

I

10

I

20

I 30

40

H(T)

Figure 14.3 Magnetic phase diagram of (TMTSF)2C10 4, from [13]. The enclosed region represents a spin density wave, an antiferromagnetic state induced by an applied magnetic field. The line near T = 1 K depicts the superconducting state.

order of 10T (105 gauss, the field on the earth is about 0.5 gauss), and the temperature regime is below 10 K. Bechgaard salts show several other novel effects but we mention them only briefly. One is the mysterious destruction of this FISDW at yet higher fields, fields above 25 T [ 13]. It appears that the very same mechanism responsible for the creation of the field-induced spin density wave leads to its demise. The very high field state is thought to be a purely one-dimensional material, with each electron literally confined to a single chain. The experiments which led to the discoveries of these electronic states required the world's largest magnetic fields and the National Magnet Laboratory at MIT. Another new feature is the so-called commensurability resonance, or magic angle effect, in which a series of dramatic changes in the conductivity and magnetization occur as a specimen is rotated in a fixed magnetic field [14]. Much theoretical effort has been invested in understanding the many novel electronic phenomena seen in the Bechgaard salts, largely because physicists realize their fundamental origin is low dimensionality. This system thus provides a real physical testing ground for interactions between electrons, which are not easily observable in ordinary metals. Figure 14.3 shows a cumulative phase diagram of one of these organic conductors in magnetic field-temperature space. 1 4 . 2 . 2 BED?'-TTF Compounds

In TMTTF, the sulfur analog of TMTSF (Fig. 14.2), methyl groups (CH3) at the corners of the molecule can be replaced by ethylene (CH2) if the fourth carbon bond in the ethyl is satisfied by closing the end rings, forming a pair of C H 2 m C H 2 bonds. This is the structure of BEDT-TTF, or [(CH2)212C688, first

310

MATERIALS FOR ELECTRONIC PACKAGING

synthesized in 1983 by G. Saito and coworkers in Japan. While related to TMTSF in many ways, compounds formed with BEDT-TTF are dramatically different from the Bechgaard salts. First, they rarely exhibit linear chain stacking, instead they form infinite two-dimensional sheet networks. In fact, this was the original intention: to increase the dimensionality with respect to the TMTSF salts, in the hope of increasing the superconducting transition temperatures. Second, they crystallize in a variety of morphologies, with different molecular packing arrangements and stoichiometric possibilities. These lead to a wide range of conducting properties, from insulating to superconducting. Perhaps more importantly, the superconductivity [15] which has been discovered in these materials occurs with transition temperatures an order of magnitude higher than in the TMTSF salts [ 16]. They have transition temperatures approaching 15 K, excluding the fullerenes, the highest of the organic superconductors. There have been over 20 BEDTTTF-based superconductors synthesized so far, with contributions coming from groups in the United States, France, Japan, Germany, and Russia. Besides the great excitement over the consistent rise in superconducting transition temperatures in organic conductors, mainly but not entirely due to progress in the BEDT-TTF salts, there are some quite interesting aspects to the normal metallic state properties in (BEDT-TTF)zX. Due to the fact that metallic organic crystals can be grown with exceptionally high purity, and the dimensionality is so very nearly 2, there are very clear Shubnikov-de Haas (SdH) resistance oscillations de Haas-van Alphen (dHvA) magnetization oscillations in large magnetic fields. These are quantum oscillations that result from magnetic energy levels crossing the constant energy surface (Fermi surface) as a magnetic field is increased. Such measurements provide invaluable information on electronic band structure and the shape of the Fermi surface. Magnetic quantum oscillations have been observed in several (BEDT-TTF)zX salts, including X=I3, AuBr2, and Cu(NCS)/. In addition to these SdH and dHvA oscillations, a new magnetotransport effect has been observed in high magnetic fields in the BEDT-TTF salts. As a magnetic field is rotated about the sample, the electrical resistance is found to oscillate, periodic in the tangent of the angle between the field, and normal to the most conducting layers, i.e. tan 0 oc n, where n is an integer. It has been shown that this new effect is a direct result of the nearly cylindrical Fermi surface, a nearly perfect two-dimensional electronic structure. A representative member of the BEDT-TTF family of organic conductors is depicted in Figure 14.4.

14.2.3 Other Organic Superconductors In addition to the two families of organic conductors discussed so far, chemists have recently succeeded in synthesizing combination, or hybrid, molecules based on TMTSF and BEDT-TTF. You may have noticed that the skeletal core of each of these molecules has the fulvalene structure, with a double carbon bond followed by either a pair of CruSe or CmS bonds. If you were to attach the left half of the TMTSF in Figure 14.1 to the right half of the BEDT-TTF in Figure 14.3, you would still retain the fulvalene structure, but in a new hybrid molecule, DMET.

Electrically Conducting Polymers and Organic Materials

31 1

/(lo2) \

Figure

14.4

C

(BEDT-TTF)2Xcrystal packing and the BEDT-TTF molecule.

This new family of materials was first discovered in 1987 by Kikuchi and coworkers [17]. Like both its parent molecules, D M E T charge transfer salts exhibit a variety of electrical properties. Many highly conducting 2:1 salts (DMET)2X have been made, including some superconductors, with transition temperatures in the range 1-2 K. A fourth family of organic superconductors is based on another hybrid molecule, MDT-TTF, with a maximum transition temperature of 4.5 K in (MDT-TTF)2AuI 2. Other hybrid molecular arrangements are made possible as new conducting compounds are synthesized. One of the potentially great advantages of the electrocrystallization growth process in organic conductors is the ability to try out new hybrids, which perhaps will lead to still newer conductors and superconductors. Two important differences separate our final class of organic conductors from those we've already discussed. The building block is an electron acceptor molecule instead of an electron donor and the center of the molecule is a transition metal such as Ni, Pd, or Pt. These materials were first synthesized in France by a group led by P. Cassoux [18-1, who intentionally designed an organic conductor with increased dimensionality with respect to (TMTSF)2X, in a search for new families of organic conductors and superconductors. The design worked, in that there are now a handful of superconductors [ 19] based on the new molecule, dmit, of the form X[M(dmit)2]2, where dmit is bis(4,5-dimercapto-1,3-dithiole-2-thione), M is nickel, platinum, and so on and X is a donor molecule such as TTF or (CH3)4N. Many of these materials have room temperature conductivity on the order of 10 3 S/cm, and are metallic to low temperature, reaching 10 5 to 10 6 S/cm at 10 K. However, due to an admixture of intercolumn and intracolumn interactions, the dimensionality of these materials is not well understood, and remains a bit

312

MATERIALS FOR ELECTRONIC PACKAGING

controversial. Nonetheless, the successful design and production of an organic superconductor is encouraging to researchers and bodes well for the future. There are many other related families of organic conductors, and while not necessarily superconducting, they continue to be of great interest to materials scientists. The fact that one can create through chemistry a highly conducting, or even superconducting, material using completely nonconducting constituent elements is a fascinating idea, one that will continue to encourage innovation in the design of new materials based on organic molecules.

14.3 Conducting Polymers As stated earlier, polymers are sometimes categorized apart from the organic crystals discussed above because of distinctly different atomic wavefunction overlap, or molecular orbitals. The overlap in most conducting polymers is an order of magnitude or two smaller than in the Bechgaard salts, and the basic conducting mechanism appears to be different. Below are brief reviews of some of the developments which have taken place in the last decade in the field of polymer conductors.

14,3,1 Polyacetylene Unlike polysulfurnitride, most polymers are inherently nonconducting, dielectric materials, the result of having completely (rather than partially) filled electronic shells. Pure polyacetylene, (CH)x, also known as polyvinylene, is one such insulator, with ambient temperature conductivity around 10 -8 S/cm, about one hundred trillion times lower than that of a good metal! The critically important discoveries that polyacetylene can be produced in film form [20], and that it can be made to conduct by stripping electrons from the chains which make up the polymer [21], thereby forming an ion, (CH)x-, opened the door to the reality of chemically doping (CH)x to form a conducting material. Solid polyacetylene is made by polymerization of gaseous acetylene in the presence of a Zeigler-Natta catalyst [22]. Recent methods [23] allow it to be grown as a film instead of a powder. The x in (CH)x refers to the number of repeat units of t h e - - C H - - C H - - building block. This number can reach 1 000, such that the molecular weight of this entity is nearly 10000. We mentioned above that the pure form is electrically insulating. Actually, it is an intrinsic semiconductor, which means there is a small amount of conduction in the pure form. At a sufficiently low temperature, the distinction between semiconductor and insulator is meaningless, since all the carriers of electronic charge will have frozen out, leaving no conduction. Upon doping, somewhat more traditional semiconducting behavior is found, albeit of an anomalous nature. Like silicon, polyacetylene can make a p-type or an n-type semiconductor, by introducing donors or acceptors which ultimately lie between the CH chains. In elemental or compound semiconductors, like silicon or gallium arsenide, these electron donors or electron acceptors can enter the lattice either substitutionally or interstitially. A phosphorous atom can

Electrically Conducting Polymers and Organic Materials

H

H

I

H

31 3

H

IC=C\

\ /c-c

H

H

I /c=q,

H

H

(a)

H

H

I

H

I

I

H

H

I

I

H

I

I

H

I

H

(b)

Figure 14.5

The two common forms of polyacetylene, trans-(CH)x and cis-(CH)x, from

[2(b)].

replace a silicon atom, donating an extra electron to the lattice (p-type) or it can fit in between two silicon sites. The are two structural forms of polyacetylene, trans-(CH)x and cis-(CH)x, are shown in Figure 14.5. The trans form is more stable; the cis form reverts to the trans form above 180~ This material grows in the form of a fibrous film, with chains of CH aligned parallel to each other. The fibers have a typical thickness of 10-20 nm, and are completely entwined. This leaves significant voids in the solid, such that only about half of the volume contains (CH)x. So far, it appears to be completely insoluble. In 1987, Naarmann and Theophilou were able to obtain copper-like conductivity (a ~ 105 S/cm) by doping polyacetylene with iodine [24]. This was an increase of several orders of magnitude over the previous best [25], and has been attributed to improved synthesis and processing, yielding a more tightly packed, denser material. This improvement could have far-reaching consequences. In this so-called new polyacetylene, dramatic effects are observed in the thermal and electrical properties upon stretching and aligning the polymeric chains. The thermal conductivity can approach that of a dirty metal or of metallic alloys, inviting applications geared toward electronic devices, including packaging. A variety of physical properties of the new polyacetylene are now being investigated with such applications in mind. One problem with electric conduction in (CH)x old or new, is the actual mechanism is unknown. It appears the conductivity is limited by barriers in the material, such as defects and impurities. Still unknown and somewhat controversial are the intrinsic conduction process and the maximum conductivity. One possibility is that solitons provide the conduction mechanism, a situation wherein conjugational defects are responsible for charge transport.

314

MATERIALS FOR ELECTRONIC PACKAGING

! 4 . 3 . 2 Polyaniline

Another heavily studied conducting polymer system is the oxidized form of aniline, polyaniline, (C6Hr with 0 < y < x (y = hydrogen content). The most attractive property of this polymer is its relative stability in air and water. In addition, it can be prepared chemically or electrochemically. Lithium rechargeable batteries employing polyaniline are already available. Bridgestone [26], a Japanese company, makes them as secondary or backup power sources for Seiko watches. Recent studies of this old material [27] have shown that, by adding protons to the base polyaniline structure, the conductivity can change by nearly 10 orders of magnitude, without actually altering the electronic content [28,29]. This type of insulator-to-metal transition has generated much interest from materials scientists. With this added degree of control, polyaniline stands as the only polymer whose conductivity can reversibly be controlled by two independent variables: oxidation and protonation. There are three interchangeable forms of polyaniline: the leucoemeraldine base (fully reduced, y = x), the emeraldine base (y = x/2), and pernigraniline (fully oxidized, y = 0). Ultimately polyaniline systems are expected to be an easier path toward conducting polymers for electronic applications, but there remain serious difficulties and uncertainties. Foremost among them are the actual conduction mechanism and the structure. Polaron, bipolaron, and glass-like conduction mechanisms have been proposed, but the question is yet to be answered. Another interesting property of polyaniline is its electrochromicity; thin films can be reversibly switched from clear to blue, to green, or to purple [30]. Although the switching speeds are slow (~0.1 s), there appears to be significant potential for this application, but before they can be realized, like all other polymers, improvements in processibility are required. 1 4 . 3 . 3 Molecular Conductors C60

The exciting 1991 discovery of high temperature superconductivity in doped C6o, buckminsterfullerene, has opened a new door to molecular engineering. Less than one year after its isolation chemists are able to perform what amounts to molecular surgery on this molecule, attaching other organic species to the spheres, doping the lattice with inorganic elements to form metals, even placing helium atoms inside the C6o sphere. In fact, there exists a series of fullerene-type structures, including Cvo and Cv6. Besides the parent sphere, colloquially known as the buckyball, another possible structure is the buckytube. Applications may be somewhat distant, but C6o is an extremely attractive system in which to design and build new molecular materials.

14.4 Potential Applications of Conducting Polymers The potential for technical utility of polymer conductors is widely recognized but hardly realized in practice. Probably the most important feature to be exploited is the systematic variability of the conductivity, whether by doping pure polymers,

Electrically Conducting Polymers and Organic Materials

31 5

or by forming composite materials such as graphite-polyethlyene. Already, polymers span the entire region of electrical conductivity, from Teflon (PFTE) and Kapton (polyimide), with conductivities close to those of quartz or diamond, to polyacetylene, polypyrrole, and graphite, similar to silicon of dirty metals. The ultimate goal is to unite the technological advances in electrical and optical properties achieved in semiconductors with the mechanical and processing advantages perceived in polymers [31,32]. Recent advances [1,2] include: Fabrication of polythiophene transistors, metal insulator semiconductor field effect transistors (MISFETs), a p-n heterojunction device with interesting electro-optical properties Increases in solubility of various polymer blends and gels important for thin film processing Improvements in environmental stability of a wide variety of polymer conductors Fabrication of solid-state polymer batteries Applications toward industrial waste degradation employing polymers Fabrication of gas separation membranes with polyaniline Production of polymer glasses with new electro-optical properties Improved routes toward new photovoltaic energy conversion devices (solar cells) and electric power distribution conductors Conducting polymer electromagnetic interference (EMI) shielding devices Developments toward large area, color display panels using electroluminescent polymer dye films. Most of these advances have taken place in the past five years and have yet to reach the market. But it is quite likely, if not inevitable, that conducting polymers will permeate our culture just like other plastics. As materials scientists improve their manipulation of conducting properties, new science and technology will emerge. The distinction between what conducts and what doesn't is long gone. References

1. International Conferences on Science and Technology of Synthetic Metals 1979 Dubrovnik, Springer Lecture Notes in Physics 95, 96, Springer (1979). 1981 Boulder, Mol. Crvst. Liq. Cryst. 77,79,81,83,85,86 (1982). 1982 Les Arcs, J. de Physique (Paris) 44, Colloque C3 (1983). 1984 Albano Terme, Mol. Crvst. Liq. Crvst. 117-119 (1985). 1986 Kyoto, Synth. Metals 13 (1986). 1988 Sante Fe, Svnth. Metals 27-29, (1988, 1989). 1990 Tubingen, Synth. Metals 41-43, (1991)i 1992 Gothenburg, Synth. Metals (1993). 2. (a) Handbook of Conducting Polymers, Vols. 1 and 2, edited by T.A. Skotheim, Marcel-Dekker, New York, 1986. (b) T. Ishiguro and K. Yamaji, Organic Superconductors, Springer Series in Solid-State Sciences 88, Springer, Berlin, 1990. (c) Low Dimensional Conductors and Superconductors, edited by D. Jerome and L.G. Caron, Plenum, New York, 1987.

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3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19.

20.

(d) J.R. Ferraro and J.M. Williams, Introduction to Synthetic Electrical Conductors, Academic, New York, 1987. (e) The Physics and Chemistry of Organic Superconductors, edited by G. Saito and S. Kagoshima, Springer, Berlin, 1990. (f) Electronic Properties of Conjugated Polymers, edited by H. Kuzmany, H. Mehring, and S. Roth, Springer Ser. in Solid-State Sciences 91, Springer, Berlin, 1991. (g) Electronic Properties of Polymers and Related Compounds, edited by H. Kuzmany, H. Mehring, and S. Roth, Springer Series in Solid-State Sciences 63, Springer, Berlin, 1985. (h) Electronic Properties of Polymers, edited by J. Mort and G. Pfister, Wiley, New York, i982. (i) Advances in Polymer Technology, Vol. 11, edited by M. Xanthos, Wiley, New York, 1991. (j) Polymers for Advanced Technology, Vol. 3, edited by M. Lewin, Wiley, New York, 1992. (k) Lower-Dimensional Systems and Molecular Electronics, NA TO ASI Series B." Physics 248, edited by R. Metzger, P. Day, and G. Papavassiliou, Plenum, New York, 1990. V.V. Walatka, M.M. Labes, and J.H. Perlstein, Phys. Rev. Lett. 31, 1139 (1973). R.L. Greene, G.B. Street, and L.J. Suter, Phys. Rev. Lett. 34, 577 (1975). A.T. Vartantan, Zh. Fiz. Khim. 23, 769 (1948) [J. Phys. Chem. (USSR) 22, 769 (1948)]. D.D. Eley, Nature 162, 819 (1948). H. Akamatu and H. Inokuchi, J. Chem. Phys. 18, 810 (1950); H. Akamatu, H. Inokuchi and Y. Matsunaga, Nature 173, 168 (1954). A.T. Vartanyan, J. Phys. Chem. (USSR) 24, 1361 (1950). O. Kahn, D. Gatteshi, J.S. Miller, and F. Palacio (eds.), Proc. Con[i Molecular Magnetic Materials, (NA TO ARWE198), Kluwer Academic, Amsterdam, 1991. W. Little, Phys. Rev. A 134, 1416 (1964). K. Bechgaard, C.S. Jacobsen, K. Mortensen, H.J. Petersen, and N. Thorup, Solid State Commun. 33, 1119 (1980). D. Jerome, A. Mazaud, M. Ribault, and K. Bechgaard, J. de Phys. (Paris) Lett. 41, L95 (1980); see also, K. Bechgaard and D. Jerome, Scientific American, July 1982. M.J. Naughton et al., Phys. Rev. Lett. 61, 621 (1988). A.G. Lebed, JETP Lett. 43, 174 (1986); T. Osada, et al., Phys. Rev. Lett. 66, 1525 (1991); M.J. Naughton, et al., Phys. Rev. Lett. 67, 3712 (1991). S.S.P. Parkin, E.M. Engler, R.R. Schumaker, R. Lagier, V.Y. Lee, J.C. Scott, and R.L. Greene, Phys. Rev. Lett. 50, 270 (1983). H. Urayama (Mori), H. Yamachi, G. Saito, K. Nozawa, T. Sugano, M. Kinoshita, S. Sato, K. Oshima, A. Kawamoto, and J. Tanaka, Chem. Lett. 55 (1988). K. Kikuchi, K. Murata, Y. Honda, T. Namiki, K. Saito, T. Ishiguro, K. Kobayashi, and I. Ikemoto, Jpn. J. Appl. Phys. 55, 3435 (1987). M. Bosseau, L. Valade, M.F. Bruniquel, P. Cassoux, M. Garbauskas, L. Interrante, and J. Kasper, Nouv. J. Chim. 8, 3 (1984); M. Bosseau, L. Valade, J.P. Legros, P. Cassoux, M. Garbauskas, and L. Interrante, J. Am. Chem. Soc. 108, 1908 (1986). L. Brossard, M. Ribault, M. Bosseau, L. Valade, and P. Cassoux, C.R. Acad. Sci. Ser. B 302, 205 (1986); J. Schirber, D.L. Overmeyer, J.M. Williams, H.H. Wang, L. Valade, and P. Cassoux, Phys. Lett. A 120, 87 (1987); K. Kajita, Y. Nishio, S. Moriyama, R. Kato, H. Kobayashi, W. Sasaki, A. Kobayashi, H. Kim, and Y. Sasaki, Solid State Commun. 65, 361 (1988). T. Ito, H. Shirakawa, and S. Ikeda, J. Polvm. Sci. Polvm. Chem. 12, ll (1974).

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317

21. C.K. Chiang, C.R. Fincher, Y.W. Park, A.J. Heeger, H. Shirakawa, E.J. Louis, S.C. Gau, and A.G. MacDiarmid, Phys. Rev. Lett. 39, 1098 (1977). 22. G. Natta, G. Mazzanti, and P. Corradini, Accad. Nazi. Lincei. Sci. Fis. Mat. Nat. 25, 3 (1958). 23. H. Shirakawa, M. Sato, A. Hamano, S. Kawakami, K. Soga, and S. Ikeda, Macromolecules 13, 457 (1980). 24. H. Naarmann and N. Theophilou, Synth. Metals 22, 1 (1987); N. Basescu, Z.-X. Liu, A. Heeger, H. Naarmann, and N. Theophilou, Nature 327, 4032 (1987). 25. K. Soga, S. Kawakami, and H. Shirakawa, Macromol. Chem. Phys. 71,4614 (1979). 26. A.G. MacDiarmid, J. Chiang, A. Richter, and A.J. Epstein, Synth. Metals 18, 285 (1987). 27. A.G. Green and A.E. Woodhead, J. Chem. Soc. 97, 2388 (1910). 28. A.G. MacDiarmid, J.C. Chiang, M. Halpern, W.S. Huang, S.L. Mu, N. Somasari, W. Wu, and S.I. Yaniger, Mol. Crvst. Liq. Crvst. 121, 173 (1985). 29. E.W. Paul, A.J. Ricco, and M.S. Wrighton, J. Phys. Chem. 89, 1441 (1985). 30. P.M. McManus, S.C. Yang, and R.J. Cushman, J. Chem. Soc. Chem. Commun. 1156 (1985). 31. A.J. Heeger, P. Smith, A. Fizazi, J. Moulton, K. Pakbaz, and S. Rughooputh, Synth. Metals 41, 1027 (1991). 32. J.E. Ellis, in [2a] Vol. 1, p. 489; see also, J.R. Ellis and R.S. Schotland, Market Opportunities jbr Electrically Conductive Poh'meric Systems, Princeton Polymer Laboratories, and Schotland Business Research, Princeton NJ, 1981.

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15 Diamond in Electronic Packages D. J. Pickrell, D. S. Hoover

1 5.1

Introduction

As the densities of integrated circuits and the power levels of discrete devices increase, rapid heat dissipation will be essential to maintain or increase operating performance and device lifetimes. To accomplish this, packages of improved thermal design will be required along with the use of high performance materials. Traditionally BeO substrates have been used in electronic substrate applications where an electrical insulator with high thermal conductivity is required. More recently, A1N is being evaluated as a substitute material for such applications because of the toxicity problems associated with BeO. Diamond has the highest thermal conductivity of any material (at room temperature), more than six times greater than A1N or BeO and five times greater than pure copper. It is also an excellent electrical insulator with high electrical resistivity, high dielectric strength, low dielectric constant, and low dielectric loss. It is therefore an extremely attractive material for use in electronic packages where rapid removal of heat from circuit components is required. Single crystals of natural diamond and synthetic diamond, made by a high pressure process, have for many years been sold as substrates for high power discrete devices. However, their use in electronic packaging has been severely limited because of their high cost and small size. Polycrystalline diamond can now be synthesized by a chemical vapor deposition process as a coating or in thick, freestanding form over large areas. It has a comparable performance to single crystal diamond but at a fraction of the cost. The availability of this polycrystalline form is greatly expanding the use of diamond in electronic packaging. This chapter will discuss the synthesis of diamond by chemical vapor deposition and its incorporation into electronic packages. 15.2

B a c k g r o u n d on D i a m o n d

The carbon atom has an electron configuration of lsZ2s22p2, essentially a helium noble gas core with four outer electrons for bonding. These outer electronic orbitals (2s and 2p) hybridize to various extents, allowing pure carbon to assume 319

320

MATERIALS FOR ELECTRONIC PACKAGING

a number of crystalline and amorphous structures. The two most common crystalline forms of carbon are graphite and diamond. In graphite, each carbon atom has a n s p 2 electronic configuration and forms strong covalent a-bonds with three other carbon atoms in a plane. The remaining electrons, one for each carbon atom, form weaker g-bonds with each other above and below the planes. The planes are stacked in an ABAB... fashion and held together by van der Waals forces. The properties of graphite are highly anisotropic due to the difference in chemical bonding within and between the carbon planes. For example, graphite has a high electrical conductivity parallel to these planes but not perpendicular to them. This is because the g-bonded electrons are delocalized and can move easily within the planes. Delocalized electrons also absorb electromagnetic radiation throughout the visible range causing graphite to appear black. Since the carbon planes are held together only by weak van der Waals forces, they can easily slip past one another; this makes graphite a soft material with high lubricity. In diamond, each carbon atom is s p 3 hybridized and forms strong a-bonds to four other carbon atoms arranged in the form of a tetrahedron. Consequently, a strong three-dimensional covalent network is produced. Since all four outer electrons of each carbon atom participate in covalent bonds, in its pure form carbon is an electrical insulator and is transparent throughout the visible and infrared spectrum, except for two-phonon absorption [1]. The strong bonding, dense packing of atoms, and high cohesive energy, make diamond the hardest, stiffest, and least compressible material ever known and are responsible for its very low thermal expansion coefficient. The strong, short, stiff bonds also give rise to diamond's most important property for electronic packaging applications, its extremely high thermal conductivity, which at room temperature is five times greater than pure copper. Because of its unique properties and rarity in nature, people have tried to synthesize diamond for over a hundred years [2]. Three distinct syntheses have emerged. First to gain commercial importance was the high pressure/high temperature (HPHT) growth process. At atmospheric pressure, graphite is the thermodynamically stable form of pure carbon and diamond is metastable. High pressures, on the order of 104 atm, are required to make diamond the stable form of carbon. To convert graphite to diamond at these high pressures, high temperatures are needed to overcome the activation energy barrier. High pressures and high temperatures can be generated statically, with a heated hydraulic press, or dynamically, by propagating a shock wave in graphitic material [3]. In the static HPHT process, the solvent/catalyst approach is used to lower the temperature and pressure from that required for direct conversion of graphite to diamond. In this technique, a metal such as nickel or iron is mixed with the graphite before it is placed in the die cavity. The mixture forms a eutectic melt around 1 300-1 500~ and under the high pressure (30000-40000 atmospheres) diamond precipitates out. Dissolution into the molten metal reduces the activation energy barrier, which lowers the necessary processing temperatures and significantly improves the kinetics for conversion of graphite to diamond. Diamond produced by HPHT processes is primarily used for industrial cutting and grinding applications. It has

Diamond in Electronic Packages

321

also been marketed for electronic substrates, but the crystals are expensive and have areas limited to a few square millimeters. Syntheses based on physical vapor deposition of carbon species at low pressures [4] can produce diamond thin films. These processes involve some form of ion bombardment to achieve conditions necessary for the formation of s p 3 bonded carbon. The films formed are typically amorphous networks with variable ratios of sp 2 t o s p 3 bonded carbon and various amounts of hydrogen. They are generally termed diamond-like carbon films because they have properties which can approach that of true crystalline diamond. Although these films are usually amorphous, some fine diamond crystals have been reported [5,6]. Diamond-like carbon films are deposited at room temperature; they are hard, transparent, and chemically impervious; they have a range of potential applications but will not be discussed in detail in this chapter. The third class of syntheses is based on chemical varpor deposition (CVD). Diamond is crystallized via a chemical reaction with the gas phase under low pressure conditions, where it is the thermodynamically metastable form of carbon. Though last to gain commercial importance, synthesis of diamond in the laboratory by CVD actually predates HPHT [7]. CVD diamond has great potential for use in electronic packaging because it can be grown relatively inexpensively in thin films or thick slabs over large areas; it is therefore the focus of discussion in this chapter.

1 5.3 Chemical Vapor Deposition of Diamond 15.3.1 Deposition Techniques There are numerous types of CVD systems for synthesizing diamond, differing mainly in the manner in which the gas phase is activated. Figure 15.1 shows two of the most common, the hot filament technique and the microwave plasma assisted technique. In the hot filament process, a refractory metal wire heated in excess of 2 000~ is used to activate diamond growth [8]. A gas mixture composed of 2% or less of CH4 in H2 flows into a chamber held at around 30-50 torr pressure. On a substrate positioned about 1 cm from the filament, and heated in the range 700-900~ diamond grows at a rate of a few micrometers per hour. Many minor variations of the basic hot filament growth system have been described. Included in these are systems using different filament materials, such as W, Ta, and Re [9,10]; using the metal in different forms, such as a tube [11] or spiral ribbon [12]; RF induction [13] instead of resistance heating of the metal; and biasing of the substrate relative to the filament to enhance growth rates [14]. In the low pressure, microwave plasma CVD system [15] (Fig. 15.1) microwaves at 2.45 GHz are directed into a tubular, fused silica reaction chamber to create a plasma in the gases flowing through the tube. Again a mixture of 2% or less of CH4 in H2 flows into the chamber and the pressure is held at around 50--100 torr. The substrate is placed on a susceptor, positioned in the plasma, and heated to around 800-1000~ by the microwaves and plasma. Diamond grows on the substrate at a rate of a few micrometers per hour. Minor variations on this

322

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process include using a glass bell jar instead of a tube [16], using an independent substrate heater and depositing on a substrate slightly downstream of the plasma [-173, and using a magnetic field to flatten the plasma or achieve the electron cyclotron resonance (ECR) effect [18]. DC [19] and RF [20] excited, low pressure plasmas have also been used to synthesize diamond, but its crystalline quality appears to be inferior to diamond obtained with microwave plasma [21] and hot filament techniques. Diamond has also been grown from thermal plasmas operating at atmospheric pressure. As with the low pressure plasmas, DC [22], RF [23], and microwave [24] excited thermal plasmas have all been used to deposit diamond. Because of

Diamond in Electronic Packages 3 2 3

Table

15.1

Properties of CVD diamond.

Thermal conductivity at room temperature (W m-1 K-1) Electrical resistivity (f~ cm) Dielectric constant Dielectric loss Breakdown field (V/llm) Thermal expansion at room temperature (K-1)

1200- 2 100 > 1011 5.7 < 0.0005 > 300 0.8 X 10 - 6

their higher pressure, these thermal plasmas require the sustainment of much higher input power, and such large amounts of heat are generated that the substrate must be placed downstream of the plasma on a water-cooled copper holder to achieve the optimum diamond growth temperature of 900-1 000~ These thermal plasmas appear to offer higher diamond growth rates, > 10/tm/h because they are effective in generating larger concentrations of atomic hydrogen and diamond growth species. Diamond can also be grown from an oxyacetylene flame [25,26]; in this case the diamond growth species are generated from the acetylene. The flame is held in a slightly fuel-rich regime during deposition. As with the thermal plasma techniques, so much heat is generated in the flame that the substrate must be placed on a water-cooled holder, and high diamond growth rates have been reported. 1 5 . 3 . 2 Nucleation and Growth of Diamond

Although a wide variety of methods have been demonstrated to be effective in growing diamond, the actual diamond nucleation and growth process is probably similar in each. In all of the techniques, a mixture containing a carbonaceous gas and hydrogen is activated by some means to form carbon precursors to diamond growth and to dissociate molecular hydrogen into atomic hydrogen (Fig. 15.2). Atomic hydrogen is an essential component for the continuous growth of diamond at low pressures; it is believed to act in two ways to kinetically favor the growth of diamond over graphite. First, it stabilizes the sp 3 bonding of carbon atoms on the diamond surface by satisfying the dangling bonds until other carbons can add to the growth surface. Without this hydrogen the diamond surface would convert into an sp z bonded structure, and addition of carbon would result in the propagation of graphite. Secondly, atomic hydrogen destabilizes or e t c h e s graphitic material, which conucleates along with diamond on the substrate surface. It therefore allows only the diamond nuclei to mature while graphite nuclei are constantly redissolved. The carbon species involved in the growth of diamond and the exact mechanism by which they add to the surface is not yet known. Two different mechanisms have been proposed, one based on CH3 radicals [27] and one based o n C z H 2 [28] as the growth species. Experimental studies have also indicated that charged species may be involved [14,29]. Chemical analysis of the gas phase

324

MATERIALS FOR ELECTRONIC PACKAGING

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Figure 15.2 Simplified picture of the chemical vapor deposition process for diamond film growth and the role of atomic hydrogen in this process.

environment during diamond growth by spectroscopic techniques is being used to elucidate what species are present, in what concentrations, and how these concentrations are affected by changes in process parameters [30-33]. Also important in the growth process are those changes occurring on the diamond surface in the optimum temperature range for diamond growth, such as adsorption/ desorption of hydrogen from surface carbons and reconstruction of the diamond

Diamond in Electronic Packages 325

surface [34]. Excellent reviews of the overall chemistry involved in diamond growth by CVD are available [7, 34-36-1. Most CVD diamond growth is accomplished with carbon and hydrogen gas mixtures, but solid carbon can also be used as the carbon source. In the chemical transport reaction, graphite is etched by atomic hydrogen in a plasma to form gaseous species which are then transported to a cooler substrate where they condense as diamond. More recently it has been shown that minor amounts of oxygen added to the precursor gas may improve the crystalline quality of the films and enhance growth rates [37,38]. It has been proposed that oxygen aids the removal of codeposited graphite, in a similar manner to hydrogen, and breaks down larger hydrocarbon species [39]. A new CVD technique based on halogen chemistry [40] appears to be very different from the rest of the diamond growth methods. The reaction is carried out by flowing the gases through a furnace in which a temperature gradient is imposed. The process is unique in that it uses no other activation of the precursor gases, and diamond grows only in a temperature range of 250-750~ This new CVD diamond chemistry is in its early stages of development and its advantages and disadvantages relative to other techniques are still not clear. But it does appear to hold the promise of a reasonable growth rate at reduced substrate temperatures (< 300~ Diamond growth refers to the addition of carbon atoms to an already existing diamond surface; on a foreign surface, diamond must first be nucleated. Although homogeneous nucleation in the gas phase has been demonstrated [41-1, chemical vapor deposition of diamond is thought to involve heterogeneous nucleation on the substrate surface. Diamond nucleation is a complicated process that is not well understood. It has been empirically determined that the nucleation density of diamond is greatly enhanced through pretreatment of the substrate, which usually involves abrasion of the surface in some manner with diamond powder. It is not clear whether surface damage or some form of disordered carbon residue acts as a nucleation site for diamond. It is also possible that diamond growth occurs on diamond seed crystals; remaining embedded in the surface after abrasion, so that a nucleation step is not required. Evidence seems to indicate that several mechanisms are involved. It has been shown that seeding with diamond powder without abrasion, and abrasion with nondiamond powder also enhance the nucleation density of diamond [42]. Diamond can be grown on a range of substrate materials, including metals, oxides, nitrides, and carbides. The chemistry of the substrate also dramatically affects the diamond nucleation process. Carbon will diffuse into the surface of many metals and this can result in the formation of an intermediate carbide layer. The absorption of carbon into the substrate delays the nucleation of diamond [43]. The thickness of the carbide layer formed depends on the substrate material and the processing conditions such as substrate temperature. On silicon the carbide layer thickness is only about 10 nm [44-46], whereas on molybdenum it can be 10 t~m or more. Diamond films on copper exhibit poor adhesion because carbon has a low solubility in copper [47], which results in little chemical interaction at the interface. Metals such as cobalt, iron and nickel tend to form carbon soot

326

MATERIALS FOR ELECTRONIC PACKAGING

initially on their surfaces under standard diamond growth conditions, which also gives rise to poor diamond film adhesion. At high growth temperatures (> 900~ some oxides can be severely etched by atomic hydrogen and carbon, and this may delay or even prevent diamond nucleation [48]. I 5 . 3 . 3 Film Structure

Once nucleated on the substrate surface, the diamond crystals grow in size and impinge to form a continuous film. The size of the crystals in the film when it becomes continuous depends on the initial nucleation density of diamond. Therefore by changing the manner in which the substrate surface is prepared, the grain size in films can be varied. The grain size in films is also a function of substrate temperature, carbon concentration in the gas phase, and film thickness. The crystal morphology of diamond films is easily visible in optical and scanning electron microscopes (Fig. 15.3). The crystallites in CVD diamond films usually have a preferred orientation with the [1 1 0], [1 00], or [1 1 1] crystal directions perpendicular to the substrate surface. Their columnar structure can be observed in film cross sections and the crystallographic orientation has been studied with X-ray texture analysis [49]. This texturing is not a strong function of the substrate structure, chemistry, or surface preparation, and can even be produced on amorphous substrates. It is a function of processing parameters, such as substrate temperature and carbon concentration in the gas phase, which change the relative growth rates of certain crystal faces. Models to explain how these textures develop based on the relative growth rates of the diamond crystal faces have been proposed [49,50]. CVD diamond films exhibit X-ray and electron diffraction patterns as well as Raman characteristics of diamond. Raman spectroscopy, now routinely used for analysis of CVD diamond films, has the additional advantage that minor amounts of s p 2 bonded carbon can be detected (Fig. 15.4). The nature of this s p 2 carbon is not well understood. It is not a separate graphite phase but is a graphitic type of carbon bonding. Recent evidence indicates that this s p 2 carbon resides at the grain boundaries in thin hydrogen free regions [-51]. From transmission electron microscopy it has been determined that CVD diamond crystals usually contain imperfections, such as stacking faults and twins, and that these defects lie on the (111) planes [52,53]. Chemical impurities can be introduced into films during deposition, but generally may be kept very low by proper reactor design and film processing conditions. Hydrogen can be incorporated in the films because of its abundance in the growth environment but its concentration is usually less than about 0.5 at. %. 1 5 . 3 . 4 Film Properties

15.3.4.1 Thermal Conductivity The most important property of CVD diamond for electronic packaging applications is its thermal conductivity. The thermal conductivity of a material depends on its structure and chemical purity, and is a function of temperature.

Diamond in Electronic Packages 3 2 7

Figure 15.3 Scanning electron micrographs of the top surface (above) and fracture cross section (below) of a 300 ltm thick diamond film grown by hot filament CVD.

For electronic packaging applications the temperature range of most interest is around room temperature up to 100~ Within this range diamond has the highest thermal conductivity of any material. A compilation of the room temperature thermal conductivities for various materials used in electronic packaging is shown in Figure 15.5. The values listed are for polycrystalline forms of these materials, with the thermal conductivity of single crystal diamond included for comparison.

328

MATERIALS FOR ELECTRONIC PACKAGING

DIAMONDSTRUCTURE

c~

1200.0 Figure 15.4

Igl

1320.0 1440.0 1560.0 1680.0 cm-1

Raman spectra for a series of diamond films with increasing s p 2 carbon impurity concentrations. The s p 2 carbon (amorphous structure) signal increases from the bottom spectrum to the top spectrum. As can be seen, in its chemically pure single crystal form, diamond has a thermal conductivity five times that of copper at room temperature. In electrical insulators, such as AIN, BeO, and diamond, heat is conducted by phonons. Any imperfections in the ordered crystalline structure of a material will scatter phonons and tend to reduce its thermal conductivity. Such imperfections can include point defects such as impurity atoms and vacancies; line defects such as dislocations; plane defects such as twins and grain boundaries; as well as microstructural defects such as porosity and secondary phases. The effect of some of these defect types on the thermal conductivity of diamond are understood, while others need to be studied further. Point defects have been shown to markedly affect the thermal conductivity of diamond. The room temperature thermal conductivity of single crystal, natural

Diamond in Electronic Packages

329

2000

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diamond decreases from 2 000 W m - 1 K - x to around 600 W m - ~ K - ~ with increasing concentrations of substitutional nitrogen impurities [54]. Similarly, the thermal conductivity of aluminum nitride is severely eroded by oxygen impurities which substitute for nitrogen in the lattice [55]. For charge compensation these substitutional oxygens produce aluminum vacancies, vacancies which have the greatest impact on lowering the thermal conductivity of the AIN. Nitrogen impurities are not a problem in CVD diamond films since they are usually grown in vacuum chambers from high purity gases. Isotopic impurities are also point imperfections which can affect the thermal conductivity of a material. Recently it has been demonstrated that the thermal conductivity of chemically pure diamond can be further improved by synthesizing crystals with lower isotopic carbon concentrations. By reducing the ~3C concentration from the natural abundance of 1.0% down to 0.1%, a thermal conductivity of 3000 W m - ~ K -~ at room temperature has been achieved [56]. CVD polycrystalline films can also be made more isotopically pure but no increase in thermal conductivity has been observed, presumably due to the dominance of grain boundary effects in the material [57]. Crystal defects such as dislocations, stacking faults, and twins are known to

330

MATERIALS FOR ELECTRONIC PACKAGING

be present in CVD diamond crystals, but their effect on thermal conductivity has not yet been quantified. The possibility of growing diamond films with varying concentrations and distributions of these defects [58,59], should eventually lead to a means of studying their effects on thermal conductivity. The thermal conductivity of CVD diamond films has been shown to be greatly affected by the size, shape, and orientation of the diamond crystallites. Graebner et al., have shown the thermal conductivity of diamond films increases with increasing film thickness, and have correlated this to an increase in average grain size in the films [60]. Extrapolation of the derived thermal conductivity versus grain size for CVD diamond indicates that films with large crystallites (> 30 ~m) may have thermal conductivities which meet or exceed the conductivity of chemically pure natural single crystals. Anisotropy in the thermal conductivity of CVD diamond films has been found to exist due to their texture. In textured films, the thermal conductivity is up to 50% greater measured perpendicular to the CVD diamond film than parallel to it. This is because the columnar crystals cause the linear density of grain boundaries to be greater parallel to the film [61 ]. Secondary phases will also influence the thermal conductivity of a material. The effect of a low thermal conductivity secondary phase depends on its relative concentration as well as its distribution throughout the matrix, and can be estimated from various mixing rules. Secondary phases may be a necessary result of processing some ceramic materials. Most high thermal conductivity nonmetallic crystals, such as AIN, SiC, cubic BN and diamond, are covalently bonded and unfortunately do not sinter easily. Therefore, special fabrication techniques have been developed to produce polycrystalline forms of AIN [55,62], SiC [63], and cubic BN [64], with reasonably high thermal conductivities. A good example is the development of sintering aids for A1N. These oxides are used not only to promote sintering of A1N particles by chemically reacting with the A1203 layer on their surface but also to draw dissolved oxygen out of the A1N lattice to increase the thermal conductivity of the grains themselves [55]. If the sintering additive is kept at a low concentration, the reduction in thermal conductivity due to the oxide second phase formation is more than compensated by the increase in thermal conductivity due to removal of oxygen from the crystals and reduction of porosity in the ceramic. Chemical vapor deposition of a material such as diamond or silicon carbide offers the advantage that bonds between crystals form during film deposition. There are no subsequent compaction and sintering steps. The grain boundaries can, therefore, be kept free of secondary phases by proper processing of the films. The fracture cross section of a CVD diamond film in Figure 15.3 shows that it is very dense with a columnar grain structure and no apparent porosity. The transgranular fracturing indicates the crystallites are strongly bonded at the boundaries. Under nonoptimum growth conditions s p 2 bonded carbon can be incorporated into the films to reside primarily at the boundaries between crystallites. The s p 2 carbon content in CVD diamond films has been shown to increase with increasing methane concentration in the precursor gas, and this has been correlated to a decrease in thermal conductivities of the films [65]. CVD diamond films have now been produced with thermal conductivities

Diamond in Electronic Packages

331

of around 2 100 W m - 1 K - 1 [66], comparable to a chemically pure, single crystal diamond and much higher than chemically impure crystals. An excellent review of thermal conductivity and diamond films is [67].

15.3.4.2 Electrical Properties Electrical isolation is important in most substrate applications for CVD diamond but not all. In some cases, the diamond is fully metallized on all faces to allow current to flow from the top to the bottom of the substrate. When electrical isolation is required the diamond must exhibit a high intrinsic electrical resistivity. Chemically pure diamond has a resistivity of around 1016 ohm cm. When doped with boron, however, it exhibits p-type semiconductor behavior and the resistivity falls to around 103 ohm cm. For the production of high resistivity CVD diamond films, therefore, the presence of boron in the reaction chamber is undesirable. It has also been shown that hydrogen incorporation in CVD diamond films can dramatically lower their resistivity (105-106 ohm cm) and that annealing films to remove this hydrogen will increase their resistivity (> 1011 ohm cm) [68-]. The process has been shown to be reversible. Other electrical properties for currently available CVD diamond substrates are summarized in Table 15.1 (p. 323).

1 5 . 4 Fabrication of Electronic Substrates CVD diamond films can now be grown from less than 1 pm thick to more than 1 mm thick, and over areas greater than 100 in. 2 (12 in. diameter wafer) at a time [69]. Depending on the particular application, diamond can be used as a coating on another substrate material or in thick, freestanding sheets. To produce freestanding sheets the diamond is physically or chemically removed from the substrate after growth. Waters of polycrystalline diamond over 300 pm thick and up to 4 in. in diameter have been produced by this method. The surface roughness of the top growth side of the diamond films increases with increasing film thickness, due to an increase in the average crystal size at the surface. The surface finish of thinner films ( < 100 pm) may be acceptable for most circuit applications and can be optimized by controlling the morphology and crystallite size of diamond during film growth. For thicker films, polishing is required to obtain finishes necessary for subsequent metallization and device attachment. Diamond can be polished using diamond powder or more sophisticated chemical techniques. Average surface roughnesses of less than 10nm can be achieved. Once the proper surface finish is obtained, the diamond substrate can be metallized. Metallization of CVD diamond is currently accomplished with thin film deposition techniques. Usually a thin layer (approximately 100 nm) of a carbide-forming metal, such as titanium, is deposited on the diamond surface to promote adhesion of subsequent metallization layers, typically platinum and gold. Freestanding diamond substrates can be metallized on their top and bottom surfaces with electrical isolation maintained between them; for some applications all six sides are metallized. Circuit patterns can be defined through photolithog-

332

MATERIALS FOR ELECTRONIC PACKAGING

raphy. Thicker metallization (> 5 #m) for high current applications is produced by electroplating. Solders, such as the Au-Sn eutectic, can be directly deposited onto the diamond for attachment of discrete devices. Large area substrates ( > l c m 2) are usually handled individually during metallization. Substrates for smaller applications, discrete devices like laser diodes, can be metallized a hundred at a time in a single diamond slab; each substrate covers a few square millimeters. This is a further cost advantage over single crystal diamonds which must be processed individually. Because diamond is chemically inert, metallization can be stripped off in acid mixtures and the substrates recycled to reduce scrap costs. This is usually only economically attractive for larger area substrates. Due to its extreme hardness, diamond cannot be diced with conventional mechanical wafer saws. For thinner coatings on silicon, the diamond can be selectively deposited such that alleys on the silicon remain uncoated for mechanical dicing [70]. Thick, freestanding diamond is cut to shape with a Nd:YAG laser. Laser cutting allows even complex shapes to be produced to close tolerances (_+0.0001 in.). Parameters such as pulse frequency, traverse speed across the diamond, and power determine the cutting rate and quality of the cut surface. Figure 15.6 shows the laser cut surfaces of a small diamond substrate; they are smooth and perpendicular to the top surface. This is important in applications such as substrates for laser diodes which after mounting to the diamond must have an optical fiber precisely aligned and attached to the end of the lasing stripe. Via holes can be laser cut through the diamond substrate and metallized to electrically connect pads on the top surface to the backside metallization. Displayed in Figure 15.7 are a variety of diamond heat spreaders sold for electronic packaging applications.

Figure 15.6

metallization.

Edge view of a CVD diamond heat spreader, laser cut after polishing and

Diamond in Electronic Packages

333

Figure 15.7 CVD diamond heat spreaders used in electronic packaging: a 1 in. x 1 in. polished square of diamond; a 1 in. x 1 in. square of diamond polished and metallized with gold; a smaller square of diamond with patterned metallization; diamond substrates of various final sizes; a 100 ;Lm thick diamond coating on molybdenum metallized with gold; 100 pm thick diamond on molybdenum with patterned gold metallization and attached discrete devices; and a 4 in. diameter molybdenum prescribed wafer coated with 20 pm of diamond.

15.5 Package Design Considerations Many properties must be considered in the selection of materials for electronic substrate and packaging applications. A high thermal conductivity is important for rapid removal of heat from circuit components. High electrical resistivity and breakdown voltage are usually required for maintaining electrical isolation between components. A low dielectric constant is desirable for high frequency applications, to minimize capacitive coupling effects, and for IC packaging, to maximize the transmission speed of signals between chips. A low dielectric loss is important for high frequency applications to minimize energy loss in the package. The thermal expansion of packaging materials should be closely matched to the chip material to minimize thermal stresses generated from the heat rise during device operation. Other considerations are the chemical and process compatibility of the materials in the package and their cost. No single material combines all the desirable properties and no single material will be optimum for all substrate and packaging applications. For example, very

334

MATERIALS FOR ELECTRONIC PACKAGING

ELECTRC ICFIMPrINENT-~ /SPREADINGANGLE I.I,/I.I .,

i

FP IPERN IH KEAT

Figure 1 5.8 An ideal thermal design in which a diamond heat spreading layer is placed between the heat source and heat sink. The electronic devices generating the heat are placed directly against the diamond surface.

low dielectric constant materials, such as polymers and fused silica, are extremely poor thermal conductors. The importance of each requirement will depend on the particular circuit application, but advanced packages are likely to be composites of several materials serving different functions. Diamond can rapidly conduct heat away from circuit components because of its high thermal conductivity, but diamond does not store heat well because of its low heat capacity. An optimum thermal design would therefore incorporate a diamond heat spreading layer between the circuit component generating the heat and a heat sink (Fig. 15.8). The heat sink could be copper or another metal, it could be air blown across cooling fins, or it could be a liquid circulated through cooling channels. Microchannels could be laser cut directly into the diamond slabs for liquid cooling. Ideally, the heat-generating device is mounted directly against the diamond surface, in aflip-chip fashion, so the heat has no need to travel through the chip material of lower thermal conductivity, be it silicon or gallium arsenide. In this ideal package structure, heat will be rapidly spread laterally away from the heat source into the diamond layer, and conducted downward into the heat sink. The spreading angle is a measure of the amount of lateral heat flow in a system, and depends upon the thermal conductivities of the heat spreading layer and the heat sink. As the thermal conductivity of the spreading layer increases relative to the heat sink, the heat will travel further laterally and the spreading angle will increase. A diamond layer'will produce the largest spreading angle of any material for a given heat sink material and design. Diamond therefore produces the greatest rate of heat dissipation from the circuit component. The area and thickness of CVD diamond used in a particular circuit design will depend upon the thermal performance required and the cost restraints. The cost of CVD diamond increases almost linearly with increasing film thickness and film area. As the area of the diamond is increased, for a given thickness, the heat

Diomond in Electronic Packages

335

removal rate will increase until the spreading angle is exceeded. Once the spreading angle is exceeded, no gain will be achieved with further increase in area. Similarly, thermal modeling has shown the heat removal rate will increase with increasing diamond film thickness, for a constant film area, only up to a certain point after which a plateau occurs. The film thickness at the onset of the plateau depends on the parameters selected for the model, but has been estimated to be around 200-400 pm for heat sources such as laser diodes [71]. To minimize cost packages should therefore be designed to minimize the area and thickness of diamond used, and this can be done without sacrificing thermal performance.

1 5 . 6 Conclusion Currently CVD diamond is being used as a substrate for high power discrete devices such as laser diodes, FETs, and I M P A T T diodes. CVD diamond's lower cost is helping it to replace natural and H P H T synthetic diamond, and its superior thermal performance is helping it to replace BeO substrates. For these discrete devices the size of the diamond substrate is small, only about 1 mm2. CVD diamond is also being evaluated in larger area applications, such as for entire hybrid circuit substrates and multichip modules. And opportunities exist for further expansion of CVD diamond in electronic packaging. As production costs fall and manufacturing experience increases, CVD diamond could penetrate more deeply into lower cost markets dominated by AIN and BeO.

References 1. J.E. Field (ed.), The Properties of Diamond, Academic Press, New York, 1979. 2. R.C. Devries, Ann. Rev. Mater. Sci. 17 (1987). 3. R.J. Wedlake, in The Properties of Diamond, edited by J.E. Field, Academic Press, New York, 1979. 4. J.C. Angus, P. Koidl, and S. Domitz, in Plasma Deposited Thin Fihns, edited by J. Mort and F. Jansen, CRC Press, Boca Raton FL, 1986, Ch. 4. 5. K. Ogata, Y. Andoh, and E. Kamijo, in Nuclear hlstruments and Methods in Physics Research, B33, North Holland, Amsterdam, 1988. 6. M. Kitabatake and K. Wasa, J. Vac. Sci. Technol. A6, 3 (1988). 7. J.C. Angus and C.C. Hayman, Science 241 (1988). 8. S. Matsumo, Y. Sato, M. Tsutsumi, and N. Setaka, J. Mater. Sci. 17 (1982). 9. B. Singh, O.R. Mesker, A.W. Levine, and Y. Arie, Appl. Phys. Lett. 52, 451 (1988). 10. F. Jansen, M.A. Machonkin, and D.E. Kuhman, J. Vac. Sci. Tech. A8, 5 (1990). 11. W.A. Yarbrough and R. Roy, in Extended Abstracts 15, Diamond and DiamondLike Materials Synthesis, edited by G.H. Johnson, A.R. Badzian, and M.W. Gies, Materials Research Society, Pittsburgh PA, 1988. 12. P.J. King and Y. Tzeng, J. Appl. Phys. 66, 10 (1989). 13. T. Debroy, K. Tankala, W.A. Yarbrough, and R. Messier, J. Appl. Phys. 68, 5 (1990). 14. A. Sawabe and T. Inuzuka, Appl. Phys. Lett. 46, 146 (1985).

336

MATERIALS FOR ELECTRONIC PACKAGING

15. M. Kamo, Y. Sato, S. Matsumoto, and N. Setaka, J. Crvst. Growth 62, 642 (1983). 16. P.K. Bachmann, W. Drawl, D. Knight, R. Weimer, and R. Messier, in Extended Abstracts 15, Diamond and Diamond-Like Materials Synthesis, edited by G.H. Johnson, A.R. Badzian, M. Geis, Materials Research Society, Pittsburgh PA, 1988. 17. D.J. Pickrell, W. Zhu, A.R. Badzian, R. Messier, and R. Newnham, Appl. Phys. Lett. 56, 20 (1990). 18. J. Suzuki, H. Kawarada, K. Mar, J. Wei, Y. Yokota, and A. Hiraki, Jpn. J. Appl. Phys. 28, 2 (1989). 19. V.P. Varnin, I.G. Teremenskaya, D.V. Fedoseev, and B.V. Deryagin, Soy. Phys. Dokl. (Engl. Transl.) 29, 5 (1984). 20. S. Matsumoto, J. Mater, Sci. Lett. 4, 600-602 (1985). 21. P.K. Bachmann and H. Lydtin, Mater. Res. Soc. Symp. Proc. 165 (1990). 22. K. Kurihara, K. Sasaki, M. Kawarada, and N. Koshina, Appl. Phys. Lett. 52, 6 (1988). 23. S. Matsumoto, M. Hino, and T. Kobayashi, Appl. Phys. Lett. 51, 737-739 (1987). 24. Y. Mitsuda, T. Yoshida, and K. Akashi, Rev. Sei. Instrum. 60, 2 (1989). 25. Y. Hirose and N. Kondo, paper presented at the Japan Society of Applied Physics Meeting, Tokyo, 1988. 26. L.M. Hanssen, W.A. Carrington, J.E. Butler, and K.A. Snail, Mater. Lett. 7, 289 (1988). 27. M. Tsuda, M. Nakajima, and S. Oikawa, J. Am. Chem. Soc. 108 (1986). 28. M. Frenklach and K.E. Spear, J. Mater. Res. 3, 1 (1988). 29. F.P. Doty and W.A. Jesser, J. Electronic Materials 20, 2 (1991). 30. S.J. Harris and A.M. Weiner, Appl. Phys. Lett. 53, 17 (1988). 31. F.G. Celli, P.E. Pehrsson, H.T. Wong, and J.E. Butler, Appl. Phys. Lett. 52, 24 (1988). 32. C.H. Wu, M.A. Tamor, T.J. Potter, and E.W. Kaiser, J. Appl. Phys. 68, 9 (1990). 33. F.G. Celli and J.E. Butler, Appl. Phys. Lett. 54, 11 (1989). 34. A.R. Badzian and R.C. Devries, Mater. Res. Bull. 23, 385-400 (1988). 35. K.E. Spear, J. Am. Ceram. Soc. 72, 2 (1989). 36. T.R. Anthony, Vacuum 41, 4-6 (1990). 37. T. Kawato and K. Kondo, Jpn. J. Appl. Phys. 26, 9 (1987). 38. Y. Saito, K. Sato, H. Tanaka, K. Fujita, and S. Matsuda, J. Mater. Sci. 23, 3 (1988). 39. S.J. Harris and A.M. Weiner, Appl. Phys. Lett. 55, 21 (1989). 40. D.E. Patterson, C.J. Chu, B.J. Bai, N.J. Komplin, R.H. Hauge, and J.L. Margrave, in Applications of Diamond Films and Related Materials, edited by Y. Tseng, M. Yoshikowa, M. Murakawa, and A. Feldman, Elsevier, New York, 1991. 41. W. Howard, D. Huang, J. Yuan, M. Frenklach, and K.E. Spear, paper presented at the Second International Conference on the New Diamond Science and Technology, Washington, D.C., Sept. 23-27, 1990. 42. P.K. Bachmann, W. Drawl, D. Knight, R. Wiemer, and R. Messier, in Extended Abstracts 15, Diamond and Diamond-Like Materials Synthesis, edited by G.H. Johnson, A.R. Badzian, and M.W. Geis, Materials Research Society, Pittsburgh PA, 1988. 43. B. Lux and R. Haubner, in Diamond and Diamond-Like Films and Coatings, edited by R.E. Clausing, Plenum Press, New York, 1991. 44. B.E. Williams, J.T. Glass, R.F. Davis, K. Kobashi, and Y. Kaware, in Extended Abstracts 15, Diamond and Diamond-Like Materials Synthesis, edited by G.H. Johnson, A.R. Badzian, and M.W. Gies, Materials Research Society, Pittsburgh PA, 1988.

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337

45. D.N. Belton, S.J. Harris, S.J. Schmieg, A.M. Weiner, and T.A. Perry, Appl. Phys. Lett. 54, 416 (1988). 46. R. Meilunas, M.S. Wong, K.C. Sheng, and R.P.H. Chang, Appl. Phys. Lett. 54, 2204 (1989). 47. M. Hansen, Constitution of Binary Allo)'s, McGraw-Hill, New York, 1958. 48. D.J. Pickrell, W. Zhu, A.R. Badzian, R.E. Newnham, and R. Messier, J. Mater. Res., 6, 6 ( 1991). 49. C. Wild, N. Herres, and P. Koidl, J. Appl. Phys., 68, 3 (1990). 50. R.E. Clausing, L. Heatherly, E.D. Specht, and K.L. More, in Proc. 2nd Int. Conjl New Diamond Science and Technology, edited by R. Messier, J.T. Glass, J.E. Butler, and R. Roy, Materials Research Society, Washington D.C., 1990. 51. W.J.P. van Enckevort, G. Janssen, W. Vollenberg, J.J. Schjermer, L.J. Giling, and M. Seal, Diamond and Related Materials 2, 5-7 (1993). 52. W. Zhu, A.R. Badzian, and R. Messier, J. Mater. Res. 4, 3 (1989). 53. B.E. Williams, H.S. Kong, and J.T. Glass, J. Mater. Res. 5, 4 (1990). 54. E.A. Burgermeister, Physica 93B (1978). 55. A.V. Virkar, T.B. Jackson, and R.A. Cutler, J. Am. Ceram. Soc. 72, 11 (1989). 56. T.R. Anthony, W.F. Banholzer, J.F. Fleischer, L. Wei, P.K. Kuo, R.L. Thomas, and R.W. Pryor, Phvs. Rev. B. 42, 2 (1990). 57. T.R. Anthony, J.L. Fleischer, J.R. Olson, and D.G. Cahill, J. Appl. Phys. 69, 12 (1991). 58. A.V. Heatherington, C.J.H. Wort, and P. Southworth, J. Mater. Res. 5, 8 (1990). 59. Z.L. Wang, J. Bentley, R.E. Clausing, L. Heatherly, and L.L. Horton, in Applications of Diamond Films and Related Materials, edited by Y. Tzeng, M. Yoshikawa, M. Murakawa, and A. Feldman, Elsevier, New York, 1991. 60. J.E. Graebner, S. Jin, G.W. Kammlott, J.A. Herb, and C.F. Gardinier, Appl. Phys. Lett. 60, 13 (1992). 61. J.E. Graebner, S. Jin, G.W. Kammlott, B. Bacon, L. Seibles, and W. Banholzer, J. Appl. Phvs. 71(11)(1992). 62. N. Kuramoto, H. Taniguchi, and I. Aso, Ceram. Bull. 68, 4 (1989). 63. Y. Tokeda, Ceram. Bull. 67, 2 (1988). 64. S. Yazu, New Diamond No. 2 (1990). 65. A. Ono, T. Baba, H. Funamoto, and A. Nishikawa, Jpn. J. Appl. Phys. 25, 10 (1986). 66. J.E. Graebner, S. Jin, G.W. Kammlott, J.A. Herb, and C.F. Gardinier, Nature 359 (1992). 67. J.E. Graebner, Diamond Films and Technol. to be published. 68. M.I. Landstrass and K.V. Ravi, Appl. Phys. Lett. 55, 10 (1989). 69. D.S. Hoover, D.J. Pickrell, and M. Kelly, in Proc. 1st Int. Conf. Applications of Diamond Films and Related Materials, Auburn AL, 1991. 70. D.J. Pickrell and D.S. Hoover, Inside ISHM, July/Aug. 1991. 71. D.J. Pickrell, D.S. Hoover, and C.M. Kelly, Adv. Packaging, 1(2) (1992).

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VI

Materials Testing

16 Measurements of Properties of Materials in Electronic Packaging Joseph A. Carpenter, Jr.

16.1

Introduction

Designers require reliable values of properties of the materials in electronic packaging in order to accurately predict the performance of their products. This chapter looks at techniques for measuring the important electrical, thermal, mechanical, and physical properties of electronic packaging, and three other properties which assess the ease, efficiency, degree of success, or costs of processing the materials, manufacturability properties, for want of a better term. Techniques for structural and chemical analyses, which indicate the properties have certain values, are well covered elsewhere [1-3]. Examples of data for important properties are presented in Tables 16.1 through 16.3; this is to provide a feel for the property ranges of contemporary packaging materials. Several recent works on electronic packaging technology provide more extensive tabulations [4] [5] [-6] [-7] [8]. Reference [7] is especially thorough and [8] is particularly good in identifying the methods used to make the measurements which are reported. Even more data can now be obtained via computerized searches of electronic databases [9], some on line. Because of limitations in space, only brief descriptions of the techniques are given here. The principal approach in this chapter is to outline this very broad subject and guide the reader to a few current references which provide illustrations; details on applicability, procedures, and expected accuracies and precisions; and further references. The American Society for Testing and Materials (ASTM) Annual Book of A S T M Standards [ 10] and the Test Methods Manual [ 11] of The Institute for Interconnecting and Packaging Electronic Circuits (IPC) are especially valuable for detailed descriptions of methods that have been standardized. Definitions of properties names, terms and units are assumed in this chapter to be as given in [ 10]. 341

Table 16.1

Selected electrical properties of typical materials in electronic packaging, from [7]. Resistivity fn m )

Mureriul Epoxy glass printed wiring board substrate Alumina substrate Silicon substrate Polyimide dielectric film Epoxy adhesive Epoxy encapsulant Electrodeposited copper 63Sn-37Pb solder

1O1O

> 10l2 640 10l6 10~~-10~~ 1012-1013 17-20 x lo-' 1.45 x lo-'

w P

u

Dielectric strength f V/cm)

Dielectric constant at I M H z

Dissipation factor at I MHz

18-158 x lo3 3 x lo3

4.5-5.2 9.9-10

0.01-0.025 0.0003-0.0005

-

-

-

235G2750 x lo3 157 x lo3 11G177 x lo3

3.5 3.4-3.6 3.5-4.8

0.003 0.016-0.32 0.006-0.029

-

-

-

-

-

-

3

5

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n

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2

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Table 16.2

Selected thermal properties of typical materials in electronic packaging, from [7]. Conductioit~v (Wm-I K-')

Epoxy glass printed wiring board substrate Alumina substrate Silicon substrate Polyimide dielectric film Epoxy adhesive Epoxy encapsulant Electrodeposited copper 63Sn-37Pb solder

CTE

K- ' )

Specijic heat (Jkg-' K-l)

Ma-uimum use temperature ( K )

Table 16.3

Selected mechanical and physical properties of typical materials in electronic packaging, from [7].

Material

Epoxy glass printed wiring board substrate Alumina substrate Silicon substrate Polyimide dielectric film Epoxy adhesive Epoxy encapsulant Electrodeposited copper 63Sn-37Pb solder

Tensile strengtlz f MPa)

Fle.uure strengtll f MPa)

Elastic modulus f GPa)

Density (kg/m3)

Moisture absorption (%)

344

MATERIALS FOR ELECTRONIC PACKAGING

16.2 Electrical Properties The electrical properties of main interest in electronic packaging are resistivity, dielectric strength, dielectric constant, and dissipation factor [ 10, D 1711-92]. a Representative values are given in Table 16.1. Magnetic properties are rarely reported since few materials seen in modern packaging are magnetic. The volume b resistivity of a material is normally determined by measuring the resistance, cross-sectional area, and length of a specimen between two direct-current-carrying contacts. The resistance is determined by means of Ohm's law by measuring the relationship between applied and resultant current and voltage. In a two-point probe method, the voltage and current are measured by external circuits using the two contacts. For insulators, the electrodes are usually placed on opposite sides of the specimen, often utilizing a third (guard) electrode to avoid leakage currents, as shown in Figure 16.1 [10, 257-91]. For conductors, the current contacts are often placed on the same side of the specimen. In a four-point probe method, the voltage is measured separately from the current by means of two additional contacts, usually located between those supplying the current. [12] [10, B-193-87, D257-91, D1829-90, D4496-87] [11, 2.5.9, 2.5.13, 2.5.14, 2.5.17]. In the standard tests for dielectric strength, electrodes of circular or square cross section are applied to opposite faces of a material specimen of known uniform thickness, and the voltage is increased smoothly or stepwise until a sudden, large increase in the electrical conductivity is measured or mechanical failure occurs.

ELEETRIIOE NEI 1 GUARDELEETRllOE

SPEEIMEN

ELEETRlqEIENil 2 Figure 16.1 Typical specimen configuration for measurement of volume resistivity using two current electrodes (1 and 2) and a third guard electrode. See [10, D257-91] for further details. "The standards are identified in the text by a reference number followed by a comma and the standard number. Thus [9, B193-87] designates ASTM standard B193-87 [10, 2.5.5.4] designates IPC-TM-650 method 2.5.5.4. b This is the resistivity most often reported in the electronics literature. See the references at the end of the paragraph for discussions of weight and surface resistivities.

Measurements of Properties of Materials in Electronic Packaging

34~

The voltage may be alternating, usually 60 Hz, or DC. This property is most important in high power electronics and very thin insulating films [13] 1-10, D149-91, D3755-86] [11, 2.5.6.2]. The dielectric constant and dissipation factor of a dielectric are important because, among other things, they affect, respectively, the speed and the shape of a pulse propagating through a conductor on or surrounded by the dielectric. There are three general methods for determining them: lumped element, resonant, and transmission line [14]. In the typical lumped element technique, the sample is inserted between and in contact with two flat plate or coaxial electrodes of known dimensions and the capacitance and conductance are measured to yield the dielectric constant and loss factor. A specimen configuration such as that shown in Figure 16.1 is typical. These methods can be used for measurements over a range of frequencies up to about 1 GHz. Most dielectric constant and dissipation factor data in the literature were obtained in this way, typically at 1 MHz. Microdielectrometry, an outgrowth of this approach, is used to monitor changes in specimens, but as yet has not been accepted as a method for providing accurate data [ 10, D 150-87, D669-92, D2149-90] [ 11, 2.5.5.1] [ 15]. Pulse risetimes shorter than 100 ps are becoming commonplace, so measurements of the dielectric constant and the loss factor at frequencies up to about 100 GHz are needed. Resonant and transmission line methods are required at frequencies above 1 GHz and are considerably more difficult to perform than the lumped element techniques. Examples are shown in Figure 16.2. In a resonant

sample

APC7 cell

.... /..

.....

I

I

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I

m~/I/ll//I/I////////////////////////////////////////[[/////#

R~sodator

~strate

(a) (b)

PUMPBEAM ~ L E N S

TR~N._SMIT._T_~R

SAMPLE

PROBEBEAM

RE_CE/VEN (e)

CURRENT LOCK-IN

AMPLIFIER AMPLIFIER

Figure 16.2 Examples of techniques used to measure the dielectric constants and loss factors of dielectrics at high frequencies (> l GHz): (a) coaxial transmission technique, (b) microstrip resonator method, and (c) free-space bridge transmission. See [18] and [19] for details.

346

MATERIALSFOR ELECTRONIC PACKAGING

method, the specimen is loaded into or made part of a resonant cavity or structure and the resonant frequency and quality factor are measured to yield the dielectric constant and dissipation factor [10, 2520-86, D3380-90] [11, 2.5.5.5] [16] [17]. In a transmission line method, changes of the amplitude, phase and/or shapes of waves propagated through or reflected by a sample are measured to yield the same parameters [ 18] [ 19]. Another possibility is the use of pulse propagation delay and shape analyses. In these approaches, the time delay and degradation of a pulse along a conductor surrounded by an insulator might be used to measure the dielectric constant and loss factor of the insulator. This approach is similar to time domain reflectometry commonly used in industry for assessing the electrical quality of packaging. These approaches also offer the possibility of using the conductors in the packaging for in situ measurements. Recent work [20] [21] suggests the exploration of such techniques may have begun. 16.3

Thermal Properties

The thermal properties of main interest in modern electronic packaging are thermal conductivity/diffusivity, thermal expansion, specific heat, and maximum use temperature. Representative values are given in Table 16.2. References [22] through [28] are recommended, especially the more recent ones, [27] and [28]. Thermal conductivity [ 10, C 168-90] is the major material property determining the ability of packaging to dissipate heat. The overall thermal resistances of packages are experimentally assessed by means of thermal test chips or other devices of known heat output mounted in the package and measurements of the overall temperature drop between the test chip or heating device and the exterior of the package. The temperature profiles in the package are then calculated via models using values of the thermal conductivity [29] [30] [31]. Following Touloukian et al. [22], the methods for measuring thermal conductivity can be categorized as either steady-state or nonsteady-state. In a steady-state method the measurements are made after thermal equilibrium has been reached whereas in a nonsteady-state method measurements are made while the temperature is changing. The nonsteady-state methods determine the thermal diffusivity from which the thermal conductivity may be calculated by multiplying the thermal diffusivity by the material density and specific heat. Techniques for measuring density and specific heat are discussed below. A thermal conductivity value derived from such a calculation may not agree with the measured value because of such factors as variable anisotropies in the specimens and differences in the mechanisms of heat transfer, specific heats, and densities over the temperature ranges of the two methods. Unknown impedances of interfaces may also lead to large uncertainties in the test configuration. The majority of the thermal conductivity data in the literature is derived from either the guarded hot plate method [10, C177-85] or the longitudinal bar method [10, E1225-87]. Both are steady-state methods in which heat flows in one

Measurements of Properties of/Hateriab in Electronic Packaging

347

direction through the short thickness of a disk or plate (guarded hot plate) or down the long axis of a bar or rod (longitudinal bar) and the resulting temperature gradients are measured to yield the thermal conductivity knowing the heat flow and the cross-sectional areas of the specimens [32]. Though most such measurements have been made on bulk specimens, Decker et al. [33] employed thin film thermocouples to measure the thermal conductivities of dielectric films less than about a micrometer thick; the results indicated thermal conductivities as much as one order of magnitude lower than those of bulk specimens. A thermal comparator technique, in general, is one in which the thermal property is derived by comparing the thermal response of the unknown specimen with the responses of similar specimens with known thermal properties. The expected uncertainties in thermal conductivities measured by a thermal comparator method are typically twice those measured by the guarded hot plate or longitudinal bar methods [28, Chs. 1, 3-1.In a novel, steady-state, thermal comparator technique, a probe tip heated to one temperature is touched to the surface of the unknown specimen held at another temperature and the intermediate temperature of the probe at equilibrium is determined. The probe tip is similarly touched to specimens of known thermal conductivities to provide a calibration curve of intermediate equilibrium temperatures versus thermal conductivity from which the thermal conductivity of the unknown can be determined. Lambropoulos et al. [34] report results, using the thermal comparator shown in Figure 16.3, which indicate thermal conductivities of thin films two orders of magnitude lower than those of bulk specimens. Reference [34] is an excellent review of other techniques for making measurements of the thermal conductivities of thin films.

Probe

Substrate_ ~

Sample

/

Film Layer ~ t / ~ i 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ~ (_ __Sensing.Tip-~ ConslantanTubing u.z:)-mm alam.)x~ll~-~,~/ ~N~lll~~Constantan Block CopperHeating / / ~ ~ 1 1 : ~ ~ Block :

Heat

Figure 1 6,3 Schematic of thermal comparator probe used to measure the thermal conductivities of thin films. For details see text and references listed in [34] and [35].

348

MATERIALS FOR ELECTRONIC PACKAGING

The nonsteady-state methods are further categorized [21] as either transient or periodic. In a transient method a single application of heat is made and the rate of change of temperature is measured. In a periodic method the heat is applied at some point on the specimen in pulses of fixed period, and the amplitude, velocity, and phase of resulting pulses at other points on the specimen are measured with reference to those of the pulses at the point of application. The flash diffusivity method [32] [36] [37] [38] is a transient method in which a short burst of radiant energy is applied to one face of a thin specimen and the temperature profile on the opposite face is measured as a function of time, usually by means of a thermocouple of small mass or an infrared sensor. The thermal diffusivity is calculated from a time characteristic of the rise (usually the half-rise time, tso) to a maximum temperature and the square of the measured specimen thickness. In early versions of this method, the heat pulse was applied uniformly to the specimen face, typically by means of a flash lamp, but more commonly now it is applied by a laser or sometimes an electron beam, both of which permit micrometer-scale resolution probing of any variations of the diffusivity at various points on the specimen. In the case above where the temperature is measured directly opposite from the point of heat application, the diffusivity parallel to the specimen thickness is measured. In another version of the flash diffusivity method, the temperature-time profile is monitored at a point on the back of the specimen, somewhat removed from the location of the point directly opposite the location where the heat pulse is applied, so the diffusivity parallel to the plane of the specimen can also be measured. For highest accuracies, this requires calibration by means of standards of known diffusivity. Other possible transient techniques that may be applied in the future to packaging materials include the forced Rayleigh scattering method and the use of thin film thermocouples. In forced Rayleigh scattering [39], two laser beams are crossed at a point on the surface of a specimen to create fringes. These fringes produce a standing heat wave pattern, which serves as a temporary diffraction grating as result of the change of refractive index with temperature. A third laser beam is directed through this grating, and the change of the diffraction angle with time after the two crossed beams are turned off yields the thermal diffusivity. Of course, the specimen must be transparent to the third (probing) laser beam. Thin film thermocouples [40] deposited onto a specimen may be pulse heated, and the fall in temperature with time may be used to determine the diffusivity of the substrate. Since metals such as copper and platinum, used as conductors in packaging, are also used in thermocouples, it is possible that thin film thermocouples might be formed within the packaging multilayer structures, thus providing measurements to verify the thermal models used today or monitor process and service conditions. Tye et al. [36] [37] have described a periodic method termed the AC calorimeter. A portion of the face of a long, thin, rectangular specimen is irradiated with chop-modulated light from a lamp or a defocused laser while the other portion is shielded from the heat by a mask. The temperature of the specimen at a position

Measurements of Properties of Materials in Electronic Packaging

349

shielded by the mask is measured by a thermocouple. The thermocouple measures the temperature amplitudes with the mask edge located at various positions along the long side of the rectangular specimen. The logarithms of the amplitudes are plotted versus distance between the mask edge and the thermocouple. The slope of the line is proportional to the ratio of the frequency divided by the diffusivity, from which the diffusivity can be calculated since the frequency is known. This method is a measure of the diffusivity in the plane of the specimen. In another technique [41], somewhat similar to the AC calorimeter and the flash techniques, periodic heating pulses are applied to one face of a thin specimen and the temperature-time profiles are measured on the other face. The frequency is varied and the temperature amplitudes of the pulses on the back are measured. The amplitudes are plotted as functions of the square root of the frequency to yield a straight line with a slope proportional to the thickness of the specimen divided by the square root of the diffusivity, which can be calculated knowing the thickness. For this method to work, the specimen must be thinner than the thermal diffusion length, meaning that for most of the polymers and ceramics in packaging, the specimen must be no more than a few to a few hundreds of micrometers thick. In thermal wave techniques [42] [43], a thermal pulse or wave is introduced at a point on the surface of a specimen and the resultant temperature is measured at a point on the same surface, either by pyrometry or an effect on the atmosphere just above it. The penetration of the thermal energy into the surface can be varied by varying the frequency of the incident pulse, thus providing a way of measuring the diffusivity at various thicknesses near the surface. This method has the advantage that access to only one free surface is required. The relative thermal expansions of the various materials in an electronic package determine the extent of thermally induced stresses in the packaging and the chips it contains. Though expansion occurs in three dimensions, the expansion in only one dimension is usually measured. Data are most often reported as linear coefficients of thermal expansion (CTE) assumed constant to a reasonable degree of approximation over a limited range of temperatures. The main methods available for measuring thermal expansion are [24] dilatometry, telemicroscopy, interferometry, capacitance, and (for crystalline materials) X-ray diffraction. Dilatometry remains by far the commonest way to measure most packaging materials. Telemicroscopy and X-ray diffraction methods are hardly ever seen in the packaging literature. In a dilatometric technique, one end of a long, thin probe rod made of a material of known thermal expansion characteristics touches the specimen, held in a heating or cooling chamber. The other end of the rod protrudes from the chamber and the expansion of the specimen upon heating or cooling is determined by measuring the movement of the protruding end of the probe rod by some means, usually electromechanical or optical [10, E228-85, D696-91] [11, 2.4.41, 2.4.41.1]. A thermomechanical analyzer (TMA) [10, D3386-84] [11,2.4.24] is a form of dilatometer typically used in bulk polymers measurements. The precision of dilatometry is on the order of + 1 ~m which, while adequate for many applications, is not adequate for high accuracy or applicable to thin films, which are themselves

350

MATERIALS FOR ELECTRONIC PACKAGING

only a few micrometers thick. In these cases other capacitance or interferometric techniques are required. Capacitance [44] and laser-based interferometric [45] techniques have been used for measuring CTE in the direction of film thicknesses. An example of a recently developed capacitance method is given in Figure 16.4. Strain gages have been used to measure the inplane thermal expansion of ceramics and metals used in packaging [46]. Resistive thin films used as strain gages are another possibility provided compensation can be made for the effects of temperature on the resistance of the films; films with low thermal coefficients of resistance (TCRs) appear most promising. Moir6 interferometry has been used [47] to follow the thermally induced distortions of packaging, but not to measure values of the expansion properties. Because the specific heat determines the temperature to which a material will rise for a given heat input, it is especially important in analyses to determine the maximum temperature the packaging will reach as a result of the input of a sudden, transient heat spike. It is also needed in deriving the thermal conductivity from the nonsteady-state methods discussed above. The most basic calorimetric methods [25] [27] [28] involve dropping a specimen heated to a known temperature into an adiabatic chamber containing another known substance at some other known temperature, and determining the final equilibrium temperature achieved by the specimen and the other substance. It can also be determined by differential scanning calorimetry (DSC) [ 10, E 1269-90] and the AC calorimeter technique discussed above for use in determining the thermal diffusivity [36] [37]. In a DSC, an unknown specimen and a standard are subjected side-by-side to a predetermined rate of temperature increase in an apparatus in which the heat flow into the unknown and standard can be determined. Analyses of the heat flows into the unknown versus the standard determine the heat capacity of the unknown. In the case of modern packaging, the m a x i m u m use temperature of concern is usually determined by a relevant property of the polymers. The glass transition temperatures of the thermoplastic polymers are often reported as rough indicators of their maximum use temperatures; in practice, maximum use temperatures are usually set by the degradation of some property to a specified value in a given time. The glass transition temperature is determined by TMA [11, 2.4.24], DSC [10, E1356-91] [11, 2.4.25] and dynamic mechanical thermal analysis (see stress-strain response in the next section). The glass transition temperature of a polymer is the temperature, really a narrow range of temperatures, at which the material changes from a rigid to a rubbery solid. It is most important in considering possible deleterious effects arising from the various higher temperature procedures involved in fabrication and assembly. The melting temperatures of the metals and ceramics in packaging are usually provided as rough indicators of their maximum use temperatures, but maximum use temperatures are actually set with reference to the temperature at which the materials will degrade in a certain time due to such factors as oxidation, corrosion or reactions with other materials. This is true for polymers and especially true for solder.

Measurements of Properties of Materials in Electronic Packaging

351

CAPACITANCE METER m

HP 16048B TEST LEADS

[2

FUSED QUARTZ PLATE

CABLE

WEIGHT

POLYMER FILM HOT PLATE

ALIGNMENT CROSS

TOP ELECTRODE PLATE

POLYMER FILM

BOTTOM ELECTRODE PLATE

Figure 1 6 . 4 Recently developed capacitance method for measuring the coefficient of thermal expansion of polymer films. The C-shaped film establishes the thickness of the air gap between the top and bottom electrodes and the thickness is gaged by measuring the capacitance. See [44] for details.

352

MATERIALSFOR ELECTRONIC PACKAGING

16.4

Mechanical Properties

The mechanical properties are important as they determine the ability of the packaging to resist stresses imposed thermally or mechanically during processing or in service. The main properties of interest are the stress-strain responses, adhesion, and residual stress. Representative values of some stress-strain response properties are given in Table 16.3. The stress-strain responses of main interest in packaging are the elastic responses and time-dependent properties of creep, stress relaxation, and fatigue. Uniaxial tensile testing of cylindrical or fiat specimens [10, E8-91, E345-87, D638-90, D882-90] [11, 2.4.18, 2.4.19] has been used mostly for measuring the elastic responses of the metals and polymers used in packaging, whereas three- and four-point flexure testing has been used mostly for measuring ceramics [48] [49] and many polymers, especially laminates [10, D790-91-] [11, 2.4.4, 2.4.4.1]. Techniques for tensile testing of specimens (Fig. 16.5) with micrometer dimensions typical of features in modern packaging are under development [50] I-511. Biaxial tests are sometimes seen [52] [53] [54]. In addition to tension, solders are often tested in shear, double-lap shear [55], and torsion [56]. The elastic strength

Figure 16.5

Scanning electron micrograph showing enlargement of the miniature arrays of four tensile specimens, each 0.25 mm wide, 1 mm long and 2.2 #m thick, prepared using deposition, patterning and etching processes common to the semiconductor industry. Each array of four specimens is carried on and protected by a 6 mm • 8 mm rectangular silicon frame, similar in size and shape to IC dies. See [50] and [51] for details.

Measurements of Properties of Materials in Electronic Packaging

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properties are usually reported as the elastic (Young's) modulus and stresses and strains where the material departs significantly from elastic behavior under the conditions of the test. The most significant test variables are temperature and rate of loading. Dynamic mechanical thermal analysis is used to measure the complex (measuring both the parts of elastic response in phase and out of phase with the applied stress) elastic modulus of polymers in oscillating flexure or shear [57]. This technique is often also used to detect the glass transition temperatures. Acoustic analyses [58] and microindentation [59] [60] can be used to measure the tensile and shear moduli of materials. Poisson's ratio is determined by measuring a dimension of a specimen in a direction perpendicular to the axis of applied stress. Creep and stress relaxation are of concern to the long-term reliability mainly of polymers and solder, which in packaging often operate at temperatures near to their maximum use temperature. In a creep test, a specimen is quite rapidly loaded to a stress significantly below the point at which it no longer behaves elastically then its extension at constant load or its stress is measured. A stress relaxation is performed in a similar way but measures the specimen stress as constant extension. The loading may be in tension, compression, flexure, or shear [55] [10, E328-86, D2990-90, D2991-84]. Tension is most appropriate for surface mount solders and for polymers, which tend to be in tension because their CTE is high with respect to other materials. Compression and shear are appropriate for solder used in die attach. Fatigue is the number of cycles required to fracture a specimen that has been repetitively cycled between two elastic stresses. It is of primary concern to the mechanical reliabilities of the thin film conductor stripes and the solder. The electrical conductor stripe material is almost always measured in alternating tension [10, E796-88] [11, 2.4.2.1], whereas the solders are measured in tension [61], compression [62], and shear [63]. Adhesion is the property that assesses how well two parts, properly termed adherends, resist being separated at their junction. Adhesive separations truly occur at the interface; cohesive separation occurs within the adherends. Of the hundreds of approaches for testing adhesion that have been developed [64] over the years, only a few have been used in packaging; excellent recent reviews are available [65] [66] [67]. These approaches include direct pull-off, direct shear, peel, scratch, stretch, laser spallation, and microindentation [ 11, 2.4.1, 2.4.1.2, 2.4.8, 2.4.9, 2.4.20, 2.4.21 ]. Three popular techniques are shown in Figure 16.6. Each yields measurements dependent in complicated ways on the properties of the two adherends, the strength of the interface, and the geometry of the bond. Since the true strength of the interface is virtually impossible to measure quantitatively, these approaches are best categorized as semiquantitative screening tests rather than measurements of basic material properties. Intrinsic residual stress results from defects introduced in the processing of packaging materials, whereas extrinsic residual stress results from the mismatch of their CTEs. Materials having residual stresses of the same nature (tension, compression, or shear) and the same sign as an externally imposed stress can fail at a much lower value than expected because much of their strength has already

354

MATERIALS FOR ELECTRONIC PACKAGING

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F

t

e

1

ii~ P

ROUNDEDSTYLUS

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SUBSTRATE

SUBSTRATE

COsuBSTRATE

(a)

(b)

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SIDE VIEW

P

Au-Sn BRAZE OR Pb-Sn SOLDER

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TOP VIEW

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been consumed by the residual stress. X-ray diffraction has been used to measure residual stress in packaging metallization and ceramic substrates [68]. The most popular methods for measuring polymers are based upon the bending of a substrate on which the polymer has been deposited [69]; commercial instruments are available. Indentation [59] [70] has recently been used [71] to map the residual stresses in ceramic substrates near bonding pads (Fig. 16.7). Laser-based methods, making use of infrared or Raman lines, have been used to measure stress in surfaces of ceramics and polymers [72], and cathodoluminescence lines, induced by electron

Measurements of Properties of Materials in Electronic Packaging

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beams, have been shown to exhibit shifts with stress. Because of their potential for high spatial resolution, methods based on indentation and spectral line shifts should find wider use in the future.

16.5 Physical Properties The physical properties of most interest are density and moisture absorption. Representative values are given in Table 16.3. Density determines the designed weight of the packaging and is needed to calculate many of the electrical, thermal, and mechanical properties, for example, to calculate the thermal conductivity from the thermal diffusivity measured by a nonsteady-state test. It can be determined by simply measuring the specimen dimensions and the specimen weight or by displacing the specimen in a liquid or gas of known density [10, D792-91]. Moisture absorption is of great concern in polymer applications, in fact so great is the concern there are current efforts to formulate polymers with low absorption and to provide other means of protecting the chips from moisture while still using the polymers to reduce costs associated with ceramic and metallic packaging that is completely hermetic. Moisture can result in swelling of the polymer and concentration of ionic species which can corrode the metallization. It can also cause changes in many of the properties mentioned above and even the popcorn phenomenon, catastrophic puffing or delamination during soldering [73]. The moisture absorption test method most commonly seen in the packaging literature is simply to weigh a sample as a function of time in a controlled humidity environment [74] [11, 2.6.2]. More sophisticated techniques are used, such as coulometry [10, D4019-88] and change of frequency of a vibrating substrate (e.g., a quartz crystal) covered with an absorbing polymer film [75].

16.6 Manufacturability Properties Manufacturability properties have an important bearing on the ease, efficiency, degree of success, or costs of processing the materials. The manufacturability properties of most interest are solderability, degree of polymer cure, and viscosity. Solderability is a term used to describe a combination of subjective and semi-quantitative factors determining the relative ease with which solder joints can successfully be made in an industrial setting. It is most often characterized by the solder wettability, the ease and tenacity with which the molten solder spreads on the substrate. The simplest test is the dip-and-look test in which a substrate is dipped into a solder bath and examined visually to determine how much of the substrate area is covered [11, 2.4.12, 2.4.14, 2.4.14.1). The most common quantitative method is the wetting balance or meniscograph method in which a test specimen is dipped into a solder bath and the force it experiences measured as a function of time [76]. The principle is depicted in Figure 16.8. The deyree of cure is important because it determines the desired achievement of many of the other properties and the degree of stability of the polymer itself. For example, incomplete cure can leave unreacted chemicals which, in the presence

356

MATERIALS

FOR

ELECTRONIC

PACKAGING

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-1.0

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0

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6

TIME (s)

Figure 1 6 . 8 Wetting balance test for solderability. The test specimen is dipped into a solder bath and the force it experiences is measured as a function of time [76]. The solder bath will tend to reject all specimens at first and will wet some more rapidly than others.

of moisture, can corrode the metallization. Workers are beginning to notice variations in packaging polymer properties due to their curing [77]. An excellent and thorough review and assessment of techniques that have been and could be used to monitor the degree of cure has recently been completed [78]. Many techniques for measuring the electrical, thermal, and mechanical properties have been used. Other techniques include fluorescence, ultraviolet absorption, infrared and Raman spectroscopy, refractive index changes, and microdielectrometry. Fourier transform infrared techniques seem to have been used most recently to assess the degree of completion of the chemical reactions involved in the curing process. But techniques for measuring the physical order of the polymer molecules are also needed to fully specify the degree of cure. Viscosity is a measure of how well a liquid or semiliquid can flow. It is most important in determining how easily polymeric molding compounds can be forced into molds to form a package. The various techniques used are well covered in a recent book [79]. They include spiral flow length, capillary rheometer, and cone and plate. The variation of viscosity with temperature is of particular concern to packaging molders.

16.7 Summary Most of the data in the current literature on the properties of electronic packaging materials were measured on bulk specimens using standardized tests common to semiconductor chip technology or engineering materials technology. Though some new opportunities are apparent, most techniques for measuring the properties on the scale of the features in modern electronic packaging are yet to be developed or need to be assessed to determine limits of accuracy and

Measurements of Properties of Materials in Electronic Packaging

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precision and their applicability to research and development, process control, and quality assessment in manufacturing, in-service diagnostics, and failure analyses. Yet, the evidence to date indicates that at least some fine-scale properties are quite different from bulk properties; further development and assessment appears to be warranted. These techniques may allow studies to determine when the assumption of bulk properties ceases to be valid. The development should be connected with modeling to determine which are the most important parameters to measure and with how much accuracy and precision.

Acknowledgments Credit for identification of the most important measurements in packaging goes to the participants at a NIST workshop [80] held in May 1990. Special thanks go to G. Arjavalingam and W.T. Chen of IBM, R.P. Tye of Ulvac, and C. Lee of the Microelectronics and Computer Technology Corporation for reviewing the manuscript and for discussing the subtleties of various techniques. And special thanks to Ken Kreider of NIST for his review and critique.

References 1. E.S. Meieran, P.A. Flinn, and J.R. Carruthers, Proc. IEEE 75, 908 (1987). 2. L. Kashar, in Electronics Packaging Forum, Vol. 1, edited by J.E. Morris, Van Nostrand Reinhold, New York, 1990 pp. 219-281. 3. M. Ohring, in The Materials Science of Thin Films, Academic Press, New York, 1992, pp. 249-306. 4. R.R. Tummala and E.J. Rymaszewski (eds.), Microelectronics Packaging Handbook Van Nostrand Reinhold, New York, 1989. 5. M.L. Minges (ed.), Electronic Materials Handbook, Vol. 1, Packaging, ASM International, Materials Park, Ohio, 1989. 6. D.P. Seraphim, R.C. Lasky, and C.-Y. Li (eds.), Principles of Electronic Packaqhl.q, Design and Materials Science McGraw-Hill, New York, 1989. 7. M. Pecht (ed.), Handbook of Electronic Packaging Design, Marcel Dekker, New York, 1991. 8. C.A. Harper (ed.), Electronic Packaging and lnterconnection Handbook, McGrawHill, New York, 1991. 9. E.F. Begley and S.J. Dapkunas, J. Mater. Eng. Perf. The Semiconductor Research Corporation (SRC), Research Triangle Park, North Carolina, maintains a database of evaluated properties of materials in electronic and photonic packaging. That database is only available to organizations that are SRC members. 10. Annual Book of A S T M Standards. ASTM, Philadelphia PA (annually updated). 11. Test Methods Manual, IPC-TM-650, Institute for Interconnecting and Packaging Electronic Circuits, Lincolnwood IL (intermittently updated). 12. M. Ohring, in The Materials Science of Thin Films, Academic Press, New York, 1992, pp. 453--455. 13. M. Ohring, in The Materials Science of Thin Films, Academic Press, New York, 1992, pp. 477-480. 14. J.A. Carpenter, Jr., in Microwave Processing of Materials H edited by W.B. Snyder, W.H. Sutton, M.F. Iskander, and D.L. Johnson, Materials Research Society, Pittsburgh PA 1991, pp. 477-487.

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MATERIALS FOR ELECTRONIC PACKAGING

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Measurements of Properties of/Hateria/s in Electronic Packaging 3 5 9

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58. G.V. Blessing, in Dynamic Elastic Modulus Measurements in Materials, edited by A. Wolfenden, ASTM, Philadelphia PA, 1990, pp. 47-57. 59. B. Wong, R.J. Holbrook, C.A. Magerle, and L.E. Medina, in Proc. Int. Symp. Microelectronics, ISHM, Reston VA, 1986, pp. 399-410. 60. I.J. McColm, Ceramic Hardness, Plenum Press, New York, 1990, pp. 178-180. 61. R. Cortez, E.C. Cutiongco, and M.E. Fine, Superconductin9 Sci. Technol. 5, 354-359 (1992). 62. Z. Guo, A.F. Sprecher, D.Y. Jung, and H. Conrad, in Materials Developments in Microelectronics Packaging: Performance and Reliability, edited by P. Singh, ASM International, Materials Park, Ohio, 1991, pp. 806-812. 63. H. Doi, K. Kawano, R. Minamitani, and T. Hatsuda, Superconductin9 Sci. Technol. 5 167-170 (1992). 64. K. L. Mittal (ed.), Adhesion Measurement of Thin Films, Thick Films, and Bulk Coatings, ASTM Special Publication 640, ASTM, Philadelphia PA, 1978. 65. D.B. Knorr, J. Metals 44, 29 (1992). 66. W. Sachse, K. Y. Kim, and H. D. Conway, in Electronic Packagin9 Materials Science IV, edited by P.S. Ho, R. Jaccodine, K. Jackson, E.D. Lillie, and R.C. Sundahl, Materials Research Society, Pittsburgh PA, 1989, pp. 293-303. 67. P.A. Steinmann and H.E. Hintermann, J. Vac. Sci. Technol. 7, 2267 (1989). 68. N.N. Schulz, A. Elshabini-Riad, R.W. Hendricks, in Engineered Materials Handbook, Vol. 4, Ceramics and Glasses, edited by S.J. Schneider, Jr., ASM International, Materials Park, Ohio, 1992, pp. 321-328. 69. H.M. Tong, K.L. Saenger, and L. T. Nguyen, in Microwave Processin9 of Materials II, edited by W.B. Snyder, W.H. Sutton, M.F. Iskander, and D.L. Johnson, Materials Research Society, Pittsburgh PA, 1991, pp. 29-56, 57-94. 70. T.L. Baker and S.W. Freiman, in Electronic Packagin9 Materials Science II, edited by K.A. Jackson, R.C. Pohanka, D.R. Uhlmann, and D.R. Ulrich, Materials Research Society, Pittsburgh PA, 1986, pp. 81-90. 71. D.-Y. Shih, P. Palmateer, Y. Fu, J. Kim, S. Kapur, A. Arnold, B. Ghoshal, P. Brofman, D. Waldman, P. Hayunga, S. Cvikevich, J. Corso, and G. Advocate, in Proc. bTt. Syrup. Microelectronics, ISHM, Reston VA, 1991, pp. 74-81. 72. James W. Rydzak and Roger W. Cannon, J. Am. Ceram. Soc. 72(8) 1559-1561 (1989). 73. S. Ito, T. Nishioka, S. Oizumi, K. Ikemure, and Igarashi, in Materials Developments in Microelectronic Packagin9: Performance and Reliability, edited by P. Singh, ASM International, Materials Park, Ohio, 1991, pp. 190-197. 74. D.D. Denton and H. Pranjoto, J. Metals. 44, 97-105 (1992). 75. K.K. Kanazawa, in Microwave Processing of Materials H, edited by W.B. Snyder, W.H. Sutton, M.F. Iskander, and D.L. Johnson, Materials Research Society, Pittsburgh PA, 1991, pp. 125-138. 76. P.T. Vianco, F.M. Hosking, and D.R. Frear, in New Characterization Techniques for Thin Polymer Films, edited by H.-M. Tong and L.T. Nguyen, Wiley, New York, 1990, pp. 373-380. 77. D. Pietila, L. Debra, J. Guan and C. Lee, Superconductin9 Sci. 5, 289-294 (1992). 78. D. Hunston, W. McDonough, B. Fanconi, F. Mopsik, F. Wang, F. Phelan, M. Chang et al., "Assessment of the State-of-the-Art for Process Monitoring Sensors for Polymer Composites," NISTIR 4514, NIST, Gaithersburg MD, June 1991. 79. L.T. Manzione, in Plastic Packaging of Microelectronic Devices, Van Nostrand Reinhold, New York, 1990, pp. 48-52, 110-16. 80. J.A. Carpenter, Jr., "Measurements of the Properties of Materials in Microelectronics Packaging," unpublished report on workshop held at the National Institute of Standards and Technology, Gaithersburg MD, May 1990. The results are summarized in [35] ~. cMention of these organizations is for information only, and as an endorsement by the National Institute of Standards and Technology.

Index

AC calorimeter, 348-349 Acoustic analyses, 353 Activated acid vapor fluxless soldering process, 86-93; acid vapors, 88-89; contact angle, 91-92; experimental procedure, 87-89; experimental results, 89-93; formic acid vapor concentration, 91-92; process details, 86; reducing agents, 89; soldering chamber, 88; time to wetting, 89-90; wetting experiments, 87; wetting rate, 91 Adherends, 353 Adhesion, 353; measurement of, 267-270 Adhesive bond energy, 269 Adhesives, die attach, 153 Advanced composites: applications, 135139; future directions, 139-142; materials available, 128; unique properties of, 128 A1-A1203 interface, 110 A1N as packaging material, 105, 169, 319 A1N particle filled polyimide siloxane, 151 Alumina substrates, 202-203 Aluminum: compared to copper, 221; infiltrated graphite foam (Gr/A1), 128, 130 Aluminum-matrix composites, 147, 148 Aluminum wire, ultrasonic bonding of, 189, 191 Amber, 304 Anelastic strains, 59, 70 Arrhenius law, 66 Asperity contact model, 120 ASTM Standards, 341 Athermal plastic strain, 59

Au-A1203 interface, 116-119; crack fronts at, 118; crack tip in, 114; fracture energy as function of metal layer thickness, 113 Auger electron spectroscopy (AES), 270, 272, 275 Backboards, 147-149 Barium titanate, 198 BEDT-TTF, 305, 309-10 Bend testing, 275 BeO, 319 Beryllia particle reinforced beryllium, (BEO)p/Be, 128, 130 Binder chemistry, 187 BioRad MRC-500 unit, 294 Bismuth oxide, 187 Bonding and debonding mechanisms, 105 Boron fiber reinforced aluminum (B/A1), 130, 138 Brazes, 5, 149-150 Brazing alloys, tailoring, 55 Buckminsterfullerene, 303 Calorimetry, 350 Capacitance measurement techniques, 350 Capacitors: dielectrics, 197-198; printed, 199; screen-printed, 198; thick film, 196 Carbon/carbon (C/C) composites, 127, 148 Carbon fiber polymer-matrix composites, 149 Carbon fiber reinforced aluminum (C/A1), 130, 132 Carbon fiber reinforced composites, 136 Carbon fiber reinforced copper (C/Cu), 130, 137 361

362

Index

Carbon fiber reinforced epoxy (C/Ep), 130, 140 Ceramic-matrix composites (CMCs), 127, 142 Ceramics, 10; low temperature systems, 24, 25; molding materials, 16; monolithic, 169; packages, 241; substrates, 11, 21, 22. See also Metal-ceramic interfaces CFC- 113, 80 Charge transfer salts, 303, 305 Chemical vapor deposition (CVD), 12, 128, 141; diamond, 321-331 Chip cartier, 10 Chip-to-substrate connections, 165 Chlorofluorocarbons (CFCs), 80 Circuit cartier: first lamination, 18; second lamination, 18 Coefficient of thermal expansion (CTE): ceramic substrates, 16; effect of filler, 155; encapsulants, 33, 199, 282-284; Kovar, 17; material requirements, 128-138, 145, 168, 349; measurement, 351; silicon carbide particle reinforced aluminum, 2627; thick film capacitor, 196 Coffin-Manson relationship, 71 Collision processes, 255-256 Commensurability resonance, 309 Composite materials, 105, 127-143; glassbonded, 187-188; key classes of, 127; low thermal expansion, 145-152; status of, 128-135. See also Advanced composites and under specific types Conductors, 185-194; molecular, 303; organic, 303, 305-312; performance characteristics, 189; performance of soldered and unsoldered, 187; polymermatrix composites, 153-171; polymers, 303, 312-315; powders, properties of, 158; silver bearing, 199; silver fired film surfaces, 188; solder interconnections, 189; solderable, 185-190; surface structure, 189; thick film, resistivities of, 192. See also Copper material system (CMS) Confocal laser microscopy, 297 Connectors, 5 Contact resistance variations (CRVs), 185 Contact resistivity, 154 Copper: blanket-deposited, 223; compared

to aluminum, 221; deposition, 222; dry etching, 223; oxidation, 222; patterning, 222-223, 227; sputtered, MTTF, 221222; stress measurement, 274; technology problems, 222; wet etching, 222. See also Electroless copper; Electroless copper deposition Copper material system (CMS), 191-194 Copper-matrix composites, 148 Copper-solder interface, 97, 98, 100 Crack branching due to residual stress, 115 Crack-opening displacement, 121 Crack propagation in metal-ceramic interfaces, 111 Crack tip: in Au-A1203 interface, 114; in metal-ceramic interfaces, 110 Crack trajectory in metal-ceramic interfaces, 109 Creep, 353 Creep strain, 59 Critical energy release rate, 108 Critical stress intensity, 108 Critical stress intensity factor, 108 Cryopumps, 246 C-shaped springs, 162 Cure: degree of, 355-356; silicone, 285-288 Debye length, 258 Debye shielding, 258 Degree of cure, 355-356 Density, 355 Deuterated formaldehyde (DCOD), 238 Deuterium in electroless copper, 238-239 Dewetting, 50 Diamond, 319-337; area and thickness used, 334-335; background, 319-321; chemical vapor deposition, 321-331; electrical properties, 331; film properties, 326-331; film structure, 326; HPHT process, 320; laser cutting, 332; metallization, 331-332; nucleation and growth, 323-326; package design considerations, 333-335; physical vapor deposition, 321; polycrystalline, 319; powder, 169; structure, 319-320; substrates, 319, 331-332; syntheses, 320321; thermal conductivity, 319, 326-331 Die attach, 5, 14, 30-31,150-151; adhesives, 153; materials, 30-31 Dielectric constant, 23, 194, 197-198, 333, 345

/ndex

Dielectric films: characterization, 291; for high-temperature high-voltage power electronics, 291-302; key properties, 292; microvoids in, 295-297; properties of, 295-300 Dielectric loss, 293, 297, 299, 333, 345 Dielectric strength, 293, 300, 344 Dielectrics, 194-199; applications, 291; characterization and breakdown studies, 292-294; crossover, 194-195; crystallizable glass composition, 195; encapsulant, 198-199; interlayer, 5, 12, 33-34; multilayer, 195-197. See also Copper material system (CMS) Differential scanning calorimetry (DSC), 350 Dilatometry, 349 Direct chip attach module (DCAM), 5-6 Dissipation factor, 345 DMET, 305, 310-311 Dual in-line package (DIP), 14 Ductility measurement, 275 Dynamic mechanical thermal analysis, 353

Elastic strain, 59 Electrical contacts, 5, 153, 154 Electrical properties, 342, 344-346 Electrical vias, 7, 10 Electrically insulating thermally conducting composites, 168-169 Electroless copper: deuterium in, 238-239; electrical properties, 233-235; hydrogen in, 236-239; MTTF, 222; oxidation, 235236 Electroless copper deposition, 223,224-226; alkaline free stock solution, 227; fully planar technique, 232-233; ingredients added to activate stock solution, 228; nanoline processing, 227-233; nonplanar and fully planar line processing procedures, 227; nonplanar technique, 229-230; oxidation-reduction potential (ORP), 228; stock solution, 227 Electromagnetic interference (EMI) shielding, 3, 35, 153, 156, 157, 159, 163, 166 Electron, 304 Electron beam evaporation, 253-254

363

Electron cyclotron resonance (ECR) effect, 322 Electron guns, 253-254 Electron impact ionization, 256 Electron spectroscopy for chemical analysis (ESCA), 270, 272 Electronic packaging: hierarchy of, 3; levels, 3, 128; use of term, 3 Electronic packaging materials: applications, 5; overview, 3-39 Ellipsometry, 274 Encapsulants (and encapsulation), 5, 14-16; advantages and disadvantages, 282; applications, 199; ceramic, 31-33; coefficient of thermal expansion (CTE), 33; dielectrics, 198-199; glass, 198, 199; layer thickness, 199; materials, 282; overview of potential materials, 283; polymer, 31-33; preferred properties, 3133; properties of, 282; purposes of, 281284; test methods, 288-289; thermal expression, 199. See also Silicone-based polymers; Silicone gels Enclosures, 35 Environmental scanning electron microscopy (ESEM), 45, 49, 52, 53, 55 Epoxy resin, 19, 130, 140 Evaporation methods and sources, 251-254; electron beam, 253-254; radiation, 252; RF induction, 252; thermal resistance, 252 Ex situ network composites, 161-162 Fatigue, 353 Fatigue testing, 275 Filler-filler interactions, 286 Filler-matrix bonding, 146 Filler-resin interactions, 286 Firing process, 207-211; airflow arrangement, 208 Flash diffusivity method, 348 Flip-chip, 334 Flux carrier, 79-80 Flux residue, 79-80 Fluxes: action of, 79; applications, 79 Fluxless laser soldering, 81-86; application, 101; experimental procedure, 81-82; experimental results, 82-86; process details, 81; process schematic, 82; working limits, 81

364

Index

Fluxless soldering, 79-103; examples, 101102. See also Activated acid vapor fluxless soldering; Fluxless laser soldering; Laser ablative fluxless soldering (LAFS) Foils, yield strength in, 112-114 Forward recoil emission spectroscopy (FRES), 237-239 Fracture energy: measure of, 108; and metal layer thickness, 113; and microstructure, 106-107; and mode mixity, 120; and plastic dissipation, 111; and yield strength, 110-112 Fracture mechanics, 107-108 Fracture modes in metal-ceramic interfaces, 109 Fracture surface, Nb-A1203 interface, 122 Fracture toughness, 108 Free electrons, 304 Fullerene, 303 Gallium arsenide, 304 GenRad 1689 Precision RLC Digibridge, 293 Glass ceramic multiplier substrate, 26 Glass fiber reinforced polymer (GFRP), 128 Glow discharge, 256-258 Gold conductor-aluminum wire couple, 191 Gold conductors, 190-191; thick films, 190191 Gold-plated microwave carriers, 135 Gold wire: thermocompression bonding, 189, 191; thermosonic bonding, 189, 191 Graphite, 303 Guarded hot plate method, 346-347 Hall-Petch relation, 112 Heat sinks, 5, 16, 147-149; composite materials, 34; material requirements, 3435 Heat transfer, physical vapor deposition (PVD), 263-265 Hermetic sealing of lids, 101 High density interconnect (HDI), 5 Hipotronics AC dielectric test set, model 7100-20A, 293 Housings, 5, 35 Hydrogen in electroless copper, 236-239

In situ networks, 163-164 Integrated circuit package types, 8 Interconnect overlay, 5 Interconnections, 5, 11-12, 14, 27-30, 105, 152, 169; card-to-backplane, 29; card-tocard, 29; chip-to-card, 29; corrosion, 30; electrical, 28; types, 27 Interface analysis, 270-272 Interlayer dielectrics, 5, 12; material property requirements, 33-34 Interpenetrating composites, 163 Interstitial via holes (IVHs), 7

Kapton, 291 Knudsen's cosine law of emission, 250 Kovar, 16, 17, 35, 83, 84, 86, 135, 136

Lambert's law of illumination, 250 Laser ablative fluxless soldering (LAFS), 93-101; experimental procedure, 94-96; experimental results, 96-100; surface mount technology (SMT), 102; wettability test specimens, 94 Laser-based interferometry, 350 Laser soldering. See Fluxless laser soldering; Laser ablative fluxless soldering (LAFS) Laser trimming, 211-220; aperture, 216; average power, 214; diamond, 332; focus, 216; fundamental mode, 213-214; mechanics of, 216; multimode operation, 213; overlap, 216; peak pulse power, 215, 220; process control variables, 218; process variables, 214; pulse frequency, 214, 220; trimming speed, 216 Lead insertion hole, 7 Lead-tin solders. See Pb-Sn solders Leadless chip carriers (LLCCs), 7, 15 Leakage current, 300 Lids, 5, 35; hermetic sealing of, 101 Linear accelerators, 216 Linear elastic fracture mechanics (LEFM), 107 Longitudinal bar method, 346-347 LOPED, 223 Low temperature transient liquid phase (LTTLP) bonding, 30 Low thermal expansion composite materials, 145-152; filler materials, 146

Index

Magic angle effect, 309 Manufacturability properties, 341, 355-356 Marangoni motions, 54 Mass transfer, solderability model, 48-49 Material properties, 341-360 Maximum use temperature, 350 M(dmit)2, 305 MDT-TTF, 305, 311 Mechanical bulge test, 275 Mechanical properties, 343, 352-355 Melt through phenomenon, 50 Melting temperatures, 350 Metal-ceramic interfaces, 105-124; crack propagation in, 111; crack tip in, 110; crack trajectory in, 109; flow distribution, 117; fracture behavior, 105, 107-110; fracture energy, 106; fracture mechanisms, 110; fracture modes in, 109; grain distributions in metal layer, 110115; microstructures, 106-107; mixed mode fracture, 117; pore distribution, 115-119; residual pores, 115-116; residual stress in, 114-115; surface roughness effects, 119-121 Metal layer thickness, and fracture energy, 113 Metal-matrix composites (MMCs), 127, 141 Metal particle filled polymers, 155 Metal substrates, 10, 26 Microindentation, 353 Microstructure and fracture energy, 106107 Mode I loading, 107-108 Mode II loading, 107-108 Mode mixity, 108, 109; and fracture energy, 120 Moir6 interferometry, 350 Moisture absorption, 355 Molecular conductors C60, 314 Montreal Protocol, 80 MOSFETs, 308 Multichip module (MCM) packaging, 3, 12, 16, 21,284 Multichip module laminate (MCML), 6 Multilayer substrates, 10 Nb-A1203 interface, 121-122; fracture surface, 122

365

Neodymium-doped yttrium aluminum gamet (Nd:YAG) laser, 211,332 Nitrogenius soldering machine, 102 Oil diffusion pumps, 246 Organic conductors and superconductors, 303, 305-312 Organic polymers, 304 Oxygen-free high conductivity (OFHC) copper, 94, 96, 99 Ozone layer depletion, 80 Pb-Sn solders: creep at -40~ in eutectic solder, 67-68; creep strain curve, 61-62; data analysis, 58-63; deformation behavior, 58, 59-68; determining damaging strains causing failure, 57-77; effect of anelastic strains on accelerated test results, 70; effect of hold times and temperature on creep strain stored in secondary region, 72-75; envelope strain curve, 61; failure criterion, 71-73; measurement of nonrecoverable strain per cycle, 61-63; operating temperatures in different applications, 64; strain response of load-controlled cycle, 59; strain separation, 59-61; stress response of strain-controlled cycle, 59; test methodology, 58-63; time predictive equation, 70-75 Peel tests, 267-270 Peierls transitions, 307 Percolation threshold, 307 Perfluoroalkoxy (PFA) film, 293, 295-301 Permittivity, 293, 297 Perylene, 305 PES/Ni particle composite, 166 Phthalocyanine, 305 Physical properties, 343, 355 Physical vapor deposition (PVD), 247-251; background, 248; coating distribution and uniformity, 250-251; deposition rate, 249; diamond, 321; evaporation pressure, 248; gas atom mean free path, 248; heat transfer, 263-265; history, 247-248; impingement flux, 249; vacuum levels in evaporation, 248 Pin grid array (PGA), 9 Pin-inserting-type package, 7, 8 Plasma discharge, 256

366

Index

Plastic dissipation and fracture energy, 111 Plated-through holes (PTH), 6, 7, 19 Polyacetylene, 303, 304, 312-313 Polyaniline, 314 Polybenzimidazole (PBI), 292, 293 Polyenes, 304 Polyether sulfone (PES), 160, 163 Polyimide, 19, 291 Polymer-matrix composites (PMCs), 127, 128, 168-169; electrical properties, 164 Polymers: conducting properties, see Conductors; molding material, 15; organic, 304; substrates, 10; viscosity, 164-165 Polyphenylene, 304 Poly p-xylylene (PPX), 292, 293, 295, 297301 Polypyrrole, 304 Polysulfurnitride, 304, 305 Polyvinylene, 312 Popcorn phenomenon, 355 Postmolded packages, 284 Power hybrid packaging, 5 Precursor films, 53; dynamics of, 52-53; in wetting process, 52-53 Printed circuit boards, 5, 16-19; basic ingredients, 20; construction, 7; design and processes, 17; fabrication process, 9; failures, 19; materials, 17; mounting classes and scale of equipment, 4; requirements, 17; specifications, 17 Printing process: print thickness, 206; surface being printed and surface of substrate, 204; terminology, 204-207 Profilometer technique, 275 Pull test, 106 Pyrochlore structure, 179-180 Q-switch, 211, 214 Radiant heating, 252 Radio frequency (RF) induction, 252 Random arrangement, 155 Rayleigh scattering, 348 Residual stress, 353; crack branching due, 115; in metal-ceramic interfaces, 114115; in thin films, 274 Resistance nonlinearity, 190 Resistance stability, 178 Resistivity, 178, 344; and composition, 179

Resistors, 178-185; compositions, 178-18 l; encapsulation, 198; laser trimming, 211220; reliability, 183; resistance value, 180183; special applications, 185; stability, 181, 183; thick films, 178, 181. See also Copper material system (CMS) Roll coater metallization, 265-266 Roll electron beam evaporators, 254 Rosin-based, mildly activated (RMA) flux, 96 Ruthenium compounds, 179-180 Ruthenium dioxide, 180 Rutherford backscattering spectrometry (RBS), 270, 272 Rutile structure, 179-180

Sandwich composites, 149 Scratch test, 267 Screen mesh selection, 206 Screen peel, 205 Screen printing process, 206 Screen wiping, 207 Secondary ion mass spectroscopy (SIMS), 270, 272 Segregated arrangement, 155 Selective electroless copper deposition (SED), 221 Semiconductors, 10, 305 Shockley-Read-Hall (SRH) model, 222 Silicon carbide particle reinforced aluminum ((SiC)p/A1), 130-140 Silicon carbide particles, 128, 129 Silicone-based polymers, 281-290; cure study, 286-288; heat curable, 286-288; heat cured, 285; purification, 286; room temperature vulcanized (RTV), 284-286; RTV formulations, 287. See also Encapsulants Silicone gels, 283-284; chemistry of, 284286; encapsulation, 284; reliability performance, 284 Silver particles, 153 SIM-2030M composite materials, 158 Slug as filler, 164 Solder joints: cyclic stresses in, 57; failure prediction, 57; life prediction, 57, 58; mechanical behavior, 58; reliability, 57; stress, 14. See also Fluxless soldering Solder-matrix composites, 151

Index

Solder-substrate reaction, 50 Solder wetting. See Wetting Solderability, 43-56, 355; control of, 55; evaluation, 54; fundamental problem, 4448; indicators of, 43; microscopic analyses, 43; microscopic mass transfer model, 48-49; restoration, 102; wetting balance test for, 355-356 Soldering: control of, 43; physical metallurgy of, 43 Solders, 5, 149-150; alloy selection and process design, 54-55; behavior of, 43; bump arrays, 165; compositionsolderability process design paradigm, 54 Solvent substitution processes, 81 Specific heat, 350 Spreading angle, 334, 335 Sputtering process, 254-255; bombardment and ejection, 258-259; deposition rate, 262; excitation, 256; glow discharge, 257258; magnetron sputtering, 260-263; recombination, 257; relaxation, 257; yield, 259-260 Steel ball drop test, 106 Stefan-Boltzmann constant, 263 Strain rate, 65; secondary, 62, 63 Stress intensity factor, 107 Stress measurement, copper, 274 Stress relaxation, 353 Stress-strain responses, 352 Substrates, 5, 19-27, 147-149; alumina, 202-203; ceramic materials, 11, 21, 22; diamond, 319, 331-332; materials, 10; multilayer, 10; polymers, 10 Superconducting transition temperature, 308 Superconductors, 303-312 Surface mount technology (SMT), 7, 8, 102, 165 Tape automated bonding (TAB), 241 Tape pull tests, 267 Tape system technology, 197 TCNE, 306 TCNQ, 305 Teflon, 292 Temperature coefficient of resistance (TCR), 178, 180-182, 185 Temperature cycle testing, 288-289

367

Temperature humidity bias (THB) testing, 288 Tensile testing, 275 Test Methods Manual, 341 Tetramethylammonium hydroxide (TMAH), 223 Thermal coefficient of resistance (TCR), 350 Thermal comparator technique, 347 Thermal conductivity, 333; BeO, 25; diamond, 319, 326-331; measurement methods, 346-349; silicon carbide particle reinforced aluminum, 27; substrates, 23; thin films, 347 Thermal diffusivity, 346, 350 Thermal expansion, 14-15; measurement methods, 349; mismatch, 14, 57, 145, 190 Thermal expansion coefficient. See Coefficient of thermal expansion (CTE) Thermal interface materials, 5 Thermal properties, 342, 346-351 Thermal resistance, 346 Thermal vias, 9 Thermal wave techniques, 349 Thermocompression bonding of gold wire, 189, 191 Thermomechanical analyzer (TMA), 349, 350 Thermosonic bonding of gold wire, 189, 191 Thick films, 28, 175-220; gold conductors, 190-191; major components, 177; manufacture flow charts, 177; overview of materials and processes, 175-178; processing, 202-220; production line, 177; resistors, 178, 181; yield strength in, 112114. See also Conductors; Resistors; Vehicles Thin films, 28; multilayers, 12-14; physicochemical submicroscopic phenomena, 52-53; primary, 53; residual stress in, 274; secondary, 53; stress effects, 273-274; thermal conductivities, 347; thermocouples, 348; yield strength in, 112 Three-dimensional interconnection, 5 Three-dimensional networks as fillers, 161164 Tin-silicone, 163 TMTSF, 303, 305, 307-309 Transition metal oxides, 187 TTF, 305

368

/ndex

TTF-TCNQ, 305 Turbopumps, 246 Ultrahigh modulus carbon (graphite) fibers, 128 Ultralarge-scale integration (ULSI), 281 Ultrasonic bonding of aluminum wire, 189, 191 Vacuum chambers, 244 Vacuum deposition, 241,244 Vacuum metallization, 241-277; batch processing, 246-247; coating material properties, 266-267; coating thickness and coverage measurement, 274-275; current applications, 241; evaluation of deposited films, 267; film stress, 273-274; in-line processing, 246-247; interface analysis, 270-272; role processing, 246247 Vacuum pressure, 243-244; base pressure, 244 Vacuum processes, 241-246; effect of residual air and water vapor, 245; gas flow under various pressure regimes, 245; residual gases and leaks, 245 Vacuum pumps, 246 Vapor deposited coatings, adhesion measurement, 267-270

Vehicles, 199-202 Very large-scale integration (VLSI), 221 Via hole, 7 Vias: electrical, 7, 10; thermal, 9 Viscosity, 356 Void growth: far ahead, 118; near crack tip, 118 Wafer-scale integration (WSI), 5 Wettability test specimens, 94 Wetting balance test for solderability, 355356 Wetting experiments, 87 Wetting process, 52-53, 79, 84, 87; schematic geometry, 48 Wetting rate, 91 Wetting time, 89-90 X-ray diffraction technique, 294, 295, 354 X-ray fluorescence (XRF), 274 X-ray photoelectron spectroscopy (XPS), 270 Yield strength: and fracture energy, 110112; in thick films and foils, 112-114; in thin films, 112 Young's equation, 44 z-axis conductors, 165-168