Multi-Mode Multi-Band RF Transceivers for Wireless Communications: Advanced Techniques, Architectures, and Trends

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MULTI-MODE/MULTI-BAND RF TRANSCEIVERS FOR WIRELESS COMMUNICATIONS

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MULTI-MODE/MULTI-BAND RF TRANSCEIVERS FOR WIRELESS COMMUNICATIONS Advanced Techniques, Architectures, and Trends Edited by

Gernot Hueber Robert Bogdan Staszewski

A JOHN WILEY & SONS, INC., PUBLICATION

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C 2011 by John Wiley & Sons, Inc. All rights reserved. Copyright


Published by John Wiley & Sons, Inc., Hoboken, New Jersey. Published simultaneously in Canada. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as permitted under Sections 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, or online at http://www.wiley.com/go/permission. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (317) 572-3993 or fax (317) 572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic formats. For more information about Wiley products, visit our web site at www.wiley.com. Library of Congress Cataloging-in-Publication Data: Multi-mode/multi-band RF transceivers for wireless communications : advanced techniques, architectures, and trends / edited by Gernot Hueber and Robert Bogdan Staszewski. p. cm. Includes bibliographical references and index. ISBN 978-0-470-27711-9 1. Radio–Transmitter-receivers. 2. Wireless communication systems–Equipment and supplies–Design and construction. 3. Cellular telephones–Design and construction. 4. Wireless LANs–Equipment and supplies–Design and construction. I. Hueber, Gernot, 1972– II. Staszewski, Robert Bogdan, 1965– TK6564.3.M85 2011 384.5 3–dc22 2010001881 Printed in Singapore 10 9

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CONTENTS Contributors

xi

Preface

xiii

I

TRANSCEIVER CONCEPTS AND DESIGN

1

1

Software-Defined Radio Front Ends

3

Jan Craninckx

1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8

2

Introduction 3 System-Level Considerations 4 Wideband LO Synthesis 5 Receiver Building Blocks 12 Transmitter Building Blocks 23 Calibration Techniques 25 Full SDR Implementation 27 Conclusions 30 References 30

Software-Defined Transceivers

33

Gio Cafaro and Bob Stengel

2.1 2.2 2.3 2.4

3

Introduction 33 Radio Architectures 34 SDR Building Blocks 34 Example of an SDR Transceiver References 60

54

Adaptive Multi-Mode RF Front-End Circuits

65

Aleksandar Tasic

3.1 Introduction 65 3.2 Adaptive Multi-Mode Low-Power Wireless RF IC Design 66 3.3 Multi-Mode Receiver Concept 68 3.4 Design of a Multi-Mode Adaptive RF Front End

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3.5 Experimental Results for the Image-Reject Down-Converter 76 3.6 Conclusions 80 References 81 4 Precise Delay Alignment Between Amplitude and Phase/ Frequency Modulation Paths in a Digital Polar Transmitter

85

Khurram Waheed and Robert Bogdan Staszewski

4.1 4.2 4.3 4.4

Introduction 85 RF Polar Transmitter in Nanoscale CMOS 87 Amplitude and Phase Modulation 90 Mechanisms to Achieve Subnanosecond Amplitude and Phase Modulation Path Alignments 96 4.5 Precise Alignment of Multi-Rate Direct and Reference Point Data 101 References 109 5 Overview of Front-End RF Passive Integration into SoCs

113

Hooman Darabi

5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8

Introduction 113 The Concept of a Receiver Translational Loop 119 Feedforward Loop Nonideal Effects 122 Feedforward Receiver Circuit Implementations 125 Feedforward Receiver Experimental Results 129 Feedback Notch Filtering for a WCDMA Transmitter 133 Feedback-Based Transmitter Stability Analysis 138 Impacts of Nonidealities in Feedback-Based Transmission 141 5.9 Transmitter Building Blocks 148 5.10 Feedback-Based Transmitter Measurement Results 150 5.11 Conclusions and Discussion 153 Appendix 155 References 156 6 ADCs and DACs for Software-Defined Radio

159

Michiel Steyaert, Pieter Palmers, and Koen Cornelissens

6.1 6.2 6.3 6.4 6.5 6.6 6.7

Introduction 159 ADC and DAC Requirements in Wireless Systems Multi-Standard Transceiver Architectures 162 Evaluating Reconfigurability 165 ADCs for Software-Defined Radio 166 DACs for Software-Defined Radio 172 Conclusions 184 References 184

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II RECEIVER DESIGN

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7 OFDM Transform-Domain Receivers for Multi-Standard Communications

189

Sebastian Hoyos

7.1 7.2 7.3 7.4 7.5 7.6 7.7

Introduction 189 Transform-Domain Receiver Background 190 Transform-Domain Sampling Receiver 191 Digital Baseband Design for the TD Receiver 195 A Comparative Study 204 Simulations 208 Gain–Bandwidth Product Requirement for an Op-Amp in a Charge-Sampling Circuit 211 7.8 Sparsity of (G H G)−1 213 7.9 Applications 214 7.10 Conclusions 215 References 216 8 Discrete-Time Processing of RF Signals

219

Renaldi Winoto and Borivoje Nikoli´c

8.1 8.2 8.3 8.4 8.5 8.6 8.7

Introduction 219 Scaling of an MOS Switch 221 Sampling Mixer 223 Filter Synthesis 226 Noise in Switched-Capacitor Filters 234 Circuit-Design Considerations 237 Perspective and Outlook 242 References 244

9 Oversampled ADC Using VCO-Based Quantizers

247

Matthew Z. Straayer and Michael H. Perrott

9.1 9.2 9.3 9.4 9.5 9.6 10

Introduction 247 VCO-Quantizer Background 248 SNDR Limitations for VCO-Based Quantization 252 VCO Quantizer
 ADC Architecture 257 Prototype
 ADC Example with a VCO Quantizer 265 Conclusions 275 References 276

Reduced External Hardware and Reconfigurable RF Receiver Front Ends for Wireless Mobile Terminals Naveen K. Yanduru

10.1 10.2

Introduction 279 Mobile Terminal Challenges

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10.3 10.4 10.5 10.6 10.7 11

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Research Directions Toward a Multi-Band Receiver 282 Multi-Mode Receiver Principles and RF System Analysis for a W-CDMA Receiver 286 W-CDMA, GSM/GPRS/EDGE Receiver Front End Without an Interstage SAW Filter 292 Highly Integrated GPS Front End for Cellular Applications in 90-nm CMOS 299 RX Front-End Performance Comparison 305 References 305

Digitally Enhanced Alternate Path Linearization of RF Receivers

309

Edward A. Keehr and Ali Hajimiri

11.1 11.2 11.3 11.4 11.5 11.6 11.7

Introduction 309 Adaptive Feedforward Error Cancellation 311 Architectural Concepts 313 Alternate Feedforward Path Block Design Considerations 320 Experimental Design of an Adaptively Linearized UMTS Receiver 331 Experimental Results of an Adaptively Linearized UMTS Receiver 336 Conclusions 341 References 343

III TRANSMITTER TECHNIQUES 12

Linearity and Efficiency Strategies for Next-Generation Wireless Communications

347

349

Lawrence Larson, Peter Asbeck, and Donald Kimball

12.1 12.2 12.3 12.4 12.5 13

Introduction 349 Power Amplifier Function 349 Power Amplifier Efficiency Enhancement 354 Techniques for Linearity Enhancement 362 Conclusions 371 References 372

CMOS RF Power Amplifiers for Mobile Communications Patrick Reynaert

13.1 13.2 13.3

Introduction 377 Challenges 378 Low Supply Voltage

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13.4 13.5 13.6 13.7 13.8

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ix

Average Efficiency, Dynamic Range, and Linearity 381 Polar Modulation 386 Distortion in a Polar-Modulated Power Amplifier 390 Design and Implementation of a Polar-Modulated Power Amplifier 397 Conclusions 408 References 408

Digitally Assisted RF Architectures: Two Illustrative Designs

411

Joel L. Dawson

14.1 Introduction 411 14.2 Cartesian Feedback: The Analog Problem 412 14.3 Digital Assistance for Cartesian Feedback 416 14.4 Multipliers, Squarers, Mixers, and VGAs: The Analog Problem 427 14.5 Digital Assistance for Analog Multipliers 429 14.6 Summary 435 Appendix: Stability Analysis for Cartesian Feedback Systems 436 References 447

IV DIGITAL SIGNAL PROCESSING FOR RF TRANSCEIVERS

451

15

453

RF Impairment Compensation for Future Radio Systems Mikko Valkama

15.1 15.2 15.3 15.4 15.5

16

Introduction and Motivation 453 Typical RF Impairments 454 Impairment Mitigation Principles 469 Case Studies in I /Q Imbalance Compensation Conclusions 487 References 488

480

Techniques for the Analysis of Digital Bang-Bang PLLs

497

Nicola Da Dalt

16.1 16.2 16.3 16.4 16.5 16.6

Introduction 497 Digital Bang-Bang PLL Architecture 498 Analysis of the Nonlinear Dynamics of the BBPLL Analysis of the BBPLL with Markov Chains 503 Linearization of the BBPLL 508 Comparison of Measurements and Models 526 References 531

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Low-Power Spectrum Processors for Cognitive Radios

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Joy Laskar and Kyutae Lim

17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8

Index

Introduction 533 Paradigm Shift from SDR to CR 534 Challenge and Trends in RFIC/System 535 Analog Signal Processing 536 Spectrum Sensing 537 Multi-Resolution Spectrum Sensing 538 MRSS Performance 542 Conclusions 555 References 556 557

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CONTRIBUTORS Peter Asbeck, University of California at San Diego, La Jolla, California Gio Cafaro, Motorola Labs, Plantation, Florida Koen Cornelissens, Katholieke Universiteit Leuven, Leuven, Belgium Jan Craninckx, IMEC, Leuven, Belgium Nicola Da Dalt, Infineon Technologies, Villach, Austria Hooman Darabi, Broadcom Corporation, Irvine, California Joel L. Dawson, Massachusetts Institute of Technology, Cambridge, Massachusetts Ali Hajimiri, California Institute of Technology, Pasadena, California Sebastian Hoyos, Texas A&M University, College Station, Texas Edward A. Keehr, California Institute of Technology, Pasadena, California Donald Kimball, University of California at San Diego, La Jolla, California Lawrence Larson, University of California at San Diego, La Jolla, California Joy Laskar, Georgia Tech, Atlanta, Georgia Kyutae Lim, Georgia Tech, Atlanta, Georgia Borivoje Nikoli´c, University of California, Berkeley, California Pieter Palmers, Katholieke Universiteit Leuven, Leuven, Belgium Michael H. Perrott, Massachusetts Institute of Technology, Cambridge, Massachusetts Patrick Reynaert, Katholieke Universiteit Leuven, Leuven, Belgium Robert Bogdan Staszewski, Texas Instruments, Dallas, Texas; currently at Delft University of Technology, Delft, The Netherlands Bob Stengel, Motorola Labs, Plantation, Florida Michiel Steyaert, Katholieke Universiteit Leuven, Leuven, Belgium Matthew Z. Straayer, Massachusetts Institute of Technology, Cambridge, Massachusetts xi

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CONTRIBUTORS

Alexander Tasic, Qualcomm, San Diego, California Mikko Valkama, Tampere University of Technology, Tampere, Finland Khurram Waheed, Texas Instruments, Dallas, Texas; currently at BitWave Semiconductors, Lowell, Massachusetts Renaldi Winoto, University of California, Berkeley, California Naveen K. Yanduru, Texas Instruments, Dallas, Texas; currently at University of Texas at Dallas, Richardson, Texas

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PREFACE Current and future mobile terminals become increasingly complex because they have to deal with a variety of frequency bands and communication standards. Achieving multi-band/multi-mode functionality is especially challenging for the radio frequency (RF)-transceiver section, due to limitations in terms of frequency-agile RF components that meet the demanding cellular performance criteria at costs that are attractive for mass-market applications. The focus of this volume is on novel transceiver concepts for multi-mode/multi-band cellular systems from the antenna to baseband. One approach is based on the integration of digital signal processing capabilities implemented locally on the RF integrated circuit. The utilization of digital signal processing capabilities is in line with the ongoing trend toward minimum-featuresized RF-CMOS in the cellular market, which makes it extremely attractive in terms of flexibility, power consumption, and costs. Moreover, advances in the field of antennas, RF-front-end modules and novel analog signal processing architectures are covered to give a consolidated outlook on future concepts for cellular radios. This volume summarizes cutting-edge physical-layer technologies for multi-mode wireless RF transceivers, specifically RF, analog, and digital circuits and architectures, anticipating the major trends and needs of the future wireless system developments. Firsthand materials from distinguished researchers and professionals from both academia and industry are collected. Furthermore, this volume offers a comprehensive treatment of the topic, presenting state-of-the-art technologies and insight covering all the essential transceiver building blocks to be used in future multi-mode (third generation and beyond) wireless communication systems. G. Hueber R. B. Staszewski

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PART I Transceiver Concepts and Design

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Software-Defined Radio Front Ends JAN CRANINCKX IMEC, Leuven, Belgium

1.1

INTRODUCTION

The ultimate dream of every software-defined radio (SDR) front-end architect is to deliver a radio-frequency (RF) transceiver that can be reconfigured into every imaginable operating mode, in order to comply with the requirements of all existing and even upcoming communication standards. These include a large range of modes for cellular (2G–2.5G–3G and further), WLAN (802.11a/b/g/n), WPAN (Bluetooth, Zigbee, etc.), broadcasting (DAB, DVB, DMB, etc.), and positioning (GPS, Galileo) functionalities. Obviously, each of them has different center frequency, channel bandwidth, noise levels, interference requirements, transmit spectral mask, and so on. As a consequence, the performances of all building blocks in the transceiver must be reconfigurable over an extremely wide range, requiring ultimate creativity from the SDR designer. Reconfigurability is a requirement for SDR functionality, but often one forgets that it can also be an enabler for low power consumption. Indeed, once flexibility is built into a transceiver, it can be used to adapt the performance of a radio to the actual circumstances instead of those implied by the worst-case situation of the standard. Since linearity, filtering, noise, bandwidth, and so on, can be traded for power consumption in the SDR, a smart controller is able to adapt the radio at runtime to the actual performance required, and hence can reduce the average power consumption of the SDR. In this chapter, several important innovations and concepts are presented that bring this ultimate dream closer to reality. These include circuits for wideband local oscillator (LO) synthesis, multifunctional receiver and transmitter blocks, and novel ADC (analog-to-digital converter) implementations. The result of all this is integrated in the world’s first SDR transceiver covering the frequency range from 174 MHz to 6 GHz, implemented in a 1.2-V 0.13-µm CMOS technology. Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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SOFTWARE-DEFINED RADIO FRONT ENDS

1.2

SYSTEM-LEVEL CONSIDERATIONS

A first choice to be made is the radio architecture to be used. In past decades, lots of studies and examples have been presented on heterodyne, homodyne, low-IF (intermediate frequency), wideband-IF, and other architectures, all having certain benefits and problems for a certain application. Which one to choose? In view of SDR, this question perhaps becomes a little easier to answer. Indeed, when the characteristics of all possible standards are taken into account, not a single intermediate frequency can be found that suits them all. And having multiple IFs and the associated (external) filtering stages increases the hardware cost of the SDR, which cannot be tolerated. So direct-conversion architectures are the right choice for the job. All of the well-known problems, such as dc offsets, I /Q mismatch, 1/ f noise, and power amplifier (PA) pulling, that have limited the proliferation of zero-IF CMOS radios into mainstream products have been better understood in recent years, and it will enable the design of a low-cost front end. A schematic vision of what the final SDR will look like is represented in Fig. 1.1. For a low cost in a large-volume consumer market, the active transceiver core is implemented in a plain CMOS technology. It includes a fully reconfigurable directconversion receiver, transmitter, and two synthesizers [for frequency-domain duplex (FDD) operation]. The functions that cannot be implemented in CMOS are included on the package substrate. These are related primarily to the interface between the active core and the antenna. They must provide high-Q bandpass filtering or even duplexing, impedance-matching circuits, and power amplification. In the remainder of the chapter we focus primarily on the transceiver implementation. The hard works starts with determining performance specifications for each block in the chain. The total budget for gain, noise, linearity, and so on, must be divided

MCM substrate

CMOS IC

MEMS switches

Tunable matching

DMQ

Frac-N PLL

VCO Distr.

Frac-N PLL

Tunable filtering

DMQ

Power amplifier

NoC controller

FIGURE 1.1

Conceptual view of an SDR transceiver front end.

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WIDEBAND LO SYNTHESIS

FIGURE 1.2

5

System-level analysis tool.

over all blocks, ensuring that all possible test cases are covered, and this must be done for every standard. Having very flexible building blocks helps a great deal, of course, but making a smart system analysis at this point is crucial to obtaining an optimal SDR solution. A custom MATLAB tool has been developed to do this exercise [1]. It takes in a netlist that describes all building blocks, with the performance characteristics and gain ranges, and simulates on a behavioral level the complete chain for a list of different test cases. Figure 1.2 shows a screenshot. The performance under all circumstances can thus be evaluated, and the building block performance can be tuned to fulfill all requirements. Gain ranges and signal filtering must be set such that the signal levels are an optimal trade-off between noise and distortion. Although being a difficult exercise, the analysis can show that with the built-in flexibility, a software-defined radio can achieve state-of-the-art performance very close to that of dedicated single-mode solutions. In the next sections we go deeper into the design of some crucial building blocks.

1.3

WIDEBAND LO SYNTHESIS

To generate all required LO signals in the range 0.1 to 6 GHz, several frequencygeneration techniques have been proposed to relax the tuning range specifications of a voltage-controlled oscillator (VCO). They use division, mixing, multiplication,

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SOFTWARE-DEFINED RADIO FRONT ENDS

or a combination of these [2]. However, to make these systems efficient in terms of phase noise and power consumption, the VCO tuning range still has to be maximized. In the following section we discuss the design of such a wideband VCO, and the architecture required to generate all LO signals is discussed in Section 1.3.2. The target frequency band of the VCO is around 4 GHz, so that it does not coincide with any of the major RF frequency bands used. The actual LO frequency will be obtained by further division and mixing. Since the VCO frequency differs from the RF frequency, most direct-conversion problems will be relaxed or avoided. 1.3.1

3 to 5-GHz Voltage-Controlled Oscillator

To reach the stringent phase noise specifications for today’s mobile communication systems, most RF transceiver integrated circuits (ICs) use LC-VCOs. Frequency tuning of LC VCOs is commonly done by changing the capacitance value of the resonant tank using varactors and/or an array of switched capacitors [3]. Switched or controlled inductor designs have been reported [4], but it remains difficult to cover the desired wideband continuously and to limit the deterioration of the phase noise performance caused by the insertion of these switches. Instead of using a single large varactor to tune the frequency, a mixed discrete/ continuous tuning scheme is usually chosen [3]. A small varactor is used for fine continuous tuning, and larger steps are realized by digitally switching capacitors in and out of the resonant tank. This has two advantages: The VCO gain is lower, allowing easier phase-locked loop (PLL) design, and digitally switched varactors have a higher ratio between the capacitance in the on-state (Con ) and the capacitance in the off-state (Coff ). A higher Con /Coff ratio allows a larger VCO frequency tuning range. However, as the tuning range of a VCO is increased and exceeds the typical 20% range obtained in many designs, new problems and trade-offs appear that need a solution. In this design we have tackled the two main problems encountered in wideband LC-VCOs [5]. First, the negative resistance required to maintain oscillation varies a lot over the frequency range, leading to significant overhead when a fixed active core is used. Second, the large variation of the VCO gain (K VCO ) across the entire tuning range creates problems for optimal and stable PLL design. Solutions are proposed for both problems. 1.3.1.1 Tank Loss Variations In the target frequency range (< 5 GHz), the losses in the oscillator tank are usually dominated by the inductor. It can be modeled by an inductor series resistance R S , which in this simple example we consider to be frequency independent. This simplification is, of course, not completely valid, since extra losses due to the skin effect, for examples will increase the resistance at higher frequencies, but that does not change the general conclusion we will make. The negative resistance needed to compensate for the inductor losses is given by G m = R S (ωC)2 , where C is the total tank capacitance and ω is the √ oscillation frequency, which is, of course, given by the simple equation ω = 1/ LC, with L the inductance value [6]. If we want the oscillation frequency to change by a factor of 2, for example, the total capacitance of the resonant tank has to be changed by a factor of 4, and hence the required negative resistance must also change by a factor of

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4. The transconductance required for the active core is four times higher at the lower end of the frequency tuning range than at the higher end. Recent phase noise theory based on the impulse sensitivity function (ISF) theory of phase noise, together with a linear-time-variant circuit analysis [7], has shown that not only the small-signal transconductance must be considered. The VCO phase noise depends on the large-signal oscillation amplitude, and that is proportional to the bias current and the parallel tank resistance, which varies with frequency. In a traditional design, the active core will be designed for the toughest case (i.e., for the lowest frequency). For the highest frequency, the active core is largely overdimensioned, which is obviously a waste of power. Changing the VCO operating point with frequency is beneficial. Another argument to take into account is the tuning range achievable. The key to a wideband VCO is, of course, to have a tank capacitance that consists as much as possible of varactors and as little as possible of parasitics. The smaller the active transistors, the better. Here it is obvious that if we could eliminate some of the parasitics at high frequencies, the tuning range could be extended considerably. The basic idea behind the solution presented here is thus not only to scale the biasing current of the active core, but simultaneously to change the size of the transistors as well, to keep parasitics at a minimum, which is beneficial for both the phase noise performance and the tuning range achievable. Therefore, the active core will be constructed from an array of core units, which can be turned on or off when necessary. In each of these core units, switches must be added to turn the active transistors on or off. The position and size of those switches has to be considered carefully, to avoid degrading the oscillator phase noise performance as well as to ensure that additional parasitic capacitances are small. The circuit diagram is depicted in Fig. 1.3.

0

Dtune

1

Vtune 0

Ckvco

1

Dunit

M3

M4 SW1

M1

FIGURE 1.3

SW2

M2

Wideband VCO architecture.

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As is clear from the analysis above, it is of utmost importance that together with the negative resistance, the parasitic capacitance is removed from the oscillator tank to ensure a large tuning range. In the on-state the switch is closed, and the parasitic capacitance is then determined by the drain–gate and source–gate capacitance of the switch, plus the drain and gate capacitance of the active transistors. This is obviously larger than the parasitics of a simple negative resistance because of the added switch parasitics, but that is not an issue. Indeed, the core units are activated only when the oscillation frequency is lowered, and hence a larger capacitance is tolerated. In the off-state, the active NMOS transistors (M1, M2) keep their gate connected to the LC tank and their parasitic remains. But the active PMOS transistors (M3, M4) are turned off by the positive gate–source voltage, and their gate capacitance drops considerably. Finally, the switch transistors (SW1, SW2) also turn off and only the drain parasitics stay attached to the tank, which results in a large drop is capacitance. This information is, of course, used in the sizing the various transistors. The NMOS is made small (W = 2.6 µm per unit) and the PMOS is approximately three times larger (W = 8.5 µm). The greatest width is given to the transistor that has the largest on/off ratio, so the switch size is set to W = 18 µm. With this structure a Con /Coff ratio close to 3 is obtained, without any significant contribution of the switches’ series resistance to the overall phase noise. So, in fact, we have been able to use the negative resistance core as a varactor. For high oscillation frequency, the capacitance is low and there is no negative resistance. For lower frequencies, more and more core units are gradually activated, and the total bias current increases to keep the oscillation amplitude steady and the parasitic capacitance increases, helping the “normal” varactors in their goal to increase the total tank capacitance. 1.3.1.2 Sensitivity Variations The second problem solved in the design presented is the variation in VCO sensitivity for wide-tuning-range VCOs. A change in the control voltage Vtune results in a change C in the analog varactor capacitance Cvar . This causes a change in frequency  f . The size of this frequency change depends on the relative weight of the analog capacitance change with respect to the total tank capacitance (which consists for a large part of digitally switched varactors): f =

2π

1 √

LC

→

−1 f = √ C 4πC LC

(1.1)

If we go back to the example of the VCO with a frequency ratio of 2, we have seen that the tank capacitance has to change by a factor of 4. As√can be seen from (1.1), the VCO frequency sensitivity will then change by a factor 4 4 = 8. In this example the nonlinearity of the CV curve of the varactor has been neglected, but typically the varactor is used in the middle of its tuning range, where this curve is rather linear. Such a large change in VCO gain presents serious problems for the design of the PLL in which it will be incorporated. It prevents keeping the PLL bandwidth constant and hence endangers the loop stability and an optimal phase noise performance. The solution proposed here is to make the varactor size changeable. Instead of making one big analog varactor, a number of unit analog varactors are used. These

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WIDEBAND LO SYNTHESIS

9

varactors can be controlled in two ways. Some units are used for analog continuous tuning, and their control node is connected to oscillator tuning voltage Vtune . The other units are used for fine-grain discrete tuning, and their control node is connected either to the power supply or to ground. At the lowest frequency the sensitivity is low, so a large analog varactor is needed. Most of the unit varactors will be connected to the analog control voltage. At high frequencies the sensitivity is relatively high and only a small analog varactor is needed. The other units can then be used as a discrete switched varactor, giving extra-fine discrete tuning curves. 1.3.1.3 Circuit Implementation Figure 1.3 shows a simplified view of the complete VCO architecture implemented. The inductor value was chosen small (0.75 nH) and is optimized for a wide tuning range. It has a symmetrical octagonal shape [8] and is implemented in the top metal layer, which has a thickness of 2 µm. The next metal level is used for the underpass connections only. The typical series resistance of the inductor is about 1 . The coarse frequency tuning is done with an array of 31 equal-sized varactors, controlled by the 5-bit control word Dtune . In combination with those varactors, active core units (control word Dunit ) add the necessary negative resistance and also add some extra capacitance when the frequency is lowered. A total of 31 switched core units are employed, in parallel with a fixed negative resistance that has the size of about 10 units. This allows controlling the negative resistance generated by the VCO core over a factor of 4, as was required for a factor of 2 tuning of the oscillation frequency. Correspondingly, the total current of the active core will vary between 2.1 and 8.5 mA, whereas the bias circuit consumes 0.55 mA. An analog varactor consists of 15 small units and is controlled by Ckvco . That digital code actually consists of two control words. Four bits are used to set the number of varactors that must be connected to the analog control voltage Vtune . Fifteen other bits are used to set the varactor control to power (1) or ground (0) in case it is not used for analog control. That creates a large set of extra-fine tuning curves that cover the range between two adjacent coarse-tuning settings. As there are many control bits to set the proper frequency and gain of the VCO, and as the required settings of those bits are partially dependent on process, temperature, and voltage variations, a calibration sequence is needed to identify the correct setting for each desired center frequency. At power-up time, before actual operation, both the frequency and the frequency sensitivity of the VCO must be measured and stored in a look-up table for correct operation. The setting chosen must be such that the VCO gain is kept proportional to the frequency over the entire frequency range, as this keeps the PLL bandwidth constant [5]. Figure 1.4(a) shows a selected set of the measured frequency response of the VCO. Only some of the 32 coarse frequency steps are shown for most of the frequency range, showing a total tuning range from 3.14 to 5.2 GHz, equivalent to 49%. In the upper frequency range, a detail of the fine-tuning steps is also shown. At this high frequency, only 2 of the 15 small varactors are controlled by the analog tuning voltage. The others can be set digitally to 0 or 1, resulting in an extra set of 14 fine-tuning curves. The plot shows that there is sufficient overlap between consecutive curves. In

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(a)

(b) 3.80

Fine Tuning

5.0

4.5 Coarse Tuning

4.0

3.5

3.0

Freq. [GHz]

3.78

Freq. [GHz]

c01

3.76

C(KVCO)

3.74 3.72

0.2

0.4

0.6 0.8 Vtune [V]

1.0

1.2

3.70

0.2

0.4

0.6 Vtune [V]

0.8

1.0

1.2

FIGURE 1.4 VCO measurement results: (a) set of coarse and fine tuning curves selected; (b) VCO gain settings.

the lower-frequency range (not shown), the coarse-tuning curves are closer together because the total capacitance in the tank is higher. But also, more analog varactor units are connected to the tuning voltage, leaving fewer analog units that are digitally controlled and hence fewer fine-tuning curves. Eventually, the entire frequency band can be covered continuously with the desired slope for the oscillator sensitivity. The flexibility of the VCO gain is shown in Fig. 1.4(b). For a fixed coarse frequency setting, the number of analog varactor units is changed, giving different slopes of the frequency curves. The varactors that are not connected to the analog tuning voltage are biased at the power supply; hence all curves overlap at Vtune = 1.2 V. Clearly visible in the graph is the limited linear range of the MOS varactors used in the design. In the PLL the VCO settings are controlled so as only to be used in the most linear range of the tuning voltage, between 0.4 and 0.8 V, where K VCO is almost constant. Measured phase noise at an offset of 1 MHz ranges from −115 to −119 dBc/Hz for the upper and lower frequencies, respectively. This variation can be explained perfectly by the difference in ( f 0 / f )2 [6], indicating indeed that the design is still limited by the limited Q of the inductor and that the use of the switched active core allows us to keep the current consumption optimal over the entire frequency range. The closed-loop integrated phase noise of the complete PLL is typically −36 dBc. These measurements show that the VCO achieves continuous coverage over a very wide frequency range, with a fully controllable K VCO , resulting in a stable and optimal PLL design for the entire tuning voltage range used. 1.3.2

0.1 to 6-GHz Quadrature Generation

As a result of the wideband VCO, the problem of LO carrier generation can be solved in a system that is not too complex and hence does not carry a large power penalty. The block diagram of the divide/multiply and quadrature (DMQ) is presented in Fig. 1.5. The DMQ contains several divide-by-2 blocks. They generate I and Q phases down to a division factor of 32. Each divider consists of two dynamic simplified flip-flops

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DIV2

DIV2

250M

11

DIV2

DIV2

125M

DIV2

BUF

0.5G

1G

4G

2G

WIDEBAND LO SYNTHESIS

4G

PPF 4G:2G

c01

PPF

4G

5G:3G

DIV2 1.5G

FIGURE 1.5

Block diagram of the DMQ circuit.

in feedback. The rail-to-rail operation of the latches ensures a minimal addition of phase noise, very important in cellular standards. The DMQ further employs a single-side band (SSB) mixer. For a VCO at its 4-GHz center frequency, the mixer combines 4GHz or 2 GHz with 1 GHz to obtain 5 GHz or 3 GHz, respectively. The 2- and 1-GHz components are obtained by division of the VCO frequency. The 4-GHz quadrature phases needed for SSB mixer operation in the 5-GHz mode are generated through a polyphase filter (PPF1). This is implemented as a three-stage polyphase filter, with notches at negative frequencies of 3, 4, and 5 GHz. The circuit diagram of the SSB mixer is presented in Fig. 1.6. As both base frequencies used in the SSB mixing are square waves, they contain all odd harmonics. These are also combined in the mixer and will generate unwanted frequency components. To limit these, the 1-GHz (F1) component is first linearized by filtering out the third harmonic of the 1-GHz square wave. This negative frequency is attenuated by 40 dB with a two-stage polyphase filter with notches at −2 and − 4 GHz. The output of this polyphase filter is a current whose four quadrature phases are injected directly into the SSB mixer. With the VCO at its center frequency, the mixer’s switches are driven by either a 2- or 4-GHz rail-to-rail square wave. Cascode transistors below the switches provide a low impedant input for the linearized 1-GHz current. The bias current is provided by current sources at the bottom. Note that both current sources and cascode transistors are common to both the I and Q paths. The output of the mixer (F3) is amplified up to full rail swing with a differential pair followed by a string of inverters, of which the first is biased around its threshold voltage. The SDR’s LO frequency can be selected by a multiplexer integrated in the DMQ. This function is obtained by powering down the unused blocks and placing their outputs in a high-impedance state. In this way, no extra circuits are placed in the signal path.

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Vdd

F3QP

Vdd

F3QN

F3IP

F3IN

F2I F2Q

VC IP

F1I

Vdd

IN QP F1Q

QN

PPF

Gnd

FIGURE 1.6

1.4

SSB mixer circuit diagram.

RECEIVER BUILDING BLOCKS

A key aspect for the receiver RF part is its interference robustness. The blocking requirements for simultaneous multi-mode operation imply the need for tunable narrowband circuits at the antenna interface. Either this function can be provided by a multi-band filtering block [9], in which case the receiver’s input can be a wideband low-noise amplifier, or part of this burden can be taken up in the low-noise amplifier (LNA) design, as shown in the following section.

1.4.1

MEMS-Enabled Dual-Band Low-Noise Amplifier

In this first example the option of using microelectromechanical systems (MEMSs) switches to build a low-loss reconfigurable antenna filter section on a thin-film substrate is explored. This is especially relevant when simultaneously considering the design of the LNA, whose active CMOS part must be co-designed with the MEMS switch and the passive off-chip matching. The circuit schematic of Fig. 1.7 shows how multi-band operation is achieved independent of the inductive emitter degeneration [10]. A single-pole dual-throw (SPDT) MEMS switch is used to connect the LNA to either its 1.8-GHz matching circuit and antenna filter, or to its 5-GHz

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RECEIVER BUILDING BLOCKS

S11 [dB]

c01

0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20

Gain Ctrl

Low-band High-band 0

1

2

3

4

5

6

7

5-6 GHz

1.8 GHz

A

B

13

8

Freq. [GHz]

MEMS SPDT

5-6GHz

Lbond

50 -TL

50 -TL

1.8GHz

Matching Network

Cbp

A

B

CX Input Stage

Switchable Matching Network On board On chip

Single to Diff. Conv.

FIGURE 1.7 CMOS/MEMS co-designed dual-band LNA circuit schematic and inputmatching measurement (inset).

section, which uses just the bonding wire for input matching. To prove this concept with a commercial component, a packaged MEMS switch [11] was mounted on a printed-circuit board (PCB) together with the CMOS die. Performance is affected only slightly, since the loss of the switch, including its package, was measured to be only 0.2 dB. This device has, of course, limited the validation of the proposed MEMS-enabled SDR receiver to only two bands. A mature technology that integrates MEMS switches in an MCM technology [12] will make it feasible to build more complex structures covering a broad range of frequency bands. Optimal implementation of the switchable narrowband impedance matching at the LNA’s input has been obtained by designing the on-chip part of the LNA such that no dedicated on-board matching components are needed in the 5 to 6-GHz band except for a simple series dc decoupling capacitor Cbp . The MEMS switch can be regarded approximately as a short 50- transmission line, so putting the MEMS switch before the LNA chip will not change the chip’s input return loss drastically. For the 1.8-GHz band, a simple matching network made up of one or two passive components can fulfill the matching requirement. The passband is quite narrow, making a simple passive matching network feasible. These components are less lossy at these low frequencies, and the receiver itself is also less noisy at lower frequencies, which assures a good overall noise figure (NF). To maintain good matching conditions in the full implementation, the chip, including pad parasitics and ESD devices, has been designed in combination with the bondwire inductance, on-board components, and board parasitics. The RF bondpad is modeled by a 65-fF parasitic capacitance in series with a 50- resistance. The ESD

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SOFTWARE-DEFINED RADIO FRONT ENDS

diodes are sized 2 × 0.6 µm × 12 µm each and have in total a 60-fF parasitic capacitance. Each bondwire is modeled by a 1.3-nH inductance. PCB traces are modeled as small transmission lines when needed. Surface-mounted components on the board are characterized carefully with dedicated separate deembedding structures. An extra on-chip capacitor C X connecting the gate and source of the input transistor reduces the gate inductance needed for the input matching to a value of 1.3 nH at 5 GHz, which is conveniently implemented as a bonding wire. Otherwise, this inductance can be unrealistically large and the Q-factor of the input resonance network of the LNA would be too high to cover a 1-GHz band. Thanks to the 300-fF capacitance, the gate inductance can be implemented with a single bonding wire. Internally, the LNA has two separate outputs to cover the required frequency range. A resistively loaded output is, of course, small in area and flexible in terms of wide bandwidth but can only provide enough gain at frequencies up to 2.5 GHz, due to the limitation of the 0.13-µm CMOS technology used. Therefore, a second output is added for the 5 to 6-GHz band with an LC-tuned load, and the selection of either one of those is done by proper biasing of the cascode transistors. A resistor in parallel with this inductor lowers its quality factor and hence increases its bandwidth in order to cover the 1-GHz bandwidth. Gain switching is achieved by the current steering technique, when the third common-gate transistor is activated, which bypasses a certain fraction of the signal current to the power supply so as to reduce the gain. Finally, both outputs pass through a multiplexing single-to-differential converter. The input stage is biased at 5.8 mA, and another 3.6 mA is used in the second stage, for an overall gain of 24 dB. As indicated in Fig. 1.7, S11 input matching better than −10 dB is achieved in both bands. The simulated LNA NF is around 2 dB, while the IIP3 value is −5 dBm in the low band and 3 dBm in the high band. 1.4.2

Wideband Low-Noise Amplifiers

Another option to demonstrate the SDR concept is to rely completely on the passives in the antenna interface for RF interference and blocking filtering. This makes the realization of the concept easier, as commercially available (multi-band) filtering blocks can be used in the implementation. Wideband low-noise amplifiers must now be used that cover an RF frequency range as large as possible for optimal flexibility, but on the other hand must still achieve state-of-the-art performance with respect to narrowband LNAs. Covering the full 100 MHz to 6 GHz frequency range is challenging since achieving a low NF at hundreds of megahertz requires large transistors with low 1/ f noise, while moving toward carrier frequencies of a few gigahertz requires fast transistors. Recently, several 90-nm wideband inductor-less feedback LNAs have been reported [13]. However, none of them achieved the performance targeted by a link budget analysis for an SDR-LNA below 500 MHz (for a 1.2-V power supply). LC-matched common-source (CS) LNAs typically cover a bandwidth from 3 to 10 GHz [14]. Extending the bandwidth down to 100 MHz would require prohibitively large inductors and thus chip area.

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RECEIVER BUILDING BLOCKS

15

C OUT Bandgap

IN

FIGURE 1.8

Schematic of a wideband resistive feedback LNA.

In the SDR front end presented, two LNAs are combined to cover the entire frequency range: An inductor-less feedback LNA with a small form factor (Fig. 1.8) covers frequencies from 100 MHz to 2.5 GHz, and a CS LC-matched LNA (Fig. 1.9) covers frequencies from 2.5 to 6 GHz. Only one LNA is powered at a time, to save power and provide filtering over half of the bandwidth. The LNA with resistive feedback is based on the noise-canceling topology presented in [15]. It employs resistive feedback for wideband matching and noise canceling for low NF over a wide band. The resistive feedback design in general has lower gain and a higher noise figure than these of inductively matched narrowband designs, but it offers large savings in area. Moreover, the noise-canceling approach can reduce the NF, although a compromise must be taken with the linearity performance.

OUT VC

IN

Bandgap

c01

FIGURE 1.9

Schematic of a wideband LC-matched LNA.

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SOFTWARE-DEFINED RADIO FRONT ENDS

The simplified circuit topology of the low-band LNA is shown in Fig. 1.8. For power efficiency, both NMOS and PMOS devices are used in the matching/amplifying stage. A digitally controlled bank of resistors allows us to switch from high- to intermediate- and low-gain modes. The biasing is done with a 3-bit programmable current source. This allows us to vary the gain in small steps around the different gain modes and to decreasing the power by half when switching from high- to low-gain mode. Taking into account the required gain and linearity, the maximum bandwidth achievable at the moment in the 0.13-µm CMOS technology is limited. More advanced technology nodes should overcome this issue in the future. At a maximum gain of 22 dB (including the single-ended to differential conversion stage), typical simulation results achieve an NF of 2 dB and an IIP3 of −10 dBm at a power consumption of 12 mW. At reduced gain (10 dB), the linearity improves to +3 dBm while the power consumption decreases to 8 mW. In a high-band LNA (see Fig. 1.9), broad input-matching bandwidth is achieved by taking up the input impedance of an inductively degenerated common-source stage into an LC bandpass filter [14]. Input matching from 6 GHz down to 2.4 GHz can be done with inductive elements of reasonable values, but extending that frequency band to lower values is practically not feasible. Also, the bonding wire and the ESD diodes are taken into account in the matching network. At the output, a 4-bit programmable capacitor bank provides filtering. A pullup resistor is added to obtain good linearity. Gain switching is achieved with a bypass cascode transistor that diverts a part of the signal current to the power supply for lower gain without influencing the input matching. Biasing is done with a 3-bit programmable on-chip voltage reference. Simulated values for NF and IIP3 are 2.4 dB and −10 dBm, respectively, at a maximum gain of 22 dB, with a power consumption of 12 mW. 1.4.3

Wideband Down-Conversion Mixer

As far as the dependence on RF carrier frequency is concerned, the down-conversion mixer poses no specific problems—as long as the correct LO frequency is applied, of course. Some standards do have specific blocking test cases that demand very good linearity, both second and third order, which are not yet targeted in this design. The mixer, shown in Fig. 1.10, consists of a folded double-balanced Gilbert cell driving two current mirrors. The Gilbert cell is intrinsically wideband, as it has a capacitive input impedance and can be driven by a voltage source. Here it is used for wideband operation up to 6 GHz and is the core of the mixer. The current mirrors have a digitally programmable gain B. An NMOS input pair is used as a transconductance, driving RF signal current into the core switch transistors that form the Gilbert cell. The input must be designed carefully, as it will determine both the noise and the linearity performance of the mixer. A rather large overdrive is needed for linearity, which in combination with the required low-noise performance results in a considerable biasing current of 5 mA. Because of the low power supply voltage (1.2 V), a folded topology must be used, which does indeed have some drawbacks. The extra folding transistors will

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RECEIVER BUILDING BLOCKS

17

LORF+

RF-

RF

LO+

B:1 io +

LO+

1:B io-

LO

FIGURE 1.10

Schematic of a wideband down-converter.

contribute a certain amount of thermal noise, causing the overall receiver’s NF to deteriorate. Some RF signal current will be lost in the parasitics at the folding node, lowering the mixer’s conversion gain. The LO switching transistors are thus folded PMOS transistors, which also offers an advantage, as they can reduce the mixer’s flicker noise. This can not be generalized,however; for examples, at even higher frequencies, NMOS transistors may behave better because of their higher switching speeds and smaller parasitics. The noise contributions in a switching mixer are not easy to understand or analyze [16] but can generally be kept within limits by using large LO signals and reduced dc current through the switching transistors. The switchable gain of the mixer is achieved by two flexible current mirrors whose output transistors and current gain B are digitally programmable. Consequently, the mixer is actually a voltage-input and current-output building block. The currentmode output is indeed used to drive the subsequent lowpass channel filter. Too much voltage gain must still be avoided at this point to prevent clipping of the output due to strong interferers, and is only allowed after the first stage of the baseband lowpass filter. 1.4.4

Flexible Baseband Analog Circuits

To accommodate the channel bandwidths for a wide range of standards, the flexible baseband lowpass filter (LPF) should offer cutoff frequencies from a few hundreds of kilohertz to several megahertz. Selectivity scalability could allow us to change the filter order in case weaker interferers are detected or in case the standard selected requires less adjacent channel selectivity. The requirements in terms of noise and linearity for the analog baseband channel processing depend, of course, on the

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SOFTWARE-DEFINED RADIO FRONT ENDS VDD

M5

PMOS

PMOS

PMOS

PMOS

M7

Vbias NMOS

M8

M11 R NMOS

M1

InM bit

OutP

Rc Cc1A Cc1B NMOS

M2

NMOS

NMOS Cc2A Cc2B

Vcm

InP Rc

OutM

M21

M22

NMOS

R M9

M6 M4

NMOS

NMOS

NMOS

NMOS

FIGURE 1.11

M24 NMOS

M3

M23

Switchable Miller op-amp schematic.

decisions taken in the link budget analysis for the entire receiver. In addition to that, an adaptive integrated noise level may lead to a further power saving in case a smaller signal-to-noise ratio (SNR) is required [17]. Adaptive control to provide flexible frequency discrimination and gain control may currently be met with better overall performance by employing proper tunable analog circuits. A possible solution implies the use of modular circuits made of the proper combination of basic units. This allows us to add the desired digital controls efficiently while minimizing layout issues. The concept of component arrays fits perfectly with these needs. An array is defined here as the parallel connection of dynamic analog blocks dimensioned in a binary-scaled fashion and activated whenever needed. A switchable op-amp is shown in Fig. 1.11. It is the basic unit of a flexible op-amp, which is made up of parallel connections of switchable op-amps in a binary-scaled array. Based on the standard Miller compensated architecture, this op-amp is switched on and off through a single bit. In particular, when the op-amp is off, all the PMOS gates are at VDD and all the NMOS gates are grounded by means of MOS switches. Therefore, in the off-mode, the op-amp shows very high output impedance and zero power consumption. The switches that carry signal must be sized carefully, trading off their finite conductance for their nonlinear characteristic. The two Miller capacitors arrays Ccarray are connected at the nodes C1a , C1b , C2a , and C2b , while the node Vcm is connected to the output OutP and OutM by means of two resistors Rcmfb . In these conditions, the poles and the zero still maintain their original position as in a standard Miller op-amp. This flexible op-amp is the basic active component of the biquadratic sections of the channel-select filter. It provides reconfigurable gain–bandwidth product (GBW), dynamic impedance scaling, and power scalability. The sensitivity of the dominant poles to supply voltage, process, and temperature variations can be minimized by employing a proper bias circuit [18]. Also all resistor and capacitors in the filter are implemented as arrays, such that their value can be controlled digitally over a very wide range. The capacitor arrays are

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RECEIVER BUILDING BLOCKS TGATE

Rauch biquad

Bypass TGATE

R21_array

Active-Gm-RC biquad

TGATE

Bypass

C22_array

Active-Gm-RC biquad

Bypass

R1_array Cc1_array

InM

R3_array

+

+ C1_array

+

R22_array

FLOA1

+

C21_array

FLOA2 R22_array

-

+

-

+ OutP

R3_array

Cc1_array R1_array

Cc2_array

C22_array

TGATE

OutM

FLOA 3

C3_array

R21_array

R1_array

Bypass

Cc3_array

R21_array

R1_array

InP

R3_array

Cc2_array

Cc3_array R3_array TGATE

Bypass TGATE

R21_array

Bypass

FIGURE 1.12

Flexible lowpass filter schematic.

the binary-weighted connection of basic units of metal interconnect capacitors. For better linearity performance, the NMOS control switches are always on the virtual ground side where the voltage swing is close to zero. The resistor arrays are built as a binary-weighted connection of polysilicon resistors. The control switches are implemented as straight NMOS-PMOS transmission gates; this solution assures a lower on-resistance and a better linear behavior. Figure 1.12 is a schematic of the flexible baseband lowpass filter (LPF) based on an optimized cascade of active-G m -RC [18] and Rauch biquadratic sections. The combination of this two biquadratic cells is based on power and linearity considerations. Active-G m -RC cells guarantee a very good dynamic range with a limited cost in power. However, linearity in this cell is limited by the “weak” virtual ground of its op-amp. Therefore, the Rauch cell allows us to reach the required linearity for the overall filter. Both biquad topologies include the analog components arrays. This solution provides this baseband block with all the SDR programmability required. The LPF provides the following features: coarse frequency tuning with adaptive power consumption by digitally controlling the resistor values and the number of switchable op-amp units. Fine frequency tuning for RC process deviation compensation is achieved by controlling the capacitor value. One of the power–performance trade-offs we implemented is to reduce the stopband attenuation performance when no large interferers or blockers signals are detected. This is accomplished by turning off and bypassing biquadratic sections. Low on-resistance bypass switches are implemented in each biquad. Furthermore, power consumption can be traded for increased kT /C noise by decreasing the capacitor sizes and the transconductance and increasing the resistor values at the same time. For proper interfacing with the down-conversion mixer, the biquads can also be placed in a current-input mode. Figure 1.13 summarizes the measurements of a stand-alone flexible lowpass filter. For a sixth-order Butterworth selectivity and 85 µVrms of input integrated in-band noise level, the cutoff frequency can be moved from 0.55 MHz to 17.6 MHz with a coarse step of 0.55 MHz, as shown in Fig. 1.13(a). The power consumption decreases

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SOFTWARE-DEFINED RADIO FRONT ENDS

(a)

(b)

10

−10 Amplitude [dB]

−10

Amplitude [dB]

10 0

0

−20 −30 −40

−20 −30 −40 −50 −60

−50

−70

−60

−80

−70

106

107 Frequency [Hz]

(d)

20 18 16

−90

108

IRN=85.37uVrms IRN=125.3uVrms IRN=163uVrms

14 12 10 8 6

106

107 Frequency [Hz]

108

40 20

Output Power [dBVp]

(c) Current Comsumption [mA]

c01

Fundamental 3rdorder

0 −20 −40 −60

4 −80

2 0

0.5

1 1.5 Cut−Off Frequency [Hz]

2

2.5 x 107

−100 −30

−20

−10 0 Input Power [dBVp]

10

20

FIGURE 1.13 Flexible lowpass filter measurements: (a) cutoff frequency; (b) filter order; (c) noise–power trade-offs; (d) third-order intercept point.

linearly with reduced cutoff frequency; for example, the filter consumes 13.2 mW for WLAN 802.11a (11 MHz) and 3.6 mW for UMTS 3.86 (2.11 MHz), showing lower power consumption than that of comparable but less flexible designs [18]. In addition to this coarse frequency tuning, the flexible LPF provides fine frequency tuning by configuring its 7-bit capacitor arrays. By also taking this possibility into account, the effective frequency tuning range is included between 0.35 and 23.5MHz. As shown in Fig. 1.13(b), the transition band of the filter can be traded off for less power consumption in case no large interferers are detected or when less selectivity is required. Second-, fourth-, and sixth-order Butterworth-like selectivity are available by bypassing one or two biquadratic sections. Figure 1.13(c) shows how power consumption can be traded off for noise in case a different standard or relaxed sensitivity requires a lower SNR. By reducing the total capacitor size by a factor of 2 or 4 (and simultaneously increasing the resistor values to keep the filter bandwidth fixed), for examples, the power consumption decreases at the cost of a square-root increase in the total integrated noise level. Figure 1.13(d) shows the IIP3 measurement at the maximum cutoff frequency. The input tones are at 8 and 9 MHz, so that the intermodulation products are well inband. An IIP3 of 10 dBVp confirms the result expected. This linearity performance is nearly constant for all the cutoff frequency settings. This feature makes the proposed

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RECEIVER BUILDING BLOCKS

21

design a very good alternative to the less-linear G m C filters, even for flexible designs. I and Q mismatch measurements were also performed for every cutoff frequency; both amplitude and phase mismatch are well below 0.25 dB and 2.8◦ , respectively. The variable-gain amplifier (VGA) that increases the filtered signal level to an amplitude fit for the dynamic range of the ADC is designed using the same philosophy. It is built from two cascaded inverting amplifiers using resistive feedback. Use of a flexible op-amp makes it possible to save power by adapting the op-amp bandwidth to the signal bandwidth expected. The gain of the VGA can be adapted in 3-dB steps from 0 to 39 dB. The gain switching time is constrained by the fast automatic gain control (AGC) operation and should be lower than 100 ns. In addition to that, the VGA provides different noise levels by changing the resistors arrays by fixed factors. A dc offset compensation loop is added that senses and removes the dc offset at power-up (in closed-loop operation) and holds the steady-state dc offset compensation value during the burst received (open-loop operation). This internal loop can also be deactivated, in which case a mixed-signal dc offset compensation loop is used that measures the dc level in the digital domain and uses a feedback DAC to compensate it at the input of the AGC. 1.4.5

Analog-to-Digital Conversion

The requirements posed on an ADC by the various standards differ widely, of course, depending on the signal bandwidth, the SNR needed, and even more on the amount of channel filtering and amplification of the preceding chain received. In the link budget used here, typically 8 to 10 bits are needed with sampling speeds up to 40 MS/s (two of them should be interleaved to achieve 80-MS/s operation for 802.11n systems). Those specs have long been the territory of pipeline architectures. But in scaled CMOS they become well in range of SAR ADCs. Most SAR ADCs use an operating principle similar to the charge redistribution architecture [19]. This requires fastsettling op-amps in both the input and reference voltages, able to settle their output voltage in a very short time while driving large capacitive loads. Also a high-speed clock for the controller that has to run at 10 times the sampling speed must be available. A new SAR architecture is proposed that uses passive charge sharing (instead of active charge redistribution) to both sample the input signal and to perform binaryscaled feedback during the successive approximation [20]. The basic architecture depicted in Fig. 1.14(a) works completely in the charge domain. The input is sampled on a capacitor and during the SAR algorithm charge is added or subtracted until the result converges to zero. No active circuits are used to add and subtract these charges. Instead, simple passive switches do this. The only active element is the comparator itself, which is the basic principle that allows us to achieve the fundamental lowest limit on power consumption. Operation of the ADC can be explained using the waveforms shown in Fig. 1.14(b). Starting from a reset state, at the start of conversion the input voltage is sampled by the charge on C T , half of which afterward is transferred to C S in a passive chargesharing action. During conversion, the comparator determines the sign of the voltage,

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INp

ST

(b)

SS VTP CTP

Track

VQP M=2N- 1

CSP

4

2

Sample

1

Precharge Comp cp[0] cn[0] cp[1]

CU CTN

CSN

VTN

VQN

INp cn

INn

Track

Sample

Reset

VTp

cp

cp[0..N-2] cn[0..N-2]

Precharge

VQp Comp

CLK Control block

Result

VQn

@FS

B[0..N-1]

FIGURE 1.14

Charge-sharing SAR ADC: (a) basic architecture; (b) sample waveforms.

and the reference charges (which are stored on an array of binary-scaled precharged capacitors CU ) are added or subtracted passively. This charge sharing acts as the reference feedback DAC in the SAR algorithm, but requires no active power nor imposes constraints, on the reference voltage. The capacitor array size is determined by matching constraints, and the comparator offset needs to be calibrated, similar to the circuit proposed in [21]. To avoid the need of a high-speed clock (and its associated power consumption), an asynchronous controller was implemented. Timing of this controller uses a “valid” signal generated by the comparator when its output is ready. The fundamental power limits of the original architecture have been removed by doing all the charge redistribution passively. The input is connected to the tracking capacitor for most of the conversion period, so a fast op-amp is not needed for input sampling. Second, settling problems in the reference voltage are avoided by precharging all capacitors to the same voltage before the conversion process, and this is signal independent. This way, the only remaining active elements, in the ADC are the comparator itself and the digital controller. Another advantage is the completely digital implementation, requiring only MOS switches and MOM capacitors, which makes it portable to new CMOS technologies. The charge-sharing SAR ADC is implemented separately in a 90-nm 1P9M digital CMOS process. At a 50-MS/s conversion rate, the total current consumption is 0.7 mA from a 1-V power supply, divided over the various blocks as follows: digital 50%, comparator 35%, precharging 15%. Measured INL and DNL at 50 MS/s are below 0.6 LSB, as shown in Fig. 1.15(a). Despite this good linearity, the SNDR for low-frequency input signals is only 49 dB (ENOB = 7.8) because it is limited by underestimated comparator noise. At frequencies above 10 MHz, the nonlinearity of the input tracking switch becomes dominant because the low-VT transistors intended to be used were not processed correctly. This causes the ENOB for a near-Nyquist input at 20 MS/s to deteriorate to 7.4, as shown in Fig. 1.15(b). With only 290 µW of power, the resulting FoM is only 65 fJ per conversion step. As none of the ADC

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TRANSMITTER BUILDING BLOCKS

0.6 0.4 0.2 0 −0.2 −0.4 −0.6

(b)

INL [LSB]

(a)

DNL [LSB]

0.6 0.4 0.2 0 −0.2 −0.4

(c)

−256 −192 −128 −64

[dBFS]

23

0 −20 −40

Fs = 20MS/s P = 290µW ENOB = 7.4

SNR = 48.7dB THD = −50.5dB

−60 −80 0 9 ENOB

c01

128 192 256

4M

6M

8M

10M

8 7 6

0 64 code [−]

2M

1k

Fs = 50MS/s P = 725uW 10k

100k 1M Frequency [Hz]

10M

FIGURE 1.15 SAR ADC measurements: (a) INL/DNL; (b) near-Nyquist FFT at 20 MS/s; (c) ENOB vs. input frequency at 50 MS/s.

building blocks consume any static power, the FOM is maintained down to a very low conversion rate, allowing this ADC to be used in a wide variety of applications.

1.5

TRANSMITTER BUILDING BLOCKS

In the architecture presented, a direct-conversion transmitter architecture is used, as this offers the most potential for flexibility. The baseband section uses a programmable filter similar to the receiver filter discussed in Section 1.4.4 to remove the DAC aliases and a wideband direct up-conversion mixer. The pre-power amplifier (PPA) is the final block in the SDR transmit path and is discussed here in more detail. The PPA includes extensive programmability of gain settings. The full circuit consists of four stages and is shown in Fig. 1.16(a). The output stage is an inductively loaded common-source amplifier with programmable bias current for optimal linearity vs. power trade-off. Some care must be taken in the reliability and lifetime of the output transistor, as it is possible that the output signal swings above the power supply and hence violates the reliability ratings of the technology. The use of a thick-oxide transistor, available for 3.3-V I/O compatibility, would solve this problem totally, but the large transistor and its associated parasitics would prevent the circuit from operating at high frequencies. However, in this PPA circuit these problems are much less severe than in, for example, a full-power CMOS PA. The effective output power is not as high, and for many applications the average swing is much lower than the peak. Furthermore, a nonnegligible voltage drop across the series resistance of the inductor sets the dc output voltage below the power supply. The stage preceding the output stage provides gain programmability. Its circuit diagram is presented in Fig. 1.16(b). The core of the amplifier is a common-source stage with a PMOS resistive load. To control the gain, three additional PMOS transistors are placed in parallel with the main load. Their gates can be connected to Vdd , to turn them off and increase the gain, or to ground, to put them in the linear region and decrease the gain. However, changing the resistive load also has an impact on the dc voltage at the output of the amplifier and so, on its linearity. For a high

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(a)

INP OUT

INN

(b)

DCFB

IN

Ref OUT

FIGURE 1.16

Pre-power amplifier: (a) block diagram; (b) variable-gain amplifier stage.

gain, the resistive load is large. The dc output voltage drops, compressing the drive transistor. This effect is reduced by keeping part of the bias current out of the PMOS load. In the stage presented, this is implemented by reusing the resistive load PMOS transistors that are turned off in high gain. Instead, the PMOS load transistors that do not contribute to the resistive load are used as current sources. Their gates are biased at a dc level, which is controlled by a dc level feedback circuit (DCFB). In this way, the high-gain linearity is enhanced without adding extra parasitic capacitances on the signal path. A slight disadvantage of using the PMOS transistors as a current source, rather than turning them off, is that the gain is reduced slightly, due to the limited output impedance of the current sources. Therefore, the possibility is left open to select whether the PMOS is turned off or used as a current source. Another point of attention is the reference level to which the dc output level is controlled. In high-bias-current conditions in combination with high gain, it is not possible to have a high-output dc voltage. The dc level feedback will clip to ground, and the bias PMOS transistors will act as resistors, reducing the gain rather than as current sources. To limit this effect, it is possible to program the target output dc level voltage to some extent. Finally, the total bias current through the amplifier can be controlled to optimize the power consumption for the linearity required. The stage preceding the stage described previously has a similar structure but with extended gain programmability. A cascode transistor has been added to the main amplifier’s path. This is possible, as the signal swing is still relatively small in this stage. In parallel to the main branch, several binary-weighted cascode transistors are

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CALIBRATION TECHNIQUES

25

used to deviate part of the signal current to the supply, resulting in smaller gains. Although this approach may appear suboptimal from a power consumption point of view, the relative current that is lost for the complete PPA is minor, as the amplifier stages are scaled down from the output to the input. The performance of this circuit varies widely, of course, over carrier frequency, required output power, bias and gain settings, and so on. Simulation results indicate a total gain range of 50 dB and typical IM3 distortion levels of −35 dB at 0-dBm output power.

1.6

CALIBRATION TECHNIQUES

In a multi-mode zero-IF transceiver, design specifications normally span a broad range of present and future standards. Evidently, this overloads the design requirements and hampers effective design. An alternative is to design according to realistic design requirements and to calibrate the front end digitally for its eventual imperfections. The goal of calibration is to improve or optimize the performance of a full IC transceiver. In this sense, calibration relaxes the design requirements for multi-mode systems and enables the use of a low-cost architecture while being compliant with a broad range of standards. In the context of multi-mode systems, calibration should be dynamic, efficient, automatic, and implemented in the system. Calibration consists typically of two steps: 1. Characterization. The system imperfections are estimated, often at discrete time instances, namely at system startup, at mode handover, and/or at systemdefined time instances. Most of today’s calibration techniques require us to deactivate the system’s normal operation, which is sometimes not allowed. Fortunately, some alternative techniques exist, allowing the system to remain operational during calibration. 2. Compensation. Once the imperfections of the receiver are characterized, the information obtained is used to optimize its performance. Typically, this is achieved by digital pre- and postcompensation of the baseband time-domain signal. Calibration is one of the keys to enabling the realization of low-cost, highperformance SDR mobile terminals. However, the cost required must also be limited, and fully analog high-frequency calibration techniques are therefore rejected. The only relevant techniques in the SDR context are the digital calibration techniques, which will be discussed briefly. 1.6.1

Quadrature Imbalance

In homodyne receivers the RF signal is directly down-converted to a complex-valued baseband signal, which ideally must have equal amplitude and a phase difference of 90◦ . In a practical implementation, slight mismatches in amplitude and phase result

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SOFTWARE-DEFINED RADIO FRONT ENDS

in quadrature imbalance for both transmitter and receiver chains. This imbalance is generally characterized by its amplitude mismatch  and phase mismatch φ, resulting in a negative frequency rejection (NFR) = 10 log10 ( 2 + tan2 φ). Different quadrature imbalance characterization techniques exist at the receiver side, based mainly on adaptive filtering [22,23]. As these techniques exhibit slow convergence, they are applicable in streaming modes only. An alternative technique is presented in [24], where quadrature imbalance characterization is preformed based on one calibration measurement. This fast convergence builds on the realistic assumption of a smooth channel between the transmitter and receiver systems. The principal drawback of all the receiver characterization techniques mentioned is, however, the need for a quadrature imbalance-free generated transmitter signal and thus an ideal transmitter. A promising technique is presented in [25], where the quadrature imbalance of the transmitter and receiver systems is characterized separately based on a single calibration measurement. This technique might be perfectly suited in the multi-mode context. Realistic values of transmitter and receiver quadrature imbalance range up to 5% and 6◦ for  and φ, respectively. After calibration, the remaining transmitter and receiver quadrature imbalance should be lower than −35 dBc. 1.6.2

DC Offset

In direct-conversion receivers, parasitic coupling between the LO path and the RF path in both directions will cause self-mixing and creation of a dc offset at the baseband signal [26]. This dc offset decreases the effective dynamic signal swing, especially when the signal power received is low, and therefore reduces the gain and linearity performances of the receiver. Using a highpass filter to remove the dc offset from the baseband signal is not always an option; the targeted standards have a dense spectral occupation, and such filters cannot be implemented efficiently. Therefore, another calibration technique should be used. As the dc offset in the receiver path is generated primarily in the mixer, to limit its impact it should also be removed as close as possible to this mixer in the baseband path. Reference [27] suggests an architecture adding a digitally controlled complex compensation dc offset directly after the mixer. Building on a similar architectural approach, several authors [25,28] present characterization algorithms that find the optimal complex compensation dc value while keeping the system operational. Both techniques provide very fast convergence and are thus applicable in multi-mode transceivers. 1.6.3

Impact of LPF Spectral Behavior

Accurate control of the bandwidth of channel-select filters is required to guarantee, for example, sufficient suppression of adjacent channels. The spectral behavior calibration of the LPF can be performed completely at baseband; baseband switches are used to connect (part of) the analog baseband circuitry in between the transceiver’s

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FULL SDR IMPLEMENTATION

27

baseband input and output. In a given configuration, the spectral behavior or transfer function can be characterized by comparing the digital signal before and after propagation through the analog circuit. When using a multi-tone signal with a relatively dense and sufficiently wide spectral content, the cutoff frequency, in-band ripple, and spectral phase relation can easily be characterized.

1.7

FULL SDR IMPLEMENTATION

The complete SDR front end (without ADC) has been implemented in a 1.2-V 0.13-µm CMOS technology [29]. In this section we describe the prototype with dualwideband low-noise amplifiers (the one with a MEMS-enabled dual-band LNA is reported in [30]). Figure 1.17 shows a microphotograph of the SDR front end with highlights on the major circuits. The total die area is 3 × 3.8 mm2 , of which about 7.7 mm2 is taken up by active circuits. To verify receiver behavior over the complete input power range, a receiver budget measurement is shown in Fig. 1.18 for three different channel bandwidths. The SNDR is limited by thermal noise for low input powers. The 1/f noise corner is around 200 kHz, which explains the higher NF for the low-bandwidth mode. Realistic interferer and blocker levels are used, corresponding to a Bluetooth, UMTS, and WLAN scenario, respectively. To accommodate these interferers, the front end will reduce its LNA gain at higher input power levels, sometimes with a resulting small dip in the SNR. At high input powers, distortion is the limit.

PLL

PLL VGA

VCO

RX LPF RX DMQ

LNA

RX Mixer

TX LPF

VCO

TX DMQ

TX Mixer

PPA

FIGURE 1.17 SDR chip microphotograph.

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50

SNDR [dB]

40 30 20 10 BW=500kHz BW=2.2MHz BW=10MHz

0 −10

−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 Input power [dBm]

FIGURE 1.18

RX chain radio budget measurement.

The measured receiver noise figure, gain, and IIP3 as a function of the RF frequency are shown in Fig. 1.19 for a channel bandwidth of 20 MHz. A typical noise figure is around 5 dB up to a 5-GHz carrier frequency, above which the performance degrades, due to insufficient LO signal swing. The input IP3 varies from −8 to −4 dBm over the frequency range. A measured 64QAM OFDM constellation and corresponding output spectrum are presented in Fig. 1.20. They correspond to an EVM of −29.5 dB for an output power of −0.5 dBm at 2.45 GHz. Performance varies, of course, over the carrier frequency and operation point chosen. Power can be saved at the expense of reduced linearity and degraded EVM. Table 1.1 presents a summary of the power consumption and performance of the various SDR circuits for various operating modes.

50

maximal gain (VGA gain 0dB)

5

40 NF (maximal gain)

0

30

-5

-10

-15 0

20

IIP3 (minimal gain)

minimal gain (VGA gain 0dB)

1

2

FIGURE 1.19

3 4 Frequency [GHz]

5

SDR receiver performance.

10

0 6

Gain [dB]

NF [dB10]

10

IIP3 [dBm]

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FULL SDR IMPLEMENTATION -10 -20 -30 -40 -50 -60 -70 -80 2.4

2.45

2.5

FIGURE 1.20 SDR TX constellation and output spectrum at 2.45 GHz (Pout = −0.5 dBm; EVM = −29.5 dB). TABLE 1.1

SDR Performance Overview

Power supply = 1 .2 V Current

(mA)

Receiver

8/12 2 × 5/9/12 2 × 3/4/7 2 × 0.3/10 2 × 1/6 24 16.5 16.5 14.3 6.8

LNA Mixer LO buffer LPF VGA DMQ × 5, /4 @ 4.9 GHz × 3, /4 @ 3.0 GHz × 3, /8 @ 1.5 GHz IQ @ 4 GHz /2 @ 2 GHz Receiver performance ◦

NF (high gain) IIP3◦ (low gain) Gain Freq. range Cutoff freq. Current ◦

4.8 to 8.5 dB −8.2 to −3 dBm 10 to 90 dB 0.1 to 6 GHz 0.35 to 23 MHz 27 to 82 mA

f RF 100 MHz to 6 GHz Channel BW 20 MHz

(min./typ./max.) Transmitter

(mA) 2×4 2.6 to 5.9 25 to 51

LPF Mixer PPA

DMQ(cont.) /4 @ 1 GHz /8 @ 500 MHz /16 @ 250 MHz /32 @ 125 MHz Spur. tones × 3/4 mode

4.8 4.5 4.4 4.4 < −30 dBc

Transmitter perf.

2.45 GHz 4.9 GHz

P1dB OIP3

5.8 dBm 1 dBm 15.5 dBm 12 dBm

Pout (WLAN 64 QAM)

EVM

Ivdd

−0.5 dBm @ 2.45 GHz −3.1 dBm @ 4.9 GHz −6.2 dBm @ 5.24 GHz −0.6 dBm @ 2.45 GHz −2.3 dBm @ 2.45 GHz

−29.5 dB −29.2 dB −30.0 dB −26.5 dB −30.6 dB

51 51 51 36 36

Gain control @ 2.45 GHz

Range

Step

Mixer PPA

20 dB 43 dB

∼ 5 dB < 2 dB

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SOFTWARE-DEFINED RADIO FRONT ENDS

CONCLUSIONS

In this chapter, the basic architecture and implementation concepts of a softwaredefined radio analog front end have been presented. A direct-conversion transceiver with very flexible and reconfigurable building blocks has been analyzed at the system level in order to be able to cover the requirements imposed by a large set of communication standards in cellular, WLAN, WPAN, broadcasting, and positioning applications. An important aspect of every SDR front end is the LO synthesis. Since many RF frequency bands need to be covered, ranging from 174 MHz up to 6 GHz, it is a very complex task to generate all local oscillator signals. A very wideband and flexible VCO has been demonstrated, which in combination with division and multiplication in quadrature makes this feasible. Several innovations in the various building blocks of the receiver and transmitter chain are also needed to achieve full SDR functionality. Some examples include the use of a MEMS switch in the input stage of an LNA, wideband LNAs, an ultraflexible baseband channel select filter, an innovative chargesharing successive approximation ADC, and a programmable power amplifier driver. A versatile RX and TX path with programmability to address the various functional requirements of many different standards can offer an optimal power consumption simultaneously by trading in unnecessary performance at runtime. All these concepts are integrated in the world’s first true SDR transceiver prototype, achieving good performance combined with extensive programmability. Although several other improvements will still be needed, the work presented has already taken an important step toward an energy-efficient multi-mode software-defined radio. Acknowledgments The author would like to thank all the members of the RF design team in the Wireless Research Group in IMEC who have made the SDR project possible: Boris Cˆome, Bj¨orn Debaillie, Vito Giannini, Michael Goffioul, Dries Hauspie, Mark Ingels, Michael Libois, Mingxu Liu, Pierluigi Nuzzo, Charlotte Soens, Geert Van der Plas, Gerd Vandersteen, Joris Van Driessche, and Piet Wambacq. The results on baseband analog circuits have been obtained in cooperation with Andrea Baschirotto, University of Salento, Italy. This research has been carried out in the context of IMEC’s multi-mode multi-media program, which is partly sponsored by Samsung.

REFERENCES 1. M. Goffioul, G. Vandersteen, J. Van Driessche, B. Debaillie, and B. Cˆome, “Ensuring consistency during front-end design using an object-oriented interfacing tool called NETLISP,” in Design Automation Conference, San Francisco, pp. 889–892, July 2006. 2. J. Van Driessche, J. Craninckx, and B. Cˆome, “Analysis and key specifications of a novel frequency synthesizer architecture for multi-standard transceivers,” in IEEE Radio and Wireless Symposium, pp. 481–484, Jan. 2006.

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3. K. Manetakis, D. Jessie, and C. Narathong, “A CMOS VCO with 48% tuning range for modern broadband systems,” in IEEE Custom Integrated Circuits Conference, pp. 265– 268, Oct. 2004. 4. M. Tiebout, “A CMOS fully integrated 1 GHz and 2 GHz dual band VCO with voltage controlled inductor,” in European Solid-State Circuits Conference, pp. 799–802, Sept. 2002. 5. D. Hauspie, E.-C. Park, and J. Craninckx, “Wideband VCO with simultaneous switching of frequency band, active core and varactor size,” IEEE J. Solid-State Circuits, vol. 42, pp. 1472–1480, July 2007. 6. J. Craninckx and M. Steyaert, Wireless CMOS Frequency Synthesizer Design. Dordrecht, The Netherlands: Kluwer Academic, 1998. 7. P. Andreani and A. Fard, “More on the 1/ f 2 phase noise performance of CMOS differential-pair LC-tank oscillators,” IEEE J. Solid-State Circuits, vol. 41, pp. 2703– 2712, Dec. 2006. 8. J. Craninckx and M. Steyaert, “A 1.8 GHz low-phase noise CMOS VCO using optimized hollow inductors,” IEEE J. Solid-State Circuits, vol. 32, pp. 736–744, May 1997. 9. C. Nguyen, “Integrated micromechanical circuits for RF front ends,” in Proc. IEEE European Solid-State Circuits Conference, Montreux, Switzerland, pp. 7–16, Sept. 2006. 10. M. Liu, M. Libois, M. Kuijk, A. Barel, J. Craninckx, and B. Cˆome, “MEMS-enabled dualband 1.8 and 5 − 6 GHz receiver RF front-end,” in IEEE Radio and Wireless Symposium, Jan. 2007. 11. TeraVicta Technologies, TT712-68CSP SPDT7 GHz RF MEMS Switch. http://www.teravicta.com. 12. H. D. L. Santos, G. Fischer, H. Tilmans, and J. van Beek, “RF MEMS for ubiquitous wireless connectivity: II. Application,” IEEE Microwave Mag., vol. 5, pp. 50–65, Dec. 2004. 13. J.-H. Zhan and S. Taylor, “An inductor-less broadband LNA with gain step,” in Proc. IEEE European Solid-State Circuits Conference, Montreux, Switzerland, pp. 344–347, Sept. 2006. 14. A. Bevilacqua and A. M. Niknejad, “An ultrawideband CMOS low-noise amplifier for 3.1–10.6 GHz wireless receivers,” IEEE J. Solid-State Circuits, vol. 39, pp. 2259–2268, Dec. 2004. 15. F. Bruccoleri, E. Klumperink, and B. Nauta, “Wide-band CMOS low-noise amplifier exploiting thermal noise canceling,” IEEE J. Solid-State Circuits, vol. 39, pp. 275–282, Feb. 2004. 16. H. Darabi and A. A. Abidi, “Noise in RF-CMOS mixers: a simple physical model,” IEEE J. Solid-State Circuits, vol. 35, pp. 15–25, Jan. 2000. 17. V. Giannini, J. Craninckx, S. D’Amico, and A. Baschirotto, “Flexible baseband analog circuits for software-defined radio front-ends,” IEEE J. Solid-State Circuits, vol. 42, pp. 1501–1512, July 2007. 18. S. D’Amico, V. Giannini, and A. Baschirotto, “A 4th-order active-Gm -RC reconfigurable (UMTS/WLAN) filter,” IEEE J. Solid-State Circuits, vol. 41, pp. 1630–1637, July 2006. 19. J. McCreary and P. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques: I,” IEEE J. Solid-State Circuits, vol. 10, pp. 371–379, Dec. 1975.

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20. J. Craninckx and G. Van der Plas, “A 65 fJ/conversion-step, 0-50 MS/s 0−0.7 mW 9bit charge sharing SAR ADC in 90nm digital CMOS,” in Technical Digest, IEEE International Solid-State Circuits Conference, San Francisco, pp. 246–247, Feb. 2007. 21. G. Van der Plas, S. Decoutere, and S. Donnay, “A 0.16 pJ/conversion-step 2.5 mW 1.25 GS/s 4b ADC in a 90nm digital CMOS process” in Technical Digest, IEEE International Solid-State Circuits Conference, San Francisco, pp. 566–567, Feb. 2006. 22. A. Schuchert, R. Hasholzner, and P. Antoine, “A novel IQ imbalance compensation scheme for the reception of OFDM signals,” IEEE Trans. Consumer Electron., vol. 47, pp. 313– 318, Aug. 2001. 23. M. Valkama, M. Renfors, and V. Koivunen, “Advanced methods for I/Q imbalance compensation in communication receivers,” IEEE Trans. Signal Process., vol. 49, pp. 2335–2344, Sept. 2001. 24. J. Tubbax, B. Cˆome, L. Van der Perre, S. Donnay, M. Engels, H. De Man, and M. Moonen, “Compensation of IQ imbalance and phase noise in OFDM systems,” IEEE Trans. Wireless Commun., vol. 4, pp. 872–877, May 2005. 25. B. Debaillie, P. Van Wesemael, and J. Craninckx, “Calibration method for RF imperfections enabling low-cost SDR,” IEEE International Conference on Communications, Beijing, pp. 4899–4903, May 2008. 26. B. Razavi, RF Microelectronics. Upper Saddle River, NJ: Prentice Hall, 1998. 27. D. Haspeshgh, J. Ceuterick, L. Kiss, J. Wenin, A. Vanwelsenaers, and C. Enel-Rehel, “BBTRX: a baseband transceiver for a zero IF GSM hand portable station,” in IEEE Custom Integrated Circuits Conference, May 1992. 28. B. Cˆome, D. Hauspie, G. Albasini, S. Brebels, W. De Raedt, W. Diels, W. Eberle, H. Minami, J. Ryckaert, J. Tubbax, and S. Donnay, “Single-package direct-conversion receiver for 802.11a wireless LAN enhanced with fast converging digital compensation techniques,” in IEEE MTT-S International Microwave Symposium Digest, pp. 555–558, June 2004. 29. M. Ingels, C. Soens, J. Craninckx, V. Giannini, T. Kim, B. Debaillie, M. Libois, M. Goffioul, and J. Van Driessche, “A CMOS 100 MHz to 6 GHz software defined radio analog front-end with integrated pre-power amplifier,” in Proc. IEEE European Solid-State Circuits Conference, Munich, Germany, pp. 436–436, Sept. 2007. 30. J. Craninckx, M. Liu, D. Hauspie, V. Giannini, T. Kim, J. Lee, M. Libois, B. Debaillie, C. Soens, M. Ingels, A. Baschirotto, J. Van Driessche, L. Van der Perre, and P. Vanbekbergen, “A fully reconfigurable software-defined radio transceiver in 0.13 µm CMOS” in Technical Digest, IEEE International Solid-State Circuits Conference, San Francisco, pp. 346–347, Feb. 2007.

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Software-Defined Transceivers GIO CAFARO and BOB STENGEL Motorola Labs, Plantation, Florida

2.1

INTRODUCTION

We begin this chapter by defining software-defined radio (SDR) and cognitive radio (CR). The radio spectrum has historically been managed via centralized planning and the allocation of static licenses. This command-and-control approach effectively addresses the problem of mutual interference with the unfortunate by-product of spectrum underutilization. This is supported by spectrum measurements which indicate that at any given time, a large fraction of the available spectrum is unused [1]. Cognitive radio promises improvements in spectral access and utilization by enabling radios to take advantage of spectral opportunities in the spatial, temporal, and frequency domains and to adapt rapidly to the dynamic conditions. The potential of this technology has been recognized and acknowledged by regulatory agencies such as the U.S. Federal Communications Commission. Frequency-agile and waveform-flexible radio-frequency (RF) hardware is needed to make cognitive radio a reality. A software-defined radio is one capable of operating over a broad continuous frequency range, regardless of modulation type and channel bandwidth, where the hardware is reconfigurable via software. Most cellular telephones on the market today are multi-band and multi-mode. However, since they only cover specific predefined frequency bands and modulations, they are not considered SDR implementations. Continuous operation regardless of modulation is clear enough, but how do we define broad? As an example, we can say that 50 MHz to 6 GHz would cover many standards, including TV white space, public safety, cellular, and wireless-local area network (LAN) applications. Many military communications occur below 50 MHz, and future standards will certainly utilize spectrum above 6 GHz, but the purpose is to put the challenge in perspective. A broad operating range in terms of channel bandwidths means covering narrowband FM public safety systems with 25-kHz channels as well as the 20-MHz channels of broadband wireless protocols such as 3GPP long-term evolution (LTE). Those operating ranges represent a significant challenge to hardware designers attempting to implement a radio within the size and power dissipation constraints Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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of a portable device. The particular radio architecture will determine how those challenges are addressed. A review of possible architectures is presented below so that we can analyze performance trade-offs and determine which are best suited for SDR applications. We conclude with an example SDR transceiver that exemplifies the choices that we made. 2.2

RADIO ARCHITECTURES

The ideal SDR architecture would be an analog-to-digital converter (ADC) coupled directly to an antenna [2]. Large chunks of the RF spectrum of interest could be sampled so that digital signal processing could separate out unwanted signals, extract the signal of interest, and perform such functions as automatic gain control (AGC) and demodulation. Such an ADC would require a sampling rate, dynamic range, and signal-to-noise ratio (SNR) to cover existing and future standards with varying performance requirements. One study of existing standards concludes that the ADC would need to sample at 230 MS/s with 14-bit resolution and maximum jitter of 1 ps [3]. Performance in each of these categories can be increased at the cost of higher power dissipation. The figure-of-merit calculations presented in [4] estimate that such a converter would consume 47 W. These requirements are well beyond state-of-theart ADCs today, especially considering the power dissipation limitations of portable devices. Furthermore, this topology would require tunable RF bandpass filters. There are, however, other radio architectures that are practical today and can achieve the frequency-agile reconfigurable characteristics required for SDR transceivers. In the rest of this chapter we explore the building blocks of such transceivers and present an implementation example. 2.3 2.3.1

SDR BUILDING BLOCKS Receivers

Receiver architectures can be broadly categorized in three groups: heterodyne, direct conversion (also called zero-IF), and sampling receivers. Although there are many variations within each group, such as single or dual conversion, we can focus on these main classes to explore the challenges related to SDR implementation. We start by looking at how they handle two problems that every receiver must address: signal selection and dynamic range [5]. Signal selection refers to the process of capturing a slice of bandwidth while rejecting adjacent frequencies, which sometimes contain signals of higher power than the signal of interest. The dynamic range is defined by the maximum and minimum signal levels that the receiver can process without distortion that would degrade the SNR to an unacceptable level. Heterodyne receivers convert an RF signal, ωRF , into an intermediate frequency, ωIF , by mixing the RF signal with a local oscillator (LO) signal, ωLO . The resulting IF frequency is passed through high-Q bandpass filters. The filtering process removes undesired signals such as the image frequency and potential interfering signals. This

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relaxes the requirements of the ADC by limiting the dynamic range of the signal at its input. The down-conversion process for high-side injection (ωLO > ωRF ) produces an intermediate frequency, ωIF , given by ωIF = ωLO − ωRF

(2.1)

ωIF = A1 cos(ωLO t)A2 cos(ωRF t) =

A1 A2 [cos(ωLO − ωRF )t + cos(ωLO + ωRF )t] 2

(2.2)

where the image frequency is ωimage = ωLO + ωRF

(2.3)

Heterodyne receivers require preselect and image reject filters to isolate the desired RF signal and convert it into a usable baseband signal. This IF approach works well for systems with defined channel bandwidths. But large banks of fixed filters would be required to cover the broad range of possible channel bandwidths encountered in SDR applications. This is not a practical solution, due to space constraints and the losses that would be incurred in switching between the many filters. One possible solution to the variable-bandwidth problem is that of switched capacitor circuits in a sampling receiver [6]. In this implementation, the bandwidth is programmable by varying the capacitor ratio and the clock frequency of the switched capacitor circuit. Although this example is used to process the 200-kHz channel bandwidth of GSM, the 450-MS/s sampling rate of the filter could process much higher bandwidths. Another way to handle varying channel bandwidths is with the use of directconversion receivers. The motivation behind the development of direct-conversion receivers was primarily to reduce the number of discrete component (off-chip) parts. The direct-conversion process mixes a complex LO signal, ωLO , at the same frequency as the desired RF signal, ωRF , thereby down-converting the RF signal directly to baseband. In this case, the mixing process is given by ωLO = ωRF = ω A1 cos(ωLO t)A2 cos(ωRF t) =

A1 A2 [1 + cos(2ωt)] 2

(2.4) (2.5)

Since no image frequency is produced in the quadrature down-conversion mixing process, RF preselect filters can be eliminated. Furthermore, the removal of adjacent channel energy no longer requires high-Q bandpass filters but can be accomplished with lowpass filters, which are much easier to integrate. This is a great advantage because it is possible to integrate lowpass filters with programmable gain and bandwidth in today’s technology [7]. Although direct conversion receivers have many desirable properties, they also present several challenges, including dc offsets and 1/f noise. Dc offsets are caused

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primarily by transistor mismatch in the differential paths and/or by LO signal energy coupling into the RF mixer port. The undesired effect is saturation of the following dc-coupled gain stages. One way to alleviate dc offsets is to ac-couple the mixer. This approach works for waveforms without signal energy at dc, but other cancellation techniques are required for waveforms, such as GMSK [8]. One approach is to perform a calibration procedure whereby the dc level is measured at the baseband output and then corrected by providing a feedback loop into one of the baseband gain stages. Since dc offsets can result from second-order nonlinearities, they can be mitigated by providing sufficient linearity in the mixers. Other prevention techniques include judicious choice of frequency synthesizer topology and LO planning along with proper on-chip isolation techniques and careful device matching. Flicker or 1/f noise is the dominant source of noise in MOS transistors at frequencies below 100 kHz. In most CMOS processes, PMOS devices have between two and five times less 1/f noise than do NMOS devices [9–12]. Where this is true, PMOS devices should be used in parts of the circuit where reducing 1/f noise is critical. Noise has a cumulative effect in a gain lineup, so the gain in the first stage should be as large as possible. In addition to these preventive measures, chopper stabilization can greatly reduce the effects of any remaining 1/f noise. This technique is covered in more detail in the SDR transceiver example presented at the end of the chapter. 2.3.2

Direct Launch Transmitters

I

dBm level

Transmitter architectures can take on a number of configurations similar to those used in receivers. In a direct launch transmitter the modulation or encoding signal is generated with Cartesian baseband signals and then frequency-translated to the carrier with a time-switching or frequency-domain multiplication function (see Fig. 2.1). A baseband digital process provides complex samples of the encoding intended, including encryption, pulse shaping, and linearization preconditioning. These discrete samples are lowpass-filtered and amplified by the post-baseband (PBB) amplifier to provide a quadrature signal set into the double-balanced mixer. A quadrature local oscillator signal is applied to each frequency translation mixer to generate a carrier

Base Band digital processing & Digital-to-Analog converter

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Amp LPF 0° Differential Quadrature LO

RF Power Amp

Occupied Signal Bandwith Far Out Noise Level dBc/Hz

90°

Q

Amp LPF

Carrier Frequency Frequency

FIGURE 2.1

Block diagram of direct launch transmitter and transmitter signal spectrum.

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signal that includes the baseband amplitude encoding. These amplitude-encoded quadrature signals can be summed at the mixer outputs as shown in Fig. 2.1 or amplified separately and then summed. The summed signal is a complex carrier signal encoding with both amplitude and phase encoding that is not required to be symmetric about the center frequency of its bandwidth. The frequency-domain encoded carrier is then amplified and delivered to the antenna for electromagnetic transmission to remote locations. The benefit of this direct-launch Cartesian encoded carrier is multi-mode compatibility with baseband frequency bandwidth and mask determination. This enables additional digital processing technology to be applied through the entire transmitter, such as feedforward or predistortion linearization. The encoding can be reconfigured for any form of amplitude, angle, frequency, or any combination of modulation formats and bandwidths with no exceptions, including complex noncontinuous multi-channel signals. The encoding ability of a directlaunch system is limited only by a baseband network’s ability to represent the intended signal in both the bandwidth and spurious free dynamic range. There are three main issues that are specific to direct-launch architectures: sideband noise level, local oscillator feedthrough, and self-generated interference (remodulation of the carrier signal). An ideal transmitter signal would have a thermal-level noise across all frequencies except the ideal encoded carrier-occupied bandwidth. In practice, the sideband noise is introduced when circuit noise is increased in level by the broadband gain in the transmitter system. This begins with the signal-to-noise ratio from the oscillator source. Additional baseband processing noise is summed in through the Cartesian frequency multiplier, resulting in a signal-to-noise ratio at the transmitter amplifier input. For constant-amplitude modulation formats such as those used in GSM, the encoding can be applied directly on the oscillator signal, thereby eliminating the baseband processing and Cartesian frequency multiplier functions and their associated far-out noise contributions. This has lead to the search for lownoise-frequency multiplication implementations, such as a CMOS transmission gate ring switching network (see Fig. 2.17). These rail-to-rail signal processing CMOS transmission gate switches with no dc current have a noise advantage over bipolar or active CMOS frequency-translation implementations. Intelligent design of the transmission gate ring switching mixer can also improve the second main direct launch transmitter issue: carrier feedthrough. This is where signal encoding is used to reduce the intended amplitude of the transmitted signal by 30 dB or more from the peak transmitter level. Without careful design the unmodulated local oscillator coupling to the mixer output can be close to or higher then the intended encoded transmission signal. With careful design of the mixer, carrier feedthrough of better than −50 dBc is attainable [48]. This is important in direct-sequence spread-spectrum systems where the near–far problem is solved with a transmitter power control range of 80 dB. It is very difficult to obtain 80 dB of input-to-output amplitude isolation from one function block, such as the mixer in a direct-launch transmitter. So the 80 dB of isolation is achieved by distributing the power control range across more than one block within the transmitter system. This can be accomplished with a programmable RF attenuator after the mixer or a RF power amplifier with programmable gain or attenuation. Of course, there is some design

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I Base Band digital processing & Digital-to-Analog converter

c02

Amp LPF 0°

Carrier VCO

+

Differential Quadrature LO

Input Referenced Added Noise

Q

FIGURE 2.2

Noise Figure contributes to Input Referenced Added Noise

Amp LPF

90°

RF Power Amp Gain = G Transmission Gate Switching Mixers

Far-out noise contribution associated with a direct-launch block diagram.

challenge to provide 80 dB of transmitter power control with optimized efficiency and linear reproduction of the desired encoded signal over the entire 80-dB power range. This transmitter far-out sideband noise can become an interference signal to receivers in close proximity to the transmission signal (Fig. 2.2). For transmitters designed to operate within a given mode, such as GSM, a bandpass filter is often used to reduce the far-out noise significantly outside the GSM transmitter frequency bands. Similar to the receiver, the lack of broadband tunable RF bandpass filters results in far-out noise over a very wide range of frequencies. This increases the probability of the far-out noise offending a receiver in close proximity. In addition to the potential victim receiver being in close proximity to an all-band transmitter, it would be in a threshold signal reception location within a communications system with signal-tonoise limited design, such as narrowband public safety. Public safety systems are an example of a wide-area coverage system where a single base station is intended to provide communications over a 50-km radius from the base location. Threshold signal reception can occur at the fringe of the 50-m radius, where the path loss of the base transmitter signal is reduced to a minimum signal-to-noise ratio suitable for detection. There are many communications systems, such as cellular organized systems, that are no longer designed with signal-to-noise coverage. Instead, these communications systems are designed with signal-to-interference limited coverage range. Cellular base stations are placed with a density to handle the volume of users. The expectation in cellular systems is much higher communications traffic compared with that of public safety systems. The result is cellular base equipment designed to provide communications over a radius much smaller than that of a public safety system. Adjacent cellular base equipment is organized with channels that are optimized in frequency separation to reduce mobile reception interference. For a mobile receiver at the fringe of a cellular system coverage area, the intended base station signal is

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FIGURE 2.3 Transmitter far-out noise interfering with the close frequency and physical proximity of victim receivers.

usually well above the signal-to-noise reception limit. However, at this fringe the mobile is subject to competitive-level potential interference signals from adjacent cellular base stations. Figure 2.3 shows a 1-W transmitter with a −160-dBc/Hz (−130-dBm/Hz) far-out noise level. Narrowband public safety receivers in close frequency and physical proximity (4 m) might have a −120-dBm/10kHz interferer competing with an intended −121-dBm threshold signal. Given the first responder density expected at the scene of an emergency event, this 4-m range is not unrealistic. Future SDR communications systems with multiple transmissions in close proximity would have uncorrelated noise that would sum at each victim receiver, making the interference issue worse. Perhaps the solution is a combination of increased signal-to-noise performance at the signal source and communications systems with threshold extension below the potential interference noise level. Direct-launch transmitters have an output frequency equal to that of the oscillator signal source frequency. These signal source oscillators are typically implemented as a voltage-controlled frequency source (VCO) within a phase-locked loop (PLL) control network. The PLL control bandwidth is usually lower than the encoding bandwidth of the signal desired, so as to reduce the signal synthesis spurious component levels. In addition, the VCO is a circuit with a high-impedance resonant frequency-determining network that is subject to electromagnetic interference signals at the same frequency. The interference causes perturbations in the VCO that are not corrected by the PLL control loop. This undesirable remodulation of the VCO signal frequency will degrade the quality of the signal transmitted (Fig. 2.4). Besides shielding and grounding, two main methods are used to overcome this remodulation: decreased VCO sensitivity to electromagnetic signals and the use of subharmonic, higher harmonic, or translated reference signal frequency. There are a number of elements associated with decreased VCO sensitivity needed to provide enough rejection to electromagnetic interference. These include lowering the inductive and capacitive coupling coefficient of the VCO resonant network, use of differential VCO, and integrated implementation with a lower coupling area profile. These are combined with multiple layers of isolation shielding between the antenna and the VCO to form a remodulation rejection system. Such a system will prevent electromagnetic energy from coupling into the frequency-determining node

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SOFTWARE-DEFINED TRANSCEIVERS Transmitter radiated signal coupled input VCO signal source

Base Band digital processing & Digital-to-Analog converter

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I

Amp LPF

Antenna Network 0°

Carrier VCO

Differential Quadrature LO

RF Power Amp

90°

Q

Amp LPF

DC supply and ground conducted into VCO signal source network Electromagnetic Shielding

FIGURE 2.4 source.

Transmitter remodulation from a conducted or radiated carrier into a signal

of the VCO. Any undesired coupling from the antenna can change the VCO phase, frequency, or amplitude and appear as an unintended modulation on the VCO output. Moving the VCO operation to a subharmonic frequency of the electromagnetic signal frequency at the transmitter antenna helps to protect the VCO from remodulation. Another alternative is to operate the VCO at a second or fourth harmonic and then divide down to provide a quadrature signal source to the mixer. Although an integer frequency-related VCO signal source is less sensitive to subharmonic or higher harmonic electromagnetic energy, it is not 100% effective. Although it does add complexity, an interim translation frequency is an effective means of eliminating the VCO sensitivity to the antenna’s radiated signal. A third transmitter architecture eliminates remodulation by increasing the PLL loop bandwidth to include the signal modulation radiated. An offset VCO and frequency-translation mixer are added to the PLL synthesizer to increase the phase detector frequency, thereby reducing the control signal lowpass filtering requirements shown in Fig. 2.5. This increased PLL control bandwidth mitigates the interference signal impact on the VCO and prevents the undesirable increase in the modulation bandwidth that would otherwise occur. An alternative direct-launch architecture that does not have a VCO operating at the transmitter output frequency uses direct digital signal synthesis (DDS). DDS is covered in more detail in Section 2.2.4, but briefly stated, a high-frequency clocking signal is used to generate an output signal source without the use of an oscillator operating at the output frequency. DDS can be an all-band signal source for SDR, assuming that it is technically practical for up to 6-GHz operation with acceptable power dissipation. Direct-launch transmitter architecture provides any encoding format for a complete SDR application signal set. This can be implemented as a Cartesian or polar baseband signal processing encoder (Fig. 2.6). A Cartesian format provides baseband

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SDR BUILDING BLOCKS

90° Ft or 2*Ft

carrier VCO very wideband LPF

0°

Quad Generator

control Phase Frequency Detector

Reference

Fr Fr

control

Narrow band LPF Synthesizer

Ft or 2*Ft Offset VCO F = Ft or 2*Ft +/– Ft

FIGURE 2.5 width.

Frequency-translation block diagram to increase the VCO control loop band-

90°

QuadPhase - Q

v(t)

v(t)

Q Magnitude = A(t) = [|2(t) + Q2(t)]1/2 Phase = θ(t) = arctan[Q(t)/|(t)]

Q A(t) θ(t) 180°

InPhase - l

Cartesian

Polar

v(t) = |(t) Cos (ω(t)) + j Q(t) Sin (ω(t))

FIGURE 2.6

0° –90°

v(t) = A(t) e – j (ω(t) + θ(t))

Cartesian and polar signal processing representations.

signal processing in both in-phase and quadrature signals at half the bandwidth of the encoded modulated carrier signal. Each of the Cartesian baseband signal processing formats can be implemented with identical networks that should have correlated processing effects, such as latency delay. Polar processing at baseband is a transformation of the Cartesian format into magnitude and phase. The advantage of polar processing is direct phase encoding on the signal source and the potential of an efficiency enhancement implementation in the amplitude modulation. However, there are at least two issues associated with polar encoding signal processing. First, the bandwidth associated with the magnitude and phase signals are multiples of the Cartesian equivalent signals. Second, the magnitude and phase terms are very different, which causes divergent signal processing effects, including potential time alignment imperfections. These bandwidth and time alignment effects require additional complexity and consideration for each mode of operation.

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Overcoming the issues associated with direct-launch architectures provides an opportunity to develop a solution that reduces the complex requirements to a simple and routine implementation. Direct modulation provides an SDR platform that is reconfigurable to existing as well as future encoding formats. The ability to respond in a timely manner to what–if scenarios will facilitate the introduction of new wireless communications technology. 2.3.3

RF Power Amplification

The topic of power amplification for SDR is best divided along applications of portable battery-operated and fixed-base station equipment. Portable equipment is below 4 W of peak power from a 3.6- to 9-V dc battery power source. Fixed-base station equipment is above 10 W of peak power with a 110-V ac power source. There is a third vehicle mobile class of RF power amplifiers with a 10-W or higher power level from a 12-V dc power source and a unique set of SDR issues as well. In this section we focus on portable RF power amplification issues with simultaneous challenges of size, cost, power dissipation, broadband, and multi-mode performance. A first approach to an SDR solution for the RF power amplifier function is based on the multi-mode and broadband requirements that would lead to a bank of specific RF power amplifier solutions versus a tuned, more complex set of solutions that would span multiple bands or modes of operation. Early multi-mode or multi-band products on the market utilized single solutions where the implementation could be optimized for power dissipation within the portable low battery voltage and physically limited space environment. As the number of modes and bands increases, the size, cost, and performance of a bank of single solutions will become prohibitive without technology advancement in the passive frequency-determining elements needed for matching at each port of the power transfer gain stages within the transmitter system. The migration from single solutions could take the interim step of combining bands to expand the RF power amplifier across applications with an acceptable compromise of optimized single-solution performance. Multi-mode operation would be divided between time-domain duplex (TDD) or frequency-domain duplex (FDD). The TDD switches between transmitter and receiver operation modes, where only one is active at any given time (Fig. 2.7). This reduces the potential interaction between the two functions while increasing the FTX -to-FRX transit operation of a common transmitter/receiver local oscillator signal source. The FDD has simultaneous transmitter and receiver operation at different frequencies, shown in Fig. 2.8. This reduces the signal source FTX to FRX transit complexity while increasing the potential transmitter and receiver interaction. Another incremental step would use programmable frequency-matching or device- operating conditions to expand the band or mode of application associated with a common RF power amplifier implementation. One issue has limited use in the past of programmable elements with a power amplifier implementation. Unlike a receiver, the RF signal levels associated with power amplifiers (especially in the final output stage) can reach levels greater than

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Amp LPF

Amp LPF

0° VCO FTx

Differential Quadrature LO

0°

Multiplexer

I

Amp LPF

Amp LPF

Differential Quadrature LO

90° Amp LPF

Q

TDD multiplexer transceiver block diagram where FTX can equal FRX .

Amp LPF

VCO FTx

VCO FRx

90°

0°

Q

Differential Quadrature LO

FTx = FRx

Amp LPF

FIGURE 2.7

Low Noise Amp

RF Power Amp

90°

Q

I

Base Band digital processing & Analog-to-Digital converter

I

I

0° Low Noise Amp

RF Power Amp Duplexer

FTx = FRx

Differential Quadrature LO

VCO FRx

90° Amp LPF

Q

Base Band digital processing & Analog-to-Digital converter

Base Band digital processing & Digital-to-Analog converter

SDR BUILDING BLOCKS

Base Band digital processing & Digital-to-Analog converter

c02

FIGURE 2.8 FDD transceiver block diagram where the simultaneous transmitter carrier FTX is not equal to the receiver local oscillator FRX .

the dc voltage source used for program control. For example, a varactor is a twoterminal variable capacitance that is defined by the average or dc voltage across the two terminals. When a small RF signal is added to the terminals, the varactor capacitance is still determined by the larger dc voltage. However, if the RF signal voltage is greater than that of the dc control range of the varactor, its capacitance is a function of the RF signal in combination with the dc control voltage. The capacitance is a function of the RF signal and is no longer constant at all times. This can result in modulation of the programmable element’s impedance value and distortion in the RF signals. Special care is needed to provide programmable solutions suitable for RF power amplifier implementations. A single RF power amplifier solution is the ultimate goal for SDR application. This would be an RF power amplifier with continuous operation across all frequencies and optimized power dissipation at every multi-mode format across all operating power levels. In addition, it would provide acceptable linear performance and harmonic content for any mode or band of operation. If we begin the search for this ultimate RF power amplifier solution with a closer examination of each requirement, it could lead to a common SDR RF power amplifier solution. A recent review of broadband power amplifier technologies yielded only two solutions that begin to meet SDR requirements: gain blocks cascaded with wideband

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matching networks and vector-distributed multi-section gain stages in a vector signal combining network configuration. As the bandwidth approaches two orders of magnitude, 100 MHz to 6 GHz, a cascade of wide bandwidth-matching network gain stages becomes a complex design. Programmable elements could become part of the solution to provide a design that would compete successfully with a band of multi-mode or band-optimized performance solutions. However, a vector combined distributed implementation (distributed amplifier) can provide wideband performance with a modest increase in complexity. A brief description of a distributed power amplifier is given here, with more detail provided in the appendix. A distributed power amplifier begins with the final power device divided into a number of smaller devices with a total composite power density equal to that of the original single device. Each of the smaller device outputs is connected in a series arrangement with an inductor or transmission-line element having a value determined to model a transmission line. This is known as a traveling-wave or distributed network. A similar traveling-wave network is implemented on the inputs of the smaller device sections, resulting in a common input terminal for the composite device sections and a common output terminal [13,14]. These terminals will have a bandwidth response equal to the series inductance and shunt capacitance of the device sections represented by a model similar to a broadband transmission line (Fig. 2.9). The output travelingwave network can be implemented with a tapered characteristic impedance to provide an efficient peak power similar to conventional single-stage class A, B, or AB RF power amplifiers [15]. Given a broadband RF power amplifier with efficient peak power operation and acceptable linear performance, the remaining issues are sideband noise level and harmonic content. Outside the frequency selectivity of the cascade gain stage matching network or the distributed traveling-wave passband, the far-out sideband noise will be equal to the thermal noise of the resistive antenna load impedance. Inside the passband frequency, the far-out noise will be the RF power amplifier added input noise, n a , plus the input signal noise floor, n i , plus any VCO output noise, n vco and n f (Fig. 2.10), times the gain of the power amplifier. If the noise added by the RF power amplifier is close to the level of the input VCO signal noise, neither dominates

Cds

Cds Lo

V1(t)

Cds Lo

V2(t)

Cgs

Lo V4(t)

L Cgs

RL i (t)

V3(t)

L

L/2

Cds

L Cgs

L/2 Cgs

Ri

Ri

FIGURE 2.9

Distributed amplifier schematic with input/output traveling-wave networks.

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VCO Far Out Noise nvco

RF Power Amp Input Added Noise na

RF Power Amp Gain = Gt

VCO FTx

nf VCO 1/f Noise

FIGURE 2.10

45

s0 n0

Gt . STx Gt (nvco + nf + na + ni)

ni RF Power Amp Termination Noise

RF power amplifier output signal-to-noise ratio.

and the output noise will be the composite of the two input noise signals times the gain of the RF power amplifier. The gain is the voltage or power gain, G t , of the RF power amplifier, assuming that the small-signal gain is equivalent to the large-signal gain. For narrowband public safety communications, the far-out noise specification is −150 dBc/Hz at 1 MHz of offset. GSM has a tighter specification of −162 dBc/Hz at 20 MHz of offset. To put this dBc noise level into perspective for a 1-W carrier signal level, −162 dBc/Hz of noise would have a power of −132 dBm. This is 42 dB above the 50- thermal noise level of −174 dBm. For an RF power amplifier with n a and n vco equal to zero, n i times G t results in an n o of −132 dBm/Hz, with a maximum RF power amplifier broadband gain of 42 dB. An RF power amplifier with a noise figure greater than zero or an added input noise n a greater than the thermal resistive input termination n i , will decrease the maximum gain for a conventional series-connected set of gain stages. This would result in the RF power amplifier output signal-to-noise ratio (dBc/Hz) having a smaller magnitude than the input signal-to-noise ratio. However, there is literature indicating that distributed amplifiers have an improved output signal-to-noise ratio as a result of vector summing of uncorrelated noise to a correlated signal [16]. Harmonic level is a bit more complex for a broadband RF power amplifier since the harmonics of the lower bands are within the operating range of a broadband distributed amplification. For example, a 100-MHz to 6-GHz broadband RF power amplifier operating at 500 MHz would have the second through twelfth harmonics within the broadband amplifier operating frequency range. This could be improved with the use of differential RF power amplification, which would ideally eliminate all of the even-order harmonic terms. Assuming that the RF power amplifier was operating with a square-wave output with no even-order terms, the harmonic levels would have a worst-case value equal to Vout = cos ωt − 13 cos ωt + 15 cos ωt − 17 cos ωt + · · ·

(2.6)

This results in a third harmonic component that is only 10 dB below the fundamental signal level. The choices for reduction of this in-band harmonic content are a programmable lowpass filter, a frequency-selective output network (including

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SOFTWARE-DEFINED TRANSCEIVERS

antenna response), or a frequency-selective vector combing. Each of these frequencyselective solutions have alternative implementations, with the ideal being software programmable and independent of frequency. There are additional RF distributed power amplifier references with vector-combined frequency-selective networks for harmonic rejection [17]. There are a number of special topics associated with RF power amplifiers that are of interest for SDR applications: efficiency enhancement over a wide amplitude range, linearization extension into the amplitude compression operation, and stability under stressed source and output terminal conditions. Although there are many more special RF power amplifier topics, these three are covered in this section with emphasis on SDR applications. The vector-summed distributed amplifier will continue to be the example used to demonstrate potential solutions for SDR applications. 2.3.3.1 Transmitter Efficiency Battery life is an important performance metric for portable products and can be a marketing product differentiator. Although there are many schemes for extending peak output power efficiency to low output power levels, most of them are frequency-domain dependent. However, supply modulation is one technique that is carrier frequency independent with a number of variations that can be applied effectively to a distributed amplifier implementation. The peak output power of a linear class B amplifier occurs ideally when the peak output voltage is equal to that of the dc supply voltage, and defined with the following relation for sinusoid signal processing: η=

π Vout π Pout = = = 0.785 Pin 4Vdc 4

(2.7)

The output power efficiency is a function of the output signal voltage level. So a modulation format with a peak-to-average ratio of 3 dB would have an efficiency reduction by a factor of 2. Since the RF power amplifier consumes a significant portion of the battery’s power, operating at any output power with the peak efficiency is a worthy goal. This can be accomplished by modulating the dc supply voltage as a function of the encoded output power magnitude to provide peak operating efficiency at all power levels. Any phase encoding on the carrier signal is synchronized with the amplitude encoding at the RF power amplifier output, and the dc supply modulation is accomplished with an efficient dc-to-dc implementation. A linear voltage regulator is not an efficient dc-to-dc converter. There are a number of supply modulation variations, such as envelope following [18], envelope elimination and restoration, and polar modulation format. All are frequency independent and can be applied to a distributed amplifier. 2.3.3.2 Transmitter Linearization The signal quality of any amplifier is a measure of the output reproduction compared to the input signal desired. There are a number of signal quality measurements and methods to identify impairments introduced by the transmitter signal processing system. Two popular measurements are error vector magnitude (EVM) and adjacent channel power ratio (ACPR). EVM is a comparison

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of the modulated input signal to the demodulated signal associated with the encoded transmitter in a Cartesian format. The error is a measure of the decoded symbol location relative to the input symbol location on a Cartesian chart. This error can be expressed in magnitude from the ideal point, phase offset from the ideal point, or a combination of both. In addition, the error must be processed using a population of random symbols and condensed into statistical terms such as peak and standard deviation. The EVM is a measure of the encoded signal quality and is specified within the standard of each of the various modulation formats. ACPR is a measure of the unintended generation of electromagnetic energy from the transmitter network into frequency bands adjacent to the intended operating frequency band. This unintended adjacent channel energy can become interference to receivers in close proximity operating on or near the adjacent frequency band. A transmitter frequency-domain mask is defined by standards bodies and agreed upon by industry equipment manufacturers to limit transmitter adjacent channel interference signal level. The source of the unwanted adjacent channel energy is nonlinear distortion products within the RF power amplifier. It begins with any amplifier input-to-output signal processing defined using the relation vout (t) = a0 V0 + a1 vin (t) + a2 [vin (t)]2 + a3 [vin (t)]3 + · · ·

(2.8)

where ax is the forward transfer coefficient and can be complex, vin (t) is the input time-domain signal, and vout (t) is the composite output time-domain signal. To help understand the mechanism that generates the signal energy outside the desired frequency band, the time-domain input signal is represented as two equal-amplitude tones with a frequency offset within the intended operation bandwidth: vin (t) = A (cos ω1 t + cos ω2 t)

(2.9)

Multi-tone input signals where both tones are within the intended operating bandwidth can be processed with a plus or minus frequency shift equal to the multi-tone frequency offset by the higher-order odd nonlinear functions: a3 [vin (t)]3 = a3 [A (cos ω1 t + cos ω2 t)]3

(2.10)

After the use of trigonometric identities, the third-order distortion terms of interest are equal to a3 A3 43 [cos(2ω1 − ω2 )t + cos(2ω2 − ω1 )t]

(2.11)

This odd-order nonlinear signal process is also referred to as intermodulation distortion and defined with an extrapolated measurement called an intermodulation intercept point (IPx), where x is the odd-order nonlinear transfer term associated with the distortion product relative to the intended output signal. For a modulated signal the existence of multiple tones is a transient event over the occupied bandwidth of the intended signal. The nonlinear generated signals will have the same bandwidth as the

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TABLE 2.1

Linearization Technology Comparison with Respect to SDR

Linearization Technology

Advantages

Disadvantages

Device selection

Simplest

Limited improvement (≈15 dB) High implementation cost

Feedback

35-dB improvement Not dependent on carrier frequency

Narrowband, <1 MHz Instability potential Dependent on output termination

Feed/forward

35-dB improvement Not dependent on carrier frequency Wide bandwidth, < 100 MHz

Efficiency performance Complexity

Predistortion

Reduced hardware Table-based comp value? Wide bandwidth, <10 MHz

Limited improvement (≈15 dB)

intended signal on both sides of the intended carrier. The specific nonlinear transfer function from the intended signal to new frequencies is complex and dependent on the intended signal properties, making this a difficult property to measure. There are two primary methods of reducing nonlinear distortion products: operating the RF power amplifier with an input signal level farther below saturation and the use of linearization techniques. Reducing the output power reduces the ACPR at the expense of RF power amplifier efficiency, which is not always a practical solution. Linearization adds complexity to the amplifier to compensate or cancel generation of the distortion components. Linearization technology has four main approaches: power amplifier device selection and operation with improved distortion performance, feedback compensation, feedforward compensation, and predistortion. These linearization technology advantages and disadvantages are shown in Table 2.1. The best linearization technology for SDR applications may be a combination of device operating conditions and predistortion. This is based on the fact that predistortion is flexible and frequency independent. Furthermore, SDR-based applications are expected to need only small amounts of linearization compensation compared to the 35 dB needed for TETRA narrowband digital modulation. Predistortion has a number of implementations with increasing complexity and effectiveness that can be scaled for a specific application. For continuous-frequency SDR applications, a flexible digital solution is preferred over a fixed hardware linearization solution. 2.3.3.3 Transmitter Stability When a circuit becomes unstable, it produces output signals at frequencies not represented within the input signal. The most common form of unstable behavior in a circuit is positive feedback, where the output is coupled to the input at a level higher than the original input signal. An oscillator is an example of a disciplined unstable positive-feedback condition at a specific frequency. Unintended

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feedback can occur in conducted paths such as dc supply, bias, or control terminals or in radiated paths such as magnetic or capacitive proximity-associated components. As the bandwidth of operation increases, these unintended feedback paths become more difficult to avoid. The best place to begin stability analysis of a power amplifier device is its small-signal parameters, such as scattering or s-parameters. These are frequencydomain voltage measurements at the terminals of the device under loaded (usually 50 ) conditions at a defined operating condition. When an RF power amplifier is working, the operating condition is changing as a function of the input signal level. Therefore, the s-parameters are time-varying functions, making complete stability analysis more difficult to define. However, at a given frequency and operating condition, the s-parameters can be used to determine the stability conditions of a device candidate for an RF power amplifier application. This stability potential is usually dominated by the reverse transfer s-parameter term S12 . As S12 approaches zero, the device becomes unilateral with independent input and output interaction. With the input S11 and output S22 s-parameter magnitudes less than 1 and S12 equal to zero, the device becomes unconditionally stable under any positive real load termination condition. Neutralization, in this context, is the elimination of the reverse feedback output to input path. It is difficult to realize a broadband, neutralized RF power amplifier with a single-ended implementation. However, a differential broadband neutralized RF power amplifier has been described in the literature [19]. SDR RF power amplifier implementations begin with optimized specific solutions for each of the active applications within the industry. For example, a multi-band cellular phone will have separate optimized power amplifier solutions for each band. As SDR applications approach continuous frequency coverage, RF power amplifier implementation will progress down two paths: cascade gain stages with programmable frequency-domain component values and fixed-broadband networks using vector combined signal processing elements. As passive component technology progresses along with device technology, the idea of broadband RF power amplifier for SDR applications will emerge. Until then, higher-cost broadband RF power amplifier implementations will serve as a platform for future proof-of-concept testing and rapid prototyping. 2.3.4

Broadband LO Generation

Perhaps the greatest challenge for software-defined radios is the generation of local oscillator signals over broad, continuous frequency ranges. Given that direct conversion is the receiver topology of choice, quadrature generation must be part of the solution. This is an area that requires innovation to achieve SDR performance. 2.3.4.1 Phase-Locked Loops Phase-locked loops (PLLs) are the most common implementations of frequency synthesizers. A voltage-controlled oscillator (VCO) is phase-locked to a stable reference frequency (typically, a crystal oscillator) through a feedback path by comparing the VCO output to the reference signal and then producing an analog control voltage proportional to the phase difference between

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them. There are a variety of VCO architectures. Ring oscillators have found applications in some wireless LAN standards [20] and broadband TV tuner applications. However, the LC-tuned oscillator is most commonly used in applications with stringent phase noise requirements. As on-chip inductor quality improves, an increasing number of applications have been able to fully integrate PLL-based synthesizers (except for a crystal reference). In addition to the benefits of integration into CMOS processes, they typically exhibit very good performance in terms of phase noise, current drain, area, and spurious performance. The greatest challenge for PLLs is making them tunable over a broad frequency range. Tuning ranges of 20% are typical but can be as high as 30% [21]. Recent results suggest that ranges approaching 50% are possible [22]. Even a 50% tuning range is not enough for SDR applications, so additional techniques must be employed. There are a multitude of approaches for extending the frequency range of PLL systems. The brute-force approach is to have multiple VCOs [23–27], which in most cases can share the same PLL circuitry. But for SDR applications requiring continuous coverage over a wide range, the size of the integrated inductors places a practical limit on the number of VCOs and therefore the achievable frequency range. Whether on- or off-chip, cost and manufacturing issues prevent the use of huge banks of VCOs to cover SDR tuning ranges. Another way to get a broad tuning range is to have one or more VCOs and some combination of multipliers [28,29], dividers [30], or mixers [31]. Inevitably, the addition of these circuits comes at the cost of higher power consumption for equivalent noise and spurious performance. 2.3.4.2 Direct Digital Synthesis Direct digital synthesizers (DDSs) represent a fundamentally different means of frequency synthesis. They have a broad frequency tuning range, fine frequency resolution, and very fast switching times. First reported in 1971 [32], traditional DDSs typically consist of a phase accumulator, an ROM look-up table, a DAC, and an LPF (Fig. 2.11). A frequency control word, K , and reference clock, Fref , are supplied to the n-bit accumulator. At each rising edge of Fref , the accumulator will increment by K and the new value, K j , will select an address in the ROM look-up table. The DAC converts the digital output from the ROM into an analog value that is the instantaneous amplitude of the sine wave. Since the DAC output has finite resolution, its output must be smoothed by the LPF to create the final sine-wave output, Fout , which is given by Fout =

K Fref 2n

(2.12)

The main drawback to this architecture is that the ROM consumes a large amount of power and usually represents the frequency-limiting component in the system. From (2.12) we see that the frequency resolution of the system is set by the accumulator bit width, n. By using only the m MSBs of the accumulator to address the ROM, the system can maintain good frequency resolution and mitigate the power and speed penalties imposed by the ROM. Although ROM-less architectures have been developed [30,33] to reduce power consumption, the improvements have not been dramatic enough to make them viable in commercial battery-operated devices.

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t

Fout

DAC Output

ROM Output

SDR BUILDING BLOCKS

Acc. Output

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t

t

t

Acc. Output

ACC n

ROM

m

ROM Output

DAC

DAC Output

LPF

Fout

K

Fref

FIGURE 2.11

Traditional direct digital synthesizer architecture.

Another promising approach to reducing DDS power consumption is the use of a digital-to-time converter (DTC) to construct an output frequency from the phase information in the accumulator. Referring to Fig. 2.12, the accumulator will increment by K until its capacity (2n ) is reached and an overflow is generated. The average frequency of the overflow will be equal to the output frequency stated in (2.12). However, each overflow pulse must be phase-adjusted to provide a jitter-free output signal. The phase adjustment performed in the DTC is determined by

=

K ov 2π K

(2.13)

where K ov is the accumulator contents after an overflow occurs. Acc. Output

Digital-to-Time Converter ACC n

m

Fout

Tap Selection Logic

K Tap0 Tap1 Tap2

Fref

TapX-1 TapX

Tapped Delay Line Tap0 TapX

FIGURE 2.12

Phase Detector

Charge Pump

vtune

LPF

DTC-based direct digital synthesizer architecture.

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The tapped delay line within the DTC in Fig. 2.12 accepts the reference signal, Fref , and produces multiple copies of the signal that are offset in time. A voltagecontrolled tapped delay line can be made from a string of inverters, like the one shown in Fig. 2.14, where the output of each inverter is the input to the next inverter and where every other inverter output is a tap output. The delay line is placed in a delay-locked loop to ensure that its total delay is equal to one wavelength of the input frequency, Fref . For a delay line with x taps, this ideally produces x identical copies of Fref that are equally spaced in time by td =

Tref x

(2.14)

The tap selection logic uses the accumulator output at the time of overflow to select one of the x taps to construct the output waveform as shown in Fig. 2.13. As one might expect, there is a quantization impact on the spurious performance level associated with the digital-to-time conversion process. This is analogous to the quantization performance of a digital-to-analog converter. The frequency offset and level of the spurs constitute a predictable function based on the number of accumulation cycles before the process repeats and the digital-to-time resolution error. There are several ways to improve the spurious performance; two of them are to increase the number of taps or to dither between two adjacent taps. Increasing the number of taps decreases the quantization error of the digital-to-time conversion process

td FREF Tap 0 Tap 1

Tap x−3 Tap x−2 Tap x−1

FOUT

FIGURE 2.13

Tap selection process to produce the output waveform.

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by providing finer time resolution. However, this method reaches a practical limit that is set by the minimum time delay that can be achieved in a given process technology. The second spur reduction method is to dither the tap selection process in order to spread the spurious energy over a frequency range. However, the spreading range must be greater than the frequency range of interest to have a net lowering impact on the spurious level. 2.3.4.3 Frequency Extension Both PLL- and DDS-based systems must provide quadrature outputs if they are to drive direct-conversion receivers. They also both require some method of frequency extension to cover the frequency range of SDR applications. Delay- locked loop (DLL)–based multipliers can provide both functions. Two recently reported SDR transceivers use this method [34,35]. DLL-based multipliers take the multiple phase copies from a tapped delay line and process them, typically with combination logic, to construct an output signal at some multiple of the input reference frequency. Like the preceding example, the delay line is configured in a DLL as shown in Fig. 2.12, thereby locking it to one wavelength of the input frequency and establishing predictable phases at the tap outputs. The control voltage, vtune , sets the delay of the individual cells by varying the tail current through an inverter as shown in Fig. 2.14. In making the tuning range as large as possible, care must be taken to prevent false locking, where the loop tries to lock to something other than the desired number of wavelengths. This may be avoided by using startup sequences that force the delay line to a known state before letting the loop take over. Imperfections in the delay line, such as mismatch error or DLL offset error, will cause spurs and undesired harmonic content in the output spectrum.

vdd vdd

Vin

Vout Vout,m Vp

Vout,p Vm

vtune vtune

(a)

FIGURE 2.14 PMOS load.

(b)

Delay cells: (a) simple current-starved inverter; (b) differential pair with a

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DLL-based multipliers can be constructed using either recirculating or edge combining methods. The recirculating method uses the delay line in a ring oscillator configuration and then periodically breaks the loop in order to inject a reference pulse onto the delay line [36]. The edge-combining method multiplies by combining the appropriate phases from the tapped delay line using XOR gates [37,38] or custom analog circuits [39,40]. Various multiplication factors are possible, depending on how the phases are combined. These circuits lend themselves to quadrature generation. There are challenges to generating high frequencies this way. At 5 GHz, the pulse width of a 50% duty cycle square wave is 100 ps. Interconnecting parasitics between the output combining cells place a capacitive load on each output stage and can degrade the rise and fall transition rates to a significant portion of the output period. This, in turn, degrades the performance of the switching mixers it is driving by not providing full swing and fast transitions. Also, cross-coupling between adjacent wires can degrade the I/Q accuracy, which will decrease the sideband suppression at the mixer output. 2.3.4.4 LO Generation Summary Significant innovation is required to meet the LO generation needs of SDR transceivers. PLL-based synthesizers require new methods for increasing the tuning range. Recent approaches that combine maximized VCO tuning range with a DLL-based multiplier make progress toward that goal. DDS approaches achieve a broad tuning range more easily, but innovation is required to decrease power consumption and control spurs.

2.4

EXAMPLE OF AN SDR TRANSCEIVER

The following example is a highly reconfigurable low-power transceiver implemented in a 90-nm CMOS process. Flexible programming allows the RFIC to process signals of multiple wireless protocols from 100 MHz to 2.5 GHz with −6 dBm and a voltage gain of 48 dB. The transmitter has better than 40 dB of carrier suppression, 35 dB of sideband suppression, and an EVM of 1% at 800 MHz. The frequency synthesizer uses direct digital synthesis to achieve instantaneous frequency switching and a phase noise of −115 dBc/Hz at 25 kHz offset for a 500-MHz carrier frequency. Referring to Fig. 2.15, three independent DDSs use a single 1-GHz PLL reference to provide differential quadrature LO signals to the receiver, transmitter, and Cartesian feedback mixers. Direct conversion is used in the receiver and a direct launch quadrature modulator is used in the transmitter. One of five receiver paths is selected to drive a common analog baseband lowpass filter section with programmable corner from 4 kHz to 10 MHz. There are provisions for receiver AGC, dc offset correction, and in-band and out-of-band receiver signal strength indicators (RSSIs). Dynamic matching is used in direct-conversion-mixers for improved second-order intermodulation intercept point (IP2), flicker noise, and dc offset. Differential baseband analog in-phase and quadrature receiver signal outputs are provided for external connection to an ADC and digital processing.

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EXAMPLE OF AN SDR TRANSCEIVER

Rx DDS

Reference PLL/VCO

PMA

VGA

DCOC

BQ

MUX SPI

Tx TEST POINTS

Reference

Tx Forward DDS Forward Pole 2

Butterworth

Input Buffer

Cartesian BB Forward

Cartesian Rev Amp/Mixer

Tx Reverse DDS

FIGURE 2.15

Reference

Transceiver block diagram.

Differential baseband in-phase and quadrature inputs from an external transmitter DAC are applied to programmable lowpass filters similar to the receiver with 10% bandwidth steps from 4 kHz to 10 MHz bandwidth. There is one of three selectable transmitter paths with up to 90 dB of on-chip programmable gain available (for power control). A transmitter feedback network is provided for closed-loop narrowband linearization or open-loop alternative transmitter signal analysis and processing. 2.4.1

Direct-Conversion Receiver

The RFIC contains five fully differential receiver inputs that drive fully differential dynamically matched (chopping) passive quadrature (I/Q) mixers. Four of the five RX inputs have on-chip LNAs with 50  of differential input impedance, and the last is designed with a 200- differential input impedance for use with an external

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OUTm

LOp

FIGURE 2.16

LOm

OUTp

RFm

CHOPp

RFp

CHOPm

c02

Dynamic matching mixers.

LNA. The RX input path is selectable through software. The LNA is a common-gate architecture with cascoding and RF AGC provided by the current steering pair. Source followers are used to drive the capacitive load of the mixer stage as well as the significant parasitic of the caps used for ac coupling. The quadrature mixers on RX inputs 1, 3, and 5 are nonchopped passive mixers built with a quad ring of CMOS transmission gates. The quadrature mixers on RX inputs 2 and 4 use dynamic matching (chopping) [41,42] to improve second-order intermodulation (IP2), flicker noise, and dc offset. The chopping mixers are built with three mixers in series (Fig. 2.16), where each mixer is built with a quad ring of CMOS transmission gates (Fig. 2.17).

RFp

LOm

OUTp

LOp

OUTm

RFm

FIGURE 2.17

Mixer made from CMOS transmission gates.

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Because the mixer design is passive (with active CMOS devices acting as switches), excellent power drain, linearity, and noise figure are achieved. The current drain from the 1.2-V supply of the LO buffers for the nonchopped I/Q mixers is typically 3.7 mA at 1 GHz, while the IIP3 of the mixers is +17 dBm. The noise figure of the mixers is 5 dB (essentially equal to the conversion loss). All of the mixer current drain comes from the LO buffers and multiplexers, since there is no dc current drain in actual mixer switching CMOS devices. The drain with the chopping mixers is somewhat higher than the nonchopped mixers, due to the additional hopping clock buffers and depends on the value of the chopping frequency. Baseband filters that support multiple bandwidths are implemented along with gain control and dc offset correction. The filter architecture has four poles of filtering, with two real poles and one complex pole pair in the Sallen–Key BiQuad. The shape was designed by taking a fourth-order Butterworth prototype and replacing the low-Q complex pole pair with two real poles. A filter bandwidth is programmable from 4 kHz to 10 MHz in 6.25% steps or less. Sufficient margin is built into the design to allow for a 20% change in RC tolerance and still maintain the bandwidth range of 4 kHz to 10 MHz. Bandwidth selection is implemented by adjusting the resistor and capacitor values in the filter design. The user has independent control of the pole locations of the post-mixer amplifier (PMA), voltage-gain amplifier (VGA), and BiQuad, as well as control of the BiQuad filter Q. This gives the user flexibility to trade off filter shape and attenuation for passband amplitude and phase distortion. Baseband filter gain control is accomplished at three points. A programmable resistor divider at the input of the PMA allows attenuation in four 6-dB steps while maintaining an input impedance of 2 k differential. The PMA has a maximum gain of 32 dB and a minimum gain of −10 dB. The VGA has a gain range of 8 dB, and the output buffer has a programmable gain control of 0 to 18 dB in 6-dB steps. The entire baseband filter lineup has a maximum gain of 64 dB and a minimum gain of −4 dB. A notable feature of the baseband filter is the use of chopper stabilization to mitigate the undesirable effects that occur in direct-conversion receivers when designed in a CMOS process. This is of particular concern in narrowband FM applications, where CMOS flicker noise can degrade sensitivity and noise figure. Chopper stabilization is implemented around the first-stage amplifier of each twostage op-amp. This implementation was chosen due to the fact that the op-amp’s input-referred voltage offset and flicker noise performance are heavily dependent on the first stage of the op-amp. The chopper frequency is derived from the crystal input and can be selected as a divide by 1, 2, 4, or 8 of the crystal frequency. Flicker noise is essentially eliminated when chopping is enabled, and thus narrowband protocols will see improvement in receiver sensitivity. The measured performance of chopper stabilization is shown in Fig. 2.18. Dc offset correction circuitry (DCOC) is implemented as a complete control loop that corrects dc offsets automatically at the output of the baseband filter. DCOC consists of a 1-bit ADC (comparator), control logic, and a 5-bit current-mode DAC that injects current into the feedback resistors of the VGA to adjust the offset voltage. The control logic implements a successive approximation algorithm that converges on the correct 5-bit word that compensates for the filter’s dc offset.

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Ref –30.01 dBmV Samp Log 2 dB/

Mkr1 0 Hz –28.96 dBmV

Atten 0 dB

Average 20 VAvg 20 S1 V2 V3 FC AA

CHOPPER DISABLED

CHOPPER ENABLED Center 0 Hz •Res BW 1 kHz

FIGURE 2.18

2.4.2

•VBW 30 Hz

Span 100 kHz Sweep 4.285 s (401 pts)

Received signal spectrum with and without chopping.

Direct-Launch Transmitter

A transmitter direct-launch quadrature modulator will support both linear and constant envelope modulation formats to cover standards with baseband bandwidths of 4 kHz to 10 MHz (channel bandwidths of 8 kHz to 20 MHz) and RF carrier frequencies from 100 MHz to 2.5 GHz. There are two fully differential modes of operation: classical I/Q or polar (with an external PA). In either case, baseband bandwidths and output power are programmable to meet the spectral mask requirements of a given protocol. For narrow- and medium-band protocols, a Cartesian feedback system provides the necessary linearization. This system requires a down-mix path (receiver) that samples the output of the power amplifier and uses that sampled signal to correct for any nonlinear induced errors in the forward transmission path. The baseband transmitter block provides filtering, programmable attenuation, level shifting, and buffering for the DAC inputs and drives the forward RF section and/or the Cartesian baseband forward path. The input buffers provide stepped attenuation for the incoming baseband signals. Programmable active RC reconstruction filters limit the amount of far-out quantization noise and images due to aliasing. An RC tracking oscillator provides automatic filter pole adjustment for the reconstruction filters. Closed-loop correction of baseband dc offsets and I/Q phase and gain imbalance is done in the pretransmittal warm-up period. The forward RF chain contains three separate RF mixer/driver paths along with the associated biasing and gain control. Each path is independently programmable to trade off bandwidth, power control range, and linearity according to the signal protocol being processed. The Cartesian feedback path is essentially a highly linear direct-conversion receiver with low sensitivity. The output of the external power amplifier is coupled into

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the RF inputs of this block, where the signal is either amplified or attenuated and then down-converted to baseband using the down-mixer and feedback LO. Two baseband amplifiers provide programmable gain for the feedback signal before being fed into the Cartesian forward path. With its programmable gain control, this block provides the feedback gain in the Cartesian system that ultimately controls the output power of the transmitter. Two 6-bit dc offset DACs tune out any offset errors at 2.5 mV per step. 2.4.3

Direct Digital Frequency Synthesizer

A single VCO provides the 1-GHz clock (labeled “Reference” in Fig. 2.15) to the digital processing blocks of multiple independent DDSs, each of which can be tuned independently and with phase-coherent properties. This arrangement is completely immune to VCO pulling [26] and transmitter remodulation [27] since the VCO is not operating at the DDS output frequency. Each DDS generates square-wave outputs with fast rise and fall times that are ideal for driving the switching mixers in the receiver and transmitter. Finally, the cycle-to-cycle frequency switching enables unique transceiver capabilities that are not possible with traditional phase-locked loops with their associated lock times. Traditional direct digital synthesizers have two disadvantages relative to PLL-based synthesizers: power consumption and spurious frequency content. The DDS architecture developed in Motorola Labs [43–45] uses a ROM-less architecture to achieve typical power consumption below 120 mW and non-zero-mean dither [46] to keep spurious frequency components below −35 dBc. The differential I and Q outputs can switch frequency on a (glitch-free) cycleto-cycle basis anywhere from 100 MHz to 2.5 GHz. With 15 Hz of resolution and a measured phase noise of −115 dBc/Hz at 25 kHz of offset and −150 dBc/Hz at 20 MHz of offset for a 500-MHz carrier, the DDS has the flexibility and the noise and switching time performance that is needed for SDR applications. 2.4.4

Performance Summary

The transceiver provides continuous receiver and transmitter coverage from 100 MHz to 2.5 GHz. It utilizes programmable lowpass filters with bandwidth selectable in 10% steps from 4 kHz to 10 MHz. Technical issues associated with direct-conversion receiver technology were overcome with a novel implementation of dynamic matching. A universal transmitter was implemented with direct-launch quadrature modulation using a DDS solution. Differential transmitter output power of +6 dBm with 80 dB of 1 dB of resolution power control was implemented with a power dissipation of 180 mW. A Cartesian feedback network is included to provide up to 30 dB of adjacent channel-coupled power transmitter linearization improvement at 25 kHz of offset, maintained over a 30-dB power control range. Only a single reference voltage-controlled oscillator (VCO), operating at a single frequency is required by using DDS signal source technology instead of phase-locked-loop signal synthesis.

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TABLE 2.2 Summary of Transceiver Performance Frequency range RX NF RX gain RX IIP2 RX IIP3 RX current drain TX output power TX sideband suppression TX current drain EVM π /4 DPQSK 3.5 MS/s LO phase noise LO frequency resolution LO current drain per DDS

2.4.5

100 MHz–2.5 GHz 7 dB 48 dB +60 dBm −6 dBm 40 mA +6 dBm 35 dBc 40−90 mA 1% @ 800 MHz −115 dBc/Hz @ 25 kHz 15 Hz 80 mA

RFIC Transceiver Application Example

The transceiver chip described above is at the heart of a CR platform that integrates the RFIC, data converters, Xilinx FPGA, and PowerPC microprocessor into a low-cost (≈ $6000), compact module. Small development teams have used it to demonstrate GSM, UMTS, Tetra, 802.11, and proprietary waveform communications. One early CR demonstration used an experimental OFDM-based physical layer, spectrum sensing and neighbor discovery module, and a GUI to display how the system was interfacing with the RF signal environment [47]. Transmission performance is summarized in Table 2.2. REFERENCES 1. M. McHenry and D. McCloskey, Spectrum Occupancy Report for New York City During the Republican Convention August 30–September 1, 2004 Technical Report, Shared Spectrum Company, 2004. 2. J. Mitola, “The software radio architecture,” IEEE Commun. Mag., vol. 33, no. 5, pp. 26–38, May 1995. 3. S. Rodriguez-Pareram, A. Bourdoux, F. Horlin, J. Carrabina, and L. Van der Perre, “Frontend ADC requirements for uniform bandpass sampling in SDR,” in IEEE Vehicular Technology Conference, pp. 2170–2174, Apr. 2007. 4. R. H. Walden, “Analog-to-digital converter survey and analysis,” IEEE J. Select. Areas Commun., vol. 17, no. 5, pp. 539–550, Apr. 1999. 5. A. A. Abidi, “Low-power radio-frequency IC’s for portable communications,” Proc. IEEE, vol. 4, no. 4, pp. 544–565, Apr. 1995. 6. K. Muhammad, Y.-C. Ho, T. Mayhugh, C.-M. Hung, T. Jung, I. Elahi, C. Lin, I. Deng, C. Fernando, J. Wallberg, S. Vemulapalli, S. Larson, T. Murphy, D. Leipold, P. Cruise, J. Jaehnig, M.-C. Lee, R. Staszewski, R. Staszewski, and K. Maggio, “The first fully integrated quad-band GSM/GPRS receiver in a 90-nm Digital CMOS process,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1772–1783, Aug. 2006.

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7. V. Giannini, J. Craninckx, S. D’Amico, and A. Baschirotto, “Flexible baseband analog circuits for software-defined radio front-ends,” IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1501–1512, July 2007. 8. A. Loke and F. Ali, “Direct conversion radio for digital mobile phones: design issues, status, and trends,” IEEE Trans. Microwave Theory Tech., vol. 50, no. 11, pp. 2422–2434, Nov. 2002. 9. P. Allan and D. Holberg, CMOS Analog Circuit Design, 2nd ed. New York: Oxford University Press, 2002. 10. J. Chang, A. A. Abidi, and C. R. Viswanathan, “Flicker noise in CMOS transceivers from subthreshold to strong inversion at various temperatures,” IEEE Trans. Electron Devices, vol. 41, no. 5, pp. 1965–1971, Nov. 1994. 11. Y. Nemirovsky, I. Brouk, and C. G. Jakobson, “1/f noise in CMOS transistors for analog applications,” IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 921–927, May 2001. 12. M. Grozing and M. Berroth, “Derivation of single-ended CMOS inverter ring oscillator close-in phase noise from basic circuit and device properties,” in Proc. 2004 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 277–280, June 2004. 13. W. S. Percival, “Thermionic valve circuits,” British Patent Specification 460,562, Jan. 1937. 14. E. L. Ginzton, W. R. Hewlett, J. H. Jasberg, and J. D. Noe, “Distributed amplification,” Proc. IRE, pp. 956–969, Aug. 1948. 15. L. Zhao, A. Pavio, B. Stengel, and B. Thompson, “A 6 watt LDMOS broadband high efficiency distributed power amplifier fabricated using LTCC technology,” in IEEE MTT-S International Microwave Symposium (IMS) Digest, pp. 897–900, June 2002. 16. J. Y. Liang and C. S. Aitchison, “Signal-to-noise performance of the optical receiver using a distributed amplifier and P-I-N photodiode combination,” IEEE Trans. Microwave Theory Tech., vol. 43, no. 9, pp. 2342–2350, Sept. 1995. 17. B. Thompson and R. Stengel, “Amplifier containing programmable impedance for harmonic termination,” U.S. Patent Application 2008/0079496, Apr. 2008. 18. G. D. Leizerovich and M. A. Goldberg, “Method and apparatus for optimizing supply modulation in a transmitter,” U.S. Patent 7,164,893, Jan. 2007. 19. B. Stengel and B. Thompson, “Neutralized differential amplifiers using mixed-mode S-parameters,” in Proc. 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 711–714, June 2003. 20. Z. Shu, K. L. Lee, and B. Leung, “A 2.4 GHz ring oscillator based CMOS frequency synthesizer with a fractional divider dual-PLL architecture,” IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 452–462, Mar. 2004. 21. M. Steyaert, B. D. Muer, P. Leroux, M. Borremans, and K. Mertens, “Low-voltage lowpower CMOS-RF transceiver design,” IEEE Trans. Microwave Theory Tech., vol. 50, no. 1, pp. 281–287, Jan. 2002. 22. D. Hauspie, E. Park, J. Craninckx, and B. Comel, “Wideband VCO with simultaneous switching of frequency band, active core and varactor size,” in Proc. European Solid-State Circuits Conference (ESSCIRC’06), Sept. 2006. 23. P. Zhang et al., “A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18 micron CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1932– 1939, Sept. 2005.

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SOFTWARE-DEFINED TRANSCEIVERS

24. K. Araki, T. Nakagawa, M. Kawashema, K. Kobayashi, K. Akabane, H. Sheba, and H. Hayashi, “Implementation and performance of a multi-band transceiver for software defined radio,” in Proc. IEEE Radio Wireless Conference (RAWCON’04), pp. 207–210, Sept. 2004. 25. R. Bagheri, A. Mirzaei, M. E. Heidari, S. Chehrazi, L. Minjae, M. Mikhemar, W. K. Tang, and A. A. Abidi, “Software-defined radio: dream to reality,” IEEE Commun. Mag., vol. 44, no. 8, pp. 111–118, Aug. 2006. 26. J. Rogers et al., “A multiband − fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 678–689, Mar. 2005. 27. O. Charlon et al., “A low-power high-performance SiGe BiCMOS 802.11a/b/g transceiver IC for cellular and Bluetooth co-existence applications,” IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 1503–1512, July 2006. 28. P. Torkzadeh, A. Tajalli, and M. Atarodi, “A wide tuning range, 1GHz–2.5GHz DLL-based fractional frequency synthesizer,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS’05), pp. 5031–5034, May 2005. 29. J. V. Drieessche, J. Craninckx, and B. Come, “Analysis and key specifications of a novel frequency synthesizer for multi-standard transceivers,” in Proc. IEEE Radio and Wireless Symposium (RWS’06), pp. 481–484, Jan. 2006. 30. T. Maeda et al., “Low-power-consumption direct-conversion CMOS transceiver for multistandard 5-GHz wireless LAN systems with channel bandwidths of 5–20 MHz,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 375–383, Feb. 2006. 31. A. McEwan and S. Collins, “Direct digital-frequency synthesis by analog interpolation,” IEEE Trans. Circuits Syst. II, vol. 53, no. 11, pp. 1294–1298, Nov. 2006. 32. J. Tierney, C. Rader, and B. Gold, “A digital frequency synthesizer,” IEEE Trans. Audio Electroacoust., vol. 19, no. 1, pp. 48–57, Mar. 1971. 33. C. Wang et al., “A 13-bit resolution ROM-less direct digital synthesizer based on a trigonometric quadruple angle formula,” IEEE Trans. VLSI Syst., vol. 12, no. 9, pp. 895– 900, Sept. 2004. 34. J. Craninckx et al., “A fully reconfigurable software-defined radio transceiver in 0.13 micron CMOS,” in Proc. IEEE International Solid-State Circuits Conference (ISSCC’07), pp. 346–347, Feb. 2007. 35. G. Cafaro et al., “A 100 MHz–2.5 GHz direct conversion CMOS transceiver for SDR applications,” in Proc. 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 189–192, June 2007. 36. P. Maulik and D. Mercer, “A DLL-based programmable clock multiplier in 0.18 µm CMOS with −70 dBc reference spur,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1642–1648, Aug. 2007. 37. C. Lin and C. Chiu, “A 2.24 GHz wide range low jitter DLL-based frequency multiplier using PMOS active load for communications applications,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS’07), pp. 3888–3891, May 2007. 38. K. Cheng, S. Chang, S. Jiang, and W. Yang, “A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS’05), pp. 1174–1177, May 2005.

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39. M. Faisal and P. Zhao, “A low-power clock frequency multiplier,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS’06), pp. 1495–1498, May 2006. 40. C. Kim, I. Hwang, and S. Kang, “Low-power small-area +/−7.28 ps jitter 1 GHz DLL-based clock generator,” in Proc. IEEE International Solid-State Circuits Conference (ISSCC’02), pp. 107–107, Feb. 2002. 41. E. Bautista, B. Bastani, and J. Heck, “A high IIP2 downconversion mixer using dynamic matching,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1934–1941, Dec. 2000. 42. ———, “Method and apparatus providing improved intermodulation distortion protection,” U.S. Patent 6,125,272, Sept. 2000. 43. J. Juan, R. Stengel, F. Martin, and D. Bockelman, “Cascaded delay locked loop circuit,” U.S. Patent 6,891,420, Sept. 2006. 44. D. Bockelman and J. Juan, “Time interpolating direct digital synthesizer,” U.S. Patent 6,353,649, Mar. 2005. 45. F. Martin, R. Stengel, and J. Juan, “Method and apparatus for digital frequency synthesis,” U.S. Patent 7,154,978, May 2005. 46. T. Gradishar and R. Stengel, “Method and apparatus for noise shaping in direct digital synthesis circuits,” U.S. Patent 7,143,125, Nov. 2006. 47. D. Taubenheim et al., “Implementing an experimental cognitive radio system for DySPAN,” in Proc. IEEE Global Telecommunications Conference (GLOBECOM’07), pp. 4040–4044, Nov. 2007. 48. M. Rowley and D. Bockelman, “Mixer with reduced carrier feedthrough,” U.S. Patent 6,603,964, Aug. 2003.

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Adaptive Multi-Mode RF Front-End Circuits ALEKSANDAR TASIC Qualcomm, San Diego, California

3.1

INTRODUCTION

To provide various services from different wireless communication standards with high capacities and high data rates, integrated multi-functional wireless devices are required. In the current multi-standard scenario of portable wireless systems, transceivers are mostly implemented by replicating the radio-frequency (RF) front end for each operating standard and by sharing partially the analog baseband circuitry, but with the aid of a number of additional switches. Although this approach allows for an optimal performance optimization across the bands, the increase in hardware required to implement such a multifunctional wireless device increases the total silicon area and cost and may reduce the use time compared to single-standard implementations. By sharing building blocks between different applications and standards, portable wireless devices potentially gain advantage over existing devices: They use a smaller chip area and have a potential for lower overall cost. This requires the development of adaptive circuits and systems that are able to trade off power consumption for performance on the fly. Realization of adaptivity functions requires scaling of current consumption to the demands of the signal processing task [1]. The design implementation of such an adaptive front-end circuit is presented later in the chapter. In the following section we outline the application of adaptivity to multi-standard low-power wireless RF circuits. In Section 3.3 we describe a multi-mode receiver concept in the framework of second- and third-generation communication standards. The design of the adaptive quadrature down-converter circuits used in the experimental implementation is described in Section 3.4. Measurement results of the multi-mode test circuit presented in Section 3.5 demonstrate that power consumption can be saved when adaptivity is employed in the multi-mode receiver. Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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ADAPTIVE MULTI-MODE LOW-POWER WIRELESS RF IC DESIGN

Progress in silicon integrated-circuit (IC) technology [2] and innovations in IC design have enabled the mobility of wireless products and services [3,4]. Mobile wireless equipment today is shaped by user and application demands and RF microelectronics. Main drivers for mobile wireless devices are related to cost, which depends on volume of production, size of mobile units, engineering bill of materials, power consumption, and performance; power consumption, which depends on available frequency spectrum, functionality, and performance; and performance, which depends on applications, standards, and protocols. Wireless systems for new applications [5–9] require an extension of the capabilities for the RF devices of today, creating an opportunity for low-power adaptive and multifunctional RF ICs.

3.2.1

Low-Power and Adaptive RF Circuit Design

The communication devices of both today and the future will not only have to allow for a variety of applications, supporting the transfer of text, audio, graphic, and video data, but will also have to maintain connection with many other devices rather than with a single base station, in a variety of environments. Moreover, they should be position aware, and perhaps wearable rather than just portable [10–12]. A combination of multiple functional requirements and limited energy supply from a battery is an argument for the design of both adaptive low-power hardware and software [10,11]. An adaptive design approach poses unique challenges: from hardware design to application software, and ultimately throughout all layers of the underlying communication protocol [10–15]. A block diagram of the receiver in an adaptive mobile device is shown in Fig. 3.1. This receiver consists of adaptive analog RF front-end circuitry, adaptive analog baseband circuitry, and an adaptive digital signal processor in the back end. Whereas the transceiver circuits determine instantaneous power consumption, the average power consumption depends on the power management of the complete system [12]. This implies that not only local, but also global power optimization

FIGURE 3.1

Topology of an adaptive receiver.

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67

and awareness (i.e., at all layers and at all times) are important to extend the battery lifetime (i.e., the time between battery charges) of mobile devices. Setting the performance parameters of an RF front end by means of adaptive circuitry is a way to manage power consumption in the RF path of a receiver [1]. An adaptive low-noise amplifier (LNA), an adaptive mixer, and an adaptive voltagecontrolled oscillator (VCO) allow more efficient use of scarce battery resources, thereby extending the lifetime of a mobile device. Furthermore, adaptive analog baseband and digital back-end circuits enable complete hardware adaptivity. Analog and digital baseband signal processing functions could be used to monitor quality of service (e.g., bit-error rate) and adjust the receiver parameters (e.g., tune a single or multiple bias currents) in real time to meet the performance requirements. RF front-end robustness can be further improved by control of antenna beam patterns, transmitter power levels, and by control of circuit noise and linearity levels. For example, adaptive modulation and adaptive coding strategies [13], where the system can choose an optimal modulation and coding technique based on the temporal circumstances, can ameliorate the effects of multi-path fading, shadow fading, and path loss. Application-level adaptivity can be related to the scaling of the operating power and clock frequency in a general-purpose processing unit under the control of poweraware applications, such as video- and audio-decoding software. Here, dynamic adjustment of the supply voltage can be traded for processor speed, allowing power savings in the digital circuitry [15]. 3.2.2

Multi-Mode and Adaptive RF Circuit Design

To provide various services from different wireless communication standards at high data rates requires not only adaptive and low power designs, but also the designs that work across multiple bands and standards [2,16–20]. Global system for mobile communications (GSM), universal mobile telecommunications system (UMTS), Bluetooth, 802.11a,b,g wireless local area network (WLAN), global positioning system (GPS), and digital video broadcasting–handhelds (DVB-H) are some of the standards likely to be present in the multi-standard, multi-mode, multi-band (i.e., multifunctional) mobile terminals of the future. The design of multi-functional wireless devices is accompanied by various challenges at the system, circuit, and technology levels. System challenges include the design of a single high-performance, low-power terminal that is cheaper than a compound of separate single-mode terminals. Circuit design challenges for full integration of multifunctional devices include on-chip image rejection and provision of wide bandwidth and dynamic range. Technological challenges include the integration of low-cost and high-performance-scaled silicon devices on a chip. Multi-standard modules can be implemented in various ways: r As stand-alone circuits that are designed for the worst-case condition of the most demanding standard. Even though operating conditions might improve or a less demanding standard might be active, these circuits always operate at the highest power consumption levels.

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r As multiple circuits (i.e., one per standard). Even though simpler to implement, this approach requires more silicon area. Moreover, when multiple standards operate simultaneously, power consumption increases. r As stand-alone adaptive circuits. When different standards do not operate simultaneously, circuit blocks of a multi-mode handset can be beneficiary shared, offering power and area savings compared to other multi-standard receiver implementations, such as multi-standard receivers implemented using circuits designed for the worst-case condition [21] and multi-standard receivers implemented with one receiver circuit per standard [16]. For adaptive low-noise amplifiers and mixers, power consumption is traded off for dynamic range, whereas adaptive oscillators trade off power consumption for phase noise and oscillation frequency. The design of such an adaptive multi-mode RF front-end circuit is presented in this chapter. After a signal is down-converted to the baseband, it is filtered, amplified, and digitized. To accommodate multiple radio standards with different bandwidths and modulation schemes, multi-mode lowpass filters need to compromise bandwidth, center frequency, selectivity, and group delay for optimal dynamic range and power consumption [22–24]. Multi-mode analo-to-digital converters have to sample signals belonging to different standards, tailoring different sample rates, dynamic range, and linearity requirements [25,26]. System requirements for multi-mode circuits and design of adaptive multi-mode RF front-end circuits are discussed in the next sections. 3.3

MULTI-MODE RECEIVER CONCEPT

The rationale behind the choice of a receiver architecture supporting multiple standards is detailed in this section. Multi-mode receiver operation is then introduced to describe the multi-standard scenario. Wireless devices may use a common receiver if the protocols of the radio standards support intersystem operability. One multistandard receiver scenario is shown in Fig. 3.2. Impedance matching, packaging, and prefiltering requirements are relaxed and simplified by using multiple LNAs. An RF

FIGURE 3.2

Multi-standard and adaptive receiver RF front end.

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MULTI-MODE RECEIVER CONCEPT

TABLE 3.1

Requirements for Various Standards Referred to Input of LNA

f 0 (GHz) NF (dB) IIP3 (dBm) PN @1 MHz (dBc/Hz)

DCS1800

WCDMA

WLAN

Bluetooth

DECT

1.8 9 −9 −123

2.1 6 −9 −110

2.4 10 −12 −110

2.4 23 −16 −110

2.4 18 −20 −100

switch selects the mode of interest. If the VCO and mixer performance is adequate to cover the range of signals anticipated for each application, the quadrature downconverter enables a multi-standard receiver realization with a single circuit block (multi-mode adaptive quadrature down-converter, MMA-QD IC, in Fig. 3.2) [20]. We consider the application of the design for adaptivity to multi-mode RF frontend circuits in the framework of the requirements of the standards listed in Table 3.1 [2,27–35] (out of many different sets of specifications, a single set of specifications is considered in this design, without loss of generality). Located between 1.8 and 2.4 GHz, these standards may be supported by a single wireless device. In the remainder of the chapter, we refer to the multiple modes of operation for the adaptive receiver shown in Fig. 3.2: With respect to the noise figure, linearity, and phase noise requirements of Table 3.1, the receiver operating modes are classified as demanding, moderate, and relaxed, as given in Table 3.2. In the context of the noise figure (NF) and third-order input intercept point (IIP3) requirements of the standards listed in Table 3.1, the demanding mode of operation may be related to the DCS1800 and WCDMA standards, the moderate mode to the IEEE 802.11b WLAN standard, and the relaxed mode to the Bluetooth and DECT standards. Table 3.2 also summarizes the phase noise (PN) requirements for different modes of operation: The demanding phase noise mode is related to the DCS1800 specification, moderate to the WCDMA and 802.11b/Bluetooth specifications, and relaxed to the DECT specification. Referring to Table 3.2, the adaptive oscillator has to cover a range of phase noise of around 21 dB [19]. Based on the noise figure and linearity requirements for each mode, the ranges of the NF and IIP3 to be realized by the adaptive multi-mode receiver are calculated from Table 3.2 as 12 and 7 dB, respectively. Given the bandwidth requirement, 1.8 to 2.4 GHz, and the noise and linearity requirements listed in Table 3.2, a single adaptive quadrature down-converter has been realized to interface the RF and baseband sections of the multi-mode receiver, shown in Fig. 3.2. The design of the down-converter circuits suiting this multi-mode implementation is described in the next section. TABLE 3.2

Receiver Noise and Linearity Specifications per Mode of Operation Mode

Specification NF (dB) IIP3 (dBm) PN @ 1 MHz (dBc/Hz)

Demanding

Moderate

Relaxed

6 −9 −123

10 −12 −110

18 −16 −100

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Referring to the channel spacing of the standards considered [28–32], zero intermediate-frequency (IF) and low-IF receiver configurations may be supported. For example, the multi-mode adaptive quadrature down-converter may operate in zero-IF mode for all standards considered except the 200-kHz narrowband GSM (DCS1800 band) standard where low-IF operation would be favored. The standards considered are chosen to illustrate the feasibility of the adaptivity design concept for multi-mode receivers. The procedure for designing for adaptivity presented in this chapter can be applied to any combination of standards. 3.4

DESIGN OF A MULTI-MODE ADAPTIVE RF FRONT END

Selection of the specifications for the multi-mode quadrature down-converter and choice of the down-converter circuits suiting sharing and adaptivity are described next. The design of a quadrature signal generator and quadrature mixers is then presented. The test circuit of the multi-mode quadrature down-converter consists of an adaptive VCO, oscillator buffers, a two-stage polyphase filter to generate quadrature local oscillator signals, mixer buffer amplifiers, and two double-balanced mixers, as illustrated in Fig. 3.2. 3.4.1

Multi-Mode Adaptive Quadrature Signal Generation

The VCO shown in Fig. 3.3 is used to implement the adaptive oscillator. A brief description of this multi-mode oscillator design [19] is presented here. The VCC-VCO L

CV

CV

VTUNE

QO1

LO -

CA

LO+

CB

CB

RB

RB

QO2 CA

VB

ITAIL QCS

QCS LRID

FIGURE 3.3

LRID

Adaptive LC oscillator.

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TABLE 3.3

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Parameters of the Adaptive LC-VCO

Parameter

Expression RL + RC (ωo C V )2 (ωo L)2 C A + C /2 1+ CB gm 2n G M,tk G tk Itail 2VT L
 1 C ACB CV + 2 CA + CB 1 √ 2π L tot Ctot

G tk n G M,tk k gm L tot Ctot f0

voltage-controlled oscillator consists of an LC tank (inductor L and p-n junction varactor C V ), two capacitive voltage dividers, C A and C B , and a cross-coupled transconductance amplifier, Q O1 –Q O2 . A resonant-degenerated bias-current source is implemented with the degeneration inductor L rid . This on-chip inductor is chosen to resonate with the base–emitter capacitor of Q CS at twice the oscillation frequency of f 0 in order to reduce the contribution of noise from the bias circuit to the phase noise of the oscillator [19,36]. The relationships between the parameters of the oscillator are summarized in Table 3.3. The resistors R L and RC model the inductor L and varactors C V series losses, G tk the effective LC-tank conductance (describing the total loss of the resonator), n the capacitive divider ratio, −G M,tk the small-signal conductance seen by the LC tank, k the small-signal loop gain, gm the transconductance of bipolar transistors Q O1 and Q O2 , C their base–emitter capacitance, and VT the thermal voltage. When the noise contributed by the bias circuit can be neglected [36], the oscillator phase noise performance depends on the components in the ac signal path (i.e., transconductance cell and resonator), as simplified by [1] PN ≈

1 + n/2 + nck n2k 2

(3.1)

where c is a small (usually smaller than 1) circuit constant. This phase noise model is parameterized with respect to power consumption via the small-signal loop gain k. It relates to the excess of the negative conductance of the oscillator transconductor necessary for compensation of the losses in the LC tank. A k-fold increase in negative conductance of the oscillator active part requires a k-fold increase in current consumption.

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In this adaptive voltage-controlled oscillator, the small-signal loop gain and voltage swing across the LC tank can be varied by changing (programming) bias tail current Itail (see Fig. 3.3). This allows adaptation of the oscillator phase noise to different operating conditions and specifications. We name this phenomenon phase noise tuning, and the phase noise tuning range (PNTR) as its figure of merit [37]. For a k2 /k1 -times change in current consumption, the phase noise tuning range for the oscillator under consideration can be defined as PNTR ≈

k12 1 + n/2 + nck2 k22 1 + n/2 + nck1

(3.2)

The minimum (k2 ) and the maximum (k1 ) small-signal loop gain and bias current are now estimated from the PNTR requirement and (3.2), as detailed in [1]. A PNTR of around 20 dB can be realized from a small-signal loop gain between 2 and 20, which is sufficient to accommodate the requirements of the multiple modes defined for this demonstration circuit in Table 3.2. For the maximum small-signal loop gain and lowest phase noise, a voltage swing across the bases (vS,B ) of the transconductor devices of 1.2 V is estimated from vS,B =

8 kVT . π

(3.3)

Once the maximum small-signal loop gain is known, the oscillator bias point can be determined. The choice of the base bias voltage VB is a compromise between a large output voltage swing and saturation of transconductor devices Q O1 and Q O2 [19]. To avoid the saturation of the transistors in the active part, the maximum voltage swing across the bases vS,B,max should satisfy vS,B,max ≤ 2

VCC − VB + VBE − VCE,sat n+1

(3.4)

where VCC = 3 V is the supply voltage, VBE is the active base–emitter voltage (≈ 0.8 V), and VCE,sat is the collector–emitter saturation voltage. For a capacitive divider ratio n of around 1.4, a base voltage VB of around 2.1 V is obtained. These calculations indicate that more than a tenfold reduction in power consumption can be realized between the phase noise–demanding and phase noise–relaxed modes of the adaptive voltage-controlled oscillator under consideration. A 3-nH tank inductor L is chosen as a compromise between low power consumption and high quality factor in the 2.1-GHz band. The inductor is fabricated using 4-µm-thick aluminum top metal in a 50-GHz SiGe bipolar technology [38]. This differentially shielded symmetric three-turn inductor uses a ladder metal filling, has an outer diameter of 320 µm, a metal width of 20 µm, and a metal spacing of 5 µm [39]. The varactor consists of two base–collector diodes with 32 fingers, each 4 µm wide and 20 µm long. Metal–insulator–metal capacitances C A = 150 fF and C B = 600 fF have been chosen. The degenerative inductance L rid has been set to 3.4 nH using

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FIGURE 3.4

73

Polyphase filter and buffer circuits.

the resonant-inductive degeneration noise-reduction method [36]. Common-collector buffers interface the polyphase filter and the oscillator. They consist of 0.5 × 1.7 µm2 transistors and consume 1 mA each. Given the frequency band of the down-converter implementation, 1.8 to 2.4 GHz, and the configurations supported, zero and low IF, the quadrature oscillator signals that drive the mixers are derived from a two-stage polyphase filter (PPF) (see Figs. 3.2 and 3.4). This PPF is chosen as a compromise between the rejection of the image signals and the attenuation of the oscillation signals. The first and second stages of the polyphase filter provide rejection at 1.75 and 2.15 GHz, respectively. This allows for higher image rejection in the 1.8-GHz band, where a low-IF operation is presumed: An image-rejection ratio (IRR) in excess of 30 dB suffices for down-conversion to a 100-kHz intermediate frequency [40]. Image-rejection requirements are relaxed around 2.1 and 2.4 GHz, as a zero-IF operation is assumed in these bands; an image-rejection ratio in excess of the signalto-noise ratio requirement is needed [40]. Taking into account noise and distortion sources accumulated throughout a receiver, some margin has to be added to the IRR requirement. The attenuation of the oscillation signal through the passive polyphase filter necessitates a second buffer stage between the filter outputs and the mixer quads. Each buffer provides 160 mV of signal swing and consumes 1.1 mA of bias current.

3.4.2

Multi-Mode Adaptive Quadrature Down-Converter

Selection of specifications for receiver circuits is a complex task, taking into account the relationships and trade-offs between gain, noise figure, linearity, and power consumption [1]. For adaptive and multi-mode circuits, these relationships become even more complicated. Next to the design requirements for single-mode systems (i.e., sensitivity, selectivity, and spectral mask) in the design of multi-mode transceivers

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TABLE 3.4 Required Performance for the Multi-Mode Quadrature Downconverter in Various Modes of Operation for 0 dB of Gain Mode Specification

Demanding

Moderate

Relaxed

NFqd (dB) IIP3qd (dBm)

12.7 6.74

19.75 3.35

28.8 −0.87

with multiple signal paths integrated on silicon, blocking, distortion, and wideband noise from interferers belonging to different transmitters and standards have to be taken into account. To facilitate the selection of specifications for the experimental adaptive quadrature down-converter, we assume that each LNA has a noise figure of 2 dB, an IIP3 of 1 dBm, and 13 dB of gain. For the (quadrature) baseband (BB) circuitry (i.e., the cascade of baseband circuits, such as IF filters and amplifiers), an NFbb of 14 dB and an IIP3bb of 9 dBm are assumed in the specifications’ derivations. Given the multi-mode receiver requirements (see Table 3.2) and the specifications for the LNA and baseband circuitry, the noise figure and linearity performance of the quadrature down-converter can be determined for each mode of operation using the optimal performance selection criteria [1] as a form of the cascaded NF and IIP3 formulas [11,41]. They are summarized in Table 3.4. When the quadrature down-converter NF and IIP3 values are adapted between 12.7 dB/−0.87 dBm and 28.8 dB/6.74 dBm, respectively, the multi-mode receiver satisfies the requirements listed in Table 3.2, the demanding-mode performance is met with a 0-dB gain of the down-converter with an accompanying NF tuning range (NFTR) of 14.6 dB and an IIP3 tuning range (IIP3TR) of 7.6 dB [1]. Note that by trading off the performance of the LNA and baseband circuitry, a different (more relaxed or more demanding) set of down-converter requirements results. The second-order intermodulation (IM2) performance of the quadrature mixers dominates the IM2 distortion for the complete receiver. As the IM2 products fall close to dc, they interfere with the signal desired in zero-IF mode of operation. However, the IM2 products from an LNA can be filtered by a tuned LNA load or by ac-coupling between the LNA and the mixer. Typically, a receiver with an input-referred secondorder intercept point (IIP2) better than 45 dBm would suffice for zero-IF operation within the framework of the standards under consideration [43]. For example, for an LNA with 13 dB of gain, this translates to an IIP2 requirement of 58 dBm from the quadrature down-converter. The choice of the mixer circuit stems from the receiver architecture chosen and the receiver bandwidth and performance requirements. The 1.8 to 2.4-GHz bandwidth requires a mixer circuit with a relatively broad (and flat) frequency response to accommodate receiver operation in the various modes. Figure 3.5 is a schematic of the double-balanced mixer that is used to implement the quadrature down-converter [44]. It suits adaptivity and circuit sharing and has the

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DESIGN OF A MULTI-MODE ADAPTIVE RF FRONT END

FIGURE 3.5

75

Mixer with output transformer balun.

potential to meet the down-converter performance requirements in different modes of operation. The mixer consists of a class AB input stage (Q M1−M4 ) for improved linearity, cascoded by switching quad Q M5−M8 . The single-ended input is converted into a differential current via common-base stage Q M1 and current mirror Q M2 , Q M3 . Distortion and RF input impedance matching are improved by resistors R M1 to R M4 . Transistors Q M1 and Q M4 improve symmetry in the input stage and attenuate local oscillator leakage to the RF input. A low mixer input impedance facilitates the matching of the down-converter over a relatively wide range of frequencies. Only a simple input matching network is required when characterizing the gain, noise figure, and linearity performance of this mixer. Linearity performance in the mixer can be traded for the noise figure. By reducing the mixer bias current, the switching noise contribution can be reduced. However, this tends to degrade the linearity of the switching quad. On the other hand, the emitter area of the quad transistors is a compromise between a small transistor, which allows for better linearity, and a large transistor, which generates less thermal noise in the switching quad. Faster switching of the quad (and accordingly, better linearity and noise figure) can be ensured to a certain level by a large VCO signal amplitude. The linearity and noise figure of the transconductance stage can also be traded off by adjusting the bias current and area of transistors Q M1 –Q M4 [44]. The transistors and resistors are therefore sized to optimize conversion gain, noise figure, and linearity. For the mixer input stage, transistors Q M1−M4 have a length/width ratio of 40 µm/0.5 µm, and RM 1 to RM 4 are the low-ohmic resistors. For the switching quad, transistors Q M5 to Q M8 have a length/width ratio of 8 µm/0.5 µm. The mixer performance parameters can be adaptively adjusted by changing the mixer bias current, which is set by the voltage applied to the base terminals of Q M1 and Q M4 .

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Simulations show that the down-converter satisfies the demanding-mode requirements, drawing 10 mA of current from a 2.2-V supply, and that a twofold reduction in power consumption can be realized between its moderate and demanding modes of operation. Performance trade-offs for the mixer described here have been studied extensively [44]. The performance of the voltage-driven quadrature down-converter has been characterized so far. However, if a complete receiver had been implemented, the mixer circuits could have been driven from a current output of an LNA, obviating the need for resistors R M1 and R M4 . The linearity performance of the mixer would improve expectedly, given the current-driven common-base input stage of the mixer [45]. This is a natural step toward complete elimination of the mixer input transconductor with manifold benefits for the linearity performance of such an implementation (i.e., a current-driven passive mixer). Different mixer circuit parameters could then be selected to meet the multiple requirements of Table 3.2.

3.5 EXPERIMENTAL RESULTS FOR THE IMAGE-REJECT DOWN-CONVERTER A 0.65 × 1.0 mm2 test chip (excluding bondpads) implemented in a 50-GHz SiGe bipolar technology (Fig. 3.6), was wirebonded into a 32-pin quad package. A custom printed-circuit board (see Fig. 3.7) with bias and supply line filtering was designed for testing. The differential quadrature IF signals are converted into single-ended form via external transformers with a 2 : 1 turns ratio. A 50- quadrature hybrid combines the mixer outputs at baseband, giving an effective mixer load of 200 . A block diagram of the complete test setup is shown in Fig. 3.8 (see Figs. 3.3, 3.4, and 3.5 for notation).

FIGURE 3.6

Photomicrograph of the adaptive quadrature down-converter.

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EXPERIMENTAL RESULTS FOR THE IMAGE-REJECT DOWN-CONVERTER

FIGURE 3.7

77

Packaged multi-mode adaptive quadrature down-converter IC in the test fixture.

FIGURE 3.8

Block diagram of the test setup.

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The performance of the complete adaptive quadrature down-converter has been characterized for the demanding mode of operation in the 2.1-GHz frequency band. The measured results for the image-reject down-converter in the demanding mode are summarized in Table 3.5 [20] after deembedding from the test setup shown in Fig. 3.8. Capacitors on the IF output signal lines (10 pF at each IF output) suppress highfrequency signals, and for the 70-MHz IF used in gain testing also attenuate some of the desired signal. The gain of the quadrature down-converter is around +1.4 dB. A higher gain can be achieved for a higher mixer load impedance. The noise and linearity performance has been measured within the bandwidth of the commercial hybrid, ranging from 70 to 150 MHz. The low input impedance of the down-converter facilitates a broadband response of the input network. This provides a similar gain for the input RF signals over the range of frequencies assessing the linearity performance of the quadrature down-converter. For the intermodulation products falling within the bandwidth of the hybrid, second- and third-order intercept points have been determined. An IIP3 of 5.5 dBm and an IIP2 of 51 dBm have been measured for a bias current of 5 mA per mixer. An improvement of around 5 dB can be expected for the IIP2 after low-frequency baseband filtering [33,34]. Moreover, increasing the amplitude of the applied quadrature VCO signals (at the cost of increased power consumption of the VCO and/or differential amplifiers) can improve the second-order intermodulation distortion [46]. The quadrature downconverter has a single-sideband noise figure of 13.9 dB in the demanding mode while drawing 10 mA of bias current. The measured image rejection of 20 dB is satisfactory for the zero-IF mode of operation. For low-IF operation, better image rejection would be required. Quadrature combining implemented on-chip at baseband (or in a digital back end) and a threestage polyphase filter implemented for oscillator quadrature signal generation are ways to improve the IRR in excess of 30 dB. Isolation between the oscillator port of the quadrature down-converter and the measured input RF port is approximately 45 dB. The quadrature mixers consume 10 mA in the demanding mode. The oscillator performance was characterized separately from a stand-alone test circuit implemented in the same technology [19]. Operating from a 3-V supply, the adaptive VCO achieves a tuning range of 600 MHz, ranging from 1.8 to 2.4 GHz, as shown in Fig. 3.9. To relax the requirement of a large frequency tuning range from a varactor, switched capacitor banks can be used [47]. They would allow for switching between standards, whereas varactors would perform fine frequency tuning within a band. The complete 2.4-GHz band could be covered using this method. The oscillator achieves a phase noise of −123 dBc/Hz at 1 MHz of offset from the carrier at 2.1 GHz for bias current of 6 mA, fulfilling the demanding-mode phase noise requirement. This is shown in Fig. 3.10. By adapting the bias current between 0.5–0.9 mA and 0.5–6 mA, a phase-noise tuning range of 15 and 20 dB has been achieved [19]. This satisfies the requirements of the various standards considered. The image-reject down-converter test chip (comprising the VCO, two mixers, and buffers) consumes around 20 mA in the demanding mode of operation. For the performance of the LNA and baseband circuits the multi-mode image-reject

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EXPERIMENTAL RESULTS FOR THE IMAGE-REJECT DOWN-CONVERTER

FIGURE 3.9

79

Oscillator frequency-tuning curve for a 3-V tuning voltage.

down-converter has the potential to meet the multi-mode receiver specifications in the demanding mode of operation, as summarized in Table 3.5. For the (less stringent) receiver requirements in the other modes of operation, the performance of the quadrature down-converter circuits may be relaxed accordingly. The multi-mode receiver noise and linearity performance required in the moderate and relaxed modes, as listed in Table 3.2, may be satisfied while reducing the power consumption of the oscillator and mixer circuits. Control of the circuits’ bias currents for the different operating modes can be realized by additional baseband circuitry, for example. By trading power consumption for phase noise, operation of the voltage-controlled oscillator may be adapted between different modes: More than a factor of 10 reduction in current consumption suffices to fill the phase noise requirement in the relaxed mode

Ref –70.00dBc/Hz 10.00 dB/

Mkr

1.00617 MHz

–122.96 dBc/Hz

30 kHz

FIGURE 3.10

Frequency Offset

3 MHz

Oscillator phase noise at 1 MHz offset from the 2.1-GHz carrier.

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TABLE 3.5 Measured Image-Reject Down-Converter Performance in the Demanding Mode of Operation Conversion power gain (dB) Noise figure (dB) Input third-order intercept point (dBm) Input second-order intercept point (dBm) Phase noise at 1 MHz offset (dBc/Hz) Image-rejection ratio (dB) LO-to-RF coupling (dB) Power consumption of mixers (mW) Power consumption of oscillator (mW) Power consumption of buffers (mW) Total power consumption (mW)

1.4 13.9 5.5 51 −123 20 −45 30 18 12.6 60.6

of operation [19]. By adapting the bias currents of the mixers, the gain, the noise figure, and the linearity of the image-reject down-converter may be varied [20,44]: the noise and linearity performance requirements in the relaxed mode of operation, as listed in Table 3.2, allow for more than a twofold reduction in the power consumption of the mixers. The experimental multi-mode image-reject down-converter presented in this chapter allows for a reduction of power consumption between the demanding and relaxed modes of operation, from around 60 mW to 30 mW. Compromising between the performance of the low-noise amplifier and baseband circuits, a different set of performance requirements for the quadrature down-converter would result. This may then result in different realizations of the down-converter circuits and different performance/power consumption trade-offs.

3.6

CONCLUSIONS

The coexistence of numerous wireless communication standards requires multi-mode multi-band, and multi-functional terminals. For a multi-functional terminal to be profitable, it has to be cheaper than the simple compound of separate single-mode devices and still achieve good performance with low power consumption. This can be achieved by a large scale of integration, elimination of external components, and extensive reuse of resources. Sharing of functional blocks between different standards in multi-mode wireless terminals using adaptive circuits offers low power consumption, small chip area, and may reduce overall cost. The exploratory multi-mode adaptive image-reject down-converter design presented in this chapter satisfies the requirements of the demanding second- and thirdgeneration standards in the 1.8 to 2.4-GHz band at a current consumption of about 20 mA. It offers more than a twofold saving in power and current consumption between the demanding and relaxed applications, while still maintaining sufficient functionality.

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REFERENCES 1. A. Tasic, W. A. Serdijn, and J. R. Long, Adaptive Low-Power Circuits for Wireless Communications. New York: Springer-verlag, 2006. 2. Radio Frequency and Analog/Mixed-Signal Technologies for Wireless Communications, ITRS road map, 2003 edition. http://www.itrs.com. 3. GSM World. http://www.gsmworld.com/news/press 2005/press05 21.shtml. 4. C. Ambrosio, Global Handset Sales Historical and Forecasts 2002–2011. Tech. Rep. Strategyanalytics, Oct. 2006. http://www.strategyanalytics.com. 5. Telemedicine Information Exchange. http://tie.telemed.org. 6. Intelligent Transportation Systems. http://www.its.dot.gov. 7. Intelligent Mobiles: Context Awareness and Bluetooth. http://www.research.philips.com/ profile/people/researchers/intelligentmobiles.html. 8. http://www.research.philips.com/technologies/projects/ambintel.html. 9. http://www.research.philips.com/technologies/projects/mirrortv.html. 10. A. A. Abidi, G. J. Pottie, and W. J. Kaiser, “Power-conscious design of wireless circuits and Systems,” Proc. IEEE, vol. 88, no. 10, pp. 1528–1545, Oct. 2000. 11. M. Pedram and J. Rabaey, Power Aware Design Methodologies. Dordrecht, The Netherlands: Kluwer Academic, 2002. 12. R. L. Lagendijk, Ubiquitous Communications Research Program Final Program Report. Jan. 2002. http://www.ubicom.tudelft.nl. 13. T. Keller and L. Hanzo, “Adaptive multicarrier modulation: a convenient framework for time–frequency processing in wireless communications,” Proc. IEEE, vol. 88, no. 5, pp. 611–640, May 2000. 14. A. van der Schaaf, K. Langendoen, and R. L. Lagendijk, “Design of an adaptive interface between video compression and transmission protocols for mobile communications,” in Proc. Packet Video Workshop (PV’01), pp. 395–404, Apr. 2001. 15. J. Pouwelse, K. Langendoen, and H. Sips, “Dynamic voltage scaling on a low-power microprocessor,” in Proc. 7th Annual International Conference on Mobile Computing and Networking (Mobicom), pp. 251–259, July 2001. 16. J. Ryynanen, K. Kivekas, J. Jussila, A. Parssinen, and K. Halonen, “A dual-band RF frontend for WCDMA and GSM applications,” IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1198–1204, Aug. 2001. 17. F. Behbahani, J. C. Leete, Y. Kishigami, A. Roithmeier, K. Hoshino, and A. A. Abidi, “An adaptive 2.4GHz low-IF receiver in 0.6 µm CMOS for wideband Wireless LAN,” in Proc. IEEE International Solid-State Circuits Conference (ISSCC’00), pp. 146–147, Feb. 2000. 18. M. Brandolini, P. Rossi, D. Manstretta, and F. Svelto, “Toward multi-standard mobile terminals: fully integrated receivers requirements and architectures,” IEEE Trans. Microwave Theory Tech., vol. 53, no. 3, pp. 1026–1038, Mar. 2005. 19. A. Tasic, W. A. Serdijn, and J. R. Long, “Design of multi-standard adaptive voltage controlled oscillators,” IEEE Trans. Microwave Theory Tech., vol. 53, no. 2, pp. 556–563, Feb. 2005. 20. A. Tasic, S. T. Lim, W. A. Serdijn, and J. R. Long, “Design of adaptive multi-mode RF front-end circuits,” IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 313–322, Feb. 2007.

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21. D. Wang, X. Wang, A. Eshraghi, D. Chang, and P. Bacon, “A fully integrated GSM/ DCS/PCS RX VCO with fast switching auto-band Selection,” in Proc. IEEE Radio Wireless Conference (RAWCON’02), pp. 209–212, Jan. 2002. 22. B. Xia et al., “An RC time constant auto-tuning structure for high linearity continuous-time sigma-delta modulators and active filters,” IEEE Trans. Circuits Syst. I, vol. 51, no. 11, pp. 2179–2188, Nov. 2004. 23. D. Chamla, A. Kaiser, A. Cathelin, and D. Belot, “A Gm -C low-pass filter for zero-IF mobile applications with a very wide tuning range,” IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1443–1450, July 2005. 24. W. Fathelbab and M. B. Steer, “A reconfigurable bandpass filter for RF/microwave multifunctional systems,” IEEE Trans. Microwave Theory Tech., vol. 53, no. 3, pp. 1111–1116, Mar. 2005. 25. M. R. Miller and C. S. Petrie, “A multibit sigma-delta ADC for multimode receivers,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 475–482, Mar. 2003. 26. S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation. Piscataway, NJ: IEEE Press, 1997. 27. J. Ryynanen, K. Kivekas, J. Jussila, L. Sumanen, and A. P. K. A. I. Halonen, “A singlechip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA,” IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 594–602, Apr. 2003. 28. Digital Cellular Communication System (Phase 2), Radio Transmission and Reception. E. . ., G. ., version 5.4.1, European Telecommunications Standards Institute, 1997. 29. Third-Generation Partnership Project (3GPP), TS 25.101 UE Radio Transmission and Reception (FDD), vol. 3.0.1. 2000. 30. Wireless Local Area Network, IEEE 802.11 Working Group on Wireless Local Area Networks, 1999.http://standards.ieee.org/getieee802/download/802.11b-1999 Cor12001.pdf. 31. B. SIG, Specification of the Bluetooth System, Feb. 2001. http://www.bluetooth.com. 32. E. . 175-2, Digital Enhanced Cordless Telecommunications (DECT); Common Interface (CI); Part 2: Physical Layer (PHL), European Telecommunications Standards Institute, 2003. 33. J. Rudell, An Integrated GSM/DECT Receiver: Design Specifications, UCB Electronics Research Laboratory Memorandum UCB/ERL M97/82, Technical Report, 1998. 34. O. K. Jensen, T. E. Kolding, C. R. Iversen, S. Laursen, R. V. Reynisson, J. H. Mikkelsen, E. Pedersen, M. B. Jenner, and T. Larsen, “RF receiver requirements for 3G W-CDMA mobile equipment,” Microwave J., 2000. 35. M. Steyaert, B. D. Muer, P. Leroux, M. Borremans, and K. Mertens, “Low-voltage lowpower CMOS-RF transceiver design,” IEEE Trans. Microwave Theory Tech., vol. 50, no. 1, pp. 281–287, Jan. 2002. 36. A. Tasic, W. A. Serdijn, J. R. Long, and D. Harame, “Resonant-inductive degeneration for a fourfold phase-noise improvement of a 5.7GHz band voltage-controlled oscillators,” in Proc. Bipolar/BiCMOS Circuits and Technology Meeting (BCTM 2005), pp. 236–239, Oct. 2005. 37. A. Tasic, W. A. Serdijn, and J. R. Long, “Adaptivity of voltage-controlled oscillators: theory and design,” IEEE Trans. Circuits Syst. I, vol. 52, no. 5, pp. 894–901, May 2004.

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38. A. Joseph et al., “A 0.18 µm 120/100GHz ( f T / f MAX ) HBT and ASIC-compatible CMOS using copper interconnect,” in Proc. Bipolar/BiCMOS Circuits and Technology Meeting (BCTM’01), pp. 143–146, Oct. 2001. 39. T. S. D. Cheung, J. R. Long, K. Vaed, R. Volant, A. Chinthakindi, C. M. Schnabel, J. Florkey, Z. X. He, and K. Stein, “Differentially-shielded monolithic inductors,” in Proc. IEEE Custom Integrated Circuits Conference (CICC’03), pp. 95–98, Sept. 2003. 40. J. Janssens and M. Steyaert, CMOS Cellular Receiver Front-End. Dordrecht, The Netherlands: Kluwr Academic, 2002. 41. F. Friis, “Noise figure of radio receivers,” Proc. IRE, vol. 32, no. 7, pp. 419–422, July 1944. 42. B. Razavi, RF Microelectronics. Upper Saddle River, NJ: Prentice Hall, 1998. 43. D. Manstretta, F. Gatta, P. Rossi, and F. Svelto, “A 0.18 µm CMOS direct-conversion receiver front-end for UMTS,” in Proc. IEEE International Solid-State Circuits Conference (ISSCC’02), pp. 240–241, Feb. 2002. 44. B. Gilbert, “The micromixer,” IEEE J. Solid-State Circuits, vol. 32, no. 9, pp. 1412–1423, Sept. 1997. 45. P. Wambaq and W. Sansen, Distortion Analysis of Analog Integrated Circuits. Norwell, MA: Kluwer, 1998. 46. D. Manstretta, M. Brandolini, and F. Svelto, “Analysis and optimization of IIP2 in CMOS direct downconverters,” in Proc. IEEE Custom Integrated Circuits Conference (CICC’02), pp. 243–247, Sept. 2002. 47. D. M. W. Leenaerts, C. S. Vaucher, H. J. Bergveld, M. Thompson, and K. Moore, “A 15mW fully integrated I/Q synthesizer for Bluetooth in 0.18 µm CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1155–1162, July 2003.

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Precise Delay Alignment Between Amplitude and Phase/Frequency Modulation Paths in a Digital Polar Transmitter KHURRAM WAHEED and ROBERT BOGDAN STASZEWSKI Texas Instruments, Dallas, Texas

4.1

INTRODUCTION

Modern complex envelope modulation schemes such as EDGE, WCDMA, extendeddata-rate Bluetooth (BT-EDR), WLAN, LTE, and WiMAX impose strict performance requirements on radio-frequency (RF) transceivers. For digital polar transmitters, typical stringent performance requirements exist for modulated close-in and far-out spectra, adjacent channel power/leakage ratio (ACPR/ACLR), error vector magnitude (EVM), phase trajectory error (PTE), and percentage power in-band. Implementation of such modern communication standards using the digital polar modulation approach is possible only if precise alignment can be maintained between the amplitude modulation (AM) and phase/frequency modulation (PM/FM) paths. This is an arduous task, as both the amplitude and phase (or frequency) paths have different modulation bandwidths and comprise digital components that need to operate on different clock domains for power efficiency, while complying with the stringent performance requirements. The front end comprises digitally controlled analog components, such as a digitally controlled oscillator (DCO) and a digitally controlled pre-power amplifier, which together transform the digital signals to the continuous-time domain with high precision. Figure 4.1 is an overview of key circuits of a single-chip polar transceiver radio. At the heart lies a digitally controlled oscillator (DCO) [1,2], which deliberately avoids analog tuning controls. Fine frequency resolution is achieved through highspeed
 dithering [3] of its varactors. As first suggested in [4], a digital logic built around the DCO realizes an all-digital PLL that is used as a local oscillator for both the transmitter (TX) and receiver (RX). The polar transmitter architecture utilizes Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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Xtal Dither Amplitude modulation

Σ∆

FREF

Internal DRP Processor

Digital Baseband Processor

DCXO

SRAM

c04

Front-end Module • 2-watt PA • T/R switch • RX SAW filters

DPA Σ∆ Digital logic

Processor clock

DCO TDC

LO clock

TX

Dividers

RX Digital logic

Power Management (PM)

Battery Management

A/D

Discrete time CH

iRF Current sampler

LNA +TA

RF in

RF Built-in Self Test (RF-BIST)

VBAT

FIGURE 4.1 Single-chip polar transceiver radio with an all-digital local oscillator and c 2008 IEEE.) transmitter and a discrete-time receiver. (Copyright


the wideband direct frequency modulation capability of the ADPLL and a digitally controlled pre-power amplifier (DPA) for the power ramp and amplitude modulation. The DPA operates in near-class-E mode and uses an array of nMOS transistor switches to regulate the RF amplitude. Fine amplitude resolution is achieved through highspeed
 dithering of the DPA nMOS transistors. The DPA is followed by a matching network and an external front-end module, which comprises a power amplifier (PA) and a transmit/receive switch for the common antenna. The receiver employs a discrete-time architecture [5] in which the RF signal is sampled directly at the Nyquist rate of the RF carrier and processed using analog and digital signal processing techniques. The transceiver is integrated with a dedicated ARM family processor and SRAM memory. The frequency reference (FREF) is typically generated on-chip by a digitally controlled crystal oscillator (DCXO). The integrated power management is connected to an external battery management circuit that conditions and stabilizes the supply voltage. The power management consists of multiple low-dropout (LDO) voltage regulators that provide internal supply voltages and also isolate the supply noise between circuits, especially protecting the DCO. The RF built-in self-test (BIST) performs autonomous phase noise and modulation distortion testing as well as various loopback configurations for bit-error-rate measurements. Almost all the clocks on this system on a chip are derived from and are synchronous

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87

to the RF oscillator clock. This helps to reduce susceptibility to the RF noise and spurious tones generated through the use of multiple clocks for the massive digital logic. For the transmitter, which is the primary focus of this chapter, the architecture chosen is polar and it implements the amplitude and phase modulations in separate paths. Transmitted symbols generated in the digital baseband (DBB) processor are first pulse-shape filtered in the Cartesian coordinate system. The filtered in-phase (I) and quadrature (Q) samples are then converted through a CORDIC algorithm into amplitude and phase samples of the polar coordinate system. The phase is then differentiated to obtain frequency deviation. The polar signals are subsequently conditioned through signal processing to increase the sampling rate sufficiently in order to reduce the quantization noise density and lessen the effects of the modulating spectrum replicas.

4.2

RF POLAR TRANSMITTER IN NANOSCALE CMOS

A new paradigm facing analog and RF designers of deep-submicron- or nanometerscale CMOS circuits was formulated in [1]: In a deep-submicron- or nanometer-scale CMOS process, time-domain resolution of a digital signal edge transition is superior to voltage resolution of analog signals. A successful design approach for highly integrated RF circuits in this environment would exploit the paradigm by emphasizing the following: r Fast switching characteristics or high f T (20 ps and 250 GHz in 45-nm CMOS, respectively) of MOS transistors: high-speed clocks and/or fine control of timing transitions r High density of digital logic (1 Mgates/mm2 ) and SRAM memory (4 Mb/mm2 ), which make digital functions and assistant software extremely inexpensive r Small-device geometries and precise device matching made possible by the fine lithography while avoiding the following: r Biasing currents commonly used in analog designs r Reliance on voltage resolution with ever-decreasing supply voltages and increasing noise and interferer levels r Nonstandard devices that are not needed for memory and digital circuits, which constitute the majority of the silicon die area The resulting architecture will probably be more robust by producing a low phase noise and spurious degradation of the transmitter chain and low noise figure of the receiver chain in the face of millions of active logic gates on the same silicon die, as proven in [6] and [7], respectively, for 90-nm CMOS. Additionally, the new architecture would be highly reconfigurable with analog blocks that are controlled by software to guarantee the best achievable performance and parametric yield. Another

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Digital signal processing symbols

I/Q pulseshape filtering

I Q

Amplitude

NA

Cordic and polar signal processing

DFC NF

DRAC Modulator

DCO

RF out Modulator

Frequency DPA

FIGURE 4.2 Polar transmitter based on a digitally controlled oscillator circuit and a digitally controlled power amplifier circuit. For simplicity, the all-digital PLL around the DCO is not shown.

benefit of the new architecture would be easy migration from one process node to the next without significant rework [8,9]. Figure 4.2 illustrates an application of the new paradigm to an RF wireless transmitter performing an arbitrary quadrature amplitude modulation (QAM). The low cost of digital logic allows for the use of sophisticated digital signal processing techniques. The tiny, well-matched devices allow for precise and high-resolution conversions from digital to analog domains. The use of ultrahigh-speed clocks (i.e., high oversampling ratios) can eliminate the need for subsequent dedicated reconstruction filtering of spectral replicas and switching transients, so that only the natural filtering of an oscillator (1/s due to the frequency-to-phase conversion), matching network of power amplifier, and antenna filter are relied upon. Since the converters utilize DCO clocks that are of high spectral purity, the sampling jitter is very small. The sampling jitter is not significantly affected by modulation, since the jitter due to modulation is not greater than the oscillator thermal jitter. The conversion functions covered in this chapter are phase/frequency and amplitude modulations of an RF carrier realized using DCO and digitally controlled power amplifier (DPA) circuits, respectively. They are digitally intensive equivalents of the conventional voltage-controlled oscillator (VCO) and power amplifier (PA) driver circuits. Due to the fine feature size and high switching speed of modern CMOS technology, the respective digital-to-frequency conversion (DFC) and digital-to-RF-amplitude conversion (DRAC) transfer functions could be made very linear and of high dynamic range. The frequency deviation output signal is fed into the DCO-based N F -bit DFC, which produces the phase-modulated (PM) digital carrier: yPM (t) = sgn(cos(ω0 t + θ [k]))

(4.1)

where sgn(x) = 1 for x ≥ 0 and sgn(x) = −1 for x < 0, ω0 = 2π f 0 is the angular RF carrier frequency,
t and θ [k] is the modulating baseband phase of the kth sample. The phase θ (t) = −∞ f (t) dt is an integral of frequency deviation, where t = kT0 , T0 being the sampling period.

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The amplitude modulation (AM) signal controls the envelope of the phasemodulated carrier by means of the DPA-based N A -bit DRAC. Higher-order harmonics of the digital carrier are filtered out by a matching network so that the sgn(·) operator is dropped. The composite DPA output contains the RF output spectrum desired: yRF (t) = a[k] cos(ω0 t + θ [k])

(4.2)

where a[k] is the modulating baseband amplitude of the kth sample. The amplitude is represented in N A = I A + FA bits, I A and FA being integer and fractional amplitude bits, respectively. Despite their commonalities, there are important differences between the two conversion functions. Due to the narrowband nature of the communication system, the DFC operating range is small but has a fine resolution. The DRAC operating range, on the other hand, is almost full scale, but not as precise. In addition, the phasemodulating path features an additional 1/s filtering caused by the frequency-to-phase conversion of the oscillator. Of course, the signal processing and delay between the AM and PM paths should be matched; otherwise, the recombined composite signal will be distorted. Fortunately, the matching invariability to the process, voltage, and temperature changes is guaranteed by the clock-cycle accurate characteristics of digital circuits. The group delay of DCO and DPA circuits is relatively small (tens of picoseconds, due to the high f T value of the deep-submicron CMOS devices) in comparison to the tolerable range (tens of nanoseconds for EDGE). The DFC and DRAC are key functions of an all-digital transmitter, which does not use any current biasing or dedicated analog continuous-time filtering in the signal path. To improve matching, linearity, switching noise, and operational speed, the operating conversion cells (bit to frequency or RF carrier amplitude) are realized mainly as unit weighted. Due to the excellent device-matching characteristics in a deep-submicron CMOS process, it is relatively easy to guarantee 7-bit conversion resolution in one design iteration cycle without resorting to elaborate layout schemes. The DFC and DRAC architectures are presented below. Spectral replicas of the discrete-time modulating signal appear at the DCO and DPA inputs at integer multiplies of the sampling rate frequency f s , here equal to the reference frequency f R from a crystal oscillator, as shown in Fig. 4.3. They

Sf/a(ω)

sinc

2

Replicas

Signal

Attenuated replicas

0

2π • fR

2π • 2f R

ω

FIGURE 4.3 Spectral replicas of the modulating signal and their sinc2 filtering through zero-order hold. Additional 6-dB/octave filtering from S f (ω) to Sφ (ω) is provided inherently by the DCO.

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are attenuated through multiplication of the sinc2 function due to the zero-order hold of the DCO/DPA input. The frequency spectrum S f (ω) replicas are further attenuated by 6 dB/octave through the 1/s operation of the oscillator, to appear finally at the RF output phase spectrum Sφ (ω). The sampling rate of f R = 26 MHz is high enough for the replicas to be attenuated sufficiently, thus making the RF signal undistinguishable from that created by conventional transmitters with continuoustime filtering at baseband. 4.3

AMPLITUDE AND PHASE MODULATION

For the simplified polar transmitter shown in Fig. 4.4, the pulse-shaping filter contains separate I and Q filters followed by a CORDIC algorithm that converts to the polar-domain phase and amplitude format. The pulse-shaping sampling rate is typically derived from the reference clock. The output of the pulse-shaping filter is then interpolated to smoothen both the amplitude and phase modulating signals. The phase output of the CORDIC is adjusted for AM-PM distortions in the DPA and the external PA and is then differentiated to fit the I F + FF bits of the frequency command word (FCW) format after interpolation M F to the DCO direct modulation rate of the ADPLL input. During the modulation stage, the ADPLL drives the DCO varactors with NDCO raw integer bits and S D F
-dithered raw fractional bits. The amplitude output is scaled for the appropriate power level as well as mapped to the step size of the digitally controlled power amplifier (DPA). The amplitude is then AM-AM-predistorted followed by interpolation M A to the appropriate injection rate for the DPA. The (I A + FA )-bit amplitude control word (ACW) is then converted to the N D P A -bit integer unit-weighted format of the DPA. Another dedicated bank of DPA transistors also undergoes a high-frequency third-order
 modulation to IA

Amplitude Modulation

BB Data

AM-AM Predistortion

MA

I A+FA

Pulse Shaping Filter

Amplitude CKVDz CKVDz, z=16, 32 Control Word or more (ACW) DIV

FA

CKVDz

NDPA

Encoder and DEM

CORDIC + Polar Signal Processing

chain

Digital Σ∆ modulator

SDA

CKVDy, y=4 or 8

DIV chain

Phase Modulation

AM-PM Predistortion + PM FM CKVDz

MF

Frequency Command Word (FCW)

CKVDx, x=1 or 2

IF FREF

ADPLL Loop CKVDz

CKV

I F+FF

NDCO Oscillator CKVDz Tuning Word (OTW)

FF

DIV chain

Encoder and DEM

Digital Σ∆ modulator

SDF

DCO

RF out Variable clock (CKV)

CKVDx

FIGURE 4.4

Integer

Gain Normalization

Fractional (dithered)

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Amplitude and phase modulation paths of the polar transmitter.

DPA

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enhance the amplitude resolution (by S D A bits) and to achieve noise spectral shaping. Both the DCO and DPA controllers also perform dynamic element matching (DEM) to enhance the time-averaged linearity due to possible device mismatch. The polar mechanism described above is employed for complex modulation schemes such as EDGE, WCDMA, and beyond. However, in the GSM mode, the CORDIC circuit is bypassed and a single pulse-shaping filter is used to perform frequency modulation according to Gaussian minimum shift keying (GMSK) format. The AM path is engaged only temporarily to ramp the output power to a desired level and then remains fixed throughout the payload. For a good overview of polar transmitters, see [10–12]. Satisfactory performance of a polar transmitter relies on the proper delay match between phase and amplitude modulation signals from the CORDIC input to the DPA output (called small-signal polar TX) or the PA output (called large-signal polar TX). The phase modulation is accomplished by injecting the phase information into the ADPLL, whereas the amplitude modulation path is quite different, further complicated by the need for power control and spectral replica mitigation. To reproduce the frequency-translated source I/Q data at the antenna port, such path delays in phase and amplitude paths of the transmitter must be matched properly [9,13]. 4.3.1

Alignment Accuracy Between Amplitude and Phase Modulation Paths

Beyond the CORDIC, the amplitude and phase modulation paths are separate signal processing paths. Desirable transmitter performance characteristics can be achieved only if the two distinct paths are tuned properly and perfect alignment can be achieved between the two paths. For complex modulation schemes that utilize both of these modulation paths in a polar transmitter, mostly symmetric signal processing operations are done at lower clock rates to ensure by design that the alignment can be maintained between the two paths. However, for high-speed transmitter operations, the two paths may experience misalignment due to the need to perform asymmetric operations for accurate amplitude and phase reconstruction. Second, even for the similar clock rates used in the two paths, the clock tree delay for each path is also independent and thus introduces additional alignment skews. Third, the digital-to-analog interfaces of both the amplitude and phase (or frequency) modulation paths involve certain analog delays, which are a function of process, voltage, and temperature. A confluence of several of these factors necessitates that the alignment requirements for each modulation scheme be analyzed and appropriate design measures taken to ensure that the optimal alignment accuracy can be achieved. This timing alignment precision (and granularity) between the amplitude and phase paths required for a 2.5G EDGE is on the order of a few nanoseconds (<10 ns) [13]. For WCDMA and the 4G modulations, this AM/PM alignment needs to be better than a nanosecond or severe degradation will occur in the critical transmitter performance parameters. Below we analyze the alignment accuracy needed for EDGE and WCDMA modulations. 4.3.1.1 EDGE Modulation Time alignment between amplitude and phase for EDGE can be done in several stages. A coarse time alignment circuit is placed after the CORDIC with a resolution of CKVD256 (CKV divided by 256), with CKV being

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Effect of time misalignment between amplitude and phase on EDGE spectrum points: 400KHz, 500KHz and 600KHz, averaged over 30KHz around each point −55 −60 −65 −70 −75

dB

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−80 −85 −90

400KHz point 500KHz point 600KHZ

−95 −100

0

1

2

3

4

5

Time misalignment, steps of 1ns

6

7 x

10−8

FIGURE 4.5 Effect of time misalignment between amplitude and phase on a modulated EDGE spectrum.

the channel frequency for the approximately 2-GHz high band (HB), and twice the channel frequency in the approximately 1-GHz low band (LB). A finer time alignment circuit follows in the CIC interpolation block after each interpolator stage. By doing that we have a progressively finer resolution all the way down to the CKVDy (CKV divided by y) clock rate, which is the integer data injection rate into the DCO and the DPA. Typically, this alignment is accurate up to a few nanoseconds. Further alignment mechanisms are discussed below. Figure. 4.5 shows various frequency offset points on the close-in EDGE spectrum with a time delay between the amplitude and phase swept from 0 to 60 ns. Figure 4.6 shows the close-in spectra at specific time mismatches. 4.3.1.2 WCDMA Modulation For WCDMA, the CORDIC typically runs at a rate that is significantly higher than that for EDGE. This is needed to preserve the much wider modulation signal bandwidth. This results in much higher frequency excursion (due to possible high-speed 180o phase transitions) as well as faster amplitude changes [due to a higher peak-to-average ratio (PAR)]. Consequently, there is an increase in sensitivity of WCDMA modulation reconstruction to the delay between the amplitude and phase modulation paths. Simulated analysis results for WCDMA are presented in Figs. 4.7 and 4.8.

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Effect of time misalignment between phase and amplitude on EDGE spectrum 0 Perfect alignment 6.4ns misalignment 13.8ns misalignment 19.2ns misalignment 25.6ns misalignment

−20

−40

−60 dB −80

−100

−120

−140 0

1

2

3

4

5

6

7

FIGURE 4.6

8 x 105

Frequency

Modulated EDGE spectrum under different time mismatches.

10

8

6

4

2

0

-2

-4

-6

-8

5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -1 0

Change in EVM [%]

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AM-PM Delay [in ns]

FIGURE 4.7 WCDMA EVM degradation as a function of time mismatch between amplitude and phase modulation paths.

4.3.2 Alignment Accuracy Between Integer and Fractional Bits of Amplitude and Phase Modulation In this section we present the investigation results for the impact of integer and fractional alignment of amplitude and phase in a polar transmitter. As WCDMA is more sensitive to such artifacts, the results below are based on WCDMA polar

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20 18 16 14 12 10 8 6 4 2 0

10

8

6

4

2

0

-2

-4

-6

-8

ACLR1 ACLR2

-1 0

Change in ACLR [dB]

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AM-PM Delay [in ns]

FIGURE 4.8 WCDMA ACLR(s) degradation as a function of time mismatch between amplitude and phase modulation paths.

TX simulation results. These misalignments may be introduced by the fact that the integer part of each operates (see Fig. 4.4), at the CKVDy clock rate, whereas the
 modulators for the fractional representation need a high oversampling ratio (OSR) and hence use a much higher clock CKVDx. 4.3.2.1 Alignment Requirement Between Amplitude Integer and Fractional Bits It is observed that the amplitude integer and fractional subword misalignment causes spectral regrowth, which results in a degradation of the adjacent channel leakage (see Fig. 4.9). However, as shown in Fig. 4.10, WCDMA TX EVM is not very sensitive to the amplitude integer/fractional timing mismatch. The ACLR degradation

16 14 Change in ACLR [dB]

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ACLR1 ACLR2

12 10 8 6 4 2 0 0

1

2

3

4

5

AM Fraction Delay w.r.t AM Integer [ns]

FIGURE 4.9 WCDMA ACLR(s) degradation as a function of time mismatch between amplitude integer and fractional bits.

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AMPLITUDE AND PHASE MODULATION

95

0.15 0.13 0.11 0.09 0.07 0.05 0.03 0.01 -0.01 -0.03 -0.05 0

1 2 3 4 5 AM Fraction Delay w.r.t AM Integer [ns]

FIGURE 4.10 WCDMA EVM degradation as a function of time mismatch between amplitude integer and fractional bits.

indicates that the nanosecond alignment accuracy is needed for good TX performance parameters. 4.3.2.2 Alignment Requirement Between Phase Integer and Fractional Bits WCDMA TX performance is quite sensitive to the timing mismatch between integer and fractional bits. Such a misalignment has a direct impact on the modulated phase noise of the DCO. This severely degrades the WCDMA spectrum. The impact on EVM, ACLR(s), and TX-RX noise is shown in Figs. 4.11 to 4.13, respectively. In fact, the sharp degradation in the ACLR(s) and TX noise contribution in the RX band warrants that a precise time alignment for the phase integer and fractional bit is a requisite for requisite WCDMA TX operation. 3.5 3 Change in EVM [%]

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2.5 2 1.5 1 0.5 0 0

1 2 3 4 5 6 7 8 9 PM Fraction Delay w.r.t PM Integer [ns]

10

FIGURE 4.11 WCDMA EVM degradation as a function of time mismatch between phase integer and fractional bits.

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40 Change in ACLR [dB]

35 30 25 20 15 ACLR1 ACLR2

10 5 0 0

1 2 3 4 5 6 7 8 9 PM Fraction Delay w.r.t PM Integer [ns]

10

FIGURE 4.12 WCDMA ACLR(s) degradation as a function of time mismatch between phase integer and fractional bits. Change in TX- RX Noise [dBc/Hz]

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30 25 20 15 10 5 0 0

1 2 3 4 5 6 7 8 9 PM Fraction Delay w.r.t PM Integer [ns]

10

FIGURE 4.13 WCDMA RX-TX performance degradation as a function of time mismatch between phase integer and fractional bits.

4.4 MECHANISMS TO ACHIEVE SUBNANOSECOND AMPLITUDE AND PHASE MODULATION PATH ALIGNMENTS In this section, some of the special techniques used to achieve the subnanosecond time alignment between the amplitude and phase modulation paths in a polar transmitter for 2G/2.5G/3G and beyond are described below. In fact, the method described in this work is applicable to any signal that has been split into multiple independent paths and finally, recombined again to reconstruct the original but frequency-translated signal. To reproduce the exact signal when all the independent paths are recombined, every signal path needs to be delay aligned (i.e., each must have the same exact amount of delay before recombination); otherwise, the end results will be distorted and of not much use.

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The presented approach is a combination of design elements and calibration procedure to achieve the desired goal of subnanosecond delay. In analog-centric approaches, which are applicable to the conventional analog I/Q transmitters, the processing delays per element are relatively small, but the delay alignment varies significantly over process, voltage, and temperature. In digital polar transmitters, however, the delay alignment scheme presented has fully digital controls with precisely known and predictable delay settings of the amplitude and phase/frequency modulation paths. Furthermore, the scheme is amenable to dynamic calibration using either an embedded processor or other on-chip computational resources. In short, better than a nanosecond alignment accuracy is achieved by accounting meticulously for processing delays in different digital modules and addition of programmable delay elements across several clock domains: CKVDz, CKVDy, CKVDx, and CKR (retimed reference), to name a few. Furthermore, care has been exercised in the design of clock hand-offs between different clock domains so as to preserve the existing alignment between the amplitude and phase/frequency modulation paths. 4.4.1

Multiple Clock Domain Delay Alignment Scheme

Figure 4.14(a) is a block diagram of the proposed circuit arrangement for the use of two different clock domains for the control of delay in a signal path. These two clocks may or may not be derived from a single master clock source. The sample rate conversion technique used between the flip-flops (FFs) placed in the two clock domains can be chosen based on the spectral and signal integrity needs of the signal path. As needed, a sample rate converter (SRC) may use simple zero-order hold, linear or second-order interpolation, or third-order Lagrange (or cubic-spline) interpolation/decimation schemes. However, note that in case the clk hi and clk lo clocks are completely asynchronous to each other, the accuracy of sample rate conversion will be a limited by the accuracy with which their phase and edge timing relationships can be determined. In this particular case, the two clocks used for clk lo and clk hi are CKVDz and CKVDy, respectively. As shown in Figs. 4.4 and 4.15, these clocks are derived from the same source (an RF oscillator output clock, CKV, in this case), the possibility of signal degradation is virtually avoided, due to the simplified and causal estimation of the timing relationship between these two clocks. Furthermore, specific to a polar transmitter, the clock rate typically increases from the transmitter’s baseband I/Q input to the high-speed RF clock rate recombination of amplitude and phase. Therefore, in this case we utilize the circuit of Fig. 4.14(a), where the SRC is represented by a linear interpolation of the data rate from the CKVDz to the CKVDy clock domain. The scheme proposed above has been used as an alignment and data hand-off building block in Fig. 4.15 to create a fully digital delay alignment scheme. This circuit has a precisely known and predictable delay setting based on the two clock rates, chosen as CKVDz and CKVDy, the number of flip-flops (FFs) employed in each clock domain, and the linear interpolation (sample rate conversion) scheme chosen for the data hand-off.

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clk_lo

Delay Nyx

clk_hi

Delay Signal Output

P Flops

Q Flops

FF

FF

Sample Rate Conversion by

clk_lo

clk_lo

clk_hi/clk_lo

Signal Input

Signal Output

FF

FF

clk_hi

clk_hi

(a) Signal Input

clk_hi

Delay

clk_lo

Delay

Nyx

Signal Output

P Flops

Q Flops

FF

FF

Sample Rate Conversion by

clk_hi

clk_hi

clk_lo/clk_hi

Signal Input

Signal Output

FF

FF

clk_lo

clk_lo

(b)

FIGURE 4.14 Digital delay adjust circuit, consisting of registers in two clock domains and use of a sample rate converter between the two clock domains: (a) signal is propagating from a slow clock domain to a faster clock domain with possible interpolation in the SRC; (b) signal is propagating from a faster clock domain to a slower clock domain with possible decimation in the SRC.

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SUBNANOSECOND AMPLITUDE AND PM PATH ALIGNMENTS IA

CORDIC + Polar Signal Processing

Nyx

I A+FA

Encoder and DEM

Amplitude CKVDy CKVDxa Control Word (ACW)

FA

Digital Σ∆ modulator CKVDxa

SDA Clock Module

DIV

CKVDz, z=16, 32 or more CKVDxq

AM-PM Predistortion + FM PM

Phase Modulation

NDPA

R E G

CKVDy, y=4 or 8

CKVDxa

DIV

TDL

CKVDz

Delay

CKVDy

Delay

chain

Fractional (dithered)

MF

DIV chain

TDL1

CKVDx, x=1 or 2 CKVDz

chain

Nyx Exception Handler

Frequency Command Word (FCW)

FREF

IF

IF +FF

ADPLL Loop CKVDz

CKV

CKVDy

Encoder and DEM

R E G

NDCO

CKVDxq

QSync

I+ Q+ IQ-

Oscillator CKVDy CKVDx Tu ning Word (OTW)

RF out

SD F

FF

Digital Σ∆ modulator

DCO

Integer

CKVDz Pulse Shaping Filter

CKVDy

BB Data

Delay

AM-AM Predistortion

Amplitude Modulation

Delay

Gain Normalization

CKVDz

c04

Dividers + Quad switch

Variable clock (CKV)

DPA

CKVDx

FIGURE 4.15 WCDMA TX block diagram with precise delay alignment between frequency and amplitude modulation (both integer and fractional components) as well as the quad-switchbased exception-handling mechanism. Note the location of tapped delay lines in the high-speed clocks used by amplitude and quad switch paths.

Figure 4.15 is a block diagram of a WCDMA-compliant polar transmitter using a hybrid polar/Cartesian transmit modulator. This hybrid architecture restricts the amount of phase modulation done by the ADPLL to be less than ±45o . The sharper phase modulation transitions are mitigated by switching between the four quadrature output phases of the DCO. In the transmitter architecture of Fig. 4.15, the phase modulation output of CORDIC is split using exception handling between the ADPLL and the quad switch path. The exception handler operates by computing the delta phase in the CKVDz domain and then splitting it between the quad switch and ADPLL, as in Table 4.1. “Quad Out” is the control for the quad switch, and “Phase Out” is the phase modulation that is fed to the ADPLL as an equivalent frequency modulation. For the polar transmitter with exception handling in Fig. 4.15, the modulation accuracy for complex wide-modulation bandwidth standards such as WCDMA, TABLE 4.1 Phase Exception-Handling Scheme Delta Phase θi n +45 · · · + 135 +135o · · · + 225o −45o · · · − 135o −45o · · · + 45o o

o

Quad Out

Phase Out

Qout (prev) + 1 Qout (prev) + 2 Qout (prev) − 1 Qout (prev)

θin − 90o θin − 180o θin + 90o θin

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BT-EDR, and 4G, in terms of EVM, ACLRs, and far-out noise, to name a few, can be achieved only if precise delay alignment between the phase modulation path in ADPLL, the switching control of quadrature-modulated DCO phases, and the amplitude path alignments can be achieved meticulously. Evidently, the signal processing done on the amplitude and phase modulation paths is asymmetric and the proposed digital delay adjust blocks can be tuned to achieve the requisite delay alignment between all the modulation paths by accounting for digital group delay of each digital signal processing block in each path. Furthermore, a very precise nanosecond range delay is achieved by ensuring that for both the amplitude and phase, integer and fractional components are aligned in the high-speed CKVDx clock domain. For example, in case CKVDx is chosen to be the CKVD2 clock (approximately 1 GHz), the delay alignment accuracy between these different paths will be less than 1 ns. To ensure such tight compliance: 1. CKVDx-based registers are introduced as the clock domain for the last stage of registers on integer components of AM and PM signals, which are otherwise handled in the CKVDy domain. 2. The CKVDx clock used for this final set of registers can be precisely the same clock used for both AM and FM paths. This is done to mitigate the effects of possible independent clock tree delays in AM and FM paths. 3. Alternatively, the CKVDx used for the amplitude and phase quad-switch paths (i.e., CKVDxa and CKVDxq, respectively) are adjusted for the physical analog delay in the DCO with its divider tree and DPA, respectively. This is discussed in more detail below. 4.4.2

High-Speed Clock Alignment Using Buffer Delays

To adjust the phase relationship between the highest-speed clocks used in each path, a set of buffer delays can be used to achieve a very fine adjustment at the picosecond level. Figure 4.16 shows a simplified tapped delay line (TDL) comprised of a set of m buffers, each with a τ B delay (in picosecond), followed by an “analog” multiplexer, which can be digitally controlled using the AMUX CTL digital (memory) register.

Signal Input

B

B

B

B1

B2

Bm-1

Bm

ANALOG MUX

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B0

Signal Output

40 ~ 50 ps

AMux_ctl(log2(m)-1:0)

FIGURE 4.16 A tapped delay line consists of analog buffer stages with 40 to 50 ps of delay. The number of buffers to be used can be selected by the digital control word AMUX CTL.

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The buffer B0 is a fixed buffer, which is always used to ensure that the TDL delay is not skewed due to excessive loading on the switchable buffers. For the polar transmitter with the exception-handling mechanism, a TDL such as that shown in Fig. 4.16 can be used to compensate for the analog propagation and settling delays in DCOs, dividers, quad switches, buffers, level shifters, and DPAs. Each step in the tapped delay line consists of a single buffer delay, which can be digitally controlled. This makes it possible to achieve finer than CKV (i.e., sub-nanosecond) delay alignment among all the constituent modulation paths. Figure 4.15 shows one embodiment in which separate TDLs are introduced for the adjustment of the analog delays between the CKVDx used for DCO fractional modulation to the appropriate CKVDx used for the amplitude and phase quad-switch paths: CKVDxa and CKVDxq, respectively. The adjustment between CKVDx and CKVDxq is to account for the analog propagation delays in the DCO and the quad switch. The DCO clock is followed by high-speed clock dividers that divide the DCO clock running on a multiple of the channel frequency down to the high band (HB) or low band (LB, where LB = HB/2 in terms of frequencies) clock rate. These dividers have a response time that depends on their topology, the threshold set by the circuit biasing, and so on. Note that both the delays described above are functions of process, voltage, and temperature (PVT). Consequently, the adjustment in CKVDxa is done to maximize the power-added efficiency in the DPA. This is achieved by ensuring that the DCO phase-modulated clock feeding to the DPA is correctly aligned to the amplitude modulation data feed to the DPA, which controls the number of devices enabled in the DPA. For more details, see [19]. As described above, TDLs are used to account for mostly “analog” propagation delays, which are a function of PVT and frequency. If needed, a calibration scheme can be developed to use a memory look-up table to adjust the TDL delays based on the on-chip temperature and voltage monitors. Figure 4.17 shows an alternative embodiment in which the TDL is placed between the DCO and the DPA. In this scheme it has been assumed that the analog propagation delay between the ADPLL modulation and the quad switch is negligible. The purpose of the TDL in this scheme is primarily to maximize the power-added efficiency (PAE) in the DPA.

4.5 PRECISE ALIGNMENT OF MULTI-RATE DIRECT AND REFERENCE POINT DATA MODULATION INJECTION IN ADPLL The all-digital phase-locked loop (ADPLL) of the digital RF processor (DRP) is described in detail in the literature [1,5,6,16]. The stringent modulation mask and spectral compliance requirements of 2.5G (EDGE), 3G (WCDMA), and beyond impose requirements that dictate the CORDIC rate in a polar transmitter. Further, to minimize the spectral regrowth due to the spectral replicas, modulation injection needs to happen at a significantly higher rate then that of the typical reference frequency clock (8 to 52 MHz) used for RF frequency synthesis. Merely running the ADPLL at a rate higher than the reference clock rate is both pointless and wasteful since

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PRECISE ALIGNMENT BETWEEN AM AND PM/FM PATHS IA

CKVDz Pulse Shaping Filter

Nyx

CKVDz

BB Data

Delay

AM-AM Predistortion

Amplitude Modulation

CORDIC + Polar Signal Processing

Delay

Gain Normalization

I A+FA

Encoder and DEM

NDPA

R E G

Amplitude CKVDy CKVDx Control Word (ACW)

FA

Digital Σ∆ modulator

SDA CKVDz, z=16, 32 or more

CKVDy, y=4 or 8 AM-PM Predistortion + FM PM CKVDz

DIV chain

CKVDx, x=1 or 2 Clock Module

MF

DIV chain

CKVDz

Delay

CKVDy

Delay

CKVDx

QSync

Fractional (dithered)

Phase Modulation

DIV chain

CKVDx

Nyx Exception Handler

Frequency Command Word (FCW)

FREF

ADPLL Loop CKVDz

IF

IF +FF CKV

CKVDy

Encoder and DEM

R E G

NDCO

Oscillator CKVDy CKVDx Tuning Word (OTW)

SD F FF

Digital Σ∆ modulator

DCO

I+ Q+ IQ-

TDL Dividers + Quad switch

Integer

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CKVDy

c04

RF out Variable clock (CKV)

DPA

CKVDx

FIGURE 4.17 Block diagram of a WCDMA transmitter with precise delay alignment between the frequency and amplitude modulation (both integer and fractional components) as well as the quad-switch-based exception-handling mechanism. Note the location of TDL between DCO and DPA.

the variable phase/frequency feedback happens precisely at the rate of the retimed reference or CKR. To better understand the evolution of the ADPLL architecture to support the wider bandwidth phase/frequency modulation, we describe the three generations of ADPLL with respect to the modulation path. In ADPLL, the frequency reference (FREF) clock contains the only reference timing information for the RF frequency synthesizer to which the phase and frequency of the RF output are to be synchronized. The RF variable output frequency f V is related to the reference frequency f R according to the formula fV = N f R

(4.3)

where N ≡ FCW is real-valued. The FREF source features excellent long-term accuracy and stability, at least as compared to the variable RF oscillator. Figure 4.18 shows the first realization of a DRP transmitter based on an ADPLL with a wideband frequency modulation capability. The digitally controlled oscillator (DCO) produces a digital variable clock (CKV) in the RF frequency band. In the feedforward path, the CKV clock toggles NMOS transistor switches of the near-class E RF power amplifier (PA) that is followed by a matching network, and then terminated with an antenna. In the feedback path, the CKV clock is used to retime the FREF clock. The FREF retiming quantization error is determined by the

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Pulse filter

data

y[k] Reference phase accumulator

CKR Channel Frequency Command Word (FCW)

Data FCW

+ +

(FCW’)

Σ

Phase detector

φΕ[k]

RR[k]

fR

+

(NTW)

-

KDCO

PA

DCO

d[k]

CKV

RF out

(OTW)

-

−ε[k] TDC

DCO gain normalization

Loop filter

KDCO

Sampler

RV[k]

Latch

c04

Oscillator phase accumulator

R V[i]

Σ

1

DCO period normalization

FREF

CKR Retimed FREF

FIGURE 4.18 ADPLL-based transmitter of the first-generation DRP.

time-to-digital converter (TDC), which is built as an array of inverter delay elements and registers, to compensate the quantization error by the system. The operation above strips FREF of its critical timing information and produces a retimed clock (CKR) that is subsequently used throughout the system. The CKR edge time stamps are now synchronous to the RF oscillator, in which time separation between the closest CKR and CKV edges is time invariant. In this embodiment, it is beneficial for avoiding injection pulling, in which the slowly varying timing separation between CKR and CKV causes the oscillator to be pulled, thus creating frequency-beating events that are exhibited as spurs in the output generated [14]. 4.5.1

Phase Modulation in the First-Generation DRP

Figure 4.19 is a simplified view of Fig. 4.18 that highlights the phase/frequency modulation path in the first-generation DRP, which targets the Bluetooth standard for short-range wireless communications. To ease the timing in actual interfaces among the FREF, CKR, and CKVD (i.e., the divided CKV clock or CKV/Mx , where Mx is an integer, preferably a power of 2) domains, the FREF clock retiming circuitry performs retiming by the CKV/N x clock, where N x = 8 in the actual implementation of the Bluetooth SoC. The N x > 1 value will create additional far-out spurs, which might be problematic in some system configurations, as described in [15]. Following are the salient features of the architecture: 1. The ADPLL phase operation and the entire PM modulation are performed on the CKR clock. 2. The phase error samples φ E and the FCW-normalized modulating data samples y[k] of the feedforward branch are merged before the tuning word computation.

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y’[k]

D

D

CKR

CKR y’[k]

FCW_CH FREF

Phase

D CKRET

D

y[k]

φΕ

fR KDCO

DCO OTW

D

CKV

CKR ÷Nx CKV/N x

FIGURE 4.19 Phase modulation path in the first-generation DRP.

3. To the extent of the DCO support of high-frequency deviations and correct DCO gain estimation, K DCO , the modulating path bandwidth is flat from dc to f R /2. DCO , controls both the modulation index 4. The DCO gain multiplier, f R / K m = 2 f pk Ts and the PLL bandwidth. For Bluetooth (m = 0.32) and GSM (m = 0.5), the K DCO value needs to be estimated precisely. 4.5.2

Phase Modulation in the Second-Generation DRP

Figure 4.20 shows the phase/frequency modulation path in the second-generation DRP, which targets the GSM standard. In the GSM standard, the output of the pulseshaping filter is proportional to the frequency deviation, and no conversion to the phase-proportional signal is explicitly required. Following are the salient features of the architecture: 1. The ADPLL phase operation and the PM modulation are performed on a CKR clock. To reduce circuit complexity and save dissipated power, the pulseshaping filter at the front end of the modulating path can operate at a lower CKR/N x rate, where N x is an integer, followed by the CKR-rate up-sampler. 2. The tuning word samples and the DCO-normalized modulating data samples x[k] of the feedforward branch are merged before the final CKR-clocked flipflop of the DCO interface. 3. To the extent of the DCO support of high-frequency deviations and correct DCO gain estimation, K DCO , the modulating path bandwidth is flat from dc to f R /2. DCO , now appears independently in two places. 4. The DCO gain multiplier, f R / K Only the modulating path multiplier f R /K DCO , which controls the modulation index m, needs to be set precisely. The ADPLL loop multiplier needs only to be accurate to the extent of the desired accuracy of the PLL bandwidth.

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FCW_DT D

CKR/N x

D

D

D

x[k]

y’[k]

CKR

fR KDCO

CKR

y’[k]

x[k]

FCW_CH

fR KDCO

FREF

Phase

D CKRET

FIGURE 4.20

4.5.3

D

φΕ

DCO OTW

CKV

D

CKR ÷Nx CKV/Nx

Phase modulation path in the second-generation DRP.

Phase Modulation in the Third-Generation DRP

Figure 4.21 shows the phase/frequency modulation path in the third-generation DRP. It adds support for the high data rates of the WCDMA and WLAN standards by dramatically increasing the frequency-modulating bandwidth. The maximum bandwidth limitation of f R /2 in the first and second generations of the DRP architecture is expanded here by employing CKV-down-divided clocks in the final stages of the modulating path. Since the modulating sample rate is much higher now than the CKR clock, the modulating stream is merged with the ADPLL phase/frequency corrections just before the DCO input. Following are the salient features of the architecture: 1. The ADPLL phase operation is performed on the CKR clock. 2. To reduce circuit complexity and save dissipated power, the pulse-shaping filter at the front end of the modulating path operates at the lower CKV/Nz rate, where Nz is an integer. The FCW-normalized samples are then resampled to the CKR rate for the y[k] compensating path. The FCW-normalized samples are also converted to the tuning word format and then up-converted to the CKV/N y rate for the feedforward x[k] path. 3. The tuning word samples and the DCO-normalized modulating data samples x[i] of the feedforward branch are merged on the high-speed CKV/N y interface. 4. The PM modulating path is synchronous to the CKV clock, by operating entirely on the CKV integer divisions.

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PRECISE ALIGNMENT BETWEEN AM AND PM/FM PATHS PCW_DT D

D

D

D

y’[k]

CKR

CKV/Nz FCW_DT

τ= ½T

D

D

x[i]

D

Nz y’[k] (FM only)

CKV/Nz

FCW_CH

fR KDCO

CKV/Nz

CKV/Ny

CKV/Nz y’[k]

x[i]

FCW_CH

fR KDCO

FREF

Phase

D CKRET

D

φΕ

DCO OTW

D

D

CKV

CKR ÷Nx CKV/Nx

CKV/Ny

CKV/Nz

FIGURE 4.21 Phase modulation path in the third-generation DRP.

5. This architecture makes sense mainly for the frequency relationship of CKV/N y > CKR. To the extent of the DCO support of high-frequency deviations, the modulating path can be made arbitrarily wide, from dc to f V /2N y . 6. Being synchronous to the CKV clock, the pulse-shaping filter clock rate is now channel dependent. This necessitates adjustment of the coefficient or operating in an interpolative manner, as described in [14] and Chapter 5 of [16]. DCO , 7. As in the second generation of DRP, the DCO gain multiplier, f R / K appears independently in two places. Only the modulating path multiplier f R /K DCO , which controls the modulation index, needs to be set precisely. The ADPLL loop multiplier needs only to be accurate to the extent of the desired accuracy of the PLL bandwidth. 4.5.4

Reference and Direct Modulation Point Injection Alignment

The third generation of ADPLL, as described using the digital delay adjust (DDA) block of Fig. 4.14, is shown in Fig. 4.22. Due to the higher phase modulation accuracy required of 2.5G (EDGE), 3G (WCDMA), and 4G (LTE or WiMAX) transmitters [see Fig. 4.14)], the direct point injection needs to operate at the CKVDy clock while the reference point injection is at the retimed FREF clock rate (CKR). The alignment of these two paths for correct frequency/phase error computation needs to be achieved in the CKR domain. Use of the interpolative correlation technique allows

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107

Data FCW@ CKVDy

CKVDy

Delay

CKVDx

Delay

Nyx

Sample Rate Converter

Frequency error Frequency detector accumulator

fE[k]

Channel Frequency Command Word (FCW)

CKVDy Loop filter

(OTW)

- [k]

RV[k] 1-z

TDC

OTI

d[k]

E[k]

+

[k]

ADPLL direct point injection

-1

CKR

CKR

OTF (SD)

CKVDx

CKR

RV[k]

Bit shift

DCO

Sampler

Variable phase accumulator

RV[i]

1

CKV

CKR

DCO gain normalization

(1.6 — 2.0 GHz)

ADPLL reference point injection

Latch

c04

DCO period normalization

FREF Retimed FREF (CKR)

FIGURE 4.22 ADPLL with a direct point injection rate of CKVDy and a reference point injection rate of CKR.

for the precise tuning of CKVDy and CKVDx delays in the direct point to achieve overall alignment. The direct point injection of modulation data into the PLL modulates the DCO directly at the CKVDy rate. The DCO in turn feeds the phase-modulated clock to the DPA, as well as feeding it back into the ADPLL loop. Cancellation of such modulated feedback is required to avoid the PLL loop from responding to transient modulation effects. Without the reference feed cancellation, the PLL loop would not be stable enough to meet the required phase noise performance. Proper delay matching is thus a requisite for proper two-point closed-loop modulation [17] without degradation of the ADPLL phase domain performance. Thus, the ADPLL loop can maintain the proper center frequency only by the exact cancellation of two modulation injections to the loop. Reference point modulation injection in a closed-loop PLL happens at a phase/frequency detector at the CKR rate, where the difference between the reference frequency control word (FCW) and the feedback frequency data (obtained by the differentiation of the variable clock phase with respect to the FREF clock) is being computed. While a direct modulation signal is fed back through the ADPLL feedback loop, comprising an accumulation and time-to-digital converter (TDC), with some propagation delay, the reference FCW signal that carries the same modulation information in the CKR clock domain should be aligned properly in time to produce zero phase/frequency error. Note that the DCO interface circuit takes the fixed-point oscillator tuning word (OTW) with the integer and fractional split between the integer part of the OTW (OTI), block and the fractional part of the OTW (OTF) block,

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respectively. The OTI operates a CKVDy clock, and the OTF is a sigma-delta modulator that operates on a high-speed CKVDx clock. Note that these two blocks are the same as the frequency modulation integer and fractional blocks shown in Figs. 4.15 and 4.17. The alignment approach taken in this work is carried out in two stages. In the first stage, theoretical analysis is done to provide a starting point for matching. Second, mathematical correlation between the reference and feedback signals is used to provide quantitative results on the magnitude of the delay mismatch. To ensure proper delay alignment, signal correlative measures were developed in which the data from the two paths to be matched was first interpolated and then cross-correlated to achieve accuracy better than that of the clock domain of comparison (Fig. 4.23). In particular, this is critical for precise alignment of ADPLL reference and direct point injection points. The time resolution of the magnitude of the correlative mismatch can be selected using interpolative measures to determine the practical matching needed in the CKR, CKVDx, and CKVDy clock domains, respectively.

9

1.242

x 10

1.241 1.24 1.239 1.238 1.237 1.236 1.235

0

20

40

60

80

100

120

80

100

120

(a) 9

1.242

x 10

1.241 1.24 1.239 1.238 1.237 1.236 1.235

0

20

40

60

(b)

FIGURE 4.23 Use of multi-rate correlation for the alignment of direct and reference point injections in ADPLL using WCDMA modulation data: (a) correlation achieved by analytic clock alignment; (b) correlation achieved by using correlative measures to tune multiple clockdomain delays.

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109

The underlying technique is to correlate the reference and test signals at a meaningful time resolution (which aligns with one of the tunable clock domains). 1. The absolute delay for each signal from the start to the end points is obtained by computing the cross correlation with a reference signal as the start point and a test signal as the end point. 2. Once the delays for each path are known, they can be delay matched to the time resolution available in the system: the CKVDx, CKVDy, and CKR time domains. 3. To tune the delay elements appropriately using multiple clock domains, crosscorrelation can be carried out starting from the coarsest time delay. After correlation, the result is truncated (floored), and the appropriate delay elements are set in the coarse clock domain. This is carried out in steps up to the finest clock domain, ensuring good delay alignment while minimizing the total number of delay elements required for tuning. 4. Alternatively, for better tuning resolution, the cross-correlation computation can be carried out in a highly oversampled signal domain (e.g., CKVDx), but the delays can be tuned starting from the coarsest clock domain: CKR in Fig. 4.14. This minimizes the overall need for digital registers that are needed for such alignment. Further, this also reduces the overall power consumption of the circuit. 5. The precise sub-CKR clock period alignment within the direct and reference point modulation injection within the ADPLL can also be dealt with using built-in self-test (BIST) techniques with PHE as the quality monitor [18]. If needed, the scheme can also be adapted dynamically using an embedded on-die processor or other available on-chip computational resources. The proposed scheme results in approximately 20% improved root-mean-square (rms) phase error as well as peak phase error performance of the ADPLL as compared to that which can be achieved without the proposed correlative optimization. It is important to note that this proposed approach is capable of handling any unknown independent component of delay in one of the data paths because the respective transfer function group delay can be treated as a lumped component of the correlation function computed. Acknowledgments The authors would like to acknowledge invaluable help from the following colleagues: Sameh Rezeq, Janardhanan Jayawardhan, Tim Foo, and Saket Jalan. REFERENCES 1. R. B. Staszewski, “Digital deep-submicron CMOS frequency synthesis for RF wireless applications,” Ph.D. dissertation, University, of Texas at Dallas, Aug. 2002.

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2. R. B. Staszewski, C.-M. Hung, D. Leipold, and P. T. Balsara, “A first multigigahertz digitally controlled oscillator for wireless applications,” IEEE Trans. Microwave Theory Tech., vol. 51, no. 11, pp. 2154–2164, Nov. 2003. 3. S. R. Norsworthy, D. A. Rich, and T. R. Viswanathan, “A minimal multibit digital noise shaping architecture,” in Proc. 1996 IEEE International Symposium on Circuits and Systems, pp. 5–8, 1996. 4. R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara, “Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process,” IEEE Trans. Circuits and Syst. II, vol. 50, no. 11, pp. 815–828, Nov. 2003. 5. R. B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J. L. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung, J. Koh, S. John, I. Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O. E. Eliezer, E. de-Obaldia, and P. T. Balsara, “All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2278– 2291, Dec. 2004. 6. R. B. Staszewski, J. Wallberg, S. Rezeq, C.-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, “All-digital PLL and transmitter for mobile phones,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2469–2482, Dec. 2005. 7. K. Muhammad, Y.-C. Ho, T. Mayhugh, C.-M. Hung, T. Jung, I. Elahi, C. Lin, I. Deng, C. Fernando, J. Wallberg, S. Vemulapalli, S. Larson, T. Murphy, D. Leipold, P. Cruise, J. Jaehnig, M.-C. Lee, R. B. Staszewski, R. Staszewski, and K. Maggio, “The first fully integrated quad-band GSM/GPRS receiver in a 90nm digital CMOS process,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1772–1783, Aug. 2006. 8. W. B. Sander, S. V. Schell, and B. L. Sander, “Polar modulator for multi-mode cell phones,” in Proc. 2003 IEEE Custom Integrated Circuits Conference, vol. 3, pp. 594–597, May 2003. 9. E. McCune and W. Sander, “EDGE transmitter alternative using nonlinear polar modulation,” in Proc. 2003 IEEE International Conference on Circuits and Systems, vol. 6, no. 1, pp. 44–55, Mar 2005. 10. T. Sowlati, D. Rozenblit, R. Pullela, M. Damgaard, E. McCarthy, D. Koh, D. Ripley, F. Balteanu, and I. Gheorghe, “Quad-band GSM/GPRS/EDGE polar loop transmitter,” IEEE J. Solid-State Circuits, vol. 39, pp. 2179–2189, Dec. 2004. 11. M. R. Elliott, T. Montalvo, B. P. Jeffries, F. Murden, J. Strange, A. Hill, S. Nandipaku, and J. Harrebek, “A polar modulator transmitter for GSM/EDGE,” IEEE J. Solid-State Circuits, vol. 39, pp. 2190–2199, Dec. 2004. 12. E. McCune, “High-efficiency, multi-mode, multi-band terminal power amplifiers,” IEEE Microwave Mag., vol. 6, no. 1, pp. 44–55, Mar. 2005. 13. Yonghui Huang, Yuanxun Wang, and T. Larsen, “Filter considerations in polar transmitters for multi-mode wireless applications,” in Proc. 2005 IEEE Annual Conference on Wireless and Microwave Technology, vol. 1, p. 4, 2005. 14. R. B. Staszewski, D. Leipold, and P. T. Balsara, “Direct frequency modulation of an ADPLL for Bluetooth/GSM with injection pulling elimination,” IEEE Trans. Circuits Syst. II, vol. 52, no. 6, pp. 339–343, June 2005. 15. K. Waheed, R. B. Staszewski, and J. Wallberg, “Injection spurs due to reference frequency retiming by a channel dependent clock at the ADPLL RF output and its mitigation,” in

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18. 19.

111

Proc. 2007 IEEE International. Symposium on Circuits and Systems, New Orleans, LA., sec. 5.5, pp. 3291–3294, May 2007. R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS. Hoboken, NJ: Wiley, Sept. 2006. R. B. Staszewski, D. Leipold, J. Wallberg, and P. T. Balsara, “Just-in-time gain estimation of an RF digitally-controlled oscillator,” in Proc. 2003 IEEE Custom Integrated Circuits Conference, San Jose, CA, sec. 25-8, pp. 571–574, Sept. 2003. R. B. Staszewski, I. Bashir, and O. Eliezer, “RF built-in self test of a wireless transmitter,” IEEE Trans. Circuits and Syst. II, vol. 54, no. 2, pp. 186–190, Feb. 2007. P. Cruise, C.-M. Hung, R. B. Staszewski, O. Eliezer, S. Rezeq, D. Leipold, and K. Maggio, “A digital-to-RF-amplitude converter for GSM/GPRS/EDGE in 90-nm digital CMOS,” in Proc. 2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Long Beach, CA, sec. RMO1A-4, pp. 21–24, June 2005.

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Overview of Front-End RF Passive Integration into SoCs HOOMAN DARABI Broadcom Corporation, Irvine, California

5.1

INTRODUCTION

Whereas integration of digital baseband and radio seemed impossible less than 10 years ago, today large systems-on-a-chip (SoCs) with the radio-frequency (RF), mixed signal, and digital blocks integrated on the same die are almost inevitable. The volume of investment and economies of scale make the standard CMOS process the perpetual cost leader. With more than 1 billion units produced each year, the cell phone market is the largest and most competitive that the semiconductor industry has to address, and as such, CMOS systems-on-a-chip with a large level of integration provide the lowest-cost path to products, assuming that the technical hurdles of implementation can be crossed. Despite the low-cost CMOS advantages and RF and digital integration, in all cellular applications where very aggressive filtering is required, external SAW filters are still very common. In addition to the extra cost and physical printed-circuit board (PCB) space imposed by these components, they introduce significant challenges in RF IC, package, and board design in multi-mode and multi-band systems, which are quite typical in cellular applications. Considering all these concerns, given the advances on technology, and with the innovations on circuit and system design happening continuously, integrating these components on the SoC seems inevitable, and imminent. In this chapter we address some of these concerns in more detail and introduce several circuit-level and architectural techniques to integrate narrowband RF filters on the same die as the CMOS RF integrated circuit (IC). We address the 2G global system for mobile communications (GSM) and EDGE receivers, as well as 3G transceivers, where for a very different reason, similar aggressive filtering is required. Let’s first study GSM receivers. In a time-division duplexing (TDD) radio system such as GSM, where the transmitter is guaranteed to remain inactive during the entire receiver slot, the only interferers are the in-band blocker produced due to other GSM receivers communicating with their corresponding base stations, or out-of-band blockers, due to other wireless systems Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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nearby. Generally, the noisy RF environment demands a very stringent blocking requirement for most wireless applications. Depending on the type of the blocker, the receiver may be affected in two ways: 1. A large out-of-band blocker can saturate the receiver front end, and hence by reducing the receiver gain, elevate the noise contribution of the following baseband blocks. 2. An in-band blocker may desensitize the receiver, due to reciprocal or spurious mixing or through intermodulation [1]. Since the in-band blockers are very close in frequency to the channel desired, RF filtering prior to the receiver is not helpful. Thus, whereas the in-band blockers are typically removed by adjusting the local oscillator (LO) phase noise and linearity of the receive path, and ultimately through baseband filtering, the large out-of-band blockers may only be eliminated through front-end filtering. In both cases, proper frequency planning is helpful, although due to the high level of integration demanded in most applications today, a low-IF or direct-conversion architecture [1,2] is usually preferable. To address the receiver functionally under extreme blocking conditions, in most standards, and especially in wireless wide-area network (WAN) applications, the receiver must satisfy a certain blocking template defined at various blocker frequencies and levels. For example, as shown in Fig. 5.1, in the GSM standard a desired signal only 3 dB above the sensitivity could be accompanied by an out-of-band blocker as large as 0 dBm and as close as only 80 MHz to the edge of the personal communications service (PCS) band. Since the desired signal is weak, the low-noise amplifier (LNA) gain must be kept high, and thus the blocker must be filtered prior to reaching the amplifier output. On the other hand, due to the modest quality factor (Q) of on-chip inductors, it is not practical to integrate such a sharp filter on-chip. For these reasons, all existing receivers inevitably use an external surface acoustic wave (SAW) filter at the LNA input. Since the external filters are typically not tunable, in multi-band applications each band requires a dedicated filter. Shown in Fig. 5.2 is an example of a current quad-band GSM/EDGE transceiver where four filters are needed.

FIGURE 5.1

GSM out-of-band blocking profile.

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INTRODUCTION

FIGURE 5.2

115

Example of a current quad-band GSM radio.

This has several obvious disadvantages. First, it increases the cost, especially in multi-mode and multi-band applications, where several of these filters are needed, as described earlier. Second, the insertion loss of the SAW filter, typically as high as 2 to 3 dB, degrades the receiver sensitivity directly. Third, the presence of these filters removes the flexibility of sharing the LNAs in multi-mode or multi-band applications, particularly in software-defined radios. Therefore, it is highly desirable to eliminate these external filters. Unlike the receiver, the GSM transmitter does not suffer from similar issues, thanks primarily to the translational loop, or PLL-based architecture [3–8]. The narrow PLL bandwidth typically makes the VCO the only contributor at far-out offset frequencies, and typically, by proper design, the noise and spur requirements are met. This effectively creates a tunable narrowband RF filter at the output, whose center frequency is a function of the VCO frequency and whose bandwidth is set by PLL characteristics. On a 3G transceiver on the other hand, a similar issue exists in both RX and TX modes. While a WCDMA scheme proves to be more resilient to out-of-band blockers, due to the spread-spectrum nature of the system, another issue arises from the frequency-division duplex (FDD) requirement in the radio. In normal operation, both receiver and transmitter are active concurrently in different frequency bands and are typically separated by an external duplexer. The duplexer is effectively a dual-band highly selective filter, isolating the RX and TX bands, which are typically separated by 45 MHz in low bands (bands V and VIII), and 190, 80, or 90 MHz for high bands (bands I, II, and II, respectively) [9]. However, cost and size constraints play the major role, especially in multi-band applications, and limit the duplexer performance [10]. As a result, the duplexer isolation is finite, on the order of 45 to 50 dB, and the receiver is plagued by the transmitter signal and its noise [3,12], as shown in Fig. 5.3.

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FIGURE 5.3

WCDMA FDD issue with TX leaking to RX.

This affects the receiver in two ways: First, the TX noise appearing at the RX band degrades the sensitivity, and second, the TX leakage mixing with another out-of-band blocker causes intermodulation issues in the receiver front end. Thus, traditionally, at both the TX output and at the input of the receiver, external SAW filters are used to alleviate the issue. Moreover, to overcome the loss of the external SAW filter at the receiver input, typically an external single-ended LNA is used, which helps to achieve a lower noise figure and eases the RF IC interface. The issue becomes worse in multi-mode and multi-band applications, where several of these external filters or low-noise amplifiers are needed. Shown in Fig. 5.4 is an example of a triband WCDMA, quad-band EDGE transceiver with the required peripheral external components, which may be as many as 20.

FIGURE 5.4

Tri-band WCDMA, quad-band EDGE radio.

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INTRODUCTION

FIGURE 5.5

117

Tri-band WCDMA, quad-band EDGE radio with integrated SAW filters.

As shown in Fig. 5.5, if both the receiver and transmitter SAW filters could be integrated, the number of the external components would be reduced by a factor of 2, to 10. This is a much more favorable situation, and not only reduces the cost but also improves the PCB and package complexity. However, this comes at the cost of more stringent requirements for both receiver and transmitter, explained briefly as follows. As indicated earlier, removing the receiver SAW filter reduces the receiver immunity to out-of-band blockers. An example is the case where the TX leakage, say at a frequency offset f RXTX /2 away from the desired receiver channel, mixes with an out-of-band blocker at exactly half the space, f RXTX /2 (see Fig. 5.6). Due to the third-order nonlinearity of the receiver, the IM3 product will then fall exactly on top of the desired receiver channel. These two effects are typically relaxed by placing an external SAW filter at the receiver to further attenuate the transmitter leakage and out-of-band blockers. Otherwise, the second- and third-order nonlinearity requirements would be very stringent [3,12]. Depending on the duplexer

FIGURE 5.6

Example of receiver problems due to blockers with the SAW filter removed.

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FIGURE 5.7

TX leakage noise at the RX band, masking the weak desired receiver signal.

isolation in the TX band, it can shown that with typical blocker levels specified in the 3GPP standard, this could lead to an IIP3 requirement of somewhere around −5 to 5 dBm [13]. Desensitization of the receiver by the RX-band transmitter noise is another notable consequence of finite isolation of the duplexer. Again, due to the modest Q value of on-chip inductors, typically use of a costly SAW filter before the power amplifier is inevitable [14–16]. On the other hand, as a result of the aggressive advancement toward more integration, this external SAW filter has been removed in some designs [14,17–19]. However, without deploying a proper on-chip filtering mechanism and due to the stringent noise requirements, this would result in excessive transmitter power dissipation. To understand the challenges, since the problem arises primarily from the noise of the TX leakage appearing at the receiver band of interest—that is, at f RXTX away, as shown in Fig. 5.7—we run some calculations. Assuming an ideal PA, with a TX power of 27 dBm at the PA output (to allow for 3 dB loss of duplexer to ensure 24 dBm at the antenna) and a phase noise of −158 dBc/Hz at the TX output, with 45 dB of duplexer isolation in the RX band, the receiver noise floor due to the TX will be 27 d Bm −45 − 158 = −180 dBc/Hz. Thus, if the receiver chain noise figure alone is 3 dB, for instance, with the TX turned on at the maximum gain, it degrades to 3.5 dB. With a SAW filter placed at the TX output, the TX phase noise can be relaxed directly proportional to the SAW rejection, to tolerate the same noise figure degradation. However, in a SAW-less TX, depending on the duplexer isolation, a very stringent phase noise of about −158 to −160 dBc/Hz at the TX-RX frequency offset (that could be as low as 45 MHz for band V, or 80 MHz for band II) would be needed, which could lead to extra power consumption if no notch filtering at RX frequency (which would naturally be coming from the SAW filter in the existing designs) is implemented. In this book, two different ideas of creating an on-chip narrow filter are presented to alleviate some of the problems mentioned earlier. In Section 5.2, an on-chip filtering technique based on a feedforward cancellation is presented which eliminates the need for a SAW filter in the receiver input. This could apply to both 2G and 3G receivers. In Section 5.3 we discuss a detailed analysis of the nonideal effects of the feedforward

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THE CONCEPT OF A RECEIVER TRANSLATIONAL LOOP

119

cancellation technique. In Section 5.4, the circuit implementation of the key building blocks is introduced. Experimental results are presented in Section 5.5. In Section 5.6 we present the idea of noise nullification by a feedback system and explain how it warrants elimination of a bulky transmitter SAW filter. Since the TX notch filter is feedback-based, a full stability analysis is carried out in Section 5.7, and the correct structure is chosen accordingly. After studying nonideal effects in Section 5.8, we present building blocks of the transmitter in Section 5.9. Finally, in Section 5.10 we present some measurement results for the TX, followed by an overall summary and conclusions in Section 5.11.

5.2

THE CONCEPT OF A RECEIVER TRANSLATIONAL LOOP

As demonstrated in Fig. 5.8, one way of reducing the out-of-band blocker is through feedforward injection, where a replica of the blocker is subtracted at the LNA output. In order not to reject the desired signal as well, a notch filter in the feedforward path is needed to distinguish the signal from the blocker. The notch filter should be centered at the desired RF bandwidth, rejecting the desired signal, but it must be sharp enough to pass the blocker, which could be as close as only 80 MHz away. The shape of this filter is almost the inverse of the input SAW filter, and thus it demands the same stringent requirements on the passives. Thus, similarly, it cannot be implemented on-chip in practice. On the other hand, filtering could be performed much more efficiently at an intermediate frequency (IF) through down-conversion. This new concept is shown in Fig. 5.9, where the desired signal accompanied by the blocker is down-converted to zero or low IF by the same LO signal as that used in the main receiving path. The desired signal is now at or near dc, and is easily removed by a highpass filter (HPF), whereas the blocker located at least 80 MHz away passes through. The same LO up-converts the blocker back to RF and subtracts it at the output. As a result of

FIGURE 5.8

Feedforward blocker cancellation in a receiver.

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FIGURE 5.9

Concept of a receiver translational loop.

this, a sharp frequency response is created, whose bandwidth and slope are controlled simply through adjusting the highpass filter characteristics. The HPF corner needs to be high enough to filter the desired signal, but should be sufficiently low to pass the blocker. Since the signal is at dc while the blocker is at least 80 MHz away, this is easily achieved. The resulting RF filter passband moves with the desired signal; that is, it is always centered at the LO frequency. Thus, despite its narrow bandwidth, it does not affect the desired signal band. This could be thought of as a receiver translational loop, where the frequency response of the IF filter is translated to RF through down-conversion. Similar to transmitter, the resulting sharp frequency response at RF eliminates the need for a SAW filter at the front end. To prove this concept, the LNA architecture shown in Fig. 5.10 is fabricated and measured.

FIGURE 5.10

LNA with an on-chip feedforward notch.

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Since a quadrature LO signal is available in the receiver, the filtering path exploits the I and Q mixers for single-sideband selection. Due to the quadrature mixing, the filtering path remains a linear and time-invariant (LTI) system, whose impulse response is calculated by y(t) = [[x(t) cos ωLO f ] ∗ h(t)] cos ωLO t + [[x(t) sin ωLO t] ∗ h(t)] sin ωLO

(5.1)

where y(t) is the output signal, x(t) the input signal, h(t) the impulse response of the baseband filter, and ∗ the convolution operator. After expanding the convolution integral and regrouping, the output signal
y(t) =

[x(τ )h(t − τ )] (cos ωLO t cos ωLO τ + sin ωLO t sin ωLO t) dτ

(5.2)

Thus,
y(t) =

x(τ ) [h(t − τ ) cos(ωLO (t − τ ))] dτ

(5.3)

Therefore, the impulse response of the RF filtering path, H (t) = h(t) cos ωLO t

(5.4)

Hence, as shown in Fig. 5.11, in the frequency domain, the transfer function of the RF filter resembles that of the original baseband highpass filter, but translated to ±ωLO , providing a desirable notch at RF. A power detector at the LNA output (Fig. 5.10) activates the filtering only when a strong out-of-band blocker is present. Thus, the extra power consumption as a result of the filtering circuitry is practically negligible. As mentioned earlier, this idea is not limited to 2G receivers, and could in fact be used in a 3G front end as well. In the case of a 3G receiver, the duplexer protects the LNA from out-of-band blockers in general; however, due to its finite isolation, the TX leakage remains. This is, of course, an easier scenario to handle than that of the SAW-less 2G receiver, as the TX leakage is much less than 0 dBm (around

FIGURE 5.11 Transfer function of the notch translated to RF.

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−20 to −30 dBm, depending on the duplexer) and will be rejected similarly by the translational loop.

5.3

FEEDFORWARD LOOP NONIDEAL EFFECTS

To achieve the desired attenuation in practice, the phase and gain of the filtering path must be well matched to that of the main signal. Figure 5.12 shows a more detailed description of the actual implementation of the filtering circuitry. The LNA and mixers share the same matching circuit at the input and output. The down-conversion mixer is an active design, and consists of a transconductance stage followed by switching devices, and the up-conversion mixer is a current-mode passive device. Obviously, any mismatch between the gain and phase of the two paths results in less stopband filtering. In this section we discuss the effects of mismatch as well as some other practical issues. 5.3.1

Gain Mismatch

At the blocker frequency, the highpass filter has an ac gain of exactly 1. Assuming that the mixers are ideal, then, the blocker will be multiplied by sin2 in the I path and by cos2 in the Q path. So the switching gain of the cascade of down- and upconversion mixers is equal to unity as sin2 + cos2 is equal to 1. In practice, however, the switching gain is somewhat different, due to harmonic mixing and the fact that higher LO harmonics are subject to some filtering. Still, the switching gain is fairly well defined, and thus only the transconductance stage of the first mixer needs to be matched to that of the LNA. The effect on stopband filtering of a mismatch between the LNA and mixer transconductance stages is shown in Fig. 5.13. For example, to achieve higher than 20 dB of stopband rejection, the two transconductance stages need to be better than 10% matched, which is a reasonable target, knowing that both the LNA and the mixer use large devices for noise and other practical concerns.

FIGURE 5.12

Detailed description of actual filtering circuitry.

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123

FIGURE 5.13 Effect of mismatch on stopband filtering.

5.3.2

Phase Mismatch

Phase mismatch, which is more critical than gain mismatch, is created in three places (Fig. 5.14): 1. The mixers’ finite RF bandwidth 2. The down-conversion mixer’s finite IF bandwidth 3. The delay introduced in the highpass filter The highpass filter delay is easily avoided by reducing its 3-dB corner frequency. The stopband rejection vs. the highpass corner for a blocker 80 MHz away is shown in Fig 5.15. To achieve higher than 20 dB of attenuation, for example, the filter corner should be about 8 MHz or less. The mixers’ RF bandwidth is generally on the order of the device f T , and fortunately, its negative effect is partially canceled by the LNA lowpass behavior, which is on the same order. Nevertheless, the mixers must be designed for sufficiently wide bandwidth. The main limiting factor in phase mismatch is due to the down-conversion mixer finite IF bandwidth. A high IF bandwidth causes the desired signal sideband at 2 f LO to pass through and eventually to be down-converted by the second mixer to f LO . This creates some passband loss and degrades the noise figure proportionally. Therefore, it is best to set the IF bandwidth below 2 f LO , but large enough to minimize the excess delay created at IF.

FIGURE 5.14

Sources of phase mismatch.

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FIGURE 5.15

5.3.3

20:12

Stopband rejection vs. highpass filter corner.

LNA Noise Figure Degradation

Another practical concern arises from noise figure degradation resulting from the injection circuitry. However, this is not an issue, for several reasons. First, the filtering devices are turned off in the normal receive mode and are active only when a blocker is present. Fortuitously, the receiver noise figure may typically be relaxed by 3 dB or more when a blocker is present. For example, in the GSM standard, assuming that a conservative signal-to-noise ratio (SNR) of 9 dB is required at baseband, the receiver blocking noise figure is relaxed to 13 dB. Moreover, the noise created at the output of the first mixer experiences the same filtering that the signal does. Shown in Fig. 5.16 is the noise transfer function of the down-conversion mixer to the output.

FIGURE 5.16

First mixer noise transfer function to the LNA output.

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FEEDFORWARD RECEIVER CIRCUIT IMPLEMENTATIONS

FIGURE 5.17

125

Stopband rejection and gain vs. phase/gain imbalance.

Similar to the signal, the noise at the IF is attenuated due to the highpass filter following the mixer. Thus, only the up-conversion mixer contributes noise to the LNA output, and it is minimized by proper design. The circuit design of the second mixer is addressed in Section 5.4.2.

5.3.4

I– Q Imbalance

Figure 5.17 shows passband gain and stopband rejection vs. I –Q phase and gain imbalance. All the other nonidealities, such as the finite bandwidth of the circuits, are included. A phase mismatch of up to 10◦ with a gain imbalance as high as 2 dB has a relatively small impact on the filter rejection or the LNA passband gain. Thus, common layout techniques are sufficient to meet the requirements. Although the impact of I –Q imbalance on passband gain and rejection is small, it must be noted that it does create an unwanted sideband at f LO −  f , where  f is the frequency separation between the blocker and the receiver LO. This sideband, along with the blocker, down-converts to a frequency of  f and is eventually removed by the baseband filter. Thus, as long as this unwanted sideband is low enough not to saturate the amplifier output, it does not cause a problem.

5.4 FEEDFORWARD RECEIVER CIRCUIT IMPLEMENTATIONS In this section, we discuss the circuit implementation of the feedforward-based lownoise amplifier as well as that of down- and up-conversion mixers.

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FIGURE 5.18 Low-noise amplifier schematic.

5.4.1

Low-Noise Amplifier

An LNA circuit is shown in Fig. 5.18. Despite its higher noise figure, a commongate design is chosen, for two reasons. First, although the filtering attenuates the blocker at the output, the LNA input must be able to tolerate a large signal. Since the common-gate LNA has no gain at the input, it is a desirable choice compared to other implementations, such as an inductively degenerated common-source amplifier [20]. Second, the common-gate design has a wide input bandwidth and allows the inputs of different bands to be shared, eliminating the need for a switch in multi-band applications. A cascode structure is used for better isolation between the input and output ports. Moreover, it provides a low-impedance node, suitable for injection of the second mixer output current for blocker subtraction. The LNA output employs a programmable capacitance array to tune the output to cover other bands as well. The LNA simulated and measured gain and noise figures are shown in Fig. 5.19. The passband gain is about 23 dB, and the noise figure is 3.9 dB. Even though this is higher than what is typically achieved [7], it is still advantageous once the 3-dB loss of the SAW filter and the switch is included. The LNA is tuned to 1.96 GHz and has a measured 3-dB bandwidth of about 250 MHz, set primarily by the output inductor, which has a Q value of about 8. The simulated gain and noise figure both match the measurements very well. The LNA input return loss remains below −10 dB over a wide frequency range of almost 1 GHz, as shown in Fig. 5.20. If needed, an optional tunable capacitor at the input can adjust the input S11 to go as low as 1 GHz without affecting the noise figure, as the LNA input matching is fairly low-Q. The LNA measured in-band input IP3 is shown in Fig. 5.21. The two tones are centered at 1.96 GHz and are 2 MHz apart. The measured IIP3 is 2.6 dBm, which is fairly close to the simulated value of 2.8 dBm.

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FEEDFORWARD RECEIVER CIRCUIT IMPLEMENTATIONS

FIGURE 5.19

LNA simulated and measured gain and noise figure.

FIGURE 5.20

5.4.2

127

Simulated and measured return loss of LNA.

Mixers

The down-conversion mixer is a fully differential active circuit and is shown in Fig. 5.22. It uses grounded source devices at the input for better linearity, with a 12-dB capacitive attenuation to reduce the blocker. The attenuation raises the mixer power consumption, but it is necessary to lower the blocker level, or otherwise the mixer linearity suffers, due to headroom issues. This is not the case for the LNA, however, as it consists of only two transistors stacked, with the drain of the cascode device set at VD D .

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FIGURE 5.21 LNA measured IIP3.

The size of the input devices is optimized for the best linearity, and is chosen such that the overall transconductance of the mixer matches that of the LNA input devices. The output employs a cascode current source with a common-mode feedback, providing a current to the second mixer. Shown in Fig. 5.23 is an up-conversion mixer, which is a current-mode passive circuit with a blocking capacitor at its input [21]. The passive design ensures that the noise contribution of the second mixer is minimal. Moreover, since the switches do not carry any dc current, the flicker noise contribution of these devices is practically negligible [22].

FIGURE 5.22 Down-conversion mixer schematic.

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FIGURE 5.23 Circuit diagram of up-conversion mixer.

Assuming that the input impedance of the up-conversion mixer is much less than the output impedance of the first mixer, the highpass filter 3-dB corner frequency, ω3dB ≈

1 roMX1 Cc

(5.5)

where Cc is the blocking capacitor and rroMX1 is the output resistance of the downconversion mixer. Although the mixer output impedance, and hence the highpass filter corner frequency in (5.5), vary with process or temperature, the exact value is not critical as long as it remains below a certain level to guarantee the desired stopband rejection, as discussed in Section 5.3.2.

5.5

FEEDFORWARD RECEIVER EXPERIMENTAL RESULTS

To prove this concept, a test chip is fabricated in 65-nm 1P-7M CMOS technology. It occupies an active area of 0.28 mm2 and is housed in a 24-pin LPCC package. A microphotograph of the die is shown in Fig. 5.24. The common-gate LNA is in the middle, the I –Q down-conversion mixers are on the left side, and the up-conversion mixers are on the right side. The blocking capacitor for a highpass filter is a MOS capacitor, to reduce the area. The measured and simulated frequency response of the amplifier with and without filtering is shown in Fig. 5.25. With the filtering enabled, the bandwidth narrows down to about 4.5 MHz and starts following the HPF roll-off. It then flattens, due to the phase mismatches resulting mainly from finite IF bandwidth, and then starts rolling off again due to the LNA output inductor. The measurements agree well with simulations, and a stopband attenuation of more than 21 dB is achieved. Shown in Fig. 5.26 is the amplifier frequency response at 1930 and 1990 MHz. The stopband rejection and the shape of the response stay more or less the same.

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FIGURE 5.24 Die photo of feedforward filtering technique.

The equivalent frequency response of the receiver is superimposed as well, which follows the 1930-MHz curve on the left, then there is a flat passband covering the PCS band, followed by the 1990-MHz curve on the right. Even though a commercial SAW filter provides more rejection (Fig. 5.27), since the in-band blockers could be as large as −23 dBm, the mixer must be designed to be linear enough to handle this

FIGURE 5.25

Frequency response of the amplifier with and without filtering.

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FIGURE 5.26 Amplifier frequency response over the PCS band.

level of blocker. Therefore, an attenuation of 20 dB in principle is good enough to allow removal of the external filter. To ensure the robustness of this scheme, the LNA gain with filtering is simulated and measured over temperature and shown in Fig. 5.28. Naturally, as expected, the passband gain varies by about ±1 dB, due to mobility variation with temperature, but in both cases the filter shape stays consistent and a rejection of over 20 dB is achieved. The LNA frequency response with and without filtering measured up to 6 GHz is shown in Fig. 5.29. At frequencies above 3 GHz, the filtering rejection degrades, due

FIGURE 5.27

Commercial SAW filter response.

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FIGURE 5.28 LNA rejection over temperature.

to the finite IF bandwidth of the first mixer. This is not an issue, however, as the LNA itself provides sufficient filtering at these frequencies. The discrepancy between the simulated and measured gain at frequencies above 4 GHz is due to the external balun, as in simulation an ideal balun is used. The LNA gain vs. the blocker power is shown in Fig. 5.24. The signal desired is at 1.96 GHz, and the blocker is 80 MHz away. The gain stays relatively flat up to a blocker level as high as 0 dBm. Without the filtering, the LNA 1-dB compression is about −12 dBm, limited by the output (Fig. 5.30).

FIGURE 5.29

LNA frequency response over a wide frequency range.

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FIGURE 5.30 LNA measured 1-dB compression.

5.6

FEEDBACK NOTCH FILTERING FOR A WCDMA TRANSMITTER

In this section we discuss a different approach to creating filtering in a WCDMA transmitter. Here we present a feedback-based filtering technique to null the receiverband noise of the transmitter with negligible area or power penalty. This architecture allows us to eliminate the TX SAW filter and design the transmitter for minimum power consumption while meeting the noise requirements. Since the external PA contribution is typically negligible, the receiver-band noise of the transmitter is dominated mainly by RFIC circuits. Therefore, by introducing an on-chip null at the very last stage of the TX chain (i.e., the output of the PA driver), regardless of its origin, the TX noise will be effectively attenuated.1 The best place for such a null is the output impedance seen by the PA driver, which is 50  imposed by the external PA.2 This can be done elegantly, as depicted in Fig. 5.31. A sharp bandpass filter centered at RX frequency passes the receiver-band noise selectively at the PA-driver output while suppressing the TX signal. The noise components selected are amplified and fed back to the PA-driver input. In this feedback loop, since the loop gain is almost zero at the TX frequency, the transmitter signal is not affected. On the contrary, at the RX frequency the loop gain is set large, which scales down the impedance seen at the PA-driver output by the loop gain, and thus effectively filters out the noise. Generally, any frequency component passing through the bandpass filter of the feedback path is deemed to be diminished at the PA-driver output. This means that the null width is as wide as the bandpass filter. However, the depth of the null is equal to 20 log |1 + LG( jω)|, which is controlled only by the loop gain. One of the 1 We 2A

present an alternative feedback-based approach in the appendix. slight deviation occurred due to parasitics of bondwires and pads.

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FIGURE 5.31

Introducing a null at RX frequency for the PA-driver current.

main advantages of this feedback-based noise cancellation approach compared to feedforward-based schemes [23] is that as long as the feedback remains stable, there is no need to control the gain and phase of the feedback signal. Eliminating the external high-Q bandpass filter (SAW) necessitates an alternative on-chip high-Q high-frequency bandpass filter. Moreover, this on-chip bandpass filter should be tunable and centered at the RX frequency with large precision. Since the quality factors of on-chip passive inductors are very low, such a high-Q filter obviously cannot be passive. Techniques such as Q-enhancement to realize integrated high-Q tunable RF bandpass filters [24–28] were proposed. However, built with active devices at gigahertz ranges, these filters consume a huge amount of power not feasible for mobile handsets, and suffer from poor linearity and a large noise figure. On the other hand, realization of high-Q RF filters based on the IF frequency translation technique [23] introduced in Section 5.2 was proved to be a more integration-friendly solution for the foreseeable future. In this way, the RF signal is down-converted to the baseband in quadrature, and all that is needed are two identical baseband filters whose bandwidth and slope of transition are the same as those of the original bandpass filter. Therefore, in many cases, simple RC filters work fine. Figure 5.32(a) demonstrates the realization of the bandpass filter based on the IF frequency-translation technique. It is assumed that the LO signals are sinusoidal with no harmonics and that the mixers are ideal multipliers. Impacts of harmonic mixing will be studied later. The RF input signal is down-converted by an RX local oscillator (LO) in quadrature, followed by a lowpass filter (LPF). The mixer in one path is driven by cos ωRX t, whereas the other mixer is clocked by its quadrature phase, sin ωRX t. The lowpass filter outputs are given by [29]
VU (t) =
VL (t) =

t −∞ t −∞

h LP (t − τ )Vin (τ ) cos ωRX τ dτ

(5.6)

h LP (t − τ )Vin (τ ) sin ωRX τ dτ

(5.7)

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in which h LP (t) is the LPF impulse response. Now, the low-frequency components selected are up-converted back to the RF by another pair of quadrature LO phases that are phase-shifted by an arbitrary angle α with respect to the corresponding LOs in the down-conversion mixers. One up-conversion mixer is clocked by cos(ωRX t + α), whose corresponding down-conversion mixer was clocked by cos ωLO t. The other up-conversion mixer is driven by sin(ωmathrmR X t + α). The resulting RF signals are added together. From (5.6) and (5.6) we can calculate the final RF output:
Vout (t) = cos(ωRX t + α)

t −∞




+ sin(ωRX t + α)
=

t

−∞

h LP (t − τ )Vin (τ ) cos ωRX τ dτ

t −∞

h LP (t − τ )Vin (τ ) sin ωRX τ dτ

Vin (τ )h LP (t − τ ) cos [ωRX (t − τ ) + α] dτ

= Vin (t) ∗ [h LP (t) cos(ωRX t + α)]

(5.8)

in which * is the convolution integral. Equation (5.8) proves that the overall system is linear-time invariant (LTI) with the following impulse response [29]: h BP (t) = h LP (t) cos(ωRX t + α)

(5.9)

which maps to the following frequency response in the s-domain: HBP (s) =

1 2



e jω HLP (s − jωRX ) + e− jω HLP (s + jωRX )



(5.10)

Evidently, the LPF frequency response is shifted to ±ωRX to perform the bandpass filtering. As mentioned earlier, the bandwidth and slope of this bandpass filter are adjusted by the LPF characteristics. This is similar to what we drove for the HPF case in Section 5.2 and equations (5.1) to (5.4). However, we derive more details here and use the results to gain more insight, and will use it further for stability analysis. For this application, the LPF bandwidth should be large enough to pass the desired signal (i.e., the TX noise at the RX frequency), yet low enough to adequately attenuate the transmitter signal located at a relatively large offset away. For example, for WCDMA band II, the receiver channels are spaced 80 MHz above the transmitter channels. For such an application, a simple RC-LPF would suffice. For a first-order lowpass filter with a transfer function of HLP (s) = sp /(s + sp ), the transfer function of the bandpass filter is found to be HBP (s) =

sp cos α(s + sp ) − sp sin αωRX 2 (s + sp )2 + ωRX

(5.11)

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(a)

(b)

FIGURE 5.32 (a) High-Q bandpass filter based on IF frequency-translation technique; (b) pole–zero diagram of the resulting filter.

Consequently, the LPF with a real pole at −sp is translated to a BPF with two high-Q complex poles at −sp ± jωRX and a real zero at −sp + ωRX [Fig. 5.32(b)]. Thus, unlike the poles, the zero is a function of α, and shortly we will show that it is highly influential on the stability of the feedback loop. It can easily be shown that |HBP ( jωRX )| ∼ = 1/2, meaning that the passband gain is independent of α. Since only differential quadrature signals of the RX-LO are available, there are two practical choices for α: 0 (π ) and −π/2 (π/2). The type I implementation is shown in Fig. 5.33. The resulting BPF has one zero at −sp and one zero at infinity. Realization based on the second choice, called type II (Fig. 5.34), which doesn’t have a finite zero. To determine which type is the better candidate, we need to carry out a stability analysis. Before performing such an analysis, let’s present the complete transmitter schematic with an on-chip notch filter (Fig. 5.35). Details of the building blocks are outlined in Section 5.9. The quadrature TX mixer, which is composed of small unit cells, up-converts the differential baseband signals and injects the resulting RF currents into the primary of a transformer. The center of this LC load is adjusted to the TX frequency by switchable capacitor arrays. After differential-to-single-ended

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(a)

(b)

FIGURE 5.33

(a) High-Q bandpass filter type I; (b) pole–zero diagram.

(a)

(b)

FIGURE 5.34

(a) High-Q bandpass filter type II; (b) pole–zero diagram.

137

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FIGURE 5.35

Transmitter with an on-chip notch filter.

conversion, the secondary of the transformer capacitively drives an on-chip PA driver whose load is the 50- input impedance of the external PA. The feedback path of the notch filter takes its input from the PA driver output, and after bandpass filtering, injects the final RF currents into the primary of the same transformer. This effectively creates a notch at the output impedance seen by the PA driver at the RX frequency.

5.7

FEEDBACK-BASED TRANSMITTER STABILITY ANALYSIS

In this section we study a stability analysis to choose the best structure (type I or II) for the bandpass filter. First, for both cases one must be careful to avoid a positive feedback and as a result, oscillation. Use of a differential-to-single-ended transformer makes this task perilous, as depending on the secondary and primary orientation, the polarity of differential-to-single-ended conversion would change. This uncertainty can be resolved by placing cross-point switches after the lowpass filters to change the polarity when required. Now, let’s focus on the stability of type I–based implementation, as shown in Fig. 5.36. We assume that no poles and zeros exist at the PA-driver output at around operation frequency: for example, from 1 to 3 GHz if the operational frequency is 2 GHz. Moreover, all the other high- and low-frequency poles are neglected. Consequently, the bandpass filter of the feedback path and the LC load of the TX modulator are the only building blocks contributing poles and zeros. As opposed to the feedback path, the LC load offers two modest-Q complex poles at the operational frequency plus a zero at dc. The Bode plots of the loop gain are presented in Fig. 5.36 [30]. In this Bode plot it has been assumed that the center of the LC load is tuned at ωRX

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FIGURE 5.36

139

Stability analysis when the high-Q BPF is type I.

rather than ωTX (Fig. 5.36). This assumption means that the Q vlaue of the LC load is low enough not to have an appreciable roll-off at the RX frequency. This is only for the sake of simplification and would not change the end result. Over a small frequency range around the RX frequency, [ωRX − (ωRX /2Q BPF ), ωRX + (ωRX /2Q BPF )], the loop gain is maximum and the overall phase shift is zero. As we depart further from the RX frequency, high-Q poles of the feedback path unveil their impact on the magnitude, causing roll-off at −20 dB/dec. They also cause the Bode phase to rise sharply to +45◦ at the lower knee and to decrease to −45◦ at the upper knee. So in this narrow frequency region the phase is the steepest. Due to the modest Q of the poles of the LC load, the magnitude slope changes by another 20 dB/dec, to −40 dB/dec, at a relatively large offset (±ωRX /Q LC ) away from both sides of the center frequency. Moreover, at these two knees the phase becomes ±135◦ . As observed from the Bode diagram, there are two crossover points where the magnitude becomes 0 dB. In order to have a stable feedback loop, the associated phases for these two points must remain in [−180◦ , 180◦ ] (positive phase margin (PM)). If the phase at the right crossover point is −180◦ + φ, it is 180◦ − φ at the left crossover ponit. Thus, the PM at the right crossover point, PMR , and the PM at the left, PML , are both equal to φ. Now, let’s study the Bode diagram when the feedback path is based on the type II structure (Fig. 5.37). As was pointed out, around the operational RF frequency, the magnitude of the loop gain is quite similar to that of type I–based implementation, whereas the phase plot is just shifted down by −90◦ . Right and left phase margins, PMR and PML , are now unequal and, in fact, PMR is the determining (limiting) factor for the stability. More important, PMR is now smaller than that of type I–based structure, which results in a loose stability. As inferred from Fig. 5.36, with a first-order lowpass filter the type I–based realization remains unconditionally stable regardless of the loop gain. On the contrary,

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FIGURE 5.37

Stability analysis when the high-Q BPF is type II.

in a type II feedback path, a large loop gain will make the feedback unstable by pushing PMR to be negative. The stability of the feedback can also be examined using root-locus plots [30], and the same conclusions must be obtained. To do this, let us assume that Z LC (s) is the LC-load impedance and is given by Z LC (s) =

s2

K1s 2 + (ωTX /Q LC )s + ωTX

(5.12)

in which K 1 is a constant and can be calculated in terms of RLC values. The transfer function of the bandpass filter in the feedback path is given by K 2 HBP (s), in which K 2 is another constant proportional to BPF gain, and HBP (s) is given by (5.11). The closed-loop transfer function is given by Hclosed-loop (s) =

Z LC (s) 1 + K 2 Z LC (s)HBP (s)

(5.13)

Thus, the poles of the feedback system are the zeros of the closed-loop system. In this way, the high-Q poles of the feedback path eventually become high-Q zeros of the closed-loop system, which is the cause of the notch at the RX frequency. Moreover, the closed-loop poles (roots of the characteristic equation) of the transfer function are the solutions to the equation 1 + K 2 Z LC (s)HBP (s) = 0. When K 2 or, equivalently, the loop gain increases from 0 to infinity, trajectories of the closed-loop poles start from an open-loop pole and end at an open-loop zero, which can be either finite or infinite. As depicted in Fig. 5.38(a), for the type I–based implementation when the LPF is first order, all four closed-loop poles remain on

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(a)

141

(b)

∗ FIGURE 5.38 Root-locus plots. PLC , PBPF , and their conjugates are the poles coming from the LC load and the feedback path, respectively: (a) when the BPF is type I; (b) when the BPF is type II.

∗ the left side of the s-plane and the feedback is unconditionally stable. PLC and PLC ∗ are poles from the LC load, and PBPF and PPBF are those of the BPF. Calculations reveal that even for a second-order lowpass filter the feedback becomes stable over a wide range of loop gain, and for typical sizes of the TX components no additional compensation is required. However, the situation is very different for the type II–based feedback path whose root–locus is plotted in Fig. 5.38(b). The relative distances between the poles are scaled to fit the trajectories in the plot. Now, by increasing the loop gain, two of the trajectories cross the imaginary axis and enter the right-hand side of the s-plane, which drives the feedback loop toward instability. Since type I is more suited for our application, as it results in a more reliable stability, we choose this structure to implement the WCDMA transmitter with an integrated notch filter. Therefore, in the remainter of the chapter we focus on this structure.

5.8 IMPACTS OF NONIDEALITIES IN FEEDBACK-BASED TRANSMISSION In this section, similar to the feedforward RX section we review the nonideal effects in the feedback TX. 5.8.1

Noise Requirements of the Feedback Path

The notch filter attenuates the receiver-band noise of the transmitter. However, the feedback path adds its own noise. In this section we consider the noise sources, beginning with the noise contribution of the up-conversion mixer. Fortuitously, these noise components are eventually nulled out by the notch filter using a mechanism similar to that by which the TX output signal is suppressed. Noise sources of the

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(a)

(b)

FIGURE 5.39 (a) Noise contribution of the feedback path. (b) Due to harmonic downconversion, the TX high-frequency noise components can be aliased to RX frequency.

lowpass filters and the down-conversion mixer can be modeled with an effective input-referred noise Vn [Fig. 5.39(a)], similar to what is modeled in a zero-IF receiver design [31]. The transfer function by which this input-referred noise appears at the output can be readily calculated by H (s) = −LG(s)/[1 + LG(s)]. At the frequency of interest, f RX , since the loop gain is large, this transfer function approaches unity. Therefore, at f RX , Vn appears at the output almost untouched. It is confirmed by simulations as well as measurement results that the RX-band noise is limited to this noise and the TX noise is suppressed by the null. Thus, the target RX-band noise at the transmitter output, −160 dBc/Hz, is exactly the upper bound for the input-referred noise of the feedback path, Vn . Harmonic down-conversion (HD) is another undesirable phenomenon that requires special attention. At the PA-driver output, noise components located at odd harmonics of f RX can be down-converted by the LO harmonics3 and aliased on top of desired components at around dc. Once aliased, they cannot be distinguished from the desired components and eventually are up-converted to the RF at around the fundamental. For example, Fig. 5.39(b) explains the case where noise components 3 This

can be due to the LO harmonics or to the mixer structure such as hard-switching.

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of the TX at around 3 f RX are down-converted by the third harmonics of the RXLO in the feedback path. Having up-converted by f RX , they are aliased into the RX band. Fortunately, this HD mechanism is not important at all, for a few reasons. First, in a hard-switching LO, which is almost the most brutal nonlinearity of all, the conversion gain at the third harmonic is 1/3 (−9.5 dB) of the fundamental. Second, the PA-driver noise contribution is almost insignificant and the TX noise is dominated primarily by the prior circuits, especially the TX modulator. However, the LC load of the mixer eliminates the problem by heavily attenuating noise components at around the third and all higher-order harmonics.

5.8.2

Linearity Requirements of the Feedback Path

The presence of a strong transmitter signal imposes stringent linearity requirements on the RF buffer and the down-conversion mixer of the feedback path. Due to thirdorder nonlinearity, the strong TX signal intermodulates with the noise components at the image frequency, 2 f TX − f RX , and may increase the noise floor through aliasing them into the RX band (Fig. 5.40). Prior to estimating the required IIP3, it should be highlighted that third-order nonlinearity of post downconversion where the TX signal is filtered out significantly is quite relaxed and is not a concern. Now, let’s model the TX signal with a sinusoidal of ATX cos(ωTX t + φTX ) and the noise component at the image frequency with An,image cos(ωn,image t + ωn,image ). For the reason mentioned above, third- order nonlinearity of the RF section only is considered and is modeled with an input–output relation of y = α1 x + α3 x 3. A simple calculation reveals that the resulting noise component at the RX band referred to the input is equal to n aliased (t) =

FIGURE 5.40

3 a3 2 A An,image cos(ωRX t + 2φTX − φn,image ) 4 a1 TX

Impact of third-order nonlinearity of the feedback path.

(5.14)

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If the target noise floor due to this mechanism is −166 dBc/Hz, and the noise floor at the image frequency is assumed to be as large as −152 dBc/Hz,4 for a +3-dBm TX power at the RF-IC output the required IIP3 is found to be +14 dBm. This is a challenging linearity specification but is feasible with the choice of the right topology. 5.8.3

Impact of Quadrature Phase and Gain Errors in the Feedback Path

Suppose that in the bandpass filter of the feedback path in Fig. 5.33(a) there is a quadrature phase error of φ.5 Therefore, the upper arm is clocked by cos ωRX t and the lower arm by sin(ωRX t + φ). Let’s calculate the output vs. the input signal:
Vout (t) = cos ωRX t

t −∞

h LP (t − τ )Vin (τ ) cos ωRX τ dτ

+ sin(ωRX t + φ)




t −∞

h LP (t − τ )Vin (τ )

× sin(ωRX τ + φ) dτ

(5.15)

Assuming that |φ|  1, after straightforward math it is shown that Vout (t) = Vin (t) ∗ [h LP (t) cos ωRX t] + φ sin 2ωRX t(Vin (t) ∗ [h LP (t) cos ωRX t] − φ cos 2ωRX t(Vin (t) ∗ [h LP (t) sin ωRX t])

(5.16)

Equation (5.16) is illustrated graphically in Fig. 5.41. The two undesirable terms are mapped to the two parasitic paths, in which the input signal passes through two highQ bandpass filters with impulse responses h LP (t) cos ωRX t and h LP (t) sin ωRX t and is then shifted in frequency by ±2 f RX . For a sinusoidal input x(t) = A x cos(ωRX − ωm )t (ωm  ωRX ), the desired path results in a sinusoidal output that can be written as ydesired (t) = A y cos[(ωRX − ωm )t + φ y ]. However, the undesired path in Fig. 5.41 leads to an output at the mirror frequency: yundesired (t) = φ A y sin[(ωRX + ωm )t + φ y ]. That means that the input signal is flipped over f RX in the frequency domain and after scaling by φ is added to the output of the desired path as undesired noise. This increases the noise floor by a factor of 1 + (φ)2 , which is quite insignificant for practical values of quadrature error. For example, even a quadrature error as large as 10◦ increases the noise floor by only 0.13 dB. A similar analysis can be applied for the gain error between the two quadrature paths in Fig. 5.33. The conclusion is also the same as the quadrature phase error with an equivalent system (Fig. 5.41).

4 This

is the measured noise floor at the image frequency. brevity we consider quadrature phase error between the LO signals. However, the analysis remains valid for a delay mismatch between the I and Q paths.

5 For

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FIGURE 5.41

5.8.4

145

Impact of quadrature LO phase error in the feedback path.

RX-LO Feedthrough and RX-LO Leakage

The mixers in the feedback path are clocked by the RX-LOs, and we must ensure that the RX-LO leakage doesn’t violate the transmitter mask. Let’s study different mechanisms by which the RX-LO can leak to the PA-driver output. The LO leaking through the down-conversion mixer of the feedback path is not important, as it is neutralized by the following lowpass filter. The residual LO of this mechanism is also up-converted to twice the frequency or down-converted to dc via the second mixer. The RX-LO leakage through the up-conversion mixer enters into the primary of the transformer, similar to the RF current of the TX modulator. Thus, this leakage component is subject to attenuation by the zero of the transfer function. Another practical concern may arise from the leakage of receiver LO to the PAdriver output through some sort of parasitics path such as substrate. This is not of importance as well, as the feedback senses this leakage and weakens it by storing appropriate dc values at the LPF outputs. From feedback theory it can easily be shown that this leakage is lowered by the loop gain. The residual LO leakage will be further attenuated by an additional 45 to 50 dB of duplexer isolation before reaching the receiver or antenna. The measured LO feedthrough is −45 dBm at the RF-IC output; after experiencing a 24-dB gain of the external PA, the leakage at the antenna decreases to less than −66 dBm. This value is well below the spurious emission requirements, −60 dBm. Moreover, on the receiver side this only results in a fixed offset that would be corrected by the dc-cancellation loop. Nevertheless, well-known layout techniques and proper sizes are utilized to minimize this leakage. 5.8.5

Phase Noise Requirements

Since receive-band frequency components of the transmitter RF signal are filtered out by the notch filter, the TX-LO phase noise requirement at RX frequency becomes trivial. However, this is not the case for the RX-LO. Let us assume that the quadrature

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RX-LO signals in Fig. 5.33 are noisy and are given by cos[ωRX t + φ I (t)] and sin[ωRX t + φ Q (t)], in which φ I (t) and φ Q (t) are small phase fluctuations representing the phase noise in the I and Q paths, respectively. We can decompose the phase fluctuations into common mode, (φ I + φ Q )/2, and differential mode, (φ I − φ Q )/2. Quadrature signals are usually obtained either from a quadrature oscillator (QOSC) or a divide-by-2 divider. It has been shown that in a QOSC, the phase noise from internal noise sources appear as common mode at quadrature outputs [32]. A similar predicament holds true in any ring oscillator–based dividers, including divide-by-2 as a special case [33]. Clock buffers of each quadrature LO signal also contribute to the phase noise. However, since the noise sources associated with each phase are independent, the resulting phase fluctuations are separated equally as common and differential modes. Typically, the common-mode phase noise is dominant. First, we start exploring the aftermath of common-mode phase noise. The cosine and sine terms have identical arguments equal to ωRX t + φ(t), where φ(t) = φ I (t) = φ Q (t). This can be perceived as the two arms in Fig. 5.33 being clocked with quadrature LOs whose frequency is equal to ωRX + dφ/dt. For small variations of φ(t) (dφ/dt  lowpass filter bandwidth), we can visualize this as the center of the lowpass filter sliding around RX-LO in response to the phase noise. Although this is a correct observation, a quasistatic approach cannot be utilized to explain the impact of phase noise components at frequency offsets around f RX − f TX , which potentially can alias the strong transmitter signal on top of the desired components. Instead, we use rigorous mathematical analysis as follows. In the presence of common-mode phase noise, (5.6) and (5.7) are modified to
t h LP (t − τ )Vin (τ ) cos[ωRX τ + φ(τ )] dτ (5.17) VU (t) = −∞


VL (t) =

t −∞

h LP (t − τ )Vin (τ ) sin[ωRX τ + φ(τ )] dτ

(5.18)

and the resulting RF output of the BPF is calculated to
Vout (t) = cos[ωRX t + φ(t)]

t

−∞




+ sin[ωRX t + φ(t)]
=

t −∞

h LP (t − τ )Vin (τ ) cos[ωRX τ + φ(τ )] dτ

t

−∞

h LP (t − τ )Vin (τ ) sin ωRX τ + φ(τ )] dτ

Vin (τ )h LP (t − τ ) cos [ωRX (t − τ ) + φ(t) − φ(τ )] dτ

(5.19)

Knowing that the phase fluctuations are very small (|φ(t)|  1), (5.19) is simplified to more physically understandable terms Vout (t) = Vin (t) ∗ [h LP (t) cos ωRX t] − φ(t) {Vin (t) ∗ [h LP (t) sin ωRX t]} − [φ(t)Vin (t)] ∗ (h LP (t) sin ωRX t)

(5.20)

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FIGURE 5.42 Impact of common-mode phase fluctuations between RX-LO quadrature signals.

Equation (5.20) is mapped to the equivalent signal flow diagram in Fig. 5.30. The first term in (5.20) is the desired term and maps to the upper arm. For the second term, which is mapped to the middle arm, the signal passes through a high-Q bandpass filter with an impulse response given by h LP (t) sin ωRX t and then multiplied to the phase fluctuations whose spectral frequency is concentrated around dc. However, the transmitter signal was intensely attenuated by the BPF, and its reciprocal aliasing by the jitter is quite negligible. The tormenting term is the third one, which is mapped to the third arm in Fig. 5.42. The signal is first modulated by the jitter before passing through the bandpass filter. Consequently, the frequency components of φ(t) at f RX − f TX alias the strong transmitter signal into the RX band. This imposes a stringent phase noise requirement (assuming it is mainly common mode between the I and Q signals), which must be better than −163 dBc/Hz6 at an offset of f RX − f TX . However, such a phase noise must already be achieved in RX, due to reciprocal mixing of TX leakage with the RX-LO. We can perform similar calculations to understand the consequences of differential-mode phase fluctuations between quadrature signals. It is proved that the impact can be presented in the signal flow diagram in Fig. 5.43. Once again, in the third arm the jitter is multiplied to the TX signal prior to high-Q bandpass filtering, which aliases the TX signal into the RX band. This leads to the same stringent requirement for differential-mode phase fluctuations that was calculated earlier for the common mode.

6 This

would cause an RX-band noise of −163 dBc/Hz at the TX output.

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FIGURE 5.43 signals.

5.9

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Impact of differential-mode phase fluctuations between RX-LO quadrature

TRANSMITTER BUILDING BLOCKS

Figure 5.44 presents down-conversion mixer and lowpass filter circuits. A source follower buffers the PA-driver output and capacitively drives a passive mixer. This architecture allows us to apply PA-driver output directly without the need to attenuate the RF signal, which relaxes the noise requirement. Since no dc currents are involved, the switches of the passive mixer do not contribute any flicker noise [22]. Moreover, current source devices, M1 and M2 , and common-gate transistors, M3 and M4 , are designed large enough to lower the overall flicker noise corner down to a few kilohertz. Unlike the traditional current-mode switching mixer [21], the switches here commutate voltage rather than current. Thus, the capacitor is not selected arbitrarily large but, instead, is optimized to trade linearity with gain and noise. The optimum size is simulated to be 250 fF, which corresponds to an impedance of about −j320  at around 2 GHz. Hence, compared to the series combination of 50- output impedance of the source follower, 50- switch resistance, and 155- input impedance of the common-gate buffer, the capacitor impedance contributes a significant portion. Moreover, the capacitor C1 , in parallel with the impedance seen from the sources of M3 and M4 , forms a lowpass filter whose cutoff frequency is tuned to attenuate the strong transmitter signal at IF. This filtering significantly lowers the swing across C1 and as a result, improves linearity. The simulated IIP3 of the down-conversion circuit referred at source follower input is better than +15 dBm over different process corner and temperature variations (PVT). The RC load of the common-gate buffer introduces an additional stage of lowpass filtering.

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FIGURE 5.44

149

Circuit of a down-conversion mixer and lowpass filter.

Clocked by the same down-conversion LO, a quadrature mixer up-converts the LPF outputs to the RF (Fig. 5.45). Only one quadrature channel is shown. The RX-LO signals are applied to the switch transistors, M1 and M2 , to commutate the dc current source and up-convert it to the RF frequency. Since LPF outputs are biased at around 1.2 V, the transconductance transistors,M3 to M6 , are on top of the switch transisters, as opposed to the arrangement in a conventional Gilbert mixer [34]. Due to the double-balanced structure, the RX-LO feedthrough is theoretically zero, and the transistors are sized and laid out carefully to minimize the feedthrough, although it would eventually be rejected by the notch filter. The differential output currents of the up-conversion mixer are fed to the primary of an integrated transformer (Fig. 5.35).

FIGURE 5.45

Circuit of the up-conversion mixer of the feedback path.

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FIGURE 5.46

Circuit of a TX modulator unit cell.

The transmitter mixer modulates the IQ baseband signals and injects the resulting RF signal to the primary of the same transformer. Arrays of capacitors are used to tune the center of the impedance at the primary. The simulated tuning range is 230 MHz. Composed of small unit cells, the transmitter mixer embeds some portion of the TX gain control. Figure 5.46 shows the unit cell, and once again, only one quadrature channel is shown. The degeneration resistor improves the linearity of the voltage-tocurrent conversion of the baseband signals. Furthermore, this resistor also lowers the capacitance seen at the mixer input, which otherwise can be large and make design of a baseband filter difficult. The voltage headroom consumed by this resistor is the main driving force for using a 2.5-V supply for the modulator. Once again, because of its double-balanced structure, the LO-RF isolation is ideally infinite. Usually, the TX calibration handles the residual LO feedthrough [34,35]. Fabricated as a test chip mainly to verify the notch filter performance, the gain of the TX modulator is controlled by only 30 dB in 6-dB steps (32-unit mixers). After differential-to-single-ended conversion, the secondary of the transformer capacitively drives the PA driver whose gain is programmable as well (Fig. 5.35). A 6-dB gain control is implemented in the PA driver. The PA driver sinks its bias current from a 2.5-V supply through an RF choke to feed 50- impedance of the external PA. It consumes 14 mA and its noise contribution at frequencies around 2 GHz is less than −170 dBc/Hz, when it delivers 3 dBm of power to a 50- load.

5.10

FEEDBACK-BASED TRANSMITTER MEASUREMENT RESULTS

The test chip was fabricated in a 65-nm digital CMOS process, and its die micrograph is shown in Fig. 5.47. The active area is 0.153 mm2 . Two integrated divide-by-2

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FIGURE 5.47

151

Die photo of the transmitter with an on-chip notch filter.

dividers accommodate TX and RX quadrature LO clocks through dividing externally applied 4-GHz differential signals. The contribution of the RX (feedback path) divide-by-2 and its associated clock buffers on the phase noise at 80-MHz offset and above is designed to be less than −170 dBc/Hz. phase noise requirements of the TX counterparts are very relaxed, which are now determined by the transmitter EVM. Additionally, to feed the RX divider, the signal generator output at double frequency passes through a tunable RF bandpass filter to suppress the noise components (including phase noise) at 80 MHz and above. The transmitter transfer functions with and without notch filter are measured and compared against simulation results as shown in Fig. 5.48(a). The transmitter LO is set at the edge of band II (i.e., 1850 MHz) and the receiver LO is 80 MHz higher. The quadrature baseband signals are applied externally whose frequency is swept from almost dc to about 200 MHz. As shown in Fig. 5.48(a), the feedback establishes a notch of about 19.4 dB at the receiver frequency, attenuating the noise of the transmitter chain proportionally. This allows the TX to be optimized for the lowest power consumption while meeting the stringent noise requirements. Without the feedback, the transmitter rejection at 80 MHz away is only 1.9 dB, set by the modest roll-off of the on-chip transformer. The TX passband gain changes negligibly when the feedback turns on. The receiver-band noise for 3.3-dBm output power with filtering enabled is shown in Fig. 5.48(b) and is about −160.4 dBc/Hz, dominated by the noise of the feedback path. The transmitter LO is at 1850 MHz. If a receiver-band noise floor of better than −160.4 dBc/Hz is required, what is needed is to lower the input-referred noise of the feedback path by increasing its power consumption. For example, doubling the power consumption of the feedback path (less than 5 mA extra current) lowers the noise floor by 3 dB. Although this transmitter covers all WCDMA higher bands, the results are intentionally provided for band II, which is more challenging, as the separation between the

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(a)

(b)

FIGURE 5.48 (a) Measured and simulated transfer functions for band II; (b) simulated and measured RX band noise with 3.3-dBm TX output power.

RX and the TX channels is the least. To prove the robustness of the scheme, the transfer functions of the transmitter are also measured vs. temperature [Fig. 49(a)]. Over a temperature range of −30◦ C to +85◦ C, the null depth achieved is at least 17 dB, better than what is needed for our application. Loop gain drop is the cause of the null-depth reduction at higher temperatures. This can be compensated utilizing proper bias currents, as opposed to the simple diode-connected biasing used in this test chip. With a 3.3-dBm output power, the transmitter noise at RX band is also measured under the same temperature conditions. At room temperature the RX-band noise is −160.4 dBc/ Hz, which is slightly degraded by about 0.5 dB at 85°. This degradation is not because of shallower null depth, but it is because of natural increase in input referred noise of the feedback path at higher temperatures. With the filtering enabled, an ACLR

(a)

(b)

FIGURE 5.49 (a) Measured and simulated transfer functions vs. temperature for band II; (b) measured RX band noise vs. temperature with 3.3-dBm TX output power.

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FIGURE 5.50 Measured output spectrum at 3.3-dBm power vs. the emission mask.

of −44 dBc at ±5 MHz and −58 dBc at ±10 MHz is measured (Fig. 5.50). The corresponding EVM is 4.5%.

5.11

CONCLUSIONS AND DISCUSSION

In conclusion, two filtering techniques that allow for integration of SAW filters in cellular transceivers have been presented. The first technique removes blockers in SAW-less wireless receivers and eliminates the need for an external SAW filter in either a 2G or 3G a receiver. The circuit employs a feedforward cancellation to produce a sharp frequency response in the low-noise amplifier. The required notch filtering is achieved efficiently through down-conversion, translating the IF highpass filter frequency response to RF. This eliminates the need for the front-end external SAW filter. Apart from filtering, one of the challenging requirements of the design is the ability to tolerate blockers as large as 0 dBm. A common-gate amplifier is employed to achieve the linearity required at the input, and to minimize the noise contribution of the filtering devices, a passive device is used for the up-conversion mixer. In certain applications where the filtering is critical but the blocker level is not as strong as those in GSM, the down-conversion mixer power consumption could be lowered significantly. A good example is 3G applications [13], as mentioned earlier, where due to the TX leakage in the receiver band, typically an external SAW filter at the input is required. Although to relax the receiver front-end linearity a notch filer at the TX frequency (190 MHz away for band I, for example) is needed, the blocker strength is fairly weak, around −20 to −30 dBm for most typical duplexers. For such a case, the power dissipation and noise contribution of the filtering path are reduced substantially.

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TABLE 5.1

Summary of Receiver Performance

Parameter Gain NF In-band IIP3 3-dB bandwidth Stopband rejection S11 Current drain Power supply Operating temperature Active die area Technology

Measured, w/ Filtering

Simulated, w/ Filtering

20.9 dB 6.8 dB — 4.5 MHz >21 dB <−10 dB 29 mA

21.3 dB 5.8 dB — 6 MHz >23 dB <−10 dB 29 mA

Measured, w/o Filtering

23.4 dB 3.9 dB 2.6 dBm 250 MHz 3 dB <−10 dB 8 mA 1.2/2.5 V −20 to 85◦ C 0.28 mm2 65-nm digital CMOS

Simulated, w/o Filtering 23.5 dB 3.5 dB 2.8 dBm 220 MHz 3 dB <−10 dB 8 mA

A summary of performance is shown in Table 5.1. Without filtering, the LNA has a passband gain of 23.4 dB and a noise figure of 3.9 dB. When the filter is active, the noise figure degrades by 2.9 dB but is still well below the required blocking noise figure. The LNA has a 3-dB bandwidth of about 250 MHz, which reduces to only 4.5 MHz when the filter turns on. A stopband attenuation of better than 21 dB is achieved. The LNA is biased at 8 mA, and each of the active mixers drains 10.5 mA. The excess power consumption of mixers is practically negligible, as they only need to turn on at the infrequent event of receiving a large blocker. The device is fabricated in a 65-nm process and is functional over a temperature range of −20 to −80◦ C. All measurements agree very well with simulation results. In addition to the feedforward receiver filtering scheme, a feedback-based on-chip notch filter is introduced to attenuate receiver-band noise in a WCDMA transmitter. To do this, a selective high-Q bandpass filter passes the RX band noise at the PA driver output and after amplifying, feeds the noise back to the PA driver input. This feedback system introduces a null at the output impedance seen by the PA driver to reject the RX band noise without affecting the transmitter signal. The IF frequency translation technique is used to realize the bandpass filter, which allows us to control the width of the notch by adjusting its lowpass filters. Furthermore, we performed stability analysis to choose the best combination of LO phases for the bandpass filter in the feedback path. We also analyzed the impact of various imperfections, such as quadrature phase and gain errors, LO feedthrough, harmonic down-conversion, and phase noise. Finally, we presented a 65-nm CMOS WCDMA transmitter which achieves an output noise level of −160.4 dBc/Hz at 80 MHz, of offset, while dissipating only 65 mW. A summary of performance is shown in Table 5.2. The technique allows us to eliminate the transmitter SAW filter while passing stringent noise requirements with minimum power consumption, which paves the way for more integration and fewer external components.

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APPENDIX

TABLE 5.2

155

Summary of Transmitter Performance

Parameter Maximum output power 1dB compression RX-band noise RX-band rejection ACLR at ±5 MHz EVM Power dissipation Power supply Active die area Technology

With Filtering

Without Filtering

3.3 dBm 9 dBm −160.4 dBc/Hz 19.4 dB −44 dBc 4.5% 64 mW

3.3 dBm 9 dBm −152.1 dBc/Hz 1.9 dB −46 dBc 4% 55 mW

1.2/2.5 V 0.153 mm2 65-nm digital CMOS

APPENDIX Instead of introducing a notch at RX frequency to attenuate the noise, we can attenuate all frequency components of the TX output, except of course the TX signal. This can be done as depicted in Fig. 5A.1, which is quite similar to Fig. 5.31 except that lowpass filters in the feedback path are replaced with bandpass filters. Additionally, the up- and down-conversion mixers are now clocked by the TX quadrature LOs. The lower cutoff frequency, f L , should be large enough to block the TX signal, but

FIGURE 5A.1

Alternative method of RX band noise attenuation.

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small enough to pass the TX noise components at the RX frequency. The upper cutoff frequency, f H , just needs to be low enough to block the up-converted TX components at 2 f TX of the first mixer [23]. Once again, since the loop gain at the TX frequency is zero, the TX signal is not affected, whereas the loop gain is set large at other frequencies, including RX. As a consequence, the impedance seen by the PA driver is lowered at those frequencies. Although this scheme outperforms in terms of linearity, unfortunately the underlying feedback is unstable and requires compensation. Acknowledgment The author would like to thank Ahmad Mirzaei from Broadcom for very helpful discussions and feedback. REFERENCES 1. S. Tadjpour, S. Cijvat, E. Hegazi, and A. A. Abidi, “A 900-MHz dual-conversion lowIF GSM receiver in 0.35-µm CMOS,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1992–2002, Dec. 2001. 2. A. A. Abidi, “Direct-conversion radio transceivers for digital communications,” IEEE J. Solid-State Circuits, vol. 30, no. 12, pp. 1399–1410, Dec. 1995. 3. H. Darabi et al., “A fully integrated quad-band GPRS/EDGE radio in 0.13 µm CMOS,” in Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pp. 206–207, Feb. 2008. 4. Y. Akamine et al., “Polar loop transmitter with digital interface including a loop-bandwidth calibration system,” in Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pp. 348–349, Feb. 2007. 5. M. Elliott et al., “A polar modulator transmitter for EDGE,” in Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pp. 188–189, Feb. 2004. 6. O.-H. Bonnaud et al., “A fully integrated SoC for GSM/GPRS in 0.13 µm CMOS,” in Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pp. 482–483, Feb. 2006. 7. O. E. Erdogan, R. Gupta, D. G. Yee, J. C. Rudell, J. Ko, R. Brockenbrough, S. Lee, E. Lei, J. L. Tham, H. Wu, C. Conroy, and B. Kim, “A single-chip quad-band GSM/GPRS Transceiver in 0.18 µm Standard CMOS,” in Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pp. 318–319, Feb. 2005. 8. A. Molnar et al., “A single-chip quad-band (850/900/1800/1900 MHz) direct-conversion GSM/GPRS RF transceiver with integrated VCO’s and fractional-N synthesizer,” in Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pp. 232–233, Feb. 2002. 9. Third-Generation Partnership Project (3GPP), TS 25.101 UE Radio Transmission and Reception (FDD), vol. 3.0.1, 2000. 10. C. Eder, G. Fischerauer, P. Hagn, and G. Riha, “SAW filters for 3G systems: a quantum leap in size and passive integration is ahead,” in Proc. IEEE Ultrasonics Symposium, pp. 338–339, 2001.

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11. V. Aparin, G. J. Ballantyne, C. J. Persico, and A. Cicalini, “An integrated LMS adaptive filter of TX leakage for CDMA receiver front ends,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1171–1182, May 2006. 12. S. K. Reynolds, B. A. Floyd, T. J. Beukema, T. Zwick, U. R. Pfeiffer, and H. A. Ainspan, “A direct-conversion receiver integrated circuit for WCDMA mobile systems,” IBM J. Res. Deve., vol. 47, pp. 337–353, 2003. 13. F. Gatta, D. Manstretta, P. Rossi, and F. Svelto, “A fully integrated 0.18 µm CMOS direct conversion receiver front-end with on-chip LO for UMTS,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 15–23, Jan. 2004. 14. P. Eloranta, P. Seppinen, S. Kallioinen, T. Saarela, and A. Parssinen, “WCDMA Transmitter in 0.13 µm CMOS using direct-digital RF modulator,” in Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pp. 340–341, 2007. 15. D. L. Kaczman, M. Shah, N. Godambe, M. Alam, H. Guimaraes, L. M. Han, M. Rachedine, D. L. Cashen, W. E. Getka, C. Dozier, W. P. Shepherd, and K. Couglar, “Single-chip tri-band (2100, 1900, 850/800 MHz) WCDMA/HSDPA cellular transceiver,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1122–1132, May 2006. 16. X. Yang, A. Davierwalla, D. Mann, and K. G. Gard, “A 90-nm CMOS direct conversion transmitter for WCDMA,” in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symposium 2007, pp. 17–20, 2007. 17. C. Jones, B. Tenbroek, P. Fowers, C. Beghein, J. Strange, F. Beffa, and D. Nalbantis, “Direct-conversion WCDMA transmitter with −163dBc/Hz noise at 190-MHz offset,” in Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pp. 336–337, 2007. 18. D. Papadopoulos and Q. Huang, “Linear uplink WCDMA modulator with −156-dBc/Hz downlink SNR,” in Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pp. 338–339, 2007. 19. G. Brenna, D. Tschopp, J. Rogin, I. Kouchev, and Q. Huang, “A 2-GHz carrier leakage calibrated direct-conversion WCDMA transmitter in 0.13 µm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1253–1262, Aug. 2004. 20. D. Shaeffer and T. H. Lee, “A 1.5-V, 1.5 GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745–759, May 1997. 21. M. Valla, G. Montagna, R. Castello, R. Tonietto, and I. Bietti, “A 72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner,” IEEE J. SolidState Circuits, vol. 40, no. 4, pp. 970–977, Apr. 2005. 22. H. Darabi and A. A. Abidi, “Noise in RF-CMOS mixers: a simple physical mode,” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 15–25, Jan. 2000. 23. H. Darabi, “A blocker filtering technique for SAW-less wireless receivers,” IEEE J. SolidState Circuits, vol. 42, no. 12, pp. 2766–2773, Dec. 2007. 24. J. Kulyk and J. Haslett, “A monolithic CMOS 2368 ± 30 MHz transformer based Qenhanced series-C coupled resonator bandpass filter,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 362–374, Feb. 2006. 25. S. Bantas and Y. Koutsoyannopoulos, “CMOS active-LC bandpass filters with coupledinductor Q-enhancement and center frequency tuning,” IEEE Trans. Circuits Syst. II, vol. 51, no. 2, pp. 69–76, Feb. 2004.

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26. B. Georgescu, H. Pekau, J. Haslett, and J. McRory, “Tunable coupled inductor Qenhancement for parallel resonant LC tanks,” IEEE Trans. Circuits Syst. II, vol. 50, no. 19, pp. 705–713, Oct. 2003. 27. J. Ge and A. dinh, “A 0.18 µm CMOS channel select filter using Q-enhancement technique,” in Canadian Conference on Electrical and Computer Engineering, pp. 2143–2146, 2004. 28. Y. C. Wu and M. F. Chang, “On-chip RF spiral inductors and bandpass filters using active magnetic energy recovery,” in IEEE Custom Integrated Circuits Conference (CICC’02), pp. 275–279, May, 2002. 29. A. V. Oppenheim, A. S. Willsky, and S. H. Nawab, Signals and Systems, 2nd ed. Upper Saddle Rever, NJ: Prentice Hall, 1996. 30. W. S. Levine, The Control Handbook. Piscataway, NJ: IEEE Press, 1996. 31. H. Darabi and A. A. Abidi, “A 4.5-mW 900-MHz CMOS receiver for wireless paging,” IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1085–1096, Aug. 2000. 32. A. Mirzaei, M. E. Heidari, R. Bagheri, S. Chehrazi, and A. A. Abidi, “The quadrature LC oscillator: a complete portrait based on injection locking,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1916–1932, Sept. 2007. 33. A. Mirzaei, M. E. Heidari, R. Bagheri, and A. A. Abidi, “Multi-phase injection widens lock range of ring-oscillator-based frequency dividers,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 656–671, Mar. 2008. 34. B. Razavi, RF Microelectronics. Upper Saddle River, NJ: Prentice Hall, 1998. 35. K. Y. Lee, S. W. Lee, Y. Koo, H. K. Huh, H. Y. Nam, J. W. Lee, J. Park, K. Lee, D. K. Jeong, and W. Kim, “Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 43–53, Jan. 2003.

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ADCs and DACs for Software-Defined Radio MICHIEL STEYAERT, PIETER PALMERS, and KOEN CORNELISSENS Katholieke Universiteit Leuven, Leuven, Belgium

6.1

INTRODUCTION

The analog-to-digital converter (ADC) in the receiving (RX) path and the digital-toanalog converter (DAC) in the transmitting (TX) path of a transceiver form a bridge between the analog front end and the digital signal processor (DSP) at the back end. Consequently, they are indispensable in any modern communication system. The shift to multi-mode transceivers increases their importance even further. A softwaredefined radio (SDR) system should be able to handle any modern communication standard. This should be achieved by reconfiguring the transceiver with software. This means that the settings and performance of the transceiver can be changed without a need for additional hardware. In an SDR system, the ADC and DAC should be fast and accurate enough for each communication standard. Moreover, due to the flexibility requirements of the multi-mode transceiver, the analog front end is often simplified, leading to tougher specifications for the ADC and DAC. As wireless systems are mostly battery operated, the power consumption of the ADC and DAC should be minimized. Furthermore, technology scaling can result in more difficult specifications for the ADC and DAC. The drive behind technology scaling is the fact that each step makes digital signal processing cheaper and cheaper. However, this is not true for analog signals. Because of noise and mismatch limitations, the area of analog blocks doesn’t scale the same as digital. Moreover, the low supply voltages make analog design even more complicated. Therefore, a general trend is to shift as much complexity as possible to the digital domain. For example, filtering in transceiver front ends is shifted as much as possible to the DSP. However, such measures tend to increase the requirements put on the ADC and DAC. For example, the bandwidth of the ADC should be higher to counteract the reduced aliasing suppression due to less Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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analog filtering. As a result, optimal design of the ADC and DAC becomes of utmost importance. In Section 6.2 the requirements for the ADC and DAC in wireless systems are summarized. In Section 6.3 we discuss and compare different options to obtain a multi-mode system. In Section 6.4 we describe briefly the requirements for reconfigurable systems. Sections 6.5 and 6.6 focus on the implementation of reconfigurable ADCs and DACs. Different architectures are evaluated, and methods to make them suitable for multi-mode reception are discussed. Section 6.7 concludes the chapter. The majority of the chapter deals with the implications of the SDR concept on data converters when more-or-less traditional transceiver concepts are used. Some interesting concepts that deviate from the traditional approach are introduced briefly.

6.2

ADC AND DAC REQUIREMENTS IN WIRELESS SYSTEMS

Each communication standard has different requirements for all parts of the transceiver: different carrier frequencies, bandwidths, TX-power and RX-sensitivity requirements, and so on. The derivation of building block specifications from a specified standard is a very complex task that involves a multitude of trade-off decisions, which is outside the scope of this chapter. Table 6.1 summarizes some numbers available in the literature [1–5], to serve as a frame of reference. Table 6.1 allows us to derive some general specifications of a flexible multistandard transceiver for current wireless standards. It should support: r r r r

Carrier frequencies from 400 MHz to 5 GHz Channel bandwidths up to 40 MHz An ADC dynamic range up to 90 dB Transmitter power up to 2 W

TABLE 6.1 Standard GSM EDGE GPRS CDMA2000 W-CDMA Bluetooth IEEE802.11a IEEE802.11b IEEE802.11n

Overview of Wireless Communication Standards Carrier Frequency

Channel Bandwidth

ADC Dynamic Range

Maximum TX Power

850–1900 MHz 850–1900 MHz 850–1900 MHz 450–2100 MHz 1900/2100 MHz 2.4 GHz 5 GHz 2.4 GHz 2.4/5 GHz

200 kHz 200 kHz 200 kHz 1.228 MHz 3.84 MHz 1.1 MHz 20 MHz 5.5 MHz 20/40 MHz

90 dB 87 dB 84 dB 80 dB 60 dB 66 dB 55 dB 55 dB 55 dB

2W 2W 2W 2W 100 mW 800 mW 1W 1W

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We use these numbers to evaluate the viability of the multi-standard transceiver architectures discussed, as they provide a sufficiently good frame of reference. If future standards are to be supported, these numbers have to be updated with appropriate estimates. 6.2.1

Evaluating ADC Feasibility

In general, the main specifications for the ADC are the channel bandwidth and dynamic range (DR) required. As indicated before, system-level choices will severely affect the specifications of the ADC: the choice of antialiasing filtering will affect the sampling frequency of the ADC; the DR required depends on many factors, such as variable-gain amplifier (VGA) gain, input sensitivity, and interferer levels. Evaluating the feasibility of a certain set of specifications is a difficult task since it is dependent on a large number of parameters, such as ADC topology, process technology, design choices, and so on. A rough estimate can be made by using a figure of merit (FOM). For ADCs the following FOM is commonly used: FOM =

P · 2BW

2ENOB

fJ/conversion

(6.1)

where P is the power consumption, BW the converted bandwidth, and ENOB denotes the effective number of bits achieved over this bandwidth when considering both noise and distortion [i.e., the signal-to-noise-and-distortion ratio (SNDR)]. The dimension of this FOM is energy per conversion, and hence it is a measure of the efficiency of the converter. Typical values of this FOM for state-of-the art ADC designs are around 1 pF/conversion. The best FOM reported in 2007 was 65 fJ/conversion [6]. When assuming that this FOM value can be achieved at all points in the performance space, it can be used to estimate the ADC power consumption. For example, using (6.1), the power consumption of a converter requiring 72 dB SNDR (i.e., 12 effective bits) over a bandwidth of 5 MHz can be estimated as follows: P = 65 fJ/conv. · 212 · 2 · 5 MHz = 2.66 mW

(6.2)

When comparing this estimation with real-world designs (e.g., [1,7]) one can see that it is an underestimation of real-world power. Nevertheless, this method is useful to give a generic idea of the feasibility of a certain set of specifications. 6.2.2

Evaluating DAC Feasibility

A very similar story holds for the DAC in the transmitter chain. Again system-level decisions have large impact on the specifications of this building block. The number of channels transmitted and out-of-band emissions will determine the linearity and noise requirements, the type of power amplifier will influence the DAC output power required, and so on.

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As for ADCs, a similar FOM-based technique can be used to evaluate the feasibility of a set of DAC specifications. The most commonly used FOM for telecommunication DACs is FOM =

2 N · BW P

MHz/mW

(6.3)

where P is the power consumption, N the number of bits, and BW the maximum frequency with a spurious free dynamic range (SFDR) larger than 6N − 1. For DACs the SFDR is used rather than the SNDR since most converters are limited by quantization noise instead of circuit noise, and hence the distortion components are dominant in the SNDR. The best FOM at present is 36,900 MHz/mW, reported in [8]. This value is used in the remainder of the chapter. For most telecommunication standards, a DAC SFDR of approximately 60 dB is sufficient.

6.3

MULTI-STANDARD TRANSCEIVER ARCHITECTURES

In this section we describe a set of tentative multi-standard transceiver architectures. The advantages and disadvantages of each implementation are discussed. A practical multi-standard transceiver can be a combination of more architectures. For example, a transceiver that should be able to cope with two low-bandwidth and one highbandwidth communication standard can be made using two parallel transceivers, whereby the low-bandwidth transceiver is made reconfigurable. 6.3.1

Parallel Transceivers

One could design a multi-standard transceiver by implementing a separate transceiver for each standard supported, as illustrated in Fig. 6.1. The digital back end has a separate DSP for each transceiver. This is a very power-efficient solution, as only the

ADC Front−end 1

DSP DAC

ADC Front−end k

DSP DAC

FIGURE 6.1

Parallel transceiver.

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parts that are required at a certain time should be activated. Moreover, each transceiver can be optimally designed for its intended communication standard. As front ends for the various standards are readily available, feasibility is not a problem. The main disadvantage of this approach is cost. Aside from the large engineering cost associated with implementing multiple transceivers, the extra area and external components required increase the manufacturing cost. Second, this solution is not flexible. If support for another standard is desired, a new transceiver has to be added to the system, which can only be achieved by a hardware redesign.

6.3.2

Software Radio

The other extreme is a software radio (SR), illustrated in Fig. 6.2. The ADC and DAC are connected to the antenna with only minimal analog circuitry (e.g., just the transmitting/receiving multiplexer). The idea is to shift all signal processing to the digital domain. The received signal is digitized as soon as possible, while the transmitting path has its digital-to-analog conversion as late as possible. The DSP is responsible for all signal processing, such as filtering, equalization, mixing, and (de)modulation. A first remark is that the DSP in such a system should be extremely powerful and therefore will be power hungry. The major advantage is that this architecture offers ultimate flexibility. If another communication standard is wanted, the DSP software can be reprogrammed to perform signal processing accordingly. An SR also allows us to process all desired standards at the same time. The downside is that the requirements for the ADC and DAC in an SR are tremendous. Due to the lack of analog mixing, the bandwidth of both the ADC and DAC is determined by the carrier frequency instead of the channel bandwidth. For the specifications outlined in Section 6.2, this results in a bandwidth requirement of at least 5 GHz. The Nyquist sampling theorem hence dictates a sample rate of at least 10 GS/s. Although this raw sample rate is achievable in modern CMOS technologies, the converter should also maintain a sufficiently high dynamic range over this range. Current state-of-the-art ADCs with bandwidths over 1 GHz are limited to 25 dB DR [9], while high-accuracy converters are limited to about 1 MHz of signal bandwidth [10]. Even if the FOM of [6] is achievable, (6.1) shows that an ADC with 5 GHz of bandwidth and a dynamic range of 100 dB would consume approximately 67 W.

ADC DSP DAC FIGURE 6.2

Software radio transceiver.

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Achieving simply the DR required by the most stringent standard (90 dB in Table 6.1) does not suffice for an SR. These requirements were derived such that the system can cope gracefully with the remaining in-band interferers after automatic gain control (AGC) and channel filtering. The lack of AGC in an SR requires that additional DR must be present to cope with varying input power levels. The absence of channel filtering means that the ADC needs extra DR to handle out-of-band interferers. As an example, consider an SR-based device that is receiving both a GSM and a wireless LAN (WLAN) signal. The device is positioned far from the GSM base station but immediately next to the WLAN base station. It might receive the GSM signal at −80 dBm while the WLAN signal received power is 20 dBm. To receive both signals linearly, another 100 dB of dynamic range is required in addition to the specifications in Table 6.1. In an SR transmitter the DAC is placed directly at the antenna of the transmitter. Therefore, the DAC should convert the modulated signal directly with sufficient precision, linearity, and speed. This comes down to a sample frequency that is at least twice the highest carrier frequency (5 GHz) (i.e., 10 GS/s). When considering an oversampling ratio (OSR) of 10 to alleviate the reconstruction filter design (see Section 6.6.2), the sample rate required becomes 100 GS/s. The resolution and linearity at each carrier frequency should meet the requirements of the corresponding standard(s). However, speed and accuracy specifications for the DAC are not the only limiting factors. If the DAC is placed directly at the antenna, it should also provide sufficient power to the antenna. This is a serious issue, especially in low-voltage technologies. High-speed CMOS DACs tend not to output more than 10 dBm, being insufficient to handle all wireless standards in Table 6.1. Any transmitter power control or simultaneous multi-standard conversion increases the DR specification for the DAC to unrealistic levels, very similar to the effect of ADC input power on its DR. 6.3.3

Software-Defined Radio

A single transceiver is used in an SDR. But all parts can be reconfigured by the software, as illustrated in Fig. 6.3. By doing so, multi-standard operation becomes

Rx front−end

ADC

LO

Tx front−end

FIGURE 6.3

DSP

DAC

Software-defined radio transceiver.

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DAC 0 90

PA

DAC

FIGURE 6.4

Direct-conversion transmitter architecture.

possible. This reconfigurability requires new circuit design techniques. A strategy to achieve this is to make the analog front end as simple as possible, shifting the design complexity to the ADC and DAC. However, good system-level design is required to find power-optimized solutions. The ADC should be designed such that it can meet the specifications for the communication standard with the toughest accuracy requirement and the speed of the standard with the largest channel bandwidth. For each standard, the ADC should then be reconfigured to obtain the specifications required with minimal power consumption. For the transmitting path, a direct conversion (or homodyne) implementation might be preferable over the traditional heterodyne transmitter [11]. In a direct-conversion architecture, the DAC output is directly up-converted by a single mixer stage to the carrier frequency required. This topology is shown in Fig. 6.4. The filtering requirements of a heterodyne transmitter are very problematic for reconfigurable front ends. The often-used SAW filters are impossible to reconfigure and are hence to be avoided in SDR front ends. A direct-conversion architecture requires fewer filters, making it easier to implement in a reconfigurable manner. Of course, a direct-conversion transmitter also demonstrates some drawbacks [e.g., local oscillator (LO) pulling]. A potential issue of a system such as Fig. 6.3 arises when multiple modes must be received concurrently. In such a case, the ADC should be able to convert the entire band between the two modes, leading to almost the same specifications as the SR concept of Section 6.3.2. For such systems it might be necessary to combine an SDR with a parallel transceiver architecture, leading to a system with a few reconfigurable transceivers.

6.4

EVALUATING RECONFIGURABILITY

As pointed out in Section 6.3.3, reconfigurable hardware is mandatory to obtain an SDR transceiver. However, a method is needed to evaluate the performance of a

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TABLE 6.2 Power and Area Overhead for the ADC Part of a Dual-Mode GSM–WLAN Transceiver

Architecture Parallel SR SDR, fixed ADC SDR, reconf. ADC

Power Overhead, GSM Mode ≈0 Very large f C,WLAN ∼ f C,GSM (Very) small

Area Overhead, GSM Mode AWLAN Small < AWLAN < AWLAN

Power Overhead, WLAN Mode ≈0 Very large DRGSM ∼ DRWLAN (Very) small

Area Overhead, WLAN Mode AGSM Small < AGSM < AGSM

certain reconfiguration method. To do so, the reconfigurable building block must be compared with a dedicated solution for each of its operating modes. Two performance metrics for a reconfiguration method are the power overhead and the area overhead. The power overhead is the additional power consumption above that required for a dedicated solution. The area overhead is the additional area needed to implement the reconfigurability. These concepts are illustrated in Table 6.2 for the ADC of four hypothetical implementations of a dual-mode transceiver for GSM and IEEE802.11a. For a parallel architecture, there is no power overhead if the transceiver not in use can be powered off. However, the area overhead is very large: namely, the ADC of the other transceiver. For an SR transceiver, the power overhead is very large, whereas the area overhead will be small. For an SDR transceiver, two cases are considered. In the first, an ADC is made that can cope with the two standards without reconfigurability. As a result, the power overhead for GSM is determined by the required increase in bandwidth, while the power overhead for WLAN is determined by the increase in DR [12]. The total area should be smaller than the area for two separate converters. In the second case, one reconfigurable ADC is used. Now the power overhead will be small for both modes and will depend on the reconfigurability method chosen. The area will be slightly larger than in the previous case, due to the additional circuitry to implement the reconfigurability, but is expected to be less than two separate converters.

6.5 6.5.1

ADCs FOR SOFTWARE-DEFINED RADIO ADC Topologies

There exist many different topologies to implement an ADC. For each region in the accuracy–speed plane, another topology is optimally suited. This is shown in Fig. 6.5. Very low-speed but high-accuracy ADCs are implemented as integrating types of ADCs. This type of converter requires many clock cycles to convert one sample. Low-accuracy but very fast ADCs, on the other hand, are implemented using a flash architecture. These process one sample each clock cycle.

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16 Resolution [bits]

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14

delta−sigma

12 Bluetooth

successive approximation

10 8

IEEE802.11a

pipeline

6

subranging interpolating folding flash

4 10 2

10 4

10 6

10 8

Signal Bandwidth [Hz]

FIGURE 6.5

Operating ranges for various ADC topologies.

Also indicated in Fig. 6.5 are the ADC requirements for various wireless communication standards. An SDR ADC should be able to meet all those standards with minimal power consumption. Three architectures are prime candidates for achieving this:
, successive approximation, and pipelined ADCs. In the remainder of this section we explain their operating principles and focus on how they can be implemented such that they can be used in a multi-mode receiver. 6.5.2

Delta-Sigma ADCs

6.5.2.1 Operation Delta-sigma ADCs are able to obtain high accuracies while using a low-accuracy (often 1-bit) quantizer. This is achieved with two principles: oversampling and noise shaping. By using a sampling frequency much higher than the Nyquist frequency, the large quantization noise spreads out over a large bandwidth. A sharp digital decimation filter is placed at the output of the converter, to filter out all noise above the signal bandwidth. As a result, only a small portion of the quantization noise remains after the filter. Noise shaping is a process to shape the quantization noise such that most of it falls outside the signal band. As a result, the remaining quantization noise is even lower. Figure 6.6 shows the architecture of a
 converter. As the quantization noise has a different path to the output, H (z) can shape the quantization noise without affecting the input signal. If a lowpass function for H (z) with sufficient dc gain is chosen, the quantization noise will be shaped to high frequencies while leaving the signal nearly unaffected in the signal bandwidth. Therefore, H (z) is implemented mostly as a cascade of integrators.

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+ −

decim. filter

H(z) DAC

FIGURE 6.6

General delta-sigma architecture.

When assuming that the quantization noise can be modeled as a white noise source, and if the filter is composed of a cascade of n integrators, the resulting signal-tonoise ratio (SNR) can be calculated [equation (6.4)]. B is the number of bits used in the quantizer, and OSR is the oversampling ratio (defined as f S /2 f B , with f S the sampling frequency and f B the signal bandwidth):   2 OSR 2n+1 3π
B 2 − 1 (2n + 1) SNR = 2 π

(6.4)

In reality this performance cannot be achieved. Due to the nonlinearity of the quantizer, scaling coefficients must be introduced for stability of the loop. These will degrade the filter characteristic. Therefore, for higher-order
 ADCs, cascading is often used. These converters consist of a cascade of low-order filters. The outputs of the quantizer of each filter are then recombined digitally. However, this requires accurate control of the analog filter coefficients to avoid quantization noise leakage, often leading to more stringent filter specifications [13]. As can be seen from (6.4), another possibility for increasing the SNR is to increase the number of bits of the quantizer. The main problem for such multi-bit converters is the fact that the quantized signal must be fed back to the input of the filter. As it is added directly to the input signal there, it doesn’t undergo any shaping. As a result, the DAC in the feedback path in Fig. 6.6 needs the same accuracy as does the
 converter itself. To achieve this, dynamic element matching (DEM) techniques are often used [14]. Also at the system level,
 ADCs offer a large advantage over other topologies. The oversampling nature of
 ADCs is beneficial for the filtering in front of it. Because the sampling frequency is higher than the signal bandwidth, less aggressive antialiasing filtering is necessary. This allows easier reconfigurability of this filter [15]. In deep-submicron CMOS, the intrinsic speed of the technology can be used to maintain a high OSR, even for large signal bandwidths [16]. 6.5.2.2 Reconfigurability Figure 6.7 shows different methods to make a
 ADC reconfigurable. In most implementations, some of these methods are combined to enable a broad operating range. There are two methods of changing the signal bandwidth of the converter. The first one is simply to scale the sampling frequency [1,7,17] so that for the same OSR the signal bandwidth changes. This technique is very easy to implement, as it requires no additional circuitry. However, all components of the filter and ADC must be designed to operate correctly at the maximal sampling

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number of bits B sampling frequency

filter function order n + −

OSR decim. filter

H(z) DAC

FIGURE 6.7

Reconfigurability options for
 ADC.

frequency. When such circuits are operating at a lower frequency, they often have a large power overhead. Second, the OSR can be changed [7,17]. This has no consequences for an analog loop filter. For a decimation filter, this can be achieved by switching off some downsampling stages, resulting in only a very small circuit overhead. However, as the OSR is lowered, the SNR also decreases. If a broad signal bandwidth range must be covered with the same SNR, a combination with other reconfiguration methods is mandatory. The SNR can be changed by changing the number of quantizer bits [2]; for example, a multi-bit quantizer can be implemented in parallel with a 1-bit structure. By making sure that the multi-bit quantizer and DAC can be turned off when they are not required, there is no additional power overhead. However, the additional quantizer and more complicated DAC will increase the chip area of the ADC. It is beneficial to combine this method with a variable filter function. A multi-bit topology has fewer stability problems. Therefore, more aggressive noise-shaping functions are possible, leading to a further increase in SNR. Changing the order of the filter function is also possible. It is easiest to implement in cascade
 ADCs, where the latter stages can be switched off when their noiseshaping ability is not required [2]. Finally, the transfer function of the filter can be changed [1]. Introducing zeros can lead to a higher SNR [18]. In a reconfigurable ADC, the location of these zeros should be shifted depending on the signal bandwidth wanted [7,17]. To optimize power consumption, the capacitors in the filter should be made scalable. Their ratios determine the filter characteristic and their size determines the thermal noise floor. For a differential implementation, the SNR due to thermal noise can be approximated by [13] SNRthermal =

(2 · OL · VREF )2 OSR · C S 2 4kT

(6.5)

The maximal capacitor value is determined by the standard supported, which requires the highest SNR. When converting signals from other standards, the capacitors’ size and hence the OTA current required can be decreased [7].

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stage 1

stage 2

stage m

n bits

S&H

n bits

A/D

D/A

−

+

2n

n bits digital recombination FIGURE 6.8

6.5.3

An m-stage n-bit per stage pipelined ADC.

Pipelined ADCs

6.5.3.1 Operation Figure 6.8 shows the operation of an m-stage, n-bit per stage pipelined converter. In this example, each stage quantizes n bits. It calculates the difference between the input and the quantized signal, amplifies this, and feeds it to the next stage. After m stages, the input is quantized with m · n bits. Quite often, 1.5 bits per stage and a gain of 2 are used. This configuration introduces some redundancy, enabling digital error correction. This reduces the accuracy requirements for the comparators of each stage. To obtain higher accuracies, some form of calibration is necessary. The calibration should compensate for effects such as finite OTA gain and capacitor mismatch, to correct the gain of each stage. As each stage incorporates gain, the input-referred thermal noise of subsequent stages is suppressed. As a consequence, stages farther down the pipe can be scaled down, saving power. Almost all pipelined ADCs are made using switched capacitor techniques. A switched capacitor pipeline stage alternates between the sampling and amplifying phases. Moreover, each stage is always opposite in phase to the preceding one. As the OTA is used only in the amplifying phase, it can be shared between two stages. For a gain of 2 per stage and taking the stage scaling into account, this OTA sharing technique could lead to a power reduction of 33% compared to a standard pipelined ADC. In a quadrature receiver, even more power savings are possible. If separate ADCs are used for the I and Q paths, the OTA can be shared between the same stage of each of the two pipeline ADCs. As this allows perfect scaling for each stage, a 50% power saving is possible [19]. 6.5.3.2 Reconfigurability The resolution of a pipeline ADC can be changed using stage bypass. As each stage converts a certain number of bits, switching off some stages decreases the total number of bits converted. This leads to a less accurate but lower-power ADC. As lower accuracies allow a higher thermal noise floor, it is best to bypass the first stages of the pipe, as these are the most power hungry [20]. The resolution can also be varied by using residue feedback. By resending the output of the last stage through some stages, more bits are obtained. However, this

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technique will lower the sampling rate, as some stages are now used twice for each output sample. This is also not power optimal. In a standard solution each stage is scaled down, whereas here “oversized” stages are used after the residue feedback. The bandwidth can be changed by scaling the sampling frequency. For optimal power design, the OTA biasing currents should be changed as well. Another bandwidth-improving technique is interleaving. By alternating between two pipeline ADCs, the bandwidth is doubled. Moreover, as the OTA in each stage of a pipeline ADC is used only in half a clock period, each OTA can be shared between the two converters. As a result, interleaving with two pipeline ADCs results in very little power consumption increase. The area, on the other hand, is almost doubled. 6.5.4

Successive Approximation ADCs

6.5.4.1 Operation The architecture of an n-bit successive approximation ADC is shown in Fig. 6.9. A successive approximation ADC actually implements a binary search algorithm to convert the input signal to a digital value. Starting with the most significant bit (MSB), each clock cycle an additional bit is converted, by comparing the sampled input signal with the value converted so far. As a result, the sample rate equals the clock frequency divided by n. The advantage of a successive approximation ADC is the small area and simple architecture. Only a comparator is needed. Everything else can be implemented using switches and scaled capacitors [6]. However, because n clock cycles are required to convert to an n-bit word, its maximal signal bandwidth is rather limited. The comparator needs to be as accurate as the entire ADC, as it must be able to correctly resolve the least significant bit (LSB). Redundancy as with the pipelined converter cannot be introduced here. The DAC is often implemented as a capacitive DAC, composed of binary-scaled capacitors which are charged either to a reference voltage or to ground. As a result, the accuracy is determined by the capacitor ratios. Therefore, to obtain over about 12-bit accuracy in standard CMOS technologies, some form of trimming or calibration will be required. 6.5.4.2 Reconfigurability The resolution can be changed simply by converting less bits. Consequently, for the same output data rate, the clock frequency can also be lowered. Simply by scaling the clock speed, the bandwidth can be modified. In

S&H

S. A. Register b1 b2

bn D/A

FIGURE 6.9

General n-bit successive approximation architecture.

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1 2 1

2 2

1

− +

V fb

1 2

1

− +

V fb A/D

(a) Switched capacitor integrator

(b) Switched capacitor pipeline stage

FIGURE 6.10 Configuration modes for a filter element in a hybrid
-pipelined ADC.

[6], a SAR which has only dynamic power consumption, is described. As a result, power scales linearly with clock frequency. This is very advantageous when a large range in bandwidth must be covered, as power-efficient operation can be achieved for any frequency. This is achieved by using passive charge sharing. The input is first sampled onto a capacitor. Then a comparator determines the MSB and a precharged capacitor is used to add or remove charge from the value sampled. This is repeated for all bits, with binary-scaled precharged capacitors. This ADC achieves 8 effective bits with signal bandwidths up to 20 MHz. 6.5.5

Hybrid ADCs

It is also possible to combine different types of ADCs. For example, a switched capacitor integrator of a
 ADC [shown in Fig. 6.10(a)] doesn’t differ much from a pipeline stage [shown in Fig. 6.10(b)]. This means that with a few additional switches a switched capacitor
 ADC could be changed in a pipeline ADC. In [20] this idea is used to implement a hybrid
-pipelined converter, with an adaptive bandwidth up to 10 MHz and between 6 and 16 effective bits. In
 mode, the accuracy is changed by changing the OSR and sampling frequency. In pipeline mode, capacitor sizes and pipeline length can be modified using stage bypass. A PLL is used to sense the clock frequency and adapts the bias current of the op-amps automatically.

6.6

DACs FOR SOFTWARE-DEFINED RADIO

Selection of an appropriate DAC for an SDR system is subject to a multitude of considerations. In this section we present the most important system- and implementationlevel topics. As indicated in Section 6.2, the selection and design of a DAC for SDR is largely dependent on the topology chosen for the entire transmitter. The various options regarding the frequency planning and intermediate frequencies result in different specifications for the filters used in the transmitter. The specifications of these filters, especially the reconstruction filter, are very important when determining the

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specifications of the DAC. Furthermore, all practical DACs introduce some sort of amplitude distortion. This can also be exploited to simplify the system-level design of an SDR. In this section we provide an overview of the dominant topologies used to implement wide-bandwidth telecommunication DACs, along with some recent CMOS DAC implementations. Their usability in an SDR radio is discussed for standard transmitter architectures. The section ends with the introduction of some interesting ideas that deviate from the standard transmitter concept. 6.6.1

Topologies for High-Speed CMOS DACs

From the multitude of DAC topologies that exist, the current-steering DAC is the most common, if not the only, topology used for CMOS implementations targeting telecommunication applications. Due to its lack of high-impedance nodes experiencing voltage swing and the absence of a closed-loop output stage, it can achieve very high update rates and signal frequencies. This topology is also capable of achieving the required accuracy and linearity (up to 14 bits). Since they require only CMOS transistors and no resistors or capacitors, current-steering DACs can be implemented in a fully digital CMOS technology. Current-steering DACs use a current as the reference quantity for its output signal. The output is constructed by switching weighted current sources according to the binary input word. Based on the weighting used for switching the current sources, three different implementations can be distinguished: r Binary weighted r Unary weighted r Segmented In a binary-weighted DAC the switched currents are weighted according to the binary weight of the bit that controls the switch. In a unary-weighted DAC the switched currents are all equal, and the digital input word is converted into thermometer code, which is used to drive the switches. A segmented DAC combines a binary and unary section. The LSBs of the input word are applied directly to a binary-weighted section, while the MSBs are converted to thermometer code and drive a unary-weighted section. The number of MSBs that are converted into thermometer code define the degree of segmentation of the converter. The main advantage of a binary-weighted DAC is the design simplicity, enabling very high update rates [21]. It also features a low implementation area and a very low power consumption [22]. The disadvantage is the lower spectral purity at high signal frequencies due to MSB switching transients. A unary-weighted DAC requires a full binary-to-thermometer-code converter. The power and area of such converters scale exponentially with the number of bits. As a result, for high-resolution DACs the power and area consumed by this block is very high. The main advantage of the unary-weighted DAC is the high linearity, even at high signal frequencies [23].

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The segmented topology provides a trade-off between the properties of both the binary- and unary-weighted DACs. The less important LSBs of the input word are implemented in a binary-weighted manner. Hence, their implementation is simple and consumes little power. Due to the exponential scaling of power and area used by a thermometer-code converter, reducing its number of bits has a large impact on the performance of the complete converter. On the other hand, the binary LSBs limit the linearity of the complete converter. Hence, a trade-off between linearity and area/power consumption is established [23]. 6.6.1.1

Performance Limits of Current-Steering D/A Converters

Update Rate Limits The first fundamental limit on a current-steering DACs performance is the maximal clock frequency for correct operation of the digital section in the converter. According to the Nyquist theorem, the maximal output signal bandwidth is equal to half of the update rate. Hence, the maximal update rate presents an upper bound on the output signal frequency. Signal-to-Noise Ratio In most DACs the quantization noise is the major noise limit. The SNR of a quantized digital signal is approximately equal to SNRq ≈ 6.02N

(6.6)

For a quantized signal with quantization step
, the integrated quantization noise power is Pe =


2 12

(6.7)

For signals that are sufficiently active (such as telecommunication signals), the quantization noise can be seen as white noise, distributed between 0 and f s . This means that the spectral density of the noise can be calculated as 
2 1 Sn ( f ) = (6.8) 12 f s This result shows that by increasing the sampling frequency, the noise spectral density is decreased. The in-band quantization noise power, assuming a brick-wall reconstruction filter with bandwidth BW, can then be calculated as  BW
2 1 Pe (6.9) Sn2 ( f ) = 2BW = Pnoise = 12 f s OSR −BW Therefore, we can see that the in-band noise power improves: Pnoise 1 = Pe OSR

(6.10)

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Improving the signal-to-noise ratio at (6.6) into SNRq,in-band = 10 log

Psignal = 10 log Pnoise

= SNRq + 10 log(OSR)



Psignal · OSR Pe



(6.11)

Hence, oversampling with a factor of 4 improves the SNR with the equivalent of 1 bit. This allows for systems to synthesize small-band signals with very high-speed, low-resolution DACs and still have sufficient SNR. In reality the reconstruction filter is not a brick-wall filter, resulting in a diminished effect of the OSR on the converter noise. For non-first-order filters, the error made can be neglected. An extension of the simple oversampling presented in the preceding paragraph is the addition of noise shaping as introduced in Section 6.5.2.1. This results in a higher SNR in the signal band. However, it moves significant amounts of energy out-of-band and this has to be filtered out, placing extra constraints on the reconstruction filter. Static Accuracy and Linearity Limits Besides the inherently limited accuracy of the digital source signal, the DAC can limit the accuracy even more due to nonlinear conversion. Mismatch-induced errors are a first cause of nonlinear conversion. Since the actual currents provided by the unit current cells deviate from the nominal unit current value, the analog output value deviates from the nominal output value, resulting in a nonlinear overall static transfer function for the DAC. This phenomenon is frequency independent and hence provides a frequency-independent upper bound on the achievable linearity of the converter. At higher frequencies, however, this is not the dominant cause of nonlinearity. Dynamic Accuracy and Linearity Limits At high output signal frequencies, additional effects start limiting the linearity of the conversion. The most important effects, commonly recognized as the output-frequency limiting factor, are related to the limited isolation of the current cell internal nodes from the output signal. The output current is usually converted to a voltage (e.g., by a resistor) in order to perform further signal processing. Even if the output current is not explicitly converted to a voltage, there is still some implicit current-to-voltage conversion at the output of the converter, due to the nonzero input impedance of the next processing stage. However, the output impedance of the converter is not constant. It consists of the parallel network of the impedances of all current cells that are switched on. Therefore, the output impedance itself is signal dependent. The current flowing through this signal-dependent output impedance as a result of the voltage at the output is added to the intentional signal current and introduces higher-order harmonics. The relation between the noninfinite converter output impedance, the nonzero load impedance, and the output signal linearity is well studied [8,24,25]. Since a current-steering DAC is a mixed-signal system, more effects causing unwanted signal-dependent current and distortion are present (e.g., switching of

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the switch source node capacitance [26] and timing issues [27]). Most of them are proportional to the output signal frequency. It is important to note that the majority of the dynamic nonlinearities are independent of the update rate. This means that a converter should be designed for the worst-case linearity–bandwidth requirement. It also means that increasing the update rate of a converter doesn’t necessarily degrade its linearity, a property that can be exploited to simplify reconstruction filter design. 6.6.1.2 Reconfigurability of Current-Steering D/A Converters Due to their mostly digital nature, the reconfiguration of current-steering DACs is fairly straightforward. If the converter is designed for the most stringent linearity specification that the system should be able to handle, it can easily be reconfigured to operate in the most favorable point of the performance–power trade-off curve. Signal-to-Noise Ratio and Signal Bandwidth As shown in Section 6.6.1.1, the SNR of a given DAC core can be traded for bandwidth by changing the OSR and/or the use of noise shaping. Since bandwidth is assumed to be determined by the standard, changing the oversampling rate requires a flexible clock frequency. For this, a resampling/interpolation block might be required to convert between the DSP data rate and the DAC sample rate. These operations are digital and hence well suited for the SDR concept. Output Power To facilitate power control in the transmitter, flexible control over the output swing of the converter is desirable. In current-steering DACs, this can be achieved by modifying the reference current used to derive the cell current. Although the output current has some influence on the linearity, the control range can still be fairly large ([23] reports one octave). Another option is to incorporate an active output stage [28] with reconfigurable gain. Power Consumption The power consumption of a current-steering DAC can be split into four parts: clock, digital, analog, and output power. A large part of the total converter power is due to clock distribution. The digital power is consumed mainly by the thermometer-code converter (if present). The clock and digital power follow the trends in digital power scaling. Hence, they are linearly dependent on the clock speed if the supply voltage is not scaled. If the supply voltage is scaled, the digital power exhibits a cubic dependency. This means that the update rate has a significant influence on the power consumption of the converter. Since most of the analog section consists of “pseudodigital” circuits (switch drivers and resynchronization latches), it also follows the digital power-scaling rules. However, headroom requirements in the analog circuits prevent down-scaling of the supply voltage. Consequently, the analog power scales linearly with the clock frequency. The signal frequency influences the power consumption of the digital and analog sections. Higher signal frequencies result in higher switching activity, hence higher power consumption. The output current is also a significant contributor to the total

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output power, especially in converters with low segmentation [29]. It is independent of clock and signal frequency. 6.6.2

Dealing with Nyquist Images

Digital signal processing theory teaches that the spectrum of a sampled signal equals an infinite replication of the spectrum of the base signal. When a digital signal is converted into the analog domain, this property remains intact. These replicas are highly unwanted since they result in out-of-band signals, possibly violating the emission masks. Therefore, systems using a DAC have to incorporate some means of dealing with these images. This can have a significant impact on the reconfigurability of the transmitter. The most straightforward method of suppressing images is to filter them out using an analog lowpass filter. When using a brick-wall lowpass filter with a cutoff frequency at f s /2, the image is completely removed from the output spectrum. Implementing brick-wall (infinite-order) filters is not possible, however, and even high-order analog filters are far from trivial to design. Therefore, real-world applications are limited to lower-order (typically, around four) filters. The transfer function of an Nth-order lowpass filter with cutoff frequency f p can be approximated as H( f ) =

1 [1 + j( f / f p )] N

(6.12)

For signals that are well above the cutoff frequency of the filter, we can thus write the amplitude transfer as  |H ( f )| ≈

fp f

N (6.13)

Should the system require a bandwidth BW with an out-of-band suppression S and we use a reconstruction filter that has its cutoff frequency at f p = BW, we can determine the following relation between the sample frequency f s of the converter and the filter order N :   fs −1 (6.14) SdB = N · 20 log BW If we define the oversampling ratio of the DAC as the ratio between the actual sampling frequency and the minimal sampling frequency to fulfill the Nyquist criterion, OSR =

fs fs = 2 f Nyquist 2BW

(6.15)

we can rewrite the Nyquist image attenuation (NIA) as NIAfilter = (2OSR − 1) N

(6.16)

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This equation indicates the trade-off between the required filter order and the DAC sampling frequency. In case of minimal sampling frequency (OSR ≈ 1), the filter order approaches infinity, corresponding to a brick-wall filter. For a system that requires a NIA larger than 60 dB we can calculate that when using an OSR equal to 10, a third-order reconstruction filter is required. As mentioned before, a filter order higher than 4 is difficult and/or expensive to implement. Another conclusion that can be drawn from the equations above is that when changing the signal bandwidth or DAC update rate, the reconstruction filter should be changed accordingly. This means that the degree of reconfigurability of a DAC is not only a function of its own reconfigurability but also of its associated reconstruction filter. 6.6.3

Pulse-Shape-Induced Amplitude Distortion

Besides the image components introduced by sampling, a DAC also introduces amplitude distortion. This due to the fact that a DAC uses real-world pulses instead of the mathematical Dirac impulse trains used in sampling theory. The pulse shape used by the DAC determines the properties of the distortion. The resulting distortion can introduce a significant error. To compensate for this effect, the digital signal is often predistorted, especially for low oversampling rates. On the other hand, this amplitude distortion can be exploited to lower the amplitude of the Nyquist images. 6.6.3.1 Zeroth-Order-Hold DAC The zeroth-order-hold DAC is the most common type of DAC. Each output value is held for one clock period, resulting in a square pulse shape. The distortion introduced by this pulse shape is characterized by the following equation: |H ( f )| =

f sin[π ( f / f s )] = sinc π ( f / fs ) fs

(6.17)

The sinc distortion can be used to implement some form of reconstruction filtering. It has an inherent lowpass characteristic, having |H (n f s )| = 0 for integer values of n. If sufficient oversampling is used, the sinc shaping can provide a significant filtering of the Nyquist images: for a signal located between dc and BW, the Nyquist image is located between f s − BW and f s . Therefore, the amplitude of the highest image component (i.e., the one at f s − BW) is |H ( f )| = sinc

  f s − BW 1 = sinc 1 − fs 2OSR

(6.18)

For example, for an oversampling ratio of 10, the attenuation of the Nyquist images by the sinc response is approximately 26 dB. This effect is solely dependent on the OSR and is independent of blocks external to the DAC. Therefore, it is an interesting property for reconfigurable systems.

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0

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1 1.5 2 2.5 3 3.5 Relative signal frequency (fsig /fsample )

4

FIGURE 6.11 Amplitude distortion for higher-order-hold D/A converters.

6.6.3.2 Higher-Order-Hold Converters In a higher-order-hold converter the analog output is interpolated between two or more sampled values. The amplitude shaping of a Kth-order hold converter can be described as  |H ( f )| = sinc

f fs

 K +1 (6.19)

The main property of these higher-order-hold converters is that they have a higher Nyquist image attenuation. The amplitude distortion for first- and second-orderhold DACs is plotted in Fig. 6.11. In certain cases this effect, combined with some oversampling, can be sufficient to deal with the Nyquist images. The Nyquist image attenuation due to the Kth-order-hold effect can be calculated as  NIA K = sinc 1 −

1 2OSR

 K +1 (6.20)

However, implementation of such higher-order-hold converters is not trivial, resulting in approximations such as L-fold linear interpolation [30]. 6.6.4

CMOS DAC Implementations for Wideband Communication

Over the last decade, several high-performance CMOS DACs have been described in the open literature. In this section we highlight some of these to provide an overview of the current state-of-the-art. A first-order assessment is made whether these converters

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can be used to achieve 10-bit performance (60 dB SFDR) over a 0- to 50-MHz signal bandwidth. The filter order needed to suppress the Nyquist images is also estimated. A 10-Bit 500-MS/s DAC in 0.35-µm CMOS One of the first wideband highresolution CMOS DACs was presented in [23]. It was implemented in a 0.35-µm CMOS technology and consumes 125 mW at 500 MS/s. The converter achieves approximately 60 dB linearity over a 50-MHz signal bandwidth when running at 400 MS/s. For higher update rates, the linearity drops below 60 dB; hence the OSR is restricted to 4. The zeroth-order-hold output waveform results in approximately 17 dB of NIA. The remaining 43-dB suppression needed to ensure that the first Nyquist image lies below the 60-dB specification mandates the use of a third-order reconstruction filter. An OSR of 4 results in an extra 6 dB of signal-to-quantizationnoise ratio (SNRQ) (i.e., 1 bit). A 10-Bit 1-GS/s DAC in 0.35-µm CMOS Another benchmark high-speed, highresolution CMOS DAC was presented in [31]. This design was also manufactured in a 0.35-µm CMOS technology and consumes 110 mW at 1 GS/s. It achieves a 60-dB linearity over its complete first Nyquist zone (500 MHz). The oversampling ratio when using this converter would be 10, resulting in 26 dB of NIA due to pulse-shape distortion. A second-order filter would ensure sufficient aggregate NIA. The OSR of 10 lowers the in-band quantization noise with 10 dB. A 10-Bit 250-MS/s DAC in 0.18-µm CMOS The design presented in [22] and [29] shows that binary converters are also able to convert large signal bandwidths. The converter was designed in a 0.18-µm CMOS technology and achieves 60 dB of linearity over its complete Nyquist range when running at 250 MS/s. It consumes 40 mW. To achieve the specifications derived in Section 6.2.2, a fourth-order filter would be required. As the OSR is only 2.5, the NIA due to pulse-shape distortion is 12 dB, leaving the remaining 48 dB to be achieved by means of the reconstruction filter. A 6-Bit 4.5-GS/s DAC in 0.13-µm CMOS The converter presented in [21] demonstrates a 6-bit DAC implemented in a 130-nm CMOS technology that operates up to 4.5 GS/s. It consumes 30 mW from a 1.2-V supply. The very high update rate and low power consumption are due largely to its fully binary architecture. For signal frequencies up to 50 MHz at an update rate of 3 GS/s, it achieves a linearity of approximately 50 dB. This means that it is unable to meet the linearity specifications. However, to illustrate the concept of highly oversampled DACs, the calculations are included. Due to the very high update rate, an OSR of 30 is possible, resulting in an extra 2.5 bits of quantization noise performance. This means that the 6-bit converter achieves approximately 8-bit quantization noise performance, due to its very high OSR. A first-order filter combined with the sinc distortion suffices to suppress the Nyquist images at these oversampling rates.

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A 68-dB SFDR 100-MHz Bandwidth
-DAC in 0.13-µm CMOS The DAC introduced in [8] combines the very high update rate with noise shaping to improve baseband SNR. The converter described uses a 5-bit core combined with a third-order digital
 modulator to achieve an in-band SNDR of 68 dB over a bandwidth of 100 MHz. It consumes only 11 mW, resulting in a peak FOM of 36,900 MHz/mW. The 10-fold oversampling, combined with the third-order noise shaping, results in 12 effective bits in the 50-MHz band. The high core sample rate ensures that the Nyquist images can still be filtered using a first-order filter. The noise-shaping operation will, however, result in significant out-of-band noise power that has to be filtered. This should be accounted for when determining the order of the reconstruction filter. A 1.5-V 13-Bit 130-300-MS/s DAC in 0.13-µm CMOS In [28] a dynamically calibrated converter with an active output stage is presented. It is designed in 0.13-µm CMOS technology and achieves 68 dB of linearity over a 50-MHz bandwidth while running at 300 MHz. This means that it exceeds the linearity specification set in Section 6.2.2. Since the OSR is only 3, the converter requires a fourth-order reconstruction filter to remove the Nyquist images. 6.6.5

Advanced Techniques and Implementations

Recently, some new architectures and techniques have been proposed to ease the implementation and integration of transmitters. A lot of them are interesting from an SDR perspective, and some are discussed in the following section. 6.6.5.1 Digital IF Multi-Step Architecture An architecture greatly simplifying the front end is the digital-IF architecture, shown in Fig. 6.12. This architecture tries to combine the advantages of a direct conversion and a multi-step architecture. The signal is first up-mixed digitally, resulting in a real signal that corresponds to the quadrature-modulated IF signal in a multi-step transmitter. Then it is converted using a high-speed DAC, followed by a single-sideband up-mixer. The digital up-mixing causes the modulated signal to be centered around an ac carrier (as opposed to around dc for the direct-conversion transmitter). This allows the subsequent stage to be ac coupled, preventing LO leakage caused by dc offsets. The digital-IF technique hardens the requirements of the DAC, since its output signal

0

PA

DAC

90

SSB

FIGURE 6.12

Digital-IF architecture.

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IN

2

DAC

CLK

2

0 180

z –1

2

DAC

FIGURE 6.13 Two converters clocked with complementary clocks. The two output currents are summed by tying them to the same node. The inputs are constructed such that the first set of Nyquist images is suppressed.

frequency is higher. More important, it increases the demands on the reconstruction filter, since the oversampling ratio is smaller. The filter alternatives presented in Section 6.6.5.2 can be used to cope with this. Another approach is to use a higher-order hold converter and careful frequency planning to exploit the amplitude distortion [32]. 6.6.5.2 Parallel-Path Converter Following Nyquist’s theorem, for a bandlimited waveform with bandwidth BW, at least 2 · BW samples per second must be provided to the converter. It is possible to use multiple converters with a lower sample rate to obtain a combined sample rate 2 · BW for the system. This can be achieved by time-interleaving the output of multiple DACs [28]. However, this requires additional analog circuitry, increasing area and power consumption. Another option is to sum the outputs of multiple DACs together, as indicated in Fig. 6.13 for two converters. This configuration was introduced in [33]. It enables the suppression of half of the Nyquist images when the appropriate inputs are applied. Although not fully equivalent to a double-speed DAC, the parallel-path DAC is functionally equivalent for practical oversampling ratios. A remark should be made regarding the amplitude distortion of the parallel-path converters. Since their output is the linear combination of N separate DACs each running at f s /N , the amplitude distortion exhibits the frequency response equal to that of one DAC running at f s /N . Figure 6.14 shows the amplitude distortion of a parallel-path DAC compared to a traditional DAC running at the same update rate. 6.6.5.3 RF-DAC and Direct-to-RF Modulators A recent trend in telecommunication DAC design is to combine the D/A function together with an up-mixing function in order to obtain a converted spectrum around a RF carrier. A first method to achieve this is to exploit the high-frequency Nyquist images that are present in the converted spectrum. The most straightforward method is to filter these images out using a bandpass filter at RF, as shown in Fig. 6.15(a). The main disadvantage of this technique is the reduced output power of the image due to the sinc amplitude distortion. This can be alleviated by using current sources that are switched at the target RF frequency as shown in Fig. 6.15(b) [34]. This boosts the amplitude of the Nyquist image significantly at the current cell switching frequency.

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FIGURE 6.14

1 1.5 2 2.5 3 3.5 Relative signal frequency (fsig /fsample)

4

Amplitude distortion for parallel-path D/A converters.

A further development of this was presented in [35]. Instead of switching the current source on and off, the entire cell is replaced by a Gilbert mixer, as shown in Fig. 6.16. The carrier frequency desired is applied to the RF port, and the digital control signal to the LO port. By using a large degree of oversampling, the need for an intermediate lowpass filter or a reconstruction bandpass filter is avoided. An interesting side effect of using a pulse shape having zero value at the digital switching time instant is that it improves the general linearity performance of the

DAC

RF-DAC

OUTP

OUTP

OUTN

OUTN

D0

D0

Di

Di

FLO

(a) Direct use

FIGURE 6.15

(b) RF boosting

Use of higher-order Nyquist images by bandpass-filtering the DAC output.

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B

B

DC IB

B

B

B

RF+

RF– IB

FIGURE 6.16 Transformation to a Gilbert-style mixing cell.

converter. It lowers the sensitivity to clock jitter and reduces intersymbol interference. In RF-DACs this is achieved by ensuring that the RF frequency is an integer multiple of the converter clock rate.

6.7

CONCLUSIONS

In this chapter we discussed ADC and DAC requirements for multi-standard transceivers. Three categories of multi-standard transceivers (parallel, SR, and SDR) can be distinguished, although combinations are possible. By applying widely used definitions of FOMs, it is shown that a full SR system is impossible to build and would consume an enormous amount of power. Instead, it is wiser to make the transceiver reconfigurable (or “software defined”). The basic operating principles of three different ADC architectures (
, pipelined, and successive approximation), which are typically used in receivers, are explained. For each architecture, numerous options to make them reconfigurable are discussed and evaluated. Recent state-of-the-art publications prove that reconfiguration in accuracy and speed is possible, without much power overhead. Implementations for the DAC are covered, together with different methods to filter out the Nyquist images in the output spectrum. The possibility of reconfiguration of these methods is addressed. This is elaborated further with a comparison of six state-of-the-art DACs. Finally, some advanced techniques particularly suited for reconfigurable systems are discussed briefly.

REFERENCES 1. R. van Veldhoven, “A triple-mode continuous-time 
modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 1900–1911, Dec. 2003. 2. A. Dezzani, and E. Andre, “A 1.2-V dual-mode WCDMA/GPRS SD modulator,” ISSCC Dig. Tech. Papers, pp. 58–59, Feb. 2003.

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3. J. Koh et al., “A sigma-delta ADC with a build-in anti-aliasing filter for Bluetooth receiver in 130nm digital process,” in 2004 IEEE CICC, pp. 535–538, May 2004. 4. J. Arias et al., “A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multimode wireless-LAN receivers,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 339–351, Feb. 2006. 5. Y. Ke, J. Craninckx, and G. Gielen, “A design approach for power-optimized fully reconfigurable delta-sigma A/D converter for 4G radios,” IEEE Trans. Circuits Syst. II, vol. 55, no. 3, pp. 229–233, Mar. 2008. 6. J. Craninckx and G. Van der Plas, “A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7mW 9b charge-sharing SAR ADC in 90nm digital CMOS,” ISSCC Dig. Tech. Papers, pp. 246–247, Feb. 2007. 7. S. Ouzounov et al., “A 1.2V 121-mode CT
 modulator for wireless receivers in 90nm CMOS,” ISSCC Dig. Tech. Papers, pp. 242–243, Feb. 2007. 8. P. Palmers and M. Steyaert, “A 11-mW 68-dB SFDR 100-MHz bandwidth
− -DAC based on a 5-bit 1-GS/s core in 130-nm,” Proc. ESSCIRC’08, pp. 214–217, Sept. 2008. 9. O. Viitala, S. Lindfors, and K. Halonen, “A 5-bit 1-GS/s flash-ADC in 0.13-µm CMOS using active interpolation,” Proc. ESSCIRC06, pp. 412–415, Sept. 2006. 10. R. Brewer et al., “A 100dB SNR 2.5MS/s output data rate DS ADC,” ISSCC Dig. Tech. Papers, pp. 172–173, Feb. 2005. 11. M. Brandolini, P. Rossi, D. Manstretta, and F. Svelto, “Toward multistandard mobile terminals: fully integrated receivers requirements and architectures,” IEEE Trans. Microwave Theory Tech., vol. 53, no. 3, pp. 1026–1038, Mar. 2005. 12. S. Rabii, and B. Wooley, “A 1.8-V digital-audio sigma-delta modulator in 0.8-µm CMOS,” IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 783–796, June 1997. 13. Y. Geerts, A. Marques, M. Steyaert, and W. Sansen, “A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications,” IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 927–936, July 1999. 14. R. Baird and T. Fiez, “Linearity enhancement of multibit delta-sigma A/D and D/A converters using data weighted averaging,” IEEE Trans. Circuits Syst. II, vol. 42, no. 12, pp. 753–762, Dec. 1995. 15. D. Chamla, A. Kaiser, A. Cathelin, and D. Belot, “A switchable-order Gm-C baseband filter with wide digital tuning for configurable radio receivers,” IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1513–1521, July 2007. 16. K. Cornelissens and M. Steyaert, “A novel bootstrapped switch design, applied in a 400MHz clocked
 ADC,” Proc. ICECS, pp. 1156–1160, Dec. 2006. 17. T. Christen, T. Burger, and Q. Huang, “A 0.13µm CMOS EDGE/UMTS/WLAN tri-mode DS ADC with −92dB THD,” ISSCC Dig. Tech. Papers, pp. 240–241, Feb. 2007. 18. Y. Yin, H. Klar, and P. Wennekers, “A cascade 3-1-1 multibit
 A/D modulator with reduced sensitivity to non-idealities,” IEEE ISCAS2005, pp. 3087–3090, May 2005. 19. D. Kurose, T. Ito, T. Ueno, T. Yamaji, and T. Itakura, “44-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers,” Proc. ESSCIRC, pp. 527–530, Sept. 2005. 20. K. Gulati and H. S. Lee, “A low-power reconfigurable analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1900–1911, Dec. 2001.

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21. X. Wu, P. Palmers, and M. Steyaert, “A 130 nm CMOS 6-bit full Nyquist 3GS/s DAC,” IEEE J. Solid-State Circuits, vol. 43, pp. 2396–2403, Nov. 2008. 22. J. Deveugele and M. Steyaert, “A 10-bit 250MS/s binary-weighted current-steering DAC,” ISSCC Dig. Tech. Papers, pp. 362–363, Feb. 2004. 23. C.-H. Lin and K. Bult, “A 10-b, 500-Msample/s CMOS DAC in 0.6 mm2 ,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948–1958, Dec 1998. 24. S. Luschas and H.-S. Lee, “Output impedance requirements for DACs,” in Proc. 2003 International Symposium on Circuits and Systems, 2003, vol. 1, pp. I-861 to I-864, May 25–28, 2003. 25. A. van den Bosch, M. Steyaert, and W. Sansen, “SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters,” Proc. ICECS 1999, pp. 1193–1196, Sept. 1999. 26. J. Deveugele and M. Steyaert, “RF DAC’s: output impedance and distortion,” Analog Circuit Design. New York: Springer-Verlag, 2006, pp. 45–63. 27. K. Doris and A. van Roermond, “High-speed digital to analog converters,” in Analog Circuit Design. New York: Springer-Verlag, 2006, pp. 91–109. 28. M. Clara et al., “A 1.5-V 13-bit 130–300-MS/s self-calibrated DAC with active output stage and 50-MHz signal bandwidth in 0.13-µm CMOS,” Proc. ESSCIRC08, pp. 262–265, Sept. 2008. 29. J. Deveugele and M. Steyaert “A 10-bit full-Nyquist 250-MS/s binary-weighted currentsteering DAC,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 320–329, Feb. 2006. 30. Y. Zhou and J. Yuan, “A 10-bit, 100-MHz CMOS linear interpolation DAC,” Proc. ESSCIRC02, pp. 471–474, Sept. 2002. 31. A. van den Bosch, M. Borremans, M. Steyaert, and W. Sansen, “A 10-bit 1-Gsample/s Nyquist current-steering CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 315–324, Mar. 2001. 32. V. W. Leung, and L. E. Larson, and P. S. Gudem,“Improved digital-IF transmitter architecture for highly integrated W-CDMA Mobile Terminals,” IEEE Trans. Veh. Technol., vol. 54, pp. 20–32, Jan 2005. 33. J. Deveugele, P. Palmers, and M. Steyaert “Parallel-path digital-to-analog converters for Nyquist signal generation,” IEEE J. Solid-State Circuits, vol. 39, pp. 1073–1082, July 2004. 34. S. Luschas, R. Schreier, and H.-S. Lee, “Radio frequency digital-to-analog converter,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1462–1467, Sept. 2004. 35. P. Eloranta and P. Seppinen, “Direct-digital RF modulator IC in 0.13µm CMOS for wideband multi-radio applications,” ISSCC Dig. Tech. Papers, pp. 532–533, Feb. 2005.

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OFDM Transform-Domain Receivers for Multi-Standard Communications SEBASTIAN HOYOS Texas A&M University, College Station, Texas

7.1

INTRODUCTION

Digital deep-submicron CMOS architectures for wideband receivers are highly desirable for their flexibility, scalability, and programmability properties. However, while these technologies aid digital circuit design, they make more difficult the design of conventional analog circuits. Hence, there is a need to shift the complexity to the digital domain. This requires either front-end topologies where the analog-to-digital converter (ADC) is close to the antenna or analog circuit schemes that are intensively digital. Pushing the ADC toward the antenna imposes very high tracking bandwidths and dynamic ranges which become prohibitively area- and power-expensive in wideband applications. On the other hand, digital-intensive radio-frequency (RF) front ends not only take advantage of deep-submicron CMOS but also relax the ADC requirements. At this end, successful examples of narrowband digital RF front ends have been reported in [1], where switched G m -C filters and passive switched capacitor circuits are used to implement charge-sampling finite and infinite impulse response (FIR and IIR) filters in a narrowband direct RF-sampling receiver with built-in antialiasing for GSM and Bluetooth standards. A bank of this circuit topology has been proposed to address multi-narrowband standards [2]. However, receivers that can cope as well with wideband and ultrawideband signals remain a major challenge for the realization of software-defined radio and cognitive radios. In this chapter we present transform-domain (TD) receivers, based on charge sampling, as a candidate for the implementation of high-performance wideband and ultrawideband RF receivers. The TD receiver parallelizes the front end by expanding the RF input signal onto a set of basis functions. The expansion over a base function is accomplished via mixing with a locally generated waveform and then integration over a time window. Each expansion requires a parallel path, and parallel sampling Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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at the end of the integration time provides a set of coefficients that become the digital representation of the signal. Several advantages of this receiver front end have been reported [3–5], which are discussed in a more practical way in this chapter. We propose charge-sampling circuit topologies for implementation of the TD receiver. Specifically, we show how a switched G m -C filter structure can be modified to perform mixing with the base function, signal windowing, and integration in a very compact fashion. This topology enables the realization of a software-defined radio multistandard receiver that works not only for narrowband standards such as GSM and Bluetooth, but also for very wideband standards such as UWB. Due to parallel digital signal processing, each path operates on only a fraction of the signal bandwidth, thus relaxing the tracking bandwidth requirements and minimizing the power consumption of each sampling path. The remainder of the chapter is organized as follows. Section 7.2 gives the background of the TD receiver. In Section 7.3 the TD receiver is introduced, including the receiver structure, RF front end, mixing, windowing, and integration blocks. The fundamental detection, synchronization, and calibration equations for the design of the digital baseband blocks for multicarrier signals are presented in Section 7.4.1. Additionally, two applications of TD receivers are presented in Section 7.9; one is the software-defined radio multi-standard receiver and a TD distributed sensor network relay. Finally, conclusions are provided in Section 7.10.

7.2

TRANSFORM-DOMAIN RECEIVER BACKGROUND

Transform-domain receivers compute the signal expansion coefficients of the signal received. Therefore, the signal is processed in the transform domain rather than in the time domain. To accomplish digital TD processing, the signal is partitioned in windows of duration Tc . These windows have an overlapping time of Tov , which defines an overlapping ratio OVR = Tov /Tc . Then a set of N coefficients are computed N −1 . If M in each window via a signal expansion over the basis functions
n (t)|n=0 windows are needed for digital signal processing, a total of M N expansion coefficients M−1 N −1 |n=0 are computed as Rm,n |m=0
Rm,n =

mTs +Tc

mTs

r (t)
∗n (t) dt

(7.1)

where Ts = Tc − Tov , m = 0, 1, . . . , M − 1 and n = 0, 1, . . . , N − 1. At the end of each integration time Tc , the coefficients reach a value that is fed to an ADC for M−1 N −1 |n=0 are sent to a DSP for quantization. Finally, the quantized digital words R¯ m,n |m=0 further digital processing. The basis functions can be as simple as sinusoidal local oscillators, or just square clocks in a hard-switching implementation. In the sinusoidal basis case, the expansion coefficients become the Fourier series coefficients, which is referred to as frequencydomain (FD) sampling. The signal information symbols can be reconstructed using

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frequency-domain estimators, including a matched filter estimator, a least-squares estimator, and a linear minimum-mean-squared-error (MMSE) estimator [3]. An adaptive solution that incorporates the calibration and synchronization is covered in detail in Section 7.4.1.

7.3

TRANSFORM-DOMAIN SAMPLING RECEIVER

Transform-domain (TD) basis coefficients are computed by mixing the input broadband signal with the local oscillator frequencies followed by integration. Figure 7.1 is a block diagram of a TD receiver. The G m stages convert the input RF voltage signal into an RF current signal, which is down-converted to zero/low-IF by passive mixers. This zero/low-IF current is integrated onto a capacitor during the time window Tc . At the end of the integration window, the charge stored in the capacitor is the TD-basis coefficient. As the capacitor is reset before the new integration window, the circuit does not behave as a continuous-time filter. Instead, the windows overlap in time, introducing some degree of oversampling. This is fundamentally different from traditional filter bank approaches, where the filter has continuous operation. An immediate advantage of inherent resetting in the TD receivers is that sporadic interference does not propagate. The windowed integration of the input current signal, also referred to as charge sampling, has been analyzed in [6,7] and compared with conventional voltage sampling. This windowed integration provides an inherent antialiasing sinctype filter that offers robustness to interference and aliasing of the out-of-band noise.

Basis Coefficients

Mixing and Integration

Basis Functions

Gm

∫

mTs+Tc

(.) dt

ADC

mTs

F1 – I and Q RF broadband signal

Gm

∫

mTs+Tc

(.) dt

ADC

mTs

LNA

F2 – I and Q

Gm

∫

mTs+Tc

(.) dt

ADC

mTs

FN – I and Q Windowed Integration

m = 0 to M, M - no. of segments Tc - Actual integration time Ts - Integration time – Overlap time

FIGURE 7.1

Sinc filter Inherent anti-aliasing

Block diagram of TD receiver with N parallel paths.

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FIGURE 7.2

Wideband LNA design with noise cancelation [11].

RF receivers that make use of charge sampling to provide additional filtering of the signal have been reported [1,8–10].

7.3.1

Receiver Front End

The low-noise amplifier (LNA) is followed by a bank of G m stages, each of which drives a mixer and an integrator. Signal current is integrated in sampling capacitors, where the subsequent ADCs read the data out. A candidate circuit of the LNA and driver for a single path is given in Fig. 7.2 [11]. The resistor R provides a wideband input impedance matching from dc to gigahertz. MN2 and MP2 form the G m stages, which translates the voltage into current driving the subsequent mixers. MN2 and MN3 are cross-coupled to cancel the noise coming from the LNA. The noise current of the LNA will flow through R, generating correlated noise voltages at nodes X and Y. MP2 samples the noise voltage at Y, and MN3 samples the noise voltage at X. They are canceled out differentially. On the other hand, the signal components are in opposite phase and then are added coherently by the differential circuit. Given that the two stages have matched gains, the noise figure (NF) can be optimized [12]. This topology helps to improve the NF, which is usually high in deep-submicron CMOS technologies, due to flicker noise.

7.3.2

Mixing, Windowing, and Integration

The computation of basis coefficients of the FD receiver needs the signal to be integrated onto a capacitor for a certain time window. Since the incoming signal is passband, the flicker noise will not be a problem until the signal is down-converted to baseband. The G m stage converts the signal into a current and then it is downconverted using mixers and integrated on the capacitors as shown in Fig. 7.3. Passive FET mixers are used for the purpose of down-conversion, as they offer low-1/f noise and high linearity [8].

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TRANSFORM-DOMAIN SAMPLING RECEIVER Tc

φr LO

Rf

CH

Cs −

Vin

Gm

iIF

LO

+

Cs

CH

Rf

LO

φr

(a) Active integrator configuration

LO Vdd

CH R Vin

Gm

LO

R

iIF Vb

CH

φs

Vb

Tc

φs

LO

φr

Cs

Cs

φr

(b) Common gate configuration

FIGURE 7.3

G m stage: mixing and windowed integration.

To minimize the flicker noise of the mixer switches and improve the linearity of the G m stage, the swing at the output of the mixer must be minimized. Since the mixer is switching current, low voltage swing can be achieved by creating very low impedance at the output of the mixer. There are at least two ways in which this can be done: by using an active integrator or by using a common-gate stage [2]. Both of these circuits introduce flicker noise, which can seriously degrade the performance, as the signal is now at zero/low IF. This issue can be tackled by using large device sizes and resistors in the common-gate stage and implementing autozeroing for the active integrator. As explained earlier, an overlapping time Tov and filter bandwidth optimization needs to be introduced to gain robustness to clock jitter [13]. An overlap of 15 to 20% between the windows was found to be optimum from simulations. The sampling time is reduced by the amount of overlap introduced, and hence the sampling rate is

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iIF+ φs Mixer

Gm

Vin

φint

Cs

iIF-

φint′

iIF+ φ′s Gm

Mixer

vout+

Cs

iIF-

(a) Simple charge integration circuit

Tov Tc

φ′s

Tc

Tov Tc

φs φint φint′

Tc− Tov (b) Overlapping windows and interleaving

FIGURE 7.4

Windowed integration with overlap.

increased as a result. To incorporate overlap, signal is integrated on two capacitors using two G m stages and mixers, and the output is then interleaved. Figure 7.4(a) shows the implementation for just the positive output of the mixer. The increase in sampling rate is evident, as the integrated output is available every Tc − Tov seconds, as shown in Fig. 7.4(b). The two G m stages are necessary to avoid charge sharing between the two capacitors during the overlap time. Any circuit added after the mixer to avoid overlapping introduces flicker noise, which gets integrated directly on the sampling capacitors along with the signal-degrading SNR. The first null of the inherent sinc function provided by charge sampling depends only on the integration time Tc and is independent of the sampling capacitor, unlike the case of voltage sampling, where tracking bandwidth depends on the switch resistance and capacitor. The total integrated noise in case of charge sampling can be much greater than kT /C and depends on the integration time [6]. The SNR specification required for fixed signal power and certain bandwidth or, equivalently, Tc dictates the design of the switch, sampling capacitor, and G m stage. The noise analysis for the case of charge sampling is different from voltage sampling, for which the total integrated noise is kT /C. The output voltage on the capacitor can be viewed as the convolution of the

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signal current and the window in the time domain and, equivalently, multiplication of their Fourier spectra in the frequency domain. Thus, the total integrated mean-squared noise vn2 during charging can be calculated in a way similar to [2] vn2 =

1 Cs2




∞

Si ( f )|Fo ( f )|2 df

(7.2)

0

where Fo ( f ) = Tc sincπ f Tc is the Fourier transform of a square time window of length Tc , and Si ( f ) is the thermal current noise spectral density: Si ( f ) =

4kT Rs

(7.3)

Here Rs is the equivalent noise resistor representing the thermal noise from all the sources, including the G m stage and the switch. After substituting Fo ( f ) and Si ( f ), we get vn2

4kT = Rs Cs2


0

∞

  2kT Tc kT 2Tc Tc2 sinc2 π f Tc  df = = Rs Cs2 C s Rs C s

(7.4)

When 2Tc < Rs Cs , the noise will be the same as kT = C, as in the case of voltage sampling.

7.4

DIGITAL BASEBAND DESIGN FOR THE TD RECEIVER

In this section we provide fundamental equations for the design of the receiver digital baseband. The design will jointly perform calibration, synchronization, and data detection. 7.4.1

Digital Baseband Estimators for Multi-Carrier Signals

Orthogonal frequency-division multiplexing (OFDM) is an effective multi-carrier modulation scheme for high-data-rate transmission. With a cyclic prefix or guard interval to deal with the intersymbol interference, it divides the frequency-selective wideband fading channel into multiple flat fading narrowband subchannels and therefore simplifies the otherwise complicated multi-tap equalization to multiple one-tap equalizations [14,15]. Conventional and dominant implementation of the OFDM receiver is based on time-domain sampling, applying analog-to-digital conversion (ADC) at rates higher than the Nyquist rate, and then processing blocks of samples with the fast Fourier transform (FFT). Orthogonal frequency-division multiplexing (OFDM) has been standardized into both wireless and wireline broadband communication systems. The wireless area covers digital video broadcasting (DVB), digital audio broadcasting (DAB), IEEE 802.11a/g/n for wireless local area networks (WLANs), IEEE 802.16 (WiMAX) for wireless metropolitan area networks

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(WMANs), and even more emerging applications. The wireline area covers asymmetric digital subscriber lines (ADSLs) and very high speed digital subscriber lines (VDSLs). As the bandwidth of the OFDM signal is increased to achieve higher data rates or to accommodate more users, the time-domain sampling approach of the conventional OFDM receiver poses serious challenges to the sampling speed requirement of the ADC. This trend has already been seen in the emerging ultrawideband (UWB) radio, for which the U.S. Federal Communications Commission (FCC) has allocated the entire spectrum from 3.1 to 10.6 GHz. Related applications such as wireless personal area networks (WPANs) aim at providing wireless connectivity among entertainment devices at home and wireless connectivity between a computer and peripherals in an office environment. Since the transmit power spectral density has to be very low so as not to interfere with existing services in this band, the instantaneous signal bandwidth has to be large enough to offer the high data rates desired. Multi-band OFDM, the multi-carrier flavor of the two major competing proposals for the WPAN standard, uses an instantaneous bandwidth of 528 MHz.

7.4.2

Transform-Domain Receiver with Input OFDM Signal

In each channel of a transform-domain receiver, the input signal is mixed with a local oscillator (LO) signal and integrated in a window of duration Tc seconds. As explained in detail in [13], the windows are overlapped by a small amount Tov , which, together with filter bandwidth optimization, provides robustness to jitter and eliminates the high-frequency artifacts. The overlap can also be exploited to create a superior antialiasing filter [13]. The M overlapped windows that cover the entire M−1 N −1 |n=0 , given by signal block provide a total of M N samples R(m, n)|m=0
Rm,n =

mTs +Tc

mTs

r (t)
∗n (t) dt

(7.5)

where Ts = Tc − Tov , x(t) is the received signal, m = 0 to M − 1 indicates the mth segment in each channel, and n = 0 to N − 1 refers to the nth channel. Each channel operates only on a fraction of the input signal bandwidth, which relaxes the tracking bandwidth requirements for the ADC that quantizes the analog samples, thus minimizing power consumption. These quantized samples are processed digitally to estimate the symbols directly using a least-squares (LS) estimator [3,16]. The sampled data, given by (7.5), can be represented in the form of a vector r: T  r = R0,0 , R0,1 , . . . , R0,N −1 , R1,0 , R1,1 , . . . , R M−1,N −1

(7.6)

If the in-phase and quadrature components of each Rm,n are represented separately in r, the size of r is 2NM × 1. Without loss of generality, it is assumed that the input

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signal is a multi-carrier OFDM signal with S subcarriers and is given by

x(t) = Re

S    a(s) e− j2π Fc (s)t s=1

=

S 

  ai (s) cos(2π Fc (s)t) + aq (s) sin(2π Fc (s)t)

(7.7)

s=1

In (7.7), ai (s) and aq (s) represent the in-phase and quadrature components of the data a(s) modulated on the sth subcarrier. Fc (s) corresponds to the carrier frequency of the sth subcarrier. The data that are modulated on all the subcarriers can be represented in vector form as   a = ai (0), aq (0), ai (1), aq (1), . . . , ai (S − 1), aq (S)

(7.8)

It can be seen that the entire system that generates the vector r from a can be represented by a linear matrix equation as G · a = r

(7.9)

Each element in G corresponds to integration of the sth carrier (in-phase/quadrature) mixed with the nth LO signal (in-phase/quadrature) observed at the end of the mth segment. The elements in G are given by
G(m, n i , si ) =

mTs +Tc

cos(2π Fc (s)t) cos(2π f LO (n)t) dt

(7.10)

mTs

where f LO (n) corresponds to the frequency of the nth LO signal. The subscript i in G(n i , m, si ) refers to the in-phase component. As the in-phase and quadrature components of both the carrier and the LO signal are represented separately inside G, it is a 2NM × 2S matrix. The data a can be reconstructed from the received vector r using the LS estimator. If H is defined as the reconstruction matrix, the LS solution for the forward problem of (7.9) for the case when NM ≥ S is given by [17] H = (G HG)−1 G H

(7.11)

With knowledge of the reconstruction matrix H and the received vector r, the data transmitted can be estimated using the equation aˆ = H · r

(7.12)

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VRF

Multi-carrier signal Transmitter

r a

Modulator

Offset in the LO frequency at transmitter and receiver.

IRF

Gain and phase mismatch

LO

for each carrier. Flat gain model is used for channel.

Gain and Phase mismatch between multiple channels due to process variations and environment conditions.

Sampling

Charge sampling Integrator & Sampler Mixer

clocks are synchronized with LO signals

Actual LO signal

IIF

in the receiver

Ideal LO signal Finite bandwidth of

IIF

LO

circuits alters LO

Phase offset

waveform shape

in LO signals

Mismatches in capacitors introduces gain error and distortion.

FIGURE 7.5 Mismatches and imperfections in a single channel of a typical multi-channel communication system.

7.4.3

Mismatches, Imperfections, and Offsets in the System

In the preceding section it was assumed that the reconstruction matrix H perfectly matches the circuit implementation of the system, which is seldom the case. There are several offsets and mismatches present in the transmitter, the channel, and the receiver that deteriorate the system performance. Figure 7.5 gives a brief outline of all the mismatches that could be present in a multi-channel communication system. The multi-carrier signal generated by the IFFT block at the transmitter is modulated by a local oscillator signal to RF frequencies. Ideally, this LO frequency should be perfectly synchronized with the LO signal at the receiver. However, there will always be some frequency offset between the two signal sources. The wireless channel between the transmitter and receiver introduces a gain and phase variation to each subcarrier in the multi-carrier signal.1 A certain time delay for the input signal arriving at the receiver introduces different initial phase delays for each subcarrier. The LNA and G m stage could introduce gain and phase offsets among the different channels, due primarily to the variations in the process and imperfections in the implementation of each channel. There could be variations in the capacitors used in the charge-sampling filter, which would result in an additional gain error. If square LO signals are used for mixing, the waveform could have an exponential rise and decay due to the finite 1A

flat gain can model the path between the source and the receiver only if the bandwidth of the analog samples in each channel is narrowband enough. Multi-path fading can also affect the model and needs to be taken into consideration in a typical scenario. However, study of these phenomena is beyond the scope of this chapter.

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bandwidth of the circuit. Further, the LO signals are subject to frequency and phase offsets. However, this is avoided by generating all the LO signals and the sampling clocks from a single reference in the receiver. Even if the reference suffers from a frequency offset, the LO signals and the sampling clocks are still aligned with respect to each other. In the presence of all these mismatches and offsets, it is clear that the H matrix defined earlier would be unable to detect the symbols: thus the need for a calibration technique to learn these mismatches and offsets. 7.4.4

Calibration Algorithm

The complete system calibration is illustrated in Fig. 7.6. Initially, the frequency offset in the LOs at the transmitter and receiver is estimated using a maximum-likelihood estimator, which is explained in detail in Section 7.4.5; next, the estimation matrix H is initialized; and finally, the least-mean-squares (LMS) [17] algorithm is used to calibrate all the mismatches and imperfections. Once the frequency offset in the carriers is estimated, the problem is reduced to calibration of static mismatches and offsets in a communication system. The equation for estimation of the transmitted data aˆ is aˆ = H · r = (G HG)−1 G H · r

(7.13)

where H is the least-squares solution of the system and r contains the sampled output. For the best performance, the matrix H must match the actual circuit implementation Multi-carrier signal Transmitter

Multi-carrier signal Receiver

e j 2π ( fo +∆Fc )T

r a

LO

Modulator noise

r r

Least Squares Estimation of data with LMS calibration

r ) a = (GH G)−1G H r

) a

rˆ

r a ref

Estimated Data

r r

Forward Problem calibration

r a ref

) a

Reverse Problem calibration

r r

G

r a ref

r r

r a ref

( corrected )

r r

correction

)

e − j 2π ∆Fc (L−1)T

H = (G H G)−1G H

FIGURE 7.6 Complete multi-channel charge sampling receiver system with frequency offset estimation and LMS calibration of static mismatches and offsets.

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of the system perfectly. Figure 7.6 illustrated two techniques of calibration of the system. The first method involves calibration of the G matrix (forward problem), and in the second method, the H matrix is calibrated (reverse problem). The leastmean-squared (LMS) algorithm is used for calibration in both techniques. The update equation for the H matrix in the reverse problem calibration is based on the normalized LMS algorithm [17] and is given by ea (L) * r Hˆ (L + 1) = Hˆ (L) + r 2

(7.14)

where ea is the error in the a vector. In the case of forward problem calibration, the complexity analysis in Section 7.5.2 shows that by splitting the computation into two steps, aˆ = (G H G)−1 · p and p = G H · r, the complexity could be reduced. The LMS update is applied to the G matrix by considering the forward problem r = G · a and using the following update: er (L) * a ˆ + 1) = G(L) ˆ G(L + a2

(7.15)

where er is the error in the r vector. From the updated values of the G matrix, (G H G)−1 and G H are computed for the next block. It is shown in Section 7.6 that the LMS algorithm tracks the system mismatches and over a period of time converges to the ideal solution. The two techniques of calibration are similar from a performance point of view. The next question is: What initial values should be used for the H matrix? Choosing an arbitrary H matrix would result in an extremely slow convergence. There is a need to start with an initial H matrix that is close to the desired solution. The linear matrix equation that represents the forward problem is G · a = r

(7.16)

If the transmitted data, a , is given by a = [1000 · · · ], the received vector r is the first column of matrix G, along with a noise term. The transmitted vector a is repeated in sequence [1000 · · · ], [0100 · · · ], [00100 · · · ], and so on, to compute each column of the G matrix. After traversing through all the elements of a , the entire G matrix is formed. From the G matrix, (G HG)−1 and G H are computed, which are used for symbol detection based on the LS estimate (7.13). However, this does not represent the ideal solution because the r vector is contaminated by the noise present in the circuit. Using this G matrix as the initial starting point, the LMS algorithm can be used to converge quickly to the ideal solution. It appears that the drawback of this method is that an inverse operation (G HG)−1 needs to be performed. However, the sparsity of the G HG matrix is exploited to drastically reduce the complexity of the inverse computation. In the next section we discuss a technique to estimate the frequency offset in the multi-channel charge-sampling receiver.

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7.4.5

201

Frequency-Offset Estimation

Several techniques have been proposed to estimate the frequency offset in OFDM systems [18,19]. In the following discussion, it is seen how the frequency offset can be factored out from the received signal r despite the presence of several mismatches, and the maximum likelihood (ML) estimation technique could be used to estimate the frequency offset [18]. M−1 N −1 |n=0 , is defined in (7.5) and is The expression for the data sampled, R(m, n)|m=0 rewritten here for convenience:
Rm,n,L =

mTs +Tc +T

mTs +T

x L (t)
∗n (t) dt

(7.17)

Here L represents the block number.
n (t) is the nth LO signal in the multi-channel receiver, and combining the in-phase and quadrature components, it can be represented as
n (t) = e− j[2π f LO (n)t + φLO (n)] − e j[3 · 2π f LO (n)t + 3φLO (n)] + e− j[5 · 2π f LO (n)t + 5φLO (n)] − · · ·

(7.18)

x L (t) is the input multi-carrier signal corresponding to the Lth block and is given by S      ai (s) cos 2π Fc (s)t + φc (s) + 2π Fc (L − 1)T x L (t) = s=1

   + aq (s) sin 2π Fc (s)t + φc (s) + 2π Fc (L − 1)T

(7.19)



where Fc (s) = Fc (s) + Fc , Fc is the carrier frequency offset, φc (s) is the initial phase offset of carrier s, and 2π Fc (L − 1)T is the accumulating phase offset in block L that results from Fc . Substituting (7.18) and (7.19) in (7.17) yields
Rm,n,L = An e jθn

mTs +Tc +T mTs +T

S      ai (s) cos 2π Fc (s)t + φc (s) + 2π Fc (L − 1)T s=1

   + aq (s) sin 2π Fc (s)t + φc (s) + 2π Fc (L − 1)T  × e− j[2π f LO (n)t + φLO (n)] − · · · dt

(7.20)

where An e jθn is the lumped complex constant representing the gain and phase mismatch in the nth channel. φLO (n) is the initial phase offset in the nth LO signal. The

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offset in the integration window, T , can be brought inside the integration as a phase   offset in the signals. φc (s) and φLO (n) are defined as follows: 



φc (s) → φc (s) + 2π Fc (s) T + 2π Fc (L − 1)T 

φLO (n) → φLO (n) + 2π f LO (n) T.

(7.21) (7.22)

Incorporating the new expressions, (7.20) becomes
Rm,n,L =

mTs +Tc mTs

S       ai (s) cos 2π Fc (s)t + φc (s) s=1

    + aq (s) sin 2π Fc (s)t + φc (s) × An e jθn 

 × e− j[2π f LO (n)t + φLO (n)] − · · · dt

(7.23)

Writing the carrier signals in terms of complex exponentials, the following expressions are obtained:

     1 j(2π F  (s)t + φ  (s))   − j(2π F (s)t + φ (s)) c c c c e +e cos 2π Fc (s)t + φc (s) → 2

       1   j(2π F (s)t + φ (s)) − j(2π F (s)t + φ (s)) c c c c e −e sin 2π Fc (s)t + φc (s) → 2j (7.24) Now (7.23) becomes

 S

   ai (s) j(2π F  (s)t + φ  (s)) c c e + e− j(2π Fc (s)t + φc (s)) 2 mTs s=1

   aq (s) j(2π F  (s)t + φ  (s)) − j(2π F (s)t + φ (s)) c c c c e −e + 2j

  (7.25) × An e jθn e− j[2π f LO (n)t + φLO (n)] − · · · dt


Rm,n,L =

mTs +Tc

The term inside the integral of (7.25) contains tones at several frequencies, in cluding the desired tone at f LO (n) − Fc (s) and higher-order harmonics at f LO (n) +    Fc (s), 3 f LO (n) ± Fc (s), 5 f LO (n) ± Fc (s), and so on. However, the charge-sampling sinc filter attenuates these high-frequency tones. Neglecting these high-frequency

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terms, (7.25) is simplified to the following expression:
Rm,n,L =

S 

mTs +Tc



ai (s) j[2π F  (s)t + φ  (s) − 2π f LO (n)t + φ  (n)] c c LO e 2 mTs s=1  aq (s) j[2π F  (s)t + φ  (s) − 2π f LO (n)t + φ  (n)] c c LO e dt (7.26) + 2j An e

jθn



The phase term φc (s) in (7.26) is expanded using (7.21). Factoring out the term e2π jFc (L−1)T , the following expression is obtained: Rm,n,L = e2π jFc (L − 1)T ×




mTs +Tc mTs

× +

ai (s) e 2

S 

An e jθn

s=1

   j[2π Fc (s)t+φc (s)+2π Fc (s)T −2π f LO (n)t+φLO (n)]

  aq (s) j[2π Fc (s)t+φc (s)+2π Fc (s)T −2π fLO (n)t+φLO (n)] dt e 2j

(7.27)

If it is assumed that the same data set is transmitted in successive blocks, it can be noted that the only term that will vary in Rm,n,L is the term outside the integral. Let Rm,n,L = αm,n e jβm,n ; then Rm,n,L+1 is given by Rm,n,L+1 = e2π jFc T × αm,n e jβm,n

(7.28)

In a typical scenario, the quantities Rm,n,L and Rm,n,L+1 are contaminated by some AWGN noise. If these noise terms are also included in the expressions, Rm,n,L and Rm,n,L+1 become Rm,n,L = αm,n e jβm,n + Wm,n,L Rm,n,L+1 = e2π jFc T × αm,n e jβm,n + Wm,n,L+1

(7.29)

where Wm,n,L and Wm,n,L+1 are noise terms in Rm,n,L and Rm,n,L+1 , respectively. From (7.29), the frequency offset FC is estimated by applying the maximum likelihood (ML) algorithm used to estimate the frequency offset in the OFDM case [18]. The ML estimate of Fc is obtained by taking the mean of the argument over K consecutive blocks and is given by K ∗ Im(Rm,n,L+1 Rm,n,L ) 1 −1 L=1 ˆ tan  K  Fc = 2π T Re(R R∗ ) L=1

m,n,L+1

m,n,L

(7.30)

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The choice of K depends on the noise present in the system and the desired accuracy of estimate. This estimate of the frequency offset  Fˆc is used to make a correction in the received vector rL . The corrected vector rL (update) is given by rL (update) = rL e − j2πFc (L−1)T

7.5

(7.31)

A COMPARATIVE STUDY

The structure of the TD receiver resembles a multi-channel filter bank front end. However, there are some fundamental differences that provide some analog and digital complexity reductions that can be instrumental in the practical applications highlighted in Section 7.9. In this section the multi-channel sinc filter bank is compared with conventional analog filter banks. Both the analog and digital complexities of both filter banks are analyzed and compared in a multi-carrier receiver scenario. 7.5.1

Analog Front-End Complexity

FIGURE 7.7 bank.

Digital Post Processing

Initially, the front-end analog complexity of both filter banks is considered. Figure 7.7 shows a very simplified block diagram of the multi-channel charge-sampling sinc filer

Digital Post Processing

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Block diagram of multi-channel sinc filter bank and multi-channel analog filter

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bank and the multi-channel analog filter bank with a continuous integrator. The key difference in both filter banks is the implementation of the filer in each channel. In the sinc filter, the windowed integration of the signal combines filtering and sampling in a single stage. There are two replicas of the charge-sampling circuit, so that when the charge on one capacitor is being sampled, integration continues on the other capacitor. In the analog filter bank, the input signal is filtered by the active RC integrator circuit and the output voltage of the integrator is sampled by a sampleand-hold amplifier. Assuming that both filter banks are used to implement the multicarrier receiver example described in Section 7.6, a simplified first-order estimate of the capacitor sizes and op-amp gain–bandwidth product (GBW) is obtained to compare the complexity of both implementations. The transconductance (G m ) in both cases is assumed to be 1 mA/V, and the sampling time (Ts ) is taken to be 4 ns. Assuming a value of 1 pF for the capacitors in the sinc filter bank, the dc gain is G m Ts /Cs = 1m × 4n/1 p = 4. The dc gain in the analog filter bank is given by G m R f , and to achieve the same dc gain with G m = 1 mA/V, R f = 4 k. The 3-dB cutoff frequency in the sinc filter bank is 0.44/Ts = 0.44/4n = 110 MHz [20]. In the analog filter bank, the 3-dB cutoff frequency is given by 1/2π R f C f , and to achieve the same cutoff frequency, C f ∼ 360 fF. The total integrated noise of the sampled signal in the sinc filter bank is KT/C [2G m Ts /C] + KT/C = 9KT/C [20]. In both cases, the op-amps are assumed to be noiseless. In the analog filter bank, the total integrated noise in the sampled signal is G m R f · KT/C f + KT/C f + KT/Cs . Since C f ∼ C/3 and G m R f = 4, the total integrated noise is 13KT/C + KT/Cs . Thus, it is clear that the analog filter bank adds more noise than the sinc filter bank, and Cs must be large to keep the noise low. In this example, Cs = 1 pF is a good value considering the GBW requirement of the op-amp in the sample-and-hold circuit. In the case of the analog filter bank, the GBW of the op-amp in the integrator is given by the expression f u 1/(2π R f C f ). Since C f ∼ C/3, f u = 1.5 GHz is required for this op-amp. For the op-amp in the sample-and-hold circuit, f u ≥ 7/Tset for 10-bit accuracy. Since the sampling time Ts = 4 ns and the sample-and-hold operation involves two phases, the value of Tset = 2 ns, and hence for this op-amp, f u ≥ 3.5 GHz. In the sinc filter bank, it is shown in Section 7.7 that for 10-bit accuracy, the required GBW of the op-amp in each path, f u ≥ 1.75 GHz. Due to the interleaved two-path topology and additional 3Tc /4 seconds for settling, the GBW of the op-amp in the charge-sampling circuit is about half the GBW of the op-amp in the sample-and-hold circuit. To summarize, although the capacitors in the sinc filter bank are larger than those in the analog filter bank, because of the need of an additional resistor R f for finite dc gain in the analog filter bank, there might not be significant area savings. Further, the noise in the analog filter bank is more than 1.5 times higher than that in the sinc filter bank. Considering the load capacitance and the GBW of the op-amp in each case, the power consumption of the op-amps in the analog filter bank is roughly 15% higher than that in the sinc filter bank. Another significant advantage of the sinc filter bank is that the bandwidth of the filter can be tuned easily by varying the samplingtime duration Ts , which is not possible in the analog filter bank, whose bandwidth is determined by the values of R f and C f .

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7.5.2

Digital Complexity Analysis

In this section we analyze the computational complexity in the digital processing block of the multi-channel sinc filter bank. The entire analysis is centered on the sparsity of the G HG matrix, which is exploited to drastically reduce the complexity of symbol estimation. The first step is to analyze the complexity of the symbol estimation, which is given by aˆ = H · r. Using the least-squares solution for H , aˆ = (G HG)−1 G H · r. This computation is decomposed into two steps, which reduces complexity. First p = G H · r is obtained, and then aˆ = (G HG)−1 p is used to estimate the symbols. In obtaining p, the complex representations are retained for G and r for clarity in the analysis. The resulting complex p can be expanded to contain only real values and is then used in the second step. In this discussion it is assumed that frequency offset in the carriers has already been corrected. The other static offsets and mismatches are also omitted for sake of clarity; however, including them does not alter the analysis. Each element in G is given by
mTs +Tc e− j2π Fc (s)t
n (t) dt G m,n,s = mTs

=e

− j2π Fc (s)mTs




Tc

e− j2π Fc (s)t
m,n (t) dt

(7.32)

0

where
m,n (t) is the mth segment of
n (t). Without loss of generality, the LO signals f LO (n) can be chosen such that f LO (n) · Ts is an integer, which means that the basis functions
n (t) are periodic with respect to Ts . So
m,n (t) is a periodic repetition of
0,n (t) and (7.32) becomes
Tc G m,n,s = e− j2π Fc (s)mTs e− j2π Fc (s)t
0,n (t) dt 0

=e

− j2π Fc (s)mTs

Q s,n

(7.33)

T where Q s,n = 0 c e− j2π Fc (s)t
0,n (t) dt. The carrier frequency is given by Fc (s) = Fo + s/T , where Fo is the transmitter carrier frequency. Fo can be chosen such that Fo Ts is an integer, and since M Ts = T , e− j2π Fc (s)mTs = e− j2πsm/M , and hence (7.33) becomes G m,n,s = e− j2πsm/MQ s,n

(7.34)

Using (7.34), each element of p can be written as ps =

M−1 N −1 

G ∗m,n,s Rm,n

m=0 n=0

=

N −1  n=0

=

N −1  n=0

Q ∗s,n

M−1 

Rm,n e j2πsm/M

m=0

Q ∗s,n Ts,n

(7.35)

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207

where Ts,n in (7.35) is periodic in s with a period M, and similar to an M-point FFT, the complexity of computation of the complete Ts,n is o(NM log M). The total complexity of computation of p includes an additional NS multiplications and is given by o(NM log M) + o(NS). However, this involved all complex multiplications and taking into account the fact that each complex multiplication involves four real multiplications, the complexity of computation of p is o(4NM log M) + o(4NS) ∼ o(4S(N + log M)). The next step is to determine the complexity of (G HG)−1 · p. It is shown in Section 7.8 that G HG is a sparse matrix with only 2N nonzero elements in each row. It can be seen that the inverse of G HG also has the same number of nonzero elements. So the complexity of (G HG)−1 · p is o(2N · 2S) = o(4 NS). It is to be noted that all computations in this step are real multiplications, and the p used in this step is expanded to contain only real terms. Putting it all together, the total complexity of symbol estimation aˆ = H · r is o(4S(N + log M)) + o(4 NS). It must be noted that the simplification in (7.32) is possible due to the reset in integration windows in charge-sampling circuits. In the case of multi-channel analog filter banks (such as integrators without reset), the complexity of symbol detection for the same specifications is o(4NMS). The multi-carrier example described in Section 7.6 is considered to compare the complexity of the LS estimate of a multi-channel receiver with the sinc and analog filter banks and the conventional FFT used in OFDM receivers. The complexity of an S-point FFT is o(S log S), and in terms of real multiplications it is o(4S log S). In this example, N = 5, M = 32, and S = 128: Complexity of FFT: o(4S log 128) = o(28S) Complexity of LS estimate: Sinc filter bank: o(4S(5 + log 32)) + o(20S) = o(60S) Analog filter bank: o(4N M S) = o(4 · 160S) = o(640S) It can be seen that in the case of the sinc filter bank, the complexity of symbol detection is only marginally higher than that of the conventional FFT. However, in the case of the analog filter bank, the complexity of detection is significantly higher than that of the FFT. Next, the complexity of symbol detection for the sinc filter bank in the calibration phase is compared for the forward and reverse problem calibration scenarios. In forward problem calibration, the G matrix is updated after each block, so symbol detection comprises the following computations: G HG, (G HG)−1 , p, and (G HG)−1 · p, and the total complexity of these compuations is given by o(4N 2 · 2S) + o(4N 2 · 2S) + o(4S(N + log M)) + o(4 NS) = o(16N 2 S) + o(4S(1 + log M)) + o(4 NS). In reverse problem calibration, the H matrix is updated for every block, and symbol detection involves the computation H · r, whose complexity is o(4NMS). Considering the example above, the complexity of symbol detection in the calibration mode for the two cases is as follows: Complexity of LS estimate (calibration phase): Forward problem: o(400S) + o(40S) + o(20S) = o(460S) Reverse problem: o(4 N M S) = o(4 · 160S) = o(640S)

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TABLE 7.1

Complexity of Sinc and Analog Filter Banks TD Receiver (Sinc Filter Bank)

Analog Filter Bank

Analog front-end complexity

Larger capacitors No resistor required; reset ensures finite dc gain Less noise Small GBW for op-amps

Smaller capacitors Resistor required for finite dc gain Noise is high Large GBW for op-amps

Analog power consumption

Less

High

Digital complexity (estimation)

o(4S(N + log M)) + o(4N S) Example: o(60S)

o(4NMS) Example: o(640S)

Digital complexity (calibration)

o(16N 2 S) + o(4S(1 + log M)) +o(4NS) Example: o(460S)

o(4NMS) Example: o(640S)

Digital power consumption

Significant power reduction Example: About 10% of power in analog filter

Much higher than sinc filter bank Example: 10 times more power than sinc filter

It can be seen that there is a reduction in complexity when using the forward problem calibration compared to the reverse problem calibration. Again, this reduction could be achieved only in the sinc filter bank; in the analog filter bank, the complexity is o(640S) for both forward and reverse problem calibration. Table 7.1 summarizes the complexity analysis of the sinc and analog filter banks.

7.6

SIMULATIONS

In this section simulation results are presented to show LMS calibration and frequency offset estimation of the system. A system model is created in MATLAB. The input to the system is a QPSK-modulated signal of 128 carriers with a bandwidth of 1 GHz from 1 to 2GHz. The receiver model used in this example has five parallel I and Q channels. The frequencies of the mixing signals (I and Q) used in each channel are chosen such that they are uniformly spaced around the center frequency of 1.5 GHz and also are orthogonal to each other in a signal block of duration T . The output of the mixer is integrated over a time window of duration 6 ns. The integrated outputs are processed digitally to recover the data. An overlap of 2 ns is introduced in between the integration windows, so the effective time duration between samples is 4 ns (i.e., the sampling frequency is 250 MHz). Symbol detection is carried out using the leastsquares estimator. AWGN noise is added to the input signal such that the SNR = 100 dB. The system mismatches and offsets discussed earlier are introduced in this model. There is a random delay T in the arrival of the signal block. Each subcarrier s has a random initial phase offset φc (s). All subcarriers have a frequency offset Fc .

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209

Each channel has a random gain and phase mismatch An e jθn . All the in-phase and quadrature LO signals have a random initial phase offset φLO (s). A finite rise and fall time is introduced in all the clocks, including the LO signals. It is assumed that the LO signals and the sampling clocks are aligned, as they are generated from a single reference source. In the initial simulations it is assumed that the frequency offset Fc in the subcarriers is already estimated, and the problem is reduced to the calibration of static mismatches. The initial H matrix is formed by the technique described in Section 7.4.4. Figure 7.8 shows the variation of mean-squared error vs. iterations, and Fig. 7.9 shows the SNDR across the subcarriers after convergence is achieved. As expected, the LMS algorithm could calibrate all the static mismatches, and the mean SNDR across carriers is close to the input signal SNR of 100 dB. Further, when the SNDR is better than 20 dB, data transmission can be started and in the background LMS calibration can be continued by making difficult decisions on the data received and then computing the error. This is possible because for an SNDR greater than 20 dB, the bit error rate (BER) is low enough to calibrate in a blind fashion. The maximum likelihood estimate, discussed earlier, is used to correct the frequency offset Fc . Figure 7.10 shows the estimated value of Fc and L, where L is the number of blocks used to estimate the frequency offset. Based on these simulations, an optimum value of L = 500 is chosen for this estimation. Figure 7.11 shows a comparison of the performance of the receiver in the presence of frequency offset in carriers with and without frequency offset estimation. The SNDR is plotted vs. frequency offset for both cases. It can be seen that with frequency offset estimation there is roughly about a 20-dB improvement in the mean SNDR across carriers.

−70

−75 Mean squared error (dB)

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−80

−85

−90

−95

−100 0

0.5

1

1.5 2 Number of blocks

2.5

3 x 10

4

FIGURE 7.8 Convergence of mean-squared error with the number of blocks when the initial H matrix is formed from the received r vector.

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120 115

SNDR (dB)

110 105 100 95 90 85 80

1

1.2

1.4 1.6 Carrier Frequency (Hz)

1.8

2 x 10 9

FIGURE 7.9 Performance of the receiver with static mismatches and offsets following LMS calibration, when the initial H matrix is formed from the received r vector. Frequency Offset Estimation − ∆ Fc vs. Number of blocks (L) 52

9 8

∆ Fc = 100Hz

102

0

100

100

200

300

400

Estimate: 95.7 Hz Error: 4.3 %

98 96 94 92

0

100

200

300

400

Estimate: 48.9 Hz Error: 2.2 %

50 49 48 0

500

100

200

300

400

500

Estimate: 476.8 Hz Error: 4.6 %

480 460

500

0

100

200

300

400

500

5200 Estimate: 987.9 Hz Error: 1.22 %

1000

0

100

200

300

FIGURE 7.10

400

500

∆ Fc = 5000Hz

1050

950

51

47

500 ∆ Fc = 500Hz

7

∆ Fc = 50Hz

Estimate: 8.9 Hz Error: 11%

10

c

∆ F = 10Hz

11

∆ Fc = 1000Hz

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5000 Estimate: 4635 Hz Error: 7.3 % 4800 4600 4400 0

100

200

300

Estimation of frequency offset for K = 500.

400

500

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GAIN–BANDWIDTH PRODUCT REQUIREMENT FOR AN OP-AMP

211

80 Before Freq offset estimation After freq offset estimation

70 60 SNDR (dB)

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50 40 30 20 10 0 100

101

10 2 103 −> Frequency offset (Hz)

10 4

FIGURE 7.11 Plot showing SNDR vs. frequency offset in carriers with and without frequency offset estimation.

7.7 GAIN–BANDWIDTH PRODUCT REQUIREMENT FOR AN OP-AMP IN A CHARGE-SAMPLING CIRCUIT A lower bound on the gain–bandwidth product (GBW) of the op-amp in a chargesampling circuit is obtained in this section. Figure 7.12 shows a simplified chargesampling integrator. The windowed integration is embedded in the input current signal by considering it to be a unit pulse of duration Tc . The op-amp is assumed to be a single-pole amplifier with dc gain Ao and a 3-dB bandwidth given by ωo . The transfer function of this op-amp is A(s) =

Ao 1 + s/ωo

(7.36)

The simplified transfer function of the entire charge-sampling integrator can be shown as 1 vo (s) =− i(s) sC(1 + s/Ao ωo )

(7.37)

i(t) v(t)

C

i(t)

1

Gm Ro

vo(t) Tc

FIGURE 7.12

Schematic of a simplified active charge-sampling integrator.

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This expression assumes that Ro C 1/Ao ωo . The Laplace transform of the input current signal i(t) = u(t) − u(t − Tc ) is given by i(s) =

1 − esTc s

(7.38)

Substituting (7.38) in (7.37) yields 1 1 − esTc s sC(1 + s/Ao ωo ) 

1 1 1 −sTc ) 2− = − (1 − e C s s(s + Ao ωo )

vo (s) = −



 1 1 L−1 2 − s s(s + Ao ωo )

 1 1 − L−1 e−sTc − s2 s(s + Ao ωo )

L−1 [vo (s)] = −

(7.39)

1 C

  1 1  −Ao ωo t Ao ωo (t−Tc ) vo (t) = − Tc − e −e C Ao ωo

(7.40)

(7.41)

At the end of Tc seconds, the current is steered to the other path and Tc seconds are available to sample and discharge the charge on the capacitor. Allocating Tc /4 seconds for discharge, the vo (t) has an additional 3Tc /4 seconds to settle. Then vo (t) at the end of this period is given by

vo

7Tc 4

 =−

  1 1  −Ao ωo 7Tc /4 Tc − e − e Ao ωo 3Tc /4 C Ao ωo

(7.42)

The gain–bandwidth product, GBW = Ao ωo , and the error in the output voltage, e(GBW), is given by e(GBW) =

 1 1  −GBW7Tc /4 e − eGBW3Tc /4 C GBW

(7.43)

Tc 1 C 2N

(7.44)

For N -bit precision, e(GBW) ≤

Considering the example discussed in Section 7.5, where Tc = 4 ns and N = 10, the minimum required GBW for the op-amp in a charge-sampling circuit is 1.75 GHz.

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SPARSITY OF (G HG)−1

7.8

213

SPARSITY OF (G HG)−1

In this section it is shown that G HG is a sparse matrix, and hence (G HG)−1 is − j2πsm/M Q s,n . If G HG is denoted by also a sparse  matrix. From (7.34), G m,n,s = e X = X i, j S×S , X i, j can be written as X i, j =

M−1 N −1 

e− j2π(i− j)m/M Q i,n Q ∗j,n

m=0 n=0

=

N −1 

Q i,n Q ∗j,n

n=0

X i, j =

⎧ ⎪ ⎨ ⎪ ⎩

M

N −1 

M−1 

e− j2π(i− j)m/M

(7.45)

(i − j)mod M = 0

(7.46)

m=0

Q i,n Q ∗j,n

n=0

0

otherwise

It is clear that X is nonzero only when (i − j) mod M = 0. When the complex matrix X is expanded to represent the real and imaginary values separately, the nonzero elements of X form a mesh with only 2N nonzero elements in each row. Figure 7.13 shows the sparsity pattern of a G HG matrix generated in MATLAB. Further, from

Sparsity pattern of GH G 0

50

100

150

200

250

0

50

100

FIGURE 7.13

150 nz = 4808

200

250

Sparsity pattern of G HG.

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0

50

100

150

200

250

0

50

100

150 nz = 5080

200

250

FIGURE 7.14 Sparsity pattern of (G HG)−1 .

the fundamental definition of the inverse of a matrix, it can be seen that (G HG)−1 has the same sparsity. Figure 7.14 shows the sparsity pattern of (G HG)−1 . This sparsity in (G HG)−1 greatly reduces the computational complexity.

7.9 7.9.1

APPLICATIONS Software-Defined-Radio Multi-Standard Receiver

The TD receiver provides a convenient trade-off between complexity and speed. Different speeds and dynamic range can be achieved by varying the number of parallel paths used for signal expansion and quantization. This flexibility offered by the TD receiver makes it an attractive option for a software-defined-radio multistandard receiver. For low-speed high-resolution standards such as GSM (200 kHz and 14 bits) and Bluetooth (1 MHz and 12 bits), only one or two paths of the frequency-domain ADC can be activated. The high degree of oversampling can be exploited in a sigma-delta ADC to provide the necessary resolution. As the input signal in this case is narrowband, the simple integrator filter can be replaced by a more complex multi-stage charge-sampling infinite impulse response (IIR) filter to provide better antialiasing. Such higher-order antialiasing filters for current-mode sampling have been used for RF receivers [8–10]. When very high sampling speeds are required for wideband input signals such as the UWB, all the parallel paths are turned on, to provide maximum sampling speed. Thus, the FD receiver can be

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CONCLUSIONS

215

Digital Post Processing

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FIGURE 7.15 Transform-domain receiver used in a multi-standard receiver that can cope with narrowband, wideband, and ultrawideband communications signals.

configured to different standards simply by choosing the number of parallel paths to be activated, making it an interesting candidate for a software-defined radio multistandard receiver. 7.9.2

Transform-Domain Distributed Sensor Relay

The transform-domain (TD) receiver idea can be used in a sensor network. Each sensor node computes a TD coefficient by mixing the received signal with a locally generated basis function (see Figs. 7.15 and 7.16). Each locally computed TD coefficient is transmitted to a fusion center using some kind of multiple access transmission, such as DS-CDMA. In this sensor network relay, fundamental design specifications such as the sampling rate and transmission rate of each sensor node are reduced linearly with the number of sensors, lowering complexity and saving power per sensor node.

7.10

CONCLUSIONS

Multi-path transform-domain charge-sampling wideband receivers that expand the received signal over a basis set and then operate on the basis coefficients have been described. The TD receiver has the advantage of sub-Nyquist sampling rate, enabling parallel digital signal processing, flexibility, and scalability in design, making it an attractive option for software-defined radio and cognitive radio. The TD receiver

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Data

S1

sampled

S3

@

∫

sub-Nyquist rate by

∫

sensor nodes S1-S4 is

transmitted

to

Fusion Center for processing

a0 a1 a2 .

..

a0 r1

S2

r2

∫

r3

Least

Calibration

a2

Sync

Squares Estimator

Ref. signal

LMS

a1

and

r4 Error RF broadband signal Mixer

Charge sampling Integrator

∫

mTs+Tc

S4

(.) dt mTs

∫

LO signal Modulated signal (to central unit)

Transmitter

hi(t) is the equivalent channel impulse response for sensor node Si

FIGURE 7.16 Distributed sensor relay using the transform-domain receiver idea in a distributed fashion in order to reduce the tracking bandwidth and sampling rate at each sensor node. No quantization is needed and the TD coefficient is retransmitted to the central unit for processing.

exhibits very low analog and digital complexity compared with more traditional analog approaches, such as filter banks based on continuous-time filters. A complete system calibration scheme has been presented for the multi-channel receiver based on sinc filter banks. This consists of a maximum-likelihood estimation of the frequency offset in the carriers followed by a normalized LMS calibration of all the static gain and phase mismatches in the receiver. It is shown that the reset in the integration windows greatly simplifies computation of the least-squares estimate for the detection of symbols. Its complexity is comparable to that of conventional FFT, unlike multichannel receivers with continuous filters, where the computational complexity of the DSP block is several times higher than in the multi-channel sinc filter bank.

REFERENCES 1. R. B. Staszewski, K. Muhammad, and D. Leipold, “Digital RF Processor (DRPTM ) for cellular phones,” in IEEE/ACM International Conference (ICCAD’05), pp. 122–129, Nov. 2005. 2. R. Bagheri, A. Mirzaei, S. Chehrazi, M. E. Heidari, M. Lee, M. Mikhemar, W. Tang, and A. A. Abidi, “An 800-MHz-6-GHz software-defined wireless receiver in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2860–2876, Dec. 2006.

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REFERENCES

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3. S. Hoyos, B. M. Sadler, and G. R. Arce, “Broadband multicarrier communications receiver based on analog to digital conversion in the frequency domain,” IEEE Trans. Wireless Commun., vol. 5, no. 3, pp. 652–661, Mar. 2006. 4. S. Hoyos and B. M. Sadler, “Ultra-wideband analog to digital conversion via signal expansion,” IEEE Trans. on Veh. Technol. (invited), vol. 54, pp. 1609–1622, Sept. 2005. 5. ———, “UWB mixed-signal transform-domain direct-sequence receiver,” IEEE Trans. Wireless Commun., vol. 6, pp. 3038–3046, Aug. 2007. 6. G. Xu and J. Yuan, “Performance analysis of general charge sampling,” IEEE Trans. Circuits Syst. II, vol. 2, pp. 107–111, Feb. 2005. 7. G. Xu, “Comparison of charge sampling and voltage sampling,” in IEEE Custom Integrated Circuits Conference (CICC’04), pp. 440–443, Aug. 2000. 8. S. Chehrazi, R. Bagheri, and A. Abidi, “Noise in passive fet mixers: a simple physical model,” in IEEE Custom Integrated Circuits Conference (CICC’04), pp. 374–378, Sept. 2005. 9. K. Muhammad and R. B. Staszewski, “Direct RF sampling with recursive filtering in charge domain,” in Proc. 2004 IEEE International Symposium on Circuits and Systems, vol. 1, pp. I-577 to I-580, May 2004. 10. S. Karvonen, T. Riley, and J. Kostamovaara, “Charge-domain FIR sampler with programmable filtering coefficients,” IEEE Trans. Circuits Syst. II, vol. 53, no. 3, pp. 192–196, Mar. 2006. 11. X. Chen, J. Silva-Martinez, and S. Hoyos, “A CMOS differential noise cancelling low noise transconductance amplifier,” in Proc. DCAS 2008, Oct. 2008. 12. F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, “Noise cancelling in wideband CMOS LNAs,” in Digest of Technical Papers, ISSCC, pp. 406–407, Feb. 2002. 13. P. Prakasam, M. Kulkarni, X. Chen, Z. Yu, S. Hoyos, J. Silva-Martinez, and E. SanchezSinencio, “Applications of multi-path transform-domain charge sampling wideband receivers,” IEEE Trans. Circuits Syst. II, vol. 55, no. 4, pp. 309–313, Apr. 2008. 14. J. A. C. Bingham, “Multicarrier modulation for data transmission: an idea whose time has come,” IEEE Commun. Mag., vol. 28, pp. 5–14, May 1990. 15. J. G. Proakis, Digital Communications, 4th ed. New York: McGraw-Hill, 2001. 16. S. Hoyos and B. Sadler, “Ultra-wideband analog-to-digital conversion via signal expansion,” IEEE Trans. Veh. Technol., vol. 54, no. 5, pp. 1609–1622, Sept. 2005. 17. S. Haykin, Adaptive Filter Theory, 4th Ed. Upper Saddle River, NJ: Prentice Hall, Sept. 2001. 18. P. Moose, “A technique for orthogonal frequency division multiplexing frequency offset correction,” IEEE Trans. Commun., vol. 42, no. 10, pp. 2908–2914, Oct. 1994. 19. H. Nogami and T. Nagashima, “A frequency and timing period acquisition technique for OFDM systems,” in Personal, Indoor and Mobile Radio Communications, 1995 (PIMRC’95), Sixth IEEE International Symposium on “Wireless: Merging onto the Information Superhighway,” vol. 3, pp. 1010–, Sept. 1995. 20. G. Xu and J. Yuan, “Performance analysis of general charge sampling,” IEEE Trans. Circuits Syst. II, vol. 52, no. 2, pp. 107–111, Feb. 2005.

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Discrete-Time Processing of RF Signals RENALDI WINOTO and BORIVOJE NIKOLIC´ University of California, Berkeley, California

8.1

INTRODUCTION

Signal processing in a radio-frequency (RF) receiver consists of three fundamental elements: frequency translation, filtering, and amplification. These three elements are necessary in order to precondition the RF signal so that efficient analog-to-digital conversion of the signal desired can follow [1]. Filtering in an RF receiver, which is the main subject of this chapter, is used to cope with the large dynamic range of the input signal. The RF signal desired is sensed at the RF receiver’s antenna, along with all other electromagnetic signals that are present in the environment. Analog filters can eliminate large unwanted signals and thereby relax the dynamic-range requirements of subsequent blocks, particularly the dynamic-range requirements of an analog-todigital converter (ADC). Alternatively, some filtering in the analog domain can be transferred to the digital domain if a suitably high-dynamic-range ADC is available. Several factors must be considered in designing analog filters for an RF receiver. First and foremost are the traditional linear circuit design metrics: noise, power consumption, and distortion. Second, it is often desirable to have a precise, and programmable, corner or stopband frequency. Having precise control over the corner frequency is important, because in many cases the most troublesome blockers are those located close to the desired frequency band. If the corner frequency is not defined precisely, there is a risk of either filtering out part of the signal of interest or not sufficiently attenuating the out-of-band blockers. The programmability of the corner frequency is becoming more important with the proliferation of a variety of wireless technologies, which effectively necessitates a single RF receiver to be interoperable with different frequency bands as well as different wireless standards. Finally, the resulting filter topology or architecture should be amenable for integration with complementary metal-oxide semiconductor (CMOS) technology in order to keep the overall cost of the RF receiver low. Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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There are two classes of analog filters, continuous-time and switched-capacitor filters. A continuous-time filter can be built in several ways: using a transconductor and a capacitor (gm -C), an op-amp with an RC network (op-amp-RC), or using a transconductor with an inductor. A continuous-time filter can operate at a very high frequency, often much higher than that achievable by a switched-capacitor filter. However, in integrated-circuit form, a continuous-time filter suffers from poor control of corner frequencies. Corner frequencies of this filter are usually defined by absolute values of resistance, capacitance, or inductance, none of which can be controlled precisely in a standard low-cost integrated-circuit manufacturing technology. A switched-capacitor filter, on the other hand, operates in the sampled-data or discrete-time domain. Because it is a sampled-data system, its frequency range is limited by the sampling frequency. More important, a switched-capacitor filter is susceptible to aliasing of signals, due to its inherent sampling operation. Nevertheless, the switched-capacitor filter has become a popular filter topology, for the simple reason that it fulfills the requirements stated previously. The corner frequencies of a switched-capacitor filter are set by ratios of capacitors, which can be controlled very well in integrated circuits. Programming the corner frequency can then be accomplished by connecting or disconnecting additional capacitors as needed. Finally, high-density capacitors are readily available in modern CMOS technologies. Passive operation of a switched-capacitor filter is an old idea that has garnered renewed attention recently. We broadly define passive switched-capacitor circuits as those not needing active amplifiers, such as operational transconductance amplifiers (OTAs), in order to transfer charge between capacitors. A passive switched-capacitor circuit simply relies on achieving voltage equilibrium between two capacitors in order to perform charge transfer. Research in this area has reached a level of maturity with the recent development of commercial Bluetooth [12] and GSM RF receivers [11], an academic software-defined receiver (SDR) prototype [2], and several other published examples [10,16,29] utilizing passive switched-capacitor filters. Eliminating active elements in a switched-capacitor filter is beneficial for two reasons. First, it is generally accepted that linear amplification devices such as an OTA cannot take full advantage of CMOS scaling. Second, without the active element, the maximum operating frequency of the filter is no longer set by the closed-loop bandwidth of the OTA; instead, it is determined purely through the proper sizing of MOS switches. We make an argument in Section 8.2 that MOS switches have benefited significantly from CMOS scaling. Thus, one could expect that the performance of passive switched-capacitor filters will continue to improve in the future. In Section 8.3 we also argue that the output of a current-commutating mixer can be reformulated to appear identical to a sampled-and-held signal. Thus, the presence of a mixer in an RF receiver obviates the need to implement a separate sample-and-hold circuit. More important, it provides the means to operate a passive switched-capacitor filter at a very high sampling rate. Because the signal processing is done without amplification, being able to control circuit noise is a concern. A method of analyzing noise within a passive switchedcapacitor circuit is reviewed. Operating at a high sampling rate, or more specifically

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operating with a high signal oversampling ratio, is beneficial with respect to noise, as it tends to spread the sampling noise out over a wider bandwidth. 8.2

SCALING OF AN MOS SWITCH

The basic argument that a metal-oxide-semiconductor (MOS) switch has benefited from gate-length scaling is due to the fact that its on-conductance scales proportionally with the ratio of gate width over gate length (W/L), while the value of all other undesirable parameters or parasitics scale proportionally with the device area (WL). It is safe to assume that an MOS switch will be operated in the strong inversion region in order to get the maximum on conductance. In this region, the inversion-layer charge is given as [21]  WL(VG − VS − VT ) Q I = Cox

(8.1)

 where Cox is the gate-to-channel capacitance per unit area, VG and VS are the gate and source voltage, respectively, and VT is the extrapolated threshold voltage of the transistor. The gate voltage VG is usually connected to the highest voltage available in order to maximize the conductance. Since an MOS device is symmetrical with respect to the two ends of the conducting channel, the “source” of the MOS switch is defined to be the end of the channel with the lower potential voltage. The on-conductance, G on , of the switch is  G on = µCox

W (VG − VS − VT ) L

(8.2)

where µ is the mobility of the carriers within the channel. Finally, the energy required for a single cycle of turning an MOS switch on and off, E sw , can be calculated as (ignoring parasitics) E sw = Q I (VG − VS − VT )  = Cox WL(VG − VS − VT )2

(8.3)

To form an inversion layer under the oxide with a total charge of Q I , the same amount of charge has to be provided at the gate electrode. Similarly, when the switch is turned off, the gate has to be discharged. The energy consumed in the process of charging and discharging the gate of an MOS switch is E sw . Subthreshold conduction is neglected in this analysis, and a gate voltage of VS + VT is therefore assumed to be sufficient to turn the transistor off. This assumption is not necessary, but it simplifies the ensuing derivation. We are now in a position to make some general conclusions regarding scaling of MOS switch. If E sw is normalized with respect to G on , the following equation would result: E sw VG − VS − VT = L2 G on µ

(8.4)

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Equation (8.4) states that for the same on-conductance G on the energy required per cycle is reduced quadratically as the gate length of the transistor is reduced. One can incorporate the effects of velocity saturation by a reduction in the carrier mobility µ, which would somewhat reduce the benefit of gate-length scaling.1 The factor VG − VS − VT is an available parameter for circuit designers. This parameter trades-off the MOS switch maximum signal-handling capability with its onconductance. Charge injection is a concern for precision analog circuits utilizing MOS switches. The severity of errors induced by charge injection is proportional to the amount of inversion-layer charge [27]. After normalizing the inversion-layer charge of an MOS switch with respect to its on-conductance, the following expression results: L2 QI = G on µ

(8.5)

A reduction in the minimum allowable gate length would mean that an MOS transistor with a quadratically smaller area can be used to achieve the same on-conductance. Naturally, a smaller area transistor would contain less inversion-layer charge. Similar arguments can also be made for reduction in parasitic junction capacitances (to substrate) at the two ends of an MOS switch. The introduction of a new CMOS process usually incorporates a reduction in the minimum allowable diffusion width that is commensurate with the reduction in the transistor gate length. For this reason, a similar quadratic reduction in parasitic junction capacitances can be expected as the gate length is reduced. This analysis does not take into account the parasitic capacitances between the gate and the source–drain diffusion areas with their metal contacts. In the past, the parasitic capacitance per unit length of the transistor’s gate has remained relatively constant across different process generations. However, in the near future, the capacitance per unit length might increase, due to an increasing gate-structure height and closer proximity between the gate and the source–drain metal contacts. To summarize, MOS switches are a benefactor of CMOS scaling [4]. The availability of better MOS switches enables circuit designers to obtain a better trade-off among operating speed, voltage accuracy or resolution, and power. For example, in applications where the resolution is limited by charge-injection-induced errors, scaling of MOS transistors would enable the use of an MOS switch with a smaller area, thereby reducing the errors related to charge injection. In another application where a certain settling time is desired, use of a smaller MOS switch would allow simultaneous reduction in operating power as well as charge-injection-induced errors. Ultimately, scaling of MOS switches would be limited by the ever-increasing leakage current that exists when the transistors are supposedly in its nonconducting state. 1 Velocity saturation can be modeled by a drain–source voltage-dependent mobility; µ(V ) DS

= vdmax /(εc + εx ), where εx is the lateral electric field in the channel, vdmax the saturated carrier velocity, and εc the critical electric field when velocity saturation occurs [21].

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Such a case might mandate the use of larger-than-minimum gate-length transistors to keep leakage current to a manageable level.

8.3

SAMPLING MIXER

In this section, operation of a single-balanced current-switching mixer with a singleended output is examined. The output signal is reformulated mathematically to emphasize that the output of a mixer can be interpreted as a sampled-and-held version of the continuous-time input signal [2,13,28,30]. The choice of a singlebalanced mixer—where in one-half of the cycle, the input signal is shorted to ground—is merely for brevity of the ensuing discussions and derivations. The analysis shown below can easily be extended to a differential double-balanced currentswitching mixer. Consider the single-balanced current-switching mixer shown in Fig. 8.1. The input transconductor G m converts the input voltage VRF (t) into output current i out (t). The large output impedance of the transconductor forces the resulting current to flow through either of the two switching transistors, depending on the local oscillator (LO) phase. As a result, the output current i out undergoes frequency down-conversion, and the resulting output is taken as a voltage across the capacitor C H . The output voltage Vout is naturally segmented into two phases that are periodic in time. In the first phase, the transconductor is sourcing current into C H , and therefore actively changing the output voltage Vout . In the second phase, where the transconductor is disconnected from C H , the capacitor C H is isolated from any external input, LO Vout CH

Iout (t)

VRF t

LO

m

LO LO (n-1).TLO

FIGURE 8.1

n.TLO

(n+1).TLO

Single-balanced passive mixer with single-ended output.

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and the output voltage Vout is being held constant. These two phases can be referred to as the sample phase and hold phase, respectively. Let us define a discrete-time series vout [n], which describes the voltage Vout (t) sampled during the hold phase of each LO period: vout [n] =

qin [n] + vout [n − 1] CH


qin [n] = G m

(8.6)

nTLO +TLO /2

VRF (τ )dτ

(8.7)

nTLO

The formulation above divides the circuit operation into two parts. The first part is a charge-sampling operation, in which a charge packet qin [n] is created on each sampling instant [14]. The second part implements a discrete-time integrator, in which incoming charge packets from each sampling instant are added continuously to a running sum. In the frequency domain, an integrator realizes a lowpass filter. The charge packet qin [n] can be further reformulated as a continuous-time convolution between the input signal VRF (t) and a prefilter, or a windowing function p(t): TLO qin [n] = G m 2






nTLO +TLO /2 −∞

⎧ ⎨ 2 , p(t) = TLO ⎩ 0,

VRF (τ ) p

TLO nTLO + 2

if 0 ≤ t ≤ TLO /2



 −τ

(8.8)

(8.9)

otherwise

The formulation above emphasizes that each charge packet qin [n] is in itself the result of a two-step process: a continuous-time filtering of the input VRF (t), followed by an impulse-sampling operation. Premultiplication by the factor 2/TLO to the filter p(t) normalizes the dc gain of the filter to 0 dB. Furthermore, in this manner, the term G m TLO /2 in (8.8) simply denotes the voltage-to-charge-packet conversion gain of the mixer at dc. The frequency response of the prefilter p(t), denoted H p (), is shown in Fig. 8.2. This filter attenuates signals located at even multiples of the LO frequency f LO and passes signals located at odd multiples of f LO . In other words, the prefilter p(t) implements a (partial) antialiasing filter needed prior to the sampling operation. The filter gain at frequency f LO can be calculated to be 2/π . Sampling the resulting signal at a rate of f LO would finally down-convert the signal at frequency f LO , and consequently all other signals at integer multiples of f LO , to baseband. This reformulation is consistent with what is expected as the output of a current-switching mixer. In a current-switching mixer, signals located at odd harmonics of f LO will be susceptible to folding, but signals located at even harmonics of f LO will not be susceptible to folding.

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0 −5 −10 −15

Hp (Ω) (dB20)

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−20 −25 −30 −35 −40 −45 −50

fLO

0

2fLO

3fLO

4fLO

5fLO

6fLO

Frequency

FIGURE 8.2

Frequency response of antialiasing prefilter p(t).

Figure 8.3 displays a step-by-step process in forming the output voltage vout [n] using the formulation developed in this section. The analysis presented in this section recasts a current-commutating mixer circuit as a sampler, complete with a builtin antialiasing filter. It is worthwhile to stress the importance of this observation. Traditionally, a sample-and-hold circuit is needed prior to a switched-capacitor filter. It is needed to sample new input signals on one phase and to hold that value constant over the next phase, for further processing. This sample-and-hold circuit consumes a lot of power and is usually the bottleneck in achieving higher speed of operation or better linearity. This analysis demonstrates that a mixer, which is readily available in most RF receivers, performs the same function. In this section we also introduce the concept of a charge packet [14]. A charge packet is a nonobservable quantity, and, as the name implies, it is simply a signal expressed in the charge domain. As will be seen in the sections to follow, chargedomain analysis lends itself naturally to understanding various switched-capacitor filter topologies [9]. As a result, the succeeding analysis is done completely in the charge domain, with appropriate conversion done at the input and output of the system in order to relate the resulting charge-domain equations to observable quantities such as input and output voltages. fLO VRF(t)

GmTLO 2

Hp( )

FIGURE 8.3

qin[n]

1 1 z

qH[n] 1

1 CH

Signal flow graph diagram of a sampling mixer.

vout[n]

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8.4

FILTER SYNTHESIS

In this section a general framework for constructing discrete-time filters using passive switched-capacitor circuits is reviewed. There are two types of discrete-time filters, infinite impulse response (IIR) and finite impulse response (FIR) filters. The approach taken here is to discuss the basic building block for each filter class: a discrete-time integrator for an IIR filter and a delay cell for an FIR filter. More complex filter circuits can then easily be constructed from these basic building blocks. For more complete and rigorous analysis of switched-capacitor networks, readers are referred to the literature [9,18–20]. 8.4.1

IIR Filter Synthesis

As mentioned before, the circuit given in Fig. 8.1 contains both a discrete-time integrator and a sampler circuit. A capacitor C H 1 forms a discrete-time integrator simply because it keeps a running sum of input charge packets over time. This statement can be formalized as follows: Let us define q H [n] as the total charge contained within capacitor C H at sample time n. Therefore, q H [n] = q H [n − 1] + qin [n]

(8.10)

The transfer function in the z-domain is Q H (z) 1 = Q in (z) 1 − z −1

(8.11)

which is a transfer function of an ideal discrete-time integrator. A lossy discrete-time integrator can be created by adding a second, smaller capacitor C R to the circuit, as shown in Fig. 8.4.2 During ϕ2 , C R is connected to ground, thus resetting the charge contained within it to zero. During ϕ1 , C R is connected to C H , and charge sharing occurs in order to obtain voltage equilibrium between the two capacitors. The charge contained within C H after equilibrium is q H [n] = αq H [n − 1] + qin [n]

(8.12)

or equivalently, it can be expressed in the z-domain as Q H (z) 1 = Q in (z) 1 − αz −1

(8.13)

where α = C H /(C H + C R ), a value that is always smaller than unity. By connecting the two capacitors, a part of the charge that originally resided in C H is now transferred to C R , creating a loss factor in an otherwise lossless integrator. Since C R is 2 For

brevity, the LO switch is omitted in this and all subsequent figures.

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FILTER SYNTHESIS

LO

1

Iout (t)

VRF t

227

Vout

m

CH

CR

2

LO 1 2 (n-1).TLO

n.TLO

FIGURE 8.4

(n+1).TLO

Lossy discrete-time integrator.

subsequently reset to zero, the charge within C R is forever removed from the system. The parameter α determines the dc gain of the integrator or, similarly, the quality factor of the integrator. This parameter also determines the 3-dB bandwidth of the resulting first-order lowpass filter. In this chapter the term loss factor is used to refer to the α parameter. The output of the lossless and lossy integrators above is typically taken as an output voltage. The output voltage vout [n] is vout [n] =

Q H [n] CH

(8.14)

The overall input–output voltage conversion gain G c for a narrowband input signal at frequency f LO can be calculated as Gc =

G m TLO π 1 1 · · · 2 2 1 − α C H  

   1 

V →Q

conv. gain at dc

H p ( f LO )

DT integrator

gain at dc

(8.15)

Q→V

conversion

Equation (8.15) consists of four terms. The first and last terms are the voltage-tocharge conversion gain at dc and the charge-to-voltage conversion gain, respectively. The second term represents the frequency response of the prefilter p(t). The third term is the gain of the discrete-time integrator at dc or, equivalently, (8.13) evaluated at z = 1. Based on (8.15), an ideal sampling mixer, as shown in Fig. 8.1, would have an infinite conversion gain. However, as we show in Section 8.6, any realizable transconductor would have a finite output resistance, which would limit the achievable conversion gain. Next, a mechanism to cascade two discrete-time integrators is needed in order to build a general IIR filter transfer function. The connection between the output of

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LO

1

2

Iout (t)

VRF t

Vout

m

CH1

CR

3

CH2

LO 1 2 3 (n-1).TLO

FIGURE 8.5

n.TLO

(n+1).TLO

Cascade of two lossy discrete-time integrators.

one integrator to the input of another has to be established without the need for any additional active element, such as a transconductor or an amplifier. This task can be accomplished by using one additional capacitor. In this role, the capacitor actually acts as a vessel in which charge packets can be transported between two different integrators. Figure 8.5 shows a cascade of two lossy integrators. The two capacitors C H 1 and C H 2 act as the first and second integrator, respectively; while a third, usually much smaller capacitor C R is used to link the two integrators. In the first phase, ϕ1 , a discharged capacitor C R is connected to capacitor C H 1 . This process makes the first integrator lossy, with a loss factor of α1 = C H 1 /(C H 1 + C R ). The amount of charge stored in capacitor C R at the end of ϕ1 is proportional to the output of the first integrator q H 1 [n]: q R [n] = βq H 1 [n]

(8.16)

where β=

CR =1−α CH1 + CR

(8.17)

In the next phase, ϕ2 , capacitor C R is connected to the second integrating capacitor C H 2 . At this point it might be helpful to (conceptually) make the distinction between the capacitor C R as an empty charge-carrying vessel, and the charge packet q R [n] contained within it. As a discharged capacitor, C R would make the second integrator lossy, with a loss factor of α2 = C H 2 /(C H 2 + C R ). However, capacitor C R contains an input charge packet q R [n], whose value is proportional to the output of the first integrator. Thus, in the latter role, capacitor C R acts to relay the output of the first

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FILTER SYNTHESIS qin[n]

qH1[n]

1 1

qR [n]

1 1z

FIGURE 8.6

qH2 [n]

1 1

229

1 2z

Signal-flow-graph diagram of a cascade of two integrators.

integrator to the input of the second integrator. The factor β indicates the gain between the two integrator stages. The term interstage gain will be used subsequently to refer to this parameter. In the next phase, ϕ3 , capacitor C R is reset, and the sequence repeats from the first phase, ϕ1 . If a third integrator is to be cascaded, capacitor C R can be connected to a fourth capacitor, C H 3 , instead. Thus, a general mechanism of cascading multiple lossy integrators is realized. The resulting signal-flow-graph diagram for the two cascaded integrators is shown in Fig. 8.6. The overall input–output voltage conversion gain G c for a narrowband input signal at frequency f LO can be calculated as Gc =

G m TLO π 1 1 1 · · β · 2

2 1 − α1 1 − α2 C H 2   

 



V →Q

conv. gain at dc

H p ( f LO )

discrete-time filter gain at dc

(8.18)

Q→V

conversion

The method outlined above is by no means limited to an integrator with one input and one output. Multiple capacitors, each of which has a role similar to that of C R , can be used to carry a plurality of input and output charge packets to and from a single integrating capacitor. Furthermore, the interstage gain β can also be negated simply by flipping the polarity of the capacitor C R . This can easily be accomplished using cross-connected switches in a differential implementation. At this point the major limitation of this passive filtering approach should become apparent. Propagation of signal in the filter is accomplished by physically moving charge from one integrator to the next. In other words, each integrator in the filter loses a fraction of its total charge on each sampling period, thus making it a lossy integrator (α < 1). In fact, as shown in (8.17), the sum of the loss factor α and the interstage gain β of each integrator within the filter has to be equal to unity. This fact is a direct result of the charge conservation principle. The charge lost on each integrator acts as input to the next integrator. For this reason, there is an inherent trade-off between the interstage gain between integrators and the quality factor of each integrator. To keep the integrator loss to a minimum, which is desired in many cases, the interstage gain has to be kept very small. The trade-off between the loss factor and the interstage gain does not become much of a problem if the IIR filter can be expressed as a feedforward connection of integrators. The limitation would simply manifest itself as a limitation on the passband gain of the filter, which can be compensated for elsewhere. However, this trade-off poses a severe problem for other IIR filter structures, such as resonators, that inherently require feedback connections. In this case the trade-off between having a

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low-loss integrator and a high interstage gain greatly limits the possible placement of poles and zeros, thereby significantly limiting the range of transfer functions that can be synthesized. For example, resonators with a reasonably high Q-factor cannot be created using this passive switched capacitor approach.3 For this reason, an IIR filter using passive circuits is best suited for lowpass filtering, where the natural frequency response of an integrator can be used without much modification. 8.4.2

FIR Filter Synthesis

An FIR filter is constructed by adding delayed and scaled versions of the filter input samples. This process is amenable to implementation in integrated circuits [7,22,25]. To begin with, a capacitor is a perfect delay element, as it would retain the charge stored within it as long as various leakage mechanisms are kept to a minimum. Furthermore, scaling of the various delayed input samples can easily be accomplished by proportional sizing of each capacitor. The output of the filter is formed by properly connecting a set of capacitors, each of which contains a delayed and scaled version of the input samples. Construction of an FIR filter using capacitors and MOS switches is best described by way of an example. Consider the circuit in Fig. 8.7, which shows a four-tap FIR filter. Therefore, there are four capacitors of different sizes on each bank, and there are four identical banks. The number in parentheses with each capacitor indicates to which capacitor bank it belongs. Each capacitor bank is used sequentially from first to last on successive sampling instants. When all capacitor banks have been used, the sequence is repeated from the beginning. In general, for a length-N FIR filter, N identical capacitor banks of N capacitors each are needed. On each sampling instant the input charge packet qin [n] is distributed over all capacitors within the capacitor bank (n|4), where the operator “|” indicates a modulo

0

VRF t

1

m

2 3

1(0)

2(0) 1(0) 1(0)

3(0) 2(0)

2(0) 1(0)

FIGURE 8.7

2(0) 2(0)

3(1) 2(0)

2(0)

3(2) 2(0)

3(3)

Input sampling for a four-tap FIR filter.

3 A resonator Q-factor is defined as the ratio of the resonator’s center frequency to its bandwidth. Multi-rate

techniques can also be utilized to synthesize a bandpass filter consisting of two time-interleaved lowpass filters [15,26,28].

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231

operation. Each capacitor in the capacitor bank stores a fraction of the input charge packet; this fraction is proportional to the size of the capacitor relative to the total capacitance in the capacitor bank. Thus, for an N -tap FIR filter, N different scaled input samples are created at once. Each of these scaled input samples is then used to form the next N output samples. The output of the FIR filter is formed by appropriately connecting together one capacitor from each capacitor bank. For example, to form the nth output in the fourtap FIR filter example, one would connect capacitors C0(n|4) , C1((n−1)|4) , C2((n−2)|4) , and C3((n−3)|4) . Capacitor bank (n|4), with its constituent capacitors, stores this period input sample; capacitor bank ((n − 1)|4) stores the last input sample; and so on. Therefore, upon forming the output, we have qout [n] =

C0 qin [n] + C1 qin [n − 1] + C2 qin [n − 2] + C3 qin [n − 3] C0 + C1 + C2 + C3

(8.19)

where qout [n] is stored within a composite capacitor of size Ctot = C0 + C1 + C2 + C3 . Through this process, a four-tap FIR filter with coefficients {C0 /Ctot , C1 /Ctot , C2 /Ctot , C3 /Ctot } is created. After the output is formed, each capacitor is reset to ground (not shown in Fig. 8.7) to prepare it for sampling subsequent input samples. 8.4.3

Sample-Rate Down-Conversion

Sampling-rate down-conversion, or simply down-sampling, is often needed in a switched-capacitor filter circuit. For example, the sampling rate of a switchedcapacitor band-select filter in an RF receiver needs to be sufficiently high to avoid excessive aliasing. However, the resulting sampling rate might be too high for efficient A/D conversion. If the sampling rate can be reduced, an ADC with a lower sampling rate, therefore a lower power consumption, can be used instead. A switched-capacitor FIR filter, such as one described in Section 8.4.2, lends itself naturally to be used as a down-sampling circuit for two reasons [24]. First, an FIR filter is an all-zero filter, which makes it an ideal antialiasing filter. The zeros of the FIR filter can be placed strategically at frequencies where potential interferers can alias and overlap with the desired signal. Second, the actual down-sampling operation can be realized by forming only every Mth output sample. Therefore, only a single capacitor in each filter bank, instead of M, is needed in the FIR filter circuit. A popular FIR filter of choice for antialiasing is an M-tap FIR filter with equal tap weights [2,12]. This FIR filter has zeros at all multiples of f s /M, where f s is the sampling rate. If the desired signal occupies a small bandwidth around dc, it would be protected from all signals that can potentially overlap with it due to the down-sampling-by-M operation. This sample-rate conversion block, consisting of a combination of an FIR filter and a down-sampler, can be embedded inside more complicated filter topologies. Figure 8.8 shows a two-tap FIR filter with a down-sample-by-2 circuit inserted between two discrete-time integrators. In this example the two capacitors C R1 and

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2

LO

VRF (t)

CH2

Gm 1A

1B

CH1 CR1

3

3

CR2

LO 1A 1B 2 3

(n-1).TLO

qin[n]

n.TLO

1 1–

–1 1z

FIGURE 8.8

2-tap FIR

(n+1).TLO

↓2

qH2[n]

1 1–

2z

–1

Decimation filter inside a cascade in an IIR filter.

C R2 have equal capacitances of size C R . These two capacitors sample the output of the first integrator, C H 1 , in a time-interleaved manner, as apparent in the timing diagram. On ϕ2 , which occurs only on every other sampling period, capacitors C R1 and C R2 are connected simultaneously to capacitor C H 2 . By connecting capacitors C R1 and C R2 together, a two-tap FIR filter with coefficients {1, 1} is formed. Moreover, since this operation is done only on every other sampling period, a down-sampleby-2 operation is also realized. The first integrator, consisting of capacitor C H 1 , is sampled at the original rate, with α1 = C H 1 /(C H 1 + C R ) and β = C R /(C H 1 + C R ). The second integrator, consisting of capacitor C H 2 , is run at the lower sampling rate, with α2 = C H 2 /(C H 2 + 2C R ). The factor 2C R appears at the denominator to take into account the fact that the second integrator takes its input from two capacitors, C R1 and C R2 . Figure 8.9 is another example of a sample-rate conversion block embedded within an IIR filter. Unlike the previous example, where the output of the first integrator is sampled in a time-interleaved manner, in this example the output is sampled once every two sampling periods. As a result, the first integrator in this example is run at the lower sampling rate. The rest of the filter circuit is identical to the one shown in Fig. 8.5. Figure 8.10 shows a circuit that uses a combination of the techniques described so far. This example is adapted from a filter within a commercial GSM receiver

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FILTER SYNTHESIS

LO VRF (t)

1

2

Vout

Gm CH1

CR

CH2

3

LO 1 2 3 (n-1).TLO

qin [n]

n.TLO

1

↓2

2-tap FIR

FIGURE 8.9

(n+1).TLO

1–

2z

–1

Decimation filter before a cascade in an IIR filter.

2

LO

VRF (t)

qH2[n]

1

–1 1z

1–

3

4

Vout

Gm 1A

1B

CH1

CH2 CR1

3

CR3

CH3

2

3

CR2

LO/2 1A

1B

2

3

4

(n-1).2TLO qin[n]

1+z -1

↓2

1 1–

1z

–1

1

n.2TLO

1+z -1

(n+1).2TLO

↓2

2z

qH3[n]

1

1 1–

–1

2

1–

3z

–1

FIGURE 8.10 Complex switched-capacitor filter adapted from a commercial GSM receiver [11].

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Normalized Frequency Response (dB20)

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Hp (Ω) Int1 Int2 Overall

20 0 −20 −40 −60 −80 −100 −120

0

fLO

2fLO

3fLO

Input Frequency

FIGURE 8.11 Frequency response of circuit shown in Fig. 8.10.

[11]; in this example, the timing signals have been simplified, for clarity. This filter consists of three IIR stages and two down-samplers. A discrete-time antialiasing FIR filter, with tap coefficients {1, 1}, precedes each down-sampler. Capacitors C R1 and C R2 are of equal size. The values of each parameter in the signal-flow-graph diagram are as follows: α1 = C H 1 /(C H 1 + C R1 ), α2 = C H 2 /(C H 2 + 2C R1 + C R3 ), α3 = C H 3 /(C H 3 + C R3 ), and β1 = C R1 /(C H 1 + C R1 ), β2 = C R3 /(C H 2 + 2C R1 + C R3 ). The overall frequency response of the circuit is shown by the solid line in Fig. 8.11. The frequency response of the windowing function p(t) is shown using a dashed line. Also shown are two intermediate signal responses, int1 and int2, which correspond to the signals contained within capacitors C H 1 and C H 2 , respectively. Note that the frequency responses are referred to the input signal frequency; in other words, the signal of interest is at frequency f LO . The vertical axis is normalized against the conversion factors between charge and voltage domains: namely, (G m TLO /2)(1/C H 3 ). Because of the down-sample-by-4 operation in the circuit, signals spaced at f LO /4 will overlap each other.

8.5

NOISE IN SWITCHED-CAPACITOR FILTERS

Noise in a passive switched-capacitor filter originates from the thermal noise within each of the constituent MOS switches. The total noise at the filter’s output can be obtained simply by enumerating all the MOS switches in the filter and determining the noise transfer function from each MOS switch to the output [6]. Consider the circuit shown in Fig. 8.12, which consists of one capacitor and one MOS switch. Noise generated in the reset phase of an IIR or FIR filter discussed previously can be modeled with this circuit. When the MOS switch is on, its inversion

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Ron

~ in

FIGURE 8.12

CR

Noise on a single switched capacitor.

channel creates a connection between the top and bottom plates of the capacitor. Ideally, this connection would short the two capacitor plates, therefore depleting all the charge stored within the capacitor C R . However, thermal noise generated within the transistor’s channel prevents this from happening perfectly. Since an MOS switch has a finite conductance, it is also susceptible to thermal energy fluctuation. This effect can be modeled as a noise current source in parallel with the MOS switch, as shown in Fig. 8.12 [23]. Noise generated inside the switch would continuously modulate the voltage across the capacitor C R . At the instant when the switch is opened, the connection between the two plates and the noise source is cut off. The instantaneous noise charge stored within the capacitor remains in the capacitor C R , effectively sampling the noise process i˜n at the exact instant the switch is turned off. To quantify the preceding description, the on-resistance of the MOS, Ron , and the capacitor C R form a lowpass filter. The total integrated noise represented as a voltage across the capacitor C R has a variance of  2
∞   1   df var(v˜o ) = 4kTRon  1 + 2π j f Ron C R  0 =

kT CR

(8.20)

where k is Boltzmann’s constant and T is the temperature. The resulting discrete-time noise process has a flat power spectral density across the frequency (− f s /2, f s /2), where f s is the sampling frequency [8]. The noise voltage v˜o can be represented equivalently as a noise charge packet q˜ R with a variance of kTC R . This noise charge packet is stored within C R and is generated every time that C R is reset. By casting the discrete-time noise process as a charge-packet generation mechanism, the noise source can easily be incorporated into the analysis framework developed so far. The same noise analysis can also be extended easily to cases where an MOS connects two capacitors, as shown in Fig. 8.13. When the MOS switch is turned on, it completes a loop that contains the two capacitors C H and C R in series. Therefore, the MOS switch is effectively connected to an equivalent series capacitor of size C H ||C R = C H C R /(C H + C R ). The noise voltage across this equivalent series capacitor has a variance of kT /(C H ||C R ). Thus, each capacitor C H and C R contains an identical noise charge packet of variance kT (C H ||C R ), with the polarity shown in Fig. 8.13.

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+

-

CH

+

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q~H

q~R

+ -

CR

q~R -

CR

+ q~H -

CH

FIGURE 8.13 Noise on two switched capacitors.

It turns out that noise analysis of these two seemingly simple circuits is sufficient to analyze and explain noise generation and propagation in more complicated switchedcapacitor circuits. To illustrate this point, we analyze an example circuit of a secondorder lowpass filter, shown in Fig. 8.5. Recall that this filter is a cascade of two lossy integrators, the first composed of capacitor C H 1 and the second composed of capacitor C H 2 . A discrete-time signal flow graph diagram has been developed and is shown in Fig. 8.6; the intention here is to incorporate the various noise sources into the diagram. There are three MOS switches in the IIR filter circuit, and therefore three independent noise sources need to be accounted for. The first noise source comes from the ϕ3 switch. This switch would generate a noise charge packet of variance kT C R , which is then stored within capacitor C R . Because the capacitor C R is subsequently connected to capacitor C H 1 , the noise charge packet generated during the ϕ3 will act as an input charge packet to the first discrete-time integrator. Second, during the ϕ2 phase, two noise charge packets of variance kT (C R ||C H 2 ) are generated and stored in C H 2 and C R . The first noise charge packet, stored in C H 2 , can easily be modeled as an input to the second integrator. The noise charge packet in C R generated during ϕ2 is immaterial, because in the next phase, ϕ3 , the capacitor C R is reset. The last noise source is generated during the ϕ1 phase. As in the ϕ2 phase, two noise charge packets of variance kT (C R ||C H 1 ) are created and stored within capacitors C H 1 and C R . The noise charge packet stored within C H 1 can also be considered as an input to the first integrator. The noise charge packet in C R will act as an input to the second integrator, since in the next phase, ϕ2 , capacitor C R is connected to capacitor C H 2 . It is very important to realize that the last two noise charge packets are a manifestation of the same noise process, one that originated from the thermal energy fluctuation within switch ϕ1 . For this reason, the noise source generated during ϕ1 is represented most appropriately by a single noise source that is injected at two different locations in the signal flow graph diagram. The polarity with which the noise source is injected is also of importance, as the incorrect polarity would alter the noise transfer function to the output. The updated signal flow graph diagram, with the noise sources included, is shown in Fig. 8.14(b). Simulation of switched-capacitor noise can be performed using a combination of periodic steady-state (PSS) and periodic noise (PNOISE) analysis, which is available as part of Cadence SpectreRF circuit-simulation suite [17]. Periodic steady-state analysis is originally intended to analyze a continuous-time circuit with periodic input signals or excitations. To simulate a switched-capacitor circuit appropriately,

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237

2

Vout CH1

CR

CH2

3

(a) kTCR

kT(CH2||CR )

qin[n]

1 1

qH1[n]

qR[n]

1 1z

1 1

qH2[n]

1 2z

kT(CH1||CR )

(b)

FIGURE 8.14 diagram.

Noise in a second-order IIR filter: (a) circuit schematic; (b) signal flow graph

one needs to recognize that the output of a switched capacitor circuit is a discrete-time rather than a continuous-time signal. This discrete-time signal should be treated as the output of the circuit sampled after it has settled to the final value for each sampling period. There are two techniques that one can use to force the simulator to evaluate the output signal correctly in the manner described [8]. First, in more recent versions of SpectreRF, PNOISE analysis provides a specialized time-domain analysis method that can be invoked by setting a simulation option noisetype=timedomain. By enabling this option, the simulator would analyze noise only at particular time instants parameterized by another simulation variable, noisetimepoints. Second, on older versions of spectreRF, an explicit (ideal) sample-and-hold block can be used similarly to force the simulator to evaluate only the output of the circuit at the correct time instants. Recall that a sample-and-hold would impose a zero-order hold on a discrete-time signal; thus, the resulting sinc-shaped response in the frequency domain has to be compensated for.

8.6

CIRCUIT-DESIGN CONSIDERATIONS

The design of the input transconductor circuit (G m ) has a large impact on the overall performance of a discrete-time filter. In this section we focus on modeling the various nonidealities of the input transconductor and analyzing their impact on the overall filter transfer function. The emphasis of the discussion is on a transconductor driving

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LO VRF(t)

Vout

Gm Rpar

CH

Cpar

FIGURE 8.15 Input transconductor with finite output resistance and nonzero output capacitance.

an IIR filter, noting that transconductor design for an FIR filter is a subset of what is discussed in this section. As in previous sections, the goal is to incorporate the various circuit impairments to the analytical framework that has been developed so far. The ideal transconductor would have zero output capacitance, denoted Cpar , and an infinite output resistance, denoted Rpar . The effect of a nonzero output capacitance (Fig. 8.15) can be incorporated easily into the analysis framework developed in Section 8.4.1. On each sampling instant, charge sharing will occur between capacitor Cpar and capacitor C H . Therefore, the integrator formed by capacitor C H will become lossy, with a loss factor of αC = Cpar /(Cpar + C H ). The presence of a finite transconductor output resistance, Rpar , can be analyzed by starting with the differential equation that describes the circuit: G m Vin (t) =

q H (t) dq H (t) + C H Rpar dt

(8.21)

Solving the differential equation above and sampling the resulting function at the correct time instants would result in the following equation:


TLO q H [n] = exp − 2Rpar C H q H [n − 1] + G m



nTLO +TLO /2

VRF (τ )exp

nTLO

nTLO +(TLO /2)−τ Rpar C H

 dτ

(8.22)

or, equivalently, q H [n] = α R q H [n − 1] + qin [n]

(8.23)

α R = e−TLO /2Rpar C H

(8.24)

where


qin [n] = G m



nTLO +TLO /2

VRF (τ )exp nTLO

nTLO +(TLO /2)−τ Rpar C H

 dτ

(8.25)

The variable α R is equivalent to the loss factor α, which is defined in Section 8.4.1. It is simply a mathematical formulation to describe the amount of charge lost per sampling period. During the period when LO is high, current will flow through resistor

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239

Rpar , which will slowly deplete the charge stored within capacitor C H . Therefore, for each sampling period, a part of the charge inside capacitor C H is lost. The loss factor, α R , can be combined with other loss mechanisms, such as one due to connecting and disconnecting a second capacitor, C R (Fig. 8.4), to result in an effective loss factor αeff . The effective loss factor αeff can be computed by enumerating the total charge lost per period as a fraction of the total charge within capacitor C H . The generation of charge packet qin [n] in this scenario can be formulated similarly as a convolution or a filtering operation between the continuous-time input signal with a windowing function [equation (8.9)]. In this case the windowing function is  ppar (t) =

2 −t/Rpar C H e , TLO

0,

if 0 ≤ t ≤ TLO /2 otherwise

(8.26)

The presence of a finite output resistance Rpar modifies the antialiasing filter p(t) to be the function ppar (t). Note that as Rpar approaches infinity, the function ppar (t) degenerates into the original antialiasing filter function p(t). A comparison between the frequency response of the original prefilter p(t) and the resulting prefilter ppar (t) with a finite transconductor output resistance, Rpar , is shown in Fig. 8.16. With the addition of the effect of finite transconductor output resistance, the voltage conversion-gain formula from (8.15) can be updated as follows: Gc =

1 G m TLO 1 H ppar ( f LO ) 2 1 − αR C H

0

(8.27)

Finite Rpar Infinite Rpar

−5 −10

Hppar (Ω) (dB20)

c08

−15 −20 −25 −30 −35 −40 −45 −50

0

fLO

2fLO

3fLO

4fLO

5fLO

6fLO

Frequency

FIGURE 8.16 Impact of transconductor finite output resistance.

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When Rpar is sufficiently large, TLO /2Rpar C H is much smaller than unity. If such is the case, the following approximation can be used: 2Rpar C H 1 1 = ≈ −T /2R C LO par H 1 − αR 1−e TLO

(8.28)

Therefore, the conversion gain from (8.27) can be approximated as Gc ≈

G m TLO 2 2Rpar C H 1 2 = G m Rpar 2 π TLO C H π

(8.29)

This result is hardly surprising; it is identical to the conversion gain of a mixer. It is important to realize that, in reality, the resistance Rpar is not a physical resistance; it is merely a small-signal approximation. As such, the resistance value is susceptible to process, voltage, and temperature variation. More important, the value of this resistance is signal dependent, which causes distortion. For this reason, although it is able to, Rpar is rarely used as a parameter that sets the important filter parameters, such as bandwidth and gain. A filter circuit with a lossy integrator (Fig. 8.4) is more widely used. The transconductor can be designed such that the effective loss factor αeff ≈ C H /(C H + C R ), which necessitates Rpar C H  TLO /2. In this manner, the critical filter parameters, such as in-band gain and bandwidth, are determined entirely by the ratio of capacitances rather than by the value of Rpar . The disadvantage of such an approach is that the conversion gain of the circuit will be reduced significantly. The load of the transconductor circuit consists of an MOS sampling switch and a switched-capacitor filter. This load circuit is actually a discrete-time system. As such, its frequency response is periodic in the continuous-frequency axis, with a period equal to the sampling frequency f LO . This fact is illustrated in Fig. 8.17. The overall frequency response of the circuit is a result of a prefiltering operation with a windowing function p(t), followed by a discrete-time lowpass filter with a sampling frequency of f LO . A beneficial consequence of the foregoing concept is the fact that the lowpass filtering in the load circuit can be transformed back as bandpass filtering at the output of the transconductor [5]. If the voltage drop across the sampling switch is kept small, the output voltage of the transconductor is set by the voltage across the capacitor C H . However, the voltage across capacitor C H emerges only after the discrete-time filtering operation. Thus, if a large out-of-band blocker were to impinge on the transconductor, it would be filtered before it could cause a large voltage swing at the output of the transconductor. Finite rise and fall times of the LO signal would also affect the frequency response of the antialiasing prefilter p(t). This impairment can be modeled by modifying the impulse response p(t) to be trapezoidal in shape instead of a perfect rectangle. The overall impact is similar to that of a finite output impedance, in that it limits the rejection at even multiples of LO frequency.

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20

Normalized Frequency Response (dB20)

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Window function p(t) Discrete-time integrator Composite

10 0 −10 −20 −30 −40 −50 −60 −70 −80

fLO

0

2fLO

3fLO

4fLO

5fLO

6fLO

Frequency

FIGURE 8.17 Frequency response of a passive mixer.

One possible implementation of the input transconductor in differential form is shown in Fig. 8.18. The transconductor is built in a pseudodifferential configuration. The high output impedance is achieved by using a combination of a cascoded transistor Mcp(n) and a long p-channel current source M pp(n) . The common-gate transistor Mcp(n) also provides isolation from the input and output nodes of the transconductor, to avoid possible self-mixing issues. Furthermore, the common-gate transistor provides a low-impedance input for the output current of transistor Min p(n) , and by doing so it would act to minimize the drain-to-source voltage variation within transistor Min p(n) .

Mpp

Mpn Vbp

Von

Vop

Vcascode Mcp

Vinp

FIGURE 8.18

Mcn

Minp

Minn

Vinn

Pseudo-differential cascoded transconductor.

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PERSPECTIVE AND OUTLOOK

From the discussion in this chapter, we can draw several conclusions regarding the use of passive switched-capacitor filters in RF receivers. The advantages are: r The operating frequency limitation of a passive switched-capacitor filter is set by the dimensions of the MOS switch. Continuous scaling of CMOS technology has significantly benefited the performance of MOS switches. r Corner frequencies of the filter are set through ratios of capacitors, which are very well controlled and easily programmable in a CMOS process. r The most power-hungry element in a sampled-data system, the sample-and-hold circuit, is readily available in an RF receiver in the form of a mixer. r Lowpass filtering at baseband is transformed into bandpass filtering at the output node of the transconductor. r Any FIR filter along with a sizable collection of IIR filters can be implemented using this passive filtering approach. The disadvantages are: r The general multi-stage/high-order discrete-time filter has limited voltage gain. Voltage gain can only be obtained when the input signal is sampled at the first capacitor. Subsequent filtering stages result in no extra gain. r Trade-off between interstage gain and the loss factor in integrators limits the type of IIR filters that can be built. An FIR filter is generally more suitable for creating a notch filter since it can do so simply by inserting zeros in the transfer function. For this reason, an FIR filter built using this technique is particularly suitable for use as an anti-aliasing filter prior to a sample-rate down-conversion. There are no general restrictions on the type of FIR transfer function that can be realized using this technique. Nevertheless, FIR filter generally needs a large number of taps to obtain sufficient rejection over a wide range of frequencies. An FIR filter with a large number of taps can be quite cumbersome to implement in integrated circuits. The FIR filter coefficients might have a very large greatest common divisor, which makes exact capacitor sizing impractical. For an FIR filter with a large number of taps, acceptable matching among all the capacitors might also be difficult to achieve. On the other hand, an IIR filter with a single strategically located pole can be quite effective in attenuating blockers over a wide frequency range. For this reason an IIR filter is more appropriate for a general filtering application. But as mentioned previously, the passive nature of this filter imposes a limitation on the possible placement of poles in an IIR filter. In the end, one still needs to be judicious about when to use passive switchedcapacitor technique and when not to. When used as a filter in an RF receiver, this technique can still yield significant benefits, especially if the mixer is used as a

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PERSPECTIVE AND OUTLOOK 1

FB2

LO

DI

m

1

CH1

2

CR

FB1

CH2

DI

4

DI

CH1

CR

CH2 3

LO

FIGURE 8.19

1

2

Second-order  modulator with passive switched-capacitor filter.

sampler, as illustrated previously. A first- or second-order IIR filter with a tightly controlled corner frequency is often sufficient to attenuate most of the blockers in a typical scenario. A down-sampler with an FIR antialiasing filter can be inserted between the IIR filter and an analog-to-digital converter [2,12]. One should also realize that this technique does not solve the fact that the RF signal still needs to be amplified at some point in the receiver path. Considering that the signal at the antenna is at the tens or hundreds of microvolts level, and that a typical ADC might need signal in the 1-V range; a total gain of 60 dB or even more is still needed. The presence of a filter only eases the design of the amplifier to the extent that the filter can attenuate much of the out-of-band blockers, and therefore eases the linearity requirement of the amplifier. With such a low input signal level, the input-referred noise of the succeeding amplifier must be kept very low, which would result in a large power consumption. One potential solution to this problem is to enclose a passive, switched-capacitor filter inside a  modulator loop [3,28]. The input signal will be sampled at the mixer, and the discrete-time filter will be run at the LO rate. A 1-bit comparator evaluates the output of the filter, and the result is used to drive 1-bit feedback digitalto-analog converters (DACs). There is no explicit amplification element within the system. However, in reality the 1-bit comparator actually acts as an amplifier, as it tries to resolve the polarity of a very small input signal and produce a full CMOSlevel output. In this manner, a comparator is actually a very power- and area-efficient amplifier; since there really are no linearity or stability constraints. Regenerative or positive feedback concepts can be used to achieve a large amount of gain with very little power dissipated. Finally, variable gain control can be implemented by making the reference line of the feedback DACs be programmable. An embodiment of the concept discussed in the preceding paragraph is shown in Fig. 8.19. In this circuit, a second-order passive switched-capacitor  modulator converts the signal at the output of the mixer to produce a single-bit output. The modulator is run at the RF frequency, which gives rise to a large oversampling ratio. As a result, even with a single-bit comparator, the modulator could produce a large dynamic range for overall signal conversion.

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REFERENCES 1. A. Abidi, “Evolution of a software-defined radio receiver’s RF front-end,” in IEEE Radio Frequency Symposium, pp. 17–20, 2006. 2. R. Bagheri, A. Mirzaei, A. Chehrazi, M. Heidari, M. Lee, M. Mikhemar, W. Tang, and A. Abidi, “An 800-MHz-6-GHz software-defined wireless receiver in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2860–2876, Dec. 2006. 3. F. Chen and B. Leung, “A 0.25-mW low-pass passive sigma-delta modulator with built-in mixer for a 10-MHz IF input,” IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 774–782, June 1997. 4. Y. Chiu, B. Nikolic, and P. Gray, “Scaling of analog-to-digital converters into ultra-deepsubmicron CMOS,” in IEEE Custom Integrated Circuits Conference, pp. 375–382, 2005. 5. B. Cook, A. Berny, A. Molnar, S. Lanzisera, and K. S. Pister, “Low-power 2.4-GHz transceiver with passive RX front-end and 400-mV supply,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2757–2766, Dec. 2006. 6. J. Fischer, “Noise sources and calculation techniques for switched capacitor filters,” IEEE J. Solid-State Circuits, vol. 17, no. 4, pp. 742–752, Aug. 1982. 7. N. Guilar, P. Lau, S. Lewis, and P. Hurst, “A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topology,” in IEEE Custom Integrated Circuits Conference, pp. 633–636, 2005. 8. K. Kundert, “Simulating Switched-Capacitor Filters with SpectreRF. The Designer’s Guide Community, July 2006. 9. C. F. Kurth and G. S. Moschytz, “Nodal analysis of switched-capacitor networks,” IEEE Trans. Circuits Syst., vol. 26, no. 2, pp. 93–105, Feb. 1979. 10. H. Lakdawala, J. Zhan, A. Ravi, S. Anderson, B. Carlton, R. Nicholls, N. Yaghini, R. Bishop, S. Taylor, and K. Soumyanath, “Multi-band (1–6GHz), sampled, sliding-IF receiver with discrete-time filtering in 90nm digital CMOS process,” in Digest of Technical Papers, 2006 Symposium on VLSI Circuits, pp. 230–231, 2006. 11. K. Muhammad, Y.-C. Ho, Jr., T. L. Mayhugh, C.-M. Hung, T. Jung, I. Elahi, C. Lin, I. Deng, C. Fernando, J. L. Wallberg, S. K. Vemulapalli, S. Larson, T. Murphy, D. Leipold, P. Cruise, J. Jaehnig, M.-C. Lee, R. B. Staszewski, R. Staszewski, and K. Maggio, “The first fully integrated quad-band GSM/GPRS receiver in a 90-nm digital CMOS process,” IEEE J. Solid-State Circuits, vol. 41, pp. 1772–1783, Aug. 2006. 12. K. Muhammad, D. Leipold, and R. B. Staszewski, “A discrete-time Bluetooth receiver in a 0.13µm digital CMOS process,” in Digest of Technical Papers, 2004 IEEE International Solid-State Circuits, vol. 47, 2004. 13. K. Muhammad and R. B. Staszewski, “Direct RF sampling mixer with recursive filtering in charge domain,” in Proc. International Symposium on Circuits and Systems, pp. 577–580, 2004. 14. K. Muhammad, R. B. Staszewski, and D. Leipold, “Digital RF processing: toward low-cost reconfigurable radios,” IEEE Commun. Mag., pp. 105–113, Aug. 2005. 15. A. Ong and B. Wooley, “A two-path bandpass  modulators for digital IF extraction at 20 MHz,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1920–1934, Dec. 1997. 16. T. Sano, T. Maruyama, I. Yasui, H. Sato, and T Shimizu, “A 1.8 mm2 , 11 mA, 23.2 dBNF, discrete-time filter for GSM/WCDMA/WLAN using retiming technique,” in IEEE Custom Integrated Circuits Conference, 2007.

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17. Virtuoso Spectrerf Simulation Option User Guide. Cadence Design Systems, Nov. 2005. 18. G. C. Temes and Y. Tsividis, “The special section on switched-capacitor circuits,” Proc. IEEE, vol. 71, no. 8, pp. 915–916, 1983. 19. Y. Tsividis, “Analysis of switched capacitive networks,” IEEE Trans. Circuits Syst., vol. 26, no. 11, pp. 935–947, 1979. 20. Y. Tsividis, “Principles of operation and analysis of switched-capacitor circuits,” Proc. IEEE, vol. 71, no. 8, pp. 926–940, 1983. 21. Y. Tsividis, Operation and Modelling of the MOS Transistor. New York: McGraw-Hill, 2003. 22. G. Uehara and P. Gray, “A 100 MHz A/D Interface for PRML magnetic disc read channels,” IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1606–1613, Dec. 1994. 23. A. van der Ziel, “Thermal noise in field-effect transistors,” Proc. IRE, vol. 50, no. 8, pp. 1808–1812, 1962. 24. D. von Grunigen, U. Brugger, and G. Moschytz, “Simple switched-capacitor decimation circuit,” Electron. Lett., vol. 17, pp. 30–31, 1981. 25. D. von Grunigen, U. W. Brugger, G. S. Moschytz, and W. Vollenweider, “Combined switched-capacitor FIR n-path filter using only grounded capacitors,” Electron. Lett., vol. 17, pp. 788–790, 1981. 26. D. von Grunigen, G. Moschytz, H. Melchior, R. Sigg, and J. Schmid, “An integrated CMOS switched-capacitor bandpass filter based on N -path and frequency-sampling principles,” IEEE J. Solid-State Circuits, vol. 18, no. 6, pp. 753–761, Dec. 1983. 27. G. Wegmann, E. Vittoz, and F. Rahali, “Charge injection in analog MOS switches,” IEEE J. Solid-State Circuits, vol. 22, no. 6, pp. 1091–1097, Dec. 1987. 28. R. Winoto, “A radio-frequency bandpass  A/D converter,” Master’s thesis, UC Berkeley, May 2006. 29. A. Yoshizawa and S. Iida, “An equalized ultra-wideband channel-select filter with a discrete-time charge-domain band-pass IIR filter,” in IEEE Custom Integrated Circuits Conference, 2007. 30. J. Yuan, “A charge sampling mixer with embedded filter function for wireless applications,” In Proc. 2nd International Conference on Microwave and Millimeter Wave Technology, pp. 315–318, Beijing, 2000.

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Oversampled ADC Using VCO-Based Quantizers MATTHEW Z. STRAAYER and MICHAEL H. PERROTT Massachusetts Institute of Technology, Cambridge, Massachusetts

9.1

INTRODUCTION

High-bandwidth and high-resolution analog-to-digital converter (ADC) implementations face many challenges for circuit designers using nanometer-scale CMOS processes, yet the demand for ADC performance is unrelenting. For reconfigurable wireless receivers, continuous-time
 ADCs offer excellent out-of-band rejection and can simply be configured to trade dynamic range with input bandwidth. However, with limited power supplies and decreasing gain for minimum-size transistors, achieving a large dynamic range for high-speed converters is difficult for classical architectures that rely on precision operational amplifiers and comparators. At the same time, advanced CMOS processes offer very fast switching speed and high transistor density that can be utilized in interesting and unconventional ways. Voltage-controlled oscillator (VCO)–based quantization carries the very attractive aspect of having a highly digital implementation, and as a result, these structures take full advantage of Moore’s law and the enormous industrial investment in digital process development. Reducing the digital gate delay improves both the resolution of the VCO-based quantizer and the achievable sample rate; a 9-dB improvement in signal-to-quantization noise results from a 50% reduction in gate delay. As such, there has been an increasing level of interest in using VCO-based quantization to achieve analog-to-digital conversion in modern mixed-signal circuits [1–5]. However, one challenge for VCO-based quantizers is to mitigate the poor linearity, which can severely limit ADC performance. To address such issues from an architectural perspective, in this chapter we explore the use of a multi-phase VCO as a quantizer element in oversampling continuous-time ADC.

Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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VCO-QUANTIZER BACKGROUND

While VCO-based ADCs have recently become a topic of great interest in the mixedsignal community due to their “digital” structure, which benefits from technology scaling, the architecture has several unique and attractive properties that have been widely known for quite some time. Figure 9.1 depicts the VCO as an element that transposes an analog input voltage into an output signal with binary levels that can be interpreted as either frequency or phase. To explain, we first notice that the instantaneous VCO output frequency is directly proportional to the voltage applied to its tuning node. An example of the VCO voltage-to-frequency transfer characteristic shown on the right side of Fig. 9.1 defines the slope of the curve, K v (Hz/V), as smallsignal voltage-to-frequency gain. Second, we see that the VCO effectively behaves as a continuous-time voltage-to-phase integrator. Since the output phase of an oscillating VCO accumulates without end, the VCO voltage-to-phase integration is then ideal in the sense that there is infinite dc gain. Finally, while the phase of the VCO output signal changes continuously, its voltage output toggles between two discrete output levels: high voltage and low voltage. Consequently, the VCO can drive other digital blocks seamlessly with little additional signal conditioning or amplification. One of the earliest reported VCO-based ADCs was proposed more than 30 years ago for use in a digitally controlled switching regulator [6], and a similar topology was applied in the superconductivity community five years later [7]. While the exact implementation of the converters differed due to the choice of technology (i.e., semiconductor vs. superconductor), the overall architecture for each was essentially the same and is shown in Fig. 9.2. Here, the ADC comprises a single-phase output VCO, a counter, and a sampling register. As the analog input signal modulates the VCO frequency via the tuning node, the counter accumulates the number of transitioning edges continuously during the sampling period. At the end of the period, the resulting count is sampled by a register, the counter reset to zero, and the process repeated. As can be seen from the figure, the sampled count is proportional to the oscillation frequency of the VCO, and therefore of the input signal level. One very interesting aspect of VCO-based quantizers is their potential ability to achieve first-order noise shaping of their quantization noise [8]. Figure 9.3 illustrates this principle in simplified form by examining the counting process of one phase of the oscillator with a constant Vtune input. The key point here is that the truncation

F

VCO Fout(t)

Vtune(t)

Φout(t) Fout(t) = Kv.Vtune(t) t

Φout(t) =

FIGURE 9.1

2π.Kv.Vtune(τ).dτ 0

Kv

Fout

Vtune

V

dFout Kv = dVtune

VCO voltage-to-frequency and voltage-to-phase relationships.

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VCO-QUANTIZER BACKGROUND

FIGURE 9.2

249

Simple VCO-based ADC.

error q[k] at the end of a clock period boundary is not lost but, rather, is accounted for in the following measurement. The accumulation of phase error from sample to sample is then maintained to within a single quantization level, shown in this case by the extra count in the third sample of the sequence [3 3 4 3]. Examination of the quantization error signal, e[k], in the figure reveals that it takes the form e[k] = q[k] − q[k − 1]

(9.1)

where q[k] corresponds to the truncation error that occurs at the edge of each clock period boundary. Under the assumption that q[k] is white in its noise profile, (9.1) reveals that the overall quantization error is first-order noise-shaped. The oscillator-based ADC of Figs. 9.2 and 9.3 can be related to the well-known slope-based converter (single or dual slope) [9] in that both architectures translate an input voltage signal into the time domain, where it is then quantized. However, we make a key distinction that the single-slope ADC effectively compares an input signal

Clock Vtune Oscillator Count

Error

q[0]

q[1] -q[0]

Out

FIGURE 9.3

3

q[2] -q[1]

3

q[3] -q[2]

4

-q[3]

3

First-order noise shaping of a classical VCO-based ADC.

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OVERSAMPLED ADC USING VCO-BASED QUANTIZERS Ring Oscillator

Vtune

Ref Vtune

Reset Counters

Oscillator Phases

Count Clock

Register

Count

Out Out

FIGURE 9.4 phase VCO.

15

30

12

21

Improved resolution by counting positive and negative transitions of a multi-

to an integrating waveform, whereas the VCO-based quantizer actually integrates the input signal in continuous time. As a result, the slope-based ADC lacks noise shaping and is not well suited for oversampling applications. In fact, the linear trade-off between sampling rate and dynamic range limits the slope-based Nyquist converters to high-resolution applications only when a very low input bandwidth is required. Regardless, the many variations on these time-based circuits for ultralowpower sensor applications highlight the efficiency of combining voltage or current integration with digital clocks [10–13]. To improve the raw resolution of the VCO-based quantizer, the VCO needs to generate more edge transitions during the sample period. This can be accomplished by adopting a ring-oscillator structure to generate N multiple VCO output phases, as proposed in [8] and shown in Fig. 9.4. Here, each positive and negative phase output from the ring-VCO drives a counter input, producing a total count with higher resolution by a factor of 2N compared to the single-phase VCO-based ADC of [6,7] for the same period. Although the VCO-based quantizer shown in Fig. 9.4 provides a convenient illustration of the basic principles involved, its practical implementation is problematic, due to the reset operation that is used on its counters. Indeed, in cases where a VCO edge occurs in close proximity to the reset signal (which will occur quite often), the measured edge count is likely to become corrupted, due to the propagation delay characteristics of the counters and the need for adequate setup times on the sampling registers. This count corruption process will, in turn, destroy the desired noise-shaping properties of the structure. There are a variety of alternative VCO-based quantizer structures that could remove the reset issue just discussed; here we focus on one suited for high-sample-rate operation, which is shown in Fig. 9.5 [5]. In this structure, the multi-bit counters and resettable registers shown in Fig. 9.4 are avoided in favor of an implementation that only requires a set of standard registers (with no reset), XOR gates, and a final adder stage. We see that an explicit reset operation is avoided, and the relative

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VCO-QUANTIZER BACKGROUND Vtune

VCO Output 101010010

Fclock > 2 FVCO Clock

251

N-Stage Ring Oscillator

N-bit Register N-bit Register

011010101 z-1

Sample

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010101010 101011010 101010110

N XOR Gates First Order Difference

XOR Output

Quantizer Output

110000111

5

001111111

7

111110000

5

000001100

2

111100011

6

010110101

Out

FIGURE 9.5

High-speed multi-phase VCO frequency measurement.

simplicity of this circuit allows high-speed operation with small latency, which are important characteristics when placing the VCO-based quantizer within a CT
 ADC structure. To better understand the operation of a high-speed VCO quantizer structure, we can examine the binary sequences shown in Fig. 9.5. The key idea is to observe whether a given VCO delay cell undergoes a transition within a given clock period by comparing samples of its current and previous states with an XOR operation. The number of VCO delay cells that undergo a transition within a given clock period is a function of the delay through each stage as set by the Vtune voltage, and, in fact, corresponds to the quantized value of the Vtune voltage that we seek. An important observation from Fig. 9.5 is that the XOR outputs barrel-shift through their values with each progressing sample. This property will be exploited later in the chapter. A key constraint for achieving proper operation of the VCO-based quantizer in Fig. 9.5 is that the maximum number of VCO delay cell transitions that occur in one clock period cannot exceed the number of stages N in the ring oscillator. We express this restriction mathematically as Ts
(9.2)

where Tdelay (V ) is the propagation delay of each delay stage as a function of the VCO tuning voltage, and Ts is the sampling period. Since the oscillator period, TVCO , corresponds to the time it takes a given edge to propagate through each delay stage twice, we also have TVCO (V ) = 2N Tdelay (V )

(9.3)

By combining (9.2) and (9.3), we can offer alternative views of the same restriction to be that min{TVCO (V )} > 2Ts

(9.4)

max{FVCO (V )} < Fs /2

(9.5)

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where FVCO (V ) corresponds to the instantaneous frequency (in Hertz) of the oscillator and Fs = 1/Ts corresponds to the frequency (in Hertz) of the sampling clock. Equation (9.5) therefore states that the maximum oscillator frequency should be confined to be less than half of the quantizer clock frequency. If we assume that the nominal oscillator frequency, FVCO , is half of its maximum value (such that half of the elements transition for zero input), we are left with requiring a sampling rate that is four times the nominal VCO frequency. Thus, we have another design constraint, namely that Fs ≈

2 NTdelay

(9.6)

where Tdelay is the nominal delay for each oscillator stage.

9.3

SNDR LIMITATIONS FOR VCO-BASED QUANTIZATION

In this section we examine the key limitations in achieving a high SNDR for VCObased quantizers. We begin with a linear model of the VCO-based quantizer to provide a basis for the rest of this chapter, and then examine the theoretical limits to SNR considering only quantization noise. A behavioral simulation example is then presented which indicates the approximate SNDR performance of such quantizers in 0.13-µm CMOS technology. The example will draw out the fact that nonlinearity in VCO-based quantization is the primary bottleneck to achieving high SNDR values. 9.3.1

Linear Modeling

Figure 9.6 depicts a functional block diagram of the VCO-based quantizer on the left and its corresponding linearized frequency-domain model on the right. Comparing the block diagram to the corresponding quantizer structure in Fig. 9.5, the VCO block corresponds to the ring oscillator, and the quantizer block corresponds to the first set of registers, which sample the quantized phase signal of the VCO. The first-order

VCO Quantization Noise Noise -20 dB/dec VCO

First Order Quantizer Difference

Vtune

Out

1- z-1 Clock

f Vtune

Output Noise 20 dB/dec

f

2πKv s

1 Ts

VCO

Sampler

f Out

1- z-1 First Order Difference

Ts

FIGURE 9.6 Block diagram model and corresponding linearized frequency-domain model of VCO-based quantizer.

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difference block corresponds to a comparison of the register values to their previous sample values by the XOR gates in Fig. 9.5. In the corresponding frequency-domain model, the VCO is represented as an integrator with gain 2π K v , which represents conversion of the Vtune voltage to a VCO phase signal, and the addition of phase noise. The quantizer is modeled as a sampler that adds quantization noise, and the first-order difference block is seen as a 1 − z −1 transfer function that performs a discrete-time differentiation. A key observation offered by Fig. 9.6 is that the quantization noise is first-order noise-shaped by virtue of the first-order difference operation shown in the figure, which is in agreement with the time-domain view of the quantization noise described in (9.1). We also see that the VCO phase noise is shaped as well, but the result of such shaping is a flat spectrum due to the −20-dB/dec slope of the original phase noise signal. In reality, the shaped VCO phase noise will also include 1/ f noise, but this is ignored for now for the sake of modeling simplicity. In effect, the first-order difference block converts the VCO phase signal to a corresponding VCO frequency signal. To be precise, however, the discrete-time (DT) differentiation is not an exact inverse function of the continuous-time (CT) integration, noting first that sampling will alias the input signal, and that the 1 − z −1 filter is only an approximation to the CT differentiation. As shown in Fig. 9.7(a), the resulting DT spectrum of the VCO frequency measurement tightly follows the input spectrum for low frequencies with the expected low-frequency gain factor of 2π K v , but then begins to fall off slightly around Fs /2 ( = π ), due to the CT/DT inverse approximation.

1

CT Input Signal

DT VCO Phase

CT VCO Phase

2π πKv

DT Quantizer Output Alias

Alias

Sum

Sum

s Vtune(s)

Ω

s φvco(s)

2π πKv s VCO

1 Ts

Sampler

φvco(z)

Ω Out(z)

1- z-1 First Order Difference

(a)

Vtune(s)

1 Ts

Vtune(z) 2πK T φvco(z) v s

Sampler

1 - z-1 VCO

Out(z)

1- z-1

First Order Difference

(b)

FIGURE 9.7 View of an example spectrum as it passes through the VCO-based quantizer: (a) mixed-mode view with both CT and DT spectra; (b) DT linear model with the sampler moved to the front end.

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An interesting observation to be made here is that the VCO-based quantizer has an inherent first-order antialiasing filter. This can be seen in the quantizer output on the right side of Fig. 9.7(a) by comparing the reconstructed input signal (shown as a dark line) with the aliased copy (shown as a lighter line). Although by itself this first-order antialiasing filter can be considered as fairly crude, the aliasing rejection approximately equal to 20 log (Fs /Fb ) can be significant for some applications. Here, Fb refers to the analog input bandwidth. For purposes of linear analysis it can be useful to choose a primary time domain in which to operate, and for historical reasons we choose here to use discrete time. Therefore, we next develop a DT model for the VCO quantizer that will be helpful later in the chapter. First, it is commonly known that the CT integration can be approximated as a DT accumulator by using a Taylor series expansion of e x : 1 1 = −1 1−z 1 − e−sTs

(9.7)

=

1  (−sTs )2 (−sTs )3 (−sTs )1 + + + ··· 1− 1+ 1! 2! 3!

≈

1 sTs




|s|  Fs

(9.8)

(9.9)

To create the DT model, we then replace the CT VCO gain of 2π K v /s with the  DT VCO gain of 2π K v Ts / 1 − z −1 and move the sampler gain of 1/Ts before the VCO quantizer, as illustrated in Fig. 9.7(b). Not surprisingly, for low-frequency input signals we can now approximate the VCO quantizer as a single block with gain AVCO-q (z), which translates an input voltage Vtune (z) to a frequency (in rad/sample) at the VCO output Out(z) by AVCO-q (z) =

9.3.2

Out(z) ≈ 2π K v Ts Vtune (z)

(rad/sample/V)

ω  Fs

(9.10)

Theoretical SNR

Now that a model for the VCO quantizer has been detailed, we can utilize the wellestablished analysis of oversampling quantizers in order to understand a theoretical bound to its SNR performance. The expression for peak signal-to-quantization noise ratio (SQNR) of a
 converter is found in [14] to be SQNRpeak =


2 OSR 2n+1 3π  β 2 − 1 (2n + 1) 2 π

(9.11)

where β is the number of bits, n the
 order, and the oversampling ratio OSR = Fs /2Fb . For the first-order VCO-based quantizer, with Tdelay and Fs as the primary

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design variables related to N through (9.6), we have 2β − 1 = N =

2 Fs Tdelay

(9.12)

Therefore, we can simplify (9.11) to SQNRpeak =

9

Fs

4π 2 (Fb )3

(Tdelay )2

(9.13)

One important thing to notice from (9.13) is that SQNRpeak of the VCO-based quantizer improves with faster sampling and faster delay elements. For a series-connected ring oscillator, the nominal delay per stage is set to be approximately twice the minimum inverter delay in the process, and the sampling rate is set to be as large as practical. Thus, advancing the process to reduce the digital delay by a factor of 2 can improve SQNRpeak by 9 dB for the same input bandwidth. 9.3.3

Example

In the previous subsections we highlighted quantization noise and, to a lesser extent, thermal noise as key nonidealities of the VCO quantizer. However, one important issue that has been neglected so far is that the voltage-to-frequency tuning curve of a VCO is quite nonlinear in practice. Figure 9.8 shows that the impact of such nonlinearity is to introduce harmonic distortion, which can significantly degrade the SNDR performance of the quantizer. Although the linear models so far provide an intuitive understanding of the VCO quantizer, we will now see that the VCO nonlinearity is actually a critical bottleneck to achieving good SNDR performance when this quantizer is used for analog-to-digital conversion. To gain a better idea of the relative limitations posed by each of these nonidealities, we now present an example design of a VCO quantizer. Considering a 0.13-µm

Input Spectrum

Input Harmonics

f

f

Vtune Kv

2π s

Tuning Frequency to Phase Gain

FIGURE 9.8

VCO Noise

Quantization Noise

f

Output Spectrum

f 1 Ts Sampler

f Out

1- z-1 First Order Difference

Behavioral model illustrating the VCO quantizer nonlinearity.

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-20

Quantization Noise

-40 Amplitude (dB)

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-60 Thermal Noise

-80 -100 -120 -140

10

5

10

6

7

10

10

8

Frequency (Hz)

FIGURE 9.9

Behavioral simulation results of a VCO-based quantizer.

CMOS process technology, along with typical noise and nonlinearity performance, we choose to make the following assumptions for the design example: r r r r r

Sampling clock: Fs = 1 GHz Nominal delay per delay stage: Tdelay = 65 ps Nominal VCO gain: K v = 750 MHz/V Nonlinearity of VCO tuning characteristic: ±10% VCO noise: −100 dBc/Hz at 1-MHz offset

From (9.6), the choice of sampling frequency and delay above implies that N = 31 and that FVCO = 250 MHz. The K v of 750 MHz/V then restricts the maximum input signal to be ±300 mV. Figure 9.9 displays the impact of the three key nonidealities on the quantizer output spectrum given a 2.5-MHz input signal near full scale. The figure illustrates first-order noise shaping of the quantization noise, filling in of the low-frequency noise by the VCO phase noise, and harmonic distortion caused by the nonlinear VCO tuning characteristic. In this example, let us choose to lowpass-filter the quantizer output with a bandwidth Fb set to 20 MHz, which coincides with the point at which the influence of quantization noise is comparable to that of the VCO phase noise. In such a situation we obtain the following SNDR values: r Quantization noise only: 68 dB1 r Quantization noise and VCO phase noise: 65 dB r Quantization noise, VCO phase noise, and nonlinearity: 34 dB (SQNRpeak = 50 dB) 1 Note

that behavioral simulation with quantization noise only agrees with the theoretical calculation from (9.13).

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 ADC ARCHITECTURE

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This example clearly reveals that VCO nonlinearity forms the primary bottleneck to achieving high SNDR values for a VCO-based quantizer. It is this issue that leads us to the
 ADC architecture presented in Section 9.5. 9.4

VCO QUANTIZER
 ADC ARCHITECTURE

One approach to improving a quantizer’s linearity and quantization noise performance is to place the quantizer in a
 feedback loop. It is natural to consider the VCO quantizer for a
 ADC [1,5], since its distortion and quantization errors will be suppressed by the preceding gain of the loop filter. A general block diagram for such an architecture is shown in Fig. 9.10, which also highlights exaggerated waveforms to illustrate the loop limiting the effect of VCO nonlinearity. There are many differences between the VCO quantizer and a traditional comparator-based quantizer in the context of a
 ADC. For example, we will see that a unique attribute of the VCO quantizer architecture is that the overall quantization noise shaping is the sum of first-order shaping from the VCO-based quantizer plus the order of the loop dynamics. In the first part of this section we discuss some of these fundamental differences, such as the ability to provide dynamic element matching (DEM), the probability of metastable behavior, sensitivity to offset and mismatch, and signal-dependent power consumption. In the second part of the chapter we define a model for the VCO quantizer
 ADC, including nonlinearity error, that allows for analysis of nonlinearity suppression. This model will verify that the VCO quantizer
 ADC does indeed have an extra order of quantization noise shaping, and will highlight the fact that many traditional techniques for reducing quantization noise also apply to suppressing VCO quantizer nonlinearity. Finally, we confirm the model with behavioral simulation of two idealized converters. 9.4.1 Comparison of a VCO Quantizer and a Comparator-Based FLASH Quantizer for
 ADC 9.4.1.1 Implicit Barrel-Shift DEM Using the VCO-Based Quantizer A main attraction to high-speed CT
 ADC is the ability to leverage very high-speed

Clock

In

Error

Gain and Filtering

DAC Out

FIGURE 9.10

Vtune

VCO-based Quantizer

Out

DAC


 feedback to suppress VCO linearity and quantization errors.

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In

DAC Out

VCO-based Quantizer Implicit Barrel-Shift DEM

DAC

N-Stage Ring Oscillator

Out

Clock

N-bit Register N-bit Register

Barrel-Shift DEM Quantizer Element

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1-Bit DACs

Sample

FIGURE 9.11

DAC Out

Utilizing VCO for implicit barrel-shift DEM of DAC elements.

sampling in order to maximize input bandwidth and dynamic range. However, for high-speed multi-bit
 ADC (>500 MS/s and >2 bits), a very significant design challenge is to implement a DEM algorithm for the feedback DAC elements within strict timing requirements and for minimal power consumption. Although many dynamic element matching (DEM) techniques are well known, many approaches become overly complex for many levels or are not suitable for clocking at very high speed. Fortunately, the multi-bit VCO quantizer can implement a barrel-shift DEM algorithm without any penalty in terms of latency or power, which is a significant advantage of the architecture. Figure 9.11 illustrates how by connecting the outputs of the VCO quantizer to the DAC elements in a bitwise fashion, the phase rotation of the VCO inherently implements the barrel-shift DEM algorithm [5]. Instead of digitally summing the XOR outputs prior to the feedback DAC, an analog summation is accomplished with current after the DAC. The first element to be used in a sample period is the last one left over from the previous sample, which ensures that each element is used with equal likelihood. To generate the output word, digital adders are still required, but these may be pipelined, as the delay has been removed from the critical path. We should note that some very demanding applications have avoided use of the barrel-shift algorithm, due to the potential for tones created by limit cycles in the signal band. This issue is a valid concern, as will be seen in Section 9.5, although the level of degradation can be considered to be negligible for the vast majority of applications. Compared to the comparator-based quantizer, which has no inherent DEM properties, the barrel-shifting DEM of the VCO quantizer is very attractive. 9.4.1.2 Metastability Another critical aspect of a high-speed
 ADC design is that the quantizer bit decisions must be made quickly and decisively. It is then worthwhile to consider a useful advantage of the VCO-based quantizer over classical

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 ADC ARCHITECTURE

T CQ

Metastable Region

δv

259

CLK Vin Vthreshold

Q

T CQ-max

0

FIGURE 9.12

V threshold

V DD

Vin

Dependence of comparator clock-to-Q time on input voltage.

comparator-based, multi-level quantizers with respect to metastability behavior. Let us first consider metastability for the general case of a single comparator and then apply this result to both quantizer topologies. As shown in Fig. 9.12, the comparator regeneration time, TC Q , between the sampling clock edge and a valid output is a strong function of how close the input voltage Vin is to the comparator threshold voltage, Vthreshold . In fact, the regeneration time is infinite for an input voltage exactly equal to Vthreshold . If we can allot a maximum regeneration time TCQ-max for the comparator decision to be made, then there is a small voltage δv /2 for which
 δv ≈ TCQ-max TCQ Vthreshold ± 2

(9.14)

For simplicity we can say that the input voltage to the comparator is a random variable with uniform density on the interval [0, VD D ], which gives us the probability of metastability in a single comparator:     δv Pcomp metastability = Pcomp Vin | TCQ (Vin ) > TCQ-max ≈ VD D

(9.15)

In an ideal FLASH ADC, the input voltage interval [0, VD D ] is divided uniformly into N subintervals, each with a unique threshold voltage centered on the subinterval. We can then assume that for a single input only one comparator has an input signal close to its threshold, which gives the probability of metastability for the FLASH ADC of     N δv Pflash metastability = Pflash Vin | TCQ (Vin ) > TCQ-max ≈ VD D

(9.16)

As can be seen in (9.16), the probability of a metastable event increases linearly with the number of quantization levels in the flash ADC for the same comparator. When these metastable events become so likely that the resulting errors affect the SNR performance of an ADC, the comparator must be redesigned to have larger gain

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and/or bandwidth to reduce δv . Unfortunately, such improvements inevitably come at the price of increased power consumption and area. In the case of the VCO quantizer, we first note that the input voltages to the comparators are primarily binary voltage signals saturated to either 0 or VD D . When the VCO is a ring oscillator comprising a serial chain of inverters, only one of the outputs is transitioning at a time between these binary levels. As such, when we consider the input voltage distribution of the comparators, only one of them will see a uniform distribution at a time. Therefore, the overall probability of metastability for the VCO quantizer is the same as the single comparator, or, explicitly,     δv PVCO metastability = Pcomp TCQ > TCQ-max ≈ VD D

(9.17)

To compare, the probability of a metastable event for the VCO quantizer is approximately a factor of N smaller than for the FLASH architecture, and it is also independent of the number of quantization levels. This unique result greatly simplifies the VCO quantizer comparator design and allows for very high-speed operation with minimal power consumption. 9.4.1.3 Comparator Offset and Monotonicity Since most high-speed comparators designs utilize minimum-size devices, offset in deep-submicron comparators can be 50 mV or more. For a multi-bit FLASH ADC, this level of comparator offset can be on the order of a quantization step size, which introduces significant nonlinearity and threatens quantizer monotonicity. Although this would be an concern for any converter, in
 ADC these issues can cause the loop to severely limit-cycle or even become unstable. Consequently, some form of offset calibration is needed in the implementation of a traditional multi-bit FLASH quantizer. When we consider how comparator offset affects the VCO quantizer, we first recognize that the level of comparator offset is much smaller than a quantization step size. Using an argument similar to that discussed above for metastability, the quantization step size is effectively equal to VD D , which it can be argued will always be much larger than a comparator offset. Second, we also recognize that the quantization error due to comparator offset will be first-order shaped. To explain, recall that in the same barrel-shifting manner discussed earlier for the DAC DEM circuit, the use of comparators and their associated offsets are rotated as the VCO rising and falling edge propagates around the ring. Compared to the FLASH ADC, not only is the comparator offset a much smaller fraction of the LSB range (by a factor of N , as discussed earlier), but the offset-induced errors are also suppressed with first-order shaping. Given these results, it is not surprising that the VCO quantizer is also guaranteed to be statistically monotonic, and in fact, it is relatively easy to prove this additional property. Equation (9.10) ( AVCO-q ≈ 2π K v Ts ) states that the VCO acts as a simple gain element at dc, and thus mapping an input voltage to output frequency is one-to-one and monotonic. We next consider that due to the ideal integration and differentiation in the VCO quantizer at dc, the measurement or quantization error in determining the dc output frequency limits to zero. We can then conclude that even in

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 ADC ARCHITECTURE

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the presence of large comparator offsets, the dc transfer function from analog input voltage to digital output is monotonic. 9.4.1.4 Power Supply Considerations One final issue to consider in the design of high-resolution ADC is the correlation between the input signal and power consumption, either through digital switching or analog biasing. If such power supply variation or noise couples nonlinearly into the signal path, distortion in the actual conversion can result. For the multi-bit FLASH quantizer, each of the comparators switches for each sample, and so to first-order the quantizer power consumption does not depend on the input signal. For the VCO quantizer, the switching activity within the VCO core is directly proportional to the input signal, and as such the power supply current is a relatively strong function of the input signal. As such, care must be taken to isolate the VCO power supply properly from other analog blocks in the signal path. 9.4.2

Modeling the Suppression of VCO-Quantizer Nonlinearity

Although we hypothesized earlier that feedback with high gain will improve the VCO nonlinearity, a more quantitative examination of nonlinearity suppression can be useful in highlighting the fundamental trade-offs and limitations of the technique. Figure 9.13 shows a simplified DT and CT model for a basic
 VCO-based ADC Enl(z) U(s)

U(z)

1 Ts Sampler

Alf(z)

Avco-q

Loop Filter

VCO Tuning Gain

Eq(z) 1

V(z)

1 - z-1

1 - z-1 Phase Integrator

First Order Difference

DAC Adac

(a) Enl(s) U(s) Alf(s)

Avco-q

Loop Filter

VCO Tuning Gain

Eq(s) 1 s Phase Integrator

V(s) s

1 Ts

First Order Difference

Sampler

V(z)

DAC Adac

(b)

FIGURE 9.13 Model in discrete time (a) and continuous time (b) for a VCO quantizer
 ADC with nonlinearity error E nl and quantization error E q .

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that includes error terms from both a quantization error, E q , and a VCO nonlinearity error, E nl . Although each domain has advantages for different stages of the ADC design, as mentioned earlier we will use DT from this point forward, without loss of generality. In this model the units of E q are radians and the units of E nl are rad/sample, which normalizes the nonlinearity error to the reference frequency. As the quantization noise-transfer function Hq (z) describes how the quantization error E q (z) is shaped in the digital output of the ADC, we can also consider a nonlinearity transfer function Hnl (z) that will suppress the nonlinearity error E nl (z) from the VCO quantizer. For this analysis we make a small-signal linear approximation that decouples E nl (z) from U (z), allowing us to estimate how well the loop is able to reject E nl (z) as a function of frequency. With these definitions, we can generally describe the modulator output V (z) as V(z) = G(z)U(z) + Hq (z)Eq (z) + Hnl (z)Enl (z)

(9.18)

From Fig. 9.13 we find that G(z) = AVCO-q Alf (z)H(z) Hnl (z) = H (z)   Hq (z) = 1 − z −1 H (z)

(9.19) (9.20) (9.21)

where H (z) is given by H(z) =

1 1 + AVCO-q ADAC Alf (z)

(9.22)

Equation (9.20) confirms our intuition that the nonlinearity error Enl will approximately be suppressed by the gain of the loop, which is set by the overall loop order and dynamics. Also as expected, we can also see from (9.21) that the quantization noise suppression is one order higher than the order of the loop filter, due to the 1 − z −1 term in Eq . Finally, in terms of minimizing both quantization noise and VCO distortion, we clearly desire a large Alf (z) to minimize H (z) in the signal band of interest, noting that Alf (z) is a strong function of frequency. The standard techniques to minimize H (z) given a lowpass signal bandwidth are to increase the loop order and to optimize the placement of H (z) zeros. Figure 9.14 plots the maximum value of H (z) for varied oversampling ratio, loop order, and zero optimality [15], which corresponds directly to the minimum amount of VCO nonlinearity suppression. A loop order of up to four is readily achievable as a standard practice today, and in this case a large oversampling ratio (OSR) provides tremendous suppression of VCO nonlinearity error. However, as the OSR decreases to less than 20, for stability reasons the various loop orders begin to cluster together. In fact, if the OSR < 16, the higher-order loops lose so much advantage that a first-order loop is actually preferable to a fourth-order loop without optimal zero placement. Although the trend for OSR has been decreasing to optimize efficiency, applications that can

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 ADC ARCHITECTURE

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10

Maximum In-Band H(z) (dB)

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0 -10 -20 -30 -40 -50 -60 -70 -80 10

1st Order 2nd Order: DC Zeros 2nd Order: Optimal Zeros 3rd Order: DC Zeros 3rd Order: Optimal Zeros 4th Order: DC Zeros 4th Order: Optimal Zeros

20

40

100

Oversampling Ratio FIGURE 9.14 Maximum in-band H (z) for a lowpass modulator across oversampling ratio and loop order. The zeros are placed either at dc (dashed line) or at locations optimal for the oversampling ratio (solid line).

afford a large OSR may very well tolerate a crude and digital VCO design with poor analog characteristics. We can now make a few general observations regarding the suppression of VCO nonlinearity from
 feedback. In one sense, the
 modulator has improved the VCO quantizer nonlinearity by approximately the gain of the loop, which is a significant and marked advance over the stand-alone architecture. However, we can also see that the linearity performance of the VCO has not been improved in relation to the quantization noise. Observe that both the quantization noise Eq (z) and the distortion Enl (z) have been modified by the same factor of H (z) compared to the quantizer without feedback. Therefore, as was the case in the VCO-based quantizer example from Section 9.2, we may expect that the VCO nonlinearity may still present a limitation for frequencies very close to the maximum edge of the input bandwidth. 9.4.3

Example

To verify the analysis above, we can again simulate an example VCO quantizer
 ADC at the behavioral level using CppSim [16], a very fast code-driven C++ simulator that is especially targeted at high-performance mixed-signal systems. A tutorial that includes the example simulation is also free and available online. Before simulating the converter from Fig. 9.13, we need to consider that even in the ideal sense, the VCO quantizer has a delay that has so far not been modeled. This excess loop delay causes phase lag in the signal transfer function and must be accounted for in order to ensure loop stability. For our purposes here, the delay for the VCO

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U(z)

Adac1

Alf (z)

Avco-q

z-1

Loop Filter

VCO Tuning Gain

Delay

Adac2

V(z)

FIGURE 9.15 Model for the prototype ADC, including excess loop delay and a minor compensation loop.

quantizer is approximated by a single sample period. As we will see in Section 9.5, this estimate of a single sample period agrees fairly well with a more precise delay value calculated for a practical system, and allows for relatively simple calculation of loop filter parameters. A modified block diagram that includes this excess loop delay as a z −1 delay element is pictured in Fig. 9.15. Included in the system is a minor feedback loop that compensates for the impact of excess loop delay incurred by the latency of the VCO quantizer [17]. To explain in more detail, we can calculate that the prototype noise transfer function H (z) has been modified from (9.22) so as now to be given by H(z) =

1 . 1 + AVCO-q [ADAC1 Alf (z) + ADAC2 ] z−1

(9.23)

Although the feedback from ADAC1 is now delayed by both the loop filter and the excess loop delay, the overall effect on the loop dynamics can now be mitigated by proper design of ADAC2 and Alf (z). A design procedure has been outlined in [17] (and scripted in the tutorial) that allows the designer to map from the desired NTF to the design of Alf . In this example, we examine the SNDR performance of the same ADC with two different loop filters, and the same assumptions regarding the VCO quantizer have been made in this example as in the previous case without feedback. The first case is a second-order loop filter without zero optimization, and the second is a fourth-order loop filter with optimized zero placement for Fb = 20 MHz. Figure 9.16 displays the original VCO quantizer spectrum from the earlier example in the background, and overlays the spectrum of the
 ADC in the foreground. The first case with a secondorder loop filter is shown on the left side in Fig. 9.16(a), and one can clearly see that the suppression of both the quantization noise and nonlinearity decreases with frequency, as expected. On the right side in Fig. 9.16(b) is the second case with a fourth-order loop filter with optimized zeros. Here, the level of error suppression is increased significantly, and the suppression is generally flatter across the band of interest. By comparing the simulation results of the two loop filters, we can justify the assumptions made previously in developing the model for nonlinearity suppression. In fact, both the levels of suppression as well as the overall frequency dependence

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 ADC EXAMPLE WITH A VCO QUANTIZER 0 -40 -80

0

SNR = 86.6dB SNDR = 77.4dB Fb Open-loop VCO-quantizer

-120

2nd order loop filter

-160 5 10

6

10

7

10

Frequency (Hz) (a)

8

10

Amplitude (dB)

Amplitude (dB)

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SNR = 99.5dB SNDR = 93.7dB

-40

Fb

-80 -120 -160 5 10

4th order loop filter 6

10

7

10

10

8

Frequency (Hz) (b)

FIGURE 9.16 Behavioral simulation results of an example VCO quantizer
 ADC with (a) second-order loop filter with NTF zeros at dc and (b) fourth-order loop filter with optimized zeros for Fb = 20 MHz.

agree with what would be expected from the model. In practice, however, there are many other potential sources of nonlinearity in these very high-speed
 ADCs (e.g., DAC mismatch, front-end amplifier distortion), and these other errors must be balanced not only against the VCO quantizer nonlinearity but also against thermal and 1/ f noise. 9.5

PROTOTYPE
 ADC EXAMPLE WITH A VCO QUANTIZER

In this section we demonstrate a prototype
 ADC that is able to suppress VCO quantizer nonlinearity significantly, achieve third-order noise shaping with a single op-amp, and provide inherent dynamic element matching for the feedback DAC. We will discuss the prototype architecture, detail the design of primary circuit blocks, and then show measurement results. 9.5.1


 ADC Architecture

Figure 9.17 displays our proposed ADC structure. This circuit topology incorporates an active loop filter, two 31-element current DACs, and a 31-level VCO-based quantizer to achieve third-order noise shaping. One should immediately notice the simplicity offered by this structure: The active analog components consist of just one op-amp, two current DACs, and a ring oscillator (within the VCO-based quantizer). Indeed, the simplicity allows high-speed sampling at 950 MHz to be achieved with compact area and low power dissipation. Note that while a single-ended schematic is shown for clarity, the ADC is fully differential, with the exception of a pseudodifferential VCO quantizer, as will soon be discussed in more detail. While the topology shown in Fig. 9.17 bears a resemblance to the popular secondorder Candy structure [18], its design is actually quite different with respect to the means by which it achieves stability. In particular, the minor loop feedback, which is

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CIN VIN

RIN

RA VA

DAC1

FIGURE 9.17

RB

CB VB

Vtune VCO-based DOUT Quantizer RC with Implicit Barrel-Shift DEM DAC2

31

Block diagram of the ADC proposed.

created by feeding the output current of DAC2 into the Vtune node, is not formed around an integrator as would be done in the Candy structure. Rather, the two integrators occur before the minor loop and consist of an active integrator (formed by the op-amp and elements RA and CB ) and a lossy integrator (formed passively by elements Rin , Cin , and RA ). The stability of the structure therefore requires the inclusion of an open-loop zero in the signal transfer function, which is formed by elements RB and CB . With the ADC having a target signal bandwidth of up to 20 MHz, the actual closed-loop bandwidth of the ADC was then designed to be around 160 MHz. To achieve an adequate phase margin, the stabilizing zero formed by RB and CB was set to be in the range 75 to 110 MHz (as influenced by the setting of CB , as explained in Section 9.5.2.3). The passive filter, which forms a lossy integrator as mentioned above, was set to be slightly less than 10 MHz in order to attenuate the large current pulses from the DAC1 output. Although the inclusion of the front-end passive filter leads to a slight penalty in noise, it has the advantage of providing a very linear front end for the ADC and simplifying design of the op-amp (which would otherwise have to deal more directly with the current pulses of DAC1 ). As opposed to optimizing the zeros of the ADC noise transfer function for a signal bandwidth of 10 to 20 MHz, we chose to implement a simple ADC topology that highlights the properties of the VCO-based quantizer. Additionally, the topology chosen allows for second-order dynamics and third-order noise shaping with only a single op-amp. To explain, the proposed topology achieves third-order noise shaping through the inclusion of three zeros within its quantization noise transfer function, Eq , as explained earlier. Two of those zeros, provided by the VCO quantizer and the active integrator, are located at or very near the origin. The third zero, provided by the lossy integrator formed by the front-end passive filter, is located slightly below 10 MHz as set by the bandwidth of that filter. While the choice of a 10 to 20-MHz signal bandwidth did not explicitly influence the zero placement, it was strongly considered in choosing appropriate thermal noise levels for the op-amp, DAC1 , and the front-end passive filter. These blocks were therefore designed such that the overall thermal noise had a spectral density comparable to the quantization noise at the edge of the signal bandwidth range (i.e., 20 MHz).

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Given the foregoing overview of the proposed structure, we now examine its various blocks in detail in the subsections that follow. In particular, we present additional circuit details of the VCO-based quantizer, the current DACs, and the loop filter.

9.5.2

Circuit Implementation

9.5.2.1 VCO-Based Quantizer Figure 9.18 is a geometric view of the combined VCO-based quantizer, implicit DEM, and DAC circuitry implemented with 31 levels. In essence, this structure corresponds to the VCO-based quantizer shown in Fig. 9.5, which has been augmented with DAC elements. A bit slice of this structure, which is also shown in the figure, reveals a variable delay consisting of a four-transistor stack followed by a buffer, some digital logic to implement the first-order difference operation, and a DAC element with current output. The buffer is used to isolate the variable-delay output from the sampling register, which is implemented with standard cell regenerative latches. Simulations demonstrated that metastability is not a concern (discussed in more detail in Section 9.4). In terms of delay timing, a halfperiod is available before generating the DAC pulses, which allows use of standard cell XOR gates and true single-phase clock (TSPC) DFF for the subsequent first-order difference logic. There are several advantages of implementing the variable-delay element as a complementary four-transistor stack. First, the pseudo-differential control of the delay value provides a seamless interface with the output of a fully differential loop filter circuit so that common-mode noise in that path is rejected. Second, the topology

Vtune Vtune

V tune / Vtune

7-10x 1x 1x 7-10x

Variable delay

Iout / Iout DQ

Less transitions with small input More transitions with large input

FIGURE 9.18 and DAC.

DQ

Quantizing Register 1-z-1

Differentiator

950 MHz 1-bit IDAC slice IOUT

Current DAC

Geometric view of the proposed 31-level combined VCO quantizer/DEM

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provides reasonably good linearity in the voltage-to-frequency tuning characteristic of the VCO with a compact and low-power implementation, and allows a very large frequency tuning range for the VCO needed to achieve a high range of quantization levels. Third, full-swing CMOS logic levels in the delay element are directly compatible with the standard cell regenerative latches used for the phase register. Finally, the structure supports a high clock rate by achieving a small minimum delay of 35 to 40 ps in the 0.13-µm CMOS process, which is comparable to a loaded inverted delay in that process. In the prototype, the choice of N = 31 elements and Fclk = 950 MHz requires a nominal delay of 70 ps, and therefore a minimum delay of around 35 ps. In designing the variable-delay cell for the VCO-based ADC, care must be taken to avoid a large gain variation in the tuning characteristic of the VCO. Such a gain variation would directly alter the open-loop gain of the overall ADC, which could affect its performance and cause stability problems. Fortunately, with an input common mode set to mid-supply, the delay cell chosen has relatively smooth odd-order degradation at both the bottom and top of the tuning curve, which can be seen clearly in Fig. 9.19. Of course, the quantizer does impose a limited range for its operation, as seen by the fact that at −300 mV differential input voltage, the oscillator has slowed to a level near zero frequency, and above 300 mV the oscillator starts to reach limits in the high end of its frequency range. For the structure implemented, a useful operating range for the VCO quantizer is up to −2 dBFS for 5-bit operation at 950 MS/s. To account for process variation in the center frequency of the oscillator, four gain settings control the level of current drive in the delay cell. As shown in Fig. 9.19, the 2 bits of tuning can account for approximately ±20% of center frequency variation and are hand-adjusted in this prototype. This constitutes a relatively coarse adjustment of the frequency offset of the VCO tuning characteristic, which is acceptable since

500

Oscillation Frequency (MHz)

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400

300

200

100

0

-0.2

-0.1

0

0.1

0.2

Input Voltage (V)

FIGURE 9.19

Tuning characteristic for the VCO quantizer proposed.

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 ADC EXAMPLE WITH A VCO QUANTIZER

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any remaining offset simply translates into a differential offset voltage at the input of the VCO tuning port. Of course, in the case of a severe offset, linearity performance will suffer and, ultimately, the open-loop gain of the ADC will drop significantly if frequency saturation occurs in the VCO. Note that the impact of power supply and thermal variations on the oscillator center frequency are mitigated by the feedback having a large gain at low frequency, as will be seen in Section 9.5.3. Finally, since excess delay introduced by the quantizer degrades the phase margin of the ADC structure, it is worthwhile to estimate its value in the VCO-based quantizer structure proposed. To do so, note that Vtune is integrated over the previous sampling period, which can be seen as a 1/2 clock delay, and the DAC1 pulse logic begins 1/2 period after the quantizer positive sampling edge. Additionally, there is an estimate of 1/4 clock delay for generating the return-to-zero (RZ) DAC pulses. The combination of these effects leads to an excess loop delay of approximately 1.25 clock periods. 9.5.2.2 DAC An RZ topology was chosen for the primary DAC in the prototype ADC (i.e., DAC1 in Fig. 9.17) to minimize the impact of intersymbol interference at the high sample frequency of 950 MHz and to provide additional compensation for the excess loop delay introduced by the VCO-based quantizer. The penalties for choosing an RZ topology are larger current variation at the output summing node, increased sensitivity to clock jitter, and increased power [19]. As mentioned earlier, the issue of current variation was addressed through the use of passive filtering in the prototype. The issue of clock jitter, which strongly affects the SNR of any high-speed continuous-time
 ADC structure, was addressed by using a low noise, off-chip clocking source. The issue of power consumption was partially mitigated through circuit design efforts, the details of which are described below. The schematic for the primary RZ DAC element core is shown in Fig. 9.20, and the overall DAC structure is comprised of 31 unit elements, each connected bit-wise to the VCO quantizer outputs. Degenerated transistors with moderate channel lengths (and accompanying cascode devices) are used on both the top and bottom current sources to minimize thermal and 1/ f noise. The output common-mode range of the DAC is set via the low impedance of the input signals, which have a commonmode voltage of half-supply (VD D /2). Large off-chip capacitors are used for both the NMOS and PMOS bias voltages to reduce noise coupling from the current reference. The full-scale on current of DAC1 is ±9 mA, which corresponds to a full-scale input current of ±4.5 mA. Also as shown in Fig. 9.20, a triple-source configuration steers the current bias to either the positive or negative summing node during the active pulse, and to a relatively low-impedance node set at VD D /2 during the return-to-zero time. This configuration allows the current sources to share current during the RZ time, and therefore saves 25% of the current compared with alternative topologies. However, there is still 50% more bias current used in this design than would be for an NRZ implementation. The RZ DAC switching waveforms are at full-level CMOS logic levels, so the switching transistors see a large overdrive. The on-pulse control is output from NAND gates, which retimes the data with the negative clock state. Careful attention to balancing the differential signals helps to keep source bounce low during switching

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VDD

DATA = 1

VSS IP VP1 VP2

DAC Element (1 of 31) DATA = -1

VA-

VA+

VN2

VOFF

DATA = 0

VN1 IN VDD VSS

FIGURE 9.20 states.

Schematic and operation of the RZ DAC1 , showing the three distinct output

events. Again, the power required in generating the switching waveforms for the RZ implementation is significantly higher than for an NRZ DAC, especially considering the 950-MHz sampling rate. In contrast to the RZ approach used for the primary DAC, the minor loop DAC (which corresponds to DAC2 in Fig. 9.17) is implemented as an NRZ structure, due to its less stringent performance requirements. The clocking of this DAC is done without retiming since the sensitivity to clock jitter and ISI is suppressed by the forward integration path. The 31 elements of this second DAC are scrambled with the barrel-shift DEM, due to the bit-wise connection to the VCO-based quantizer, although the issue of DAC mismatch is not as important for this DAC as for the primary one. The full-scale current of DAC2 is nominally ±64 µA, and can be adjusted over a wide range through an off-chip bias current such that peaking is properly controlled in the noise transfer function (NTF) of the ADC. With the minor loop disabled by removing the DAC current bias, the ADC was still found to be marginally stable. 9.5.2.3 Loop Filter The fully differential loop filter schematic, which uses only a single op-amp, is shown in Fig. 9.21. As mentioned earlier, the loop filter includes a front-end passive filter composed of elements Rin , RA , and Cin in order to absorb

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 ADC EXAMPLE WITH A VCO QUANTIZER

RB

CB

IDAC1 RIN VIN

IDAC2 RC

RA VA

CIN

Vtune

IDAC1

FIGURE 9.21

271

IDAC2

Schematic of a fully differential ADC loop filter.

the large current deviations of DAC1 and provide a very linear ADC front end. Closer examination of the front-end passive filter reveals that voltage VA is actually a virtual ground when placed in
 feedback, so the ADC input current Iin is defined primarily by resistor Rin . The capacitor Cin then filters the error signal Iin − IDAC1 before IA is integrated onto capacitor CB , whose value can be adjusted by ±25% with an on-chip binary capacitor array. Adjustment of CB leads to a gain change in the active integrator, which allows for better accommodating of Kv variations in the VCO-based quantizer. Of course, changes in CB will also lead to variation in the value of the open-loop zero formed by CB and RB . The loop filter op-amp is implemented with the two-stage Miller-compensated topology shown in Fig. 9.22. Since the ADC input is assumed to have a constant common-mode voltage at its input, the first op-amp stage can be cascoded even with a low supply voltage. Note that the output common-mode voltage also controls the input common mode of the VCO, and is set according to a common-mode feedback circuit that consists of two large polysilicon resistors, a single-stage amplifier, and

VDD VP1

Vin+

VinVP2

Vout+

VoutVN1 VCMFB

VSS

FIGURE 9.22

Operational amplifier schematic.

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OVERSAMPLED ADC USING VCO-BASED QUANTIZERS

an off-chip reference voltage [19]. Interestingly, because the VCO-based quantizer offers relatively high SNR performance on its own, a large dc open-loop gain is not required for the ADC topology proposed. As such, the gain is designed to be over 50 dB, with a gain–bandwidth product in the range of 2-3 GHz. As mentioned earlier, minor loop feedback is used to compensate for excess loop delay from the quantizer and DAC1 in order to allow a more aggressive NTF. To avoid the use of another amplifier for a summation operation, current IDAC2 is directed through resistor RC such that the resulting voltage is added to the output of the op-amp. Although the op-amp output resistance is nonzero, it is much less than RC in the frequencies of interest and does not need to be well controlled since the gain and precision of this minor loop are not critical to ADC performance. The value of RC is chosen to keep the parasitic pole, which is formed by RC and the input capacitance of the quantizer, from affecting the loop dynamics. The full-scale current of DAC2 is then set based on the value of RC and considerations of the NTF. In addition to providing analog summation without an amplifier, another benefit of this topology is that the stability concerns of the operational amplifier are isolated from the input capacitance of the VCO-based quantizer.

9.5.3

Measured Results

A prototype of the ADC structure shown in Fig. 9.17 was implemented in a 0.13µm CMOS process. A microphotograph of the fabricated chip is shown in Fig. 9.23. The active silicon area of the ADC is 640 µm × 660 µm, including power supply decoupling capacitors and guard ring. The area for the 5-bit VCO quantizer core is 120 µm × 86 µm, and the total chip area, including 28 pads, is 1.3 mm × 1.3 mm. A

Opamp

Active Area

Input Cap 1.3 mm

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VCO Quantizer

1.3 mm

FIGURE 9.23

Microphotograph of the VCO-based ADC.

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 ADC EXAMPLE WITH A VCO QUANTIZER

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TABLE 9.1 Summary of VCO-Based ADC Measured Performance Specification Sampling frequency Input bandwidth Peak SNR Peak SNDR Analog power Digital power Peak efficiency Active area Total area Technology

Value 900–1000 MHz 10/20 MHz 86/75 dB 72/67 dB 20 mW (1.2 V) 20 mW (1.2 V) 0.5 pJ/step 640 µm × 660 µm 1.3 mm × 1.3 mm 0.13-µm IBM CMOS

summary of the ADC performance is given in Table 9.1, where the figure of merit is P/(2 · BW · 2ENOB ). The power consumption of the ADC is 40 mW, which is evenly split between the 1.2-V analog and digital supplies such that each draw roughly 16 to 17 mA. Although there is no direct way to measure the subsystem current, bias currents indicate that the primary DAC consumes 9 mA, and the operational amplifier, 8 mA. For the digital supply, the pulse waveform generation circuits for the RZ DAC require about 8 mA, the VCO quantizer 5 mA, and the thermometer-tobinary summation circuits take the remaining 3 mA. The SNR and SNDR vs. input amplitude curves across a number of operating conditions are shown in Fig. 9.24. If not otherwise specified, the input frequency is 2.5 MHz, the analog bandwidth is 10-MHz, and the sample rate is 950 MHz. At a 10-MHz input bandwidth, the ADC achieves at least 81 dB SNR and 65 dB SNDR across all input frequencies, a power supply of 1.2 to 1.5 V, and a sampling frequency of 900 to 1000 MHz. Whereas a peak SNR of 14 bits at 10 MHz is achieved very efficiently with only 40 mW of total power consumption, the ADC distortion performance is limited by the VCO quantizer nonlinearity to 10.5 to 12 bits, depending on the specific test configuration. The decline of SNDR with increasing signal frequency in Fig. 9.24 is a consequence of the reduced gain of the loop filter at higher frequencies, which leads to reduced suppression of the VCO nonlinearity. The degradation of SNDR by such nonlinearity was about 5 dB higher than predicted by simulation, which is probably due to the modeling accuracy of the VCO tuning characteristic, which can be affected by layout in addition to process and temperature variations. It may be possible to improve the SNDR somewhat with more attention given to modeling these issues, although as we will see later, other techniques offer more promise in improving VCO linearity. It was observed that low input signal levels into the proposed ADC led to small limit cycles which were seen in the frequency range 10 to 100 kHz. These limit cycles are an artifact of the barrel-shift algorithm used for DEM on the DACs, which is why some demanding applications avoid the use of the barrel-shift algorithm in favor of other DEM strategies [20]. These small limit cycles can reduce the SNR by a few

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90

70

SNR/SNDR (dB)

70

SNR/SNDR (dB)

SNR

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SNDR 50 40

10, 15, 20 MHz 30 20

60

30 20 10 0

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Variable Input Frequency

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Input Amplitude (dBFS)

80 70

80

VDD = 1.3V

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VDD = 1.4V 60

SNDR

50 40 30 20

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-80

-70

-60

-50

-40

-30

-20

-10

0

Input Amplitude (dBFS)

FIGURE 9.24 SNR/SNDR vs. input amplitude across a number of swept parameters, including bandwidth, input frequency, power supply voltage, and sample rate.

decibels when the input signal falls below about −35 dBFS, as seen in the SNR vs. amplitude curves of Fig. 9.24. An FFT of the ADC output with an 1.045-MHz input signal at −15 dBFS is shown in Fig. 9.25. The third-order noise shaping is visible from 10 to 50 MHz, and the quantization noise peaks around 60 MHz. A small noise skirt centered around 1 MHz was found to be from the bandpass filter used in testing. The high-frequency quantization noise feature occurring in the range 200 to 300 MHz is believed to be caused by the mismatch between rising and falling edges of the VCO quantizer, as verified with behavioral simulation. Fortunately, this artifact does not affect the functional operation of the ADC, as its stability was seen to be robust across a wide variety of operating conditions. Table 9.2 compares this work with other reported CT
 CMOS ADCs operating at a sampling rate over 250 MHz and an analog bandwidth of more than 5 MHz. The high SNR of 86 dB achieved in this work points to the strength of the VCO quantizer architecture, which is the efficient reduction of quantization noise through high-speed operation. In addition, the SNDR performance and power consumption are in line

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60 Input Bandwidth 10 MHz 20 MHz

40 Amplitude (dB)

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SNR

76.2

66.4

SNDR

72.4

65.7

0 -20 -40 -60 -80

0.1

1

FIGURE 9.25 TABLE 9.2

10 Frequency (MHz)

100

1000

190,190-point Hanning FFT normalized to an LSB.

Comparison with Published High-Speed CT ADC

Ref. [21] [22] [23] [24] [25] [26] This work

FS (MHz)

BW (MHz)

SNR (dB)

SNDR (dB)

Power (mW)

276 340 400 640 640 1000 950

23 20 12 10 20 8 10

70 71 64 72 76 63 86

69 69 61 66 74 63 72

43 56 70 7.5 20 10 40

with other realizations, and as seen in Section 9.4, additional VCO nonlinearity suppression is possible to improve performance further.

9.6

CONCLUSIONS

In combination with an optimized NTF for a 10 to 20-MHz bandwidth, a higher-order loop filter may be expected to yield at least another 10 dB or more of linearity on top of the performance reported in this chapter. Coupled with a more power-efficient NRZ DAC design, a forecast performance of over 80 dB with 20 to 30 mW in 0.13µm CMOS would certainly compete well with today’s state-of-the-art implementations and architectures. Because the VCO quantizer scales well with digital process technology, there may be even more advantage in the architecture going forward.

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Some ADC applications requiring more than 13 to 14 ENOB with low OSR may face practical limitations to the levels of linearity suppression from that which can be achieved from the known in-loop analog techniques reported herein. In addition, other sources of distortion will then become significant, both in feedback DACs and in frontend amplifiers. Future research in the area of VCO quantizers may find promising results from novel
 linearization techniques, alternative ADC architectures with less sensitivity to VCO voltage-to-frequency distortion, or operation with a more balanced level of linearity and quantization noise performance. Acknowledgments The authors would like to thank MIT Lincoln Laboratory for their funding of this work through the Lincoln Scholars Program and for access to packaging and testing resources. A thank you as well to the MIT high-speed circuits and systems group for their support, and to the high-speed converters group at Analog Devices for helpful discussions and assistance in testing. REFERENCES 1. A. Iwata, “The architecture of delta sigma analog-to-digital converters using a VCO as a multibit quantizer,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 941–945, 1999. 2. R. Naiknaware, H. Tang, and T. Fiez, “Time-referenced single-path multi-bit
 ADC using a VCO-based quantizer,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 596–602, 2000. 3. E. Alon, V. Stojanovic, and M. Horowitz, “Circuits and techniques for high-resolution measurement of on-chip power supply noise,” IEEE J. Solid-State Circuits, vol. 40, pp. 820–828, 2005. 4. J. Kim and S. Cho, “A time-based analog-to-digital converter using a multi-phase VCO,” in Proc. IEEE 2006 International Symposium on Circuits and Systems, pp. 3934–3937, May 2006. 5. M. Miller, “Multi-bit continuous time sigma-delta ADC,” U.S. Patent 6,700,520, 2003. 6. V. B. Boros, “A digital proportional integral and derivative feedback controller for power conditioning equipment,” in IEEE Power Electronics Specialists Conference Record, pp. 135–141, 1977. 7. J. Hurrell, D. Pridmore-Brown, and A. Silver, “Analog-to-digital conversion with unlatched SQUID’s,” IEEE Trans. Electron Devices, vol. 27, no. 10, 1980. 8. M. Hoven, A. Olsen, T. S. Lande, and C. Toumazou, “Novel second-order
- modulator/frequency-to-digital converter,” Electron. Lett., vol. 31, pp. 81–82, 1995. 9. G. Smarandoiu, K. Fukahori, P. R. Gray, and D. Hodges, “An all-MOS analog-to-digital converter using a constant slope approach,” IEEE J. Solid-State Circuits, vol. 11, pp. 408– 410, 1976. 10. F. Kocer and M. Flynn, “A new transponder architecture with on-chip ADC for long-range telemetry applications,” IEEE J. Solid-State Circuits, vol. 41, pp. 557–564, May 2006. 11. T. Watanabe, T. Mizuno, and Y. Makino, “An all-digital analog-to-digital converter with 12-µV/LSB using moving average filtering,” IEEE J. Solid-State Circuits, vol. 38, pp. 120– 125, 2003.

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12. M. A. Farahat, F. A. Farag, and H. A. Elsimary, “Only digital technology analog-to-digital converter circuit,” in IEEE International Midwest Symposium on Circuits and Systems, pp. 178–181, 2003. 13. A. Tritschler, “A continuous time analog-to-digital converter with 90µW and 1.8µV/LSB based on differential ring oscillators,” in Proc. 2007 IEEE International Symposium on Circuits and Systems, pp. 1229–1232, May 2007. 14. Y. Geerts, M. Steyaert, and W. Sansen, Design of Multi-Bit Delta-Sigma A/D Converters. Dordrecht, The Netherlands: Kluwer Academic, 2002. 15. R. Schreier, Delta Sigma Toolbox. http://www.mathworks.com/matlabcentral/fileexchange /loadFile.do?objectId=19&objectType=file. 16. M. Perrott, CppSim. http://www-mtl.mit.edu/researchgroups/perrottgroup/tools.html. 17. S. Yan and E. Sanchez-Sinencio, “A continuous-time
 modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth,” IEEE J. Solid-State Circuits, vol. 39, pp. 75–86, 2004. 18. S. Nortsworthy, R. Schreier, and G. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation. Piscataway, NJ: IEEE Press, 1997. 19. B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001. 20. R. Baird and T. Fiez, “Linearity enhancement of multibit deltasigma A/D and D/A converters using data weighted averaging,” IEEE Trans. Circuits Syst. II, vol. 42, pp. 753–762, 1995. 21. N. Yaghini and D. Johns, “A 43mW CT complex 
ADC with 23MHz of signal bandwidth and 68.8dB SNDR,” in Digest of Technical Papers, IEEE International SolidState Circuits Conference (ISSCC), pp. 502–503, 2005. 22. L. Breems, R. Rutten, R. van Veldhoven, G. van der Weide, and H. Termeer, “A 56mW CT quadrature cascaded
 modulator with 77dB DR in a near zero-IF 20MHz band,” in Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pp. 238–239, 2007. 23. S. Paton, A. Di Giandomenico, L. Hernandez, A. Wiesbauer, T. Potscher, and M. Clara, “A 70-mW 300-MHz CMOS continuous-time
 ADC with 15-MHz bandwidth and 11 bits of resolution,” IEEE J. Solid-State Circuits, vol. 39, pp. 1056–1063, 2004. 24. R. Schoofs, M. Steyaert, and W. Sansen, “A design-optimized continuous-time delta-sigma ADC for WLAN applications,” IEEE Trans. Circuits Syst. I, vol. 54, pp. 209–217, 2007. 25. G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, “A 20mW 640-MHz CMOS continuous-time
 ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB,” IEEE J. Solid-State Circuits, vol. 41, pp. 2641–2649, 2004. 26. R. Schoofs, M. Steyaert, and W. Sansen, “A 1 GHz continuous-time sigma-delta A/D converter in 90 nm standard CMOS,” in Digest of 2005 IEEE MTT-S International Microwave Symposium (IMS), pp. 1287–1290, 2005.

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Reduced External Hardware and Reconfigurable RF Receiver Front Ends for Wireless Mobile Terminals NAVEEN K. YANDURU Texas Instruments, Dallas, Texas

10.1

INTRODUCTION

To support software-defined radio (SDR), the radio-frequency (RF) receiver front end has to be “multi-band, multi-mode” capable. To achieve a multi-band RF receiver, band-specific external RF preselect and interstage filters form a major bottleneck. In this chapter, high-dynamic-range RF front ends that do not need an interstage external filter are shown. It is, however, extremely challenging to design a receiver front end without an RF preselect filter. Some design directions that could potentially achieve RF preselect filter elimination are discussed. To achieve a multi-mode RF front end, the design needs to have programmable performance based on the wireless standard being received to accommodate the blocking and intermodulation scenarios, signal bandwidths, and other factors that are different between standards. A direct conversion–based W-CDMA (wideband code-division multiple access) and EDGE (enhanced data rates for global evolution) dual-mode receiver scenario is used to illustrate the multi-mode concepts. The system calculations for a W-CDMA RF receiver are discussed as the first step toward elimination of an interstage filter in a W-CDMA receiver so that the hardware can be reused for EDGE. Further, the design of high-performance RF circuit blocks with digitally programmable performance is detailed. It is shown that by optimizing the design with respect to system analysis and circuit design, a W-CDMA/EDGE dual-mode receiver without an interstage filter is achieved in 90-nm CMOS. Another example of a global positioning system (GPS) receiver for a mobile terminal in 90-nm CMOS is used wherein external hardware reduction is obtained by superior circuit design. In this case, a highly integrated RF front end is achieved Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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compared to state-of-the-art solutions that use an external low-noise amplifier (LNA) and an interstage filter.

10.2

MOBILE TERMINAL CHALLENGES

The mobile terminal is facing the daunting task of having to accommodate multiple standards and frequency bands based on various mobile applications. The need for data, voice, GPS, digital TV, and short-distance wireless such as Bluetooth has made the RF transceiver and associated hardware a major bottleneck. Further, the need for integration of an RF transceiver in the digital CMOS process to achieve single-chip radio to reduce the cost has meant further design challenges for RF design. In this chapter we specifically address the receiver front-end portion of the RF transceiver. Radio-frequency bands spanning from 500 MHz to 6 GHz need to be supported for the various applications of the mobile terminal (Fig. 10.1). RF preselect filters such as duplexers and surface acoustic wave (SAW) filters along with any external interstage filters are band specific and create lots of hardware when multiple bands need to be supported for an RF receiver (RX). Thus, a “multi-band” receiver capable of operating in various radio-frequency bands would be needed to support an SDR receiver. It is equally important for the receiver to be reused for various RF standards. Different duplex schemes, such as FDD (frequency-division duplex), TDD (timedivision duplex), and half-frequency FDD (HFDD), demand different performance requirements from the RF front end of the receiver, which includes an LNA and RF mixer. Similarly, different signal bandwidths and modulation schemes result in different performance requirements in the post down-conversion circuitry of the RF receiver design. The dynamic range requirements for amplitude-modulated (AM) signals with a high peak-to-average ratio (PAR) are higher than modulation schemes based solely on phase modulation. Thus, the RF receiver needs to have digitally controlled performance flexibility to achieve a “multi-mode” receiver. The challenge for the RF receiver can thus be broadly classified into these two categories: “multiband” and “multi-mode”.

FIGURE 10.1

Multiple bands across the frequency spectrum.

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FIGURE 10.2

10.2.1

281

Multiple bands and related hardware for a W-CDMA receiver.

The Multi-Band Challenge

Figure 10.2 shows the RF front-end hardware for a W-CDMA receiver based on a subset of receiver frequency bands in the 3rd Generation Partnership Project (3GPP) [31]. The hardware shown is for various W-CDMA radio receiver bands, and neither includes receiver diversity or support for any other standards. It also assumes no external interstage filter at the output of the LNA, which is generally required for FDD standards such as W-CDMA. It can be seen that the band-specific external filters, along with associated matching networks, pins on the integrated circuit (IC) and the respective input stage of the LNA create a lot of hardware. The tuned LC load of the LNA can be shared, depending on the proximity of the RF bands and tuning range of the LC tank (Fig. 10.2). External interstage filters and receiver diversity would further compound the problem. Hence, a multi-band receiver that does not use frequency band–specific preselect filters is highly desired.

10.2.2

The Multi-Mode Challenge

A multi-mode receiver has to be capable of receiving all the standards that exist in a given RF band. The DCS band (1805 to 1880 MHz), for example, has both W-CDMA and GSM receiver coverage (Fig. 10.1). Similarly, the 2.4-GHz ISM band can be

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FIGURE 10.3

Hardware reconfigurability to support a multi-band, multi-mode RF receiver.

used by multiple standards. Although it is important to reuse the receiver hardware for a frequency band, several considerations need to be addressed. Difference in signal bandwidths is one such consideration. With the use of high-dynamic-range analog-to-digital converter (ADCs) [6,8], most of the channel select filtering and signal gain control can be performed in the digital domain. This helps in handling the difference in signal bandwidths since it is easier to program the channel select filters in digital. Certain filtering is, however, done in the analog domain after downconversion for filtering the adjacent channel and in-band blockers. Appropriate design reconfigurability of the corner frequency and gain of these analog filters has to be supported for multi-mode programmability. The difference in RF requirements for various standards is another consideration. The blocking and intermodulation specifications are different in terms of blocker frequencies and levels, which vary based on the wireless standard. FDD based standards present an additional linearity challenge because of transmitter leakage compared to TDD and HFDD, where the receiver does not have to handle its own transmitter leakage. The RF front end has to be reconfigurable to trade linearity, sensitivity, and power consumption to achieve a multi-mode receiver, which is a key component for an RF receiver, along with multi-band capability to support an SDR, as shown in Fig. 10.3.

10.3

RESEARCH DIRECTIONS TOWARD A MULTI-BAND RECEIVER

The multi-band reception is a challenging component for supporting an SDR receiver. The main challenge lies in the RF front end. For FDD systems such as W-CDMA, the transmitter (TX) power output can be as high as +25 dBm. In TDD systems such as GSM, the out-of-band blocker power is limited to 0 dBm. Compression,

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283

intermodulation, and reciprocal mixing of these blockers create requirements well beyond the reach of state-of-the-art RF front ends. For this reason, RF filters (preselect and interstage) are typically used to filter the out-of-band blockers and TX leakage to protect the RF front-end circuit from compression and nonlinear distortion. It is important, however, to note that after down-conversion, the blockers can be filtered with relative ease. In direct down-conversion receivers, for example, the blockers are more than an octave away from the desired signal after down-conversion. Clockprogrammable discrete-time analog filters [1,25] or any other analog filtering with sufficient programmability for a filter corner can achieve this. A few of the possible approaches to solving the bottleneck with the RF front end for a multi-band receiver are discussed below. 10.3.1

High-Dynamic-Range RF ADC

A high-dynamic-range RF ADC can hypothetically achieve a radio receiver without RF filtering. But the practical reality is that the performance requirements in the absence of RF filters are prohibitively high. For cellular standards, the input signal dynamic range from the reference sensitivity condition to the maximum signal level condition can be as high as 85 dB [31,34]. More than the input signal range, in the absence of RF filtering, the dynamic range requirement is set by the strong out-ofband blockers that the receiver needs to handle under the sensitivity levels of the desired signal. In GSM, for example, the sensitivity requirement is about −100 dBm and the out-of-band blocker is allowed to be as high as 0 dBm. In W-CDMA, the reference sensitivity signal is about −107 dBm and its own TX (which acts as an unwanted blocker for the RX) is at +25 dBm. The fact that the signal bandwidth is relatively low, providing a significant oversampling ratio (OSR) with respect to the Nyquist rate based on the RF carrier frequency, may be exploited to extend the dynamic range. But the high Nyquist rate, along with the high dynamic range needed, puts the requirement well beyond the scope of state-of-the-art ADCs. 10.3.2

Tunable On-Chip RF Filtering

On-chip RF filtering using coupled-resonator filters (Fig. 10.4) with frequency tuning has been shown in CMOS [20]. Theoretically, these integrated filters can replace the external preselect filters. But some practical considerations, such as the low quality factor (Q), number of orders of the filter needed, and tuning range requirements, limit the potential. In Fig. 10.4, critical coupling is achieved between the two resonators using on-chip magnetic coupling (K ) along with the intended coupling designed between the two resonators. The limited Q of the on-chip inductors is enhanced using cross-coupled transistors, which provide negative resistance. The negative resistance circuit adds noise and has linearity issues which will ultimately limit the dynamic range of the filter. To make these filters feasible for a multi-band receiver, the Q of inductors needs to be improved substantially to avoid the need for Q enhancement. Also, it is beneficial to tune the filter on a channel basis rather than on a band basis, to obtain more rejection for a given filter order and the Q of the inductor.

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FIGURE 10.4 Simplified circuit of a two-pole Q-enhanced LC RF filter in CMOS [20].

The tuning algorithm in this case needs to be designed carefully, considering the sensitivities involved with channel-dependent tuning. A high-Q inductor at RF in CMOS, sophisticated frequency tuning, and calibration and compensation would thus be needed to achieve this goal. The number of filters in this case may depend on the tuning range achieved and the band coverage needed for a multi-band receiver. 10.3.3

MEMS-Based RF Filtering

Banks of microelectromechanical (MEMS) filters for multi-band operation have been reported using RF MEMS technology [26]. The high-Q resonators used for these filters are very small in size, so it is conceivable to use a dedicated filter for each band. High-Q band-select filters thus realized and low-loss switches integrated into a module will essentially fit the requirement from a performance and hardware integration point of view for multi-band receivers (Fig. 10.5). But issues such as reliability, yield,

FIGURE 10.5

Concept of a receiver front end with a MEMS-based filter module.

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Auxiliary Path

HPF

LO

RF Input

RX down conversion

FIGURE 10.6

Concept of a feedforward cancellation of blockers, as shown in [9].

and complexities in integrating mechanical structures with transistors need to be considered. MEMS-based switches may have to be avoided, even though they have low loss, to circumvent the extra complexity of the high-voltage requirement which is necessary for MEMS-based switches. 10.3.4

RF Front Ends with Blocker Cancellation

RF translational loops by means of various feedforward and feedback signal processing mechanisms have been shown recently to achieve cancellation of blockers [3,5,9,27]. A feedforward blocker technique based on [9] is illustrated in Fig. 10.6. The blocker is rejected by adding a parallel RF path with a down-conversion mixer followed by a high-pass filter and another up-conversion before combining the signal back in the main signal path at the LNA output. The auxiliary path is combined out of phase with the main signal path, resulting in only the signal band width being selected (based on the HPF corner) and all other frequencies rejected. The linearity of the LNA is still a challenge, but the bottleneck of mixer linearity can be circumvented. For this technique to be effective, the gain of the auxiliary path needs to be well matched to that in the main signal path, while the phase of the auxiliary path needs to be 180◦ relative to the main signal path. The cancellation of several simultaneous blockers in real-world situations may require multiple signal paths in the auxiliary path. Another important issue is the extremely high phase noise requirement for the up-conversion mixer in the auxiliary path set by the reciprocal mixing of strong out-of-band blockers. 10.3.5

Summary for a Multi-Band RF Receiver Without Preselect Filters

Other approaches, including blocker detection using fast RSSI and subsequent reduction in RF gain, have been investigated. In such cases, the gain needs a lot of reduction to achieve the linearity required when the strong blockers are present, causing an unacceptable increase in the noise figure (NF). In summary, the various

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architectures discussed in this section are not able to match the RF performance of a receiver with dedicated preselect filters. The techniques discussed here may, however, be used to eliminate the external interstage filters between the LNA and the mixer used in certain state-of-the-art wireless receivers, including direct-conversion receivers. In the interim, to support the multiple bands, the best practical option to reduce the hardware to some extent is to implement a switch at the output of the preselect filters, similar to that shown in Fig. 10.5. This increases the NF, however, due to the insertion loss of the switch.

10.4 MULTI-MODE RECEIVER PRINCIPLES AND RF SYSTEM ANALYSIS FOR A W-CDMA RECEIVER A relatively easier goal is that of a reconfigurable multi-mode radio receiver for a given frequency band. For a frequency band with an RF preselect filter, it is highly desirable for the same receiver hardware to be digitally configured for various performance settings. A high-dynamic-range RF front-end design is the starting point. The design has to support various digitally controlled programming modes to trade noise, linearity, and power with each other. The overall figure of merit of the circuit needs to be maintained while programming into these various modes of operation to avoid an unreasonable amount of degradation in one parameter in order to improve another parameter. The lowpass filters used after down-conversion to reject in-band and out-of-band blockers have to be designed such that the corner frequency can be controlled digitally based on the channel bandwidth of various standards. The absence of an interstage external filter is, however, the most important requirement for a multi-mode receiver design. If an interstage external filter is used to support the requirements of a particular standard, all other standards using the receiver hardware take the penalty in performance due to the insertion loss of the external filter. To illustrate this and other concepts of multi-mode receiver design, a W-CDMA and GSM/GPRS/EDGE (GGE) dual-mode system is discussed in this and the next section. In FDD-based W-CDMA, the transmitter and receiver carry information at the same time. Due to this fact and the finite isolation of the two signals provided by the duplexer filter, there is a finite amount of TX power leakage at the input of the RX. The TX leakage amplified by the LNA creates a linearity/dynamic range issue for the RF mixer. Most state-of-the-art W-CDMA direct-conversion receivers [10,12] deal with TX leakage by using an external interstage RF filter (typically, a SAW) between the LNA and the mixer. As discussed earlier, for a multi-mode design it is important to eliminate the need for an interstage filter in a W-CDMA RX so that it is suitable for the GGE mode as well. Optimized system analysis accounting for the AM nature of the blockers [18] and superior circuit design are important to obtaining a W-CDMA RX without an interstage SAW filter. System analysis for the W-CDMA RX is discussed in this section, and the circuit design details for the various blocks in the receiver are shown in Section 10.5. The GGE mode of functionality can be realized by using the digital programmability options of the design. Direct conversion is the preferred architecture, due to reduced hardware (image reject filter, IF filter,

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FIGURE 10.7 IM2 distortion from a modulated TX blocker in the FDD mode in a directconversion receiver. (Any blocker with AM causes this distortion.)

second synthesizer) and signal processing requirements. There are, however, some drawbacks with a direct-conversion receiver. The main drawback is the second-order intermodulation distortion (or self-mixing) of AM-modulated blockers [2,14,16,23]. Figure 10.7 shows the second-order intermodulation distortion (IM2) of TX leakage in a direct conversion–based FDD receiver. Other issues with a direct-conversion receiver include susceptibility to flicker noise and dc offsets [7]. A low-IF or near-zero IF could be used to relax some of these issues if the image rejection requirement set by the blocker level in the image band is not too high. In any case, careful design to reduce LO (local oscillator) leakage, dc offset correction, and necessary IP2 performance from the receiver can circumvent these known issues with a direct-conversion receiver. 10.4.1

W-CDMA RF Receiver System Analysis

Strategic RF system budgeting, along with circuit design techniques achieving optimal performance for the circuit blocks, can result in interstage SAW filter elimination. The reference sensitivity test, in-band blocking test, out-of-band blocking test, and adjacent channel selectivity test, as defined in the RF system standard document [31], give us the key linearity and noise requirements. 10.4.1.1 Reference Sensitivity Test Details of the reference sensitivity test as defined by 3GPP [31] and other assumptions used to calculate the receiver specifications are shown in Table 10.1. Various phenomena that contribute to the input-referred noise power (PN+I ) and their respective allocation normally constitute an iterative process that depends on finding the best balance in what the circuit can support, power consumption, and cost.

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TABLE 10.1

System-Level RF Requirements for the Reference Sensitivity Test

Parameter

Value −106.7 dBm −7.7 dB −99 dBm −174 dBm/Hz 3.84 MHz +25 dBm 55 dB 1

Minimum input signal (reference sensitivity) at RX input (Ior,RS ) [31] SNR required at RX output (SNR) [11] Input referred noise allowed (PN+I ); PN+I = Ior,RS − SNR Thermal noise floor (Pthermal floor ) Bandwidth of W-CDMA signal (BW) TX output power as defined for reference sensitivity test (PTX ) Typical duplexer rejection of TX-to-RX input (L TX ) Number of channels in the TX as defined for reference sensitivity test (N )

A potential budget allocation for each of the noise and intermodulation phenomena contributing to the overall PN+I is shown in Table 10.2. From the budget allocations in Table 10.2, the following specifications for the receiver can be derived. Based on noise allocation, NF = Pnoise floor − Pthermal floor − 10 log(BW) = 7.2 dB

(10.1)

The NF calculated above is for the entire receiver, including the duplexer. Accounting for a duplexer and switch insertion loss of 3 dB, the worst-case NF target of the RF receiver is 4.2 dB. Based on the budget for reciprocal mixing, the phase noise of RX LO at TX offset, PN = PRC,mix − (PTX − L TX ) − 10 log(BW) = −144 dBc/Hz

(10.2)

Based on second-order intermodulation distortion allocation and using the equation for CW (continuous-wave) tone equivalent IP2 from [16] yields IIP2 = 2(PTX − PTX ) − PIM2 + Adj(N ) = 37.2 dBm

(10.3)

where Adj(N ) = 10 log[3/8 − 7/(24N )]. Adj(N ) is the adjustment factor, which takes into consideration that the TX is amplitude-modulated with certain PAR, along with other considerations, including accounting only for the distortion power that falls TABLE 10.2 Budget Allocation of Noise/Distortion Powers for the Reference Sensitivity Test case Noise/Intermodulation Mechanism Raised thermal noise floor due to circuit noise of the RX (Pnoise floor ) Reciprocal mixing of TX with RX local oscillator (PRC, mix ) Second-order intermodulation of TX (Fig. 10.7) (PIM2 ) RX band noise from TX output (PTX in RX ) Total input-referred noise (Pnoise floor + PRC, mix + PIM2 + PTX in RX )

Budget Allocation −101 dBm −108 dBm −108 dBm −108 dBm −99 dBm

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inside the signal bandwidth. IIP2 in (10.3) is the CW equivalent requirement for the second-order distortion caused by TX leakage [2,14,16]. More details on the analysis for the adjustment factor are provided in the literature. An Adj(N ) of −10.8 dB was used based on N = 1 as defined in the 3GPP standard for the reference sensitivity test in the calculation above. 10.4.2

In-Band Blocking Test

The in-band blocker defined in this test can be present anywhere beyond 15 MHz offset from the center of the RX channel [31]. The blocker specified causes other distortions beyond the scenarios discussed in the reference sensitivity test. But for this test, the input signal provided is 3 dB higher than in the reference sensitivity test. Hence, the input referred noise allowed, PN+I = −99 + 3 = −96 dBm, assuming an SNR target of −7.7 dB at the output of the RF receiver. Also, the TX power out of the PA (power amplifier) is 3 dB lower for this test case than for the reference sensitivity test case, leading to 3 dB lower TX leakage (PTX = −30 − 3 = −33 dBm). Due to the in-band blocker, two new phenomenon need to be considered. First, when a blocker is located at a frequency Fblk = (FTX + FRX )/2, third-order intermodulation between TX and the blocker causes distortion (PIM3 ), as shown in Fig. 10.8. Second, reciprocal mixing from the blocker needs to be considered. The blocker power as defined in the test is Pblk = −44 dBm and hence contributes very little from reciprocal mixing (in comparison to the reciprocal mixing from TX leakage of −33 dBm). The PIM3 contribution can thus be given the allocation of the entire 3 dB of extra signal for this test. Using PIM3 = −99 dBm, the IP3 requirement is then given by [24] IIP3 = Pblk + (PTX /2) − (PIM3 /2) + Adj(N )/2

(10.4)

where Adj(N ) = 10 log[4/3 − 1/(2N )]. Formula (10.4) is derived based on the AM characteristics of the blocker and the amount of distortion that falls inside the signal

90° TX

BLK

RX BB

TX Leakage

FIGURE 10.8

Third-order (IM3) distortion from TX leakage and in-band blocker.

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bandwidth of interest [15,24]. Using N = 1, the CW equivalent IIP3 requirement is calculated to be −11.4 dBm. 10.4.3

Out-of-Band Blocking Test

An out-of-band blocker mask is defined in [31]. Accordingly, the blockers farthest from the channel are highest in power, and vice versa. The duplexer filter rejects most of these blockers except those closest to the band, which do not get much rejection from the duplexer. System budgeting for this case is very similar to that of the in-band blocking test, wherein a 3-dB extra input signal is provided with respect to the reference sensitivity test. A third-order intermodulation scenario, where 2Fblk − FTX = FRX as shown in Fig. 10.9, will replace the situation shown in Fig. 10.8 for the in-band blocking test. The blocker is CW in the out-of-band blocking test, but the TX leakage, which is W-CDMA modulated, causes spreading of the IM3 distortion. Depending on the duplexer rejection performance of the blockers and TX, the IIP3 requirement for the receiver could be set by either the in-band or out-of-band blocking test scenarios. 10.4.4

Adjacent Channel Selectivity Test

The adjacent channel selectivity test defines the power of the adjacent channel, which is located at 5 MHz offset from the center of RX channel. The adjacent channel can cause receiver impairments of reciprocal mixing and second-order intermodulation in the RF section of the receiver. Further, the adjacent channel needs to be filtered to select the RX channel of interest. The adjacent channel is close to the channel of interest and hence is most difficult to filter, and thus defines the filtering order for the receiver. In cases where channel select filtering is done in the digital domain, the ADC dynamic range requirement is set by this test. Further, spectral regrowth [17] can occur in scenarios where the adjacent channel power is very high (ACS case 2 of 3GPP [31]). Noise and distortion budgeting is done similar to that in the other

90° BLK

TX

RX

BB

TX Leakage

FIGURE 10.9

IM3 distortion from TX leakage and an out-of-band blocker.

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test cases, to find an optimum balance for the various specifications. It is important to note that a higher number of channels in the AM blocker results in higher PAR, which in turn increases the magnitude of the adjustment factor resulting in higher intermodulation distortion for the same blocker power. Figure 10.10(a) and (b) show the difference in spectral regrowth at the output of RF down-converter for the cases

FIGURE 10.10 Output spectrum after direct down-conversion in the presence of (a) an adjacent channel with one channel (low PAR); (b) an adjacent channel with 16 channels (high PAR).

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where the adjacent channel had 1 and 16 channels, respectively. As can clearly be seen, the amount of spectral regrowth observed is higher when the number of channels in the blocker increases, whereas the overall power of the blocker is the same in both cases [17]. The droop seen in the adjacent channel power in Fig. 10.10 is due to the effect of lowpass filtering after down-conversion. It is also important to note that Fig. 10.10 shows both positive and negative sides of the direct down-converted spectrum, the dc component in the center. 10.4.5

Summary of RF System Analysis

The system test cases described above provide a few of the main RF performance metrics. But other RF tests specified in [31], such as the narrowband blocking, broadband intermodulation, and narrowband intermodulation tests have to be dealt with by similar analysis to derive comprehensive requirements for the RF receiver. It is important to note that the RF receiver has to be designed with an abundant margin compared to the performance requirements derived, to account for temperature, process variations, production margin, and competitive advantage. The AM nature of the blockers has to be considered in evaluating the linearity (IP2, IP3) requirements, similar to the way it was described in the previous analysis and as summarized in [18]. Taking account of the AM nature of the blockers and efficient system budgeting based on the process established in this section contributes to the elimination of a surface acoustic wave (SAW) filter in a W-CDMA receiver. To illustrate this fact, if the AM nature of W-CDMA TX leakage was not taken into account in the IIP2 calculation, as shown in (10.3), and a standard IP2 equation were used instead, the IIP2 requirement for the receiver would have been 10.8 dB higher, necessitating the use of an interstage SAW to filter the TX leakage before the RF mixer. This, along with efficient circuit design, can result in elimination of an interstage SAW in a W-CDMA RX, thus paving the way for the dual-mode (W-CDMA, EDGE) receiver design discussed in Section 10.5.

10.5 W-CDMA, GSM/GPRS/EDGE RECEIVER FRONT END WITHOUT AN INTERSTAGE SAW FILTER A receiver that can be programmed to W-CDMA or GGE mode is important to reduce the hardware in dual-mode phones. The elimination of an interstage SAW filter for W-CDMA performance is also important in making the receiver suitable for the GGE mode, as mentioned in Section 10.4. Yet another important reason for interstage filter elimination is because a triband W-CDMA receiver would need three interstage SAW filters, nine pins on the IC to route the signal in and out of the chip (the SAW used is normally a single-ended input and differential output), and six matching networks (Fig. 10.11). A diversity receiver, if needed, would double this hardware. Therefore, designing a W-CDMA receiver without an interstage SAW filter would save lots of external hardware (Fig. 10.12) while making it suitable for the GGE mode of operation.

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FIGURE 10.11 Triband W-CDMA receiver with interstage SAW filters between the LNA and the RF mixer.

Figure 10.13 is a block diagram of a direct-conversion W-CDMA, GGE dualmode receiver designed in 90-nm CMOS [35]. The design is for the DCS band (1805 to 1880 MHz), and the corresponding TX frequency is 95 MHz (1710 to 1785 MHz) below the RF frequency. The RF front-end design has a high linearity so as to eliminate the interstage SAW filter. However, a preselect filter (or duplexer in this case) would be needed at the input of this receiver, for reasons described in Section 10.3. The RF signal into the receiver is processed by an LNA with an LC load followed by an RF mixer and a variable-gain amplifier (VGA), as shown in Fig. 10.13. Single-pole RC filters which can be programmed between the W-CDMA and GGE mode are realized at the output of the mixer and VGA using

FIGURE 10.12 Triband W-CDMA receiver without interstage SAW filters between the LNA and the RF mixer.

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FIGURE 10.13

Architecture of the dual-mode receiver in 90-nm CMOS.

their respective loads. The VGA may be followed by a high-dynamic-range ADC or by more analog filtering, followed by an ADC. The gain dynamic range is realized by the coarse steps in the LNA and the VGA. The remainder of the gain dynamic range and channel select filtering may be done in the digital domain. A divide-by-2 circuit divides the external LO frequency and provides quadrature output for I/Q paths of the receiver. The measured results reported at the end of the section show that the required performance is secured without the use of an interstage SAW filter. Digital control for performance programmability is supported throughout the design to tailor the performance for the W-CDMA and GGE mode. A supply voltage of 1.4 V is used for the chip except for the transconductance stage of the RF mixer, which uses 2.4 V.

10.5.1

LNA Design

The LNA receives a single-ended RF signal and converts it into a differential signal at its outputs [22] to drive the differential down-conversion mixers. The cascoded singleended-to-differential LNA is shown in Fig. 10.14. Series feedback using inductive source degeneration helps shift the optimum noise match point closer to the desired input matching point; therefore, simultaneous noise and input matching are possible. The degeneration inductor in this design is implemented using an on-chip spiral center-tapped differential inductor. The coupling capacitor CC connected between the inverting node A at the drain of M1 and the gate of M2 provides an input signal to the second branch that is, to a first degree, opposite in phase with the input RF signal, enabling a quasi-differential amplification in the LNA. The LC tank, consisting of inductors L L1 , L L2 , and C L , which represents a digitally controlled capacitor bank, provides some filtering of the TX leakage and out-of-band blockers. The selectivity requirement favors the use of high-Q bondwire inductors over the lower Q

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FIGURE 10.14

295

Simplified single-ended-to-differential LNA circuit.

on-chip spiral inductors for L L1 and L L2 , whereas C L is designed to account for process variations. The variable resistor bank, denoted as RL, connected in parallel to the tank provides an additional degree of freedom to set the trade-offs among selectivity, gain, and linearity, as required by each mode of operation. Within the band, C L and R L are set based on the channel information using a calibrated tuning algorithm. Other digital controls for lowering gain and bias current through Vbias provide further performance programming options. To prevent up-conversion of lowfrequency noise from the biasing network under blocking conditions, the gate bias for transistors M1 and M2 is provided through large bias resistors, denoted as R B1 and R B2 in Fig. 10.14. The LNA has three gain settings, to adjust between sensitivity and linearity. The high-gain mode is designed to provide 22 dB of voltage gain, whereas the mid- and low-gain modes are 18 and 0 dB, achieved by lowering R L and current steering to the supply. The current steering degrades the noise at the low- and mid-gain settings, but with higher incoming signals, higher noise can be tolerated. The simulated IIP3 is −4 dBm and NF is 1.9 dB in the high-gain mode of the LNA. 10.5.2

Transconductance Amplifier and Mixer Design

The simplified circuit for this stage is shown in Fig. 10.15. The mixer core consists of a passive mixer that operates from a 1.4-V supply. A transconductance cascode amplifier with inductive degeneration operating from a 2.4-V supply precedes the

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FIGURE 10.15

Simplified circuit of an RF IQ mixer.

mixer core to provide conversion gain, which also reduces the overall input referred noise. Inductive degeneration is used to improve the IP3 of the transconductance stage. Gain in the amplifier is set by a combination of adjustable bias current, programmable load resistors, and inductive degeneration. Bias voltages are chosen to guarantee the reliability of the transistors. The output pole of the mixer is set using a bank of capacitors along with the load resistor (Rload ). By accurately balancing the output common-mode voltage of the differential outputs with a dc offset compensation circuit, relatively high IIP2 can be achieved. In Fig. 10.15, Vgc is the gate bias voltage for the cascode device and is referenced from the supply voltage. The output common-mode voltage (Vcm ) is set to Vref using a common-mode feedback loop. The input impedance of a common-source stage with inductive degeneration can be written as Z in =

gm 1 + s Ls + Ls sCgs Cgs

(10.5)

where Z in is the input impedance of the common-source stage, L s the source degeneration of the inductor, Cgs the gate-to-source capacitance of the input device, and gm the

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transconductance of the input device. At the frequency of operation 1/sCgs  s L s , the input can be represented as a parallel RC circuit, with C p ≈ Cgs Rp ≈

1 ω2 C p L s gm

(10.6) (10.7)

where C p and R p are the parallel C and R of the parallel RC circuit. A short-channel device is used for the input stage which minimizes the Cgs (which in turn maximizes R p ) for a required gm . High R p is desired to provide a high-impedance load to the LNA. The small-signal equation relating the drain current (i d ) and the gate-to-source voltage (vgs ) can be used to determine the bias point for the input transistors: 2 3 i d = gm vgs + gm vgs + gm vgs + ···

(10.8)

The third-order nonlinearity in the drain current comes from the second derivative of the input transconductance (gm ). Biasing the input device such that the second derivative of gm is minimized achieves the best linearity. The simulated IIP3 of the transconductance amplifier and mixer √ is 1.5 dBVrms (14.5 dBm referred to 50 ) and the input referred noise is 2.4 nV/ Hz with a voltage gain of 6 dB. 10.5.3

LO Divider and Buffer Design

The divide-by-2 circuit for the LO is shown in Fig. 10.16. The circuit takes in a differential clock input (CLK and CLKB) and generates differential quadrature output (IP, IN, QP, and QN) at half the input frequency. There is a buffer driver at the output of the divider to provide fast clocks to the mixer switches. A balanced,

FIGURE 10.16

Simplified circuit of a quadrature LO divider.

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low-parasitic layout is used to ensure good rise and fall times and a 50% duty cycle to ensure good IP2 from the mixer. 10.5.4

VGA Design

A differential amplifier using input transistors MN1and MN2 followed by a source follower (MN3, MN4) is used for the VGA, as shown in Fig. 10.17. The degeneration resistance RS of the differential amplifier is varied to change the VGA gain. At the lowest gain settings the load resistance, RL, is also lowered, to extend the gain dynamic range of the VGA. This architecture allows for low noise in the high-gain mode while providing higher linearity as the gain is reduced. Since the highest gain is used in the reference sensitivity case and the VGA gain is lowered in tests involving blockers, where linearity is more important, this architecture suits the RF requirements. A common-mode feedback using the operational amplifier shown in Fig. 10.17 is used to set the output common-mode voltage to VD D /2. Since the current in the differential amplifier varies with the process variation of the resistor, a resistor sensing circuit has been used to trim the resistors in the design to keep the performance variation to a minimum. The simulated highest gain in the VGA is

FIGURE 10.17

Simplified circuit of a baseband VGA.

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√ 11 dB with an input referred noise of 3.6 nV/ Hz , IIP3 of and an −11 dBVrms (using blockers at 10 and 21 MHz). The output LPF corner is set to 3.5 MHz, and the overall gain dynamic range is 24 dB with a step size of 2 dB. Table 10.3 shows the measured performance and Fig. 10.18 shows the chip photo. TABLE 10.3

LNA to VGA Measured Performance Summary

RF frequency Corresponding TX frequency Baseband signal bandwidth Power consumption Voltage gain Noise figure S11 Gain imbalance Phase imbalance Output dc offset (after correction) CW in-band IIP3 (blockers at 10 and 20 MHz offset) CW out-of-band IIP3a (blockers at TX and TX+47.5 MHz) CW out-of-band IIP3a (blockers at TX and TX−95 MHz) CW IIP2b (Blockers at TX) IIP2 (blocker at TX and blocker at RX + TX frequency) GGE in-band IIP3 (blockers at 800 and 1600 kHz offset) GGE IIP2 (CW IP2 with blockers at 6 MHz offset)

W-CDMA

GGE

1.85 GHz 1.755 GHz 3.84 MHz 75 mW 37 dB 2.9 dB −14 dB 0.4 dB 4◦ 50 µV −8 dBm −7 dBm −4 dBm 52 dBm 34.7 dBm

1.85 GHz

a The

200 kHz 75 mW 37 dB 2.9 dB 0.3 dB 0.8◦

−8 dBm 47 dBm

IP3s reported are CW IP3s. The corresponding IP3s for a true W-CDMA modulated blocker or TX based on the corresponding test case will be different by the adjustment factor, as reported in [15,24]. b The IIP2 reported is a CW IIP2. The corresponding IIP2 with a true W-CDMA TX instead of CW tones would be 62.8 dBm (−10.8 dB of adjustment factor according to (10.3) and the literature [2,14,16]).

FIGURE 10.18

Die photograph of the receiver IC.

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(a)

(b)

FIGURE 10.19

(a) Traditional architecture; (b) integration achieved.

10.6 HIGHLY INTEGRATED GPS FRONT END FOR CELLULAR APPLICATIONS IN 90-NM CMOS A second example of reinforcing the design techniques for high-dynamic-range RF front ends is discussed in this section. Most state-of-the-art GPS receivers in production employ an external LNA followed by a SAW filter [33], to satisfy the dynamic range requirement set by the strong cellular interferers arising from within mobile phones. A highly linear front end with low NF in a digital 90-nm CMOS process is shown, which allows significant reduction in the implementation hardware. The IIP3 of the RF front end is set by the intermodulation product of cellular blockers and other spurious signals. One such scenario is determined by the third-order intermodulation of the transmitted signal in the DCS band (1.85 GHz) and a spurious tone at 2.125 GHz (2 × 1.85 GHz − 2.125 GHz = 1.575 GHz). Evidently, elimination of an interstage filter requires the mixer linearity to be increased significantly while requiring the LNA to do the single-to-differential signal conversion (Fig. 10.19).

10.6.1

LNA Design

The cascoded, inductive source–degenerated single-ended-to-differential implementation of the LNA is similar in architecture to the one shown in Fig. 10.14. The design is, however, different from that of the LNA in Section 10.5. The supply voltage of the LNA is 1.4 V. The LNA achieves an NF of 1.5 dB with an in-band voltage gain of 31 dB and an input referred 1-dB compression point of −26 dBm.

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301

IQ Mixer Design

The mixer design is based on a current-commutating double-balanced architecture, shown in Fig. 10.20. The mixer is designed for a low-IF receiver architecture, with an IF output of 4 MHz. This architecture is chosen instead of direct conversion to reduce the impact of flicker noise, thus making the active mixer a suitable option. Additionally, degradation due to second-order intermodulation of AM blockers, which causes distortion close to dc, is avoided. Dc offset correction is also simplified with low-IF architecture. However, close attention was paid to quadrature (I /Q) balance to guarantee the image rejection requirements. The common-mode output voltage (VCM ) is set to VREF using the op-amp in a common-mode feedback loop, as shown in Fig. 10.20. The output pole of the mixer is set at 8 MHz and helps in filtering any out-of-band blockers, so that the linearity requirements of the subsequent circuit blocks are relaxed. The required input linearity of the mixer is obtained by taking advantage of the short-channel behavior of the MOS transistors in deep-submicron CMOS. Transistors M1 and M2 (Fig. 10.20) are sized and biased to approach velocity saturation. The I D to Vgs characteristic under velocity saturation is given by I D ≈ µn ξc Cox W (Vgs − Vt )

FIGURE 10.20

Simplified circuit of an RF mixer.

(10.9)

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Drain Current (Id) in mA

6.0 W/L = 4(0.9/0.12) W/L = 12(0.9/0.12)

5.0 4.0 3.0 2.0 1.0 0.0 0.40

FIGURE 10.21 high Vgs .

0.50

0.60 0.70 0.80 0.90 1.00 1.10 Gate to Source voltage (Vgs) in V

1.20

1.30

I D vs. Vgs curves for short-channel MOS, showing the linear trend at

where mobility µn , critical field ξc , gate oxide capacitance for unit area Cox , threshold voltage Vt , and width W are constants for a given device. As shown in Fig. 10.21, if the Vgs of the input pair is chosen to be sufficiently high to approach velocity saturation, very good linearity can be obtained from the input transconductance stage (Fig. 10.22). For this reason, inductive degeneration is not needed, which saves die area. A potential drawback is that the bias current can be high if a relatively large W/L ratio is used to keep the noise low. A supply voltage of 1.8 V is used for the mixer to ensure adequate output headroom for the output voltage swing. Reliability considerations are satisfied by appropriate biasing of the transistors. The output common mode is set to Vref using a feedback loop with PMOS current sources at the output, as shown in Fig. 10.20. 8.0 7.0 gm in milli siemens

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6.0 5.0 W/L = 4(0.9/0.12) W/L = 12(0.9/0.12)

4.0 3.0 2.0 1.0 0.0 0.4

0.5

0.9 1 1.1 0.6 0.7 0.8 Gate to Source voltage (Vgs) in V

1.2

1.3

FIGURE 10.22 gm vs. Vgs curves for short-channel MOS, showing the linear transconductance obtained by choosing a high Vgs value.

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303

The mixer achieves a voltage gain of 7 dB with an IIP3 of 0 dBVrms (+13√ dBm for a 50- reference system). The input referred noise of the mixer is 5 nV/ Hz, which contributes less than 0.25 dB to the input referred NF of the overall front end. 10.6.3

LO Divider and Quadrature Generation

The divide-by-2 circuit for the LO uses latches based on source-coupled logic with a VDD of 1.4 V. Differential outputs of an integrated VCO (voltage-controlled oscillator) are used to provide clocks for the dividers (CK P, CK N in Fig. 10.23). Q P, Q N, I P, and I N are frequency-divided quadrature output signals. A buffer driver is used at the output of the divider to provide fast-edged clocks to the mixer switches. The layout is carefully optimized to minimize interconnected parasitics to ensure fast toggling of the mixer switches and to guarantee a 50% duty cycle. 10.6.4

Measurement Results

Table 10.4 shows the measured performance of an RF front end. Tables 10.5 and 10.6 show the IIP3 and IIP2 performance of the RF front end for various critical combinations of cellular and spurious blockers. In this case the results are shown for DCS band transmitter leakage (the closest GSM band to GPS) interacting with any spurious tones that will cause the intermodulation product to fall in-band. For out-of-band IP3 cases of interest, the intermodulating blockers are not of equal power. In such cases the power of the blocker closer to the signal wanted has a stronger impact

FIGURE 10.23

Frequency divider and quadrature generation circuit.

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TABLE 10.4 Receiver Front-End Performance Summary Parameter

Performance

Frequency Power consumption Voltage gain Noise figure 1-dB compression point In-band IIP3 Die area

1575 MHz 36 mW 38 dB 1.8 dB −31.6 dBm −20.2 dBm 0.65 mm2

TABLE 10.5

IIP3 Performance Summarya

Blocker Location (MHz)

IIP3 (dBm)

1850, 5275 1850, 1712.5 1850, 2125

15.6 −6.2 4.2

input power of −30 dBm is used for an 1850-MHz blocker; an input power of −60 dBm is used for all other blockers.

a An

on the IM3 product. The equation for input IP3 in that case is given by IP3 = PB1 +

PB2 − PIM3 2

(10.10)

where PB1 is the input power of the blocker closer to the wanted signal, PB2 is the input power of the second blocker, and PIM3 is the input-referred IM3 product. The typical power level of the intermodulating blockers for the out-of-band IP3 results to be relevant is noted in Tables 10.5 and 10.6. The NF is measured using a low-noise, high-gain instrumentation amplifier at the output of the mixer, which converts the differential output to single-ended output. TABLE 10.6

IIP2 Performance Summarya

Blocker Location (MHz) 1850, 3425 1850, 275

IIP2 (dBm) 40 27

input power of −30 dBm is used for an 1850-MHz blocker; an input power of −60 dBm is used for all other blockers.

a An

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REFERENCES

TABLE 10.7

Comparison of Recent Publications in RF Front Ends Tech. (nm)

Ref. [12] [19] [32] [29] [30] [28] [21] [4] [13]b Sec. 10.5 Sec. 10.6

305

350 SiGe 130 CMOS 180 SiGe 350 SiGe 180 CMOS 130 CMOS 130 CMOS 90 CMOS 65 CMOS 90 CMOS 90 CMOS

Supply Supply Power Voltage Voltage Current Cons. Gain NF IIP3 Fc (GHz) (V) (mA) (mW) (dB) (dB) (dBm)

IIP2 (dBm)

9 −0.5a 8 −6 10 −2 4.9 −9.8 2.8 −2a 3.9 −9 5.2 −7.5 3.5 −10.5 3.0 −17 2.9 −8 1.8 −20.2

+55 >30 +50 >38.8a >65a +30 +50 +51 n/a +52c +40

2.1 2.1 2.1 2.1 2.1 1.9 1.8 1.9 2.4 1.8 1.6

2.8 2.7–3 1.8 2.7 2.9–5 1.2 1.2 0.75 1.2 1.4/2.4 1.4/1.8

34 35 27 31 35 — — 15 29.3 — —

— — — — — 105 20 — 35.2 75 36

56 — — 96.5 102 50 28.5 31.5 39 37 38

a The

IIP3s and IIP2s reported are out-of-band. It is difficult to compare out-of-band performance with in-band since out-of-band IP3s and IP2s can be several dB higher, depending on the location of the intermodulation blockers and RF selectivity of the RX front end. b Simulated performance only. c The IIP2 reported is a CW IIP2. The corresponding IIP2 with a true W-CDMA TX instead of CW tones would be 62.8 dBm with an adjustment factor of −10.8 dB from (10.3) and the literature [2,14,16].

10.7

RX FRONT-END PERFORMANCE COMPARISON

A performance comparison of various RF front ends published recently with respect to the RF front-end designs shown in Sections 10.5 and 10.6 is provided in Table 10.7. As can be seen, compared to other publications, the receiver front ends discussed in this chapter have the lowest NF while ensuring linearity that is sufficiently high for integration. The technology node for both front ends discussed is 90-nm CMOS, which is the most advanced among the publications, with measured results. Acknowledgments Special thanks to Danielle Griffith, Kah-Mun Low, Fikret Dulger, Yo-Chuol Ho, and Shanthi Bhagavatheeswaran for their support in the design of the ICs.

REFERENCES 1. A. A. Abidi, “Evolution of a software-defined radio receiver’s RF front end,” in Proc. 2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 27–30, June 2006. 2. W. Y. Ali Ahmad, “Effective IM2 estimation for two-tone and WCDMA modulated blockers in zero-IF receivers,” RF Design Mag., 2004.

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3. V. Aparin, G. J. Ballantyne, C. J. Persico, and A. Cicalini, “An integrated LMS adaptive filter of TX leakage for CDMA receiver front ends,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1171–1182, May 2006. 4. M. Brandolini, M. Sosio, and F. Svelto, “A 750 mV fully integrated direct conversion receiver front-end for GSM in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1310–1317, June 2007. 5. H. Darabi, “A blocker filtering technique for wireless receivers,” in Proc. IEEE International Solid-State Circuits Conference (ISSCC’07), pp. 84–85, Feb. 2007. 6. A. Das, R. Hezar, R. Byrd, G. Gomez, and B. Haroun, “A 4th order 86dB CT  ADC with two amplifiers in 90nm CMOS,” in Proc. IEEE International Solid-State Circuits Conference (ISSCC’05), pp. 496–612, Feb. 2005. 7. I. Elahi, K. Muhammad, and P. T. Balsara, “IIP2 and DC offsets in the presence of leakage at LO frequency,” IEEE Trans. Circuits Syst. II, vol. 53, no. 8, pp. 647–651, Aug. 2006. 8. P. Fontaine, A. N. Mohieldin, and A. Bellaouar, “A low-noise low-voltage CT delta sigma modulator with digital compensation of excess loop delay,” in Proc. IEEE International Solid-State Circuits Conference (ISSCC’05), pp. 498–613, Feb. 2005. 9. R. Gharpurey and S. Ayazian, “Feedforward interference cancellation in narrowband receivers,” in 2006 IEEE Dallas/CAS Workshop, pp. 67–70, Oct. 2006. 10. R. Gharpurey, N. Yanduru, F. Dantoni, P. Litmanen, G. Sirna, T. Mayhugh, C. Lin, I. Deng, P. Fontaine, and F. Lin, “A direct-conversion receiver for the 3G WCDMA standard,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 556–560, Mar. 2003. 11. S. Ghavami and V. T. Vakili, “Blind SNR estimation on WCDMA system with unequal power signals and without any prior knowledge,” in 16th IST Mobile and Wireless Communications Summit 2007, pp. 1–5, July 2007. 12. D. Kaczman, C. Dozier, N. Godambe, M. Shah, H. Guimaraes, M. Rachedine, M. Alam, Lu Han, W. Shepherd, D. Cashen, J. Ganger, K. Couglar, B. Getka, E. Brotkowski, D. Wong, and D. Hayes, “A tri-band (2100/1900/800 MHz) single-chip cellular transceiver for WCDMA/HSDPA,” in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 281–284, June 2005. 13. J. Kaukovuori, J. Ryynanen, and K. Halonen, “A direct-conversion RF front-end in a 65-nm CMOS,” in Proc. Norchip Conference, pp. 235–238, Nov. 2006. 14. M. S. Khan and N. Yanduru, “Analysis of self mixing of transmitter interference in WCDMA receivers,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS’06), 2006. 15. M. S. Khan and N. Yanduru, “Analysis of signal distortion due to third order non-linearity in WCDMA receivers,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS’06), 2006. 16. M. S. Khan and N. Yanduru, “Analysis and measurement of self mixing of transmitter leakage in WCDMA receivers,” in Proc. IEEE Radio and Wireless Symposium (RWS’07), pp. 361–364, Jan. 2007. 17. M. S. Khan and N. Yanduru, “Signal distortion due to spectral re-growth of adjacent channel interferers in WCDMA receivers,” in Proc. IEEE Radio and Wireless Symposium (RWS’07) pp. 559–562, Jan. 2007. 18. M. S. Khan and N. K. Yanduru, “Closed form equations for inter-modulation distortion parameters in WCDMA receiver validated through measurements,” in Proc. IEEE Dallas Circuits and Systems (DCAS’07), pp. 1–4, Nov. 2007.

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19. R. Koller, T. Ruhlicke, D. Pimingsdorfer, and B. Adler, “A single-chip 0.13µm CMOS UMTS W-CDMA Multi-band Transceiver,” in Proc. 2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 187–190, June 2006. 20. W. B. Kuhn, N. K. Yanduru, and A. S. Wyszynski, “Q-enhanced LC bandpass filters for integrated wireless applications,” IEEE Trans. Microwave Theory Tech., vol. 46, no. 12, pp. 2577–2586, Dec. 1998. 21. A. Liscidini, M. Brandolini, D. Sanzogni, and R. Castello, “A 0.13µm CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 981–989, Apr. 2006. 22. P. Litmanen and A. Bellaouar, “Single-to-differential low noise amplifier,” U.S. Patent 6,366,171, Apr. 2002. 23. D. Manstretta, M. Brandolini, and F. Svelto, “Second-order intermodulation mechanisms in CMOS down converters,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 394–406, Mar. 2003. 24. S. K. Mohammed and N. K. Yanduru, “Third order non linear distortion from modulated blockers in WCDMA Receivers,” in Proc. 49th IEEE International Midwest Symposium on Circuits and Systems (MWCAS’06), pp. 473–476, Aug. 2006. 25. K. Muhammad, Y.-C. Ho, T. L. Mayhugh, C.-M. Hung, T. Jung, I. Elahi, C. Lin, I. Deng, C. Fernando, J. L. Wallberg, S. K. Vemulapalli, S. Larson, T. Murphy, D. Leipold, P. Cruise, J. Jaehnig, M.-C. Lee, R. B. Staszewski, R. Staszewski, and K. Maggio, “The first fully integrated quad-band GSM/GPRS receiver in a 90-nm digital CMOS process,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1772–1783, Aug. 2006. 26. C. T.-C. Nguyen, “RF MEMS in wireless architectures,” in Proc. Design Automation Conference (DAC), pp. 416–420, June 2005. 27. A. Safarian, A. Shameli, A. Rofougaran, M. Rofougaran, and F. De Flaviis, “Integrated blocker filtering RF front ends,” in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 13–16, June 2007. 28. P. Sivonen, J. Tervaluoto, N. Mikkola, and A. Parssinen, “A 1.2-V RF front-end with onchip VCO for PCS 1900 direct conversion receiver in 0.13µm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 384–394, Feb. 2006. 29. M. Tamura, T. Nakayama, Y. Hino, A. Yoshizawa, and K. Takagi, “A fully integrated inter-stage-bandpass-filter-less direct-conversion receiver for W-CDMA,” in Proc. 2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 269–272, June 2005. 30. B. Tenbroek, J. Strange, D. Nalbantis, C. Jones, P. Fowers, S. Brett, C. Beghein, and F. Beffa, “Single-chip tri-band WCDMA/HSDPA transceiver without external SAW filters and with integrated TX power control,” in Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pp. 202–203, Feb. 2008. 31. Third-Generation Partnership Project (3GPP), TS 25.101 UE Radio Transmission and Reception (FDD), vol. 3.0.1, 2000. 32. H. Tomiyama, C. Nishi, N. Ozawa, Y. Kamikubo, H. Honda, H. Fujita, Y. Kondo, H. Iizuka, and T. Takahashi, “A low voltage (1.8V) operation triple band WCDMA transceiver IC,” in Proc. 2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 165–168, June 2006. 33. V. D. Torre, M. Conta, R. Chokkalingam, G. Cusmai, P. Rossi, and F. Svelto, “A 20mW 3.24mm2 fully integrated GPS radio for cell-phones,” in Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pp. 1902–1911, Feb. 2006.

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34. Digital Cellular Communication System (Phase 2), Radio Transmission and Reception. ETSI 300 910, GSM 05.05, version 8.4.1. European Telecommunications Standards Institute, 1999. 35. N. K. Yanduru, D. Griffith, S. Bhagavatheeswaran, C.-C. Chen, F. Dulger, S.-J. Fang, Y.-C. Ho, and K. M. Low, “A WCDMA, GSM/GPRS/EDGE receiver front end without interstage SAW filter,” in Proc. 2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 19–22, June 2006.

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Digitally Enhanced Alternate Path Linearization of RF Receivers EDWARD A. KEEHR and ALI HAJIMIRI California Institute of Technology, Pasadena, California

11.1

INTRODUCTION

The design of radio-frequency (RF) receivers is fundamentally constrained by the scarcity of gain at the high frequencies at which these circuits must operate. As feedback, a staple design technique at lower frequencies, is difficult to implement at RF due to its bandlimiting nature, signals entering the receiver are exposed to the full brunt of the active-gain device nonidealities. This situation often leads to the presence of self-generated interference, in which signals, desired or otherwise, interact with circuit block nonidealities in such a way that error terms arise and corrupt the signal intended for reception. This interference is sometimes so severe that even increasing the circuit area and power dissipation arbitrarily to reduce the nonidealities is insufficient, and costly off-chip components are required for the receiver to meet specifications. Often, this self-generated interference manifests itself as distortion products due to block nonlinearities, but can also arise due to I /Q mismatch, interstage coupling, or various other mechanisms. Unfortunately, it can also be said that these problems worsen in general as CMOS processes continue to scale. As supply voltages drop, less headroom is available to apply large overdrive bias voltages to devices in critical RF circuit blocks, worsening their linearity and matching properties. In addition, the twin trends of minimizing the size of consumer devices while increasing their functionality place immense pressure on the circuit designer to eliminate the need for off-chip components such as surface acoustic wave (SAW) filters.

11.1.1

Interference Due to Nonlinear Distortion Products: Motivation

In RF receivers, perhaps the most significant contemporaneous self-interference problem is nonlinear distortion, due to the continued and rising popularity of the UMTS Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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Desired Signal

TX Leakage IN Duplexer RX TX

PA Desired Signal

TX Leakage

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CW Blocker Freq. OUT

OUT

LNA IN Blocker Signals

Freq.

FIGURE 11.1

Blocking problem in FDD receivers.

frequency-domain duplex (FDD) standard [1] for 3G communications. UMTS and similar FDD standards typically possess stringent linearity requirements, due to the necessity of having to handle a large, unwanted blocker signal in the presence of transmitter (TX) leakage through the FDD as shown in Fig. 11.1. This situation, defined in the standard specifications [2], sets up an implicit twotone test, which can yield harmonic distortion products that corrupt the signal desired. To meet these requirements, several commercial receivers [3–5] have resorted to the use of interstage SAW filters to attenuate large blocker signals and hence to relax requirements on the integrated-circuit blocks. Recently, several SAW-less UMTS receivers have also been reported, albeit with a somewhat lower out-of-band IIP3 performance [6–8]. It should be noted that IIP3 specifications and achievements vary widely in the literature, as shown in Table 11.1. This variation is due to the fact that the IIP3 specification depends on the receiver achieved noise figure, the peak TX power that must be handled, and the characteristics of the particular duplexer used, as discussed in Section 11.4.1. Although the SAW-less receivers mentioned above meet their respective self-imposed out-of-band IIP3 specifications, it is worthwhile

TABLE 11.1 Reported IIP3 Specification and Performance Comparison Ref.

IIP3 Specification

IIP3 Performance

[4] [5]a [6] [7] [8]

+1.3 dBm −6.1 dBm −10 dBm −8 dBm −5 dBm

+1.6 dBm −0.5 dBm −7.4 dBm −7 dBm −2 dBm

a Measurement

at mixer transconductor input.

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to consider the design of SAW-less receivers with still higher IIP3 in order to permit the use of less stringent, and possibly also less expensive, duplexer blocks.

11.2 11.2.1

ADAPTIVE FEEDFORWARD ERROR CANCELLATION General Concept

Although the prognosis for self-generated interference issues as time progresses is bleak, the nature of the problem yields a plausible solution strategy. Most significantly, the error-generating mechanism is known, at least qualitatively, while at the same time, error-producing signals still exist and are accessible within the system as good approximations of the original receiver input signals. In this case, the error-producing signals within the receiver can be applied to a rough model of the error-generating mechanism in order to generate a reference signal consisting solely of corruptive error. However, the precise model of the error-generating mechanism is never known. Hence, as shown in Fig. 11.2, an adaptive equalization algorithm is employed to subtract the reference signal from the corrupted main receiver path, as it can account for minor uncertainties in the effective alternate path baseband transfer function. In Fig. 11.2, only a dc gain uncertainty is shown for simplicity. In reality, uncertainties

MAIN PATH Ideal Path

Input

Gain Nonideality 1

Out

?

Nonideality 2

Reference Nonideality 1

Adaptive Filter

ALTERNATE PATH 1

Signal Taken From Advantageous Points in Main Path

Reference Nonideality 2

Adaptive Filter

ALTERNATE PATH 2

CLK Q D

FIGURE 11.2

Adaptive feedforward error cancellation concept.

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CLK

w[n]

ALT

Input with Reference Signal

D Q

D Q

D Q

a[n] TAP

TAP

TAP

TAP

µ

Input Corrupted by Version of Reference Signal

MAIN m[n]

FIGURE 11.3

OUT e[n]

Equalizer Output

Least-mean-squares equalization concept.

related to path delay, frequency-dependent gain, and dc offset also exist and must be accounted for by the adaptive equalization scheme. For the remainder of this chapter, this general concept is referred to as adaptive feedforward error cancellation. 11.2.2

LMS as Adaptive Equalization Algorithm

Least mean squares (LMS)–based adaptive equalizers are common choices in powerconstrained applications, due to their simplicity and robustness [9]. The concept behind LMS-based adaptive equalization is depicted in Fig. 11.3. Here, a timevarying finite impulse response (FIR) filter is utilized to modify a reference signal and to subtract it from an incoming signal corrupted by a version of the same reference signal. The taps of the FIR filter are adjusted based on the instantaneous correlation estimate between the equalizer output and the reference signal. That is, if there is any signal correlated with the reference signal in the equalizer output, each tap is adjusted on average in a direction so as to reduce the reference signal content in the output. If the equalizer is designed properly, the filter taps will converge close to a solution that yields the minimum mean-squared error at the output, but will exhibit a small excess deviation around that solution. In the case of Fig. 11.2, single-tap LMS adaptive filters are used as part of an adaptive equalizer that removes multiple types of error. 11.2.3

Advantages of Adaptive Feedforward Error Cancellation

As this technique focuses on cancellation of the error itself and not the error producers, it permits a relatively narrowband alternate path. That is, although large, undesired, error-producing signals may occur over a wide frequency range, the relevant error terms that they produce are restricted to a much smaller bandwidth, equal to that of the desired signal. Hence, most of the circuitry in the alternate path can be made directly analogous to parallel circuitry in the main path. These circuits, processing solely error terms, operate with a lower dynamic range than that of their original receiver counterparts, as the corruptive error-to-noise ratio is in general much less

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than the error producer-to-noise ratio in the main path. Also, if the LMS algorithm is used to perform the adaptive equalization, multiple LMS loops in parallel can be used to cancel different interference signals, as depicted in Fig. 11.2 [10]. Furthermore, in the event that the self-generated interference of interest is due to large, undesired blocker signals, the power dissipation of an alternate path can be reduced further by powering it on only when needed, as most receivers need to operate in the presence of strong interferers for only a small fraction of the time. Finally, the adaptive nature of the equalizer permits tracking of rapidly changing blocker conditions. The indifference of the adaptive feedforward error cancellation technique to the details of the original receiver can also be exploited to simplify the design of multi-mode receiver terminals intended to work with communication standards dominated by different sources of error. For example, a frequency-band-adjustable down-converter could be designed using simple canonical block architectures. If one particular standard then requires a much higher IIP2 than the base receiver can provide, an IM2error-canceling alternate path can be enabled. Similarly, if high IIP3 is required, an IM3-error-canceling alternate path can be turned on. 11.2.4

Prior Art

In recent years, adaptive feedforward error cancellation has been proposed for use in RF receivers in order to remove IM2 distortion and dc offset [10], IM3 distortion [11,12], and signal interference resulting from quadrature I /Q mismatch in IF receiver circuitry [13,14], and was described as a general concept in the context of canceling error resulting from quadrature I /Q mismatch [14]. However, the work related to nonlinear distortion cancellation in the current literature contains at most descriptions of high-level studies implemented with discrete RF components. Furthermore, the work described in [11,12] focused on adaptive feedforward loops existing entirely at digital baseband. In RF receivers, this presents an accessibility problem in which out-of-band IM3-producing signals at frequencies far away from the receiver LO frequency are attenuated to near or below the thermal noise floor after down-conversion to baseband. In this case, the baseband IM3-producing signals are unsuitable for the generation of reference error signals. The work described in the following sections of this chapter addresses both of these issues. An adaptive feedforward error-correcting loop extending from analog RF to digital baseband is introduced to circumvent the accessibility problem, and a specification-compliant custom-designed RF front end is fabricated and tested to assess the suitability of the technique for modern communication devices.

11.3

ARCHITECTURAL CONCEPTS

The general concept behind the adaptive feedforward IM3 cancellation scheme introduced in this chapter is shown in Fig. 11.4. In this figure, a nonlinear main receiver path is subject to two large blockers such that the desired signal is overwhelmed by the self-generated IM3 interference products. The figure reflects the fact that the

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2

| |

4

6

| |

Freq.

Freq.

Freq.

MAIN PATH 1

Input

2 LNA

4

6

gm

Output LO Adaptive Filter Complex Adaptive Equalizer

(•)3 5

3

ALTERNATE PATH | |

1

| |

3

Freq.

| |

Freq.

5

Freq.

FIGURE 11.4 Adaptive feedforward IM3 distortion cancellation: proposed receiver system.

UMTS out-of-band blocking requirement [2] is an implicit two-tone test, with one of the “tones” being the modulated TX output leakage through the antenna duplexer. Reference IM3 products are generated at RF by a cubic term generator, while choosing the LO frequency of the alternate feedforward path mixer to be the same as that of the main path guarantees that the proper set of IM3 products are down-converted to baseband frequencies. In this fashion, a reference IM3 signal can be generated for any specified RF blocker that can produce significant IM3 distortion interference in the receiver, regardless of the blocker frequency offset from the RX LO frequency. Baseband postfiltering attenuates to negligible levels unwanted IM3 products in the alternate feedforward path such that the adaptive equalizer converges based only on the statistics of the IM3 products corrupting the desired signal at baseband. In this fashion, the equalized IM3 products of the alternate feedforward path can be subtracted directly from the main path, leaving only the desired RX signal. Note that this technique is not limited to a two-tone test but also removes IM3 products resulting from a three-tone test. Furthermore, this technique does not require prior knowledge of one or more of the blocker frequencies, as do techniques that rely on the cancellation of TX leakage to meet the UMTS linearity specifications [15,16]. Although both IM2 and IM3 products can be concurrently canceled by parallel LMS adaptive filters, it was decided in this project to leverage recent work [17,18] in order to perform local IIP2 improvements so as to avoid adding additional analog-to-digital converters (ADCs) to the system to pass reference IM2 products. 11.3.1

Choice of Feedforward Loop

The adaptive feedforward error cancellation technique described in this chapter differs significantly from those presented in [11] and [12] in that reference IM3 products

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are generated at analog RF rather than at digital baseband. That is, the alternate feedforward path loop is a mixed-mode system that stretches back to almost equal the length of the main receiver path. It can be shown with trigonometric identities that the resulting down-converted IM3 products are the same as those that would have been produced by I and Q baseband cubing circuits. IM3 generation in the continuous-time domain as performed here is the preferred method in an integrated down conversion receiver since it permits the use of relatively narrowband postfilters and ADCs, such as those based on sigma-delta modulators. For the architectures in [11] and [12] to cancel IM3 products for UMTS, the ADCs must pass the full spectrum of potential problematic blockers (1670 to 1850 MHz, 1920 to 1980 MHz, 2015 to 2075 MHz [3]) and would require at least six Nyquist ADCs with FS > 60 MHz, rendering this strategy unattractive from a power dissipation perspective. Given that IM3 generation is therefore to be performed in the analog domain, it should additionally be performed at RF after the LNA, where the blocker magnitudes are at their largest point in the receiver. 11.3.2

Fixed and Adaptive Equalization

It can turn out in the design of the alternate feedforward path system that the linear time-invariant (LTI) baseband path difference is known to a large degree of certainty. Adaptive equalization of this difference is computationally inefficient. The main reason for this is twofold. First, most analog path differences are infinite impulse response (IIR) in nature, while adaptive equalization algorithms such as those in the LMS family are FIR. Second, even if the path difference were FIR, the LMS-based adaptive equalizer requires two multipliers per filter tap, as opposed to just one for a fixed FIR filter. Hence, in the finalized version of the receiver described in this chapter, the known difference between the main and alternate path transfer functions is equalized by fixed real three-multiplier IIR filters. The remaining difference between the two paths is a complex dc gain and a small random mismatch in the baseband transfer function. This difference is broadband in the frequency domain and by the duality principle will correspond to a small number of taps required in the adaptive equalizer. In this project, the normalized-LMS (NLMS) algorithm is utilized, as its convergence speed is in general superior to that of canonical LMS [19–21]. The NLMS algorithm differs from the canonical LMS algorithm in that the tap update variable is normalized by the magnitude of the incoming reference signal. 11.3.3

DC Offset in Direct-Conversion Receivers

As is well known, direct-conversion receivers are susceptible to large dc offsets at baseband [22,23]. This presents an issue with regard to the adaptive filter in that if both dc offset and IM3 signal are present on both main and alternate paths, the adaptive equalizer will attempt to equalize both signals. However, because the dc offset is large and uncorrelated with the path mismatch at low frequencies, the optimal transfer function of the adaptive equalizer will have a large impulse at dc in the frequency domain. In the time domain, this corresponds to a very large number of adaptive filter taps, which will consume inordinate amounts of power and degrade the performance of the equalizer [9].

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A common solution to the dc offset issue in UMTS receivers is to use highpass filtering at baseband [4,5,24], with a cutoff frequency no greater than 10 kHz [24]. In this work, highpass filtering at 10 kHz is performed in the digital domain for both main and alternate paths to remove the dc offset of the complete analog portion of the receiver, including the ADC. The problem with doing this in either domain, however, is that when the alternate path powers on, the dc offset of the mixer appears as a step to the alternate path highpass filter. The resulting step response takes three or four HPF time constants to settle below the error floor, preventing convergence of the adaptive filter during this time. This is a problem because the cutoff frequency of the HPF is very low. Another option is to adaptively remove dc offset as part of the equalizer algorithm [10,25]. However, it can be shown that this technique effectively implements a highpass filter and would have the same settlingtime issue. The solution utilized in this work to remove this startup transient is to retain the highpass filters mentioned earlier, but also to power-on the alternate path and measure the dc offset in the digital domain in the absence of IM3 products being passed through the alternate path. This measurement is then immediately subtracted from the incoming signal to remove the dc offset. Since the only signals present at this time are dc offset and a small degree of noise, these operations can be performed relatively quickly (in a few micro seconds) by a simple averaging circuit immediately prior to enabling the full alternate path. The complete scheme is depicted in Fig. 11.5. 11.3.4

Sources of Error in Alternate Feedforward Path

The alternate feedforward path of the proposed receiver architecture suffers from some of the same error sources as do traditional receiver designs, but in often different ways and to different degrees. 11.3.4.1 Linear Term Feedthrough The first requirement of the alternate path is that it must heavily attenuate the incoming signal desired (i.e., linear term

1 2

3

Time(s)

3 (•)

Mixer

Analog Filter

3

LNA

FIGURE 11.5 correction.

3

1 2

1

3

1 2

Time(s)

Time(s)

ADC

Mixer

IN

1 2

3

3

2 DC Offset Trimming

Analog Filter

Adaptive Filter

HPF 0

ADC

Time(s)

Time(s)

Frequency

Out[n] HPF

Dc offset transient during alternate feedforward path power on with dc offset

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feedthrough) with respect to the IM3 products. This is depicted visually at point 3 of Fig. 11.4. The reason for this is that any desired signal at the reference input of the equalizer will be treated as an error by the adaptive algorithm. As the algorithm functions so as to minimize mean-squared error, it will attempt to strike a balance between eliminating the IM3 products and desired signal, reducing the small-signal gain, IM3 cancellation, or both. 11.3.4.2 IM3-to-Noise Ratio and IM3-to-Error Ratio Common metrics used to quantify the signal processing quality of a circuit block include the signal-to-noise ratio (SNR) and the signal-to-noise-and-distortion ratio (SNDR). However, in the proposed receiver architecture, a principal concern is the quality of signal processing of nonlinear IM3 distortion products. To avoid confusion between these signals and desired receiver signals, a quantity termed INR is introduced which denotes the ratio of IM3 products to in-band noise. Generalizing this metric to other forms of error results in a quantity called the IM3-to-error ratio (IER). The latter metric is most useful in that it can be used to quantify the performance impact of the alternate path on the main path receiver. Taking the output of the alternate feedforward path as the output of the adaptive filter of Fig. 11.4, the adaptive equalizer enforces the equality of the IM3 products at the outputs of the main and alternate paths (11.1). Although this equality is never perfectly achieved, any such deviation can be thought of as contributing to the alternate path IER. Imain = Ialt

(11.1)

After cancellation of the IM3 products, the equalizer output contains error due to thermal noise, higher-order IM products, and several other effects. As depicted in (11.2), this error can be attributed to separate sources in the main and alternate paths. In (11.2) it is assumed that this error is uncorrelated to good approximation: 2 2 2 = E main + E alt E tot

(11.2)

Using (11.1) and (11.2), it can be seen that the following relationship holds:
2 E tot

=

2 E main

1+



IERmain IERalt

2  (11.3)

With the relation (11.3), the total receiver error can be input-referred using the main path small-signal gain. This error can then be compared with the receiver specifications, which are typically also input referred. Since the total allowed error, main path IM3 products, and other main path error terms are known prior to consideration of the alternate path, the IER required for the alternate path can be determined by (11.3) for a given blocking condition. As the power of the IM3-producing blocker signals are varied, the IER quantities of the two paths roughly track. Using (11.3), it can be seen that this implies that the maximum total error occurs when the main path error

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is at its maximum. This condition occurs under the peak, or worst-case, blocking condition. Hence, the performance of the alternate path circuitry is specified at this point. Knowledge of the main path error and IER under peak blocking conditions, denoted IERmain,pk , along with the receiver error specifications, sets a requirement on the alternate path IER under peak blocking, denoted IERalt,pk . Provided that this requirement is met, the receiver error requirement will be met for all other blocking 2 will decrease and IERmain /IERalt will conditions, as for smaller blocker levels E main remain roughly constant. 11.3.4.3 Higher-Order Nonlinear Terms The large-signal transfer functions of real-world devices are characterized by Taylor series with an infinite number of terms. Assuming that the Taylor series coefficients in both the main and alternate paths are the same for all possible sets of input blocker frequencies, all higher-order nonlinear interference terms will cancel under equalization. However, this goal is all but impossible to guarantee in design. As the ratio of higher-order nonlinear terms to IM3 products is largest under peak blocking conditions, it is best to guarantee that the IERpk due to these higher-order terms is significantly greater than the total IERpk requirement in both paths. Cutting the IER performance close in this case is a bet on the accuracy of the nonlinear device models, and is not recommended. This requirement can be verified at the block level with a harmonic balance simulation, varying the number of calculated harmonics in order to isolate the magnitude of higher-order terms that fall at the same frequency as the IM3 products. 11.3.4.4 Quadrature Mismatch and LMS Equalization Quadrature mismatch is typically not a major issue in meeting the sensitivity requirements of direct-conversion receivers, as the image signal is merely the quadrature component of the desired signal and is hence on the same order of magnitude. In the receiver presented in this chapter, however, quadrature mismatch holds the same position of importance as it does in image-reject superheterodyne architectures, as the interference is typically at least an order of magnitude larger than the desired signal. This significance becomes evident after an examination of the complex LMS algorithm. The operation of the two equalizers in their canonical complex form is described by (11.4), with bold symbols denoting column vector quantities and the italicized portions corresponding to the NLMS algorithm alone. The variables in (11.4) correspond to the signal variables in Fig. 11.3. For adaptive feedforward error-corrected receivers in which the alternate path extends back past the mixer and in which the multistage cubic term generator proposed in Section 11.4.2 is used, the complex form of the LMS-based algorithm is required, as it is impossible to guarantee a fixed phase relationship between the main and alternate paths, due to the nonconstant nature of the cubic term generator interstage frequency response. e[n] = m[n] − wH [n]a[n],

w[n + 1] = w[n] + µe[n]a[n], ˜

µ˜ =

µ a[n]2 (11.4)

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When expanded into a physical hardware implementation, (11.4) takes the following form: µ ||aI [n]||2 + ||aQ [n]||2

µ˜ =

(11.5)

e I [n] = m I [n] − wTI [n]aI [n] + wTQ [n]aQ [n]

(11.6)

e Q [n] = m Q [n] − wTQ [n]aI [n] − wTI [n]aQ [n]

(11.7)

wI [n + 1] = wI [n] + µ[e ˜ I [n]aI [n] + e Q [n]aQ [n]]

(11.8)

wQ [n + 1] = wQ [n] + µ[e ˜ Q [n]aI [n] − e I [n]aQ [n]]

(11.9)

As can be seen from a one-tap implementation of (11.5)–(11.9), the signals in the main and alternate paths must be related by a Givens rotation (11.10) for a solution to exist to the complex filter tap such that complete equalization is achieved: 

    w I [n] −w Q [n] a I [n] m I [n] = w I [n] m Q [n] w Q [n] a Q [n]

(11.10)

This is the case in Fig. 11.6(a), which shows a vector representation of IM3 products in the main and alternate paths. After the complex equalizer applies the proper Givens rotation to the alternate path signal, subtraction yields complete cancellation, as in Fig. 11.6(b). However, if as in Fig. 11.6(c) phase and rotational mismatch exist between the two paths, clearly their respective signal vectors are not related by a Givens rotation. In this case, complete cancellation cannot be achieved, limiting the xs

(a)

xs Q

(b)

Q

I

I xc xs

(c)

xc xs

(d)

Q

Q

I xc

I

xc

Main Path Instantaneous Signal Vector Alternate Path Instantaneous Signal Vector

FIGURE 11.6 Insufficiency of complex LMS/NLMS in the presence of alternate and main path signal vector mismatches.

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0

R

45

15

R

45 40

IER(dB)

40

IER(dB)

35 30 25 1

2

a+

3

4

4

m (de gree 5 s)

6 6

5

a- m

3

2

35 30 25 1

1

a+

) rees (deg

2

3

m (de gree 5 s)

6 6

3

2

1

) rees 5 (deg m a 4

4

45

R

45 40

IER(dB)

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35 30 25 1

a+

FIGURE 11.7

2

3

m (de 4 5 gree s)

4

6 6

3

(de a- m

5

2

1

s) gree

IER vs. rotational mismatch and difference in phase mismatch.

IER of the adaptive equalization. This effect is quantified in [26] and Fig. 11.7. It is evident that even in the absence of I /Q gain mismatch, small phase mismatches can severely limit the performance of the adaptive equalization. Note that in Fig. 11.7, φ R is equal to the rotational mismatch between the main and alternate paths, while φ M and φ A are the quadrature phase mismatches in the main and alternate paths, respectively.

11.4 ALTERNATE FEEDFORWARD PATH BLOCK DESIGN CONSIDERATIONS Based on the high-level architectural choices and concepts presented in Section 11.3, it is now possible to approach the block-level design of the alternate path quantitatively. The first step in this task is to determine the performance of the main path, namely, of IERmain,pk . At this point in the chapter and in the design process, a rough idea of the main receiver path performance is sufficient to move forward. 11.4.1

Translation of Specification to System Requirements

11.4.1.1 Main Path To determine the worst-case “two-tone” blocker scenario seen by the receiver circuitry, the UMTS blocker specification [2] must be used in conjunction with the frequency response of the duplexer shown in Fig. 11.1. From

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Blocker Levels at: Antenna (dBm) LNA (dBm) Mixer (dBV)

1.8

1.9

Tx Band

30 20 10 0 -10 -20 -30 -40 -50 -60 -70 1.7

Rx Band

ALTERNATE FEEDFORWARD PATH BLOCKDESIGN CONSIDERATIONS

Magnitude (dBm/dBV)

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2.1

2.2

2.3

Frequency (GHz)

FIGURE 11.8

Expected UMTS blocker profile at various points in the receiver.

Fig. 11.8 it can be seen that for the duplexer described in [27], the largest IM3 products occur when f TX = 1.98 GHz, f CW = 2.05 GHz, and f RX = 2.12 GHz. In this case, the blocker powers are PTX = +28 dBm and PCW = −30 dBm at the antenna and PTX = −26 dBm and PCW = −34 dBm at the LNA input. Interestingly, in this case the worst-case blocking scenario does not occur over the band in which the specified CW blocker is −15 dBm. According to [28], the UMTS specifications impose an analog requirement of NFant,max = 9 dB at the antenna. A more general definition of NF, denoted error figure (EF), is adopted to encompass other forms of error, including distortion products. Although potentially cumbersome at this point, the EF quantity will later help relate better known receiver specifications to IERalt,pk . The UMTS specification allows EF = NF + 3 dB under blocking conditions. In other words, EFant,max = 12 dB. Given the insertion loss of the duplexer [27] L dup = 1.8 dB and that NFant = L dup + NFRX , it is easily computed that NFRX,max = 7.2 dB and EFRX,max = 10.2 dB at the LNA input. For UMTS, the noise due to the 50- source resistance is kT B = −108 dBm/3.84 MHz at the LNA input. Denoting all quantities as LNA input-referred, this implies that after removing the source noise, the maximum allowed receiver noise power is NRX,max = −101.7 dBm/3.84 MHz. Assuming that the error under worst-case blocking is dominated by thermal noise and IM3 distortion, the error figure limit implies that the rms sum of IRX,max and NRX,max is −98.2 dBm/3.84 MHz, where IRX,max is the maximum allowed IM3 distortion product power. It follows that IRX,max = −100.8 dBm/3.84 MHz. Using these values in (11.11) yields IIP3RX,min = +3.4 dBm. IIP3RX,min = 12 (2PCW + PTX − IRX,max )

(11.11)

The problem with this requirement is that it is higher than typical attainable values for SAW-less receivers in the absence of special enhancements (at the time of this research). For example, typical values for IIP3mixer range from +8 to +12 dBm [15].

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For the initial design in this work, the simulated values for the LNA gain G LNA and IIP3LNA are 17 dB and +6 dBm, respectively. Recalling the IIP3 relation (11.12) from [23] as used in [15], such design values yield IIP3RX = −9.1 dBm for IIP3mixer = +8 dBm.  IIP3RX =

1 G LNA + IIP3LNA IIP3mixer

−1 (11.12)

Clearly, a significant discrepancy arises and some sort of additional IIP3 enhancement is required to meet the input-referred error specification. The proposed adaptive feedforward error-canceling loop is therefore added to the receiver. In order to begin a quantitative design of the alternate path, however, it is first necessary to determine IERmain,pk . Using (11.11), the main path IM3 product magnitude under peak blocker conditions Imain,pk is equal to −75.8 dBm/3.84 MHz. Adding 2 dB of margin to the NF requirements and assuming that EFRX,max = NFRX,max + 2 dB (allowing a 1-dB margin for error due to the alternate path) the maximum error, including 50  of source noise but not IM3 products, referred to the main path LNA input is E main,pk = −100.8 dBm. Hence, IERmain,pk = 25 dB. This number can now be used to determine a target design value for IERalt,pk . 11.4.1.2 Alternate Path From IERmain,pk and the allotted 1-dB error margin for the alternate path enhancement, the requirement on IERalt,pk can be determined as follows. To obtain EFRX,max , all error is referred to the output of the equalizer:  EFRX,max (dB) = 10 log10

2 2 + E alt,pk E main,pk

 (11.13)

G 2main kT B

where G main represents the small-signal gain of the main path. Recalling that the adaptive equalizer forces Imain,pk = Ialt,pk , substitution yields  EFRX,max (dB) = 10 log10

2 E main,pk

G 2main kT B



 + 10 log10 1 +

IER2main,pk



IER2alt,pk

(11.14)

The second term in (11.14) represents the excess error figure due to the operation of the alternate path. Given the design numbers in Section 11.4.1.1, IERalt,pk > 31 dB. For simplicity, this error requirement is split equally between the cubic term generator and the remainder of the alternate path, yielding IERcub,pk > 34 dB. 11.4.2

Alternate Path Cubic Term Generator Concepts and Design

11.4.2.1 Prior Art in Cubic Term Generators Cubic term generators, or expansions thereof, have been reported in the literature as circuits to be used in the predistortion of nonlinear power amplifiers. Many early cubic predistortion circuits utilized the crossover distortion characteristic of back-to-back diodes [29,30], while an active

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implementation of such a circuit with a higher cubing gain using BJT devices was reported in [31]. However, such circuit topologies are not compatible with typical CMOS processes. Ideally, the IM3 products in the alternate path would be produced by the same mechanism as they are in the main path: namely, by the third-order nonlinearity of the MOSFET device. Recently, CMOS cubic predistortion circuits using this design approach have been presented as well [32,33]. Another class of circuits associated with this application is known collectively as polynomial predistorters. Such circuits realize polynomial predistortion functions by using a cascade of multiplier operations on the distortion-producing power amplifier input. Polynomial predistortion circuits using cascaded Gilbert cell multipliers have been implemented with discrete components [34] and in BiCMOS [35] and CMOS [36] processes. The authors of [37] propose the use of multipliers modified from those described in [38] based on a sum-and-difference squaring technique that utilizes the square-law dependence of the MOS device transconductance, but to our knowledge have not yet reported on a complete predistortion circuit. 11.4.2.2 Cubic Term Generator Block Design Strategy The principal design requirement of the receiver feedforward loop cubic term generator is the INR, as the design strategy mentioned in Section 11.3.4.3 calls for higher-order nonlinear terms to be negligible with respect to the total error floor under blocking conditions. In this regard, the use of a cubic term generator based on the third-order Taylor series coefficient of the MOS device is unattractive for two reasons. First, as the MOS device transconductance is fundamentally a square-law operation, the third-order Taylor series coefficient is relatively weak. Second, the cubing operation heavily attenuates the IM3 output signal with respect to the noise of the IM3-producing devices. Using a cubic term generator along the lines of a polynomial predistortion circuit represents a superior approach when designing for INR, as the initial nonlinear distortion products are only attenuated with respect to the noise of the nonlinear devices as the square of the input signal, not the cube. Furthermore, as the initial operation of a polynomial predistortion is even-order, there exists the possibility of using circuits that exploit the relatively strong second-order Taylor series coefficient of the MOS device transconductance. Thus, the block diagram of a cubic term generator for RF receivers should appear as in Fig. 11.9, where the cubic operation is broken up into a squaring and a multiplication. However, the design of an optimal interstage circuit architecture differs between multistage cubic term generators for receivers and polynomial predistorters [44]. Polynomial predistorters need only to retain the baseband envelope information of the distortion-producing signal because the distortion-producing signal and the

IN (•)

FIGURE 11.9

2

OUT Gain

Multistage cubic term generator concept.

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desired output signal are the same. The final multiplication in the predistorter thus up-converts the baseband signal information to the frequency of the desired signal. In RF receiver front ends limited by out-of-band blocking requirements, however, the distortion-producing and desired signals are different and do not coincide in frequency. It can be shown [44] that the bandwidth of the receiver interstage circuitry need only pass IM2 products over the range of two-tone beat frequencies specified to recreate the proper IM3 products at the output. For UMTS region 1 this range is from 65 to 250 MHz, which is much less than the 4.15-GHz bandwidth required to retain all of the IM2 products generated by the initial squaring circuit, as depicted in Fig. 11.10. Since this required bandwidth is small, large amounts of interstage gain can be realized for a relatively small amount of power. This is extremely advantageous in that a large gain can be applied prior to the final multiplication at the expense of signal bandwidth, reducing the effective noise contribution of this and subsequent stages. It can similarly be shown that in a three-tone test, signal around only one of the two beat frequencies is required to be retained. The bandlimited transfer function also has a dramatic effect on the phase response applied to the signal at the beat frequency, as shown in Fig. 11.11. The nonconstant nature of this response requires a complex adaptive equalization algorithm, as the rotational phase difference between the main and alternate paths is never known a priori. Using the interstage circuitry to filter out unnecessary signals becomes more important as the difference in peak receiver blocker amplitudes increases. In this case, IM2 products near dc are considerably greater than those at beat frequencies. Although these large dc signals do not contribute to the output IM3 products, they can dictate the compression point of the circuit and produce higher-order nonlinear terms. Hence, the optimal receiver cubic term generator interstage circuitry will remove them from the system via filtering as early as possible.

MULTIPLICATION #1 – IM2 PRODUCTS GENERATED | | INTERSTAGE BANDWIDTH

fLO

MULTIPLICATION #2 – IM3 PRODUCTS GENERATED

Frequency

| | INTERSTAGE BANDWIDTH

2 1

Frequency

fLO FIGURE 11.10

Multistage cubic term generator circuit frequency-domain operation.

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Phase Response (Degrees)

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-20 -30 -40 -50 -60 -70 80

100 120 140 160 180 200 220 240 Two-Tone Beat Frequency (MHz)

FIGURE 11.11 Simulated phase response of a cubic term generator circuit with respect to two-tone beat frequency.

11.4.2.3 Implementation of Multi-Stage Receiver Cubic Term Generator The architecture of Fig. 11.9 with the interstage topology proposed in the preceding paragraph is realized in the circuit schematic of Fig. 11.12. The circuit of Fig. 11.12 is built around the canonical MOS squaring transconductor, located at the lower left of the schematic. This circuit exploits the strong second-order nonlinearity of

VDD

VIN +

A A VIN -

VOUT +

VOUT -

GND VDD

VIN +

VIN -

VIN +

VIN -

GND

= Resistor Connected to DC Bias Voltage

FIGURE 11.12

Implemented multistage cubic term generator circuit schematic.

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the MOS device and avoids the generation of higher-order IM products associated with the nonlinearity of the current commutating devices of a Gilbert cell–based squaring circuit. It also represents a simpler approach than that described in [37], using considerably fewer noise-producing transistors. As the MOS squaring circuit produces a single-ended output, it must be followed by an active balun to recast the signal differentially. One potential issue with this scheme is that the squaring circuit passes common-mode signal directly. If the balun negative terminal were grounded, the common-mode signal would be recast differentially as well and would propagate through the remainder of the circuit. To provide some measure of commonmode rejection, a dummy squaring circuit is added to the negative terminal of the balun. With the gate terminals of the dummy squaring circuit tied together, this circuit only passes common-mode signal. Hence, the common-mode input signal is attenuated by the common-mode rejection ratio (CMRR) of the balun and subsequent gain circuits. The final multiplication of the cubing circuit is performed by a Gilbert cell multiplier. Although the LO port of this block is highly nonlinear, it can be made less so at the expense of gain by increasing the multiplying device overdrive voltages. The lost gain can then be made up earlier in the circuit. The circuit as implemented is somewhat power-inefficient, due to the voltage output at RF. This was done for testing purposes, but in a commercial implementation the IM3 reference signal would be passed to a mixer switching pair solely in the current mode. Note that in this architecture, linear term rejection will be limited only by device mismatch and coupling, so it is expected that this effect will be negligible. Furthermore, the circuit is verified in simulation to produce higher-order nonlinear terms at levels significantly below the required alternate path error floor. 11.4.2.4 Quantitative Theoretical Performance of Multi-Stage Cubic Term Generator It can be shown that if the noise of the multi-stage cubic term generator proposed is dominated by the input stage squaring transconductors and resistors (including those of the dummy stage input), the INR of the circuit is given by

INR =

I D (E sat L)4 A41 A22
 2  M H (ωLO − ωi ) 3 Ai 64kT f BW (Vod + E sat L)3 Vod i=1 H (ωLO − ω1 ) ×

1 2γ (Vod + 2E sat L) +

1 [Vod (Vod R

+ E sat L)]/I D

(11.15)

where the arguments to the expression are detailed in Table 11.2 [44]. This expression assumes that the frequency of blocker 1 (UMTS CW blocker) is closer to the RX LO frequency than the frequency of blocker 2 (a CW signal representing UMTS TX leakage).

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TABLE 11.2 Symbol

Description

Value

T L γ f BW ID I D,tot vod E sat A1

Temperature Nonlinear device length Noise gamma RF noise bandwidth Current in one transconductor device Total circuit current MOS overdrive voltage MOS saturation E-field Differential amplitude of UMTS CW blocker (V) Differential amplitude of UMTS TX blocker (V) Differential amplitude of additional blocker (V)

298 K 0.6 µm 0.55 3.84 MHz 0.42 mA 1 mA 0.132 V 1.8 V/µm Varies

A2 Ai

327

Values Used for Theoretical INR Calculations

Varies Varies

An interesting aspect of the INR expression is that it depends on the entire set of blockers that fall within the frequency range equal to the receiver LO frequency plus or minus the range of beat frequencies passed by the cubic term generator interstage circuitry. That is, although only blockers 1 and 2 contribute to output IM3 products, any blocker in this frequency range can up-convert significant interstage noise, as depicted in Fig. 11.13. This effect is captured in the summation of the denominator of (11.15), where H (ω) represents the frequency-dependent gain of the interstage circuitry. Although this seems to suggest that the INR can be arbitrarily low, depending on the particular blocking condition, in practice the total blocker power is bounded, Nonlinear Interaction to fLO

RX Bandwidth = fBW

Noise

Blocker 1

| |

Blocker 2

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Noise

fLO IM2 Products and Noise at Multiplier Baseband Input

Blocker Signals at Multiplier LO Input

Freq.

IM3 Products at Multiplier Output

FIGURE 11.13 Frequency translation of bandpass noise by multiple blocker signals to desired signal band.

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DIGITALLY ENHANCED ALTERNATE PATH LINEARIZATION OF RF RECEIVERS

VDD

B

A

A

B

A

VIN +

VIN -

IOUT +

IOUT -

QOUT + QOUT -

GND VDD

R

VIN +

R

VIN -

VIN +

VIN -

= Resistor Connected to DC Bias Voltage

FIGURE 11.14

Schematic of cubic term generator for theory simulation.

and for the UMTS specification itself only the TX leakage and CW blocker are present at any given time, fixing M = 2 in the summation. For a real-world deployment of the circuit, the total blocker power would have to be estimated by field measurements in the relevant frequency range. To verify (11.15), it is compared with simulation results of the circuit schematic shown in Fig. 11.14. In this schematic, a total current draw of I D,tot = 24I D and multiple gain stages are used to suppress the relative noise contribution of the Gilbert cell multiplier. The results are shown in Fig. 11.15 for L = 0.6 µm, I D,tot = 1 mA, T = 298 K, and swept Vod in a deep-submicron process. A relatively large value of L is targeted in order to improve matching and to minimize linear term feedthrough. This value of L also reduces velocity saturation effects in the MOS device and ensures that the device transconductance exhibits a relatively large second-order Taylor series coefficient. Values for γ and E sat were extracted from simulated device models and found to be 0.55 and 1.8 V/µm, respectively. Although γ is traditionally thought to be greater than unity in submicron devices, this result is consistent with other recent reports of noise in submicron CMOS devices [39,41]. H (ωLO − ω2 )/H (ωLO − ω1 ) was simulated and found to be equal to 0.8. Figure 11.16 shows the results of simulation vs. calculation for Vod = 132 mV, I D,tot = 1 mA, T = 298 K, and swept A2 /A1 . In both Figs. 11.15(b) and 11.16(b), the simulated INR of both the input stage and the total circuit is shown. The data points at A2 = −26 dBV in Fig. 11.15 represent the peak blocking condition for the receiver of [26], and it can be seen here

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ALTERNATE FEEDFORWARD PATH BLOCKDESIGN CONSIDERATIONS

INR (dB)

(a) INR of Cubic Term Generator - Input Stage Only 50 50 45

45

40

40

329

(b) INR of Cubic Term Generator - Total

35

35

30 30

25

25

20

20

15

15

10

5 10 -36 -35 -34 -33 -32 -31 -30 -29 -28 -27 -26 -36 -35 -34 -33 -32 -31 -30 -29 -28 -27 -26 A2 Magnitude (dBV) at IM3 Generator Input A2 Magnitude (dBV) at IM3 Generator Input A1 Magnitude is 5.7dB less than A 2 A1 Magnitude is 5.7dB less than A 2 Sim. - Vod = 0.092 V Calc. - Vod = 0.092 V Sim. - Vod = 0.112 V Calc. - Vod = 0.112 V Sim. - Vod = 0.132 V Calc. - Vod = 0.132 V Sim. - Vod = 0.152 V Calc. - Vod = 0.152 V Sim. - Vod = 0.172 V Calc. - Vod = 0.172 V Sim. - Vod = 0.192 V Calc. - Vod = 0.192 V

Instage Sim. - Vod = 0.092 V Total Sim. - Vod = 0.092 V Instage Sim. - Vod = 0.112 V Total Sim. - Vod = 0.112 V Instage Sim. - Vod = 0.132 V Total Sim. - Vod = 0.132 V Instage Sim. - Vod = 0.152 V Total Sim. - Vod = 0.152 V Instage Sim. - Vod = 0.172 V Total Sim. - Vod = 0.172 V Instage Sim. - Vod = 0.192 V Total Sim. - Vod = 0.192 V

FIGURE 11.15 (a) Calculated vs. simulated INR due to input stage components swept over Vod ; (b) Simulated INR, input stage and total, swept over Vod .

that the input stage indeed dominates the INR performance of the circuit. Furthermore, for most values of Vod presented, the circuit meets the target INR value of 34 dB for 1 mA of current. As this current consumption is much less than the 28 mA consumed by the original receiver path of [26], it represents a reasonable design option for a portion of the alternate path circuitry. (a) INR of Cubic Term Generator - Input Stage Only 50 45 40 INR (dB)

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(b) INR of Cubic Term Generator - Total 50

Sim – A2/A1 = 8dB Calc – A2/A1 = 8dB Sim – A2/A1 = 4dB Calc – A2/A1 = 4dB Sim – A2/A1 = 0dB Calc – A2/A1 = 0dB

35

45 40 35 30

30 25 25

20

Instage Sim – A2/A1 = 8dB Total Sim – A2/A1 = 8dB Instage Sim – A2/A1 = 4dB Total Sim – A2/A1 = 4dB Instage Sim – A2/A1 = 0dB Total Sim – A2/A1= 0dB

20

15

15 -36 -35 -34 -33 -32 -31 -30 -29 -28 -27 -26 A2 (dBV) at IM3 Generator Input

10 -36 -35 -34 -33 -32 -31 -30 -29 -28 -27 -26 A2 (dBV) at IM3 Generator Input

FIGURE 11.16 (a) Calculated vs. simulated INR due to input stage components swept over A2 /A1 ratio; (b) simulated INR, input stage and total, swept over A2 /A1 ratio.

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DIGITALLY ENHANCED ALTERNATE PATH LINEARIZATION OF RF RECEIVERS

Alternate Path Mixer Concepts

The alternate path mixer and LO buffer can be designed as reduced versions of their counterparts in the main path. In this case, the “blockers” seen by the mixer are the undesired IM3 products as depicted at points 3 and 5 in Fig. 11.2. For the peak blocking condition, the power of these signals is on the same order of magnitude as that of the IM3 products desired. Hence, the linearity and noise requirements on these blocks are extremely trivial. Therefore, any IIP2 enhancements in the mixer can be removed, while the gate capacitances of the switching devices can be reduced such that a simple differential pair can be used for an LO buffer. 11.4.4

Alternate Path Analog Baseband Circuitry Concepts

The procedure used to set specifications on the alternate path baseband postfiltering is different from that of the main path in that the properties of the undesired “blocker” IM3 products in this case are not independent of those of the desired IM3 products. An algorithmic procedure that takes this relationship into account is thus required and is used to design the filter in [26]. This procedure shows that if the postfiltering is comprised of the mixer baseband first-order output pole at f −3dB = 1.5 MHz and another first-order pole with f −3dB = 8 MHz embedded into the buffer driving the 8-bit pipelined ADC running at 16.66 MHz, the error due to unwanted aliased IM3 products is negligible with respect to the alternate path thermal noise floor. More important, this procedure shows that if the system proposed in this work were implemented monolithically with a sigma-delta ADC running at or around 50 MHz, only the first-order pole at f −3dB = 1.5 MHz is required, potentially simplifying this portion of the receiver design. 11.4.5

Adaptive Equalizer Concepts: Dealing with Gain and Phase Mismatch

To overcome the constraint imposed by the Givens rotation relation of canonical complex LMS, an additional degree of freedom must be added to the adaptive algorithm to accommodate gain and phase mismatch between the main and alternate paths. In the context of the Givens rotation, this means that the relationship (11.10) should change to 

  m I [n] w I [n] = m Q [n] w Q [n]

x I [n] x Q [n]



a I [n] a Q [n]

 (11.16)

where the introduction of x I [n] and x Q [n] collectively constitute the additional degree of freedom. In this case the new algorithm error subtraction equations become e I [n] = m I [n] − wTI [n]aI [n] − xTI [n]aQ [n] e Q [n] = m Q [n] − wTQ [n]aI [n] − xTQ [n]aQ [n]

(11.17)

An equivalent solution to the I/Q mismatch problem in a complex adaptive equalizer was suggested in [42,43]. Unlike in [43], however, the equalizer tap update

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EXPERIMENTAL DESIGN OF AN ADAPTIVELY LINEARIZED UMTS RECEIVER

relations are developed in this work for LMS-based adaptive equalizers by viewing the complex LMS algorithm as a completely real implementation and by substituting the relations (11.18) into (11.4). It is then seen that (11.17) is satisfied and that (11.19)–(11.20) realize the tap update equations for the new algorithm.
e[n] =
m[n] =

m I [n] m Q [n]

e I [n]




a[n] =

e Q [n]






w[n] =

˜ I [n]aI [n]] wI [n + 1] = wI [n] + µ[e



wI [n] xI [n]

a I [n]



a Q [n] T  wQ [n] T xQ [n]

(11.18)

wQ [n + 1] = wQ [n] + µ[e ˜ Q [n]aI [n]] (11.19)

xI [n + 1] = xI [n] + µ[e ˜ I [n]aQ [n]]

xQ [n + 1] = xQ [n] + µ[e ˜ Q [n]aQ [n]] (11.20)

This change is efficient from a hardware perspective, as shown in Fig. 11.17. Both the original NLMS and enhanced-degree-of-freedom NLMS equalizers have the same number of multipliers, which dominate the power and area consumption of the digital implementation. 11.5 EXPERIMENTAL DESIGN OF AN ADAPTIVELY LINEARIZED UMTS RECEIVER Based on the concepts described previously, a radio receiver capable of meeting the UMTS sensitivity requirements under worst-case blocking was built and tested. A block diagram of this system is shown in Fig. 11.18. The RF front end is implemented in 0.13-µm RF CMOS and is mounted on a gold-plated high-frequency laminate substrate to which RF and baseband connections are made. The laminate substrate is in turn mounted on PCB that contains the baseband circuitry of the main and alternate paths, which is composed of low-power commercially available discrete components. The on-board ADCs interface via a bidirectional parallel connection to an FPGA platform which conducts the digital signal processing operations of the receiver in real time. The die photo of this chip is shown in Fig. 11.19. Aside from the bandgap circuitry, which utilizes a 2.7-V supply voltage (drawing 2.5 mA), the remainder of the chip operates under a 1.2-V supply voltage. The chip is fully ESD-protected. The measurements performed on the receiver with a full equivalent UMTS downlink signal are postprocessed in MATLAB to obtain the DPCH sensitivity results. In the MATLAB code, rate change, synchronizing, derotation, despreading, and decoding are performed to recover the original bit stream from the physical receiver output.

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DIGITALLY ENHANCED ALTERNATE PATH LINEARIZATION OF RF RECEIVERS OUT I

(a) MAIN I mI[n]

eI[n] IFT

CLK

ALTERNATE I aII[n]

out >> in shift amount

CLK

QFB IFB

Q D

TAP I

IFB QFB

TAP I

QFT IFB

wI[n]

D Q

D Q

Log2 Quantizer

D Q

aQ[n] D Q

ALTERNATE Q

wQ[n] QFB

shift amount out >> in

Q D

IFB

CLK

TAP Q

TAP Q

QFB

CLK IFB QFB

-1 -1

IFT QFT eQ[n]

mQ[n] MAIN Q (b) MAIN I mI[n]

ALTERNATE I aII[n]

out in >> shift amount

TAP

TAP

TAP

OUT Q OUT I eI[n]

TAP

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CLK D Q

CLK

D Q

Log2 Quantizer Q D

D Q

aQ[n]

wI[n],xI[n], wQ[n],xQ[n]

D Q

ALTERNATE Q TAP

TAP

CLK TAP

TAP

mQ[n] MAIN Q

shift amount out >> in

eQ[n] OUT Q

FIGURE 11.17 Hardware implementation of complex NLMS algorithm: (a) canonical; (b) proposed architecture with enhanced degree of freedom.

11.5.1

Main Path Circuit Design

11.5.1.1 LNA and Balun Reflecting a typical choice for narrowband receivers, the integrated front end employs an inductively degenerated cascode LNA. As the duplexer [27] has a single-ended output, the LNA must have a single-ended input. However, as the SAW filter to be removed for this design previously handled the single-ended-to-differential conversion between the LNA and the mixer, provisions

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EXPERIMENTAL DESIGN OF AN ADAPTIVELY LINEARIZED UMTS RECEIVER

PCB

Channel Filter

FPGA

2xLO

LO Buffers

ADC

MAIN

RRC

3

HPF

PATH

Balun

LPF

ADC

SINC Filter

ADC

DC Trim

RRC

3

HPF

Cubic Term Generator

IN

Channel Filter

LPF

LNA LO Buffers

OUT I

Channel Filter

ADAPTIVE EQUALIZER

LPF

SINC Filter

OUT Q

CHIP

2xLO

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ALT.

RRC

IIR

HPF

PATH Channel Filter

Bandgap Reference And Bias

LPF

FIGURE 11.18

ADC

DC Trim

RRC

IIR

HPF

Experimental UMTS receiver architecture.

for performing this task must now be made on chip. An area-efficient method of accomplishing this goal is to place a secondary inductor winding inside the LNA load inductor, creating a transformer balun. The secondary coil should be designed to have a maximum number of turns to improve voltage gain. Although this makes the Q of the secondary relatively poor, this has little effect on the Q of the LNA tuned

FIGURE 11.19

RF front-end die photo.

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DIGITALLY ENHANCED ALTERNATE PATH LINEARIZATION OF RF RECEIVERS VDD

OUT+

OUT-

Balun (From AC Coupler) IN

LNA

VBIAS GND

(a)

(b)

FIGURE 11.20 Implementation of main path LNA and balun: (a) schematic depiction; (b) balun three-dimensional CAD representation.

load, as the load seen by the secondary coil is high, and as a result power is not lost to it. The LNA and balun designs are depicted in Fig. 11.20. 11.5.1.2 Mixer and LO Buffer As the system proposed in this chapter equalizes only IM3 products, the mixer utilizes a folded high-IIP2 mixer in order to obviate any IM2 equalization [18]. The schematic of this mixer as implemented is shown in Fig. 11.21. In order to drive the large gate capacitances of the mixer switching pair, an actively loaded Cherry–Hooper LO buffer is utilized. The schematic of this

VDD VBIAS1

+ LO -

VBIAS5 IN+

INBB OUT+

BB OUTCMFB OTA

VBIAS2 VBIAS4 GND

VBIAS3

FIGURE 11.21

VBIAS3

Main path high-IIP2 mixer.

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335

VDD

+ VOUT VIN+

VIN-

VBIAS GND

FIGURE 11.22

Main path Cherry–Hooper LO buffer.

block, shown in Fig. 11.22, reflects some biasing and neutralization modifications to the circuit shown in [3], permitting it to function under the low-voltage supply headroom. Separate divide-by-2 circuits are included immediately adjacent to the LO buffers, to avoid problems associated with on-chip RF-LO coupling [40].

11.5.1.3 Analog and Digital Baseband Circuitry The required order of the analog postfilter is obtained by considering the worst-case frequency translation to baseband of the blocker profile depicted in Fig. 11.8 after the LNA transfer function is added to the profile. It was found that for an ADC sampling rate of 50 MHz, a third-order Chebyshev filter in the analog domain was sufficient to attenuate down-converted outof-band blocker signals to levels negligible with respect to the thermal noise floor. This filter was implemented on PCB with a nominal passband edge frequency of 2.3 MHz and nominal amplitude and group delay ripples of 0.5 dB and 82 ns, respectively. Due to the integration of the analog postfilter with discrete components on PCB substrate, the actual amplitude and group-delay ripple values are somewhat worse than these numbers. Nevertheless, these parameters do not constrain the effectiveness of the adaptive equalization. The analog postfilter does not produce in-band attenuation, due to the location of its passband edge frequency. Rather, close-in adjacent channel filtering is provided in the digital domain by a 25-tap root-raised cosine FIR filter running at 16.66 MHz. The analog postfilter also includes an additional gain and buffering stage that drives the ADC, which utilizes an 8-bit pipelined architecture running at 50 MHz. The ADC sampling rates were chosen not to be equal to a multiple of the UMTS chip rate to facilitate testing with the particular FPGA platform used. However, as the baseband digital signal is oversampled, this choice does not compromise the integrity of the experiments presented herein. Coarse dc offset adjustments prior to the digital HPFs are also implemented to avoid saturating the baseband circuitry.

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DIGITALLY ENHANCED ALTERNATE PATH LINEARIZATION OF RF RECEIVERS

Alternate Path Circuit Design

The design of the alternate path in this experiment is consistent with the strategies described in Section 11.4. The mixer schematic is the same as that in Fig. 11.21 but without the IIP2-enhancing tuning inductor and with the tail current source split between the two differential halves of the circuit. The LO buffers are now simple resistively loaded differential pairs. The active analog die circuitry of the alternate path consumes 6.7 mA of current from the 1.2-V supply and only 0.2 mm2 of die area, making it suitable for monolithic integration. As in the main path, 8-bit pipelined ADCs are used, but sample at 16.66 MHz. The alternate path baseband circuitry on the PCB, including the postfilters and ADCs, consumes less than 7.6 mA under a 2.7-V supply voltage. In the alternate path digital domain an IIR fixed equalization filter also exists, which accounts for most of the known LTI path mismatch between the main and alternate paths. It is posited that calibration of this digital IIR filter is unnecessary, as the use of automatic calibration in the analog baseband postfilter to maintain a relatively constant frequency response over PVT variation is common practice in cellular receivers [4,5,24]. The implemented version of the adaptive equalizer is shown in Fig. 11.17b. Two doubly complex filter taps were used to adjust for perturbations in the baseband group delay over variations in LO frequency, although in practice the baseband group delays will also vary with temperature. The division associated with the NLMS algorithm is log 2-quantized here, allowing the use of a simple barrel shifter as a divider [45].

11.6 EXPERIMENTAL RESULTS OF AN ADAPTIVELY LINEARIZED UMTS RECEIVER 11.6.1

Receiver IIP3 Measurement Results

Figure 11.23 shows the concept behind the modified two-tone IIP3 test used to evaluate the receiver proposed. The goal is to reproduce the TX leakage and CW blocker signals at the LNA input at several amplitudes (including the worst-case specified), at all 12 UMTS RX frequencies and to measure the output across the RX band in each instance. The TX signal is a QPSK-modulated pseudorandom-noise bit sequence at 3.84 MS/s that is upsampled, passed through the UMTS-specified channel

| |

| | SWEEP

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MEASURE

Frequency

fLO FIGURE 11.23

Modified two-tone test concept.

Frequency

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filter, and up-converted to 1.98 GHz. The CW amplitude is fixed at 8 dB less than that of the TX. As this test is designed to predict the sensitivity of the receiver for UMTS communication, the RX signal power is set to zero when measuring the receiver output error. This methodology represents a valid proxy for predicting the receiver sensitivity because the total RX signal level required (including a pilot channel, etc.) at sensitivity is below the system thermal noise floor. The receiver output error is input-referred by running the modified two-tone IIP3 test along with −90- and −97dBm CW RX signal models in order to determine small signal-gain under blocking and blocking + correction conditions, respectively. This is necessary because the receiver small-signal gain will change due to the total blocker input edging closer to the ICP1 level. These CW RX signal models are swept across the RX band, and the small-signal gain measured across all of the frequency points is rms-averaged to capture any frequency dependence in the effective baseband transfer function. The resulting steady-state input-referred error over swept TX leakage amplitude is shown in Fig. 11.24a. Note that all plots shown and numbers reported depict the I /Q receiver channel with worst-case performance under worst-case specified blocking. The total input-referred error accounts for gain loss, thermal noise, and all IM products. Removing the effects of main path thermal noise and IM2 products yields a lumped input-referred error quantity consisting of all other error sources. From this quantity, which is treated as residual IM3 error, a slope-of-3 line is extrapolated from the worst-case input blocker magnitude to obtain an effective IIP3 metric. Other measurement results show that the measured IIP3 performance is limited by higherorder distortion products in the main path. Note that 50- kTB noise is removed from these plots and that the maximum total input-referred error in this regard, computed in Section 11.4.1 (−98.2 dB) under the worst-case scenario of −26 dBm TX

Input-Referred Error Power (dBm)

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(a) Enhanced NLMS Measured Results

(b) Regular NLMS Measured Results

-75

-75

-80

-80

-85

-85

-90

-90

-95

-95

-100

-100

-105

-105

-110 -32

-31

-30

-29

-28

-27

-26

-110 -25 -32

-31

-30

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-28

-27

-26

-25

Input Blocker Magnitude, TX Leakage (CW is 8dB less) (dBm) Uncorrected Error Corrected Error Corrected Error - IM3 Products Only Receiver Thermal Noise under Blocking+Correction

FIGURE 11.24 Measured results of a modified two-tone test: (a) for proposed enhanced complex NLMS architecture; (b) for canonical complex NLMS architecture.

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leakage, is met with 3 dB of margin when correction is applied. The contribution of the baseband circuitry to the uncorrected out-of-band IIP3 has been measured and found to be negligible. The results of this same test using the NLMS algorithm without the enhanced degree of freedom in Fig. 11.24(b). A phase mismatch of about 3◦ in the main path along with mismatch in the baseband frequency responses are responsible for the higher input-referred IM3 products. This confirms experimentally that this algorithm enhancement produces a noticeable performance improvement even for the moderate correction ratios required for this design. Although the case in which the CW blocker frequency is less than the TX frequency does not require alternate path equalization for this duplexer [26], the CW blocker amplitude was exaggerated far above specification in order to show that this case is covered by the proposed architecture as well. As described more fully in [44], this case generates an IM3 product in the main path consisting of a frequency-translated version of the squared modulated TX leakage. It is worthwhile to measure these results, as this condition is subject to an additional error term in the alternate path stemming from the fact that the “squared” TX leakage in this path is now TX leakage multiplied by a delayed version of itself. The results of this test are shown in Fig. 11.25 and show correction ratios similar to those seen in Fig. 11.24a. The results of this experiment repeated across the UMTS RX band are shown in Fig. 11.26. The TX frequency is kept at 1.98 GHz and the CW frequency adjusted such that the IM3 products fall within the RX band. The convergence behavior of the adaptive equalizer is shown in Fig. 11.27 for the case where f LO = 2.1225 GHz and the IM3 products land directly on the RX band. It is seen that if dc offset correction is not applied prior to the enabling of the alternate path digital back end, the convergence time is extended dramatically, as expected. The frequency-domain measurement of the digital receiver output in the presence of a moderately large tonal desired signal is shown in Fig. 11.28 both with and without correction.

(a) Experiment Concept

(b) Experiment Result

| |

f CW

f TX

f LO

Freq.

Uncorrected Error Corrected Error Corrected Error - IM3 Products Only Thermal Noise under Blocking+Correction

Input-Referred Error Power (dBm)

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-80 -85 -90 -95 -100 -105 -110 -32

-31

-30

-29

-28

-27

-26

-25

Input Blocker Magnitude, TX Leakage (CW is 5dB less) (dBm)

FIGURE 11.25 Measured results of a modified two-tone test in which IM3 products contain squared TX leakage: (a) concept; (b) results.

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IIP3 (dBm)

Input-Referred Error Power (dBm)

EXPERIMENTAL RESULTS OF AN ADAPTIVELY LINEARIZED UMTS RECEIVER

(a) Input-Referred Error vs. fLO

-75 -80 -85

(b) IIP3 vs. fLO

6 4 2

Uncorrected Error 0 Corrected Error Corrected Error - IM3 Products Only Receiver Thermal Noise -2 under Blocking+Correction

-90 -95

-100

-4

-105

-6

-110 2.11

2.12

2.13

2.14

2.15

2.16

2.17

-8 2.11

2.12

Frequency (GHz)

2.13

2.14

2.15

2.16

2.17

Frequency (GHz)

FIGURE 11.26 Measured results of a modified two-tone test for −26 dBm TX leakage, −34 dBm CW blocker swept over LO frequency: (a) input-referred error vs. f LO ; (b) IIP3 vs. f LO .

Amplitude (LSB)

TX(-25dBm)

<

CW(-33dBm)

CW(-30dBm)

800

800

600

600

400

400

200

200

<

TX

20

30

(-25dBm)

0

0 -200

-200

-400

-400

DC Offset-600 Correction Off DC Offset-800 Correction On

-600 -800 -20 -10

0

10

20

30

40

50

60

70

-20 -10

0

10

Time ( s)

FIGURE 11.27

40

50

60

70

Time ( s)

Measured convergence behavior of adaptive equalization algorithm.

(a) Full Output Spectrum Relative Magnitude (dBm, 10dBm=peak digital amplitude)

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(b) Zoomed In

Alternate Path Off Alternate Path On

-10

Alternate Path Off Alternate Path On

-11.6

-20 -11.8

-30 -40

-12

-50

-12.2

-60

-12.4

-70 -80

-12.6

-90

-12.8

-100

-13 0

1

2

3

4

5

Frequency (MHz)

6

7

8

0.998

0.999

1.000

1.001

1.002

Frequency (MHz)

FIGURE 11.28 Digital spectrum analyzer measurement of power spectral density with and without correction.

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11.6.2

Receiver Sensitivity Measurement Results

Although the IIP3 test provides insight as to how nonlinear terms contribute to the input-referred error of the receiver, the actual performance specification that must be met is that of the sensitivity test. In this work, such a test is performed using a specification-equivalent UMTS 12.2-kb/s downlink reference measurement channel [2] with both I and Q channels active and results comparable to those in [4]. The theoretical relations described in [4,28] relate the receiver sensitivity to the noise figure. These relations also hold for the error figure quantity introduced earlier in this chapter. In this test, the UMTS spreading gain G = 21.1 dB, and the back-end implementation loss is approximately 0 dB. With L DUP = 1.8 dB the receiver must achieve BER = 10−3 for DPCH EC = −118.8 dBm under typical conditions and DPCH EC = −115.8 dBm under blocking. The results of the test for f LO = 2.1225 GHz are shown in Fig. 11.29. The fact that BER = 10−3 occurs with despread SNR ≈ 1 dB indicates that the MATLAB postprocessing of the physical receiver output was done correctly [4]. Each point in Fig. 11.29 represents the average of 4.88 × 105 bits (2000 data frames), which is sufficient to resolve BER accurately down to 10−4 [46]. The baseline sensitivity is −121.9 dBm, 0.5 dB greater than predicted by the noise figure, with the discrepancy accounted for by unfiltered noise at frequencies greater than 1.92 MHz. The sensitivity of the receiver under worstcase blocking and correction is −119.5 dBm, 0.9 dB greater than predicted by total input-referred error, with 0.6 dB of this difference accounted for by noise at frequency greater than 1.92 MHz. This shows that the aforementioned effective IIP3 test is an accurate predictor of the actual sensitivity performance. Without correction, sensitivity significantly exceeds specification at −98.8 dBm under worstcase blocking. 0

3

10

2.5

10

2

10

-1

-2

SNR No Blocking BER No Blocking SNR Blking/Correction BER Blking/Correction SNR Blking/No Correction BER Blking/No Correction

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10

0

10

-0.5

BER

SNR of Despread Signal (dB)

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-7

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-105

-100

10 -95

DPCH Signal Power at LNA Input (dBm)

FIGURE 11.29 Measured receiver DPCH despread SNR and BER under sensitivity, sensitivity/blocking/correction, and sensitivity/blocking/no correction, respectively.

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35 Input Blocker Magnitude, TX Leakage (CW is 8dB less) (dBm) -25 -26 -27 -28 -29 -30 -31 -32

30

INR (dB)

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20

15

10 2.11

2.12

2.13 2.14 2.15 LO Frequency (GHz)

FIGURE 11.30

11.6.3

2.16

2.17

Measured INR performance of an alternate path.

Alternate Path Measurement Results

The INR performance of the alternate path is measured and shown in Fig. 11.30. Performance under worst-case specified blocking conditions at f LO = 2.1225 GHz is 31 dB. Additional measurements suggest that higher-order distortion products lower IER from INR by less than 1 dB. Alternate path linear term feedthrough is also measured and referred to the main path input. The attenuation referred to the main path input is found to be greater than 46 dB over all LO frequencies, indicating that the effect of these terms in the equalization process is negligible. 11.6.4

Additional Measurement Results

The performance summary for the system and front end is shown in Table 11.3. Note that these and all other results quoted differ from those reported in [47], due to improvements made to the system to permit acceptable operation across the entire RX band. The new power consumption estimate of the alternate path digital back-end circuitry was obtained from switching statistics of a gate-level Verilog simulation referencing a 90-nm CMOS process standard cell library.

11.7

CONCLUSIONS

This work introduces a novel architecture for adaptive feedforward error cancellation in RF receivers in which the alternate feedforward path extends from the analog RF domain to the digital baseband domain. The experimental results detailed in this chapter shows that the technique proposed improves the effective IIP3 performance

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TABLE 11.3

Receiver Performance Summary

Parameter Measured at f LO = 2.1225 GHz Active analog die area Active analog die alternate path area Analog die technology node Analog die supply voltage Estimated alternate path digital die area Digital die technology node Digital die supply voltage Analog die LNA + main path current Analog die alternate path current Estimated digital alternate path current Analog die LNA + main path dc gain Complete main path system dc gain to ADC input Input return loss (S11 ) 2.11–2.17 GHz [email protected] GHz Uncorrected IIP3 @ 1.98 GHz/2.05125 GHz Effective IIP3 @ 1.98 GHz/2.05125 GHz [email protected] GHz Analog die LNA + main path NF Complete LNA + main path system NF Baseline DPCH sensitivity DPCH sensitivity under blocking/correction off DPCH sensitivity under blocking/correction on Baseband signal measurement bandwidth

Result 1.6 mm × 1.5 mm 0.5 mm × 0.4 mm 130-nm RF CMOS 1.2 V/2.7 V 0.42 mm × 0.42 mm 90-nm bulk CMOS 1.0 V 28 mA (1.2 V) 6.7 mA (1.2 V) 5.6 mA (1.0 V) 30.5 dB 70.2 dB < −13 dB +58 dBm −7.1 dBm +5.3 dBm −19 dBm 5.0 dB 5.5 dB −121.9 dBm −98.8 dBm −119.5 dBm 10 kHz–1.92 MHz

of an integrated SAW-less UMTS receiver front end by over 12 dB and improves the receiver sensitivity performance under worst-case blocking by over 20 dB. The results presented herein can therefore be considered an important step toward the design of multimode receiver architectures that tackle nonlinearity problems on an “as needed” basis. An internally bandlimited multistage analog RF multistage cubic term generator was developed and implemented successfully to provide a suitable reference signal for IM3 equalization. Implications regarding the design of the other alternate path circuitry, including dc offset correction and the digital adaptive equalization, were also examined. The excess power consumption drawn by the alternate receiver path can be made small by time averaging, as it only needs to be enabled fully in the rare event that an IM3-producing situation exists. Acknowledgments The authors would like to thank F. Bohn for the frequency-divider IP and testing assistance from H. Mani and J. Yoo, all of Caltech. The help and advice of A. Emami, B. Hassibi, V. Pedroni, H. Wang, Y. Wang, F. Bohn, S. Jeon, A. Babakhani, J. Chen, and M. Loh of Caltech, and S. Kousai of Toshiba is greatly appreciated.

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REFERENCES 1. http://www.umts-forum.org/content/view/2315/110. 2. Third-Generation Partnership Project (3GPP), UE Radio Transmission and Reception (FDD), Technical Specification Group, (TSG) RAN WG4, TS 25.101, vol. 8.1.0, Dec. 2007. 3. B. A. Floyd, S. K. Reynolds, T. Zwick, L. Khuon, T. Beukema, and U. R. Pfeiffer, “WCDMA direct-conversion receiver front-end comparison in RF-CMOS and SiGe BiCMOS,” IEEE Trans. Microwave Theory Tech., vol. 53, pp. 1181–1188, Apr. 2002. 4. S. K. Reynolds, B. A. Floyd, T. J. Beukema, T. Zwick, and U. R. Pfeiffer, “Design and compliance testing of a SiGe WCDMA receiver IC with integrated analog baseband,” Proc. IEEE, vol. 93, pp. 1624–1636, Sept. 2005. 5. D. Kaczman et al., “A single-chip tri-band (2100, 1900, 850/800 MHz) WCDMA / HSDPA cellular transceiver,” IEEE J. Solid-State Circuits, vol. 41, pp. 1122–1132, May 2006. 6. M. Tamura, T. Nakayama, Y. Hino, et al., “A low voltage (1.8V) operation triple band WCDMA transceiver IC,” in IEEE RFIC Symposium Digest of Technical Papers, pp. 269– 272, June 2005. 7. N. K. Yanduru, D. Griffith, S. Bhagavatheeswaran, et al., “A WCDMA, GSM/GPRS/EDGE receiver front end without interstage SAW filter,” in IEEE RFIC Symposium Digest of Technical Papers, pp. 11–13, June 2006. 8. B. Tenbroek, J. Strange, D. Nalbantis, et al., “Single-chip tri-band WCDMA/HSDPA transceiver without external SAW filters and with integrated TX power control,” in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 202–203, Feb. 2008. 9. S. Haykin, Adaptive Filter Theory. Upper Saddle River, NJ: Prentice Hall, 2002, Chap. 5. 10. M. Faulkner, “DC offset and IM2 removal in direct conversion receivers,” IEE Proc. Commun., vol. 149, pp. 179–184, June, 2002. 11. V. H. Estrick and R. T. Siddoway, “Receiver distortion circuit and method,” U.S. Patent 5,237,332, filed Feb. 25, 1992, granted Aug. 17, 1993. 12. M. Valkama, A. S. H. Ghadam, L. Antilla, and M. Renfors, “Advanced digital signal processing techniques for compensation of nonlinear distortion in wideband multicarrier radio recivers,” IEEE Trans. Microwave Theory Tech., vol. 54, pp. 2356–2366, June 2006. 13. L. Yu and M. Snelgrove, “A novel adaptive mismatch cancellation system for quadrature IF radio receivers,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 789–801, June 1999. 14. L. Yu and M. Snelgrove, “Signal processor for reducing undesirable signal content,” U.S. Patent 6,804,359, filed Aug. 3, 1998, granted Oct. 12, 2004. 15. V. Aparin, G. J. Ballantyne, C. J. Persico, and A. Cicalini, “An integrated LMS adaptive filter of TX leakage for CDMA receiver front ends,” in IEEE J. Solid-State Circuits, vol. 41, pp. 1171–1182, May 2000. 16. A. Safarian, A. Shameli, A. Rofougaran, M. Rofougaran, and F. de Flaviis, “Integrated blocker filtering RF front ends,” in IEEE RFIC Symposium Digest of Technical Papers, pp. 13–16, June 2007. 17. M. Brandolini, P. Rossi, D. Sanzogni, and F. Svelto, “A +78dBm IIP2 CMOS direct downconversion mixer for fully integrated UMTS receivers,” IEEE J. Solid-State Circuits, vol. 41, pp. 552–559, Mar. 2006.

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18. A. Liscidini, M. Brandolini, D. Sanzogni, and R. Castello, “A 0.13µm CMOS front-end for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 981–989, Apr. 2006. 19. M. Tarrab and A. Feuer, “Convergence and performance analysis of the normalized LMS algorithm with uncorrelated gaussian data,” IEEE Trans. Inf. Theory, vol. 34, pp. 680–691, July 1988. 20. D. T. M. Slock, “On the convergence behavior of the LMS and normalized LMS algorithms,” IEEE Trans. Signal Process., vol. 41, pp. 2811–2825, Sept. 1993. 21. V. H. Nascimento, “A simple model for the effect of normalization on the convergence rate of adaptive filters,” in IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) Digest of Technical Papers, vol. 2, pp. 453–456, May 2004. 22. H. J. Bergveld et al., “A low-power highly digitized receiver for 2.4-GHz-band GFSK applications,” IEEE Trans. Microwave Theory Tech., vol. 53, pp. 453–461, Feb. 2005. 23. B. Razavi, RF Microelectronics. Upper Saddle River, NJ: Prentice Hall, 1998. 24. J. Rogin, I. Kouchev, G. Brenna, D. Tschopp, and Q. Huang, “A 1.5-V 45-mW directconversion WCDMA receiver IC in 0.13µm CMOS,” IEEE J. Solid-State Circuits, vol. 38, pp. 2239–2248, Dec. 2003. 25. L. Der and B. Razavi, “A 2-GHz CMOS image-reject receiver with LMS calibration,” IEEE J. Solid-State Circuits, vol. 38, pp. 167–175 , Feb. 2003. 26. E. Keehr and A. Hajimiri, “Equalizaion of IM3 products in wideband direct-conversion receivers,” IEEE J. Solid-State Circuits, vol. 43, pp. 2853–2867, Dec. 2008. 27. muRata Corp., Part Number DFYK61G95LBJCA, http://www.murata.com. Data sheet available at http://smartdata.usbid.com/datasheets/usbid/dsid/103495.pdf. 28. A. Springer, L. Maurer, and R. Weigel, “RF system concepts for highly integrated RFICs for W-CDMA mobile radio terminals,” IEEE Trans. Microwave Theory Tech., vol. 50, pp. 254–267, Jan. 2002. 29. T. Nojima and N. Konno, “Cuber predistortion linearizer for relay equipment in 800 MHz band land mobile telephone system,” IEEE Trans. Veh. Technol., vol. 34, pp. 169–177, Nov. 1985. 30. N. Imai, T. Nojima, and T. Murase, “Novel linearizer using balanced circulators and its application to multilevel digital radio systems,” IEEE Trans. Microwave Theory Tech., vol. 37, pp. 1237–1243, Aug. 1989. 31. L. Roselli, V. Borgioni, V. Palassari, and F. Alimenti, “An active cuber circuit for power amplifier analog predistortion,” in 33rd European Microwave Conference, vol. 3, pp. 1219– 1222, Oct. 2003. 32. F. Shearer and L. MacEachern, “A precision CMOS analog cubing circuit,” IEEE NEWCAS, pp. 281–284, June 2004. 33. R. Sadhwani and B. Jalali, “Adaptive CMOS predistortion linearizer for fiber optic links,” IEEE J. Lightwave Technol., vol. 21, pp. 3180–3193, Dec. 2003. 34. T. Nesimoglu, C. N. Canagarajah, and J. P. McGeehan, “A broadband polynomial predistorter for reconfigurable radio,” in Vehicular Technology Conference, 2001, vol. 3, pp. 1968–1972, May 2001. 35. T. Rahkonen et al., “Performance of an integrated 2.1 GHz analog predistorter,” in 2006 International Workshop on Integrated Nonlinear Microwave and Millimeter-Wave Circuits, pp. 34–37, Jan. 2006.

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36. E. Westesson and L. Sundstrom, “A complex polynomial predistorter chip in CMOS for baseband or IF linearization of RF power amplifiers,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS’99), vol. 1, pp. 206–209, June 1999. 37. T. S. Nielsen, S. Lindfors, S. Tawfik, and T. Larsen, “0.25mm CMOS analog multiplier for polynomial predistorter,” Proc. Norchip Conference, 2004, pp. 191–194, Nov. 2004. 38. H.-J. Song and C.-K. Kim, “A MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers,” IEEE J. Solid-State Circuits, vol. 25, pp. 841–848, June 1990. 39. E. Keehr and A. Hajimiri, “Analysis of internally bandlimited multistage cubic term generators for RF receivers,” IEEE Trans. Circuits Syst. I, vol. 56, pp. 1758–1777, Aug. 2009. 40. K. Han, J. Gil, S.-S. Song, et al., “Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier,” IEEE J. Solid-State Circuits, vol. 40, pp. 726–735, Mar. 2005. 41. M. T. Yang, C. W. Kuo, P. P. C. Ho, et al., “CR018 wideband noise model for AMS/RF CMOS simulation,” in IEEE RFIC Symposium Digest of Technical Papers, pp. 643–646, June 2007. 42. K. Gerlach, “The effect of I, Q mismatch errors on adaptive cancellation,” IEEE Trans. Aerosp. Electron. Syst., pp. 729–740, July 1992. 43. K. Gerlach and M. J. Steiner, “An adaptive matched filter that compensates for I, Q mismatch errors,” IEEE Trans. Signal Process., vol. 45, pp. 3104–3107, Dec. 1997. 44. R. Magoon, A. Molnar, J. Zachan, G. Hatcher, and W. Rhee, “A single-chip quad-band (850/900/1800/1900 MHz) direct conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-N synthesizer,” IEEE J. Solid-State Circuits, vol. 37, pp. 1710–1720, Dec. 2002. 45. H. Oba, M. Kim, and H. Arai, “FPGA implementation of LMS and N -LMS processor for adaptive array applications,” in International Symposium on Intelligent Signal Processing and Communications (ISPACS) Digest of Technical Papers, pp. 485–488, Dec. 2006. 46. M. Jeruchim, “Techniques for estimating the bit error rate in the simulation of digital communication systems,” IEEE J. Select. Areas Commun., vol. 2, pp. 153–170, Jan. 1984. 47. E. Keehr and A. Hajimiri, “Equalization of IM3 products in wideband direct-conversion receivers,” in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 204–205, Feb. 2008.

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PART III Transmitter Techniques

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Linearity and Efficiency Strategies for Next-Generation Wireless Communications LAWRENCE LARSON, PETER ASBECK, and DONALD KIMBALL University of California at San Diego, La Jolla, California

12.1

INTRODUCTION

Third-generation cellular wireless services are gradually being deployed on a worldwide basis, and wider bandwidth data-oriented OFDM-based standards such as WiMax and 802.11b/g/n are also becoming popular. These new services—and the 4G systems that will follow—require wider RF bandwidths and more exotic modulation schemes than those of previous physical-layer approaches. These new standards are also required to share the spectrum with existing 2G systems such as GSM and CDMA and their legacy frequencies. As a result, multi-mode/multi-band mobile terminals are now standard, and the need for these functions will increase over time. As we will see in this chapter, this evolution of wireless technology places an enormous burden on power amplifier technology. We summarize the key technical challenges presented by this evolution and present technical strategies to maintain high-power amplifier performance.

12.2

POWER AMPLIFIER FUNCTION

In the line-up of the modern wireless communications transmitter system, the linear power amplifier is the final interface between the baseband signal processing/RF upconverter and the antenna. When viewed in this light, the power amplifier function appears to be a simple amplification of the input signal and delivery of the resulting power to the antenna. This is shown schematically in Fig. 12.1. However, this apparent simplicity masks the fact that the power amplifier often dominates the power Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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LINEARITY AND EFFICIENCY STRATEGIES FOR WIRELESS COMMUNICATIONS LNA

I-Channel Duplexer

LPF sin wLO t BPF

Power Amplfier

VGA

Reconstruction Filter

IF cos wLO t

VGA RF Local Oscillator

LPF

Q-Channel

Reconstruction Filter

FIGURE 12.1 Heterodyne wireless handset transmitter section, showing a complete upconversion path from baseband.

dissipation in the mobile terminal and is often the final determiner of the quality of the waveform transmitted. Unlike the relentlessly CMOS-focused digital baseband and RF transceiver functions, the typical power amplifier in a mobile terminal or wireless LAN card utilizes a mix of semiconductor technologies and design disciplines. As a result, the power amplifier is still fertile ground for innovation at the technology, circuit and system level. This innovation can take the form of new circuit approaches, new device designs, new packaging techniques, and even innovations at the system level. In the next section we provide an overview of the signal characteristics that a typical power amplifier has to contend with in a multi-mode environment. 12.2.1

Characteristics of Power Amplifier Waveform Requirements

The performance of the power amplifier is determined largely by the waveform it has to process as well as its center frequency. As shown in Table 12.1, there are several ways to characterize the signal transmitted by the power amplifier. The TABLE 12.1 Signal Characteristics of Modern Wireless Standards System GSM EDGE CDMA ONE UMTS CDMA 2000 802.11a/g WiMax

PAR (dB)

PMR (dB)

PCDR (dB)

Bandwidth (MHz)

Access Type

0 3.2 5.5–12 3.5–7 4–9 8–10 8–10

0 17 ∞ ∞ ∞ ∞ ∞

30 30 30 80 8 25 25

0.2 0.2 1.25 5 5 20 20

TDMA TDMA CDMA CDMA CDMA TDMA TDMA

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peak-to-average ratio (PAR) compares the peak modulated output power to its shortterm (measured over many symbols) average; as the industry moves to more spectrally efficient modulation formats, this ratio is growing, creating additional linearity and efficiency challenges. Power amplifier efficiencies typically peak at the maximum saturated output power but decline precipitously as the power is reduced, so a high PAR waveform implies that the power amplifier is spending most of its time in a low-efficiency “backed-off” state. In some cases it is not possible to determine the peak of the waveform definitively, since the signal has a very wide distribution of possible amplitudes, and then a probabilistic measurement of the PAR is used. For example, the peak envelope power in this case is not specified as an absolute peak but, rather, as the power level that the signal is below for a certain percentage of the time: typically, 99.9% or 99.99% of the time. A second method of characterizing the waveform is by the peak-to-minimum ratio (PMR), which is the ratio of the peak waveform power to the minimum waveform power, again measured over a short period of time. A high PMR waveform presents a challenge to the power amplifier from an efficiency perspective, and it can also make certain linearization techniques difficult to implement. In these cases, the output power reaches close to zero for a brief period of time. The power control dynamic range (PCDR) is a measure of the maximum variation in the average output power measured over a long period of time (typically, several hours). This variation is especially large in CDMA-based systems, because of the power control loop required to prevent near–far interference in spread-spectrum systems. A high PCDR presents problems for maximizing power amplifier efficiency, since the long-term average output power is typically well below that where peak efficiency occurs. In most CDMA mobile systems, the average output power is lognormally distributed, with a mean of roughly 0 dBm and a peak of approximately 30 dBm. So the PCDR is typically over 60 dB. OFDM-based systems such as WiMax can have similar PCDR constraints. The PAR statistics of the signal can also be characterized graphically by the complementary cumulative distribution function (CCDF). The CCDF curve plots the probability that the power is equal to or above a certain average value at any given moment of time. As an example, in CDMA or W-CDMA systems, the statistics of the signal will be dependent on how many code channels and/or carriers are present at the same time. Figure 12.2 shows the CCDF curves with different code-channel configurations [1]. Even in systems that use constant-amplitude modulation, such as GSM, the peak-to-average ratio can exceed unity if the transmitter is amplifying more than one signal, such as in base station applications. Given the fact that the modulated signal, with a given CCDF and PAR, is passed through the nonlinear power amplifier and there is a resulting regrowth of the spectrum in adjacent frequencies, the linearity figure of merit for digital wireless communication systems is typically the adjacent channel power ratio (ACPR) and the alternate channel power ratio (AltCPR). The ACPR is typically measured as the ratio of the signal power in the desired channel to the distortion power in an adjacent channel; the alternate channel power regrowth (AltCPR) is a measure of the ratio of the signal

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Probability (%)

LINEARITY AND EFFICIENCY STRATEGIES FOR WIRELESS COMMUNICATIONS

Gaussian Noise

32-Code Signal 9-Code Signal

2

4

6

8

10

12

dB Above Average

FIGURE 12.2 Complementary cumulative distribution function (CCDF) of a CDMA signal with differing codes and comparison to Gaussian noise profile [1].

Power

power in the desired channel to the distortion power in the alternate channel. These two measures are shown in Fig. 12.3. Each of the digital standards characterizes the ACPR requirement differently; they are usually specified by an RF spectrum mask that is related to the spacing between channels as well as limitations on the out-of-band emissions specified by the regulating body. In addition, each standard has its own unique modulation format, and the distribution function of the waveform can alter the ACPR. There are alternative techniques for characterizing power amplifier accuracy and linearity in modern communications systems. The previous figures of merit characterized the spectral regrowth of the signal. Other figures of merit characterize the accuracy of the modulated signal. They typically involve a precision demodulation

Power

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ACPR

Frequency (a)

Alternate Channel Leakage

Frequency (b)

FIGURE 12.3 Spectrum of transmitted signal: (a) spectrum of ideal transmitted modulated signal; (b) spectrum of distorted signal illustrating ACPR and AltCPR.

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of the transmitted signal and subsequent comparison to an ideal reference signal. The figure of merit depends mainly on the modulation scheme and the wireless standard. The 802.11a and WiMax systems use the error vector magnitude (EVM) measurement, while GSM uses phase and frequency error. The CDMA IS95 and CDMA2000 systems employ a waveform quality metric ρ. The EVM measurement is a modulation-quality metric widely used in digital RF communications systems, especially in 3G and OFDM-based modulation standards. It is essentially a measure of the accuracy of the modulation of the waveform transmitted. Mathematically, the EVM is defined as
 EVM =

n

|e(k)|2 n

(12.1)

where e(k) is the normalized magnitude of the error vector at symbol time k, and n is the number of samples over which the measurement is made. Alternatively, EVM is the root-mean-square (rms) value of the error vector when symbol clock transitions occur. This is shown in simplified form in Fig. 12.4. Together, these considerations suggest several important lessons. The first is that the newer generations of wireless standards require wider bandwidth and higher dynamic range (see Table 12.1) than those of earlier standards. In addition, since each new wireless standard requires its own unique center frequency, mobile terminals of the future will be required to operate across multiple frequency bands. This challenge presents a real problem for traditionally designed power amplifiers, which typically achieve their peak efficiency at the highest output power and at only one frequency. In the next section we discuss some alternative approaches under investigation at our laboratory to the more traditional power amplifier design methods, which might provide for improved performance in these new regimes of operation.

Error Vector

Measured Signal Q Ideal Signal

I

FIGURE 12.4 The error vector magnitude is a measure of the difference between the ideal and actual waveforms transmitted.

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POWER AMPLIFIER EFFICIENCY ENHANCEMENT

The origins of the poor efficiency of a power amplifier in practical situations are straightforward. Consider the case of the simple bipolar transistor power amplifier shown in Fig. 12.5. In this case, the current–voltage characteristics dictate that the dc collector bias on the device is Vcc and the dc current through the device is Imax /2. As a result, the dc power dissipation of the amplifier is simply Vcc Imax /2. Under conditions of maximum output power, the collector voltage swings from 0 to 2Vcc and the device current swings from 0 to Imax and delivers the maximum output power to the load impedance of Vcc Imax /4. So the maximum efficiency of the amplifier under these conditions is 50%, and the load impedance that is presented to the device is 2Vcc /Imax . However, in most cases, the actual efficiency is substantially less than this maximum amount, and a good portion of the dc power delivered to the power amplifier remains inside the amplifier, becoming waste heat. The lower efficiency results from the fact that the dc power dissipated by the amplifier remains essentially at Vcc Imax /2

VCC =3.5V L

6V

20V

Impedance Matching Vin

RL=50

Impedance Matching L

5W

Vbi (a)

Collector Current

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IMAX

Load-Line

VCC Collector-Emitter Voltage (b)

FIGURE 12.5 Simplified view of a power amplifier illustrating (a) the circuit schematic with impedance matching at input and output to maximize the output power and (b) typical transistor characteristics and load line.

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355

1 Doherty 0.8

Efficiency

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ET/EER 0.6 0.4

Class B

0.2

Class A

0 0

0.2

0.4

0.6

0.8

1

Pout (normalized)

FIGURE 12.6 Comparison of ideal power amplifier power-added efficiencies for class A, class B, EER, and Doherty amplifiers [2].

for all values of output power, so the efficiency decreases linearly with output power in the class A mode of operation. It is a major challenge to maintain efficient operation of a power amplifier over a large output power range, since for standard amplifier topologies (classes A and AB) the efficiency drops markedly as the output power is backed off from its peak value [2]. As Table 12.1 demonstrated, the dynamic range of output powers can approach 100 dB for modern wireless standards. More elaborate architectures, however, provide the possibility of maintaining high efficiency down to low power levels. Figure 12.6 contrasts representative efficiency values as a function of power level for traditional class A and traditional class B amplifiers with two approaches that we discuss in this section as possible alternatives: the Doherty amplifier and dynamic supply amplifier [also known as the envelope elimination and restoration (EER) or envelope tracking (ET) approach]. The benefits of the last two architectures are particularly evident if one computes an overall time-average power-added efficiency for the amplifier considering the probability distribution of the output power required; in many cases an advantage of greater than a factor of two in battery discharge time over class AB operation can be obtained. 12.3.1

Doherty Amplifier Techniques

The Doherty amplifier is comprised of a main amplifier biased in class AB, and an auxiliary amplifier biased roughly in class C (so that it is “off” below a certain input power) [3], as shown in Fig. 12.7. The actual invention dates back to the 1930s, where the application was for kilowatt-tube amplifiers for AM radio transmitters—a remote application from today’s modern wireless handsets. However, the essential utility of the technique is applicable to a wide range of uses. At low powers, the main amplifier is operated with a relatively high load impedance, which allows it to achieve high efficiency, and the auxiliary amplifier is off. At higher power levels, the auxiliary amplifier turns on, and through the active

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Main Zc , 90 o

Vout

Zo , 90 o Vin Peaking

FIGURE 12.7

Simplified block diagram of a Doherty amplifier.

load-pulling effect of the Doherty power combiner, causes the main amplifier effective load impedance to drop at the higher output power. This maintains the high efficiency of the complete amplifier over a broad range of output power without hard saturation of the main amplifier. The classical Doherty power combiner employs a quarter-wave transmission line. It has been shown that by tailoring the transmissionline impedance (the ratio of Z c to Z 0 ), the range of power for high efficiency can be maximized [4]. To maintain adequate linearity of the Doherty amplifier, the turn-on of the auxiliary amplifier must be carefully controlled as a function of input power. The large transconductance and rapid turn-on characteristics of a heterojunction bipolar transistor (HBT) are beneficial in designing this transition, such that a relatively flat gain vs. power curve can be maintained, which is desirable for linearity enhancement. An additional difficulty is present, however, related to the phase distortion of the amplifier. The effect of the phase distortion is evident in Fig. 12.8, which shows simulations of an HBT-based Doherty amplifier driven with two-tone inputs [5]. The simulated third-order intermodulation products are dominated by AM-PM effects rather than the more customary AM-AM effects. This is a classic limitation of the Doherty approach, since the linearity is degraded by the action of the auxiliary amplifier, whose phase behavior may be very different from that of the main amplifier. 110

Phase(Degrees)

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Varying Gate Bias of Auxiliary Amplifier

100 90 80 70 60 -5

0

5

10 Pin(dBm)

15

20

FIGURE 12.8 Variation in phase shift of a Doherty amplifier with input power as a function of the dc gate bias of the auxiliary amplifier [5].

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Digital predistortion has been used to counter this phase deviation (as well as to minimize the AM-AM distortion). As a result, a combination of high efficiency and high linearity has been demonstrated [5].

12.3.2 Dynamic Power Supply Variation Using Envelope Tracking/Envelope Elimination and Restoration Techniques Like the Doherty amplifier, use of the dynamic supply variation schemes of envelope tracking (ET) or envelope elimination and restoration (EER) has a long pedigree; in fact, EER was also developed initially in the 1930s as an efficiency enhancement technique for kilowatt AM transmitters [6]! Dynamic power supply schemes are usually separated into two types: EER and ET. Figure 12.9 shows the principles of traditional EER and ET systems. EER uses a combination of a high-efficiency switched-mode PA with an envelope remodulation circuit [7–11]; ET utilizes a linear PA and a controlled supply voltage, which closely tracks the output envelope. When the supply voltage tracks the instantaneous output envelope, it is known as wide-bandwidth ET (WBET) [12–15]; when the supply voltage tracks the long-term average of the output envelope, it is known as average ET (AET) [16,17]. AET techniques are especially useful for power control schemes, such as the reverse link in CDMA, where the long-term variation in average power is

Amplitude Amplifier A(t) Amplitude Signal

DSP RF Input

RF Output

Limiter Class D/ E/F/S

LO

(a)

Amplitude Amplifier A(t) Amplitude Signal

DSP RF Input

RF Output Class AB LO

(b)

FIGURE 12.9 Block diagrams of (a) an envelope elimination and restoration power amplifier and (b) an envelope tracking amplifier.

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much greater than 20 dB [18]. However, they improve the efficiency only modestly for high PAR signals such as OFDM. In both EER and wideband ET systems, the collector–drain supply of the RF power transistor dynamically changes with the output envelope, so the RF transistor operates with higher efficiency over a wide dynamic range of output power. Theoretically, EER is more efficient than ET, since the RF transistor is always operating in a switching mode. In a traditional EER system, the input RF signal was applied to a limiter (as shown in Fig. 12.9); this could be a problem for some wide-dynamic-range signals, where the peak-to-minimum ratio is very high [19]. By contrast, ET systems are better positioned to accommodate high peak-to-minimum signals because the amplifiers operate in a linear (if slightly compressed) mode at all output power levels, so the resulting gain variation is manageable. In modern EER systems, the amplitude and phase component signals are generated directly in the baseband domain and up-converted to RF. For the complex modulated signal, the complex baseband signal sBB (t) can be expressed with Cartesian coordinate components I (t) and Q(t) or the polar phasor components A(t) and φ(t) as sBB (t) = I (t) + j Q(t) = A(t)φ(t)

(12.2)

where the magnitude of the complex envelope is A(t) =




I (t)2 + Q(t)2

(12.3)

and the complex phase signal of the envelope—with appropriate mapping to the entire complex plane—is φ(t) = e j arctan(Q(t)/I (t))

(12.4)

Due to the nonlinear operations of (12.3) and (12.4), the bandwidths of the amplitude signal A(t) and the phase signal are much wider than that of baseband signal. This imposes practical challenges to the traditional EER transmitter, and typically limits it to narrow-bandwidth applications [20,21]. By contrast, the ET system requires a lower envelope amplifier bandwidth and less precise time alignment between the envelope and RF paths [22]. Therefore, it is more easily applied to applications requiring a wide signal bandwidth, such as OFDM. The use of wideband ET techniques can boost the RF PA drain–collector average efficiency, but the total system efficiency is determined by the product of the envelope amplifier efficiency and the RF transistor drain–collector efficiency [23–25]. Thus, a high-efficiency envelope amplifier design is critical to the EER/ET system. This design is itself quite challenging, since the amplifier needs to provide a signal to a load (the power amplifier collector or drain ) of several ohms or less, at a frequency of well over 20 MHz. For example, for 802.11g applications, for a 3.3-V supply voltage and a 9-dB PAR signal, the equivalent load impedance for the envelope amplifier is

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approximately 5  for a 40% efficiency power amplifier when the output power is 19 dBm. The high-efficiency envelope amplifier is usually realized by a dc/dc converter whose switching frequency is several times the signal bandwidth [26]. For narrowbandwidth applications, most high-efficiency switching mode dc/dc converters for power amplifier applications are realized by traditional delta-sigma [27] or pulsewidth modulation (PWM) [28] modulators. However, the high switching frequency introduces a significant switching loss for a wideband signal. For example, a 20-MHz envelope bandwidth is required for an 802.11g OFDM signal for low EVM, so the switching frequency of the traditional dc/dc converter needs to be on the order of 100 MHz, which can introduce a significant switching loss and out-of-band switching noise. To overcome the trade-off between efficiency and bandwidth of the traditional dc/dc converter, a combination of linear amplification and switchingmode converter may be used. To this end, a feedforward topology is proposed in [29]. We have explored a combination of a linear stage and a switching-mode stage in a feedback loop, which we term linear control of delta modulation (LCDM). A similar topology was originally proposed to improve the fidelity of the class D audio amplifier [30,31]. A block diagram of this approach is shown in Fig. 12.10 [23]. The nonlinear transformation from I (t) and Q(t) to the envelope signal A(t) will greatly expand the envelope signal bandwidth. However, most of the energy is concentrated from dc to 20 kHz (e.g., more than 85% for an OFDM waveform), and 99% of the energy is concentrated below the signal RF bandwidth of 20 MHz. This characteristic of the signal energy implies that a “split-band” envelope amplifier using LCDM can achieve a high efficiency over a wide bandwidth. The split-band envelope amplifier is composed of a wideband (but rather low efficiency) linear stage and a high-efficiency narrowband switching stage, where the overall efficiency is a combination of the two efficiencies. In this case, a high-efficiency switching amplifier operates in parallel with a linear op-amp-based amplifier. The linear amplifier supplies the current to the RF power amplifier when the switching stage cannot respond quickly enough, and the switch stage operates by sensing the current supplied by the linear stage. A hysteretic current feedback control is used to realize the smooth power split between switch stage and linear stage amplification, as shown in Fig. 12.10. Figure 12.10(a) shows the circuit implementation of the envelope amplifier using an op-amp as the linear voltage source and buck converter as the current source (switch stage). The current feedback control is composed of a current sense resistor Rsense , which senses the current direction, and a hysteretic comparator to control the singlepole-double-throw switch, consisting of a PMOS and NMOS transistor. The inductor L is alternately switched between VD D and ground under control of the comparator, whose output is controlled by current supplied by the linear stage. The gain of the comparator operates to set the current supplied by the linear stage to zero, but as shown in Fig. 12.10(b), the integration function performed by the inductor limits the bandwidth of the loop response. The current flowing through the linear stage is minimized with respect to an error signal in the current feedback.

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LINEARITY AND EFFICIENCY STRATEGIES FOR WIRELESS COMMUNICATIONS VDD Hysteresis comparator

L

-h h

isw Vs

Rsense RF PA RF output

RF input

(a)

Vo(t)

iload (t) 1 R load isw(t)

ilin(t)

Rsense

1 L

-h

h

Vs (t) vquantize (t)

vcomp(t) vL(t)dt

vL(t)

(b)

FIGURE 12.10 Envelope tracking split-band amplifier: (a) schematic diagram of envelope amplifier; (b) signal flow graph representation of the system [23].

The switching frequency of this stage is determined by the hysteresis of the comparator, and an increase in hysteresis causes an increase in the time required for the comparator output to change states, lowering the frequency. Also, here, the average switching frequency is less than the envelope modulation frequency, which is beneficial for minimizing the switching loss and the out-of-band switching emissions. When the average slew rate required by the load current exceeds the average slew rate that the switch stage can provide, the input ac signal exceeds the slew rate limitation of the switch stage. In this case, the switching frequency becomes equal to the envelope modulation frequency, and the linear stage provides a large portion of the load current. For the envelope amplifier designer, the goal is to maximize the circuit efficiency and at the same time to maintain the high fidelity of the signal. From simulations, a hysteresis value of roughly 10 mV provides an optimized switching frequency with respect to efficiency for this application, as well as a low EVM for an 802.11g signal. The operational amplifier must be designed for a wide gain–bandwidth product and a low dc power consumption, so a class AB output stage is typically employed.

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The switch stage realized by a buck converter requires an off-chip inductor whose value is typically several microhenries. Along with the linear stage, the efficiency of the buck converter stage is critical for achieving a high overall efficiency. The power lost by the switch stage is dominated by three factors: conduction loss (Ron loss) when the switcher PMOS or NMOS transistor is on, commutation loss due to the PMOS nonzero turn-on and turn-off time, and the power consumption of the switch drivers. The output of the envelope amplifier has to be time-aligned to the output of the RF amplifier, so that extra distortion is not created by the resulting time mismatch between the two paths. Fortunately, the wideband ET system is less sensitive than the traditional EER amplifier to this misalignment effect, so the effect on EVM of a small misalignment is negligible. 12.3.3

Digital Modulation of Switching-Mode Power Amplifiers

Another efficiency enhancement technique is the use of switching-mode power amplifiers, such as class E or class S, which can approach 100% power-added efficiency under certain conditions. But due to their essentially binary mode of operation (they are either “on” or “off”), it is not possible to impress amplitude information onto the resulting signal. As shown in Fig. 12.11(a), the digital modulation of switchingmode amplifiers technique attempts to modulate the envelope through noise-shaping techniques, most typically with a delta-sigma modulator [32]. One of the advantages of this architecture is that it has a 1-bit output stream, so that the DAC requirements are alleviated. In addition, the RF filtering can be done before the power amplifier (PA), so a conventional PA can be used if desired. This approach represents a great opportunity for a radical improvement in PA efficiency and is analogous to pulsewidth-modulated audio amplifiers, but there are a number of practical challenges. For RF signals centered at several gigahertz, the oversampling of the carrier will require enormous digital clock rates and result in high power dissipation. In [33] [Fig. 12.11(b)], a bandpass delta-sigma modulator was employed, reducing the switching frequency requirements by roughly a factor of 4, but this is still quite high. Another approach, which will require considerably less dc power, shown in Fig. 12.11(c), is to quantize the I/Q envelope data to three levels at baseband using a low-frequency delta-sigma modulator, and then up-convert the resulting signal using standard RF vector modulation [34]. The combined signal maintains its constant amplitude (which is required for switching-mode operation) simply by applying a “1010” mask (the I “LO”) to the I channel and a “0101” mask (the Q “LO”) to the Q-channel prior to combining. All of these digital modulation of switching-mode amplifier approaches suffer from two fundamental problems. The first is that the high level of quantization noise extends into other frequency bands, even as it is suppressed in the band desired. In low-frequency data converter and frequency synthesizer applications, this noise is filtered out of the band of interest in a straightforward manner. But the stringent outof-band and receive band spurious emission requirements of most cellular systems, combined with the poor isolation inevitable at high frequencies, make this filtering

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I Q

Switching Mode PA Digital Upconverter

BPDS Modulator (a)

+

+

+

Input z-2

+

Output z-2 z-2

(b)

I

BPDS Modulator

Digital Template

Q

BPDS Modulator

Digital Template

Switching Mode PA +

I/Q

(c)

FIGURE 12.11 (a) Switching-mode RF power amplifiers modulated with bandpass deltasigma modulators; (b) implementation of a bandpass delta-sigma modulator [33]; (c) lowerspeed baseband delta-sigma modulation of switching-mode amplifiers [34].

almost impossible to achieve at RF. Second, although the power efficiency of the switching-mode amplifier itself might be very high, the dc power consumption of the delta-sigma modulator and driver stages represents a significant overhead. As Professor Tom Lee succinctly put it: “The switch (and its drive circuitry) has to be n times faster than in a non-PWM amplifier, where n is the desired dynamic range” [35]. For high-dynamic-range signals, the switching speed requirements are prohibitive for the near-term future. 12.4

TECHNIQUES FOR LINEARITY ENHANCEMENT

The second aspect of the challenge of power amplifier design for modern wireless communications devices is one of linearity enhancement. The techniques developed in Section 12.2 have the disadvantage that they degrade the linearity of the amplifier in order to achieve higher efficiency. Can the linearity be recovered through other techniques, and will the resulting system exhibit better overall performance after the linearity enhancement techniques have been employed? In most cases, there is an overall improvement in both linearity and efficiency, although the techniques to achieve these improvements are often expensive and complicated.

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Out Out Out

In

In HPA

In Input

In

Out

PreDistorter

Output

FIGURE 12.12 Predistortion adds a series inverse nonlinearity to the power amplifier. The combination of the two creates a linear input/output transfer function.

One of the simplest approaches for the improvement of linearity in the transmitter power amplifier is the well-known technique of predistortion. A typical power amplifier exhibits gain compression at high input powers, which results in AM-AM distortion. It also exhibits excess phase shift at high input powers, which results in AM-PM conversion. Together, these effects create distortion and intermodulation in the high power output of the amplifier, degrading the ACPR and EVM performance. If the input signal to the power amplifier could be “predistorted” with the inverse of its own nonlinearity, the overall effect of the nonlinearity could be canceled out. This is shown conceptually in Fig. 12.12, where an analog or RF predistortion circuit compensates for both the gain and phase nonlinearity of the amplifier circuit. The predistortion circuit would typically exhibit both gain and phase expansion at high input power levels, since a typical power amplifier exhibits gain and phase compression at high output power levels. Although straightforward in principle, the predistortion approach suffers from several practical drawbacks. First, it is very difficult to track precisely the effects of temperature, process, and power supply variations on the characteristics of the power amplifier nonlinearity. This is a serious drawback, because the amount of acceptable distortion in a typical system is very low, and a small offset in the characteristics of the power amplifier and the predistortion circuit can create substantial out-of-band interference. The practical limitations of the predistortion concept have naturally led to the development of more robust techniques for achieving power amplifier linearization. The traditional linearization technique for nonlinear analog systems is linear feedback. With appropriate feedback, the loop itself naturally compensates for the nonlinear transfer function of the nonlinear power amplifier. An example of a hypothetical linear feedback approach for a power amplifier is illustrated in Fig. 12.13(a). In this system, an operational amplifier supplies the necessary “predistortion” of the signal in response to the difference between the (distorted) output signal and the desired input signal. This straightforward approach has the obvious limitation that operational amplifiers with the required bandwidth and drive capability do not exist at microwave frequencies. Furthermore, the phase shift associated with a typical power amplifier

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Operational Amplifier

Power Amplifier

+

Input

-

(a)

Operational Amplifier

Input

Power Amplifier

+

-

Coupler VGA

(b)

Operational Amplifier

I Input

Power Amplifier

+

-

/2

+ Coupler

Q Input

+

-

VGA /2

(c)

FIGURE 12.13 Amplifier linearization using feedback: (a) simplified view of feedback linearization approach; (b) use of a frequency-translating down-converter to achieve linearization; (c) Cartesian feedback applied to provide both gain and phase correction.

is highly variable, making unconditional stability of the feedback circuit difficult to achieve under a wide range of conditions. Providing the feedback at lower frequencies, where operational amplifiers have sufficient bandwidth, by down-converting the amplified signal to baseband frequencies is one possibility, as shown in Fig. 12.13(b). The drawback of this approach is

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that the down-conversion mixers have to be as linear as the output signal desired. This is not a problem in most cases, since only a small portion of the output signal is required for feedback purposes. Another problem is the excess and variable phase shift through the power amplifier/down-conversion mixer/lowpass filter combination, which is difficult to control at microwave frequencies and varies depending on the power level. An additional phase shift is therefore often added to the input to the mixer to ensure stability under all conditions, and this phase shift must be carefully controlled over process, temperature, and power supply variations. The feedback approach is also prone to problems associated with amplifier saturation and rapid changes in output VSWR [36]. Digital modulation techniques typically require up-conversion of both the I and Q baseband signals. As a result, feedback is typically applied to both paths of the power amplifier inputs, with a technique known as Cartesian feedback, shown in Fig. 12.13(c). Cartesian feedback has been an active research topic for many years [37] but has not yet achieved widespread adoption. The myriad of problems associated with the predistortion approaches—both openloop and feedback—point to an opportunity for alternative solutions. Rather than predistorting the input signal, it might be more effective to measure the nonlinearity of the power amplifier, subtract the error generated by the nonlinearity from the “ideal” signal, amplify the difference, and then subtract that difference (which is the error) from the amplifier output. The result would be an “error-free” amplification of the input signal. This approach, although seemingly complicated, has been used successfully for many years to linearize satellite traveling-wave tube amplifiers (TWTAs) and is known as the feedforward approach [38,39]. It is illustrated schematically in Fig. 12.14. Feedforward techniques for amplifier linearization actually predate the use of feedback techniques; both were developed by Black in the 1930s to solve the problem of linearization for telephone network repeater amplifiers. A close examination of Fig. 12.14 illustrates the reason that feedback techniques quickly supplanted those of feedforward for most lower-frequency applications. First, the gain and phase matching between the two input paths of the subtractor circuit must be very precisely matched to achieve acceptable cancellation of the distortion products. Second, the gain of the error amplifier must precisely track the gain of the power amplifier itself. Finally, the phase shift through the final phase-shift network and hybrid coupler

In

HPA

HPA

f

f

Vector Modulator

Vector Modulator

Nulling Loop

FIGURE 12.14

Out

Error Loop

Feedforward predistortion of nonlinear power amplifiers.

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I Q

Complex Multiply

LUT

FIGURE 12.15

DAC DAC

Output

Quad. Modulator Power Amplifier

Simplified schematic of digital predistortion employing table look-up [40].

must precisely track the gain and phase shift of the power amplifier. Despite these apparent obstacles, the use of feedforward approaches has several adherents, although it is typically employed in base station and higher-frequency circuits, where power efficiency is less important than absolute linearity. Another possible approach with improved robustness is to perform the predistortion using digital techniques at baseband frequencies if the appropriate transformation function for the predistorter were known in advance. This technique is illustrated in Fig. 12.15 and is known as adaptive predistortion [40]. In this case, the AM-AM and AM-PM distortion through the amplifier is “measured,” and these data are then fed to a digital signal processor that provides the appropriate predistorted in-phase and quadrature-phase signals for the baseband upconverter. Of course, the problem is that the ideal transfer function for the predistorter varies with time, so the algorithm performing the predistortion must be updated periodically. Several different versions of adaptive predistortion have been developed [41,42]. The field of adaptive digital predistortion has a long history [43] and has found increasing acceptance in the base station field, replacing analog feedforward techniques in recent years. With the increasing sophistication of DSP techniques, as well as lower-power high-speed DACs, adaptive digital predistortion has recently become possible for mobile terminals as well [44]. As shown in Fig. 12.15, the digital baseband signal is essentially scaled by the inverse of the PA nonlinearity in the predistortion section; and when the resulting signal is fed to the nonlinear PA, the output is “ideally” perfectly linear. There are several limitations to adaptive digital predistortion: significant bandwidth expansion, a relatively high digital processing overhead, and a susceptibility to memory effects (long-time constant variations in the PA gain and phase responses that are difficult to incorporate into the predistorter transfer function). In addition, the predistortion coefficients require constant updating, due to aging, temperature, and power supply variation effects over long periods of time. In an era of CMOS of 90 nm and below, the first two limitations are becoming less significant, and there have been a number of recent attempts to compensate for memory effects. Adaptive digital predistortion works best for standards requiring a high PAR (from Table 21.1) and moderate-low PCDR, such as base stations, wireless LAN cards, and EDGE. It also works best in conjunction with efficiency

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enhancements schemes such as the Doherty amplifier or envelope tracking/EER, since it does little to enhance the overall efficiency of the basic amplifier, but it can have an enormous effect on linearity. Typically, the baseband AM-AM and AM-PM behavior of the power amplifier can be modeled by a complex polynomial of the form yn = xn

m 

ak |xn |k−1

(12.5)

k=1

where y is the instantaneous complex baseband output, x is the instantaneous complex baseband input to the power amplifier, and the a coefficients are the complex gain of the amplifier. Once these coefficients are known, the nonlinearity can be inverted in the digital baseband through a complex series reversion and the nonlinearity eliminated. A table-based look-up scheme, with an entry for each predistorted point in the signal constellation, is most commonly employed to minimize the computational requirements. The optimum size of the look-up table has been the subject of intense research over the years [45,46], and it can grow to enormous proportions quickly. For instance, a 10-bit input predistorter (with 14 bits of output) that addresses 12 different channels can require well over 106 bits! However, the optimum size is often limited by analog circuit limitations such as quadrature modulator inaccuracies and carrier leakage [47], and a variety of pruning strategies have been developed to minimize the size of the look-up table to reasonable dimensions [40]. Another limitation of digital predistortion is the bandwidth expansion that results from the predistortion. This puts a greater burden on the sampling rate of the DAC as well as the bandwidth of subsequent RF stages. The magnitude of the bandwidth expansion depends on the desired linearity improvement; if IM3 is the main source of the undesirable distortion, a bandwidth expansion by a factor of 3 is required. This is illustrated experimentally from the spectrum analyzer plots in Fig. 12.16 [2]. Long-time constant memory effects can have a significant impact on the improvement achievable with adaptive digital predistortion. Memory effects (due to thermal effects, surface traps, or dc bias effects) introduce a time dependence into the a coefficients. Their effect on the gain response can be seen in Fig. 12.17, which shows the before and after AM-AM plots of digital predistortion applied to a CDMA amplifier [49]. The linearity of the gain response is improved, but the “haze” around the lines in Fig.s 12.17(a) and (b) indicates the presence of memory effects; the output amplitude depends on the previous values of the input as well as the current value. This effect can degrade both the EVM and ACPR of the amplifier. The memory effects can be modeled with a revision to (12.5) to a new expression of the form yn =

M  m=0

xn−m

K 

ak,m |xn−m |k−1

(12.6)

k=1

where the memory effects of the amplifier are included in the model back to time M T , where T is the sample rate of the system. Again, once the ak,m are known, the

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(a)

(b)

(c)

FIGURE 12.16 Example of bandwidth expansion effects of digital predistortion: (a) original input signal; (b) spectrum of predistorted signal with bandwidth expansion; (c) output spectrum.

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FIGURE 12.17 Measured AM-AM response of a CDMA power amplifier before (a) and after (b) memoryless predistortion, and (c) with predistortion and memory effect correction [49].

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PA Isolator

PLL VCO DeltaSigma

D/A

Modulator (a) PA

VCO

Downconversion Gain Control

PLL

Amplitude Control Loop I Q

Modulator (b) Amplitude

I Q

Modulator

Switching Supply

Phase PA

VCO

(c)

FIGURE 12.18 (a) Polar modulation, (b) polar loop modulation, and (c) envelope elimination and restoration or envelope tracking when the output of the modulator contains both amplitude and phase information, and the PA is operated in the linear mode.

function can be inverted in the digital domain and the desired linear response obtained. In this case, it is difficult to find an analytical solution for the inverse polynomial function once the coefficients are known, and iterative procedures are required [48]. An example of the improvement in memory effects can be seen in Fig. 12.17, where the memory effects were measured and predistorted using results from (12.6) [49].

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CONCLUSIONS

371

We expect digital predistortion techniques to have a significant impact on mobile power amplifiers in the coming years. EER and ET can operate in either open-loop [Fig. 12.18(a)] or closed-loop mode [Fig. 12.18(b)]. Open-loop operation suffers from the inevitable errors associated with open-loop operation of any analog system, and polar-loop techniques exhibit limited bandwidth. These dilemmas can be partially addressed through digital compensation approaches. For example, digital predistortion can be used to compensate for the nonlinear AM-AM response of the digitally controlled switching-mode power amplifier in the AM path (as discussed in Section12.2), and a digital preemphasis filter to compensate for the frequency response of the frequency synthesizer in the phase modulator. In these ET and EER amplifiers, the alignment between the magnitude and phase paths is critical to achieving the lowest possible EVM. An adaptive real-time timealignment technique is needed because of inevitable environmental variations. For example, a time alignment of better than 2 ns is required to make the EVM lower than 3% for an OFDM 802.11a/g signal [23]. In this case, the signal bandwidth is approximately 20 MHz, and with a data converter sample rate of approximately 100 MHz, linear interpolation is required to achieve the necessary subsample delay accuracy.

12.5

CONCLUSIONS

The use of digital techniques to correct the imperfections and limitations of RF power amplifiers represents the next stage of development for high-frequency wireless devices, especially since transistor technology is nearly “maxed-out” in performance. In the near term, digital predistortion will move from the realm of the base station and into the handset environment. In the longer term, completely digital approaches for modulation will dominate for the highest possible efficiency. These new approaches will lead to dramatic improvements in the efficiency and bandwidth capabilities of multi-mode wireless transmitters. Acknowledgments The authors wish to thank Professors Ian Galton and Gabriel Rebeiz of UCSD and Leo DeVreede of TU Delft for valuable discussions. They would also like to acknowledge the entire power amplifier research group at UCSD, who contributed to this work: Feipeng Wang, Pavel Kolinko, Johana Yan, Myoungbo Kwak, Paul Draxler, Yu Zhao, Chia Hsia, Junxiong Deng, Chengzhou Wang, Jinh Jeong, Tsai Pi Hung, Jeremy Rhode, Tomas Osullivan, Ming Li, and Sataporn Pornpromlikit. We also acknowledge the generous support of Ericsson; Nokia; Conexant; Motorola; Freescale; Cree; Nitronex; the UCSD Center for Wireless Communications and its director, Pamela Cosman; the UC Discovery Grant Program; and the California Institute for Telecommunications and Information Technology and its directors, Larry Smarr and Ramesh Rao.

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REFERENCES 1. Characterizing Digitally Modulated Signals with CCDF Curves. Agilent Application Note. 2001. 2. P. Asbeck and L. Larson, “Synergistic design of DSP and power amplifiers for wireless communications,” in 2000 Asia-Pacific Microwave Conference, pp. 899–903, Dec. 3–6, 2000. 3. W. Doherty, “A new high efficiency power amplifier for modulated waves,” Proc. IRE, vol. 24, no. 9, pp. 1163–1182, Sept. 1936. 4. Y. Zhao, A. Metzger, P. Zampardi, M. Iwamoto, and P. Asbeck, “Linearity improvement of HBT-based Doherty power amplifiers based on a simple analytical model,” in 2006 IEEE MTT-S International Microwave Symposium Digest, pp. 877–880, June 2006. 5. Y. Zhao, M. Iwamoto, L. Larson, and P. Asbeck, “Doherty amplifier with DSP control to improve performance in CDMA operation,” in 2003 IEEE MTT-S International Microwave Symposium Digest, vol. 2, pp. 687–690, June 8–13, 2003. 6. H. Chireix, “High power outphasing modulation,” Proc. IRE, vol. 23, no. 9, pp. 1370–1392, Nov. 1935. 7. F. Raab, “Drive modulation in Kahn-technique transmitters,” in 1999 IEEE MTT-S International Microwave Symposium Digest, vol. 2, pp. 811–814, June 13–19, 1999. 8. F. Raab and D. Rupp, “High-efficiency single-sideband HF/VHF transmitter based upon envelope elimination and restoration,” in Sixth International Conference on HF Radio Systems and Techniques, 1994, pp. 21–25, July 4–7, 1994. 9. F. Raab, B. Sigmon, R. Myers, and R. Jackson, “High-efficiency L-band Kahn-technique transmitter,” in 1998 IEEE MTT-S International Microwave Symposium Digest, vol. 2, pp. 585–588, June 7–12, 1998. 10. F. Raab and D. Rupp, “High-efficiency multimode HF/VHF transmitter for communication and jamming,” in Conference Record, 1994 IEEE Military Communications Conference (MILCOM’94), vol. 3, pp. 880–884, Oct. 2–5, 1994. 11. D. Su and W. McFarland, “An IC for linearizing RF power amplifiers using envelope elimination and restoration,” in Digest of Technical Papers, IEEE 45th International Solid-State Circuits Conference (ISSCC’98), pp. 54–55, 412, Feb. 5–7, 1998. 12. G. Hanington, P. Chen, V. Radisic, T. Itoh, and P. Asbeck, “Microwave power amplifier efficiency improvement with a 10 MHz HBT dc–dc converter,” in 1998 IEEE MTT-S International Microwave Symposium Digest, vol. 2, pp. 589–592, June 7–12, 1998. 13. N. Schlumpf, M. Declercq, and C. Dehollain, “A fast modulator for dynamic supply linear RF power amplifier,” in Proc. 29th European Solid-State Circuits Conference, (ESSCIRC’03), pp. 429–432, Sept. 16–18, 2003. 14. S. Cripps, RF Power Amplifiers for Wireless Communications. Norwood, MA: Artech House, 1999. 15. F. Wang, A. Ojo, D. Kimball, P. Asbeck, and L. Larson, “Envelope tracking power amplifier with pre-distortion linearization for WLAN 802.11g,” in 2004 IEEE MTT-S International Microwave Symposium Digest, vol. 3, pp. 1543–1546, June 6–11, 2004. 16. J. Staudinger, B. Gilsdorf, D. Newman, G. Norris, G. Sadowniczak, R. Sherman, and T. Quach, “High efficiency CDMA RF power amplifier using dynamic envelope tracking technique,” in 2000 IEEE MTT-S International Microwave Symposium Digest, vol. 2, pp. 873–876, June 11–16, 2000.

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17. B. Sahu and G. Rincon-Mora, “A high-efficiency, dual-mode, dynamic, buck-boost power supply IC for portable applications,” in 18th International Conference on VLSI Design, 2005, pp. 858–861, Jan. 3–7, 2005. 18. J. Groe and L. Larson, CDMA Mobile Radio Design. Norwood, MA: Artech House, 2000. 19. T. Sowlati, Y. Greshishchev, C. T. Salama, G. Rabjohn, and J. Sitch, “Linear transmitter design using high efficiency class E power amplifier,” in Personal, Indoor and Mobile Radio Communications, 1995 (PIMRC’95), Sixth IEEE International Symposium on “Wireless: Merging onto the Information Superhighway,” vol. 3, p. 1233, Sept. 27–29, 1995. 20. T. Sowlati, D. Rozenblit, E. MacCarthy, M. Damgaard, R. Pullela, D. Koh, and D. Ripley, “Quad-band GSM/GPRS/EDGE polar loop transmitter,” in Digest of Technical Papers, (IEEE International Solid-State Circuits Conference, 2004 (ISSCC’04), vol. 1, pp. 186– 521, Feb. 15–19, 2004. 21. A. Hietala, “A quad-band 8PSK/GMSK polar transceiver,” in Digest of Papers, 2005 IEEE, Radio Frequency Integrated Circuits (RFIC) Symposium, 2005. pp. 9–12, June, 12–14, 2005. 22. D. Kimball, L. Larson, F. Wang, A. Yang, and P. Asbeck, “Design of wide-bandwidth envelope tracking power amplifiers for OFDM applications,” IEEE Trans. Microwave Theory Tech., vol. 53, pp. 1244–1255, Apr. 2005. 23. F. Wang, D. Kimball, J. Popp, A. Yang, D. Lie, P. Asbeck, and L. Larson, “Wideband envelope elimination and restoration power amplifier with high efficiency wideband envelope amplifier for WLAN 802.11g applications,” in 2005 IEEE MTT-S International Microwave Symposium Digest, p. 4, June 12–17, 2005. 24. J.-H. Chen, K. U-yen, and J. Stevenson Kenney, “An envelope elimination and restoration power amplifier using a CMOS dynamic power supply circuit,” in 2004 IEEE MTT-S International Microwave Symposium Digest, vol. 3, pp. 1519–1522, June 6–11, 2004. 25. J. Popp, D. Lie, F. Wang, D. Kimball, and L. Larson, “Fully-integrated highly-efficient RF class E SiGe power amplifier with an envelope-tracking technique for EDGE applications,” in 2006 IEEE Radio and Wireless Symposium, pp. 231–234, Jan. 17–19, 2006. 26. D. Milosevic, J. van der Tang, and A. van Roermund, “Intermodulation products in the EER technique applied to class-E amplifiers,” in Proceedings of the 2004 International Symposium on Circuits and Systems, (ISCAS’04), vol. 1, pp. I-637 to I-640, May 23–26, 2004. 27. D. Anderson and W. Cantrell, “High-efficiency high-level modulator for use in dynamic envelope tracking CDMA RF power amplifiers,” in 2001 IEEE MTT-S International Microwave Symposium Digest, vol. 3, pp. 1509–1512, May 20–25, 2001. 28. S. Abedinpour, I. Deligoz, J. Desai, M. Figiel, and S. Kiaei, “Monolithic supply modulated RF power amplifier and dc–dc power converter IC,” in 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 603–606, June 8–10, 2003. 29. F. Raab, “Split-band modulator for Kahn-technique transmitters,” in 2004 IEEE MTT-S International Microwave Symposium Digest, vol. 2, pp. 887–890, June 6–11, 2004. 30. R. van der Zee and A. van Tuijl, “A power efficient audio amplifier combining switching and linear techniques,” in Proceedings of the 24th European Solid-State Circuits Conference (ESSCIRC’98)., pp. 288–291, Sept. 22–24, 1998. 31. N.-S. Jung, N.-I. Kim, and G.-H. Cho, “A new high-efficiency and super-fidelity analog audio amplifier with the aid of digital switching amplifier: class K amplifier,” in 29th Annual

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IEEE Power Electronics Specialists Conference (PESC’98) Record, vol. 1, pp. 457–463, May 17–22, 1998. J. Keyzer, J. Hinrichs, A. Metzger, M. Iwamoto, I. Galton, and P. Asbeck, “Digital generation of RF signals for wireless communications with band-pass delta-sigma modulation,” in 2001 IEEE MTT-S International Microwave Symposium Digest, vol. 3, pp. 2127–2130, May 20–25, 2001. M. Iwamoto, A. Williams, P.-F. Chen, A. Metzger, C. Wang, L. Larson, and P. Asbeck, “An extended Doherty amplifier with high efficiency over a wide power range,” in 2001 IEEE MTT-S International Microwave Symposium Digest, vol. 2, pp. 931–934, May 20–25, 2001. Y. Wang, “A class-S RF amplifier architecture with envelope delta-sigma modulation,” in IEEE Radio and Wireless Conference (RAWCON’02), pp. 177–179, Aug. 11–14, 2002. T. Lee, Planar Microwave Engineering. New York: Cambridge University Press, 2004. J. Dawson and T. Lee, “Automatic phase alignment for a fully integrated CMOS Cartesian feedback power amplifier system,” in 2003 IEEE International Solid-State Circuits Conference (ISSCC’03), Digest of Technical Papers, vol.1, pp. 262–492, 2003. ——, “Cartesian feedback for RF power amplifier linearization,” in Proceedings of the 2004 American Control Conference, vol. 1, pp. 361–366, June 30–July 2, 2004. I. Kim, J. Cha, S. Hong, Y. Y. Woo, J. Kim, and B. Kim, “Predistortion power amplifier for base-station using a feedforward loop linearizer,” in 36th European Microwave Conference, 2006, pp. 141–144, Sept. 10–15, 2006. E. Jeckeln, F. Ghannouchi, M. Sawan, and F. Beauregard, “Efficient baseband/RF feedforward linearizer through a mirror power amplifier using software-defined radio and quadrature digital up-conversion,” in 2001 IEEE MTT-S International Microwave Symposium Digest, vol. 2, pp. 789–792, May 20–25, 2001. Y. Park, W. Woo, R. Raich, J. Stevenson Kenney, and G. Zhou, “Adaptive predistortion linearization of RF power amplifiers using lookup tables generated from subsampled data,” in IEEE Radio and Wireless Conference, 2002 (RAWCON’02), pp. 233–236, Aug. 11–14, 2002. Y. Seto, S. Mizuta, K. Oosaki, and Y. Akaiwa, “An adaptive predistortion method for linear power amplifiers,” in IEEE 51st Vehicular Technology Conference Proceedings, 2000 (VTC’00 Spring), Tokyo, 2000, vol. 3, pp. 1889–1893, May 15–18, 2000. E. Cottais, Y. Wang, and S. Toutain, “Experimental results of power amplifiers linearization using adaptive baseband digital predistortion,” in 2005 European Microwave Conference, vol. 3, p. 4, Oct. 4–6, 2005. K. Arimochi, S. Sampei, and N. Morinaga, “Adaptive modulation system with discrete power control and predistortion-type nonlinear compensation for high spectral efficient and high power efficient wireless communication systems,” in 8th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, 1997 (PIMRC’97), “Waves of the Year 2000,” vol. 2, pp. 472–476, Sept. 1–4, 1997. J. Cavers, “The effect of quadrature modulator and demodulator errors on adaptive digital predistorters,” in IEEE 46th Vehicular Technology Conference, 1996, “Mobile Technology for the Human Race,” vol. 2, pp. 1205–1209, Apr. 28–May 1, 1996. K. Lee and P. Gardner, “Effects of demodulator errors on convergence time of look-up table based iterative algorithms for adaptive digital predistortion linearizer,” in 47th Midwest

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CMOS RF Power Amplifiers for Mobile Communications PATRICK REYNAERT Katholieke Universiteit Leuven, Leuven, Belgium

13.1

INTRODUCTION

It somehow seems that the integration of RF power amplifiers (PAs) in CMOS is not very obvious, especially not when compared to the successful integration of RF transceivers in CMOS. The first research efforts to integrated transceivers in CMOS were, indeed, focused on the receiver part. Given the demanding specifications on sensitivity, phase noise, and blocker levels, this is, of course, not surprising. Designing circuits that meet these stringent system-level specifications is definitely not obvious. But from the same system-level point of view, the transmiter part looks pretty simple. A direct up-conversion mixer followed by a power amplifier, and that’s it, right? That PA can be modeled by AM-AM and AM-PM distortion curves or by a Taylor series expansion, and one has to be careful about carrier leakage and noise transmitted in the receiver band, but what other problems might there be from a system point of view? As always with circuits that make the interface to the outside world, the true trade-off picture is less clear. Whereas, for example, a down-conversion mixer is nicely embedded between an LNA and an ADC, the PA and the LNA see the outside world, so they also meet another environment and other technologies (SAW filters, duplexers, baluns, and many other discrete components mounted on the PCB). And where the LNA meets the limits of noise, the PA is limited by the power capability of CMOS. Since this power, both dc and RF, also flows through the package, the tradeoffs in CMOS PA design are heavily connected to the limitations of the external technology and circuitry. So the story of CMOS RF PA design is cross-connected with other engineering fields, such as packaging, antenna, and PCB design. This cross-connection makes it difficult, or at least a little more subtle, to have a clear view of the different trade-offs that RF-CMOS designers face when they aim at fully integrated CMOS PA. Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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CHALLENGES

The typical circuit-level challenges for the integration of RF power amplifiers in a CMOS technology are the low supply voltage, the need for a high peak and average efficiency, the power control dynamic range requirements, and the high linearity requirements. But the design of a power amplifier is not restricted to the challenges noted above. It also faces many other implementation challenges, such as reliability, VSWR robustness, heat dissipation, packaging, and many others. In what follows, some key challenges are clarified in more detail.

13.3

LOW SUPPLY VOLTAGE

When we talk about CMOS, we talk about low supply voltage. Indeed, Fig. 13.1 shows the well-known reduction in supply voltage of CMOS technologies that we have witnessed in recent years. Since the supply voltage determines the RF voltage swing, and the square of the RF voltage swing relates to output power, this trend toward a low supply voltage directly affects the output power. 13.3.1

Impedance Transformation

The most common circuit technique used to achieve sufficient output power despite a low supply voltage is an impedance transformation network or matching network. Perhaps the most common network is the L-match network shown in Fig. 13.2. Such a network changes the impedance levels, meaning that the voltage and current 6

5

4 voltage [V]

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0 1000

100 technology node [nm]

FIGURE 13.1 CMOS supply voltage scaling.

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impedance transformation network RLm PA Lm RL

Rm

Cm

FIGURE 13.2 L-match network used as impedance transformation to increase the power delivered to the load.

generated by the low-voltage CMOS PA are converted to a higher voltage and lower current signal at the 50-
load. In other words, the PA itself sees an impedance Rm much smaller than R L . The impedance transformation ratio r is equal to the ratio of R L to Rm : r=

RL = Q 2m + 1 ≈ Q 2m Rm

(13.1)

The inductor and capacitor are easily calculated as Q m Rm ω 1 Cm = 2 ω Lm Lm =

(13.2) (13.3)

Although the simple L-match network is a perfect candidate for integration in CMOS, the biggest problem with this type of matching network is the inherent low efficiency for a high-impedance transformation ratio r . And high r is exactly what is needed at a low supply voltage. Loss of the matching inductor L m dominates the efficiency of the matching network. If the loss of this inductor is, for simplicity, modeled as a series resistance R Lm as shown in Fig. 13.2, the quality factor of the inductor is equal to QL =

ωL m R Lm

(13.4)

The series loss resistance can also be written as R Lm = Rm

Qm 1 RL ≈√ QL r QL

(13.5)

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and the efficiency of the matching network can then be written as ηm =

Pin,m Rm QL QL = = ≈ √ Pout,L Rm + R Lm Q L + Qm QL + r

(13.6)

Clearly, as r increases (i.e., for low voltages), the efficiency decreases for a given inductor quality factor Q L . The main reason for this decreasing efficiency is that Rm √ is proportional to r , whereas R Lm is proportional to 1/ r . Assuming, for example, an ideal class A power amplifier, which generates a sinusoidal output voltage with an amplitude equal to VD D , the output power taking the power loss in R Lm into account can be written as Pout =

VD2 D Rm 2(Rm + R Lm )2

(13.7)

Figure 13.3 shows the efficiency of the L-match network vs. supply voltage for different power levels and inductor quality factors. Clearly, achieving watt-level output power in a CMOS technology using a 1-V supply results in a low power efficiency for the matching network. Two approaches exist to solve this fundamental problem of low efficiency for a high-impedance transformation ratio r . First, low-voltage transistors can be cascoded so that they can reliably handle a higher supply voltage and a higher output power is achieved without the need for a large impedance transformation ratio r . Second, several low-voltage power amplifiers can be placed in parallel so their output power sums up through a power-combining network. The two approaches are discussed next.

100 80 efficiency [%]

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40

3−Watt,QL=20 20

0.5−Watt,QL=10 0.5−Watt,QL=20

0

0

1

2 3 supply voltage [V]

4

5

FIGURE 13.3 Efficiency of the L-match network vs. supply voltage for different output powers and inductor quality factors.

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13.3.2

381

Stacked Devices

A cascode structure in which two or more transistors are placed on top of each other is commonly referred to as stacked devices. Such a structure can tolerate a higher supply voltage, thus resulting in more output power. This relaxes the requirements for the output matching network, meaning that the efficiency of the latter can be higher. A point of attention is the bulk connection of the stacked devices. This bulk cannot be tied to ground since that would raise reliability issues for the gate oxide. The bulk of the stacked devices indeed needs to be biased to a higher dc voltage, which results in dc leakage in the case of a twin-well process. Therefore, a triple-well process is preferred since the source and bulk can be tied together. In a stacked device solution consisting of more than two devices, the gate of the upper cascode transistors needs to be dynamically biased. To make this biasing more reliable, the voltage information at the drain can be used, as demonstrated by the self-biased cascode structure of [1]. 13.3.3

Power Combining

Power combining refers to solutions where several low-voltage power amplifiers are placed in parallel and their outputs connected together through some kind of powercombining circuitry. Aoki et al. demonstrated the effectiveness of this technique for CMOS [2]. Their distributed active transformer approach efficiently combines several low-voltage power amplifiers and uses a transformer structure for efficient impedance transformation. Haldi et al. demonstrated another solution [3]. Again, transformers are used to combine the output of several amplifiers. Each transformer can operate independently and can thus be turned off, which allows a discrete form of power control. Note that although the transformers themselves have an impedance transformation ratio of 1 : 1, the combining effect increases the impedance transformation ratio by N and the output power by N 2 , with N being the number of transformers and (differential) power amplifiers.

13.4

AVERAGE EFFICIENCY, DYNAMIC RANGE, AND LINEARITY

In Section 13.3 we discussed the challenge of achieving a high output power from a power amplifier operating at a low power supply voltage. To achieve high output power and peak efficiency, either the supply voltage needs to be increased (cascoding) or several power amplifiers (with lower output power) need to be combined. Although it is important to achieve high efficiency at peak output power, it should be realized that a power amplifier does not always operate at peak output power. Indeed, two important mechanisms cause the output power of a power amplifier to be less than its peak value: power control and amplitude modulation. These two mechanisms determine the dynamic range and linearity requirements and are discussed briefly first.

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0.6 0.5 probability density

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0.4 0.3 0.2

rural urban

0.1 0 −30

−20

−10 0 10 20 average output power [dBm]

30

FIGURE 13.4 Probability density function of the average output power due to power control for a CDMA system.

13.4.1

Power Control

Power control is typically controlled by the base station, which regulates the average power transmitted by the mobile device. In TDMA systems, the power transmitted is reduced when the mobile device is close to the base station. The advantage for the user is obvious: The battery lifetime is increased. In CDMA systems, power control plays an even more important role. For optimal performance it is important that all CDMA signals arrive at the base station with equal signal strength. Thus, the power transmitted by each mobile device needs to be tightly controlled to achieve this. As an example, Fig. 13.4 is a sketch of the probability distribution function of the output power for a CDMA system in urban and suburban environments. It can be seen that the most likely output power can be as much as 30 dB lower than the peak output power. It is also clear that power control is a relatively slow process. The output power level is updated the rate of at milliseconds or tens of microseconds. As such, it is possible to reconfigure the PA: for example, by changing the biasing or supply voltage of the PA, depending on the output power requested. 13.4.2

Amplitude Modulation

Amplitude modulation obviously causes a change in the envelope of the RF carrier transmitted, and thus in the instantaneous output power transmitted. Whereas secondgeneration (2G) digital communication systems such as GSM and Bluetooth used only the phase modulation of the carrier, most of the newest high-data-rate systems allow both amplitude and phase variations to increase the data throughput. It should be noted, though, that variations in the envelope of an RF carrier can have two causes related to the modulation. First, these variations can be caused by the location of the constellation points. Indeed, QAM modulation causes a change in

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−0.5

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0

−0.5

−1.5

−1.5

−1

−0.5

(a)

0 x(t)

0.5

1

1.5

(b)

FIGURE 13.5 Unfiltered complex envelope signal for (a) QPSK and (b) π/4-QPSK modulation where two 4-QPSK are rotated by π/4. The trajectory avoids the origin in π/4-QPSK modulation.

both the amplitude and phase of an RF carrier; 8-PSK modulation causes a change only in the phase. A second cause of variations of the envelope of an RF carrier is filtering of the baseband I and Q signals. Changes from one constellation point to the other cannot occur immediately, as this would require an infinite bandwidth. Instead, the I and Q signals are filtered to limit the bandwidth of the up-converted RF spectrum. This filtering will cause both intersymbol interference (ISI) and amplitude variations of the RF carrier. So even for an 8-PSK modulation scheme, for example, where all the constellation points lie on a circle, filtering the I and Q signals will result in a varying envelope of the RF carrier transmitted. Figures 13.5 and 13.6 show how a constant envelope constellation diagram can still result in a nonconstant envelope signal after baseband filtering. 1.5

1.5

1

1

0.5

0.5 y(t)

y(t)

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−0.5

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0 x(t)

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0.5

1

1.5

−1.5

−1.5

−1

−0.5

0 x(t)

0.5

1

1.5

(b)

FIGURE 13.6 Filtered complex envelope signal for (a) QPSK and (b) π/4-QPSK modulation. A root-raised cosine baseband filter (r = 0.35) has been applied.

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Average Efficiency

As the instantaneous output power changes, either by amplitude modulation or by power control, the instantaneous efficiency also changes. One could also think of an average efficiency, defined by the long-term average output power divided by the long-term average dc consumption. This average efficiency can be calculated as ηd  =

Po  Pdc 

(13.8)

with Po the RF output power and Pdc the dc power consumption of the PA. Assuming a one-stage power amplifier, this efficiency is also denoted as the drain or collector efficiency, as it only takes into account quantities that happen at the output terminal of the power transistor. The average efficiency can also be obtained by looking at the statistical distribution of the output power, defined as the probability density function (PDF) of the output power, and written as p(Po ) [4]. If one assumes that the amplifier has no memory effect, the efficiency and dc power consumption of the PA are a function of the instantaneous output power Po , and the calculation above can also be done by using the ηd vs. Po curve, which is actually a steady-state curve. In that case, the average efficiency can be written as





Po,max

Po,max

Po p(Po )d Po ηd  =


Po,min

Po p(Po )d Po =


Po,max

Po,min Po,max

Pdc (Po ) p(Po )d Po Po,min

Po,min

Po p(Po )d Po ηd (Po )

(13.9)

As clarified earlier, one can define two PDF functions of the output power: one due to the amplitude modulation of the carrier, and one due to the power control. Is is clear from the above that the efficiency vs. output power curve plays a crucial role in achieving a high average efficiency and thus a high battery lifetime for a mobile device. So not only is it important to achieve high efficiency at peak output power and low power supply voltage, it is even more important to maintain this high efficiency at reduced output power levels. This brings us to the core of the problem: the efficiency of a class A or AB amplifier quickly drops at lower output power. Indeed, for a class A amplifier, the efficiency is proportional to the output power. For a class B amplifier, the efficiency is proportional to the square root of the output power: 1 Po 2 Po,MAX  Po π η B (Po ) = 4 Po,MAX η A (Po ) =

(13.10)

(13.11)

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385

100

drain efficiency [%]

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80 60 40 20 0 −20

−15 −10 −5 normalized output power [dB]

0

FIGURE 13.7 Efficiency of an ideal class B (solid line) and class A (dashed line) PA vs. output power.

Figure 13.7 shows these efficiencies vs. relative output power. Clearly, backing-off 20 to 30 dB from the peak output power, a typical number for power control, results in a very low efficiency. In other words, a lot of dc power is just wasted in heat. 13.4.4

Linearization and Efficiency Enhancement

It was shown in Section 13.4.3 that the average efficiency is as important as the efficiency at peak output power. After all, amplitude modulation and power control will cause the amplifier to operate at an average output power that can be substantially lower than the peak output power. Of course, battery lifetime is the key parameter to look at, and very often a somewhat lower efficiency at lower output power can be tolerated as long as the dc power consumption scales with the output power as in a class B PA. Several techniques exist to achieve a high efficiency over a wide power range, and they can be classified as efficiency enhancement and linearization. Efficiency enhancement strives to bend the η vs. Po curve (Fig. 13.7) upward, especially for the lower power levels. Two major techniques exist in the literature: Doherty [5,6] and envelope tracking [7]. Linearization is another approach to achieving a high average efficiency. It starts from a nonlinear amplifier with a high peak efficiency. A nonlinear amplifier can only transmit a single output power (class E) or has poor linearity (class C). To expand the linear range of such a nonlinear amplifier, the supply voltage can be modulated according to the amplitude signal [8]. Figure 13.8 shows the conceptual difference between the two approaches. It should be noted that efficiency enhancement still requires linear RF driver stages. This will require more dc current for the driver stages, which is obviously a drawback. Furthermore, efficiency enhancement tries to maintain a linear PA close to its compression point. Therefore, linearity is often degraded and the IM3 products

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Efficiency

Linearization ULTIMATE PA

Class E

Class C Efficiency Enhancement

Class B

Class A

Linearity

FIGURE 13.8

Difference between efficiency enhancement and linearization.

don’t follow their normal 1 : 3 slope at power back-off. These drawbacks have favored the development of linearization techniques over efficiency enhancement approaches. In what follows, we focus on polar modulation as a means to linearize a nonlinear switching RF CMOS power amplifier.

13.5

POLAR MODULATION

From a system-level point of view, polar modulation is a fairly simple mechanism. A switching amplifier such as a class E or D power amplifier can transmit only a specific output power. This power level is determined by the supply voltage and the impedance transformation network. As such, changing the supply voltage will change the output power. If the power supply voltage is changed according to the envelope of the RF signal, the amplitude information is then reconstructed at the antenna output. Another way to look at it is to think of the polar-modulated PA as a double-sideband mixer. The modulated RF signal can be written as   vRF (t) =  A(t)e jωc θ(t) = A(t) cos [ωc t + θ (t)]

(13.12) (13.13)

which clearly shows the multiplication between A(t) and cos[ωc t + θ (t)]. Figure 13.9 shows the conceptual diagram of a transmitter based on a polarmodulated power amplifier. At baseband, the Cartesian representation (I/Q) of the RF signal is converted into a polar representation, resulting in the envelope signal A(t) and the phase signal θ (t). For correct up-conversion, the phase signal itself is

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POLAR MODULATION

387

V

t

V I/Q to A/P conversion

baseband symbols

I(t)

Q(t)

A(t)

LF−PA t

θi (t)

θq (t)

cos

RF−PA

V

0

PLL

c13

90

sin

t

FIGURE 13.9 Transmit architecture based on a polar-modulated power amplifier.

represented by an in-phase and quadrature signal. After up-conversion, the signal at the input of the RF amplifier is a constant-envelope phase-modulated signal. The envelope signal A(t) is amplified by a baseband amplifier (LF-PA) and delivers the supply voltage to the RF amplifier. The switching RF power amplifier operates at a high efficiency, independent of the actual supply voltage. Thus, to achieve high efficiency of the entire transmitter, the LF-PA should also have high efficiency. One could argue that the efficiency–linearity conflict of the RF-PA is simply shifted to the LF-PA, and this is indeed somehow true. However, one should realize that this trade-off is easier to handle at lower frequencies. Furthermore, the entire RF chain after the up-conversion mixers can now be nonlinear and thus power efficient. In addition, the RF path itself can reuse much of the well-established constant-envelope transmiter architectures for GSM and Bluetooth. The topology of Fig. 13.9 is related to the Kahn transmitter [9] or EER architecture [10]. The major difference is that in this DSP-based solution the amplitude and phase signals are already separated, and there is thus no need for an analog envelope detector or RF limiter. As such, this topology is very well suited for CMOS integration, where digital computing power is virtually for free (i.e., at low power and low cost). 13.5.1

Implementation of the Envelope Modulator

The envelope modulator (i.e., the low-frequency power amplifier that delivers the power to the RF amplifier) needs to have a high efficiency. Unfortunately, the overall efficiency of the RF switching amplifier will decrease when the output power is

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reduced, even with an ideal 100% efficient amplitude modulator. This is due to the dc power consumption of the RF driver stages. Indeed, the total dc power consumption can be written as Pdc = Pdc,driver + Pdc,PA

(13.14)

= Pdc,driver +

Po ηE

(13.15)

= Pdc,driver +

α A(t)2 ηE

(13.16)

The supply voltage of the driver stages cannot be reduced since that would drastically increase the on-resistance of the switching power amplifier. This would in turn decrease the efficiency (since the load impedance remains the same) and will also be a source of nonlinearity. The core of the problem is that at lower output power, the switching amplifier and driver stages are overdimensioned. As such, the entire PA would need to reconfigured at lower output power. The fact that the efficiency decreases at lower output power due to the constant power dissipation of the driver stages relaxes the efficiency requirement of the amplitude modulator. Good efficiency can be achieved when a series regulator is used as an amplitude modulator, as shown in Fig. 13.10. Such a series regulator will result in a class B efficiency curve for the entire transmitter, and one could argue that after all this effort, the same efficiency as that of an class B RF PA is achieved. However, V DD,AM

A(t)

G(jw)

H(jw) Z out,AM C dec

Z dec

V DD,PA

RF−PA

RL

FIGURE 13.10

Transmiter architecture based on a polar-modulated power amplifier.

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389

two major differences exist with an RF class B power amplifier and the proposed solution. r Since the amplitude modulator is operating a baseband, its linearity will be superior to that of an RF class B. As such, the amplitude modulator can operate very close to its maximum output level. This would not be the case for an RF class B, where back-off needs to be applied to meet the linearity requirements. This back-off results in lower efficiency. r In an RF class B, the driver stages also need to have linearity and they will thus dissipate more power compared to this architecture. This will reduce the overall efficiency, and thus this solution has higher overall efficiency than that of an RF class B. The other solution is to use a switching regulator for the amplitude modulator. This is discussed next. 13.5.2

Switching Amplitude Modulator: Class S

A switching amplitude modulator can be made from a class D amplifier with a low-loss lowpass filter. Such an amplifier is denoted as class S and the basic circuit is depicted in Fig. 13.11. The envelope signal first passes through a pulse-width modulator, a delta-sigma modulator, or an asynchronous delta-sigma modulator [11]. The resulting pulses are efficiently amplified by the class D amplifier and the low-loss lowpass filter restores the envelope signal, which becomes then the supply voltage of the RF amplifier. At first sight, the class S amplifier is capable of achieving an efficiency of 100% since it is a switching amplifier. However, the power loss in the parasitic drain–source VDD

A(t)

PWM / SOPA / DS modulator

c13

low−pass filter

V DD,PA

RF−PA RL

FIGURE 13.11

Basic diagram of a class S amplifier as an amplitude modulator.

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capacitances of the output transistors will degrade the drain efficiency. Furthermore, the additional power loss of the drive circuitry, and especially the power loss in the lowpass filter, cannot be neglected. The class S amplifier is well suited for CMOS integration except for the lowpass filter. The relatively large inductor (typically, several hundred nanohenries) and capacitor (typically, several hundred picofarads) cannot be integrated because of their high values. Therefore, a fully integrated solution cannot be achieved with standard CMOS. Furthermore, the inductor of the lowpass filter should be of high quality and have a high self-resonance frequency and a high current capability. Combining these three requirements inevitably results in a high-cost component or might simply not be available. Another drawback is the bandwidth limitation of the class S amplifier. The corner frequency of the lowpass filter should be at least as high as the bandwidth of the envelope signal. The switching frequency of the class S amplifier must be at least one decade higher in order to have at least 40 dB suppression of the switching noise at the output, and most wireless systems require more than 60 dB of suppression. This easily pushes the switching frequency above 100 MHz. The higher the switching frequency, the higher the power loss in a class S amplifier, making the efficiency advantage of a switching topology less obvious. Furthermore, it is difficult to fabricate a high-quality inductor with a self-resonant frequency above 100 MHz and capable of conducting sufficient current. Therefore, most designs and publications use the class S approach not to linearize a nonlinear amplifier but to improve the efficiency of a linear amplifier [4,12,13]. In such a case, the bandwidth of the class S amplitude modulator can be reduced, as it is sufficient if the modulator can slowly follow the envelope signal, and the linearity demand of the amplitude modulator is less stringent. Altogether, the class S amplifier can be used as an efficient modulator if the bandwidth of the envelope signal is below a few megahertz and a fully integrated solution is not aimed for.

13.6

DISTORTION IN A POLAR-MODULATED POWER AMPLIFIER

The major benefit of the polar-modulated architecture is the shift of the linearity requirement from RF to baseband. At lower frequencies, well-known techniques such as feedback can easily be used to improve the linearity of the amplitude modulator. Therefore, the distortion of a polar-modulated power amplifier is dominated primarily by the nonlinearities of the class E amplifier. In the next sections we describe the main causes of the nonlinearity that occurs in polar-modulated amplifiers. 13.6.1

Feedforward

Figure 13.12 shows a typical example of an RF driver stage (DRV) driving the nMOST of a switching RF power amplifier. The feedforward current from the RF driver stage to the RF PA output stage, which is flowing through the gate–drain capacitance of the nMOS transistor of the switching amplifier, is the major cause of both AM-AM and AM-PM distortion [14]. Actually, the feedforward current itself

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391

VDD

Feedforward signal

Vd

DRV

RL

Vg

Vector diagram for high Vdd Feedforward signal

Vd

Vg Vdd

Vector diagram for low Vdd Vd

Feedforward signal Vg

Vdd

FIGURE 13.12 Simple model to demonstrate the AM-PM distortion of a switching amplifier.

is not causing AM-AM or AM-PM distortion. Rather, if the supply voltage of the switching amplifier is reduced, the feedforward current is more pronounced. The latter effect causes AM-AM and AM-PM distortion. If the supply voltage of the switching amplifier is made equal to zero, the feedforward current from the driver stage will result in an output voltage that is not equal to zero. On the other hand, if the supply voltage is high enough, the amplitude of the RF output voltage will be dominated by the switching amplifier itself and the feedforward current is then of less importance. This clearly causes AM-AM distortion. Feedforward current through the gate–drain capacitance will also cause a rotation of the output carrier. Again, the rotation itself is not a problem, but the rotation will change if the supply voltage of the switching amplifier is modulated. Therefore, a variation of the envelope signal will induce a time-varying rotation or phase modulation of the carrier, which is denoted as AM-PM. The easiest way to reduce the feedforward current is to reduce the supply voltage of the driver stage as well [15]. However, such an approach will also cause the linearity of the amplifier to deteriorate and will reduce the efficiency of the switching amplifier.

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To better understand the cause of AM-PM distortion in a polar-modulated amplifier, Fig. 13.12 depicts a simple model. Assume that there is no feedforward current at all. In that case, the signal at the drain of the nMOS transistor will be approximately 180◦ out of phase compared to the signal at the gate. A feedforward current through the gate–drain capacitance will lead the gate–drain voltage by 90◦ . This current will flow to the drain of the nMOS transistor and will be converted into a voltage. At the drain, the impedance at the switching frequency is almost resistive since it is a tuned amplifier. The drain voltage will thus rotate, and the amount of rotation will depend on the amount of feedforward current. If the supply voltage is reduced, the drain voltage will be also, and thus the rotation becomes more pronounced, as can be seen in Fig. 13.12. This intuitive model also predicts that the carrier would rotate 90◦ if the supply voltage is made equal to zero. 13.6.2

Differential Delay

In a polar-modulated power amplifier, the envelope and phase signals flow through different paths and recombine only in the last stage of the RF amplifier. Both signals may experience a different delay, and as such the envelope signal might be recombined with the wrong phase signal. The linearity degradation for a differential delay can be calculated for the case of a two-tone signal [16]. The derivation is not repeated here, but the approximated formula for the intermodulation is IMD = π (t BRF )2

(13.17)

with t the delay between amplitude and phase and BRF the bandwidth of the modulated RF signal. 13.6.3

Envelope Filtering

The bandwidths of the envelope and phase signals are considerably larger than the bandwidth of the modulated RF signal. The reason for this is the nonlinear relationship between these signals and the in-phase and quadrature signals x(t) and y(t) [17]: A(t) =



x(t)2 + y(t)2

P(t) = arctan

y(t) . x(t)

(13.18) (13.19)

Even when x(t) and y(t) have a finite bandwidth, A(t) and P(t) will have a much wider bandwidth, due to the nonlinear operations. A two-tone signal can be used to demonstrate this. Figure 13.13(a) and (b) show the time waveform and spectrum of a two-tone signal. The envelope signal A(t) and the corresponding spectrum of A(t) are shown in Fig. 13.13(c) and (d). The spectrum of the envelope signal is clearly much broader than that of the modulated RF signal. The same holds for the phase signal shown in Fig. 13.13(e) and (f). Clearly, the constant-envelope RF phase signal,

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modulated RF signal [dBV]

modulated RF signal [V]

393

0

1

0.5

0

−0.5

−1 0

0.5

1 time [us]

1.5

−10 −20 −30 −40 −50 −60 960

2

980

(a)

1000 1020 frequency [MHz]

1040

(b)

0

1 envelope signal [dBV]

envelope signal [V]

−10 0.5

0

−0.5

−20 −30 −40 −50

−1 0

0.5

1 time [us]

1.5

−60

2

0

10

(c)

20 30 frequency [MHz]

40

(d)

0

RF phase signal [dBV]

1 RF phase signal [V]

c13

0.5

0

−0.5

−10 −20 −30 −40 −50

−1 0

0.5

1 time [us]

(e)

FIGURE 13.13

1.5

2

−60 960

980

1000 1020 frequency [MHz]

1040

(f)

Time waveforms and spectra of a two-tone signal.

applied at the gate of the class E amplifier, has a wider spectrum than that of the modulated RF signal. On the other hand, the amplitude modulator will limit the bandwidth of the envelope signal, and this will cause distortion. A question now arises: How large must the bandwidth of the envelope signal be to avoid excessive linearity degradation? Similar

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to the differential delay distortion, the intermodulation distortion can be calculated for a simple case only, such as a two-tone signal [16]. From that analysis it was shown that to have better than −50 dBc of intermodulation distortion, the bandwidth of the envelope path should be more than six times the bandwidth of the modulated RF signal, at least for a two-tone signal. The derivation in [16] assumes an ideal brick-wall filter. Such a filter has a zero phase response and removes all harmonics above the cutoff frequency. However, the phase response of the envelope filter will have a large impact on the distortion. After all, the phase response of the envelope filter causes an equivalent delay of the envelope signal, and this was not taken into account in [16]. In order to have a distortionless transmission of the baseband amplitude signal, the amplitude response of the amplitude modulator should be flat and the phase response should be a linear function of the frequency [18]. In a first-order lowpass filter, both requirements are clearly not met. For a first-order lowpass filter with a transfer function H ( jω) =

1 1 + jω/ω3dB

(13.20)

the phase response is θ (ω) = tan

−1



−ω ω3dB

 (13.21)

and from this, the time delay of the filter can be obtained: 1 θ (ω) = tan−1 Td = − ω ω



ω ω3dB

 (13.22)

For low frequencies, well below the corner frequency of the filter, the time delay is constant and equal to Td =

1 ω3dB

(13.23)

and for higher frequencies, the delay goes to zero. In reality, the envelope signal consists of many frequency components, and the delay of the high-frequency components will be less than the delay of the lowfrequency content of the envelope signal. If the corner frequency of the envelope filter is high enough to ensure that most of the envelope spectrum falls within the passband of the low-pass filter, the envelope signal is delayed by the low-frequency time delay of the filter, which is equal to 1/ω3dB . As said before, this delay has to be added in the phase path to realign the two signals and to ensure that the recombination in the power amplifier is correct.

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395

1

envelope signal [V]

envelope signal [dBV]

−10 −20 −30 −40

0.5

0

−0.5

−50 −60

−1 0

10

20 30 frequency [MHz]

40

0

0.5

(a)

0

0

−10

−10

−20 −30 −40 −50 −60 960

1 time [us]

1.5

2

(b)

complex signal [dBV]

complex signal [dBV]

c13

−20 −30 −40 −50

980

1000 1020 frequency [MHz]

(c)

1040

−60 960

980

1000 1020 frequency [MHz]

1040

(d)

FIGURE 13.14 Time waveforms and spectra of a two-tone signal with a lowpass envelope filter. The crosses in part (a) represent the spectrum of the unfiltered envelope signal. In part (d), the phase signal is delayed by the low-frequency time delay of the envelope filter.

To demonstrate this, the two-tone example of Fig. 13.13 can be used again. Figure 13.14 demonstrates the effect when the envelope signal is filtered by a first-order lowpass filter with a corner frequency fourfold that of the bandwidth of the modulated RF signal. The spectra of the original envelope signal and the filtered version are shown in Fig. 13.14(a). Figure 13.14(b) shows the time waveform of the filtered envelope signal. In the latter, the sharp peaks of the envelope signal that go to zero are gone. Also, the envelope signal is a little delayed by the phase response of the envelope filter. In Fig. 13.14(c), the spectrum of the modulated RF signal at the output is depicted, and intermodulation products due to the envelope filtering are clearly visible. The delay of the envelope filter can be compensated for by inserting the appropriate delay in the phase path as shown in Fig. 13.14(d). It can be concluded that the bandwidth of the envelope path, and thus also the bandwidth of the amplitude modulator, has to be considerably larger than the bandwidth of the modulated RF signal at the output. However, it is possible to reduce the

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bandwidth of the envelope signal. The distortion generated can be partially overcome by inserting a delay in the phase path. This delay is related to, but smaller than, the LF time delay of the envelope filter. 13.6.4

Injection of the Phase Signal

The large gate–drain capacitance of the nMOS switch in the class E amplifier will feedforward the signal from the driver stage to the output. This feedforward will cause both AM-AM and AM-PM distortion, as already discussed. However, the feedforward signal is only phase modulated and has a wider bandwidth than that of the RF signal, as demonstrated by the two-tone signal example in Fig. 13.13. The feedforward will thus not only cause AM-AM and AM-PM distortion but will also inject a wideband signal at the output, which might cause a violation of the spectral mask. If the envelope signal A(t) has a dc offset, the phase signal also gets injected toward the output. Such an offset may occur in the digital-to-analog converter after the DSP as well as in the analog circuitry of the amplitude modulator. The injection due to the offset can easily be seen by the equation v(t) = (A(t) + Voffset ) cos[ωc t + P(t)] = A(t) cos[ωc t + P(t)] + Voffset cos[ωc t + P(t)]

(13.24) (13.25)

The second term, Voffset · cos[ωt + P(t)], suggests that the RF phase signal is added to the output. Remember from Fig. 13.14(d) that this signal has a wide bandwidth. The injection of this signal at the output will thus give rise to a large number of spectral components, although these are not caused by a nonlinearity. 13.6.5 Linearity Improvement Techniques for Polar-Modulated Power Amplifiers The distortion mechanisms that were discussed in previous sections will cause the linearity of the polar modulation technique to deteriorate. This can be solved by using a linearity improvement technique. The two important ones are discussed briefly in this section. 13.6.5.1 Predistortion Predistortion first measures the nonidealities of the RF amplifier and applies the inverse curve to obtain more linear behavior. In a polarmodulated power amplifier, the correction can be applied on both the amplitude and phase path. Hence, predistortion can alleviate both AM-AM and AM-PM distortion. Delay compensation can also be accounted for and can also be regarded as predistortion. Predistortion cannot solve the dynamic-related distortion of the amplifier, such as filtering of the envelope signal or memory effects [19–22]. Recent results show that thermal memory effects that have a slow enough time behavior can be compensated for [23].

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397

For predistortion to be effective, the AM-AM and AM-PM distortion should first be measured, stored in a look-up table, and applied on the actual data transmitted. A drawback of predistortion is the inability of the system to anticipate any changes in system behavior. Of course, the distortion curve could be updated frequently to accommodate for this problem, but still, short-term memory effects and envelope filtering cannot be overcome with predistortion [20]. The advantage of predistortion is that instability can never occur, and it is relatively easy to implement at low cost. As such, predistortion is frequently applied, not only in research, but also in commercially available products [15]. 13.6.5.2 Polar Feedback Feedback is a well-known technique in electronics and has been applied in conjunction with polar modulation as well. Either the amplitude signal, the phase signal, or both signals could be fed back and compared with the input signal. In contrast to predistortion, feedback has the advantage of operating in real time, and as such, it can overcome distortion mechanisms that are related to the dynamic behavior of the RF amplifier, such as memory effects, envelope filtering, and temperature or other environmental variations. Of course, a feedback loop might become unstable and the analog blocks that are placed in the feedback path should have little delay and low distortion. Polar feedback consists of two loops: a phase feedback loop and an amplitude feedback loop [24]. The two feedback loops should be matched to each other accurately, and stability needs to be carefully maintained over the large dynamic range of modern communication systems. Phase feedback seems relatively easy since the feedback path does not need amplitude linearity. As such, a simple limiter can be used to extract the phase signal from the RF output signal. However, the limiter may have a substantial amount of AM-PM distortion, especially if one takes into account that the RF signal at the input can have large envelope variations [25]. Also, for modulation schemes that pass through the origin of the complex plane, the RF output voltage may become equal to zero, meaning that there is no voltage to be fed back in the phase path. The same holds for amplitude feedback. An envelope detector is required that can operate over the entire dynamic range of the system and has a low AM-PM distortion [10].

13.7 DESIGN AND IMPLEMENTATION OF A POLAR-MODULATED POWER AMPLIFIER FOR GSM-EDGE 13.7.1

Introduction

A polar-modulated switching RF power amplifier is a perfect candidate for a fully integrated CMOS solution. Such a solution combines the excellent switching behavior of CMOS for RF power amplifiers, with the digital signal processing capabilities needed for polar-modulated architectures. In this section, the design and implementation of a polar-modulated PA for GSM-EDGE is described. The polar-modulated power amplifier is designed in a 0.18-µm CMOS technology.

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Design and Implementation of the RF Amplifier

Let us first focus on the design of the 1.8-GHz PA. The GSM-EDGE class E3 specifications require a maximum modulated output power of 22 dBm. Since the peak-to-average power ratio for EDGE is 3.4 dB, the RF amplifier must thus be able to transmit a peak power of at least 25.4 dBm. To increase both the reliability and the output power, a thick gate-oxide transistor with an oxide thickness of 6.5 nm and a zero current drain–bulk breakdown voltage of 9 V was selected for the nMOS switch in the class E output stage. This transistor is actually a 0.35-µm transistor. The L-match impedance transformation network at the output is designed to transform the 50-
antenna impedance to Rm = 12
. Together with the thick gate– oxide transistor, this will meet the output power requirement. Two driver stages are added to achieve sufficient gain and to lower the input capacitance seen by the upconverter. Since the main task of the driver stages is to deliver gain, the corresponding transistors are minimum-gate-length 0.18-µm transistors that benefit from the higher f T . The amplifier is made fully differential to increase the output power, to reduce the required on-chip decoupling capacitance, and to reduce the influence of the parasitic ground inductance. A dedicated ground is provided for the differential RF output to control the inductance of the RF signal path. A single-ended version of the complete RF amplifier circuit is shown in Fig. 13.15. The actual RF amplifier is fully differential. The dc-feed inductors of the class E stage and the driver stages are merged together, to form differential inductors with a center tap. The differential inductors are modeled and simulated as full four-port networks, since the currents in the inductor are not fully differential, due to the switching nature of the class E amplifier. All the inductors of the RF amplifier are integrated on-chip. The differential topology and the integrated impedance transformation network will result in a solution

V DD,DRV,2

V b,2

L D,2

V DD,DRV,1

V b,1

L D,1

V DD,PA

L1 Rm

Lm

CBL

RL M D,2

FIGURE 13.15

M D,1

M PA

C1

Cm

Single-ended version of the RF class BE amplifier.

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TABLE 13.1

399

Component Values of the RF Power Amplifier

Parameter Gate width of MPA Gate length of MPA C1 L 1,a + L 1,b Lm Cm Gate width of M D,1 Gate length of M D,1 L D,1a + L D,1b Gate width of M D,2 Gate length of M D,2 L D,2a + L D,2b

Value 3000 µm 0.34 µm 6 pF Differential coil of 1 nH 1.7 nH 3.2 pF 800 µm 0.18 µm Differential coil of 1 nH 100 µm 0.18 µm Differential coil of 5.8 nH

that is less sensitive to the used package. Furthermore, since no off-chip striplines or inductors are required, the total board area is reduced. Inductors L 1 and L m have a quality factor Q L of about 11. To conclude, Table 13.1 summarizes the component values of the RF power amplifier.

13.7.3

Design and Implementation of the Linear Amplitude Modulator

Figure 13.16 is a simplified circuit of the amplitude modulator. For the design of this block, the RF power amplifier is first simulated for different values of VDD,PA , the supply voltage of the class E amplifier (see Fig. 13.15). From these transient RF simulations, it was found that the equivalent dc load resistance of the RF amplifier is 9
. RPA is related to the efficiency of the switching amplifier. In an ideal case, the efficiency of the RF PA is independent of the supply voltage VD D,PA and therefore RPA should remain constant. In a real implementation, however, the equivalent dc load resistance is not constant, and this variation will cause AM-AM distortion of the RF output signal. To reduce this distortion, the amplitude modulator is designed to have a very low output resistance. The output voltage of the amplitude modulator almost goes rail to rail (i.e., from zero to VD D,AM . Therefore, the feedback block H ( jω) should act as an attenuator to limit the dynamic range of the feedback voltage, and a dc shift is necessary to bring the feedback voltage within the voltage range of the input differential pair. The output of the op-amp, and thus the voltage at the gate of the pMOS transistor MAM , must also have a large dynamic range. To shut down the power amplifier, the op-amp output must be set equal to VD D,AM . At full output power, the output of the op-amp must go as low as possible to reduce the on-resistance of MAM , and thus to reduce the drain–source voltage drop of MAM .

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CMOS RF POWER AMPLIFIERS FOR MOBILE COMMUNICATIONS V DD,AM

Cdec,1

A(t)

M AM V DD,AM

Cdec,2 RPA

amplitude modulator

V DD,PA

L1 V DD,DRV,2

V DD,DRV,1

DRV−2

DRV−1

Rm

Lm

CBL

RL M PA

C1

Cm

actual RF amplifier is fully differential

RF amplifier

FIGURE 13.16

Circuit implementation of the fully integrated linear amplitude modulator.

To avoid distortion due to envelope filtering, the op-amp is designed to have a large bandwidth rather than a large gain. Therefore, to have a low output impedance, the pMOS transistor MPA should have a large gm , which reflects itself in the large gate width of 8000 µm. The gate length is 0.34 µm and the gate capacitance of that transistor is 15 pF. Together with the output impedance of the OTA, this creates a dominant pole at 8.8 MHz, which is high enough for the envelope signal. The nondominant pole at the output node is created by RPA = 9
and Cdec,2 = 80 pF, resulting in 222 MHz. The OTA has a voltage gain of 28 dB and a GBW of 260 MHz. The pMOS transistor has a transconductance gm of 440 ms, and together with RPA = 9
, this creates a gain of 4 or 12 dB. A resistive feedback with an attenuation of −18 dB is chosen to have a closed- loop transfer function with a flat phase response. All this results in a loop gain of 22 dB and a phase margin of 78◦ , which is sufficient to close the loop safely. From the numbers above, the closed- loop

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DESIGN AND IMPLEMENTATION OF A POLAR-MODULATED POWER AMPLIFIER

GND

out+

GND

amplitude modulator

RF PA

GND

FIGURE 13.17

401

out−

GND

Photograph of a linearized EDGE PA in 0.18-µm CMOS.

output impedance of the amplitude modulator can easily be calculated, and equals 0.72
. The supply voltage of the amplitude modulator is 3.3 V and has a decoupling capacitance of Cdec,1 = 110 pF. When EDGE signals are transmitted at maximum output power, the actual supply voltage of the RF PA, VD D,PA in Fig. 13.16, has a peak value of 2.9 V, an average value of 1.9 V, and a minimal value of 0.4 V. Figure 13.17 shows a photograph of the fully integrated linearized amplifier. The total chip area, including the bonding pads, is 1.8 mm × 3.6 mm (see Table 13.2). Wide bonding strips are used for the ground and supply connections. Sufficient decoupling is integrated on-chip to ensure stability and to provide a low impedance to the ac supply currents of the RF power amplifier. TABLE 13.2 Measured Performance and Process Specifications of the PA in Fig. 13.17 Parameter Technology Supply voltage Area Frequency Parameter

Specification 0.18 µm CMOS 1.8 V and 3.3 V 1.8 × 3.6 mm2 1.75 GHz Measured

Peak envelope output power Input power Overall efficiency

27 dBm −3 dBm 34%

Dc power consumption at peak envelope output power RF PA RF driver Amplitude modulator

1250 mW @ 3.3 V 186 mW @ 1.8 V 33 mW @ 3.3 V

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50

50 Class E + AM−MOD Class A

40 efficiency [%]

40 efficiency [%]

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30 20 10 0 0

Class E Class E + DRV Class E + DRV + AM−MOD

0.1

0.2 0.3 output power [W]

(a)

0.4

0.5

30 20 10 0 0

0.1

0.2 0.3 output power [W]

0.4

0.5

(b)

FIGURE 13.18 Measured efficiency vs. output power for constant-envelope signals. In (b), this efficiency is compared to a class A amplifier that would achieve the same peak envelope output power and efficiency.

13.7.4

Measurements

13.7.4.1 Constant-Envelope Measurements To measure the constant-envelope performance, a dc voltage is used for the envelope signal A(t). The measured constantenvelope maximum RF output power is 27 dBm. For DCS-1800 class 2, the required constant-envelope output power for GMSK modulation is 24 dBm. Therefore, the solution presented can also be used as a class 2 GSM power amplifier. The input power is −3 dBm, resulting in a power gain of 30 dB, and it enables a direct connection of the up-converter to the linearized amplifier. Figure 13.18 shows the measured efficiency of the amplifier for various levels of POUT . This graph is obtained by applying several dc voltages at the input of the amplitude modulator. The class E amplifier itself (ηd,E ) maintains its high drain efficiency of 40% over the entire power range. When the power consumption of the RF driver stages is taken into account (ηoa,E ), the efficiency drops to 34%. Due to the voltage drop across the amplitude modulator (ηoa,PMA ), the overall system efficiency becomes 30%. In Fig. 13.18(b), the efficiency of the class E and linear amplitude modulator is compared to the efficiency of a class A amplifier that would achieve the same output power and efficiency. Note, however, that it would not be possible to use that class A amplifier at maximum output power and efficiency due to the compression of the class A at the peak efficiency. The polar-modulated class E solution, on the other hand, is able to transmit linearly, all the way up to the peak envelope output power of the RF amplifier since the linearity requirement is shifted to the amplitude modulator. 13.7.4.2 AM-AM and AM-PM Distortion Measurement To measure the AMAM and AM-PM distortion, a slowly decreasing voltage is used for the envelope signal. Once the voltage starts to decrease, a trigger pulse is send to the spectrum analyzer. The latter uses this trigger pulse to store the down-converted data in an

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(a)

FIGURE 13.19

403

(b)

Measured AM-AM and AM-PM distortion.

internal memory, which can be accessed through the LAN bus. From this downconverted data, the amplitude and phase distortion can be obtained. Figure 13.19 shows the measured AM-AM and AM-PM distortion of the amplifier. As expected, the distortion becomes severe when the supply voltage goes to zero. The dynamic range of the EDGE signal is indicated as well. However, one should realize that this dynamic range occurs at full output power. In other words, when power control is applied, the average output power is reduced and the dynamic range moves to the left, introducing more AM-AM and AM-PM. Also note that the AMAM shows some compression for a high envelope value. This is due to the saturation or compression in the op-amp. The AM-PM distortion has been measured for different samples and temperatures, ranging from 20 to 70◦ C. All these data are plotted in Fig. 13.19(a), but little variation can be noticed. Therefore, it is justified to apply these data for predistortion. The influence of the AM-AM distortion is less severe compared to the AM-PM, and therefore only AM-PM predistortion is applied. To make a digital predistortion feasible, the measured AM-PM distortion has been averaged and is modeled by a piecewise linear approximation which is also indicated in Fig. 13.19(b) by the solid line. This predistortion will be used in the EDGE measurements, discussed next. 13.7.4.3 EDGE Measurements In EDGE, the peak-to-average power ratio is 3.4 dB. Since the RF amplifier has a peak envelope output power of 27 dBm, the maximum average output power, at least in theory, is about 23.6 dBm or 230 mW. However, some clipping can be tolerated, and the maximum average output power can therefore be higher than this number. Figure 13.20 shows several EDGE output spectra at 214 mW or 23.3 dBm average output power. It is interesting to note how AM-PM distortion, together with a delay between the amplitude path and the phase path, can generate an asymmetric output spectrum. In Fig. 13.20(a), no predistortion or delay compensation is applied. It can be seen that the spectral mask margin is very small at 400 kHz offset. Furthermore,

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CMOS RF POWER AMPLIFIERS FOR MOBILE COMMUNICATIONS 20

20 EVMRMS = 1.1%

relative output power [dB]

relative output power [dB]

EVMRMS = 1.2%

0 −20 −40 −60 −80 −800 −600 −400 −200 0 200 400 600 800 frequency [kHz]

0 −20 −40 −60 −80 −800 −600 −400 −200 0 200 400 600 800 frequency [kHz]

(a) no predistortion, no delay compensation

(b) AM-PM predistortion, no delay compensation

20

20

0 −20 −40 −60 −80 −800 −600 −400 −200 0 200 400 600 800 frequency [kHz]

(c) delay compensation, no predistortion

FIGURE 13.20

EVMRMS = 1.1%

relative output power [dB]

EVMRMS = 1.0%

relative output power [dB]

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0 −20 −40 −60 −80 −800 −600 −400 −200 0 200 400 600 800 frequency [kHz]

(d) AM-PM predistortion and delay compensation

Measured EDGE output spectra at 214 mW or 23.3 dBm.

the output spectrum exhibits a large amount of asymmetry. When piecewise linear predistortion is applied [Fig. 13.20(b)], the mask is easily met and the asymmetry has almost disappeared. However, the predistortion has little influence on the EVM. If the delay between amplitude and phase is compensated completely by a delay of 52 ns, the spectrum is again symmetrical. Applying both AM-PM predistortion and delay compensation [Fig. 13.20(d)] results in a large margin at both 400 kHz and 600 kHz offset. Figure 13.21 shows a wideband measurement of the modulated output spectrum at maximum output power, up to 6 GHz and measured with a 100-kHz resolution bandwidth. The amplifier noise inside the DCS-1800 frequency band is low enough, and the second and third harmonics of the RF carrier are visible at 3.6 and 5.25 GHz, although their power level is already low. Figure 13.22(a) and (b) show the value of the output spectrum at 400 and 600 kHz offset vs. average output power. Both the upper and lower spectral values are given to indicate the presence of an asymmetry of the output spectrum. In Fig. 13.22(a), the spectral mask at +400 kHz offset is not met if no predistortion or delay compensation is applied. The spectral mask at −400 kHz offset is much lower, which corresponds to a large asymmetry of the output spectrum. When the delay compensation of 52 ns

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DESIGN AND IMPLEMENTATION OF A POLAR-MODULATED POWER AMPLIFIER

405

0 RBW=100kHz −10 relative output power [dB]

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−20 −30 −40 −50

2nd harmonic

3rd harmonic

−60 −70 −80 −90 2

FIGURE 13.21

3

4 frequency [GHz]

5

6

Wideband measurement of the output spectrum at maximum output power.

is applied, both curves fall together, indicating a symmetrical output spectrum. With the predistortion, the spectral mask margin can be increased further, as well as the power range over which the mask is met. The spectral mask margin is high enough to allow some degradation in the up-converter. For a low average output power, the spectral mask margin is smaller due to the increased AM-AM and AM-PM distortion. At maximum output power, the spectral mask margin is reduced because of additional AM-AM distortion in the amplitude modulator, as shown in Fig. 13.22. Note that the maximum output power is 240 mW or 23.8 dBm, which is slightly higher than the theoretical value of 230 mW or 23.6 dBm. To achieve the spectral mask specifications over a wider power range, a more aggressive AM-AM and AM-PM predistortion should be applied, based on a look-up table that can be updated periodically. Figure 13.22(c) shows the measured EVMrms vs. average output power (and see Table 13.3). The EVMrms is well below the required 9% specification and is reduced primarily by the delay compensation. Figure 13.23 shows the performance of the linearized amplifier vs. frequency. The output power and spectral mask specifications are met for both the DCS-1800 band ranging from 1.71 to 1.785 GHz and the PCS-1900 band ranging from 1.85 to 1.91 GHz. To demonstrate how delay compensation can reduce the envelope bandwidth required , Fig. 13.24 shows the output spectrum measured at ± 400 and ± 600 kHz offset for different values of the envelope bandwidth. From system-level simulations, it was found that the bandwidth should be at least 1.5 MHz to meet the spectral mask requirements. This is in relatively good agreement with the measurement of Fig. 13.24. If delay compensation is applied, the envelope bandwidth can be reduced

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−40

−50 no compensation delay compensation AM−PM pred. & delay comp.

−45

relative power at 600kHz [dB]

relative power at 400kHz [dB]

−50 −55 −60 −65 0

50 100 150 200 average output power [mW]

−60 −65 −70 −75 0

250

no compensation delay compensation AM−PM pred. & delay comp.

−55

50 100 150 200 average output power [mW]

(a)

250

(b)

Error Vector Magnitude (RMS) [%]

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12 10

no compensation AM−PM pred. & delay comp.

8 6 4 2 0 0

50 100 150 200 average output power [mW]

250

(c)

FIGURE 13.22 Measurement of the relative output power at 400 and 600 kHz frequency offset and error vector magnitude (rms) vs. average output power. In parts (a) and (b), the solid line indicates the measurement at a positive frequency offset and the dashed line is the measurement at the negative frequency offset.

TABLE 13.3

Measured Performance and ETSI Specifications

Parameter

Measured

EDGE E3 Specs.

Average output power Overall efficiency Modulation spectrum 400 kHz offset, 30 kHz RBW 600 kHz offset, 30 kHz RBW Error vector magnitude Rms EVM Peak EVM

23.8 dBm 22%

22 dBm

−59 dB −70 dB

−54 dB −60 dB

1.69% 5.87%

9% 30%

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DESIGN AND IMPLEMENTATION OF A POLAR-MODULATED POWER AMPLIFIER −50

24

23 PCS1900

DCS1800

22 EDGE Class E3 power spec.

relative output power [dB]

average output power [dBm]

25

400kHz spec.

−55

400kHz 600kHz spec.

−60 DCS1800

−65

PCS1900

−70 600kHz

21

1.7

1.75

1.8 1.85 frequency [GHz]

1.9

−75

1.7

1.75

(a)

FIGURE 13.23 frequency.

1.9

Output and relative power at 400 and 600 kHz frequency offset vs. carrier

−45 −50 −55 −60

500

1000 1500 2000 2500 3000 Envelope bandwidth [kHz]

(a)

Relative power at 600kHz [dB]

−45 with delay compensation no delay compensation

−65 0

1.8 1.85 frequency [GHz]

(b)

−40 Relative power at 400kHz [dB]

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with delay compensation no delay compensation

−50 −55 −60 −65 −70 −75 0

500

1000 1500 2000 2500 3000 Envelope bandwidth [kHz]

(b)

FIGURE 13.24 Measured relative power at 400 and 600 kHz frequency offset versus envelope bandwidth, with and without delay compensation.

below 1 MHz. Altogether, the measurement of Fig. 13.24 clearly demonstrates how delay compensation can reduce the bandwidth of the amplitude modulator.

13.7.5

Architectural Improvements

The GSM-EDGE standard [26] requires that the average modulated output power can be regulated down to 0 dBm in 2-dB steps. Due to the feedforward current from the driver stages, the minimal output power of this solution, while still meeting the spectral mask requirements, is 40 mW or 16 dBm. To reduce this number, the supply voltage of the driver stages has to be reduced or modulated as well. In fact, one might as well turn off the supply of the class E amplifier, apply the polar modulation on the driver stage, and rely entirely on the feedforward current of the class E stage.

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CMOS RF POWER AMPLIFIERS FOR MOBILE COMMUNICATIONS

If the supply voltage of both the class E and driver stages is modulated, the linearity deteriorates. An example of such a system is given in [15]. The architecture uses both AM-AM and AM-PM predistortion to achieve the required linearity over the entire output power range. Another solution is to use a low-power class AB amplifier, in parallel with the class E amplifier, which takes over at low output power levels. The class AB can be placed in parallel [27] or a power-combining architecture can be used to combine the two amplifiers. Finally, a cascode solution [1,28] will have a less linear on-resistance, but the feedforward current and hence the AM-PM distortion can be reduced considerably. This would also enable a wider power range.

13.8

CONCLUSIONS

This chapter has focused on the design and implementation of CMOS RF PA for wireless communication. The low supply voltage of CMOS forms a direct conflict with output power requirements. Furthermore, the high dynamic range and linearity requirements pose a challenge to achieve high efficiency. Although the supply voltage of CMOS will probably not be reduce much below 1 V, even achieving watt-level output power is not a trivial task. Power-combining techniques have been proposed as a means to circumvent the drawbacks of the common-impedance transformation networks. But achieving high output power is not sufficient. Indeed, the efficiency needs to be high over a wide power range. This requires some form of reconfigurability in the PA. Furthermore, the fast, and thus wideband amplitude modulation that is present in most of today’s modulation schemes requires either a linearization scheme or an efficiency enhancement approach. Here, CMOS is at its best, and techniques such as digital predistortion and waveform pre-emphasis are readily available in digital CMOS. Combining all the above in a single chip, together with the requirements from industry such as reliability and maintaining the performance for VSWR mismatch at the antenna connection, is not a trivial job and requires good knowledge and overview of the different trade-offs. Hopefully, this chapter has served well in providing such an overview in this complex matter of CMOS radio-frequency power amplifiers.

REFERENCES 1. T. Sowlati and D. Leenaerts, “A 2.4GHz 0.18µm CMOS self-biased cascode power amplifier with 23dBm output power,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, pp. 294–295, Feb. 2002. 2. I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, “Fully integrated CMOS power amplifier design using the distributed active transformer architecture,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 371–383, Mar. 2002.

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3. P. Haldi, D. Chowdhury, G. Liu, and A. M. Niknejad, “A 5.8 GHz linear power amplifier in a standard 90nm CMOS process using a 1V power supply,” in RFIC Digest of Papers, pp. 431–434, 2007. 4. B. Sahu and G. A. Rinc´on-Mora, “A high-efficiency linear RF power amplifier with a power-tracking dynamically adaptive buck-boost supply,” IEEE Trans. Microwave Theory Tech., vol. 52, no. 1, pp. 112–120, Jan. 2004. 5. W. H. Doherty, “A new high efficiency power amplifier for modulated waves,” Proc. IRE, vol. 24, no. 9, pp. 1163–1182, Sept. 1936. 6. N. Wongkomet, L. Tee, and P. R. Gray, “A 1.7GHz 1.5W CMOS RF doherty power amplifier for wireless communication,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 486–487, Feb. 2006. 7. J. T. Stauth and S. R. Sanders, “Optimum biasing for parallel hybrid switchinglinear regulators,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1978–1985, Sept. 2007. 8. P. Reynaert and M. Steyaert, “A 1.75 GHz polar modulated CMOS RF power amplifier for GSM-EDGE,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2598–2608, Dec. 2005. 9. L. R. Kahn, “Single sideband transmission by envelope elimination and restoration,” Proc. IRE, vol. 40, no. 7, pp. 803–806, July 1952. 10. D. K. Su and W. J. McFarland, “An IC for linearizing RF power amplifiers using envelope elimination and restoration,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2252–2258, Dec. 1998. 11. T. Piessens and M. Steyaert, “SOPA: A high-efficiency line driver in 0.35 µm CMOS using a self-oscillating power amplifier,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 306–307, Feb. 2001. 12. K. Yang, G. I. Haddad, and J. R. East, “High-efficiency class-a power amplifiers with a dual-bias-control scheme,” IEEE Trans. Microwave Theory Tech., vol. 47, no. 8, pp. 1426–1432, Aug. 1999. 13. G. Hanington, P. Chen, P. M. Asbeck, and L. E. Larson, “High-efficiency power amplifier using dynamic power-supply voltage for CDMA applications,” IEEE Trans. Microwave Theory Tech., vol. 47, no. 8, pp. 1471–1476, Aug. 1999. 14. M. K. Kazimierczuk, “Collector amplitude modulation of the class E tuned power amplifier,” IEEE Trans. Circuits Syst., vol. 31, no. 6, pp. 543–549, June 1984. 15. W. B. Sander, S. V. Schell, and B. L. Sander, “Polar modulator for multi-mode cell phones,” in Proc. Custom Integrated Circuits Conference, pp. 439–445, Sept. 2003. 16. F. H. Raab, “Intermodulation distortion in kahn-technique transmitters,” IEEE Trans. Microwave Theory Tech., vol. 44, no. 12, pp. 2273–2278, Dec. 1996. 17. E. McCune and W. Sander, “EDGE transmitter alternative using nonlinear polar modulation,” in Proc. International Symposium on Circuits and Systems, pp. III-594 to III-597, May 2003. 18. L. W. Couch II, Digital and Analog Communication Systems. Upper Saddle River, NJ: Prentice Hall, 1997. 19. S. Kusunoki, K. Yamamoto, T. Hatsugai, H. Nagaoka, K. Tagami, N. Tominaga, K. Osawa, K. Tanabe, S. Sakurai, and T. Iida, “Power-amplifier module with digital adaptive predistortion for cellular phones,” IEEE Trans. Microwave Theory Tech., vol. 50, no. 12, pp. 2979–2986, Dec. 2002.

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20. I. Teikari, J. Vankka, and K. Halonen, “Digitally controlled RF predistortion based on vector modulator,” in Proc. International Symposium on Systems, Signals and Electronics, Aug. 2004. 21. N. Ceylan, J. E. Mueller, and R. Weigel, “A new addressing method for look-up table based digital predistortion linearizers,” in Proc. International Symposium on Systems, Signals and Electronics, Aug. 2004. 22. P. Andreani, L. Sundstrom, N. Karlsson, and M. Svensson, “A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier,” J. Analog Integrated Circuits Signal Process., vol. 22, no. 1, pp. 25–30, Jan. 2000. 23. S. Boumaiza and F. M. Ghanouchi, “Thermal memory effects modeling and compensation in RF power amplifiers and predistortion linearizers,” IEEE Trans. Microwave Theory Tech., vol. 51, no. 12, pp. 2427–2433, Dec. 2003. 24. T. Sowlati, D. Rozenblit, R. Pullela, M. Damgaard, E. McCarthy, D. Koh, D. Ripley, F. Balteanu, and I. Gheorghe, “Quad-band GSM/GPRS/EDGE polar loop transmitter,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2179–2189, Dec. 2004. 25. T. Sowlati, Y. M. Greshishchev, and C. A. T. Salama, “Phase-correcting feedback system for class E power amplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 4, pp. 544–550, Apr. 1997. 26. ETSI, Radio Transmission and Reception. ETSI TS 145 005 v4.6.0. Nov. 2001. 27. Y. Ding and R. Harjani, “A high-efficiency CMOS +22-dBm linear power amplifier,” IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1895–1900, Sept. 2005. 28. C. Yoo and Q. Huang, “A common-gate switched, 0.9W class-E power amplifier with 41% PAE in 0.25 µm CMOS,” in Symposium on VLSI Circuits Digest of Technical Papers, pp. 56–57, June 2000.

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Digitally Assisted RF Architectures: Two Illustrative Designs JOEL L. DAWSON Massachusetts Institute of Technology, Cambridge, Massachusetts

14.1

INTRODUCTION

What exactly is “digitally assisted radio frequency (RF)”? The descriptor “digitally assisted” is the leading candidate in the race to capture, in a single word or phrase, the latest trend in RF, analog, and mixed-signal circuit design. Other candidates include “mostly digital,” “all-digital,” and most awkwardly, “analog/digital hybrid”. Boiled down to its essence, the trend is that the optimal partioning of functionality between the analog and digital domains in RF circuits is changing. It is changing because digital circuits in CMOS have become blindingly fast, vanishingly small, and laughably cheap. The amount of digital signal processing power now available in a square millimeter of silicon is nothing short of astounding. At the same time, modern MOSFETs as analog-processing elements have become more difficult to work with. They have low output resistance, tolerate only low supply voltages, and have lots of gate leakage. And then there’s the big one: They are so difficult to model, and are prone to so much variation, that even digital designers are complaining. The good news is that in RF transceivers, this state of affairs has created a tremendous opportunity for designers. For the first time in decades, RF and mixed-signal designers have both the need to be creative at the architectural level and the means whereby to be creative. The need exists because our analog tricks are becoming more difficult to implement. The means exists because we have one thing that Edwin Armstrong never had: millions, even billions, of transistors all on a single die, each one essentially for free, and all of them guaranteed to work. As digital signal processing chips became ever faster, cheaper, and more impressive, it was natural to look ahead to the logical extreme: a receiver consisting only of an antenna, an analog-to-digital converter (ADC), and a microprocessor, which is the ultimate software-defined radio (SDR). The ADC has since proven to be the Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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DIGITALLY ASSISTED RF ARCHITECTURES: TWO ILLUSTRATIVE DESIGNS

bottleneck here, with the demands for sampling rate, resolution, and power consumption completely overwhelming current design techniques. Failing the achievement of this ultimate goal, what do we do in the meantime? With digital circuits getting faster and better all the time, and analog devices getting faster f T ’s but virtually dying in all other respects, what transceiver architectures will use digital circuits for what they do best and analog circuits for what they do best? And can we move beyond calibration, tuning, and mode selectability as the only uses of digital circuits in transceivers? One way to make progress on these questions is through analysis of successful examples, and in this chapter we present two designs. A power amplifier (PA) linearizer is the subject of the first part of this chapter, and a chopper-stabilized analog multiplier/mixer is the subject of the second part. In each case we talk separately about what analog and digital techniques bring to the table. We then unite them in an architecture that makes use of both.

14.2

CARTESIAN FEEDBACK: THE ANALOG PROBLEM

Cartesian feedback is one of a number of PA linearization techniques. Other strategies include predistortion, adaptive predistortion, and feedforward linearization (see also Chapter 12). The point of PA linearization is to beat a difficult trade-off that architects of modern wireless systems face. On one hand, the PA consumes the lion’s share of the power budget in most transceivers. It follows that in a cellular phone, for example, battery lifetime is determined largely by the power efficiency of the PA. On the other hand, it may be desirable to have high spectral efficiency—the ability to transmit data at the highest possible rate for a given channel bandwidth. The design conflict is that while spectral efficiency demands a highly linear PA, power efficiency is maximized when a PA is run in its nearly-saturated nonlinear region of operation. The current state of the art is to design a moderately linear PA and employ some linearization technique. The amplifier operates as close to saturation as possible, maximizing its power efficiency, and the linearization system acts to maximize the spectral efficiency in this nearly-saturated region. Among linearization techniques, Cartesian feedback is particularly compelling because it can relax the requirement for a detailed PA model. It is impossible to overstate the value of this advantage. PA models are incredibly complex and resistant to conceptual analysis. With Cartesian feedback, loop bandwidth can be traded for robustness so that wide variations in the details of the PA can be tolerated. PA memory effects, which cause great complications in predistorters and adaptive predistorters, are handled by Cartesian feedback with no fundamental change in implementation. Perhaps because of this fundamental advantage, fully integrated realizations of the Cartesian feedback concept have populated the recent literature [1–3]. A typical Cartesian feedback system is shown in Fig. 14.1. The problem with Cartesian feedback is stability. This is not to say that in general these systems cannot be stabilized. They certainly can be. In exchange for stabilizing the system, though, one accepts an upper limit on the loop bandwidth. Particularly when a surface acoustic wave (SAW) filter is used in the forward path, with its

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CARTESIAN FEEDBACK: THE ANALOG PROBLEM

413

sin t Id (s) -

Σ

eI (s)

Qd (s) -

Σ

eQ (s)

L(s) L(s)

I PA

Q

sin( t + ) cos t

I Q cos( t + )

FIGURE 14.1 Typical Cartesian feedback system. Ideally, φ = 0 and the system acts as two independent, decoupled feedback loops. All signals at RF frequencies in the feedback path have been filtered out.

notoriously large group delay suffered in exchange for sharp cutoff characteristics, this bandwidth may be too small for any but the most narrowband wireless links. The next sections give an overview of the stability problem and then show how a digitally assisted architecture rescues Cartesian feedback from its bandwidth limitations while preserving its power modeling advantage. A detailed treatment of the stability of Cartesian feedback systems is given in the appendix.

14.2.1

Instability Due to Phase Misalignment

Ideally, the system of Fig. 14.1 acts as two independent feedback loops: one for the I channel and one for the Q channel. However, these systems are vulnerable to an apparent phase difference between the local oscillator (LO) sources, and the associated problems are mentioned in practically all literature on the subject [4–14]. This phase difference is represented as φ in the figure. Delay through the PA and transmitter path filters, phase shifts of the RF carrier due to the reactive load of the antenna, and mismatched interconnect lengths between the LO source and the two mixers all manifest as an effective nonzero φ. Worse, the exact value of φ can vary with temperature, process variations, output power, and carrier frequency. A Cartesian feedback system in which φ is nonzero is said to have phase misalignment. In this state, the two feedback loops are coupled, and the stability of the system is compromised. The stability analysis for phase misalignment is well covered in the literature, with treatments to be found in [1,15]. Briffa and Faulkner [15] take their analysis a step further and suggest a graphical technique for dealing with memoryless nonlinearity in the PA. In addition to discussing stability analysis, Dawson and Lee [16] demonstrate how one can choose the loop dynamics to increase a system’s robustness to phase misalignment.

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The easiest way to appreciate the impact of phase misalignment on stability is to write down an effective loop transmission that depends on loop filter L(s)1 and the phase misalignment φ. As shown in the appendix, the effective loop transmission may be written L eff (s, φ) = L(s) cos φ +

[L(s) sin φ]2 1 + L(s) cos φ

(14.1)

There are two interesting limiting cases for phase alignment. One occurs when φ is zero, in which case the effective loop transmission reduces to the uncoupled case. The other occurs when φ is 90◦ , and the loop transmission in (14.1) becomes [L(s)]2 . The loop filter effectively becomes a cascade of two L(s)’s! Whether or not phase misalignment has an impact on bandwidth depends on how the complete system is designed. If the system includes a fast, accurate phase alignment regulator, the effective loop transmission remains L(s) and phase misalignment is a nonissue. If the design must, however, be robust to a certain degree of phase misalignment, that robustness will show up as a reduced guaranteed closed-loop bandwidth for a given required stability margin. This second case is more common.2 14.2.2

Instability Due to Dynamics in the RF Path

It is sometimes true that the RF path is so broadband relative to the baseband electronics that the dynamics of the RF path can be ignored in the stability analysis. However, when pushing for that last ounce of closed-loop speed, the dynamics of every part of the loop matter. The general case gets complicated, because every sinusoid that appears in the baseband signal actually interacts with two parts of the RF transfer function: A sinusoid on the I channel e jωt first gets up-converted to ( j/2)(e j(ω0 +ω)t − e j(ω0 −ω)t ), where ω0 is the carrier frequency, and then passes through the RF dynamics H (s). If we adopt the notation for the linearized dynamics of the RF path3 H ( jω) = |H (ω)|e jβ(ω) and follow things to the bitter end, we find that we can write a more rigorous effective loop transmission by making a substitution into (14.1)  1
|H+ |e j(β+ −φ) + |H− |e− j(β− −φ) 2  +j
|H+ |e j(β+ −φ) − |H− |e− j(β− −φ) sin φ =⇒ 2

cos φ =⇒

1 Any

(14.2)

dynamics introduced in the RF path are ignored until Section 14.2.2. are careful to distinguish phase misalignment from quadrature error in the mixers. It can be shown that in the case of the latter, no phase alignment regulator can perfectly decouple the I and Q loops. Fortunately, mixers with small absolute quadrature errors (±5◦ ) are easily realized. Such small errors cause no serious problems in experiments. 3 The reader may well ask how we can talk about linearized dynamics when the whole point of Cartesian feedback is to deal with an explicitly nonlinear RF path. It turns out that taking this approach, working out the stability analysis as if we were dealing with a linear system, and then modifying that structure to account for nonlinearities leads to the most conceptually transparent development. 2 We

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where for compactness we adopt the shorthand H (ω0 ± ω) = H± and β(ω0 ± ω) = β± . The substitutions of (14.2) are rigorous but more cumbersome than is often warranted, particularly for hand calculations. We can simplify things by observing that even a 20-MHz-wide channel on a 2-GHz carrier, which at the time of this writing is considered a very broadband link, can be considered narrowband. Looking at the magnitude part of the RF transfer function, we observe that the entire channel occupies a mere fraction of a decade, so |H+ | ≈ |H− |. Additionally, we may approximate the phase response as linear in this narrow band and therefore capture the dynamics as a group delay. The details are worked out in the appendix, but the result of making these approximations is that we make the substitutions cos φ =⇒ cos(β0 + φ) sin φ =⇒ sin(β0 + φ)

(14.3)

L( jω) =⇒ |H ( jω0 )|L( jω)e− jωTgd (ω0 ) Here β0 is the phase shift and Tgd (ω0 ) is the group delay at the carrier frequency. The really valuable expressions from the foregoing development are (14.1) together with substitutions (14.3). The critical insight is that β0 can be tuned out by whatever means is in place to deal with phase misalignment. The phase shift due to delay, e− jωTgd (ω0 ) , is, regrettably, fundamental. Like all delays in all feedback systems, the designer is left with no recourse but either to design a noncausal filter4 or to accept an ironclad, immutable upper limit on the achievable closed-loop bandwidth. In applications, it is common for the situation to be even a little more painful. Very often in real transmitters it is advantageous to put a surface acoustic wave (SAW) filter in the transmit path, which is an extremely power-efficient way to reduce out-of-band noise. In exchange for their famously flat passbands and sharp cutoff characteristics, though, they have group delays that work mightily against the Cartesian feedback loop designer. It is not uncommon to see group delays of over 20 ns, which limits the achievable unity gain frequency of the loop to less than 10 MHz.5 If we consider the “linearization bandwidth” the bandwidth over which the loop gain exceeds 40 dB,6 and if we assume dominant-pole compensation, it quickly becomes evident that we will have to work hard to get a linearization bandwidth much over 100 kHz. And that’s before we consider parasitic poles in the system, of which there are many (from the up-conversion mixer, the down-conversion mixer, the summers, the coupler, any amplification in the feedback path, and so on). The bottom line is that left unmodified, Cartesian feedback is almost exclusively limited to low-bandwidth applications. Despite its powerful advantage of greatly 4 A noncausal filter, which is to say, a filter that could predict its future inputs, would have many applications.

20-ns delay results in 90◦ of negative phase shift at 12.5 MHz. choice of definition for the linearization bandwidth is arbitrary and for example purposes only. The gain level that defines the linearization bandwidth in practice will be determined by details of the application.

5A

6 This

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simplifying the PA modeling task, the technique requires some assistance if we are to extend its capabilities to high- bandwidth systems.

14.3

DIGITAL ASSISTANCE FOR CARTESIAN FEEDBACK

So the question becomes: What kind of digital assistance can we employ to overcome the bandwidth limitation of Cartesian feedback? Our motivation is that we wish to take advantage of the analog feedback system as an efficient way to extract a PA model. Figure 14.2 illustrates the key insight that points the way to an effective digital assistance strategy. The insight is that the signals at the baseband inputs of the up-conversion mixers are correctively distorted versions of the baseband symbols desired. One can therefore view a Cartesian feedback system as an analog computer, calculating at every instant the mixer input required to realize the baseband symbol desired. Suppose now that the transmitted data are drawn from a finite set of possible symbols, as is the case with any digital modulation system, and that the power amplifier, while nonlinear, is time invariant. It follows that such a computer would need to perform its calculation only once on a given symbol. If the result is then stored, it could be recalled upon the reappearance of the corresponding symbol. In the system of Fig. 14.1, there are two major shortcomings of purely analog signal processing. These shortcomings represent opportunities for digital assistance not just in the case of Cartesian feedback but in many other systems as well. The first shortcoming is that analog systems lack a good memory mechanism, some way of

Predistortion node sin t Id (s) -

Σ

eI (s)

Qd (s) -

Σ

H(s)

eQ (s)

H(s)

I PA

Q sin cos

t

t

I Q cos t

FIGURE 14.2 Predistorting action of Cartesian feedback.

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taking a measurement, storing it indefinitely, and then retrieving it in a nondestructive manner. The closest we come in the analog domain is arguably a sampling capacitor, which we can use to capture one instantaneous value which then inevitably decays with time. The result is that even in a low-order M-QAM7 wireless system, in which a finite set of input symbols appear over and over during the course of a transmission, an analog Cartesian feedback system dutifully recalculates the proper predistortion value for each symbol, every time. This is useful if the PA’s characteristics drift on time scales similar to the symbol rate transmitted, but ordinarily this drift will be slower by many, many orders of magnitude. A second major shortcoming becomes evident when we consider that a transmitter in a digitally modulated wireless link has a tremendous fundamental advantage. At any given time, we have access to and control of Id and Q d of Fig. 14.1. If we decide to use the predistortion nodes as a way of training a look-up table, we can trade training speed for noise immunity in the system. The slower we train, the smaller noise bandwidth we can use, which means that the noise figure of the feedback path in Fig. 14.1 can in principle be very high. This translates directly into a power savings for the circuitry associated with the feedback path.

14.3.1

Architecture for a Digitally Assisted Cartesian Feedback System

Figure 14.3 shows how digital assistance can be employed to greatly enhance the performance of Cartesian feedback systems. The approach is a two-step process. The first step, shown in Fig. 14.3(a), is where we train the predistortion table. The I and Q values are stepped through all anticipated values. For each value, the Cartesian feedback loop is allowed to settle and then the necessary predistortion symbol is read off the up-converter inputs. This training process can be done very slowly. Once the look-up table has been completely filled, the next step is to shut down the feedback path as shown in Fig. 14.3(b), using the look-up table to perform open-loop predistortion at symbol rates far exceeding those employed in the training step. Notice that we exploit the fact of digital modulation explicitly, taking advantage of the availability of the digital versions of I and Q before they are passed through D/A converters. The primary form of digital assistance comes in the form of digital memory. We find in experiments that we can train at symbol rates as low as 10 kS/s and preserve that “knowledge” in the form of a look-up table that we ultimately use to linearize a 40-MHz-wide channel. Also, we take advantage of our control over the training process to take several predistortion measurements of a given symbol and then use averaging as a way of reducing the noise variance of the measurements. We find that we can exploit two relatively humble capabilities of digital circuits, memory and the ability to do averaging, to greatly enhance the capabilities of Cartesian feedback linearizers.

7 Quadrature

amplitude modulation with a low number, M, of constellation points.

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index

data A/D

I

Q

D/A

D/A

D/A

L(s) cos ω t

SAW

cos ω t −φ

ATTN

PA

L(s)

(a) index index

Look−Up Table data A/D

I

Q

D/A

D/A

D/A

L(s) cos ω t

SAW

cos ω t −φ

ATTN

PA

L(s)

(b)

FIGURE 14.3 System diagram of the basic Cartesian-feedback-for-predistortion concept. In part (a), the look-up table is populated by stepping I and Q to a possible value, waiting for the loop to settle, recording the predistortion symbol at the input of the ADC and then repeating for each possible symbol. Once the look-up table is complete, transmission resumes with no bandwidth limitation, as shown in part (b).

14.3.2

Design Issues for Applications

Once the basic concept of Fig. 14.3 is understood, there a few loose ends that must be addressed before putting the concept to work in a real wireless link. These issues are pulse shaping in M-QAM systems, adapting the technique to work for multicarrier

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FIGURE 14.4 How pulse-shaping filters generate “intermediate” voltage values. On the left is a constellation diagram for a 16-QAM system, and in the middle diagram shows how the voltage on the Q channel might look without filtering. Without filtering, a 16-QAM system might require only 16 entries in the look-up table.

links in which the number of possible symbols is extremely large, the importance of memory effects in a given application; and the issue of training while still connected the antenna. 14.3.2.1 Pulse Shaping and Signals with Large Constellations At first glance, building a predistortion table might seem to be an almost trivial exercise. A channel with extraordinarily low noise might support a constellation as high as 256-QAM, which would, in turn, imply only 256 entries in a look-up table. Figure 14.4 shows that the story is still simple, but not quite as trivial as it may first appear. The issue is that the QAM symbol stream must be filtered. Otherwise, the instantaneous transitions shown in Fig. 14.4 would imply an infinite bandwidth for the channel. Also, special filters, such as raised cosine filters, are essential for minimizing intersymbol interference (ISI). This issue is normally addressed by applying a digital filter [whose impulse response is P(t) in the figure] to the I and Q data streams. Although this neatly solves the problem of infinite bandwidth, the look-up table must now be enlarged to handle the “intermediate” values that result. The concern this raises is that the training time might become too long given the large number of look-up table entries. For example, if the digitally filtered I and Q signals are represented with 10-bit resolution, the look-up table suddenly requires over 106 entries: 210 possibilities for I and Q separately, and 210 × 210 ≈ 106 . However, we have found that performing a separate training operation for every entry is not necessary. An equally spaced subset can be used instead, and simple interpolation can be used to generate all intermediate values. The strategy also makes the technique well suited to multicarrier standards such as OFDM, for which there are an extremely large number of possible symbols. 14.3.2.2 PAs with Memory Effects Figure 14.3 shows a predistortion concept that is specifically optimized for PAs that do not exhibit strong memory effects. When the distortion that a PA applies to a symbol is dependent on the symbols transmitted immediately before it, that PA is said to exhibit nonlinear memory effects [17].

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The importance of these memory effects depends greatly on the PA that is being used, its output power, and the dynamic range requirements of the particular wireless standard that is being employed. There is evidence in the literature to suggest that when the dynamic range requirement is 40 dB, as is the case for the WiMAX standard, memoryless predistortion is sufficient [18]. At present, however, digitally assisted Cartesian feedback occupies a critical position in the power–performance trade-off space for PA linearizers. This technique takes advantage of slow training to use a low-power down-conversion path and ADC. It uses the digital Cartesian components directly instead of a polar look-up table (thereby saving the digital power overhead associated with rapid Cartesian-to-polar conversion). Moreover, by retraining the look-up table whenever necessary, the digital assistance enables adaptive predistortion. The net result is an adaptive, memoryless predistorter that carries extremely low power overhead, making it ideally suited for portable and handset applications. 14.3.2.3 Predistortion and Real Antennas Changing antenna impedance is a difficulty common to all predistorters. Once the predistortion table is programmed, the impedance presented to the PA by the antenna will vary depending on its orientation, its proximity to large metal objects, and other factors. Fortunately, as we show in Section 14.3.3, we find that the benefits of predistortion degrade only slightly for varying antenna impedances, at least up to VSWRs of 3:1. Beyond that level of mismatch, however, the concern shifts from out-of-band emissions to finding a way to keep the PA from destroying itself. This is an important observation because it means that the look-up table can be trained on a dummy 50- load instead of into a real antenna, thus preventing over-the-air emissions during the training process. 14.3.3

Measurement Results from a Prototoype

In this section we describe the results of testing a discrete-component prototype designed to demonstrate digitally assisted Cartesian feedback. The prototype is illustrated in Fig. 14.5. We designed a prototype 900-MHz transmitter built around a class A PA, the Mini-Circuits ZHL-0812HLN. Measurements on our unit showed this PA to have a 1-dB compression point of 27.5 dBm and an output-referred third-order intercept point of 39 dBm. The analog-to-digital conversion was provided by a digital oscilloscope, whose data we could download to a PC. The predistortion look-up table (LUT) was maintained on the PC, and predistorted data streams were then computed using this LUT. Finally, the predistorted and filtered data was uploaded to a Tektronix AFG3102 arbitrary function generator, whose output represented the output of the D/A block in Fig. 14.3. This prototype was first described in [19]. Figure 14.6 illustrates the linearization improvement that we achieved for a 40MHz-wide channel transmitting 16-QAM. These spectra were a critical result for us, because it answered the question of whether linearization data gathered at low symbol rates will still be good at high symbol rates. For this experiment, the LUT was trained on a data sequence at a sampling rate of 5 kS/s, and the closed-loop bandwidth of the analog Cartesian feedback system was 50 kHz. The total number of LUT entries was

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Demodulator

Compact Cartesian

Calibration

LUT Predistorter

DAC

MATLAB

14−bit Arbitrary Waveform Gen. Tektronix AFG3102 AD8340−EVB SAW

Loop Filter Loop Filter

Spectrum Analyzer Tektronix RSA3000

Q DAC

Im{data(t)}

DAC

DAC

I

Q ADC

Re{data(t)}

I ADC

8−bit Oscilloscope Agilent DSO80000

421

Preamp

PA

ZX60−3011 ZHL−0812

LO

SW

Tuner

Dummy load

Signal Generator Phase R&S SMIQ3 Align

Analog Cartesian Feedback

I_offset f Q_offset AD8132

LT5517−EVB

(a)

(b)

FIGURE 14.5 Schematic diagram and photograph of discrete component prototype to prove the digitally assisted Cartesian feedback concept. The analog-to-digital conversion was provided by a digital oscilloscope, and the digital-to-analog conversion was provided by an arbitrary function generator.

1024, and each entry was the result of 32 separate measurements that were averaged in order to reduce the effects of thermal noise. The total training time required was thus 6.55 s.8 The only way this experiment would have failed would have been if nonlinear memory effects were strong enough to dominate the distortion products. 8 See

the discussion on OFDMA transmission for ways to greatly reduce the training time.

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30 20

20 40MHz Channel Power: 26.7 dBm 10 Magnitude (dBm)

10 0 dBm

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−10

Open−loop

−20 −30

Digital predistortion with −10 downconversion noise averaging 0

Digital predistortion

−20 −30

−40

−60

−40

Predistortion

−50 900

920

940 960 Frequency (MHz)

(a)

980

1000

−50

Channel power : 26.1 dBm Channel bandwidth : 2 MHz 944 946 948 950 Frequency (MHz)

952

(b)

FIGURE 14.6 Measurements illustrating the special properties of this linearization system. (a) How the system linearizes a 40-MHz-wide channel using single-carrier 16-QAM modulation. This is twice as broadband as WiMAX, and over 100× the linearization bandwidth afforded by analog Cartesian feedback alone. (b) How, because the training sequence can be done slowly, we can gain immunity to noise in the feedback path through sample averaging.

As it stands, Fig. 14.6 represents a linearization bandwidth improvement of over 100X compared to Cartesian feedback systems that do not have digital assistance. Figure 14.6 illustrates another great advantage that digital assistance brings to Cartesian feedback. In an ordinary Cartesian feedback system, noise in the feedback path is completely indistinguishable from noise in the input. It therefore has the effect of corrupting the LUT with noise. In our prototype, the noise actually came from the analog-to-digital conversion process. From a system standpoint this is equivalent to noise injected either at the input or in the feedback path. With thermal noise, however, if we employ a small noise bandwidth, which is to say, applying a lowpass filter with a low cutoff frequency to the data stream entering the look-up table, we can substantially lower the noise floor. In the present case, we can apply this strategy only if we have the luxury of doing the training slowly. This is exactly what digital assistance allows us to do with Cartesian feedback. In Fig. 14.6, the lowpass filtering took the form of taking several samples from a given data point and performing averaging. The result is a lowered noise floor, as illustrated. Spectra are not the only way to illustrate improved distortion performance, and in Fig. 14.7 we illustrate the improvement in error vector magnitude of the linearized system. Visual inspection reveals that the bulk of the improvement occurs on the outer edges of the constellation. This is expected, as the outer edges correspond to the largest envelope magnitudes. This is where the PA is driven most deeply into compression. Figure 14.8 shows how we modified the prototype system to prevent transmission of training data sequences. In this setup, the LUT is trained while the output of the PA is connected to the dummy load. Once the training is finished, the PA is reconnected to the antenna. This modification may not be necessary for all applications. In some standards there are time windows during which it is permissible to do some sort of

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1 0.5 0

Open−Loop EVM = 8.3%

−0.5 −1 −1

−0.5 0 0.5 1 Normalized I−channel

(a)

Normalized Q−channel

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Normalized Q−channel

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1 0.5 0

Predistortion EVM = 3.7%

−0.5 −1 −1

−0.5 0 0.5 1 Normalized I−channel

(b)

FIGURE 14.7 Measurements showing the improvement in EVM for the prototype linearization system: (a) without linearization; (b) with linearization. For a 16-QAM modulation strategy, the EVM was reduced by more than a factor of 2. Notice particularly the improvement at the four corners, where the symbol magnitudes are the largest and therefore where the PA is driven the deepest into compression.

training or calibration. If this time window is sufficiently long, there is no need for a dummy load. The big concern with the strategy illustrated in Fig. 14.9 is how the system will behave when the antenna impedance changes in response to its environment. It is not uncommon to see VSWRs of 2.0 for ordinary movements of the antenna, and the question is whether the LUT will still be valid when the antenna presents this way. Figures 14.9 and Fig. 14.10 show how the predistortion system continues to reduce out-of-band distortion products for VSWRs up to 3.0. In the case of a VSWR of 1.4, we see that predistortion maintains a linearity advantage for all angles around the Smith chart. For these experiments, we first took an ordinary antenna and characterized its S11 pointing in various directions and in varying proximity to large metal objects. In our experiments we were never able to get the VSWR as high

FIGURE 14.8 Modification of the prototype to prevent transmitting training sequences through the antenna. The LUT is trained while the PA is connected to a dummy load and then reconnected to the antenna when data are transmitted.

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−40 −45 −50 −55 200kHz −60

45

−200kHz

300kHz

90 135 180 225 270 315 Load impedance angle (degree)

−300kHz 360

FIGURE 14.9 Measurements showing the effect of varying antenna impedance for a VSWR of 1.4 (S11 = −16 dB). Dashed lines are without predistortion, solid lines with predistortion.

as 3.0. However, such extreme VSWRs are possible when, for example, the antenna is accidentally disconnected.9 In this instance, however, the concern shifts from outof-band distortion products to basic survival of the PA. Once we had determined that a VSWR of 3.0 was a reasonable magnitude with which to test our system, we connected the linearized PA to a dummy load through a stub tuner and used that tuner to evaluate the linearization performance of our system at VSWRs of 1.4 and 3.0 for angles all around the Smith chart. The narrowband performance of the stub tuner greatly restricted the channel bandwidth that we could use. For these tests we imposed a WiMAX modulation on a 200-kHz-wide channel and on a 300-kHz-wide channel. Figure 14.11 shows the linearization performance for an OFDMA transmission with the Mini-Circuits’ ZHL-0812HLN PA. Multiple carrier transmission standards pose a special challenge for our linearizer because the extremely dense symbol constellation seems to indicate that the LUT size will be prohibitively large. What we found was that it was perfectly acceptable to train a LUT of only a few entries (in this case, 256), and rely on bilinear spline interpolation to fill in the rest of the entries required. For this spectrum we trained the LUT while it was connected to a dummy load, and then measured the output spectrum while the PA was transmitting into a real antenna. In addition, we made an optimization to the system to greatly improve the training time. To obtain the spectrum of Fig. 14.11, we trained the predistorter with the SAW filter removed from the system. This allowed us to run at a much higher loop crossover frequency (1 MHz vs. 50 kHz) during training. We then switched the SAW filter back 9A

consumer may do this absentmindedly during a conversation on a cellular phone, perhaps unscrewing the antenna from its place on the handset. While consumers expect the phone to fail with the antenna disconnected, they expect it to start working again as soon as the antenna is reconnected. The problem is that the extreme VSWR (10:1) or higher may destroy the PA, and the handset manufacturer bears the blame for not making a robust unit. This is a major headache for handset manufacturers.

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−30

ACPR (dBc)

−35 −40 −45 −50

210 degrees

−55 200kHz −60

45

−200kHz

300kHz

90 135 180 225 270 315 Load impedance angle (degree)

−300kHz 360

FIGURE 14.10 Measurements showing the effect of varying antenna impedance for a VSWR of 3.0 (S11 = −16 dB). Dashed lines are without predistortion, solid lines with predistortion.

into the forward path during actual transmission. Each of the 256 LUT entries in the case was the average of 16 measurements. The net result is that for this OFDMA transmission we required only 16 ms of training time for the LUT. Finally, as always, it is important to assess the actual power savings that result from employing a proposed linearization strategy. In Fig. 14.12, we report a 26.5%

10 0 Power (dBm)

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−10 −20 −30

Before Predistortion After Predistortion

−40 −50 890

895

900 Frequency (MHz)

905

910

FIGURE 14.11 Linearization of a 5-MHz bandwidth WiMAX OFDMA modulated signal, transmitting into a real antenna. Despite the implied, prohibitively large look-up table, this spectrum was obtained using a look-up table size of only 256 entries. Bilinear spline interpolation was used to generate intermediate values. In addition, the SAW filter was removed during training to allow a higher closed-loop bandwidth and therefore faster training, and then put back in for the predistorted transmission shown here. The total training time for the look-up table was 16 ms.

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11000 10000 Power consumption (mW)

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9000

2.52−W reduction

8.54 W

8000

7.17 W

7000 6000 5000

26.5% PA power savings

4000 3000 2000

22 mW Digital Predistortion 75 mW Demodulator PA 9613 / 7069 / 7069 mW Pre−amplifier 1320 mW Modulator 75 mW

1000 0 Before Predistortion

Training

After Predistortion

FIGURE 14.12 Comparison of the power required to maintain the required level of linearity between the linearized and nonlinearized cases. On the extreme left, the power increases because the PA needs to run off a higher power supply in order to keep the distortion products in check. On the right, we see the power savings offered by the predistortion method. In each case the power transmitted was approximately 22 dBm, or about the level of that of a cellular handset transmitter.

reduction in power dissipation for a WiMAX-OFDMA transmission at a channel power of 26 dBm channel power over a 5-MHz channel bandwidth. The peakto-average power ratio (PAPR) for this signal is 8.5 dB. One important consideration for all digital predistortion systems is the fact that the baseband predistorted spectrum is considerably expanded over the non-predistorted spectrum. This can be appreciated by considering that if third-order products are to be suppressed, the predistorted spectrum needs to be roughly three times more broadband than in the unpredistorted case; if fifth-order products, there is a fivefold expansion; and so on. This will affect the power dissipation of the DAC, which now must run at a higher sampling frequency, and also power dissipation of some of the digital baseband circuitry, which must also run faster to accommodate the wider bandwidth of the baseband data. However, one of the things that makes digital predistortion such a strong form of digital assistance is that the digital power, which tends to be small to begin with, only gets smaller as CMOS continues to scale.

14.3.4

Summary of Digitally Assisted Cartesian Feedback

Cartesian feedback is a powerful linearization technique for power amplifiers. Power amplifiers are very difficult to model precisely and accurately, and Cartesian feedback presents the option of greatly relaxing the modeling requirements for the PA. The great weakness of analog Cartesian feedback, however, is that we pay for the PA

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modeling simplicity by accepting a bandwidth limitation. This limitation becomes particularly acute when a SAW filter is necessary in the forward path, with the group delay fundamentally limiting the linearization bandwidth to hundreds of kilohertz or less. We provide digital assistance to Cartesian feedback using digital memory, and the simplest of signal processing techniques: averaging and interpolation. These simple tools, humble from the standpoint of a digital designer, allow us to extend the modeling simplicity of Cartesian feedback to applications whose bandwidth is over 100 times as broad as can be handled by analog techniques alone.

14.4 MULTIPLIERS, SQUARERS, MIXERS, AND VGAs: THE ANALOG PROBLEM Analog multipliers are a basic building block that continue to find application even in an increasingly digital world. Their function is to take two voltages or currents as an input, and to produce a voltage or current output proportional to the product of the input signals. Such a block is used frequently in control applications, and can be used to implement an analog squarer or a variable-gain amplifier (VGA). Perhaps the most common current application for analog multipliers is in mixers. On the high-frequency end, various topologies for analog mixers are commonly employed in wireless transceivers, with the down-conversion mixers in homodyne receivers having famously stringent offset performance requirements. On the lowfrequency end, low-offset multipliers are critical for lock-in amplifiers frequently used in medical applications. A mathematically complete description of a multiplier’s offset behavior requires three numbers, as opposed to one for an amplifier. We illustrate these in Fig. 14.13 as δx , δ y , and δo . Of the three, δo tends to dominate in the classic test of shorting the two inputs to zero potential and measuring the output. The reason for this is that for most convenient choices of multiplication constants k, the product kδx δ y will typically be on the order of a few microvolts, whereas δo tends to be on the order of a few millivolts or more. Figure 14.14 shows the analog multiplier core that we fabricated in a 0.18-µm CMOS process, together with a dc sweep showing its characteristics. The topology δo

Vx Vz δx

Vo

Vy δy FIGURE 14.13

Offsets in an analog multiplier.

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RL

RL – Vo +

Vy+

M5

M6

Vx+

M1

M2

Vx–

M7

M8

Vy–

M3

M4

Vx+

(a) 150 100 Vy=–150mV Vy=–100mV Vy=–50mV Vy=0mV Vy=50mV Vy=100mV Vy=150mV

50 Vo (mV)

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0 –50 –100 –150 –150

–100

–50

0

50

100

150

Vx (mV) (b)

FIGURE 14.14 Analog multiplier core, together with the dc characteristic measured. The prototype was fabricated in a 0.18-µm CMOS process. This example exhibits an output offset (δ0 ) of 15.6 mV.

for the multiplier core is chosen from among the many alternatives presented in [20]. This particular multiplier is nice because of its exceptionally linear dc transfer characteristic, but it should be noted that the topology of the multiplier is unimportant for the purposes of this chapter. It will turn out that multipliers with differential or quasidifferential inputs are easiest to use because differential choppers are particularly straightforward.10 Figure 14.14 illustrates one of the major challenges associated with analog multipliers. If there were no offsets, all of the traces in the figure would intersect at the origin. Instead, in this measurement we see a vertical displacement of 15.6 mV, 10 Differential

choppers use four switches to swap the positive and negative paths of a differential periodically (see Fig. 14.17). Mathematically, the effect is to modulate the signal with a square wave that alternates between +1 and −1.

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which is dominated by the δo offset of Fig. 14.13. In addition, we see a horizontal displacement of a few millivolts which betrays the offset δx . If offsets are a key analog problem for these multipliers, what is the most effective digital assistance that we can employ to remove these offsets? We can, of course, do some sort of digital calibration, but the truth is that “digital calibration” presupposes ADCs for which we have solved the very analog problem of low input-referred offsets. The analog problem thus persists even for this digital solution, and we turn to alternative ways to use what CMOS does well in order to alleviate offsets in multipliers.

14.5

DIGITAL ASSISTANCE FOR ANALOG MULTIPLIERS

In this section we show how chopper stabilization has been used for decades to achieve extremely low-offset amplifiers. Originally implemented with electro-mechanical switches, the MOSFET became a tremendous tool for such amplifiers. After reviewing the basics of chopper stabilization, we show how this technique can be modified to create low-offset multipliers. 14.5.1

Classic Chopper Stabilization

Figure 14.15 shows chopper stabilization as classically applied to low-offset amplifiers. The mixer on the input is sometimes configured to pass the signal or, alternately, to short the amplifier input to ground. The effect is to multiply the input signal by a sequence that alternates between +1 and 0. It is more common to apply chopper stabilization to fully differential signal paths, in which case the modulating signal Vch becomes an alternating sequence of +1 and −1. The modulated signal is added to the amplifier’s own offset and then amplified, and at the output of the amplifier there is now a sum of a dc offset and a modulated input. The final step is to modulate, or chop, again with the same signal that was applied at the input of the amplifier. The dc offset inherent to the amplifier is modulated to a high frequency, where it is easily filtered out, and at the end we are ideally left with an offset-free, amplified version of the input. This strategy has been applied for decades, and has recently been used to achieve excellent results in [21,22]. Vch Vos

Vin

Vout LPF

signal 0

offset

FIGURE 14.15

Chopper stabilization for low-offset amplifiers.

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Sometimes, residual chopping tones in the output of the amplifier are objectionable. When this is the case, a pseudorandom waveform instead of a square wave can be used for chopping. For this strategy to work, it is vital that the pseudorandom waveform be truly balanced, so that it has no dc content. 14.5.1.1 How Is Chopper Stabilization Digital Assistance? On first inspection, chopper stabilization hardly seems to rise to the dignity of the title digital assistance. Again, we rely on the simplest possible “digital” tricks: generating pseudorandom waveforms, possibly with linear feedback shift registers, and using MOSFETs for the voltage switching, at which they excel and at which they get better with each passing generation of scaling. Pseudorandom waveforms in particular are very difficult to generate using only analog methods, but are trivial to implement with a few digital gates and shift registers. We will see in Section 14.5.2 that chopper- stabilized multipliers can exploit orthogonal pseudorandom sequences, which are much more difficult to arrange with analog techniques but remain trivial in the digital world; and we have already examined the option of using ADCs and digital calibration to reduce offsets. The point here is that chopper stabilization represents an extremely clever division of functionality between the analog and digital domains. For some applications, it is the optimal division of functionality. 14.5.2

Chopper Stabilization for Multipliers

If, in the frequency domain, all artifacts of the offsets are to be separated from the product desired, we make two important modifications to the traditional chopping strategy, as shown in Fig. 14.16. First, we perform the up-chop operation with two orthogonal waveforms, cx and c y , each of which switches between +1 and −1. Their orthogonality implies that cx c y , the time average of their product, is zero. Second, we perform the down-chop operation with cz = cx c y , the product of the two up-chop signals. Mathematical clarity emerges by recognizing the following identities: ci ci = 1 c x cz = c y c y cz = c x

δo

Vx

Cx

δx

Vy

Vz

Vout Cz

Cy FIGURE 14.16

δy Chopper stabilization for low-offset multipliers.

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Using these identities, we write the output of the chopper stabilized multiplier as Vz = [k(Vx cx + δx )(Vy c y + δ y ) + δo ]cz = kVx Vy + kVx δ y c y + kVy δx cx + (kδx δ y + δo )cz

(14.4)

where k is the constant of multiplication. We see that all artifacts of the multiplier’s offsets are modulated by a chopping waveform and are therefore removable using a lowpass filter. We succeed in realizing offset-free analog multiplication to the extent that the chopping waveforms are perfect. 14.5.3

Limits on Performance

Dc content in the chopping waveforms and nonzero correlation between cx and c y prevent a chopper-stabilized multiplier from achieving zero-offset performance. In this section we describe the various sources of impairment that are under a designer’s control and describe the difficulties that are unique to pseudorandom versus quadrature square-wave chopping. 14.5.3.1 Chopping Waveforms with DC Content To accommodate a ci with a nonzero dc component, we define the dc-free waveform ci according to ci = ci − ci  and define δci as δci = ci . Using (14.4), it is straightforward to see how artifacts of the multiplier’s offsets creep back in. The second term in the full expansion, for examples, becomes kVx δ y (cy + δcy ) = kVx δ y cy + kVx δ y δcy

(14.5)

The artifact kVx δ y δcy is very small because of the product δ y δcy . Nevertheless, it cannot be removed from the output by lowpass filtering. 14.5.3.2 Orthogonal Spreading Codes When seeking nonperiodic choices for the ci , one looks naturally to the spreading codes that have enabled spread-spectrum communications systems. The balance property of these codes is vitally important. A code that has more +1’s than −1’s necessarily has a nonzero ci , the implications of which were examined in Section 14.5.3.1. Of more importance, however, is the correlation between the two up-chopping waveforms cx c y . Again referring to (14.4), we note that correlation between cx and c y results in a dc component in cz . We now write cz as cz + δcz , with δcz = cx c y . The final term in the expansion of (14.4) becomes (kδx δ y + δz )(cz + δcz )

(14.6)

In many practical multiplier topologies, δz , the output offset, is far larger than either δx or δ y , and almost invariably dwarfs their product, δx δ y . We can therefore isolate

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the dominant offset term from 14.6 as δz δcz = δz cx c y  Because of the relative importance of δz in practical multipliers, orthogonality between up-chopping waveforms cx and c y is the single most important variable to control for the designer of high-performance chopper-stabilized dc multipliers. Choices of spreading codes abound in the literature. PN sequences generated by linear feedback shift registers (LFSRs) are easy to implement [23]. The statistics of such sequences are well known, and based on the foregoing analysis it is straightforward to see how their use affects performance. A maximal-length sequence, or M-sequence, from a properly designed n-stage LFSR will produce a sequence of length 2n − 1, with 2n−1 occurrences of +1 and 2n−1 − 1 occurrences of −1. The average value of this waveform is therefore ci  = (1/2n − 1), and we see that using longer M-sequences is one way to improve dc performance. The correlation properties of pseudorandom waveforms are in general more complicated. Gold codes, which are easily generated from M-sequences, are known to have low cross-correlations between different codes [23]. Walsh codes have the advantage of being truly orthogonal [24]. Care must be taken, however, to ensure that the Walsh codes selected are sufficiently random to avoid strong tones and are as dc-balanced as possible. 14.5.3.3 Quadrature Square Waves Based on the discussion in Section 14.5.3.2, quadrature square waves are seen to be nearly ideal. They are perfectly balanced and their zero correlation property is easy to demonstrate [1]. Limits on performance when using quadrature chopping boil down to the difficulty of producing a truly 50% duty cycle square wave. Any deviation from this ideal will result in residual offsets left over from the chopping operation. Another limitation, as with chopper- stabilized amplifiers, is charge injection spikes that occur as the result of the fast switching provided by the choppers [21]. Although the effect is somewhat more complicated in multipliers, owing to the fact that there are two inputs instead of one, the fact remains that the presence of these spikes places a lower limit on the achievable offset for analog multipliers. 14.5.4

Nested Chopper Stabilization

Sometimes in the quest for improved performance, nested chopping is employed in precision low-offset amplifiers [21]. In nested chopping, the inner chopping frequency is chosen high enough to remove all 1/ f noise. However, residual offsets due to switch-charge injection scale linearly with chopping frequency, so this choice of chopping frequency may yet result in unacceptable offset performance. To fix this, the chopper-stabilized amplifier is surrounded by another pair of choppers, these operating at a low enough frequency to enable acceptable offset performance. This architecture thus breaks the trade-off between offset and 1/ f noise performance.

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δo

Vx

Cx,lo

Cx,hi

δx

Vout

+1 Buffer

Vy

Cy,lo

φ Vin+

Cy,hi

Cz,hi

Cz,lo

δy RL

φ

RL – Vo +

Vout+

Vin–

Vout–

FIGURE 14.17

Vy+

M5

M6

Vx+

M1

M2

Vx–

M7

M8

Vy–

M3

M4

Vx+

Employing nested chopper stabilization to get improved offset performance.

Figure 14.17 illustrates the same concept applied to multipliers. As before, chopping waveforms C x,lo and C y,lo are orthogonal to each other, and C x,hi and C y,hi are orthogonal to each other. In the integrated prototype, nested chopping resulted in worst-case offset that was 2.6 times better than in the case of a single layer of chopping. 14.5.5

Measurement Results from a Prototype

To fully test the concept of a chopper-stabilized multiplier, a prototype was fabricated in a 0.18-µm CMOS process [25]. Figure 14.18 shows a die photo of the completed IC. Figure 14.18(a) shows the final dc sweeps of the nested chopper configuration. When compared to Fig. 10.14(b), the improvement in dc offset is clearly visible. All of the traces intersect much closer to the origin than previously. This figure demonstrates the effectiveness of digital assistance in overcoming a major analog problem in multipliers. Fig. 14.19 shows the output spectra of two chopper-stabilized multipliers. This figure provides a comparison between using pseudo-random sequences or using square waves. In the case of square waves, strong tones at the chopping frequencies and harmonics are observable in the spectrum. In the case of pseudorandom sequences, the chopping operation manifests as an elevated noise floor. Table 14.1 is a summary of the offset performance measured for a chopperstabilized multiplier. The multiplier without chopping exhibits an output offset of 15.6 mV. To test the dc offset performance, the three cases of interest are with both inputs nulled and then the two cases of one input at maximum input with the other input nulled. The first case is of interest because in theory it should exhibit the

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(a) 150 100 50 V0 (mV)

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0 –50

–100 –150 –150

–100

–50

0 Vx (mV) (b)

50

100

150

FIGURE 14.18 Die photo of a nested chopper-stabilized multiplier (a), and a dc sweep for the multiplier (b). The prototype was fabricated in a 0.18-µm CMOS process.

lowest offset performance. This can be seen from the analysis in Section 14.5.3.1, where we observe that artifacts due to dc content in the chopping waveforms get nulled out when both inputs are zero. This expectation is validated by the results of Table 14.1, where with even one level of chopping the output offset is reduced to 360 nV. Further reduction of the offset with nested chopping was unobservable in this case, probably due to parasitic thermocouples in the signal path.11 Table 14.1 11 Thermocouple effects are voltages that occur across the junctions of dissimilar metals when a temperature

gradient exists across those junctions. The junctions between tin–lead solder and copper metal traces, for example, can introduce voltage offsets has high as 4µV/◦ C.

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435

0 10kHz Square-wave Chopping 10kHz PN Chopping

–20 Signal Power (dBV)

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–40 –60 –80 –100 –120 –140

0

10

20

30

40

50

60

70

80

90

100

Frequency (kHz)

FIGURE 14.19 codes.

TABLE 14.1

Multiplier spectra for square-wave chopping and using orthogonal spreading

Offset Results for Chopper Stabilized Multiplier

Inner Chopper — Square wave @ 100 kHz Square wave @ 100 kHz Square wave @ 100 kHz Square wave @ 100 kHz Square wave @ 100 kHz 7-bit Gold code over 100 kHz 9-bit Gold code over 100 kHz 11-bit Gold code over 100 kHz

Outer Chopper

Vx

Vy

Vout

— — — Square wave @ 10 kHz — Square wave @ 10 kHz — — —

0 0 0 0 150 mV 150 mV 0 0 0

0 0 150 mV 150 mV 0 0 0 0 0

15.6 mV 0.36 µV 6.06 µV 0.66 µV 4.00 µV 1.52 µV 123 µV 30.6 µV 7.8 µV

also details the performance using orthogonal Gold codes as the chopping sequences. Based on Section 14.5.3.2, we expect the output offset to go as 2n1−1 . We see in the table that this is exactly how the prototype behaves.

14.6

SUMMARY

In this chapter, two examples of digitally assisted RF and analog design were discussed. A singular feature of these two examples was that they were not easily described as “digital circuits cleaning up sloppy analog.” Rather, they are examples of optimal partitioning of functionality between the analog and digital domains. Often when designing with deep-submicron CMOS, the right thing to do will be to

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use digital calibration or digital correction to compensate for the impairments of analog circuits in these technologies, and many excellent examples of this approach have been published in the literature. However, it is also important to recognize the strengths that analog signal processing may bring to the table in a given application and to remember to exploit those strengths.

APPENDIX: STABILITY ANALYSIS FOR CARTESIAN FEEDBACK SYSTEMS Sometimes stabilizing a Cartesian feedback system is easy. If closed-loop speed is not important, simple design conservatism can be used to ensure high stability margins. Things get more complicated, however, for wideband communications systems, where high closed-loop speed is paramount. In this scenario, the designer strives for a design that supports the highest possible data rate. A comprehensive analytical framework to treat the stability of Cartesian feedback systems becomes necessary, one that accommodates not only phase misalignment and memoryless nonlinearity, but also linear dynamics in the RF path (e.g., delay) and PA memory effects. Accordingly, this appendix builds on the existing literature in two important ways. First, it broadens the analysis to take into account dynamics in the RF path as well as memory effects in PAs that have only recently been demonstrated to be critically important. Second, it shows how this two-input, two-output system is best described in the context of single-input, single-output feedback stability theory. A sophisticated set of analysis techniques is devoted to such systems, with Bode plots, Nyquist stability analysis, root-locus techniques, and describing functions forming a partial list. Because these techniques are commonly understood by practicing engineers, they are powerful set of tools to bring to bear on the stability analysis of Cartesian feedback systems. 14A.1

Phase Misalignment and Stability

The term phase misalignment refers to an apparent phase difference between the LO signal feeding the modulator and the LO signal feeding the demodulator. We illustrate this in Fig. 14.1, where the phase-misaligned case corresponds to a nonzero φ. Phase misalignment can happen any number of ways. If two physically distinct LOs are being used, of course, the danger of phase misalignment, not to mention frequency mismatch, is obvious. Even when the same LO source drives both mixers, misalignment can be caused, for example, by slight mismatches in interconnect length between the source and the mixers. Phase shift in the RF signal is also mathematically equivalent to phase misalignment, which means that the phase distortion characteristics of the power amplifier must also be accounted for properly. Variation in the impedance presented by the antenna is yet another cause of phase misalignment, since it can cause a phase shift in the RF signal. Phase misalignment’s impact on stability can be analyzed in several different ways. Here, signals along the I and Q paths of Fig. 14.1 are treated as two separate, real variables.

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14A.1.1 Effective Loop Transmission Our overall approach is to treat the Cartesian feedback system as one single-input, single-output feedback loop. A sophisticated set of analysis techniques is devoted to such loops, with Bode plots, Nyquist stability analysis, root-locus techniques, Nichols charts, and gain and phase margin forming but a partial list. By identifying an effective or equivalent loop transmission for the entire system, then, we bring a powerful body of knowledge to bear on the stability analysis problem. It is necessary to recall that phase misalignment causes the down-converted symbol S  = (I  , Q  ) to be rotated relative to the up-converted symbol S = (I, Q). To within a multiplicative constant, we have I  = (I cos φ + Q sin φ) 

Q = (−I sin φ + Q cos φ)

(14A.1) (14A.2)

We see that for φ = 0, an excitation on the I input of the modulator results in a signal on the Q  down-converter output (and similarly for Q and I  ). The two loops are coupled. Ultimately, we seek the transfer functions I  (s)/Id (s) and Q  (s)/Q d (s) of the closed loop. We can begin by considering the error signals e I (s) and e Q (s) shown in Fig. 14.1. For this linearized analysis, superposition holds, so we can ease the task of computing I  (s)/Id (s) by setting Q d = 0. Let the phase misalignment be φ. The error expressions, as a function of the single input Id (s), are written e I (s) = Id (s) − L(s)e I (s) cos φ − L(s)e Q (s) sin φ

(14A.3)

e Q (s) = L(s)e I (s) sin φ − e Q (s)L(s) cos φ

(14A.4)

where L(s) includes the dynamics of the loop compensation scheme H (s) and the dynamics introduced by the modulator, and demodulator. From here, it is straightforward to derive the transfer functions that we seek: [L(s) sin φ]2 I  (s) 1 + L(s) cos φ = Id (s) [L(s) sin φ]2 1 + L(s) cos φ + 1 + L(s) cos φ L(s) cos φ +

(14A.5)

Repeating for (Q  (s)/Q d (s)), we get the identical result [L(s) sin φ]2 Q  (s) 1 + L(s) cos φ = Q d (s) [L(s) sin φ]2 1 + L(s) cos φ + 1 + L(s) cos φ L(s) cos φ +

(14A.6)

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For completeness we can also use the error expressions to derive the “cross” transfer functions Q  /Id and (I  /Q d ): I  (s) L(s) sin φ = Q d (s) 1 + L(s) cos φ

Q  (s) −L(s) sin φ = Id (s) 1 + L(s) cos φ

1 1 + L(s) cos φ +

[L(s) sin φ]2 1 + L(s) cos φ

(14A.7)

[L(s) sin φ]2 1 + L(s) cos φ

(14A.8)

1 1 + L(s) cos φ +

We see that (14A.5) and (14A.6) are formally identical to the closed-loop response of a typical feedback system. We identify the feedback path as simply unity. The forward path is then given by the effective loop transmission L eff (s, φ) [1]: L eff (s, φ) = L(s) cos φ +

[L(s) sin φ]2 1 + L(s) cos φ

(14A.9)

The most important result of the foregoing derivations is the expression for L eff (s). With this, one can employ the entire formalism of classical control theory in analyzing Cartesian feedback systems. One simply substitutes L eff at the appropriate value of φ wherever the loop transmission is called for, be it for plotting Nyquist contours, doing root-locus diagrams, using Nichols charts, or Bode plots. As an example, Fig. 14A.1 shows a Nyquist plot parameterized in the phase misalignment φ. Figure 14A.2 illustrates the system under sufficient phase misalignment to cause instability, as evinced by the clockwise encirclement of the −1 + 0 j point. For both plots, the loop transmission for φ = 0 is chosen to be k/(s + 1), with k set to 3.3 for easy plotting over a wide range of misalignments. 14A.1.2 Two Key Analytical Results There are at least two more important results that can be derived using (14A.9). The first concerns the unity gain or crossover frequency, ωc , and the second is an important clarification on the meaning of phase margin for this system. The function L eff has the remarkable property that its unity gain frequency is the same as that of L(s) regardless of the phase misalignment φ [26]. To see this, we write (14A.9) in the equivalent form

L eff (s, φ) =

L(s) cos φ + [L(s)]2 1 + L(s) cos φ

(14A.10)

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Nyquist plots for phase misalignments from 0 to 90 degrees

Imaginary Axis

10 5 0 −5 −10 −2

0

2

4 6 Real Axis

8

10

12

Imaginary Axis

1 φ= 0

φ = 90

0.5 0 −0.5 −1 −1.5

−1

−0.5 Real Axis

0

0.5

Imaginary Axis

FIGURE 14A.1 Parameterized Nyquist plot for a dominant-pole compensated system. The phase misalignment is swept from 0 to 90◦ . 40 30 20 10 0 −10 −20 −30 −40 −80

Nyquist plot for phase misalignment of 110 degrees

−70

−60

−50

−40 Real Axis

−30

−20

−10

0

0.2 Imaginary Axis

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−1

−0.5

0

Real Axis

FIGURE 14A.2 Nyquist plot of dominant-pole compensated system with phase misalignment of 110◦ . Encirclement of the −1 + 0 j point indicates instability.

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and note that at the unity gain frequency ωc , L( jωc ) = e jθ for some θ . Substituting, and calculating |L eff (ωc , φ)|2 , we have |L eff (ωc , φ)|2 = =

e jθ cos φ + e2 jθ e− jθ cos φ + e−2 jθ 1 + e jθ cos φ 1 + e− jθ cos φ 1 + 2 cos θ cos φ + cos2 φ 1 + 2 cos θ cos φ + cos2 φ

=1

(14A.11)

Changing φ, then, neither speeds up nor slows down the closed-loop response of the system. In single-input, single-output systems, determining the closed-loop poles amounts to determining the roots of the characteristic equation 1 + L(s) = 0

(14A.12)

It is clear that at a pole of the closed-loop transfer function, |L(s)| = 1 and ∠L(s) = −π . Using the new characteristic equation, 1 + L(s) cos φ +

[L(s) sin φ]2 =0 1 + L(s) cos φ

(14A.13)

we can derive new magnitude and angle conditions on L(s). Multiplying both sides of (14A.13) by (1 + L(s) cos φ) and simplifying, we obtain 1 + 2L(s) cos φ + [L(s)]2 = 0

(14A.14)

The quadratic formula gives [15] L(s) =

−2 cos φ ±

 2

4 cos2 φ − 4

= − cos φ ± j sin φ = e− jπ e± jφ (14A.15)

For a phase misalignment φ, then, the magnitude condition remains unchanged, while one of the two angle conditions becomes ∠L(s) = −(π − |φ|). It is important to be clear about the implications of this new angle condition. It is true, for example, that the maximum tolerable phase misalignment is equal to the phase margin of the original, phase-aligned system. It is not true, however, that the phase margin of the system is exactly reduced by the phase misalignment. The phase margin of classical control theory, which allows us to estimate things such as magnitude peaking in the frequency response or overshoot in the step response, is concerned with how close the angle of the loop transmission is to −π at the crossover frequency. For Cartesian feedback systems with phase misalignment, the loop transmission is L eff (s, φ), not L(s). At the unity crossover frequency ωc , where |L( jωc )| = 1 and

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∠L( jωc ) = θ , we can use (14A.10) to show that the phase of the effective loop transmission at crossover is given by

∠L eff ( jωc ) = θ + arctan

14A.2

sin θ sin2 φ 2 cos φ + cos θ (1 + cos2 φ)

(14A.16)

Dynamics and Delay in the RF Signal Path

The foregoing treatment isolates phase misalignment and a designer-chosen loop filter [L(s)] as the only sources of phase shift in the loop. However, it is often necessary to introduce dynamics in the RF signal path as shown in Fig. 14A.3. This could be intentional, as when a designer uses a surface-acoustic wave (SAW) filter to reduce out-of-band noise. Or it could be unintentional, perhaps as a result of parasitic capacitance and/or inductance in the RF path. Regardless, our analytical framework up to this point cannot accommodate delay or linear dynamics in the RF path. This can be understood by considering that on physical grounds, an RF filter must have at least two effects on the stability of the system. First, the phase shift that it introduces must manifest as an effective phase misalignment, to be handled as above. Second, a group delay TD introduced by the filter should be the same as delay introduced anywhere else in the system, and should therefore be referable to L(s) as the modified loop filter L(s)e−sTD . We use these insights to guide our expansion of the stability analysis to include delay and RF dynamics. We treat the general case first, followed by the important simplifications that will be of use in most applications. 14A.2.1 General Case To start, (14A.1) and (14A.2) must be modified to take into account that the RF signal might have been phase shifted before down-conversion. Figure 14A.4 shows the mathematical experiment whose generalization to include both I and Q yields the necessary expressions. Here we show the I channel and

Id (s) -

Σ

eI (s)

L(s)

eQ (s)

Qd (s) -

Σ

L(s)

I

sin t

Q cos t

H(s)

PA

sin( t + ) I Q cos( t + )

FIGURE 14A.3

Cartesian feedback system with linear dynamics in the RF path.

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sin I = ej

0t

t

H(s) sin(

0t

+ )

I Q cos(

0t

+ )

FIGURE 14A.4 System for determining effective loop transmission when there are linear dynamics in the RF path.

determine the outputs I  and Q  . The input on the I channel is the ordinary12 sinusoid e jωt , which is then modulated by sin ω0 t = ( j/2)(e jω0 t − e− jω0 t ). After passing through a linear block H (s) which includes any linear dynamics and delay of the RF signal path, we demodulate with the phase-misaligned LO signals − sin(ω0 t + φ) = −( j/2)(e jω0 t e jφ − e− jω0 t e− jφ ) to get I  and cos(ω0 t + φ) = 1 jω0 t jφ (e e + e− jω0 t e− jφ ) to get Q  . 2 If we adopt the notation for the system function H ( jω) = |H (ω)|e jβ(ω) , the output of the H (s) block is  j |H (ω0 + ω)|e j(ω0 +ω)t e jβ(ω0 +ω)t − |H (ω0 − ω)|e j(ω0 −ω)t e− jβ(ω0 −ω) (14A.17) 2 We have exploited conjugate symmetry of H (s) via |H (ω0 − ω)| = |H (ω − ω0 )| and β(ω0 − ω) = −β(ω − ω0 ). We relax the notation by adopting the shorthand H (ω0 ± ω) = H± and β(ω0 ± ω) = β± , and render (14A.17) as the more compact  j |H+ |e j(ω0 +ω)t e jβ+ − |H− |e j(ω0 −ω)t e− jβ− 2

(14A.18)

With this expression we can derive I  . We demodulate by multiplying (14A.18) by −( j/2)(e jω0 t e jφ − e− jω0 t e− jφ ). Keeping only the low-frequency terms (it can be safely assumed that terms involving 2ω0 are filtered out), we are left with I = 12 We

 1
|H+ |e j(β+ −φ) + |H− |e− j(β− −φ) e jωt 2

(14A.19)

emphasize “ordinary” in the sense that its imaginary part implies nothing about the signal on the Q channel. In our development, we treat I and Q as two separate signals, as opposed to the real and imaginary parts of the complex signal I + j Q.

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where we have put in the same factor of 2 that we used to normalize (1) and (2). Performing the same manipulations to get Q  , we arrive at Q =

 −j
|H+ |e j(β+ −φ) − |H− |e− j(β− −φ) e jωt 2

(14A.20)

The importance of (14A.19) and (14A.20) is that they enable us to handle the general case of dynamics in the RF path. As a check, we consider the case for which |H (ω)| = 1 and β(ω) = 0 for all ω, or the absence of dynamics in the RF path. In this case, (14A.19) and (14A.20) reduce to I  = [cos φ] e jωt 

Q = [− sin φ] e

jωt

(14A.21) (14A.22)

which is in agreement with (14A.1) and (14A.2). It turns out that to handle the general case of dynamics in the RF path, we simply return to the effective loop transmission of (14A.9) and make the substitutions  1
|H+ |e j(β+ −φ) + |H− |e− j(β− −φ) 2  +j
|H+ |e j(β+ −φ) − |H− |e− j(β− −φ) sin φ =⇒ 2

cos φ =⇒

(14A.23)

Notice that these substitutions have the required conjugate symmetry in ω, so there is no issue replacing real quantities cos φ and sin φ with the complex expressions as suggested. From here, rigorous stability analysis will usually mean doing Nyquist plots with (14A.9) using the substitutions (14A.23). That Nyquist plots are called for is fortunate, because commercial RF filters rarely come with closed-form expressions for their frequency response. Instead, plots of their magnitude and phase response are either provided or are straightforward to measure in the laboratory. We close this subsection by noting that we have made no assumptions, even reasonable ones, about H (s). It turns out that real-world assumptions often greatly simplify the substitutions (14A.23), and we turn to them now. 14A.2.2 Pure Delay The first common scenario is that the dynamics in the RF path are well represented by a pure delay. A pure delay can be introduced in an RF system simply by inserting a coaxial cable in the signal path. It also common for SAW filters, in addition to their spectrum shaping properties, to introduce delay. The case of H (s) being a pure delay results in a dramatic simplification of the expressions derived so far. If H (s) is a pure delay of length TD , its transfer function is H (s) = e−sTd . In the development above, this means that|H+ | = |H− | = 1 and β± = −(ω0 ± ω)Td . If we

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revisit the substitutions of (14.2), we find that they become cos φ =⇒ e− jωTd cos(ω0 Td + φ) sin φ =⇒ e− jωTd sin(ω0 Td + φ)

(14A.24)

It is actually more satisfying to make three substitutions: cos φ =⇒ cos(ω0 Td + φ) sin φ =⇒ sin(ω0 Td + φ) L( jω) =⇒ L( jω)e

(14A.25)

− jωTD

This is exactly what we expect. Delay anywhere in the system should be referable to the loop filter, and the mathematics bear that out. Additionally, delay in the RF path is going to shift the carrier, and that should manifest as additional phase misalignment. 14A.2.3 Narrowband Approximation A second, extremely common situation in RF systems is that the modulation is narrowband. That is, the data bandwidth is less than one-tenth of the carrier frequency. This is almost always the situation, except with explicit exceptions such as ultrawideband (UWB) standards. Even modern highdata-rate wireless standards such as WiMAX have channel bandwidths (20 MHz) that are dwarfed by the carrier frequency (≥ 2 GHz). We expect, therefore, that even if the RF transfer function H (s) does vary dramatically with frequency, it will probably not vary greatly over the modulation bandwidth. Mathematically, two judicious approximations can encapsulate the narrowband assumption. First, we say that |H+ | ≈ |H− | and that a sensible value for both of these quantities is |H ( jω0 )|. Second, we observe that over a restricted frequency range, we may approximate the phase response of H ( jω) as linear. That is, β(ω0 ) = −β0 β+ ≈ −β0 − ωTgd (ω0 )

(14A.26)

β− ≈ −β0 + ωTgd (ω0 ) where Tgd (ω0 ) is the group delay of the RF dynamics evaluated at the carrier frequency ω0 . Making these approximations allows us to rewrite the substitutions of (14A.25) as cos φ =⇒ cos(β0 + φ) sin φ =⇒ sin(β0 + φ) L( jω) =⇒ |H ( jω0 )|L( jω)e

(14A.27) − jωTgd (ω0 )

Far and away, the substitutions (14A.27) will be the ones called for most frequently in practical systems. Because there are many active components in the loop, with

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the consequent parasitic poles, it is very difficult to achieve bandwidths that are high relative to the carrier frequency.

14A.3

Memoryless and Quasi-memoryless PA Nonlinearity

Power amplifiers stand out in RF circuit design as one of the few areas where nonlinearity cannot be ignored. Sophisticated nonlinear analysis techniques such as the Volterra series and Wiener theory, consistently find a place with PAs if almost nowhere else in RF circuits. Nonetheless, if we focus on stability analysis instead of predicting all aspects of behavior, we find that some simplifications can be employed. Describing functions prove exceptionally useful. In the context of memoryless nonlinearity, the dominant effects are amplitudeto-amplitude modulation (AM/AM) and amplitude-to-phase modulation (AM/PM). AM/AM modulation refers to the fact that the output amplitude depends in a nonlinear way on the input amplitude. Usually, this shows up as what is called gain compression: The gain of the PA diminishes as the input amplitude increases. Very often PAs will also impart an amplitude-dependent phase shift to the carrier. We refer to this phenomenon as AM/PM distortion [27]. When it comes to stability analysis for PAs that exhibit AM/PM distortion, one approach is to simplify the analysis by focusing on bounds on the phase misalignment. That is, we guarantee that the system stability margins are sufficient for the worstcase phase deviation attributable to AM/PM distortion. From a design standpoint this means that we choose L(s) to give us the phase misalignment tolerance that we need. An example design that works under extreme circumstances is described in [16]. Fortunately, it is often true that the fluctuations of the envelope are not so deep as to cause massive phase excursions. Exotic choices for L(s) are typically not warranted. To handle the AM/AM distortion analytically, it is useful to recall that the PA is considered weakly nonlinear in the sense that distortion products are usually more than 20 dB down from the principal components. PAs in this class are therefore well served by describing functions [28]. A diagram showing the PA viewed through the lens of describing functions is shown in Fig. 14A.5. We see the PA as an amplitudedependent gain block that contributes distortion products as additive disturbances. This representation has the benefit of making direct use of data that are readily available. It is common, for example, to either provide gain vs. output power curves for commercial PAs or to measure them in the lab.

E sin( t)

PA

|GD (E)| sin( t)

Σ

of distortion products FIGURE 14A.5

Using describing functions to treat AM/AM distortion.

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DIGITALLY ASSISTED RF ARCHITECTURES: TWO ILLUSTRATIVE DESIGNS

It is important here to note two simplifications on top of the simplifications represented by using describing functions in the first place. First, general treatments of describing functions emphasize the possibility of a frequency dependence. That is, G D (E) becomes G D (E, ω). However, frequency dependence implies memory, and at this stage in the analysis we consider only memoryless and quasi-memoryless nonlinearity. Second, normally in describing function treatments the output of the PA is |G D (E)| sin(ωt + ∠G D (E)), where ∠G D (E) is an amplitude-dependent phase shift. In this case, though, that phase shift actually represents AM/PM distortion. If the worst-case phase shift from the PA has already been accounted for as a bound, there is no need to keep track of it here. It is worth emphasizing the utility of bounds as a way to navigate the stability analysis for Cartesian feedback systems. For reasons of robustness, it rarely makes sense to have the stability of the system depend on the finest details of the PA model that are available. An excellent use for AM/AM and AM/PM curves is to use them to set bounds. For example, one could choose the worst-case combination of describing function gain and phase excursion and then choose the loop compensation L(s) to stabilize the system under these most demanding circumstances. 14A.4

Memory Effects in PAs

The recent literature in PA modeling has had much to say on the subject of memory effects (for an excellent overview, see [17]). Qualitatively, the observation is that the distortion introduced by a PA at a given instant depends on the history of the the signal before that instant. Memory effects are much more pronounced in high-power PAs such as those used in cellular base stations transmitting at 10 W and higher. In mobile units, where the powers transmitted are on the order of 1 W, memory effects are often negligible. There are many ways to represent a PA with memory effects. As pointed out in [17], the choice of representation is often strongly influenced by the parameter extraction process that is most convenient to implement. Figure 14A.6 shows the representation advanced in [27]. This is called a parallel Wiener model, and its structure has the advantage of being completely general. The model consists of one or more parallel branches, each H0 (s)

F0 ( )

H1 (s)

F1 ( )

Σ

Hn (s) FIGURE 14A.6

Fn ( )

Parallel Wiener model for nonlinear systems.

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REFERENCES

H0 (s) H1 (s) Ae

E0 ej( t+ 0 )

E1 ej( t+ 1 )

447

G0 (E0 ) G1 (E1 )

j t

Σ

Hn (s)

En ej( t+ n )

Gn (En )

of distortion products

FIGURE 14A.7 Parallel Wiener model, modified to treat the memoryless nonlinearities with describing functions.

consisting of a cascade of a linear filter and a memoryless nonlinearity. In addition, the authors of [27] describe a method for identifying the H ( jω)’s and F(·)’s based on laboratory measurements. Once the various elements of Fig. 14A.6 have been identified, we can progress toward a stability analysis with the aid of describing functions as shown in Fig. 14A.7. Part of what we exploit here is that we seek only stability information, not a complete characterization of the PA output. If we need a complete characterization of the PA output, the details of the additive disturbances in Figs. 14A.6 and 14A.7 become important. The only recourse then is detailed simulation and/or measurement on actual hardware. However, for stability analysis, identification of the elements of Fig. 14A.6 is the primary requirement. The next step is to derive the describing functions for the memoryless nonlinear blocks. The analysis then proceeds with the understanding that the stability margins will be a function of the output power of the PA. Acknowledgments The author gratefully acknowledges Sungwon Chung, Philip Godoy, Ali Hadiashar, Jack Holloway, and Jeffrey Huang, graduate students in the Dawson research group at MIT, whose work is described in these pages. The author would also like to acknowledge Lawrence Larson at the University of California–San Diego, Kofi Makinwa of the Delft University of Technology, and Timothy Denison of Medtronic for extremely helpful discussions. Finally, National Semiconductor deserves thanks for fabrication support.

REFERENCES 1. J. L. Dawson and T. H. Lee, “Automatic phase alignment for a fully integrated Cartesian feedback power amplifier system,” IEEE J. Solid-State Circuits, vol. 38, pp. 2269–2279, Dec. 2003.

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2. F. Carrara, A. Scuderi, and G. Palmisano, “Wide-bandwidth fully integrated Cartesian feedback transmitter,” in IEEE Custom Integrated Circuits Conference (CICC), pp. 451– 454, 2003. 3. J. Pipilos, Y. Papananos, N. Naskas, M. Zervakis, J. Jongsma, T. Gschier, N. Wilson, J. Gibbins, B. Carter, and G. Dann, “A transmitter IC for TETRA systems based on a Cartesian feedback loop linearization technique,” IEEE J. Solid-State Circuits, vol. 40, pp. 707–718, Mar. 2005. 4. B. Razavi, RF Microelectronics. Upper Saddle River, NJ: Prentice Hall, 1998. 5. M. Johansson, “Linearization of RF power amplifiers using Cartesian feedback,” Technical Report, Thesis for the degree of Teknisk Licentiat, Lund University, 1991. 6. M. Boloorian and J. McGeehan, “The frequency-hopped Cartesian feedback linear transmitter,” IEEE Trans. Veh. Technol., vol. 45, pp. 688–706, Nov. 1996. 7. M. Johansson and L. Sundstr¨om, “Linearisation of RF multicarrier amplifiers using Cartesian feedback,” Electron. Lett., vol. 30, pp. 1110–1111, July 1994. 8. A. Bateman, D. Haines, and R. Wilkinson, “Linear transceiver architectures,” in IEEE Conference on Vehicular Technology, pp. 478–484, 1988. 9. M. Johansson and L. Sundstr¨om, “Linearised high-efficiency power amplifier for PCN,” Electron. Lett., vol. 27, pp. 762–764, Apr. 1991. 10. M. Briffa and M. Faulkner, “Gain and phase margins of Cartesian feedback RF amplifier linearisation,” J. Electr. Electron. Eng. Aust., vol. 14, pp. 283–289, Dec. 1994. 11. M. Briffa and M. Faulkner, “Dynamically biased Cartesian feedback linearization,” in Proc. 1993 IEEE Vehicular Technology Conference, pp. 672–675, 1993. 12. Y. Ohishi, M. Minowa, E. Fukuda, and T. Takano, “Cartesian feedback amplifier with soft landing,” in 3rd IEEE International Symposium on Personal, Indoor, and Wireless Communications, pp. 402–406, 1992. 13. M. Faulkner, D. Contos, and M. Briffa, “Performance of automatic phase adjustment using supply current minimization in a RF feedback lineariser,” in 8th IEEE International Symposium on Personal, Indoor, and Mobile Radio Communications, pp. 858–862, 1997. 14. D. Cox, “Linear amplification by sampling techniques: a new application for delta coders,” IEEE Trans. Commun., vol. 23, pp. 793–798, Aug. 1975. 15. M. Briffa and M. Faulkner, “Stability analysis of Cartesian feedback linearisation for amplifiers with weak nonlinearities,” IEE Proc. Commun., vol. 143, pp. 212–218, Aug. 1996. 16. J. L. Dawson and T. H. Lee, “Cartesian feedback for RF power amplifier linearization,” in Proceedings of the American Control Conference, pp. 361–366, 2004. 17. J. C. Pedro and S. A Maas, “A comparative overview of microwave and wireless poweramplifier behavioral modeling approaches,” IEEE Trans. Microwave Theory Tech., vol. 53, pp. 1150–1163, Apr. 2005. 18. S. McBeath and D. Pinckley, “Digital memory-based predistortion,” in IEEE MTT-S Symposium, pp. 1553–1556, 2005. 19. S. Chung, J. W. Holloway, and J. L. Dawson, “Energy-efficient digital predistortion with lookup table training using analog Cartesian feedback,” IEEE Trans. Microwave Theory Tech., vol. 56, pp. 2248–2258, Oct. 2008. 20. G. Han and E. S´anchez-Sinencio, “CMOS transconductance multipliers: a tutorial,” IEEE Trans. Circuits Syst. II, vol. 45, pp. 1550–1563, Dec. 1998.

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21. A. Bakker, K. Thiele, and J. Huijsing, “A CMOS nested chopper instrumentation amplifier with 100nV offset,” IEEE J. Solid-State Circuits, vol. 35, pp. 1877–1883, Dec. 2000. √ 22. Q. Huang and C. Menolfi, “A 200nV offset 6.5nV/ Hz noise PSD 5.6kHz chopper instrumentation amplifier in 1µm digital CMOS,” in ISSCC Digest of Technical Papers, pp. 362–363, 2001. 23. R. L. Pickholtz, D. L. Schilling, and L. B. Milstein, “Theory of spread-spectrum communications: a tutorial,” IEEE Trans. Commun., vol. 30, pp. 855–884, May 1982. 24. A. Viterbi, CDMA: Principles of Spread Spectrum Communication. Reading, MA: Addison-Wesley, 1995. 25. P. Godoy and J. L. Dawson, “Chopper stabilization of analog multipliers, variable gain amplifiers, and mixers,” IEEE J. Solid-State Circuits, vol. 43, pp. 2311–2321, Oct. 2008. 26. M. Briffa and M. Faulkner, “Stability considerations for dynamically biased cartesian feedback linearization,” in 44th IEEE Vehicular Technology Conference, pp. 1321–1325, June 1994. 27. H. Ku, M. McKinley, and J. S. Kenney, “Quantifying memory effects in RF power amplifiers,” IEEE Trans. Microwave Theory Tech., vol. 50, pp. 2843–2849, Dec. 2002. 28. J. K. Roberge, Operational Amplifiers: Theory and Practice. New York: Wiley, 1975.

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PART IV Digital Signal Processing for RF Transceivers

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RF Impairment Compensation for Future Radio Systems MIKKO VALKAMA Tampere University of Technology, Tampere, Finland

15.1

INTRODUCTION AND MOTIVATION

The future of wireless communications is strongly heterogeneous, being composed of a rich mixture of various mobile cellular systems (UMTS/HSPA, LTE, WiMAX, IMT-Advanced, etc.), fixed wireless local area networks (e.g., 802.11x), short-range low-energy personal communications (UWB), positioning and navigation systems (e.g., GPS, Galileo), and broadcasting systems (e.g., DVB-H) [1]. To access these systems and services using a single user terminal, highly flexible and reconfigurable radio transmitters and receivers are needed. In addition to the flexibility aspect, another major issue in the design and implementation of radio equipment for massmarket applications is the cost-efficiency, in terms of radio implementation size, cost, and power consumption. This applies also to the base station radio equipment used, for example, in cellular systems. The cost-efficiency issues of individual radios are emphasized especially when multiple transmitting and receiving antennas and thus multi-antenna waveforms are deployed, calling for multiple parallel radio implementations operating simultaneously in a single device [2–6]. In general, building such compact and low-cost yet flexible and high-quality radio equipment for future wireless systems is a very challenging task. On the one hand, the needs for flexibility and reconfigurability prevent using dedicated hardware particularly designed and optimized for only a single application or part of the radio spectrum; and on the other hand, to keep the overall size and cost of the radio equipment feasible, especially in multi-antenna multi-radio scenarios, the cost and size of individual radios are strongly limited. As a result, various imperfections and impairments are expected to take place in the radio transceivers, especially in the radio-frequency (RF) analog electronics. Good examples of such imperfections are (1) mirror-frequency interference due to I/Q imbalance, (2) nonlinear distortion due to mixer and amplifier nonlinearities, (3) timing jitter in sampling and analogto-digital converter (ADC) circuits, and (4) oscillator phase noise [4,6–13]. These Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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impairments, if not properly understood and taken into account, can easily become a limiting factor to the quality and performance of the entire wireless system. This is even more true when more complex and more sensitive high-order modulated wideband communications waveforms are being deployed in future systems. In this chapter we focus on describing the most essential RF impairments typically encountered in radio transceiver design and implementation and their impact in future wireless systems such as 3GPP long-term evolution (LTE) [14,15]. This includes essential RF impairment signal models, impact and performance analysis, as well as developing digital signal processing (DSP)–based techniques for RF impairment mitigation in sophisticated radio transmitters and receivers. In compensation algorithm developments, I/Q imbalance and mirror-frequency interference mitigation are used here as an example case. An extensive list of essential literature and references is also given at the end of the chapter. In general, the impairment mitigation task and possibilities can be viewed from at least two somewhat different angles. If the effects of such impairments can be reduced using sophisticated DSP, either (1) more complicated and sensitive waveforms can be transmitted and received using any given analog RF modules, or (2) cheaper and less complex RF parts can be used to transmit and receive any given waveforms. Instead of adding the complexity and costs of the analog RF parts to meet the performance specifications, the idea is to enhance the quality of the signals using DSP, in such a way that the overall implementation size and costs of the transceiver are minimized. In addition to purely DSP-based solutions, hybrid analog–digital solutions with information exchange between the digital and analog front ends inside a transceiver are an interesting alternative with many possibilities. Altogether these “dirty-RF” issues are seen to be very important and to play a major role in the future wireless systems evolution, especially in the radio equipment used in them. Conceptually, this has already been acknowledged by both the wireless industry and the academic research community of the field. Overall, the dirty-RF theme and impairment mitigation can be seen as a very challenging research area in the sense that deep understanding is required on both sides of the analog–digital interface in radios, including analog RF modules and electronics as well as baseband digital signal processing techniques. 15.2 15.2.1

TYPICAL RF IMPAIRMENTS Radio Transmitters and Receivers at the Conceptual Level

In wireless systems based on digital transmission techniques, the transmitter and receiver functionalities can in principal be divided into (1) digital baseband/IF parts and (2) analog baseband/IF/RF parts. This is illustrated in Fig. 15.1. On the transmitter side, the digital functionalities typically include baseband waveform generation (coding, constellation mapping, pulse shaping, etc.), and possibly, frequency translation to an intermediate frequency (IF), while the analog parts then convert the signal to the final RF range, including power amplification. On the receiver side, the analog front end translates the RF signal to lower frequencies and also implements some

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TYPICAL RF IMPAIRMENTS

I D/A

455

LPF RF PA I/Q LO

DSP Q D/A

(a) DIGITAL BB/IF

LPF ANALOG BB/IF

ANALOG RF

AGC I

LPF

A/D

RF LNA BPF

DSP

I/Q LO AGC

(b)

Q LPF ANALOG RF

FIGURE 15.1

A/D ANALOG IF/BB

DIGITAL IF/BB

Principal (a) transmitter and (b) receiver block diagrams.

band limitation and amplification. Final selectivity is then usually implemented in the digital parts, which also takes care of actual demodulation, channel equalization, detection, and decoding. Also, extracting synchronization information on the receiver side in terms of carrier and timing recovery is a crucial element. Coarse carrier synchronization is typically implemented in the analog parts, while further fine tuning of the carrier frequency and phase as well as obtaining timing synchronization are then usually implemented in the digital domain. Stemming from the principal block diagrams shown in Fig. 15.1, several sources of analog/RF impairments can be identified. These are introduced here by going through the most typical imperfections at the component/block level, and the individual impairments are then discussed in more detail in the following subsections. 15.2.1.1 Digital-to-Analog Converters Typical imperfections are nonideal passband response (unintentional filtering), imperfect rejection of spectral images (reconstruction filtering), quantization noise, and nonlinear distortion due to unintentional deviations in the consecutive quantization levels. The differences between the I and Q branch DACs (and LPFs) also contribute to I/Q imbalance. 15.2.1.2 Samplers and Analog-to-Digital Converters Typical imperfections are nonideal passband response (unintentional filtering), aliasing, quantization noise,

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jitter noise due to instabilities of the sampling clock, nonlinear distortion due to clipping (input conditioning) and unintentional deviations in the consecutive quantization levels, and dc-offset (bias). The differences between the I and Q branch ADCs (and samplers and LPFs) also contribute to I/Q imbalance. 15.2.1.3 Mixers Common nonidealities include nonlinear distortion (e.g., outof-band harmonics, in-band intermodulation products, and spectral regrowth), finite isolation between the input, LO and output ports, and dc offsets. The relative differences between the I and Q branch mixers also contribute to I/Q imbalance. 15.2.1.4 Oscillators Typical oscillator nonidealities are phase noise due to random fluctuations of the oscillator phase, frequency and phase offsets due to differences between the LO and the incoming carrier, and interfering in-band signal components due to spectral impurity of the LO signal (e.g., LO harmonics). The relative amplitude difference and deviation from the 90◦ phase shift of I/Q LO also contribute to I/Q imbalance. 15.2.1.5 Transmitter Power Amplifiers Common imperfections are various nonlinear distortion effects, such as in-band interference, spectral regrowth, harmonic distortion, and intermodulation distortion, together with memory-related effects (filtering). 15.2.1.6 Receiver Amplification Stages (LNAs, etc.) Similar to the above, receiver (small-signal) amplification stages can be nonlinear, causing various nonlinear products such as harmonic and intermodulation distortion. 15.2.1.7 BB/IF Filters Typical imperfections are nonideal passband response (unintentional filtering) and insufficient stopband attenuation. The differences between the I and Q branch filters (amplitude and phase responses) also contribute to I/Q imbalance, which can also vary as a function of frequency within the interesting signal band. In the following, the most essential RF impairments are described in more detail, including the essential signal models and the resulting waveform degradation for each impairment type. Even though carrier synchronization issues are a very important practical aspect in any wireless system, synchronization is not addressed in the following. Instead, the most focus is on I/Q imbalance (and the resulting mirrorfrequency interference), nonlinear distortion due to mixer and amplifier nonlinearities, timing jitter in sampling and ADC circuits, and oscillator phase noise. 15.2.2

I/Q Imbalance

As discussed above, one of the key functionalities of radio transceivers is to upand down-convert the low-frequency message signals to and from radio frequencies. In this context, complex or I/Q mixing is of considerable importance (compared to more traditional real mixing) since, for example, the mirror-frequency problem is in

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theory avoided during the resulting frequency translations. This, in turn, then relaxes the RF filtering requirements and thus simplifies the transceiver implementation in that sense. As practical examples, both the direct-conversion and low-IF radio architectures, discussed in more detail later, are based on the I/Q mixing principle [4,11,16–18,20]. Any complex-valued signal processing implementation, including I/Q mixing, is physically based on processing two parallel real signals (i.e., the I and Q components). Then any relative deviation from the nominal amplitude and phase characteristics is called I/Q imbalance or I/Q mismatch, and, as shown below, results in crosstalk between the mirror frequencies of the corresponding complex signal. Such imbalances are typically encountered in analog I/Q signal processing (transceiver analog front ends), stemming from the finite tolerances and process variations of the analog electronics used. As a simple example, consider first a single-frequency signal of the form z(t) = cos(ω0 t) + j sin(ω0 t) = exp( jω0 t). Then changing the relative amplitude g and phase  of the Q branch with respect to the I branch results in z¯ (t) = cos(ω0 t) + jg sin(ω0 t + ) = K 1 exp( jω0 t) + K 2 exp(− jω0 t)

(15.1)

in which K 1 = [1 + g exp( j)]/2 and K 2 = [1 − g exp(− j)]/2. This clearly shows that the original signal energy located at ω0 is now split to ω0 and −ω0 , meaning crosstalk between the mirror-frequency components in general. Similarly for an arbitrary complex signal z(t) = z I (t) + j z Q (t), shifting the amplitude and phase contents of the Q branch with respect to the I branch results in z¯ (t) = z I (t) + j z Q (t) ∗ h(t) = g1 (t) ∗ z(t) + g2 (t) ∗ z ∗ (t)

(15.2)

where, as in the continuation, x(t) ∗ y(t) refers to the convolution of two functions x(t) and y(t). Here “filtering” the Q branch signal models the relative amplitude (response) and phase (response) imbalances within the bandwidth of z(t), being in general frequency dependent, and g1 (t) = [δ(t) + h(t)]/2 and g2 (t) = [δ(t) − h(t)]/2. Thus, the imbalanced signal z¯ (t) appears as a linear combination of the ideal (original) signal z(t) and its complex conjugate z ∗ (t), filtered with g1 (t) and g2 (t), respectively. In general, since the spectrum of z ∗ (t) is a conjugated and mirrored version of the spectrum of z(t), the model in (15.2) has mirror frequencies due to I/Q imbalance. Graphic illustrations are shown in Fig. 15.2. Notice that, in general, the relative amount of crosstalk within the bandwidth of z(t) can depend on frequency. Based on (15.2), this can be stated more formally by defining the level of mirror-frequency (crosstalk) attenuation as L( f ) =

|G 1 ( f )|2 |G 2 ( f )|2

(15.3)

in which G 1 ( f ) and G 2 ( f ) are Fourier transforms of g1 (t) and g2 (t). As a practical example, with 1% amplitude and 1◦ phase imbalances, the crosstalk attenuation above is roughly 40 dB.

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ORIGINAL

ORIGINAL

f (a)

f

(b)

IMBALANCED

ORIGINAL

IMBALANCED

f

ORIGINAL

f (c) IMBALANCED

f

f (d) IMBALANCED

f

f

FIGURE 15.2 Spectral illustrations of mirror-frequency crosstalk due to I/Q imbalance for (a) single-tone, (b) zero-IF, (c) low-IF, and (d) dual-carrier low-IF signals.

Based on the basic imbalance models above, analyzing the imbalance effects in I/Q mixing–based radio transmitters and receivers is relatively straightforward [21–29]. In general, it should be noted that the overall amplitude and phase mismatches between the transceiver I and Q signal branches stem from the relative differences between all the analog components of the I/Q front end. On the transmitter side, this includes the actual I/Q up-conversion stage as well as the I and Q branch DACs and lowpass filters. On the receiver side, on the other hand, the I/Q down-conversion as well as the I and Q branch filtering, amplification, sampling, and A/D stages contribute to the effective I/Q imbalance. Now, considering first the I/Q mixing stages alone, we write the complex local oscillator (LO) signals as TX (t) = cos(ωLO t) + jgTX sin(ωLO t + TX ) xLO

(15.4)

= cos(ωLO t) − jgRX sin(ωLO t + RX )

(15.5)

RX xLO (t)

Above wLO = 2π f LO and gTX , TX and gRX , RX represent the amplitude and phase imbalances of the transmitter (TX) and the receiver (RX) I/Q mixing stages, respectively. Then, also taking the relative branch filtering effects (due to the relative differences between the frequency responses of, e.g., DACs and BB filters in transmitters and ADCs and BB filters in receivers) into account, denoted here by the impulse responses h TX (t) and h RX (t), the overall baseband equivalent signal models for an imbalanced transmitter and receiver appear as z¯ TX (t) = g1,TX (t) ∗ z(t) + g2,TX (t) ∗ z ∗ (t)

(15.6)

z¯ RX (t) = g1,RX (t) ∗ z(t) + g2,RX (t) ∗ z ∗ (t)

(15.7)

The effective impulse responses g1,TX (t), g2,TX (t), g1,RX (t), and g2,RX (t) depend on the actual imbalance properties as g1,TX = (δ(t) + h TX (t)gTX exp( jTX )/2

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g2,TX = (δ(t) − h TX (t)gTX exp( jTX )/2, g1,RX = (δ(t) + h RX (t)gRX exp(− jRX )/2, and g2,RX = (δ(t) − h RX (t)gRX exp( jRX )/2. Notice that the typical frequencyindependent (instantaneous) I/Q imbalance models of the form z TX (t) = K 1,TX z(t) + K 2,TX z ∗ (t) and z RX (t) = K 1,RX z(t) + K 2,RX z ∗ (t) are obtained as special cases of (15.6) and (15.7) when h TX (t) = δ(t) and h RX (t) = δ(t) (i.e., when the I/Q mixer is the only source of imbalance). Based on the signal models in (15.6) and (15.7), the overall effect of I/Q imbalances on both the transmitter and receiver sides is to cause mirror-frequency crosstalk. Practical levels of mirror-frequency attenuation using state-of-the-art analog electronics are on the order of 25 to 40 dB [4,11,16,18]. In general, attenuation levels close to 40 dB are already very challenging to achieve using purely analog techniques. The more detailed effect of mirror-frequency crosstalk is in general highly dependent on (1) the modulation scheme (waveform type) used and (2) the radio architecture used. At the modeling level, these reflect different, more detailed structures for the ideal signal z(t) in (15.6) and (15.7). As an example, consider a basic single-channel direct-conversion transmitter or receiver with single-carrier modulation, in which the ideal signal z(t) corresponds to a pulse-shaped baseband waveform. Then based on (15.6) and (15.7), I/Q imbalances result in widely linear transformation of the original symbol constellation, which can be categorized as an “in-band” problem. Another way to view this is that a down-scaled mirror image of the ideal baseband spectrum is superimposed on top of itself. On the other hand, a totally different and also more challenging scenario is obtained when a low-IF transmitter is considered. Then the ideal signal is no longer a baseband signal but an analytic bandpass signal located at the IF frequency used. Then the mirror-frequency component due to I/Q imbalance falls on top of another signal band, being separated by twice the IF used when measured at RF, which is no longer simply an in-band problem. These architectural issues as well as the role of modulation are considered in more detail in Sections 15.2.6 and 15.2.7. In general, it can be concluded at this stage that I/Q imbalance effects are emphasized when high-order modulations and/or IF radio architectures are deployed. A simple illustration of the effect of I/Q imbalance on OFDM multicarrier waveforms is given in Fig. 15.3. Here three different amplitude and phase imbalance levels are demonstrated, assuming direct-conversion receiver topology, and the subcarrier data modulation is 64-QAM. Based on the figure, the performance of an OFDM direct-conversion receiver with high-order subcarrier modulation is very sensitive to I/Q imbalances, and thus some type of compensation or imbalance mitigation is needed.

15.2.3

Phase Noise

In general, oscillating (sinusoidal) signals are used in transmitters and receivers to translate the signals to and from the radio frequencies used. In practical implementations, oscillators used to create such signals are also subject to noise and other imperfections. One important imperfection is related to the random fluctuations or instability of the oscillator frequency and phase. This is typically called phase noise,

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10−1

SER

c15

10−2

10%, 10deg 5%, 5deg 2%, 2deg AWGN bound

10−3

10−4 5

10

15 20 25 Received SNR [dB]

30

35

FIGURE 15.3 Symbol error rates of a 64QAM-OFDM waveform in an AWGN channel with three different I/Q imbalance values for direct-conversion receivers.

and basically causes additional or unwanted phase “modulation” to the waveforms transmitted and received [4,7,10,11,17,30,31]. At the modeling level, given an ideal oscillator of cos(ω0 t) (real case) or exp( jω0 t) (complex or I/Q case), such random phase fluctuations appear as additional additive phase terms, written here as xLO,R (t) = cos(ω0 t + n (t))

(15.8)

xLO,IQ (t) = exp( j(ω0 t + n (t)))

(15.9)

or

where ω0 denotes the nominal oscillating (center) frequency and n (t) denotes the phase noise. Hereafter, the complex carrier case is assumed for generality. From the spectrum point of view, the ideal oscillator exp( jω0 t) has a purely impulsive spectrum, with all the power being located exactly at the oscillating frequency f 0 . Due to the phase noise, the spectral contents of the oscillator signal are then dispersed around the nominal oscillating frequency. This is easy to understand based directly on (15.8) and (15.9), which can simply be viewed as phase-modulated carriers. Another way to see this is to rewrite the complex carrier in (15.9) as exp( jω0 t) exp( jn (t)), implying that the shape of the practical oscillator spectrum around the nominal oscillating frequency is determined by the spectrum of the phase exponential exp( jn (t)). In practice, the characteristics of the phase noise n (t) depend on the type of oscillator used. Two basic alternatives are free-running oscillators and phase-locked

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loop (PLL)–based synthesizers. For simplicity, we focus here on the free-running oscillator case (the PLL case is addressed in detail, e.g., in [30,32–34]). For such freerunning oscillators, the phase noise term can be modeled as a random process called Brownian motion or the Wiener process. Statistically, such a process is Gaussian distributed with zero mean and linearly increasing variance (over time) of the form E(2n (t)) = αt. Despite this nonstationary nature of the phase term itself, the phase exponential (and thus the overall oscillator model) is stationary. Denoting the phase exponential with pn (t) = exp( jn (t)), the corresponding autocorrelation function reads E( pn (t1 ) pn∗ (t2 )) = exp(− 12 α|t1 − t2 |)

(15.10)

which implies stationarity for pn (t) = exp( j(t)). The corresponding power spectrum is then obtained directly by the Fourier transform of (15.10) and reads G pn ( f ) ∼

α (α/2)2 + (2π f )2

(15.11)

This gives the shape of the actual oscillator power spectrum around the nominal oscillating frequency f 0 . The essential spectral width, interpreted as the two-sided 3-dB bandwidth of the lowpass equivalent spectrum (positive and negative frequencies) in (15.11) is then given by B∼2

α α = 4π 2π

(15.12)

A graphical illustration, together with a simulated oscillator spectrum, is given in Fig. 15.4, in which the essential spectral width of the oscillator spectrum is 1 kHz (positive frequencies only shown here). Next, we focus on the basic impact of phase noise on the up-/down-converted signals and waveforms. Since exp( j(ω0 t + n (t))) = exp( jω0 t) pn (t) and mixers themselves act essentially as multipliers (at the signal modeling level), a baseband or low-frequency model for the phase-noise impaired waveform is of the form z¯ (t) = pn (t)z(t)

(15.13)

in which z(t) is the corresponding ideal signal (without any phase noise). In the frequency domain, this means that the spectrum of the impaired signal appears as a convolution of the ideal signal and the phase noise spectrum. In general, this results in both in-band and out-of-band interference or distortion. Some graphical illustrations are given in Fig. 15.5. In the transmitter case, (15.13) is a low-frequency model for the RF waveform generated, whereas in the receiver case, (15.13) represents the actual down-converted observation. In general, the relative amount of spectral broadening

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10 0 Relative Power Density [dB]

c15

−10 −20 −30 −40 −50 −60 −70 −80 100 101 102 103 104 105 106 Frequency Around the Nominal Oscillating Frequency [Hz]

FIGURE 15.4 Example of a free-running oscillator spectrum with a phase noise spectral width of 1 kHz (-500 to 500 Hz).

depends heavily on the dynamics of the phase noise compared to the dynamics of the waveforms used. Another way to state this is as the ratio of waveform bandwidth to oscillator spectral width. Thus, from an in-band distortion point of view alone, if the symbol duration of the waveform used is much smaller than the inverse of the phase noise spectral width, the spectral broadening is relatively small and phase noise appears simply as a phase shift changing slowly from symbol to symbol. One example waveform class for which phase noise can easily become a performancelimiting factor is then OFDM [33,35–39]. Practical subcarrier spacings are typically on the order of a few tens or few hundreds of kilohertz (depending on the multipath ORIGINAL

ORIGINAL

f (a)

(b)

IMPAIRED

ORIGINAL

f

IMPAIRED

f

ORIGINAL

f (c) IMPAIRED

f

f (d) IMPAIRED

f

f

FIGURE 15.5 Principal spectral illustrations of signal distortion due to phase noise, in cases of (a) single-tone, (b) zero-IF, (c) low-IF, and (d) dual-carrier low-IF type signals.

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100

10–1

10–2 SER

c15

10–3 AWGN Bound 200 Hz 400 Hz 1000 Hz 2000 Hz

10–4

10–5 0

5

10

15 20 25 Received SNR [dB]

30

35

FIGURE 15.6 Symbol error rates of a 16QAM-OFDM waveform in an AWGN channel with three different two-sided 3-dB spectral widths for a free-running receiver oscillator. The subcarrier spacing is 50 kHz, and altogether, 64 subcarriers are used.

spread of the radio channel), and thus oscillator spectral width in the kilohertz range can lead to considerable intercarrier interference (ICI). This, together with other modulation specific issues, is discussed in more detail in Section 15.2.6. Below, a simple performance example is shown in Fig. 15.6, which illustrates the symbol error rate of 64-subcarrier OFDM waveform under AWGN channel and receiver phase noise with different 3-dB bandwidths for the free-running oscillator model. The subcarrier spacing in the OFDM waveform itself is 50 kHz, and the subcarrier data modulation is 16-QAM. The effects of oscillator phase noise, especially its higher-frequency contents, are further emphasized when the processed signal contains adjacent channels possibly tens of decibels stronger than the weak band desired. In such cases, the spectral broadening of the neighboring channels due to phase noise can cause serious spectral leakage or interference on top of the weak signal band(s) desired. Typically, the specifications for the oscillator phase noise at higher frequencies are given through dBc/Hz spectral masks, to keep the interference at a tolerable level under assumed maximum dynamics in the overall signal processed. 15.2.4

Nonlinearities

The topic of nonlinear distortion in communications systems has been under intensive research for several decades. The basic impact of any nonlinear mapping of signal values is that new frequencies will appear, compared to the frequency content of the original signal. Typical examples are harmonic distortion, referring to the integer multiples (harmonics) of the input frequencies, and intermodulation distortion, which

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in turn refers to different linear combinations of the original frequency components. Depending on the overall waveform structure and range of frequencies considered, these can also be divided into in-band and out-of-band distortion components. Typically, in-band distortion products result in an increased effective noise floor (from any individual waveform point of view), while out-of-band components introduce crosstalk and interference between different signal bands [40–50]. On the transmitter side, the key source of nonlinear distortion is the power amplifier (PA). To increase the TX power efficiency, practical PAs need to operate in a heavily nonlinear region in their input power vs. output power transfer characteristics. In the PA context, the out-of-band components close to the original spectrum are typically called spectral regrowth, while the more far away components fartheraway stem from, for example, center frequency harmonics. Depending on the type of amplifier and waveforms used, the nonlinear distortion can in general be described as instantaneous (memoryless) or to contain memory. Considering the instantaneous case first, the most typical way to model the distortion is given by the AM/AM-AM/PM characteristics. In effect, the envelope A(t) and the phase (t) of the input signal are shaped according to A(t) → g A (A(t)) and (t) → (t) + g (A(t)), respectively, in which g A (·) and g (·) are memoryless nonlinear functions. Some typical examples are a clipping-type limiting amplifier, a solid-state amplifier (SSA), and a traveling-wave tube amplifier (TWTA) [43,45,51–53] For a pure clipping amplifier,
g A (A) =

A ≤ A0 A > A0

A, A0 ,

g (A) = 0

(15.14) (15.15)

in which A0 denotes the clipping level. The SSA model, in turn, is given by 



g A (A) = A 1 +

A A0

2n −1/2n

g (A) = 0

(15.16) (15.17)

in which A0 represents again the limiting (saturation) value and the parameter n affects the relative order of the nonlinearity for 0 ≤ A(t) ≤ A0 . The TWTA or Saleh model is of the form g A (A) =

a1 A 1 + a2 A 2

(15.18)

g (A) =

b1 A2 1 + b2 A2

(15.19)

in which the parameters a1 , a2 , b1 , and b2 define the exact behavior of the AM/AM and AM/PM transfer characteristics. One additional, widely applied model

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INSTANTANEOUS NONLINEARITY

465

LINEAR FILTER

(b)

(a)

LINEAR FILTER

INSTANTANEOUS NONLINEARITY

LINEAR FILTER

(c)

FIGURE 15.7 Principal types of nonlinear distortion models with memory: (a) Wiener model; (b) Hammerstein model; (c) Wiener–Hammerstein model.

for instantaneous nonlinear distortion is given by polynomial mapping between the input and output. Using the notation x(t) = A(t) exp( j(t)), one typically deployed N −1 an+1 |x(t)|n . If the model polynomial model can be formulated as y(t) = x(t) n=0 coefficients are limited to being real-valued, only AM/AM distortion will take place, described by g A (A(t)) =

N −1 

an+1 A(t)n+1

(15.20)

n=0

where A(t) = |x(t)|. The models above are based primarily on memoryless distortion assumption. In practice, many amplifiers also exhibit some memory in their nonlinear distortion characteristics [43,45,51,52,54–60]. At the modeling level, this can be incorporated by introducing linear filtering effects combined with previous instantaneous nonlinear mappings. Depending on the relative ordering of linear filtering stage(s) and instantaneous nonlinearity, the Wiener, Hammerstein, and Wiener–Hammerstein models are obtained. These are illustrated in Fig. 15.7, in which the instantaneous nonlinearity is typically one of the AM/AM–AM/PM models cited above. Based on the previous models, the key waveform feature from the PA distortion point of view is envelope dynamics. This is because in the limiting case of constant envelope signals (e.g., the frequency modulation case), the previous AM/AM–AM/PM reduce to constant amplitude scaling and phase change. Thus, the higher the envelope dynamics, the more critical the PA nonlinearities are in general. This is usually measured using the peak-to-average-power ratio (PAPR), which is smallest for constant envelope signals and increases with increasing envelope dynamics. Multicarrier-type waveforms such as OFDM form an important example of signals that typically have relatively high PAPR values (see, e.g., [61]). This is easy to understand since a multicarrier waveform is, by definition, composed of a set of subcarriers (superposition), which depending on the modulating subcarrier data symbols, can add constructively (coherently) or destructively (incoherently). As a general rule of thumb, PAPR values

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IDEAL

IDEAL

f

f IMPAIRED

IMPAIRED

(a)

(b)

f

f

FIGURE 15.8 Examples of (a) second-order intermodulation of two out-of-band signals, and (b) self-mixing interference due to finite RF-LO isolation.

on the order of 10 dB are fairly common for multicarrier signals, being composed of hundreds of subcarriers. Another important waveform class that can easily have considerable PAPR values is single-carrier modulation with high-order QAM alphabet (e.g., 64QAM) and tightly bandlimited pulse shaping (e.g., raised-cosine or rootraised-cosine with small roll-off). Varying symbol amplitudes and the low roll-off pulse shape both contribute to PAPR in this case. On the receiver side, the main sources of nonlinearity are front-end small-signal components such as LNA and mixers, together with ADCs. These are most problematic in cases where only minor selectivity is implemented at analog RF, allowing a wideband high dynamic range signal to enter the down-conversion stage. In such cases, depending on the receiver architecture, the second- and third-order intermodulation of strong blocking-type signals can easily mask the weaker signal bands desired [4,11,16,18,62,63]. One additional source of second-order nonlinear distortion is the finite isolation between the mixer RF and LO ports, resulting in self-mixing of the LO signal and, especially, the RF input. The self-mixing products of strong RF interferers falling around zero frequency can again easily mask the weak signal desired, especially in the zero-IF receiver case [18,62–68]. Principal graphical illustrations of both intermodulation and self-mixing are shown in Fig. 15.8. At the modeling level, such small-signal distortion products can be described using polynomial transformations of the ideal down-converted I and Q signals or, more generally, with Volterra series polynomials with memory. 15.2.5

Sampling Jitter

The term jitter refers here to the random fluctuations of the sampling instants with respect to the corresponding nominal (ideal) sampling instants. Such jitter is caused, for example, by any instabilities or phase noise in the sampling clock used and, of course, the sampling and analog-to-digital conversion circuits [69–73]. The basic

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observation is that the error in the sample values due to errors in the sampling instants is directly proportional to the derivative of the signal to be sampled, evaluated at the ideal sample moments. This is easy to understand and can be considered as a direct application of a first-order approximation of Taylor series expansion: x(kTS + t) ≈ x(kTS ) + t

 ∂ x(t)  ∂t t=kTS

(15.21)

where kTS denotes the ideal sample instant and t is the corresponding sampling time deviation. In sampling bandpass signals, these errors in the sample values due to jitter are then directly proportional to both the frequency range and amplitude (power) of the sampler input signal. This is evident based on (15.21) and can be demonstrated by considering a single sinusoidal of the form x(t) = A0 sin 2π f 0 t, yielding ∂ x(t)/∂t = 2π f 0 A0 cos 2π f 0 t. The nominal power of the error signal is thus (2π f 0 A0 t J )2 /2, where t J denotes the rms jitter value. For a more general bandpass input signal, with power Pin and maximum frequency f max , the corresponding jitter power is then of the form Pin (2π f max t J )2 . Given that the resulting jitter noise can be approximated as white noise (meaning essentially that consecutive jitter values are uncorrelated), the corresponding power spectral density within the sampled signal frequency range −FS /2 · · · FS /2 is then given by GJ( f ) =

Pin (2π f max t J )2 . FS

(15.22)

Based on (15.22), sampling jitter is most problematic in direct RF or IF sampling contexts in which the signal center frequencies can be in the hundreds of megahertz or even the gigahertz range. This typically leads to rms jitter requirements on the order of a few picoseconds, especially if the dynamic range of the sampler input signal is high [6]. From a jitter point of view, having an input signal with strong out-of-band energy is by far the most problematic case, in which the jitter noise of the strong signal or signals can easily block the weaker signal bands entirely. Notice that based on (15.22), increasing the sampling frequency helps to decrease the jitter requirements, since the jitter noise is distributed over a wider frequency range [6,70,71]. 15.2.6

Role of Modulation

Since most or all of the RF impairments described above can be viewed as causing different types of in-band interference, it is safe to say that higher-order modulated signals are in general more sensitive to these effects. Within single-carrier modulation methods, techniques including both amplitude and phase modulation elements (e.g., QAM) are also somewhat more sensitive than pure phase or frequency modulations (PSK, FSK). This is partially because amplitude modulation implies higher instantaneous dynamics for the RF waveforms, thus increasing, for example, the effects of nonlinear power amplifiers and also receiver nonlinearities.

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Multi-carrier modulations such as OFDM and its different variants, are also found to be fairly sensitive to RF impairments. High PAPR values imply increased sensitivity to nonlinear elements, and the subcarrier structure combined with phase noise and/or I/Q imbalances results in intercarrier interference (ICI) distortion. In case of phase noise, such ICI is produced primarily between neighboring subcarriers, while the mirror-frequency interference due to I/Q imbalances results in ICI between symmetrically located mirror-carrier pairs. In addition to ICI, phase noise also causes a common phase error (CPE) in all the subcarrier signals [22,27,33,35–39,74,75]. One essential element in many emerging wireless system developments is the introduction of multiple transmitter and/or receiver antennas. This leads to multipleinput, multiple-output (MIMO) transmission schemes, in which either the link/system spectral efficiency or an individual link quality can be improved compared to more traditional single-antenna systems. Such multi-antenna waveforms basically call for multiple parallel radio implementations, each having its own RF impairment sources. Then preliminary studies in the literature indicate that the sensitivity to RF impairments is also increased, resulting, for example, in inter-stream interference in the spatial multiplexing MIMO case [76,77]. This has been studied recently from the I/Q imbalance, nonlinear distortion, and phase noise points of view [9,10,23,29,78–88]. 15.2.7

Role of Radio Architecture

The impact of different RF impairments is also very heavily dependent on the radio architecture used. Currently, most radio devices build on the direct-conversion radio architecture or a variant such as the low-IF principle. This applies to both the transmitter and receiver implementations. The receiver side is, however, conceptually more challenging since the received signals desired are typically very weak and need to be processed and detected in the presence of (possibly much) stronger adjacent channels as well as other out-of-band signals. Thus, overall, the location and division of receiver selectivity filtering are some of the key factors determining the sensitivity to many of the RF impairments noted above. The basic and fairly manageable case corresponds to an ordinary single-channel direct-conversion transceiver, in which direct I/Q up- and down-conversion of the communication waveform from baseband to RF frequencies, and vice versa, are used. In such radios, the sensitivity to I/Q imbalances and phase noise is determined primarily by the used waveform itself (type of modulation), as discussed earlier. Spectral regrowth due to transmitter power amplifier nonlinearities can, in turn, cause adjacent channel interference, whose relative impact (when viewed from the receiver point of view) also depends on the power control strategy used. Receiver nonlinearities, in terms of second- and possibly also third-order intermodulation products, can also be problematic if only moderate selectivity is implemented in the receiver analog stages. Also, all the self-mixing products due to RF-LO leakage fall directly on top of the signal desired. Limited RF selectivity in the receiver can also cause phase noise–induced spectral leakage originating from strong out-of-band signals to hit the target band.

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One interesting variant of the basic direct-conversion radio is the low-IF principle in which a low (and typically, digital) IF is used in translating the signal from baseband to RF and back. From the mirror-frequency interference point of view, this now means that the mirror frequencies of any specific signal frequencies are located at another signal band, being in general separated by twice the IF. Then, if the IF used is, for example, half the waveform bandwidth used, I/Q imbalances result in crosstalk between the neighboring signal bands, which applies to both the TX and RX sides of the link. Given that the power levels of the neighboring signals can differ, mirror-frequency interference is then relatively a greater problem than in the pure direct-conversion case. Use of low IF (compared to zero IF) has, however, many other benefits, such as reduced sensitivity to second-order nonlinear distortion, since the signal desired is no longer located exactly at baseband. In general, the most challenging architectural case is the wideband multicarrier or multichannel transceiver scenario, in which a wide collection of different carriers or frequency bands is I/Q up- and down-converted as a whole. On the transmitter side, a clear example application is a base-station transmitter in which all the bands or carriers are carrying specific communications waveforms. On the receiver side, on the other hand, the spectral contents of the individual bands can also be either unwanted signals originating from the same communication system (mobile station receivers) or even arbitrary blocking waveforms outside the entire system bandwidth (flexible receiver implementation with a minimum amount of RF/analog selectivity). In general, if only very preliminary analog selectivity filtering is implemented, followed by a wideband digitization stage, increased flexibility and reconfigurability are obtained since the final selectivity and all or most modulation-specific processing are then implemented using DSP. This implies directly, however, that the signals in different stages of the analog front end are wideband multi-carrier signals in which the dynamic range can easily be several tens of decibels. This in turn then also implies extremely high sensitivity to the previous RF impairments, since the interfering distortion components due to the strong signals can easily dominate the weaker carriers desired.

15.3

IMPAIRMENT MITIGATION PRINCIPLES

In general, there are many different approaches in trying to control the levels and impact of RF imperfections. Conceptually, the most straightforward approach is to try to optimize the quality and functionalities of the analog front-end components and modules such that the overall RF impairment impacts are still at an acceptable level with the waveforms used and radio architecture given. This can, however, easily lead to very expensive overall radio implementation and can limit transceiver flexibility, since typically a dedicated hardware-optimized, e.g., for a certain frequency band, must be used. An alternative and very interesting approach is then simply to accept the limitations of the front end and its analog modules and try to enhance the signal quality through proper digital signal processing. In practice, such signal enhancement can be done either purely in the digital domain or by combining analog and digital techniques with some type of information exchange between the two domains. Digital

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techniques, when implemented properly, have the advantage of being tunable and adaptable, and thus able to follow, for example, possible time-variant features or center-frequency-dependent characteristics of the RF/analog imperfections. Here we focus primarily on purely digital techniques. At a conceptual level it is possible to mitigate the TX- and RX-induced effects either (1) separately in transmitters and receivers or (2) jointly in either transmitter or receiver. Separate mitigation at the “source” is in practice easier, since joint compensation calls for either feedback from receiver back to transmitter (joint compensation at TX) or estimation of both TX- and RX-induced effects in the receiver (joint compensation at RX), which in turn can be rather complicated, due to wireless channel. Also, in a multi-user system with many transmitters and receivers, mitigating individual TX effects at the corresponding transmitters reduces the effective dimensionality of the problem in the sense that interuser interference is reduced. On the other hand, in cellular systems, base stations have much more computational resources, and mitigating all the impairments in a base station (uplink RX, downlink TX) could be an interesting alternative as well. Considering the TX-based mitigation of transmitter imperfections, this basically means proper predistortion of transmitter digital signals such that when going through the analog sections, the overall RF waveform is essentially free of any imperfections. In most cases, the structure of the predistortion processing required depends on the impairment considered and typically relies on proper impairment behavioral modeling. Once the structure is fixed, finding proper predistortion parameters is then based on either (1) off-line calibration measurements of some kind or (2) online feedback information from the RF back to the lower frequencies (inside the transmitter). On the receiver side, on the other hand, RX signal enhancement is based on postprocessing or compensation trying to reduce the RX impairment effects to tolerable levels in the signals observed. Again, different impairments call for different postprocessing structures, relying on sufficient imbalance modeling. Then obtaining proper postprocessing coefficients for the structure selected can be based on (1) off-line impairment measurements and characterization, (2) processing of specific pilot or training data, which are already implemented in most communications systems for synchronization and channel estimation purposes, for examples, or (3) other communications waveform features, such as certain statistical properties, which depend on the considered impairments in a known way. What makes the receiver processing relatively more complicated than transmitter processing is the fact that frequency and timing synchronization need to recovered (whether or not there were any impairment effects) and also that the waveforms transmitted are in any case distorted by the wireless channel (noise, multipath, etc.). 15.3.1

I/Q Imbalance Compensation Principles

Most of the work reported in the literature focuses on compensation of frequencyindependent I/Q imbalances (see, e.g., [7,10,23,74,75,89–96] and the references therein). This being the case, the imbalanced signal can be written as (see also Section 15.2.2 for explicit definition of the complex coefficients K 1 and K 2 as

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functions of the imbalance values) z¯ (t) = K 1 z(t) + K 2 z ∗ (t)

(15.23)

z¯ I (t) = z I (t) z¯ Q (t) = g cos()z Q (t) − g sin()z I (t)

(15.24)

or

where g and  model the amplitude and phase imbalances, here referred to the Q branch. The corresponding frequency-dependent case is written as [again see Section 15.2.2 for explicit definition of the impulse responses g1 (t) and g2 (t) as functions of imbalance characteristics] z¯ (t) = g1 (t) ∗ z(t) + g2 (t) ∗ z ∗ (t)

(15.25)

or z¯ I (t) = z I (t)

(15.26)

z¯ Q (t) = g cos()h(t) ∗ z Q (t) − g sin()h(t) ∗ z I (t)

(15.27)

Thus, in general, an I/Q imbalance effect can be viewed either as additive conjugate interference or as mutual intermixing (and filtering) of the I and Q components. The conjugate interference model maps into mirror-frequency interference, while the I/Q model can be interpreted as creating mutual correlation between the I and Q signals observed [22–28]. In plain direct-conversion transceivers, the imbalance models above lead to signal distortion, which depends somewhat on the type of modulation. For linearly modulated signals, (15.23) or (15.24) corresponds to a certain “twist” in the symbol constellation, whereas for OFDM signals, the data at any specific subcarrier are interfered with by the conjugate of the data at the corresponding mirror carrier. This is especially troublesome on the receiver side in cases in which the wireless channel shapes (attenuates) a carrier and the corresponding mirror carrier in different ways. In low-IF transceivers, in turn, I/Q imbalances result in crosstalk or interference between the signal bands around the LO frequency. This is generally more challenging than in pure direct conversion, since these signals can originate from physically different sources and thus have considerably different power levels in the composite signal received. Given the knowledge of the imbalance values, the most obvious compensation structure is based on conceptually similar signal processing, as in (15.23) or (15.25). In the general frequency-dependent case, this is written here as y(t) = z¯ (t) + w(t) ∗ z¯ ∗ (t) = [g1 (t) + w(t) ∗ g2∗ (t)] ∗ z(t) + [g2 (t) + w(t) ∗ g1∗ (t)] ∗ z ∗ (t)

(15.28)

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where w(t) denotes the compensation filter impulse response. Thus, to remove all the mirror-frequency interference, w(t) should be selected such that g2 (t) + w(t) ∗ g1∗ (t) = 0 ∀t. In terms of Fourier transforms, this yields the optimum compensation filter of the form Wopt ( f ) = −

G2( f ) G ∗1 (− f )

(15.29)

In the special case of frequency-independent I/Q imbalances, the optimum filter above is a one-tap filter with the tap-value wopt = −K 2 /K 1∗ . Applying the foregoing imbal∗ , ance models to OFDM, the basic signal model is of the form Z¯ k = G 1,k Z k + G 2,k Z −k where Z k and Z −k denote the frequency-domain signal samples at subcarriers k and −k under perfect I/Q balance. Then the compensator combines the observations at mirror subcarriers k and −k, with proper complex weight Wk , to form an output signal of the form ∗ Yk = Z¯ k + Wk Z¯ −k ∗ = (G 1,k + Wk G ∗2,−k )Z k + (G 2,k + Wk G ∗1,−k )Z −k

(15.30)

It follows directly that the optimum compensator coefficient for subcarrier k is Wopt,k = −

G 2,k . G ∗1,−k

(15.31)

Again, if the imbalances are frequency independent, each mirror–carrier pair can be processed with the same compensator coefficient, Wopt,k = wopt = −K 2 /K 1∗ . Most practical compensation developments in the literature focus on pilot carrier– based estimation of the optimum compensator in (15.31) in the OFDM context, combined with the simplifying assumption of frequency-independent I/Q imbalances for which ∀k:Wopt,k = −K 2 /K 1∗ . One possible approach to carrying out the estimation ∗ as an extended linear is to view the basic signal model Z¯ k = G 1,k Z k + G 2,k Z −k



T ∗ T k model of the form Z¯ k = Gk Z , where Gk = G 1,k G 2,k and ZTk = Z k Z −k . When combined with channel knowledge and pilot data, identification of the imbalance parameters can be done using, for example, least-squares model fitting. Such work has been reported, in [97] for estimation of RX-induced imbalances alone and in [98] for joint estimation of both TX- and RX-induced imbalances, all assuming frequency-independent imbalances. In [109], similar techniques are also proposed for joint estimation of frequency-dependent imbalances originating from both TX and RX stages. In [24], the imbalances are also estimated in the frequency domain using pilot subcarriers, but the actual compensation is based on time-domain processing. Extensions to multi-antenna MIMO–OFDM systems are then considered in [22,23, 99], which focus on the spatial multiplexing case, as well as in [85], considering the space-time–coded (STC) multi-antenna OFDM case.

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Another general common approach, instead of estimating the imbalance values explicitly, is to interpret the compensation principle in (15.30) as an adaptive filter whose coefficients are adapted directly to estimating the target signal. When combined ∗ , with channel equalization, this can be formulated overall as Yk = W1,k Z¯ k + W2,k Z¯ −k and the filter coefficients W1,k and W2,k are then adapted using, for example, the well-known LMS or RLS algorithms utilizing pilot data. Such approaches have been proposed, for example, in [97,100]. Compared to previous pilot data–based techniques, a completely different approach to imbalance estimation and compensation is to use the statistical properties of the communications waveforms used to devise non-data-aided or blind imbalance compensators, where no explicit knowledge of the transmit waveform samples is needed. This has been a topic under active research during the past 5 to 10 years, and two different general themes have been established: one based on the statistics of the I and Q signals and another based on the statistics of the corresponding complex signals. These are addressed briefly below, and the recircularization techniques are then considered in more detail in the 3GPP-LTE context in Section 15.4. Techniques utilizing I/Q statistics build on the general observation that I/Q imbalances create a correlation (statistical dependence, more generally) between the I and Q signals observed. Different second-order statistics–based techniques to remove this correlation are proposed in [101] and [102], shown also to be robust against, for example, CFO. Higher-order statistics–based techniques in terms of blind I/Q signal separation (BSS) are in turn proposed in [103], which also takes carrier frequency offset (CFO) and channel equalization issues into account. At a complex signal level, various statistical techniques have been proposed for both low-IF and direct-conversion radio architectures. In the low-IF case, one wellestablished approach is to down-convert the signals from both positive and negative IFs to baseband in the receiver digital front end. As shown originally in [25], assuming the frequency-independent case for simplicity, the resulting complex baseband observations z¯ + (t) and z¯ − (t) are of the form z¯ + (t) = K 1 s(t) + K 2 i ∗ (t) z¯ − (t) =

K 2∗ s(t)

+

K 1∗ i ∗ (t)

(15.32) (15.33)

where s(t) and i(t) denote the baseband equivalents of the target carrier and its image band. Then signal estimation type of blind imbalance compensation schemes stemming from adaptive interference cancellation (AIC) or blind signal separation (BSS) principles are proposed [25,26,104] for both frequency-independent and frequencydependent imbalance scenarios. An alternative approach is described in [91], in which the cross-correlation of z¯ + (t) and z¯ − (t) together with the power of z¯ + (t) + z¯ − (t), are used in estimating the optimum coefficient wopt = −K 2 /K 1∗ . Similar techniques are also proposed in the OFDM direct-conversion receiver context in [27,105], ∗ and where cross-correlation of the mirror-carrier observations Z¯ k = K 1 Z k + K 2 Z −k ∗ ∗ ∗ ∗ ∗ Z¯ −k = K 2 Z k + K 1 Z −k , combined with the power of Z¯ K + Z¯ −k , are utilized to estimate wopt = −K 2 /K 1∗ .

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The techniques above utilizing cross-correlations of the mirror-frequency components can, in general, be seen as special cases of the circular or proper nature of complex communications waveforms (see, e.g., [28,106–110] and the references therein), then being degraded by I/Q imbalances. This approach is taken in [21,111] assuming frequency-independent I/Q imbalances and then generalized to cover the frequency-dependent I/Q imbalance cases and both direct-conversion and low-IF radio architectures in [28,106]. In general, a circular or proper complex random signal is defined as a signal whose complementary autocorrelation cz (τ ) equals zero at all time lags: that is,

(15.34) ∀τ : cz (τ )
E [z(t)z(t − τ )] = E z(t)(z ∗ (t − τ ))∗ = 0 It is well established in the literature that this feature holds for most complex communications waveforms, but only under perfect I/Q balance. Based on the expression on the right-hand side of (15.34), circularity can also be interpreted as being uncorrelated against its own complex conjugate, which obviously (at least at zero lag) can hold only for complex-valued quantities in general. Now, based on (15.25), the ordinary and complementary correlation functions r z¯ (τ ) and cz¯ (τ ) for the imbalanced signal z¯ (t) read r z¯ (τ )
E [¯z (t)¯z ∗ (t − τ )] = g1 (τ ) ∗ g1∗ (−τ ) ∗ r z (τ ) + g2 (τ ) ∗ g2∗ (−τ ) ∗ r z (−τ ) cz¯ (τ )
E [¯z (t)¯z (t − τ )] = g1 (τ ) ∗ g2 (−τ ) ∗ r z (τ ) + g1 (−τ ) ∗ g2 (τ ) ∗ r z (−τ ) (15.35) and thus since cz¯ (τ ) = 0, at least for some lags around and including zero, the imbalanced signal is in general noncircular. To give a concrete example, consider the frequency-independent imbalance case for which cz¯ (0) = 2K 1 K 2 σz2 = 0, where σz2 denotes the power of z(t). Now, as shown in more detail in [28,106], the compensator output signal y(t) = z¯ (t) + w(t) ∗ z¯ ∗ (t) in (15.28) can only fulfill the circularity ∗ ( f ). condition c y (τ ) = 0 if W ( f ) = Wopt ( f ) = −G 2 ( f )/G ∗1 (− f ) or W ( f ) = 1/Wopt Thus compensation can be based on “projecting” the signal received back to the circular domain. Different adaptive filtering as well as block processing– based solutions to do this in practice are described in [21,28,106,111]. More detailed practical examples are given in Section 15.4. 15.3.2

Phase Noise Mitigation Approaches

As described in Section 15.2.3, phase noise appears basically to be a multiplying type of distortion of the form z¯ (t) = exp( jn (t))z(t), in which the statistics of the phase noise exponential depend essentially on the spectral width of the oscillator. Such multiplicative noise has the effect of widening each of the signal frequencies according to the spectral width of the phase noise exponential. For linearly modulated signals, with bandwidth typically much greater than the oscillator spectral width, this essentially maps into slowly time-varying phase rotations. In case of OFDM waveforms, however, the basic subcarrier width is typically in the kilohertz or tens

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of kilohertz range, and thus the phase noise process can easily have considerable time-variations within a single multi-carrier symbol. Overall, when interpreted for OFDM waveforms, the phase noise model z¯ (t) = exp( jn (t))z(t) = pn (t)z(t) above maps into (1) common phase error (CPE), which is a phase rotation common to all the subcarriers within one OFDM, symbol, and (2) intercarrier interference (ICI), written here as Z¯ k (n) = P0 (n)Z k (n) +

K −1 

Z l (n)Pk−l (n)

(15.36)

l=0 l =k

where n refers to OFDM symbol interval, k denotes the subcarrier index, Z k (n) is the ideal signal with zero phase noise, and Pk (n) denotes the DFT of the sampled phase noise exponential within the corresponding OFDM symbol interval. In (15.36), the complex scaling factor P0 (n) common to all the subcarriers (for a given n) is the CPE and the second additive term represents the ICI. Notice that the CPE can also be interpreted as the time average (dc-bin) of the sampled phase noise exponential within any specific OFDM symbol. In general, for reasonable phase noise spectral widths relative to the subcarrier spacing used, the complex scaling factor P0 (n) has essentially unit amplitude and thus corresponds to phase rotation only (this is, of course, where the CPE terminology originally stems from). Compensation of CPE is relatively straightforward in cases where some of the subcarriers of the multi-carrier system are reserved for pilots (used for channel estimation, etc.). Thus using the pilot data at the pilot carriers as the reference, the phase rotation (or complex scaling in general) can be estimated directly if the channel response is known in advance. Within one OFDM symbol, different CPE estimates can also be averaged across the pilot carriers. This estimate is then used for derotating the CPE for the actual data subcarriers. Basically, individual estimates are then needed for each OFDM symbol if the dynamics of the phase noise process is not extremely slow compared to OFDM symbol duration. A more practical case is obtained when the estimation above is combined with channel estimation. Given that the cyclic prefix is longer than the channel delay spread, the channel response is also seen as complex multipliers on different subcarrier signals. Thus denoting the channel frequency response values by Hk (n), the pilot data at the pilot carriers is used to estimate the combined effect of CPE and channel [i.e., P0 (n)Hk (n)]. Since the channel response part is subcarrier specific, this should then be interpolated to finally get estimates of P0 (n)Hk (n) for the active data subcarriers. These estimates are then used, for example, in designing subcarrier-wise equalizers. Mitigation of the ICI term due to phase noise is in general much more complicated than CPE. This is because the ICI term depends on all the subcarrier signals as well as on the unknown ICI profile Pk (n) (DFT of the sampled phase noise exponential) and further because the exact ICI profile Pk (n) changes from one OFDM symbol to another. One relatively simple approach proposed for ICI mitigation is to consider only the average ICI power at each subcarrier, which is then taken into account in the subcarrier-wise equalizer design as increased overall noise power. Such ideas are

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described in [112]. More efficient mitigation of the ICI can be obtained given that the ICI profile P0 (k) is known (or estimated). In principle, the ICI profile can be estimated if both the channel response and the subcarrier data symbols are known. This being the case, (15.36) can simply be rewritten as a single linear model of the form z¯ (n) = H(n)p(n), in which the unknown parameter vector p(n) contains the values of Pk (n), z¯ (n) contains the subcarrier samples observed, and the elements of H(n) are symbols transmitted multiplied by the channel response values. Then, assuming that a channel estimator (of some kind) is yielding the channel response values (including the CPE), initial decisions on the symbols transmitted are first made disregarding ICI. These symbol decisions, together with the channel estimates, are then used to construct H(n), and the linear model is solved for p(n). This estimated ICI profile is then used to de-convolve (remove) the ICI, after which new decisions are made, which are now on average more reliable than the initial decisions, since at least part of the ICI has been subtracted successfully. This is then repeated until no further performance improvements are obtained. Such techniques are developed in [33,113]. Extensions to multi-antenna OFDM are then considered in [38,114]. Building on the iterative procedure above, further performance enhancement techniques where phase noise estimates at several neighboring symbol intervals are utilized jointly in an iterative manner (using interpolation) for ICI cancellation, are proposed in [34]. 15.3.3

Power Amplifier Distortion Compensation

Mitigation of power amplifier nonlinear distortion is clearly the most studied and explored RF impairment overall, having been under active research for several decades. At a general level, the PA distortion compensation techniques can be broadly divided into transmitter linearization and receiver postprocessing-based techniques. Below, only the very basic concepts are described; for more details the reader should refer to the extensive literature of the field, including [10,40,43,45,52,115–121] and the references therein. Transmitter linearization is typically based on either predistortion approaches or feedforward techniques. In predistortion, the idea is to apply proper inverse nonlinearity, before the nonlinear PA, to effectively linearize the entire transmitter chain as a whole. In principle, such predistortion processing can be applied at baseband, IF, or RF. In case of digital predistortion, baseband (or IF) techniques are most feasible, while RF predistorters are typically analog. Due to flexibility and adaptability, digital baseband predistorters are currently receiving most interest. In feedforward linearization, on the other hand, the idea, in short, is to reproduce interfering nonlinear distortion products (IMDs) and subtract them from the PA output, to obtain linear amplification as a whole. Thus, conceptually, feedforward linearizers belong to analog RF techniques. Both predistortion and feedforward IMD cancellation–based PA linearization schemes are illustrated in Fig. 15.9. In both predistortion as well as feedforward linearization approaches, proper modeling of the amplifier at hand is of course essential. After selecting the model type (memoryless or to contain memory, etc.), efficient model parameter identification is needed. This is commonly done using feedback from RF (PA output) either

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PA

INVERSE MODEL (a) MAIN PA

ERROR AMP.

(b)

FIGURE 15.9 cancellation.

Conceptual PA linearization using (a) predistortion (b) and feedforward IMD

back to digital parts through an internal down-conversion stage (digital predistortion techniques) or to the analog RF stages preceding the PA (feedforward linearizers). Depending, for example, on the amount of memory and on the type of PA model, the computational complexity of the model identification stage can vary considerably. Also notice that other practical imperfections of the feedback path can easily limit the estimation accuracy, especially in baseband digital techniques where the feedback chain includes a down-conversion stage. In addition to transmitter-based mitigation techniques, another recently established alternative to tackling the PA distortion is to carry out some of the mitigation processing on the receiver side. Conceptually, this can be seen as an interesting alternative, especially on the uplink of mobile cellular systems, where base-station receivers clearly have greater computational resources than those of mobile transmitters. On the other hand, the nature of the wireless channel (noise, multipath, etc.) makes receiver-based processing generally more complicated than transmitter based approaches. Also, if considerable spectral regrowth is allowed on the transmitter side, the overall complexity or dimensionality of the problem is increased, since adjacent frequency bands start interfering with each other. Some iterative estimation and detection techniques for mitigating the “in-band” part of the PA distortion have been proposed [10,78,79,122] in a multi-antenna OFDM context. In short, the idea is first to detect the data as if there were no nonlinear distortion at all (using any ordinary MIMO-OFDM detector). Then the decisions are used to regenerate the ideal distortion-free transmitter waveform, which together with a model of the transmitter power amplifier can be used to estimate the resulting in-band distortion due to the PA. This distortion estimate is then subtracted from the actual signal observed, and the signal is detected again. This procedure is iterated overall until no further performance improvement in signal quality is obtained. Practical receiver-based schemes for channel estimation and PA model estimation have also been proposed [10,78,122]. Another closelyrelated topic is peak-to-average power ratio (PAPR) reduction and mitigation, especially in OFDM and other multi-carrier systems. In short, the idea is

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to prevent the transmitter power amplifier from being nonlinear (or too nonlinear) by limiting the PAPR of the transmitter waveform by some type of signal processing. Various methods proposed in the literature for PAPR reduction in OFDM and MIMO– OFDM systems include ordinary waveform clipping, tone injection, tone reservation, partial transmit sequence techniques, spatial shifting principles, and different coding methods (see, e.g., [80–82,123–132]). Notice that most of the schemes proposed either require some type of signal enhancement processing in the receiver (clipping, etc.) or reduce the overall spectral efficiency of the system (tone reservation, etc.). Some techniques have also been developed in the literature for PAPR reduction in single-carrier systems, stemming either from a pulse-shaping filter or from symbol constellation optimization. 15.3.4

Compensation for Receiver Nonlinearities

The harmonic and intermodulation distortion products of strong incoming carriers due to mixer and amplifier nonlinearities can, in general, limit the sensitivity and dynamic range of radio receivers. This is especially important in many flexible radio receiver developments, where only very preliminary selectivity is implemented at RF, and strong out-of-band energy is allowed to enter the mixing stage. Thus even if ultimately rejected by the final selectivity filtering, these strong signal components can cause serious distortion or interference on top of the weaker signal bands if not taken into account properly. Instead of trying to improve the linearity and overall quality of the mixers and other front-end components, such nonlinear distortion can also be reduced using digital postprocessing. Such an approach is taken in [64–66] in the context of second-order distortion removal due to finite RF-LO isolation, and in [63,133] in a more general nonlinear distortion removal context. The basic idea is to reproduce the interfering signal energy (at the band of interest) and then subtract that with proper amplitude and phase from the main signal observation to reduce interference. This is illustrated at a principal level in Fig. 15.10. In short, the idea is to separate the target band and the main sources of interference using ordinary linear filtering (band-split filtering). After this, the interfering signal components at the band of interest are reproduced using a reference nonlinearity, and together with the target band observation, are then fed into an adaptive interference canceler (AIC). This adaptive interference cancellation stage properly weights before cancellation the distortion components NONLINEAR COMPONENT I or Q

HD BAND-SPLIT FILTERING

ADAPTIVE IC ALGORITHM

DELAY

HR

OUTPUT

(HD ) REFERENCE NONLINEARITY

BAND LIMITATION

FIGURE 15.10 Principal block diagram to reduce nonlinear distortion and interference at the band of interest, stemming from the intermodulation of strong out-of-band blocking signals.

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reproduced. In practice, proper weighting coefficients can be found by minimizing, for example, the power of the overall output signal. One practical benefit here is that the reference nonlinearity only needs to reproduce proper spectral components (frequencies), which in turn depend only on the order of nonlinear distortion selected being canceled. Thus, a detailed model of the front-end nonlinearity is not needed. Notice that the structure in Fig. 15.10 obviously neglects the cross-products of the target signal and the blocking signals. However, the relative strength of such crossproducts depends on the powers of both the target and blocking signals, and thus in cases in which the target signal is much weaker than the blocker signal, this is indeed a reasonable assumption. These, together with lots of other practical issues, are considered in detail in [63]. 15.3.5

Jitter Mitigation

In principle, jitter mitigation is nothing but an ordinary interpolation problem, given that the deviations from the nominal sampling time grid on the time axis were known. This basically means interpolating a (typically) uniformly spaced sample sequence using the nonuniformly-spaced sample stream coming from the sampling circuit, and thus, for example, polynomial-based interpolation methods would suit to this task nicely. The practical problem, of course, is that jitter is a random phenomenon with the time deviations being unobservable (unknown) and changing from one sample to another. Some approaches to extracting the jittered time instants have been reported in the literature (see, e.g., [134] and [72]). One interesting idea, focusing on the sampling clock jitter alone, is to sample another known signal parallel to the actual sampling task. Assuming that the same sampling clock is used in both tasks, samples of the known signal can basically be used to determine the clock deviations, which in turn are then used in interpolating the actual signal of interest sampled. This, of course, takes only the sampling clock nonidealities into account, and thus neglects those of the sampling circuit(s). A related alternative is to use only one sampling device and to inject or superimpose a known reference signal at the sampler input for jitter estimation purposes. With proper oversampling and/or analog filtering, the “unused” parts of the sampler input spectrum forms one interesting possibility for reference signal injection. Another interesting idea is to move away from the traditional uniform sampling principle and devise signal-dependent nonuniform sampling schemes which would be more robust to timing jitter by design. To illustrate the idea, it is clear that for any bandpass-type oscillating signal, the behavior of the waveform around the peak values is relatively immune to small time deviations around the peak instant. This is, of course, just one possible approach, but is a straightforward application of (15.21) since the signal derivative is obviously zero at the peaks. These types of approaches have very recently attracted some interest, but only very preliminary work has been reported so far. Yet another alternative approach for jitter cancellation in RF sampling radios is stemming from the obvious connection between jitter and carrier phase noise [73].

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Given that the overall waveform bandwidth sampled is much smaller than the inverse of the jitter rms value, the impact of sampling jitter in bandpass sampling can be modeled as a certain type of phase noise in the modulating carrier(s). Then, assuming further that there is correlation between consecutive jitter values, the iterative phase noise mitigation schemes described earlier can be employed for jitter cancellation [73].

15.4

CASE STUDIES IN I/Q IMBALANCE COMPENSATION

In this section we focus on more details regarding the I/Q imbalance compensation task in radio transmitters and receivers. The purpose is to introduce efficient and flexible I/Q imbalance calibration and compensation methods applicable in both direct-conversion and low-IF transmitters and receivers, and utilizable with most typically used communications waveforms. Here statistical signal processing–based techniques are emphasized, stemming from the circular nature of complex random signals (under perfect I/Q balance) described in Section 15.3.1. As shown in (15.35), the circularity of perfectly balanced communications waveforms is lost under I/Q imbalances, and thus imbalance mitigation can be based on introducing either proper predistortion in the transmitter or proper postprocessing in the receiver such that the signals are made circular again. This is described in more detail below [21,28,106, 135,136].

15.4.1

Transmitter I/Q Calibration

For generality, based on Section 15.3.1, we assume a general frequency-dependent I/Q imbalance model of the form z¯ TX (t) = g1,TX (t) ∗ z(t) + g2,TX (t) ∗ z ∗ (t). Then, stemming directly from the structure of this model, a natural form for predistortion processing is given by z p (t) = z(t) + wTX (t) ∗ z ∗ (t)

(15.37)

where wTX (t) denotes the predistortion filter impulse response and z p (t) is the predistorted baseband waveform. Then the combined baseband model for the overall TX waveform, including the predistortion, can be directly written as z¯ TX,p (t) = g1,TX (t) ∗ z p (t) + g2,TX ∗ z ∗p (t)

(15.38)

or ∗ (t)] ∗ z(t) z¯ TX,p (t) = [g1,TX (t) + g2,TX (t) ∗ wTX

+ [g2,TX (t) + g1,TX (t) ∗ wTX (t)] ∗ z ∗ (t)

(15.39)

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I/Q LO Pre-Distortion I

D/A LPF

I+jQ

RF (.)* Q

WTX (z)

D/A LPF

DSP

A/D

LPF

LO2

FIGURE 15.11 Conceptual block diagram of I/Q modulation-based direct-conversion transmitter where digital predistortion is used for I/Q imbalance calibration. The predistortion filter coefficients are estimated using feedback from RF back to the digital domain.

Thus to remove the mirror-frequency interference (conjugate signal term), and thus to restore perfect I/Q balance, the predistortion filter should be selected such that [g2,TX (t) + g1,TX (t) ∗ wTX (t)] = 0 ∀t. This corresponds to the following optimum (reference) predistortion filter: opt

WTX ( f ) = −

G 2,TX ( f ) G 1,TX ( f )

(15.40)

In practice, the imbalance characteristics g1,TX (t) and g2,TX (t) defining the optimum solution above are of course unknown. A practical estimation scheme can then be obtained using a feedback signal from RF back to lower frequencies inside the transmitter. This is illustrated at a conceptual level in Fig. 15.11. To avoid excess I/Q errors due to the feedback path, we choose to use real down-conversion (instead of I/Q mixing) of the RF band to a low intermediate frequency, followed by IF sampling. In this way, the complex envelope of the generated RF signal can be captured in a reliable manner. Using this approach, the effective complex envelope (observed feedback signal) is essentially of the form z fb (t) = G fb e j fb z¯ TX,p (t − τfb ), where G fb , fb , and τfb denote the relative gain, phase, and delay of the feedback path, respectively. Now initializing the predistortion coefficients wTX (t) in the beginning with all zeros, it is very interesting to note that cross-correlations between the feedback signal z fb (t) and the transmitter data z(t) provides a basis for identifying the imbalance model filters g1,TX (t) and g2,TX (t), and thus the optimum solution in (15.40). More precisely, we write the following two correlations: R1 (λ) = E[z fb (t)z ∗ (t − λ)] = G fb e j fb g1,TX (λ) ∗ Rz (λ − τfb )

(15.41)

R2 (λ) = E[z fb (t)z(t − λ)] = G fb e j fb g2,TX (λ) ∗ Rz (τfb − λ)

(15.42)

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where Rz (λ) = E[z(t)z ∗ (t − λ)] denotes the ordinary autocorrelation function of the opt ideal transmitter signal. These two correlations can then be used to solve for wTX (t) as described in more detail in [135]. Notice that Rz (λ) is basically known, being determined by the type of waveforms used (modulation, etc.). Above, we have further assumed that the ideal transmit signal z(t) is a circular random signal for which the conjugate autocorrelation vanishes, as defined in (15.34). This assumption can be shown to hold for most complex communications waveforms of practical interest (see, e.g., [91,107–110]). In practice, the correlations above are evaluated using sample correlations over a processing block of N samples. For more details on solving (15.41) and (15.42) for the optimum compensator, refer to [135]. In [135] it is also shown analytically that a nonideal frequency response (due to filtering, etc.) of the feedback loop does not degrade the calibration performance. This is, of course, a clear practical benefit. An alternative approach to using the feedback signal for predistortion coefficient estimation stemming from least-squares model fitting principles is described in [135]. Some practical examples on applying the compensation principle above to a 3GPP long- term evolution (LTE) mobile transmitter is given in Section 15.4.3. 15.4.2

Receiver I/Q Imbalance Compensation

Next, we turn the focus on receiver I/Q imbalance mitigation. The idea is to do some postprocessing on the signal observed, z¯ RX (t) = g1,RX (t) ∗ z(t) + g2,RX (t) ∗ z ∗ (t), to push down the mirror-frequency interference in the receiver digital front end. Here z(t) denotes the received and I/Q down-converted signal under perfect I/Q balance. Thus, conceptually, the mitigation task in the receiver is more complicated (compared to transmitter calibration) since the exact waveform structure of the perfectly balanced signal z(t) is unknown due to, for example, multipath, noise, and synchronization errors. Formally, the compensation structure to be deployed is similar to the transmitter case and is given by ∗ (t) z c (t) = z¯ RX (t) + wRX (t) ∗ z¯ RX

(15.43)

This is illustrated in Fig. 15.12. Then a direct substitution of the imbalanced signal z¯ RX (t) into the postprocessing model above yields ∗ z c (t) = [g1,RX (t) + wRX (t) ∗ g2,RX (t)] ∗ z(t) ∗ +[g2,RX (t) + w R X (t) ∗ g1,RX (t)] ∗ z ∗ (t)

(15.44)

Thus, the optimum solution for the postprocessing coefficients is the one that sets ∗ (t)] = 0 ∀t, or [g2,RX (t) + wRX (t) ∗ g1,RX opt

WRX ( f ) = −

G 2,RX ( f ) G ∗1,RX (− f )

(15.45)

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FROM RECEIVER I/Q FRONT-END

zRX

483

zc (.)*

FILTER

wRX

FIGURE 15.12 Receiver I/Q imbalance compensation using widely linear postprocessing filtering. The compensation filter coefficients are estimated using the statistical properties of the complex signals received and compensated.

As on the transmitter side, the exact imbalance behavior [g1,RX (t) and g2,RX (t)] defining the optimum solution in (15.45) is unknown and thus needs to be estimated. Here, opposed to the TX side, the perfectly balanced signal z(t) is not directly accessible, and a totally blind estimation technique is formulated below, using only the rich statistics of the complex signal received. First note that the conjugate correlation of the signal received, z¯ RX (t), is given by ∗ (t − τ ))∗ ] = E[¯z RX (t)¯z RX (t − τ )] CRX (τ ) = E[¯z RX (t)(¯z RX

= g1,RX (τ ) ∗ g2,RX (−τ ) ∗ Rz (τ ) +g1,RX (−τ ) ∗ g2,RX (τ ) ∗ Rz (−τ )

(15.46)

in which we have again assumed that the perfectly balanced signal z(t) is a circular random signal for which E[z(t)z(t − λ)] = 0 ∀λ, and Rz (λ) = E[z(t)z ∗ (t − λ)] is the ordinary autocorrelation of z(t). Notice that the circularity property of the perfectly balanced signal received, z(t), is independent of, for example, the wireless channel and synchronization information, as shown in [28]. Thus overall, based on the discussion above, I/Q imbalances make the signal observed noncircular, since, clearly, CRX (τ ) = 0, at least for some lags τ . This, in turn, implies that restoring the circular nature of the signal observed means essentially restoring the perfect I/Q balance and thus pushing down the mirror-frequency interference. Based on this, a practical estimation scheme to approximate the optimum solution in (15.45) is obtained by finding such postprocessing coefficients wRX (t) that z c (t) = z¯ RX (t) + ∗ (t) is forced circular for the span of the compensation filter wRX (t); wRX (t) ∗ z¯ RX that is, E[z c (t)z c (t − τ )] = 0

(15.47)

for values of τ within the length of wRX (t). For more details on the practical algorithm developments, including both adaptive and block processing–based solutions, refer to [28].

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Example Application: 3GPP Long-Term Evolution

At the transmission layer, one of the most essential targets in LTE is to clearly improve the spectral efficiency and throughput compared to existing 3G and 3.5G systems. To reach this goal, flexible spectrum use in terms of adaptive modulation and coding as well as fast user scheduling in both time and frequency domains are generally seen as some of the key ingredients [14,15]. In downlink, the transmission and multipleaccess technique selected is OFDMA, while the uplink is based on SC-FDMA. OFDM(A) is a direct application of multi-carrier modulation and frequency-domain multiplexing, in which the individual mobile stations are each allocated unique subsets of subcarriers from the overall subcarrier pool. Also SC-FDMA can be interpreted and implemented as a collection of subcarriers utilizing the DFT-spread OFDMA principle. Subcarrier data modulations up to 16QAM and 64QAM are supported in the uplink and downlink, respectively. The basic subcarrier spacing in both uplink and downlink is 15 kHz, and the overall operator bandwidth is scalable, ranging from 1.4 up to 20 MHz. The most typical assumptions are 5- and 10-MHz operator bandwidths, which correspond to 300 (out of 512) and 600 (out of 1024) active subcarriers, respectively. The basic building block in frequency-domain scheduling and scaling the individual mobile bandwidths is the physical resource block (PRB), which according to current standardization work contains 12 subcarriers. In time direction, the corresponding unit is called a time slot, whose length in the current specifications is 0.5 ms. Such a time-frequency element (0.5 ms, 12 subcarriers) is the basic building block in all radio resource management (RRM). Thus, for each mobile, at any given time the overall bandwidth is an integer multiple of 12 subcarriers (180 kHz) and the exact set of used subcarriers (part or subband of the entire operator band) can basically change from one 0.5-ms time slot to another. The previous challenging targets of fast scheduling and easily adaptable waveform bandwidth obviously have some implications in radio transmitter and receiver implementations. To control the locations (subbands) of the individual mobiles within the overall operator band as efficiently as possible, the basic working assumption is that both the mobile and base-station transmitters and receivers will be based on the I/Q up- and down-conversion principle, with fixed-frequency analog oscillators (within one operator band), such that the center frequency of the entire operator band corresponds to dc-bin. On the base-station side, this is a relatively obvious choice, seen, for example, to minimize the needed digital front-end sampling rate, but on the mobile transmitter side, the more traditional approach of implementing the frequency tuning (within the operator band) by tuning the analog LO could be an alternative as well. However, doing the subband tuning digitally is indeed seen to enable highly flexible and easily adaptable spectrum use, and is thus the most favorable choice in that sense. Notice also that with multi-carrier waveforms, tuning in the digital domain means simply proper subset or allocation of the subcarriers within the overall subcarrier pool. However, this also implies that from a particular mobile signal point of view, the mobile transceivers are essentially low-IF transceivers, and thus the mirror-frequency interference due to I/Q imbalances should be addressed with care.

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TX SPECTRUM

f fLO FIGURE 15.13

fMS

I/Q up-converted mobile TX spectrum without predistortion.

In the following, the previous statistical signal processing based I/Q imbalance and mirror-frequency interference mitigation techniques are employed in a 3GPPLTE context. Although the focus in the examples below is mostly on the uplink (mobile TX, base-station RX, SC-FDMA waveforms), the I/Q imbalance mitigation techniques presented are directly applicable in the downlink as well. 15.4.4 I/Q Imbalance Impact and Compensation Performance in an LTE Uplink In the first example scenario, we focus on demonstrating the achievable calibration performance in an LTE mobile (uplink) transmitter. As a concrete example, we assume that the overall system bandwidth is 10 MHz, consisting of 15-kHz subcarriers, as described above. In this example, the mobile station at hand occupies a band of 180 subcarriers from 0.765 to 3.45 MHz (before I/Q up-conversion), yielding roughly 2.7 MHz of bandwidth. A principal RF spectrum is illustrated in Fig. 15.13. The digital front-end sample rate in the mobile transmitter is 1024 × 15 kHz = 15.36 MHz, where 1024 is the IFFT size used [14,15]. The subcarrier data modulation is 16QAM, and frequency-selective I/Q mismatches are assumed for the mobile TX front end (see Fig. 15.14), with the resulting mirror-frequency attenuation varying smoothly between 25 and 40 dB. A three-tap digital predistortion filter is then used for I/Q calibration, and a block of samples is used to evaluate the sample correlations corresponding to (15.42). As explained in [135], these are then used to determine the calibration parameters (coefficients of the three-tap predistortion filter). This procedure is then repeated 10 times for independent transmit data realizations, to collect some statistics of the calibration performance. The results obtained are shown in Fig. 15.14. Very good calibration performance is obtained, the mirror-frequency attenuation with predistortion being on the order of 60 to 65 dB at the band used. For further examples for alternative calibration and estimation schemes, refer to [135]. Next we turn our attention to the LTE base-station receiver (uplink) side and give an example of the I/Q mismatch mitigation performance achievable using the recircularization-based compensation scheme described in Section 15.3.3. Again, we assume that the overall system bandwidth is 10 MHz and is now used by four rather wideband mobiles. Altogether 600 subcarriers are active and divided among the mobiles as 300, 144, 84, and 72, corresponding to individual mobile bandwidths

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80 Compensated, Average Compensated, Realizations Analog Front−End

70

Attenuation [dB]

c15

60 50 40 30 20 10

mirror band −6

−4

mobile band

−2 0 2 4 Relative Frequency [MHz]

6

FIGURE 15.14 I/Q calibration performance in a low-IF LTE uplink mobile transmitter with a three-tap digital predistortion filter.

of roughly 4.5, 2.16, 1.26, and 1.08 MHz. Thus, altogether, 9 MHz of the overall spectrum of 10 MHz is in use. The data modulation used is 16QAM for each mobile. Before arriving at the base-station, the mobile signals travel through individual multipath fading channels, drawn from the extended vehicular A power-delay profile [137]. The velocities of the four mobiles are 30, 3, 120, and 240 km/h and the RF carrier band is 2 GHz. The channel model includes also additive noise, the average SNR received being 20 dB. We further assume a challenging case of having 20 dB average dynamics in the overall spectrum received (due to fading and imperfect power control), such that the relative average spectral density levels of the four mobiles at the base-station receiver are 0, 10, 15, and 20 dB. Thus, the wideband mobile (with 4.5 MHz of bandwidth) has the weakest signal and is thus most sensitive to the mirror-frequency interference, which in this case is contributed by the other three mobiles. A principal down-converted spectrum is illustrated in Fig. 15.15. The digital front-end sample rate is 1024 × 15 kHz = 15.36 MHz, and again frequency-selective I/Q mismatches are assumed for the base-station RX front end (see Fig. 15.16), with the resulting

f fMS,1

0

fMS,2

fMS,3 fMS,4

FIGURE 15.15 Base-station I/Q down-converted RX spectrum with four mobiles (MS,1 to MS,4) and without I/Q imbalance compensation.

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487

80 Compensated, Average Compensated, Realizations Analog Front−End

70

Attenuation [dB]

c15

60 50 40 30 MS#1

MS#2 MS#3 MS#4

0 dB

10 dB 15 dB 20 dB

20 10

−6

−4

−2 0 2 4 Relative Frequency [MHz]

6

FIGURE 15.16 I/Q mismatch compensation performance in an I/Q down-converting LTE base-station (uplink) receiver with a three-tap digital compensation filter. The overall bandwidth of 9 MHz is used unequally by four different mobiles, and the overall dynamics in the spectrum is 20 dB.

mirror-frequency attenuation varying smoothly between 30 and 40 dB. A three-tap digital postprocessing compensation filter is used and a block of N = 200,000 samples received is used to determine the recircularization coefficients, as described in Section 15.3.3 (for more details, refer to [28]). The results are shown in Fig. 15.16, with 10 independent simulation realizations. Very good mirror-frequency attenuation is again obtained. Notice also that the compensator is really tuning most attenuation to those frequencies that are most sensitive to the mirror-frequency interference (in this case, the mirror band of mobile 4).

15.5

CONCLUSIONS

In this chapter we focused on the dirty-RF theme, addressing different types of nonidealities and imperfections of the most common RF/analog components and modules used in building and implementing radio transmitters and receivers. The overall focus was on building signal and link level understanding on the most essential impairment effects through proper component and signal modeling, as well as devising some digital signal processing techniques that can be used in transmitters and receivers to reduce the effects of such imperfections. Practical example imperfections covered in the chapter include mirror-frequency interference due to I/Q imbalance, power amplifier nonlinear distortion, oscillator phase noise, sampling jitter, and nonlinear distortion due to receiver small-signal components. I/Q imbalance and the resulting mirror-frequency interference were used as practical examples of more detailed DSP-based mitigation algorithm developments. To illustrate the potential and

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opportunities that such impairment mitigation techniques can offer in future radio implementations, the techniques developed were applied directly with good success in a 3GPP long-term evolution system context, to reduce the I/Q imbalance effects efficiently in both mobile and base-station radios. Overall, the various developments and RF impairment mitigation ideas described in this chapter are good examples of new opportunities that clever use of DSP can offer in radio transceiver design and implementation. Being able to compensate for different nonidealities of the analog RF sections basically relieves the specifications for those parts (e.g., by helping to reduce the power consumption of the corresponding analog blocks). Thus, cheaper circuit technologies and simpler radio architectures can be utilized than in more traditional radio devices, thereby facilitating flexible multimode, multi-band transceiver design for future wireless communications systems. Also, philosophically, we strongly believe that bringing the radio engineering and signal processing communities even closer together, through the type of developments described in this chapter, will open up new possibilities and increased synergy benefits in the future for the design and implementation of flexible radio transceivers. Acknowledgments Special thanks are in order to Prof. Markku Renfors, Tampere University of Technology, Finland; Prof. Visa Koivunen, Helsinki University of Technology, Finland; Lauri Anttila, Tampere University of Technology, Finland; Ali Shahed, Tampere University of Technology, Finland; and Ville Syrj¨al¨a, Tampere University of Technology, Finland.

REFERENCES 1. R. Tafazolli, Ed., Technologies for the Wireless Future: Wireless World Research Forum (WWRF). Chichester, UK: Wiley, 2004. 2. M. Brandolini, P. Rossi, D. Manstretta, and F. Svelto, “Toward multi-standard mobile terminals: fully integrated receivers requirements and architectures,” IEEE Trans. Microwave Theory Tech., vol. 53, no. 3, pp. 1026–1038, Mar. 2005. 3. C. Chien, Digital Radio Systems on a Chip. Norwell, MA: Kluwer, 2001. 4. J. Crols and M. S. J. Steyaert, CMOS Wireless Transceiver Design. Dordrecht, The Netherlands: Kluwer, 1997. 5. W. Tuttlebee, Ed., Software Defined Radio: Enabling Technologies. Chichester, UK: Wiley, 2002. 6. M. Valkama, J. Pirskanen, and M. Renfors, “Signal processing challenges for applying software radio principles in future wireless terminals: an overview,” Int. J. Commun. Syst., vol. 15, pp. 741–769, Oct. 2002. 7. G. Fettweis et al., “Dirty RF: a new paradigm,” in Proc. IEEE Personal, Indoor and Mobile Radio Communications (PIMRC’05), Berlin, pp. 1340–1344, Sept. 2005. 8. P. B. Kenington, RF and Baseband Techniques for Software Defined Radio. Norwood, MA: Artech House, 2005.

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9. R. M. Rao and B. Daneshrad, “Analog impairments in MIMO-OFDM systems,” IEEE Trans. Wireless Commun., vol. 5, no. 12, pp. 3382–3387, Dec. 2006. 10. T. C. W. Schenk, “RF impairments in multiple antenna OFDM: influence and mitigation,” Ph.D. dissertation, TU Eindhoven, The Netherlands, Nov. 2006. 11. E. Cetin, I. Kale, and R. C. S. Morling, “Living and dealing with RF impairments in communication transceivers,” in Proc. IEEE International Symposium Circuits and Systems (ISCAS’07), New Orleans, LA, pp. 21–24, May 2007. 12. R. Stuhlberger, R. Krueger, B. Adler, J. Kissing, L. Maurer, G. Hueber, and A. Springer, “LTE-downlink performance in the presence of RF-impairments,” in Proc. European Conference on Wireless Technology 2007 (ECWT’07), Munich, Germany, Oct. 2007. 13. J. Tsui, Digital Techniques for Wideband Receivers. Norwood, MA: Artech House, 1995. 14. Third-Generation Partnership Project (3GPP), TS 25.814 Physical Layer Aspects for Evolved UTRA. http://www.3gpp.org/ftp/Specs/html-info/25814.htm. 15. Third-Generation Partnership Project (3GPP), TS 36.300 Evolved Universal Terrestrial Radio Access (E-UTRA) and Evolved Universial Terrestrial Radio Access (E-UTRAN), Overall description, Stage 2, http://www.3gpp.org/ftp/Specs/html-info/36300.htm. 16. A. A. Abidi, “Direct-conversion radio transceivers for digital communications,” IEEE J. Solid-State Circuits, vol. 30, no. 12, pp. 1399–1410, Dec. 1995. 17. X. Li and M. Ismail, Multi-Standard CMOS Wireless Receivers. Norwell, MA: Kluwer, 2002. 18. S. Mirabbasi and K. Martin, “Classical and modern receiver architectures,” IEEE Commun. Mag., vol. 38, no. 11, pp. 132–139, Nov. 2000. 19. B. Razavi, RF Microelectronics. Upper Saddle River, NJ: Prentice Hall, 1998. 20. ———, “Design considerations for direct-conversion receivers,” IEEE Trans. Circuits Syst. II, vol. 44, no. 6, pp. 428–435, June 1997. 21. L. Anttila, M. Valkama, and M. Renfors, “Blind moment estimation techniques for I/Q imbalance compensation in quadrature receivers,” in Proc. IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC’06), Helsinki, Finland, Sept. 2006. 22. T. C. W. Schenk, P. F. M. Smulders, and E. R. Fledderus, “Estimation and compensation of TX and RX IQ imbalance in OFDM-based MIMO systems,” in Proc. IEEE Radio Wireless Conference (RWS’06), San Diego, CA, pp. 215–218, Jan. 2006. 23. A. Tarighat and A. H. Sayed, “MIMO OFDM receivers for systems with IQ imbalances,” IEEE Trans. Signal Process., vol. 53, no. 9, pp. 3583–3596, Sept. 2005. 24. J. Tubbax et al., “Joint compensation of IQ imbalance and frequency offset in OFDM systems,” in Proc. IEEE Radio Wireless Conference (RAWCON’03), Boston, pp. 39–42, May 2003. 25. M. Valkama, M. Renfors, and V. Koivunen, “Advanced methods for I/Q imbalance compensation in communications receivers,” IEEE Trans. Signal Process., vol. 49, no. 10, pp. 2335–2344, Oct. 2001. 26. M. Valkama, “Advanced I/Q signal processing for wideband receivers: models and algorithms,” Ph.D. dissertation, Tampere University of Technology, Finland, Nov. 2001. 27. M. Windisch and G. Fettweis, “Standard-independent I/Q imbalance compensation in OFDM directconversion receivers,” in Proc. International OFDM Workshop (InOWo’04), Dresden, Germany, Sept. 2004.

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95. L. Yu and W. M. Snelgrove, “A novel adaptive mismatch cancellation system for quadrature IF radio receivers,” IEEE Trans. Circuits Syst. II, vol. 46, no. 6, pp. 789–801, June 1999. 96. K. P. Pun, J. E. Franca, C. Azeredo-Leme, C. F. Chan, and C. S. Choy, “Correction of frequency-dependent I/Q mismatches in quadrature receivers,” Electron. Lett., vol. 37, no. 23, pp. 1415–1417, Nov. 2001. 97. A. Tarighat, R. Bagheri, and A. H. Sayed, “Compensation schemes and performance analysis of IQ imbalances in OFDM receivers,” IEEE Trans. Signal Process., vol. 53, no. 8, pp. 3257–3268, Aug. 2005. 98. D. Tandur and M. Moonen, “Joint compensation of OFDM frequency selective transmitter and receiver IQ imbalance,” in Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP’07), HI, Apr. 2007. 99. T. C. W. Schenk, P. F. M. Smulders, and E. R. Fledderus, “Estimation and compensation of frequency selective TX/RX IQ imbalance in MIMO OFDM systems,” in Proc. IEEE International Conference on Communications (ICC’06), Istanbul, Turkey, pp. 251–256, June 2006. 100. A. Schuchert, R. Hasholzner, and P. Antoine, “A novel IQ imbalance compensation scheme for the reception of OFDM signals,” IEEE Trans. Consumer Electron., vol. 47, no. 3, pp. 313–318, Aug. 2001. 101. F. Harris, “Digital filter equalization of analog gain and phase mismatch in I -Q receivers,” in Proc. IEEE International Conference on Universal Personal Communications, Cambridge, MA, pp. 793–796, Oct. 1996. 102. M. Valkama, M. Renfors, and V. Koivunen, “Blind I/Q imbalance compensation in OFDM receivers based on adaptive I/Q signal decorrelation,” in Proc. IEEE International Symposium on Circuits Systems (ISCAS’05), Kobe, Japan, pp. 2611–2614, May 2005. 103. ———, “Blind I/Q signal separation based solutions for receiver signal processing,” EURASIP J. Appl. Signal Process. Special Issue on DSP Enabled Radios, vol. 16, pp. 2708–2718, Sept. 2005. 104. ———, “Compensation of frequency-selective I/Q imbalances in wideband receivers: Models and algorithms,” in Proc. Third IEEE Signal Processing Workshop on Signal Processing Advances in Wireless Communications (SPAWC’01), Taoyuan, Taiwan, pp. 42–45, Mar. 2001. 105. M. Windisch and G. Fettweis, “Preamble design for an efficient I/Q imbalance compensation in ofdm direct-conversion receivers,” in Proc. International OFDM Workshop (InOWo’05), Hamburg, Germany, Aug. 2005. 106. L. Anttila, M. Valkama, and M. Renfors, “Blind compensation of frequency-selective I/Q imbalances in quadrature radio receivers: circularity-based approach,” in Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP’ 07), HI, Apr. 2007. 107. F. D. Neeser and J. L. Massey, “Proper complex random processes with applications to information theory,” IEEE Trans. Inf. Theory, vol. 39, no. 4, pp. 1293–1302, July 1993. 108. A. Papoulis, Probability, Random Variables, and Stochastic Processes, 4th ed. New York: McGraw-Hill, 2002. 109. B. Picinbono and P. Bondon, “Second-order statistics of complex signals,” IEEE Trans. Signal Process., vol. 45, no. 2, pp. 411–420, Feb. 1997.

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127. D. W. Lim et al., “A new PTS OFDM scheme with low complexity for PAPR reduction,” IEEE Trans. Broadcast., vol. 52, no. 1, pp. 77–82, Mar. 2006. 128. S. H. Muller and J. B. Huber, “OFDM with reduced peak-to-average power ratio by optimum combination of partial transmit sequences,” IEE Electron. Lett., vol. 33, no. 5, pp. 368–369, Oct. 1997. 129. T. C. W. Schenk, P. F. M. Smulders, and E. R. Fledderus, “The application of spatial shifting for peak-to-average power ratio reduction in MIMO OFDM systems,” in Proc. IEEE Vehicular Technology Conference (VTC’06 Spring), Melbourne, Australia, pp. 1859–1863, May 2006. 130. ———, “Peak-to-average power reduction in space division multiplexing based OFDM systems through spatial shifting,” Electron. Lett., vol. 41, no. 15, pp. 860–861, July 2005. 131. A. Venkataraman, H. Reddy, and T. M. Duman, “Space-time coded OFDM with low PAPR,” EURASIP J. Appl. Signal Process., vol. 2006, 2006, article ID 87125. 132. D. Wulich, “Reduction of peak to mean ratio of multicarrier modulation using cyclic coding,” IEE Electron. Lett., vol. 32, no. 5, pp. 432–433, Feb. 1996. 133. E. Keehr and A. Hajimiri, “Equalization of IM3 products in wideband direct-conversion receivers,” in Digest of Technical Papers of IEEE International Solid-State Circuits Conference, San Francisco, pp. 204–205, Feb. 2008. 134. P. D. Hale et al., “Compensation of random and systematic timing errors in sampling oscilloscopes,” IEEE Trans. Instrum. Meas., vol. 55, no. 6, pp. 2146–2154, Dec. 2006. 135. L. Anttila, M. Valkama, and M. Renfors, “Frequency-selective I/Q mismatch calibration of wideband direct-conversion transmitters,” IEEE Trans. Circuits Syst. II, vol. 55, no. 4, pp. 359–361, April 2008. 136. M. Valkama, L. Anttila, and M. Renfors, “Some radio implementation challenges in 3G-LTE context,” in Proc. IEEE Workshop on Signal Processing Advances in Wireless Communications (SPAWC’07), Helsinki, Finland, June 2007. 137. T. B. Sorensen, P. E. Mogensen, and F. Frederiksen, “Extension of the ITU channel models for wideband (OFDM) systems,” in Proc. IEEE Vehicular Technology, Conference (VTC’05 Fall), Dallas, TX, pp. 392–396, Sept. 2005.

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Techniques for the Analysis of Digital Bang-Bang PLLs NICOLA DA DALT Infineon Technologies, Villach, Austria

16.1

INTRODUCTION

The first investigations into digital frequency synthesis began quite some time ago. In the 1970s, sentences like the following appeared in technical journals: “Owing to the development of large scale integrated digital circuits and to the use of the digital computers in the implementation of communication systems, the digital phase locked loops have emerged from a background of analog loops” [1] and overview papers on the status of the digital phase-locked loops (PLLs) were being published [2,3]. Analytical or semianalytical analyses of PLLs were also published, together with investigations on several loop filter topologies (see, e.g., [4] and [5]). Despite this research effort, in those years digital PLLs never really took off in practical high-performance applications. The reason could be that because of the lack of a practical low jitter digitally controlled oscillator, the performance achievable with these architectures were far from those of the analog loops. In the 1980s, the development of the charge pump–based PLL, together with the use of type IV phase/frequency detector (see [6]), removed some of the nasty limitations of the analog PLLs loops based on the multiplier phase detector. The advantages of this new analog topology were so evident that it was immediately widely adopted in all state-of-the-art frequency synthesizers. This event finally dashed the hopes of digital PLLs to catch up with the performances of analog PLLs, and during all the 1980s and 1990s, high-performance frequency synthesis was almost exclusively in the analog realm. Recently, the attention of researchers and industry has again moved to digital loops (e.g., [7–8]). Some publications show that fully integrated digital PLLs can achieve performances as good as those of traditional analog loops, yet with advantages in portability, area, flexibility, and robustness of the digital implementation. Among digital PLLs, probably the simplest implementation uses a phase detector with a binary output, where the phase difference between reference and divided clock is Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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TECHNIQUES FOR THE ANALYSIS OF DIGITAL BANG-BANG PLLs

quantized with a 1-bit resolution. These types of loops are also known as bang-bang PLLs (BBPLL) [29]. Due to their hardware simplicity, low area, and excellent jitter performance, digital BBPLLs are a candidate for integer-N frequency synthesis in front-end transceivers for tasks such as generation of clocks for ADCs and DACs, clocking of digital blocks, and high-speed digital I/O interfaces. In this chapter we provide an overview of some techniques for the analysis of digital BBPLLs. Some of them, such as the loop linearization or the z-domain modeling of digitally controlled oscillators, can be extended easily to other digital PLLs architectures. Others, such as Markov chain theory, offer an unconventional yet insightful approach which could stimulate further research in that direction.

16.2

DIGITAL BANG-BANG PLL ARCHITECTURE

The block diagram of the digital BBPLL is reported in Fig. 16.1. The PLL consists of a binary phase detector (BPD), a digital loop filter, a digitally controlled oscillator (DCO), and a feedback divider. The function of the BPD is to provide an indication of the phase difference between the reference clock and the feedback clock in binary form. Its operation is logically identical to the operation of an ideal sampling register, with the reference clock as data input and the divided clock as a sampling clock. The binary-phase information is fed to the digital loop filter, which consists of a proportional and an integrator path. The gain factors in the two paths are indicated by β and α for the proportional and integral paths, respectively. The digital filter is clocked by the divided clock itself, which, in locked conditions, is synchronous with the reference clock. In specific applications, the reference frequency of the PLL might be quite high, exceeding several hundred megahertz, and the operations to be performed by the loop filter might require more than just one clock cycle of the reference clock. The pipeline stages introduced into the actual implementation of the integral path are modeled by the delay block, with D being the number of reference clock delays. It is convenient to implement the summation of the proportional and the

LOOP FILTER gate delay

reference clock BPD

w

β ψ

α

DCO

z −D

z −1 feedback clock

Divider 1:N

dco clock

FIGURE 16.1 Block diagram of digital BBPLL.

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ANALYSIS OF THE NONLINEAR DYNAMICS OF THE BBPLL

integral path directly into the DCO. In LC oscillator–based DCOs, this summation can be performed rather easily (see [14]) and equivalent techniques could also be developed for ring oscillator–based DCOs. In this way, the latency of the loop filter for the proportional path is reduced to the delay of a few digital gates, which should be negligible compared to the reference clock period. Note that the architecture reported here differs from that analyzed in [19], where the latency also affects the proportional path.

16.3

ANALYSIS OF THE NONLINEAR DYNAMICS OF THE BBPLL

In this section, the dynamics of the BBPLL will be analyzed using the methodology already detailed in [19]. The delay introduced on the proportional path by the presence of some digital gates will be neglected, as it is much smaller than the reference clock period. 16.3.1

Nonlinear Map

Starting from the block diagram depicted in Fig. 16.1 and following the same derivation as in [19], the normalized nonlinear map describing the dynamics can be written as (the subscript k indicates the iteration number) τk+1 = τk − Rψk−D − sgn(τk ) ψk+1 = ψk + sgn(τk+1 )

(16.1)

In this equation R = α/β and D is the latency on the integral path expressed as the number of clock cycles. The two state variables ψ and τ are the integrator output and the jitter seen at the BPD input normalized to the DCO quantization step, respectively. More precisely, τ = t/Nβ K T , where t is the time difference between the edges of the reference and feedback clocks and K T is the period gain of the DCO. The only difference with respect to the map reported in [19] is that the sign term in the first equation does not depend on the delay D. This fact has a major impact on the loop dynamics. 16.3.2

Trajectories in the Phase Plane

We start the analysis by looking at the form of the trajectories of the system in the (τ, ψ) phase plane. A qualitative understanding of the behavior of the trajectories will allow us to derive analytical conditions for the stability of the BBPLL. The second equation of (16.1) indicates that for positive (negative) values of τ , ψ increases (decreases) by 1 after each iteration, independent of the value of τ . Therefore, the trajectories plotted in a (τ, ψ) phase plane will move upward on the right half-plane and downward in the negative half. Without loss of generality, it is assumed that ψ ∈ Z, where Z is the set of signed integers.

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15 4 10

3 2

5

1 0

ψ

ψ

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0

−1 −5

−2 −3

−10

−4 −4

−2

0 τ

2

(a)

4

−15 −40

−20

0 τ

20

40

(b)

FIGURE 16.2 (a) (τ, ψ) phase plane with indications of the trajectory directions for D = 0; (b) three examples of trajectories in the phase plane for D = 3, ψ0 = 0, τ0 = 20, R = 0.38 (stars), R = 0.18 (squares), and R = 0.36 (bold).

The first equation of (16.1) indicates that the variation in the values of τ is the sum of two terms. The term −sgn(τk ) depends only on the sign of τ and drives the trajectory toward the axis τ = 0. The term −R · ψk−D depends linearly on the value of ψ at the Dth previous iteration and can push the trajectory in the same or the opposite direction as the first term. For |ψ|  1/R the second term is dominant over the first one. The left hand-side of Fig. 16.2 illustrates the direction of the trajectories on the (τ, ψ) phase plane for the case D = 0. The vector field is symmetrical around the origin and forms a sort of whirl around it. The right hand-side of Fig. 16.2 shows an example of trajectories in the phase plane, obtained with D = 3, initial conditions ψ0 = 0 and τ0 = 20, and two different values of R. For R = 0.38 (circles) the trajectory is divergent, meaning that the BBPLL is unstable, whereas for R = 0.18 (squares) the trajectory is convergent, meaning that the BBPLL is stable. For R = 0.36, the trajectory describes a limit cycle around the origin. This value of R represents the stability limit for the system.

16.3.3

Conditions for Stability

To evaluate the stability of the BBPLL, the following argument will be used (see Fig. 16.3). A generic trajectory in the (τ, ψ) phase plane starts from the point (τ0 , 0), after M iterations crosses the ψ axis at point (τ M = 0, M), and after 2M iterations crosses the negative τ axis at point (τ2M , 0) . The quantity |τ2M | − τ0 will determine the nature of the trajectory. Namely, if |τ2M | − τ0 > 0, the trajectory will diverge (BBPLL is not stable), whereas if |τ2M | − τ0 < 0, the trajectory will converge (BBPLL is stable).

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ψ

(

( FIGURE 16.3

2M

M

= 0, M)

(

, 0)

0

τ

, 0)

Trajectory used to derive the stability condition for the BBPLL.

To represent correctly the conditions occurring in the initial locking of the BBPLL, the starting value τ0 will be assumed to be much bigger than 1. Taking the sum for k = 0 to k = i − 1 of the first equation in system (16.1) and substituting ψ(k − D) = k − D, we find for τi between τ0 and τ M ,  (i − 1)i −iD −i τi = τ0 − R 2


(16.2)

The value of i that makes τi = 0 can be considered as the trajectory initial radius M. The trajectory from (τ M , M) to (τ2M , 0) can be computed in a similar way. The result is shown in the equation set (16.3). ⎧ ⎪ ⎪τ M ⎪ ⎪ ⎪ ⎪ ⎨τ M τi = τ M ⎪ ⎪ ⎪ τM ⎪ ⎪ ⎪ ⎩

− R(M − D) − 1 − Ri(M − D + (i − 1)/2) + i − 2 − R(−D(D + 1) + i(M + D) + i (1 − i)/2) + i − 2

for i = 0 for i = 1 for 3 ≤ i ≤ D + 1

(16.3)

for i ≥ D + 2

Starting from point (τ M , M), the τ axis is reached after M iterations. Under the assumption of a big initial orbit, M ≥ D + 2, so that the last equation of system (16.3) applies to calculate τ2M : τ2M = R D(D + 1) −

R M2 − M(R D + R − 1) − 2 2

where τ M has been taken equal to 0. From (16.2), for i = M we find that −

RM R M2 + + R D M − M + τ0 = 0 2 2

(16.4)

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region of validity of the derivation

2 2D+1 D(D+1) 2D+1

D+2

FIGURE 16.4

M

Plot of Rcrit as function of M.

Substituting this expression in (16.4), the value for |τ2M | − τ0 can be calculated as |τ2M | − τ0 = −R D(D + 1) + M(R + 2R D − 2) + 2 Thus, the condition for the BBPLL to be stable is that R must be smaller than a critical value Rcrit : 

R < Rcrit =

2(M + 1) M(2D + 1) − D(D + 1)

(16.5)

According to this analysis, the stability condition for R depends on the radius M of the trajectory (see Fig. 16.4 for a plot of Rcrit as a function of M). The most stringent condition for stability is obtained for M → +∞ and corresponds to Rcrit = 2/ (2D + 1), such as for the BBPLL analyzed in [19]. As the trajectory radius decreases, the condition for stability relaxes. This analysis is valid for M ≥ D + 2, so that if the PLL is stable, its trajectory on the (τ, ψ) plane will be confined to the region |ψ| ≤ D + 1. Since in this region M ≤ D + 1, when the trajectory crosses the ψ axis from the half-plane τ > 0 into the half-plane τ < 0 at ψ = M, some of the values ψk−D are still negative. Those values will push the trajectory in the direction of increasing τ , reducing its radius. Actually, for very small values of M (M D + 1) as soon as the trajectory moves into the τ < 0 half-plane, the effect of the negative value of ψk−D could be so large as to move the trajectory back to τ > 0. This effect will reduce the radius of the trajectory with respect to the case with ψk−D all positive, thus helping the convergence. In summary, if the condition for stability (16.5) is met, the trajectory of the BBPLL will converge almost down to the point (0, 0). Due to the quantization in the loop, the trajectory will not stay fixed at (0, 0) but will move on a limit-cycle trajectory of minimal size around this point.

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FIGURE 16.5 Comparison of trajectories of the BBPLL (R = 0.16, D = 5) in absence of jitter (red) and the presence of an rms white jitter of Nβ K T on the reference clock (blue). Shown are (a) the trajectory and (b) the histogram of τ in the locked condition.

16.3.4

BBPLL in the Presence of Noise

The previous analysis assumes jitter-free reference and DCO clocks. In this case, the jitter arising from the trajectory in a locked state is bounded within −Nβ K T and +Nβ K T . Since this range can be made quite small by design, in real situations the dynamics of the BBPLL in a locked state is likely to be dominated by the noise sources that are inevitably present, such as the jitter on the reference clock end the thermal noise of the DCO and that of the BPD. Figure 16.5 shows the trajectory of the BBPLL in case of no jitter and in case of an rms jitter equal to 1 NβK T on the reference clock. In this second case, the trajectory in the locked state assumes a chaotic nature, and the output jitter of the BBPLL is not dominated by the intrinsic nonlinear dynamics, rather by the internal noise sources. This is evident by looking at the histograms of τ . In the rest of the chapter, we consider two possible approaches to analyze the performance of the BBPLL in the presence of noise. The first approach is modeling the BBPLL as a Markov chain; the second is linearizing the loop.

16.4

ANALYSIS OF THE BBPLL WITH MARKOV CHAINS

In this section we analyze the behavior of the BBPLL in the presence of jitter on the reference clock by modeling the BBPLL as a Markov chain [20]. The BBPLL under investigation is a second-order system and it should be modeled strictly as a two-dimensional vector Markov process. This would lead to a quite complicated mathematical analysis. To keep it simple, we will assume that α β, so that the loop can be well approximated by a first-order system, thus modeled as a “standard”

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Markov chain. An example of treatment of a two-dimensional vector Markov process applied to PLLs can be found in [21]. 16.4.1

On the Use of Markov Chains in the Analysis of Digital PLLs

The use of Markov chain theory in the analysis of the digital PLLs is not new; indeed, it was applied in the 1070s, especially to analysis of the performance of a particular class of digital PLLs, the zero-crossing digital PLL (ZC-DPLL). Lindsey [3] gives a good overview of the results of those analysis. Holmes considers a first-order ZCDPLL with a binary quantized phase detector [22]. The reference signal is assumed to be either sinusoidal or square-wave, with superimposed stationary white bandlimited Gaussian noise. The DPLL was modeled as a discrete-time, discrete-variable Markov chain. In the case of a square wave, the transition probabilities are independent of the error state, since the SNR of the sampled signal is constant. On the contrary, for a sinusoidal wave the SNR of the sampled signal depends on the sampling point (it is low close to the zero crossing and increasingly higher away from it). In this case the Markov chain has nonuniform transition probabilities such as in the case of a BBPLL with superimposed jitter. Although the physical explanation for the nonuniformity of the transition probabilities is different for the ZC-DPLL and the BBPLL, the mathematical model is the same. The author calculates the stationary-phase error probability density function (pdf) and the mean first slip time by solving the discrete stationary Chapman–Kolmogorov (C-K) equation. There are some differences between the analysis we present in this chapter and the one in [22]. First, the transition probabilities in [22] are determined by the input wave SNR, while in our case they are determined by the jitter distribution. Second, we calculate the stationary-phase error pdf by folding the stationary states probabilities with the jitter pdf. Third, the derived phase error pdf is used to linearize the BPD and we derive compact analytical expression of the BPD gain by simplifying the infinite-length Markov chain to a three-states chain. In [4], Cessna and Levy consider a digital PLL with binary quantization and several types of sequential filters. They approach the problem by using discrete-time, discrete-variable Markov chain theory, but resort to computer simulations to obtain the stationary-phase error pdf and other performance metrics. Weinberg and Liu [21] analyze a first- and second-order ZC-DPLL. They assume a sinusoidal input signal with a limited SNR and no jitter, and neglect any form of quantization in the loop. With these assumptions, the dynamics of the first-order loop can be described by a discrete-time, continuous-variable Markov process, while for the second-order loop the nonlinear dynamics is described in terms of a twodimensional vector Markov process. The authors calculate the stationary-phase error pdf by solving the stationary continuous C-K equation, where the sinusoidal term in the transition pdf is approximated by sin z = z (linear case) and sin z = z − z 3 /6 (second-order approximation). Since no quantization is assumed, this approach cannot be used for the analysis BBPLL. In [23], Chie provides an exact analysis of the phase error statistics of the firstorder ZC-PLL by solving the C-K equation using the method of moments. This paper

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505

also assumes a sinusoidal input with limited SNR, no jitter, and no quantization, and thus its analysis cannot be applied to the BBPLL either. It can be viewed as a theoretical extension of the work in [21]. The solution obtained is compared to the results of the application of the Fokker–Planck (F-P) equation to the analysis of a multiplier-based analog PLL. The F-P equation (for further details see [24]) is a partial differential equation that describes the pdf of a continuous-time random process satisfying Ito’s stochastic differential equation (SDE). Since a multiplier-based PLL in the presence of amplitude noise on the input wave can be described by Ito’s SDE, the F-P equation has been used to calculate its stationary-phase error distribution and other performance metrics [25]. Ito’s SDE can be applied to any type of nonlinearity (not only sinusoidal), inclusive of the sign function. However, since it describes a continuous-time process, it cannot be used directly in the case of the BBPLL, which is a discrete-time system. It would be necessary to convert the nonlinear finite-difference equations describing the BBPLL loop in differential form, introducing an approximation of the real dynamics. For these reasons we believe that the Markov chain approach for the BBPLL case is favorable. 16.4.2

Markov Chain Model of the BBPLL

In this derivation we assume that α β. The nonlinear map (16.1) in the presence of jitter tjr on the reference clock can be written as tk+1 = tk + tjr − Nβ K T sgn(tk )

(16.6)

where t = τ Nβ K T is the time difference between the edges of the reference and feedback clocks. Defining with t ∗ the value of t in the case of unjittered reference, t ∗ can assume values only on discrete states n Nβ K T + t0∗ , with n ∈ Z. When the BBPLL is locked, the integral path will have centered the dynamics so that we can assume that t0∗ = 0 and t ∗ = n Nβ K T , n ∈ Z. Every time t ∗ is in a given state n Nβ K T , the jitter on the reference distributes the actual t probabilistically around n Nβ K T , replicating the pdf of tjr , if tjr is a stationary process. Therefore, the pdf of t will be given by the superposition of the pdf of tjr shifted by an amount equal to each occupied state and weighted by the probability that in the steady state, t ∗ will occupy that state (see Fig. 16.6). Indicating with n the state n Nβ K T , with qn the stationary probability of occupancy of the state n: 

qn = P[t ∗ ∈ n] and with f t and f tjr the pdfs of t and tjr , respectively, we have f t (a) =

n=+∞  n=−∞

qn f tjr (a − n Nβ K T )

(16.7)

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−2N β KT

FIGURE 16.6 of tjr .

−N β KT

0

N β KT

a

2N β KT

Probability density function of t as a weighted superposition of the pdfs

In order to find the stationary probabilities qn , the BBPLL can be modeled as a Markov chain (see [26]) . From a given state n, t ∗ must go either to state n + 1 or to state n − 1. The transition probabilities are ∗ ∈ n + 1|tk∗ ∈ n] = P[tjr + n Nβ K T ≤ 0] = Ftjr (−n Nβ K T ) P[tk+1 ∗ P[tk+1 ∈ n − 1|tk∗ ∈ n] = 1 − Ftjr (−n Nβ K T )

where Ftjr is the cumulative distribution function (cdf) of tjr and P[A|B] indicates the probability of event A given event B [26]. The Markov chain representing the  BBPLL is illustrated in Fig. 16.7, where G n = Ftjr (n Nβ K t ). It is actually a random walk with nonuniform transition probabilities. The transition probability matrix P is defined such that its element (i, j) is the probability to go from state i to state j in one step: ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ P = ⎢· · · ⎢ ⎢ ⎢ ⎢ ⎢ ⎣

⎤

.. . 1 − G2 0

0 1 − G1

G2 0

0 G1

0 0

0 0

0 0

0 0 0

0 0 0

1 − G0 0 0

0∗ 1 − G −1 0 .. .

G0 0 1 − G −2

0 G −1 0

0 0 G −2

G2

G3

...

-2 1 − G2

G1 -1

1 − G1

FIGURE 16.7

G0 0

1 − G0

G−1 1

G−2 2

...

1 − G−1 1 − G−2 1 − G−3

Markov chain representing the BBPLL.

⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ · · ·⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦

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Since the number of possible states is in principle infinite, P is a square matrix with infinite dimension. The superscript ∗ in the matrix elements denotes the element (0,0). If f tjr is symmetrical around 0, then G −n = 1 − G n (in particular, G 0 = 12 ) and the transition matrix has center symmetry around the (0,0) element: ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ P = ⎢· · · ⎢ ⎢ ⎢ ⎢ ⎢ ⎣

16.4.3

⎤

.. . G −2 0 0

0 G −1 0

G2 0 G0

0 G1 0∗

0 0 G0

0 0 0

0 0 0

0 0

0 0

0 0

G1 0 .. .

0 G2

G −1 0

0 G −2

⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ · · ·⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦

Stationary Probability Distribution

The stationary probabilities qn are defined by the discrete stationary Chapman– Kolmogorov equation: q=q·P

(16.8)

where q is the row vector [. . . , q−2 , q−1 , q0 , q1 , q2 , . . .]. Since the states describe all possible events and they are disjointed, qn must satisfy the normalization equation +∞ 

qn = 1

(16.9)

n=−∞

Equation (16.8) translates into an infinite set of linear equations: qn = G −n+1 qn−1 + G n+1 qn+1 , n ∈ Z

(16.10)

Since P is symmetrical, q−n = qn and it is enough to consider that n = 0, 1, . . . . Rewriting (16.10) for n = 0 , q0 = G 1 q−1 + G 1 q1 , so that q1 =

1 q0 2G 1

(16.11)

Taking the sum of the first n + 1 terms of (16.10) and using the result (16.11), qn+1 =

1 − Gn qn G n+1

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so that qn = q−n =

n  1 − G m−1 q0 Gm m=1

(16.12)

In order to find q0 , normalization equation (16.9) is used: 

qn = q0 + 2

+∞ 

n

qn = 1

n=1

and finally, 

+∞  n  1 − G m−1 q0 = 1 + 2 Gm n=1 m=1

−1 (16.13)

If tjr is Gaussian distributed with variance σt2jr then Gn =

1 1 n Nβ K T + erf √ 2 2 σtjr 2

where  2 erf(x) = √ π



x

e−b db 2

0

Equations (16.7), (16.12), and (16.13), together with the pdf and cdf of the reference jitter, allow the exact calculation of the stationary distribution of the jitter at the BPD input.

16.5

LINEARIZATION OF THE BBPLL

Although the behavior of the first-order BBPLL with noise on the reference clock exactly fits a Markov chain model, it is difficult to proceed with the analysis on that path. In real situations, the BBPLL has additional noise sources (at least the phase noise of the DCO), the integral constant α cannot be negligibly small, due to hardware limitations, and the loop filter could be enriched with higher-order terms, as in standard charge pump PLLs. All these factors make the application of Markov chain theory increasingly difficult and well out of the scope of practical engineering. That’s why it makes sense to investigate the possibility of linearizing the system. The only nonlinear element in the loop is the BPD. If this can be linearized, the whole loop can be described in terms of z-domain transfer functions.

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16.5.1

Linearized Model of the Binary-Phase Detector

Consider the time difference between the edges of the reference and the feedback clock t. Due to the noise generated by blocks of the BBPLL and already present on the reference clock, t can be described as a random variable with a given cdf Ft (x) = P[t < x] and pdf f t (x) = ∂ Ft (x)/∂ x, where the operator P[A] indicates the probability of event A [26]. When the BBPLL is not locked, f t (x) assumes nonzero values far away from x = 0. During the locking process, the value of t converges to zero, meaning that its pdf is gradually centered around the origin. If the bandwidth of the BBPLL is small enough compared to the correlation time of t, a probabilistic approach based on expectations can be used to derive a linear model for a generic memoryless nonlinear phase detector (see [25] and [27]). 16.5.1.1 Linearization of Memoryless Nonlinear Phase Detectors Figure 16.8 shows the concept for the linearization of memoryless nonlinear phase detectors. On the left-hand side, the actual nonlinear phase detector can be represented as a subtracting node that produces t = tr − td , followed by a memoryless nonlinear function g(x) that produces the phase detector output = g(t) (tr and td denote the time instants of the edges of the reference and divided clocks respectively). The function g(x) is the phase detector characteristic in the absence of noise. If t is a random process, the phase detector output will also be a random process. If the PLL loop bandwidth is small compared to the correlation time of t, the dynamic of the loop will react only to the average value of . By defining ¯ = E[ ] (the operator E[x] indicates the expectation of the random variable x), we can write = ¯ + n where n is a high-frequency noise term which does not contribute to the slow dynamics of the loop, but plays an important role in the overall noise performances. In the locked condition, the average value of the phase detector output must be zero E[ ] = 0. If this condition was not satisfied, the output of the integral path of the loop filter would gradually drift in one direction, modifying the output frequency and contradicting the assumption that the loop is locked. Therefore, in locked condition

tr

∆

g(x)

tr

∆t

Kbpd

¯

x td

td

FIGURE 16.8

Nonlinear phase detector linearization.

n

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the pdf f t is such that  ¯ = E[g(t)] =

+∞ −∞

g(a) f t (a) da = 0

(16.14)

If f t is shifted from its locked position by a quantity x, the effective phase detector characteristic geff (x) is given by  geff (x) = E[g(x + t)] =

+∞

−∞

g(x + a) f t (a) da

(16.15)

Note that in general the effective phase detector characteristic geff is different from the phase detector characteristic in the absence of noise g. Once geff has been found the gain of the phase detector is simply the derivative of geff (x) evaluated at the locking point x = 0: K BPD =

 ∂geff (x)  ∂ x x=0

(16.16)

Now this approach will be applied to two examples: The first is an ideal linear phase detector, the second is the BPD. Example 1: Ideal Linear Phase Detector pdf f t is such that  0=

+∞ −∞

In this case g(x) = K x. The steady-state

K a f t (a) da = K E[t] ⇒ E[t] = 0

Therefore, the equilibrium point of the loop is such that the mean value of the phase error in front of the phase detector is zero. From (16.15) the effective phase detector characteristic is  geff (x) =

+∞ −∞

K (x + a) f t (a) da = K x + K E[t] = K x

Therefore, in this case, geff and g are the same. Example 2: Binary Phase Detector f t is such that  0=

+∞

−∞

In this case g(x) = sgn(x). The steady-state pdf 

sgn(a) f t (a) da = −

0 −∞

 f t (a) +

+∞

f t (a) da 0

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so that Ft (0) = 1/2

(16.17)

Therefore, the equilibrium point of the loop is such that the median value of the phase error in front of the phase detector is zero. Note that if f t is not symmetrical, mean and median values are generally different. From (16.15) the effective phase detector characteristic is:  geff (x) =

+∞ −∞

 sgn(x + a) f t (a) da = −

−x −∞

 f t (a) +

+∞ −x

f t (a) da

so that geff (x) = 1 − 2Ft (−x) and the linearized BDP gain is equal to the double of the pdf of the jitter at zero: K BPD = 2 f t (0)

(16.18)

These results can be explained intuitively as follows. In the locked state the number of iterations with = −1 must on the average be equal to those with = +1; otherwise, the integral part of the loop filter would drift. This means that P[t < 0] = P[t > 0], which is nothing but the condition (16.17). Assume that for any reason (e.g., due to the intrinsic BBPLL dynamics) the pdf of t is shifted away from its locked point by a small amount x in the positive direction. In this case there will be more iterations with = 1 and less with = −1, so that the average value of will be slightly positive. The BBPLL will react to this situation and center the pdf again. To a first-order approximation, if the shift x is small enough, the probability that = 1 is increased by the quantity x f t (0), while the probability that = −1 is decreased by the same quantity. The net change in E[ ] is thus 2x f t (0), so that K BPD = 2 f t (0). 16.5.1.2 Computation of the BPD Gain for a First-Order BBPLL in Closed Loop The equivalent gain of the BPD K BPD cannot be fixed independent of the other parameters of the BBPLL (as is normally done in the literature [28]), since it depends on f t , which in turn depends on the dynamics of the BBPLL itself. Using (16.18) and (16.7) yields K BPD = 2

n=+∞  n=−∞

qn f tjr (−n Nβ K T )

(16.19)

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10

10

1

0

Kbpd

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−1

10

−1

0

10 σtjr

10

1

FIGURE 16.9 Plot of K BPD vs. σtjr (Gaussian jitter, Nβ K T normalized to 1): K BPD computed with a 101-state Markov chain (thick solid line), K √BPD approximated with a three-state Markov chain (thick dashed line), asymptote K BPD = 1/( 2π σtjr ) (thin solid line), asymptote K BPD = √ 2/( 2π σtjr ) (thin dashed line).

Figure 16.9 reports the plot of K BPD vs. σtjr for the case of a Gaussian reference jitter using (16.19), (16.12), and (16.13) (thick solid line). For this computation the Markov chain has been limited to 101 states, and Nβ K T has been normalized to 1. The asymptote for small values of σtjr can be derived as follows. On the assumption that σtjr Nβ K T , in the Markov chain the states n with |n| ≥ 2 occur with a probability that is negligibly small. The infinite Markov chain then simplifies to a three-state chain with perfectly reflecting barriers (see Fig. 16.10), and it is easy to show that q0 = 12 , q1 = q−1 = 14 . Applying (16.19), an approximate expression for K BPD in the case of Gaussian jitter is found: K BPD ≈ √

1 2π σtjr

  2 1 + e−(1/2)(Nβ K T /σtjr )

1 -1

FIGURE 16.10

1/2 0

1/2

(16.20)

1 1

Three-state Markov chain used as an approximation of the BBPLL.

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√ and for σtjr Nβ K T we find that K BPD = 1/( 2π σtjr ). The asymptote for large values of σtjr can be derived by considering that in this case the dynamic of the BBPLL has little influence on the pdf of t, since the displacement of the sampling point at multiples of Nβ K T is negligible compared to the jitter on the reference √ clock. Therefore, going back to (16.18), we can say that K BPD ≈ 2 f tjr (0) = 2/ 2π σtjr , which is the expression usually found in the literature (see [28]). Note that if used in the case of small σtjr , this result would be wrong by a factor of 2. Figure 16.9 reports the plots of (16.20) and of the two asymptotes. Interestingly, although derived under the assumption of small σtjr , (16.20) gives a good approximation (error is smaller than 25%) of the real K BPD on the whole axis.

16.5.2

Linear Model of the Digitally Controlled Oscillator

The DCO block can be modeled as a discrete-time linear system. The input of the system is the loop filter output w. Since the loop filter is clocked by the feedback clock and in locked condition, the feedback clock is synchronous to the reference clock, the signal w changes every reference clock period Tr 0 . Using the notation Z(T ) to identify the discrete-time domain made of multiples of T , the signal w is defined on Z(Tr 0 ). As every DCO clock cycle might, in principle, have a different period value (denoted by Tv ), the signal Tv can be defined on the discrete time domain Z(Tv0 ), where Tv0 is the nominal output clock period. This is valid if Tv is not very different from Tv0 (generally true for LC oscillators, where the tuning range is limited to some 10% of the nominal frequency). In locked condition, Tr 0 = Tv0 /N , where N is the feedback divider ratio. The interface between these two time domains is given by an interpolation with factor N . Figure 16.11 illustrates the DCO linear model. The control word w, defined on Z(Tr 0 ), is multiplied by the period gain K T and added to Tv0 , producing Tv , still defined on Z(Tr 0 ). This signal is extended to the domain Z(Tr 0 /N ) with a zeroorder hold interpolation filter. This process can be modeled by an ideal interpolation (insertion of N − 1 zeros between each two samples and multiplication of the signal amplitude by N ) followed by a gain of 1/N and a FIR filter having transfer function 1 + z −1 + z −2 + · · · + z −N +1 = (1 − z −N )/(1 − z −1 ).

T v0 w

loop filter output

KT

time domain Z(T r)

Tv

1/N

Tv1

1−z −N 1−z −1

Tv2

(1−a)z −1 1−az −1

N time domain Z(T r /N )

FIGURE 16.11

DCO linear model.

Tv3

1 1−z −1

tv

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Tv 1

Tr0

2Tr0

3Tr0

time

0

Tr0 2Tr0 Tr0 N N Tv2

2Tr0

3Tr0

time

0

Tr0 2Tr0 T r0 N N Tv3

2Tr0

3Tr0

time

0

Tr0 2Tr0 T r0 N N Td

2Tr0

3Tr0

time

2Tr0

3Tr0

time

0 Tv1 1

1

1

N

0

FIGURE 16.12 N = 4.

Tr0

Impulse response of the DCO and feedback divider linear model for

Finally, the sequence is filtered by a first-order lowpass transfer function (implemented with a first-order IR filter [1 − a)z −1 /(1 − az −1 )], which models the settling transient of the DCO and also introduces a delay for causality. The value of the parameter a can be estimated by analog simulations of the DCO. Figure 16.12 illustrates the impulse response of the DCO model for the case N = 4. The time instants of the edges of the DCO clock (tv ) are obtained by accumulation of the periods Tv3 . This is modeled as a simple time-discrete integrator.

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Tv3

Td

1−z −N 1−z −1

1 1−z −1

515

td

N time domain Z(Tr0 /N)

FIGURE 16.13

16.5.3

time domain Z(Tr0 )

Linear model for the feedback divider.

Linear Model of the Feedback Divider

The description of the feedback divider with factor N is relatively straightforward. It takes N consecutive periods Tv3 (see Fig. 16.12) of the DCO clock and adds them together to create one period of the feedback clock Td . The instants td of the feedback clock edges are then obtained by the incremental sum of the periods Td . The addition of the N periods can be modeled as a digital FIR filter defined on Z(Tr 0 /N ) having transfer function (1 − z −N )/(1 − z −1 ). The output of the FIR filter delivers a new value every Tr 0 /N seconds. To convert the signal back to the slower time domain, a decimation with factor N is necessary. The decimation ensures that two consecutive samples of Td are constituted by disjoint DCO clock periods and that no DCO clock period is skipped. Figure 16.13 illustrates the resulting linear model. 16.5.4

Complete Linear Model

The complete model of the BBPLL in the z-domain is obtained by substituting in Fig. 16.1 the linear models of the different building blocks. The resulting model is illustrated in Fig. 16.14. The proportional path of the loop filter has been modeled − as βz θ , where θ represents the ratio of the gate delay to the reference clock period Tr 0 . Note that z −1 , when converted to frequency, assumes different values for the two different time domains. Indeed, in Z(Tr 0 ), z −1 = exp(− j2π f Tr 0 ), whereas in Z(Tr 0 /N ), z −1 = exp(− j2π f Tr 0 /N ). Tv0 tr

∆t

Kbpd KT (βz −θ +

αz −D 1−z −1

Tv

)

(1−z −N )[(1−a)z −1 ] N(1−z −1 )(1−az −1 )

N time domain Z(Tr0 ) td

1 1−z −1

time domain Z(Tr0 /N)

Td

1−z −N 1−z −1

N

FIGURE 16.14

Linearized model for the BBPLL.

Tv3

1 1−z −1

tv

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Although this model is quite complete and detailed, the presence of two time domains Z(Tr 0 ) and Z(Tr 0 /N ) in the control loop complicates the mathematical derivation of the transfer functions that will be done later. Therefore, it makes sense to look for a simplification of the model which still gives a good approximation of the effective behavior. As a starting point, assume that the quantity a is zero, meaning that the DCO is able to settle instantly to the new frequency corresponding to the control word w. This is quite a good approximation to the real behavior. In this case, the function of the interpolator plus the zero-order hold is to create N identical samples of the incoming signal Tv . These N identical samples are then added together and the sum is given out as a result after the decimator. The entire chain from the interpolator to the decimator can then be replaced by a simple gain factor N . For the case a is not zero, the impulse response of the chain from the interpolator to the decimator has to be calculated. Referring to Fig. 16.12, an expression for  Tv3,k = Tv3 (kTr 0 /N ) can be found by iteratively solving the difference equation Tv3,k = (1 − a)Tv2,k−1 + aTv3,k−1 , which models the settling of the DCO. The result is

Tv3,k

⎧ ⎪ 0 ⎪ ⎨ = 1 − ak ⎪ ⎪ ⎩ (1 − a N )a k−N

for k = 0 for 1 ≤ k ≤ N for k ≥ N + 1

Due to the delay of one clock cycle, the first sample of Td at time zero will be zero. The second sample of Td (at time Tr 0 ) is equal to the sum of the first N nonzero samples of Tv3 , Td,1 = Tv3,1 + · · · + Tv3,N , and in general, Td,k = Tv3,(k−1)N +1 + · · · + Tv3,k N . After some algebra, the following expression can be found:

Td,k

⎧ 0 ⎪ ⎪ ⎪ ⎪ N ⎪ ⎪ ⎨N − a 1 − a 1−a = ⎪ ⎪ ⎪ ⎪ N 2 ⎪ ⎪ ⎩ (1 − a ) a k N −2N +1 1−a

for k = 0 for k = 1 for k ≥ 2

The resulting equivalent linear model is illustrated in Fig. 16.15. The loop is now entirely described in the slower time domain Z(Tr 0 ). Note that if a 1, the feedback path can be approximated with N − a + az −1 . The linearized model of the BBPLL is used in the next section to obtain analytical expressions for the output phase noise and the jitter of the BBPLL. 16.5.5

Linear Model of the BBPLL for Noise Analysis

In Fig. 16.16 the simplified model is illustrated again with some modifications. All quantities are now considered as differences from their nominal values. Therefore,

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time domain Z(Tr0 )

time domain Z(Tr0 /N) Tv0

tr

∆t

(

Kbpd KT βz −θ +

Tv

)

α z−D 1−z −1

(1−z −N )[(1−a)z −1 ] N(1−z −1 )(1−az −1 )

Tv3

tv

1 1−z −1

N td

z −1 1−z −1

Td

N −a

if a

(1−a 1−a ) N

1 Td

N − a + az −1

Tv

a(1−aN )2 z −1 (1−a)(1−aN z −1 )

FIGURE 16.15

Simplified linear model for the BBPLL.

the addition of the output clock nominal period Tv0 has been removed. Additionally, the internal and external noise sources are included. In particular tr is the jitter on the reference clock, tDCO is the jitter on the DCO output produced by the DCO itself, and tBPD is the equivalent input-referred jitter due to the quantization noise of the BPD. The quantities denoted with φ are the jitter contributions expressed in phase units. The blocks necessary to convert the phase noise into timing jitter are also shown. An expression for tBPD can be derived by considering Fig. 16.17, where the nonlinear and the linearized models for the BPD are reported. By equating the φdco Tr0 2πN

φr Tr0 2π

φbpd

1−z N N(1−z −1 )

Tr0 2π

T dco

tbpd tr

∆t

Kbpd KT ( βz −θ +

α z −D 1−z −1

)

Tdco

tdco 1 − z −1

N

Tv

(1−z −N )[(1−a)z −1 ] N(1−z −1 )2 (1−az −1 )

tv

2πN Tr0

φv

N td

z −1 1−z −1

Td

time domain Z(Tr0 )

FIGURE 16.16

N

time domain Z(Tr0 /N )

Simplified linearized model of the BBPLL with noise sources.

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∆t

sgn(∆t)

td

tr

∆t K Kbpd ∆t bpd

tbpd

FIGURE 16.17

td

Nonlinear and linearized models of the BPD.

outputs of the two models, the equivalent jitter, which must be introduced artificially at the input in order to emulate the quantization effect of the BPD, is 

tBPD =

sgn(t) − t K BPD

(16.21)

The DCO noise is modeled by the path from tDCO to the adder after the loop filter. The DCO timing jitter tDCO defined on Z(Tr 0 /N ) is converted into period jitter TDCO by the differentiation 1 − z − . A decimation with factor N is needed to be able to transfer TDCO in the Z(Tr 0 ) domain. However, a decimation alone would only take one of N DCO periods, so that the information present on the other N − 1 periods would be lost. To have a more accurate approach, the average over N periods is calculated using the block [(1 − z −N )/(1 − z − )/N ] and then decimated with factor N . The result T DCO represents the DCO period jitter averaged on N periods. Starting from the model in Fig. 16.16, it is straightforward to calculate the transfer functions from each noise injection point to the output tv and then compute the resulting phase noise power spectral density (PSD) and the standard deviation (rms value) of the jitter. To derive usable analytical expressions, tr and T DCO are assumed to be white Gaussian discrete-time random processes with zero mean. Regarding T DCO , this assumption leads to a DCO output phase noise having a 1/ f 2 characteristic (coming from the integration of white period noise), which agrees with the reality if flicker noise in the DCO can be neglected. Before starting with the mathematics, a small explanation of the notation used is needed. Ha,b (z) is the z-domain transfer function from signal a to signal b, and h a,b (k) is the corresponding impulse response (k = 0, 1, . . .). Time reversal is indicated by  − (k) = h a,b (−k). Given a discrete-time wide-sense stationary random process x(k), h a,b  its autocorrelation will be indicated by Rx (m) = E[x(k + m)x(k)∗ ] and its standard deviation by σx . If the process x has zero mean, the variance σx2 = Rx (0).

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16.5.6

519

Expression for the Power Spectral Density of the BPD Noise

To calculate the PSD of the phase noise at the BBPLL output, an estimation for the PSD of tBPD is needed. Roughly speaking, if the reference clock jitter is small compared to the bang-bang quantization step of the feedback clock Nβ K T , the BBPLL behaves like a first-order  modulator having a 1-bit quantizer with step 2Nβ K T . Therefore, it is reasonable to expect tBPD to resemble an almost white process with uniform distribution and variance σt2BPD = (Nβ K T )2 /3. However, it is also true that if the input jitter is very small, tBPD loops through Nβ K T , 0, −Nβ K T , 0, . . . , so that σt2BPD = (Nβ K T )2 /2. If the input jitter increases, however, it has to be expected that the  loop will be overloaded and that the equivalent jitter tBPD will also increase. To find out how the quantity σt2BPD behaves, simulations of the nonlinear map (16.6) have been made. The value tBPD has been calculated according to (16.21). In Fig. 16.18 the simulated value of σtBPD is reported for several values of reference jitter σtr . Several useful pieces of information can be extracted from this simulation. First, for σtr > 0.5Nβ K T , the jitter introduced by the BPD has a standard deviation that is roughly three-fourths of the standard deviation of the input jitter. For σtr < 0.5Nβ K T , the BPD jitter levels off around the value corresponding roughly to a uniform distribution, whereas for a very small input jitter, σtBPD increases slightly, as pointed out above. Figure 16.19 shows the absolute value of the autocorrelation coefficient of  tBPD , ρtBPD (m) = RtBPD (m)/σt2BPD . This result demonstrates that for σtr ≥ 0.5Nβ K T , tBPD is actually a white process. Figure 16.20 shows the absolute value of the

10

1

T

/(Nβ K )

10

2

0

tbpd

10

σ

c16

10

−1

σ of uniform distibution σ /(Nβ K ) tr T

10

−2

10

−2

10

−1

0

10 σ /(Nβ K ) tr

10

1

10

2

T

FIGURE 16.18 Simulation results for σtBPD /Nβ K T (circles) for different input jitter. The standard deviation of a uniform distribution and the input σtr /Nβ K T are also shown.

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1.5

|ρ

tbpd

|

1

0.5

0 0

10 10

5 10

10 Lag

15

10 20

FIGURE 16.19

10

−2

−1

0

1

σ /(N β K ) tr

T

2

Simulation results of the autocorrelation coefficient of tBPD .

0.8

tbpd,tr

|

0.6

0.4

|ρ

c16

0.2

0 −20

10 10

−10 10

0 Lag

10

10 20

FIGURE 16.20

10

1

−2

−1

0

σ /(N β K ) tr

T

2

Simulation results of the cross-correlation coefficient of tBPD and tr .

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cross-correlation coefficient of tBPD and tr , ρtBPD ,tr (m) = RtBPD ,tr (m)/(σtBPD σtr ). The results show that for σtr > 0.5Nβ K T , the two processes are already almost completely uncorrelated. This is a very important result, since it allows the application of the superposition principle to compute the PSD of the output phase noise. Considering those results, the value σtr = 0.5Nβ K T

(16.22)

can be taken as the threshold value, above which the BBPLL can be described correctly by a linearized equivalent system. Below this value the dynamics are mainly nonlinear and the jitter output of the BBPLL cannot be calculated with the linear model. 16.5.7

Power Spectral Density of the Output Phase Noise

At this point the noise analysis of the BBPLL is straightforward. Define φr , φBPD , and φDCO as the phase noises produced by the reference, the BPD, and the DCO, respectively, and φv as the phase noise at the BBPLL output. The frequency-domain PSD of the output phase noise can be obtained as a superposition of the contributions of the different noise sources:  2  2   Sφv ( f ) =  Hφr ,φv ( f ) Sφr ( f ) + SφBPD ( f ) +  HφDCO ,φv ( f ) SφDCO ( f )

(16.23)

The transfer functions can be calculated by inspection of Fig. 16.16. After some algebra, Hφr ,φv ( f ) =

K [βz −θ (1 − z −N ) + αz −D N ] (1 − z −N )2 + K z −N [βz −θ (1 − z −N ) + αz −D N ] 2  1 − z −N (1 − a)z − × 1 − z −1 N (1 − az − )

(16.24)

and HφDCO ,φv ( f ) =



(1 − z −N )2 (1 − z −N )2 + K z −N [βz −θ (1 − z −N ) + αz −D N ] 2  1 − z −N (1 − a)z − × 1 − z −1 N 2 (1 − az − )

(16.25)

where K = K BPD K T N . In both (16.24) and (16.25), z − = exp(− j2π f Tr 0 /N ). If more accuracy is needed, the constant K can be replaced by K BPD K T (N − a + az − ). From the discussions in Section 16.5.6, the PSD of the phase noise produced by the

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TABLE 16.1

Checkpoint Parameters Kα

Checkpoint

Kβ −3

CP1 CP2 CP3 CP4

10 3 × 10−2 7 × 10−2 10−2

4 × 10−2 10−1 0.9 4

BPD can be defined as  SφBPD ( f ) = max

4π 2 9 (Nβ K T )2 , Sφr ( f ) 3Tr 0 16

 (16.26)

Equations (16.20), (16.23), (16.24), (16.25), and (16.26), together with the specification of the reference clock and DCO phase noise PSDs, allow calculation of the phase noise at the output of the BBPLL. 16.5.8

Validation via VHDL Simulation

To validate the expressions for the phase noise output obtained from the linearized theory, a VHDL model of the BBPLL was built, including phase noise on the reference and on the DCO. The results of the VHDL model are compared to the analytical expression (16.23). The parameters of the BBPLL are Tr 0 = 1/(200 MHz), σtr = 4 ps, D = 1.5, K T = 4.3 ps, SφDCO ( f ) = 101/2 / f 2 , N = 24, θ = 0, and a = 0 [14]. The linearized gain of the BPD corresponding to this input jitter is K BPD = 1.4 × 1011 . Four checkpoints (CPs) have been selected for the simulations, corresponding to different values of K α and Kβ reported in Table 16.1. The first three checkpoints satisfy condition (16.22) for the validity of the linearized theory (with different ratios α/β), whereas the fourth does not. The results of the simulations are reported in Figs. 16.21 to 16.24. It can be seen that the agreement between theory and simulation is very good for the first three checkpoints, whereas for the fourth one there is a remarkable difference, meaning that in this case the output phase noise of the BBPLL cannot be predicted with the linear model. This is in agreement with the limit of validity of the theory expressed by (16.22). Indeed, from the value of Kβ reported in Table 16.1 and that of K BPD reported above, the minimum input jitter needed for the validity of the linear model [according to (16.22)] is 14.3 ps, whereas the reference clock considered here has only 4 ps. For this case, the dynamics of the system is mainly nonlinear. 16.5.9

Standard Deviation of Output Jitter

It is interesting to derive an analytic approximation of the BBPLL output jitter as a function of the input jitter. Assuming a white input jitter with variance σt2r , its PSD is Str ( f ) = Tr 0 σt2r

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Output Clock Phase Noise PSD [dBc/Hz]

−80 −90 −100 −110 −120 −130 −140 −150

Simulation Total Theory Total Reference BPD DCO

−160 −170 −180 4 10

FIGURE 16.21

5

10

6

7

10 10 Offset Frequency [Hz]

8

10

9

10

Comparison theory vs. VHDL simulation for checkpoint 1.

−80 Output Clock Phase Noise PSD [dBc/Hz]

c16

−90 −100 −110 −120 −130 −140 −150

Simulation Total Theory Total Reference BPD DCO

−160 −170 −180 4 10

FIGURE 16.22

5

10

6

7

10 10 Offset Frequency [Hz]

8

10

9

10

Comparison theory vs. VHDL simulation for checkpoint 2.

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−80 Output Clock Phase Noise PSD [dBc/Hz]

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−90 −100 −110 −120 −130 −140 −150

Simulation Total Theory Total Reference BPD DCO

−160 −170 −180 4 10

FIGURE 16.23

5

10

6

7

10 10 Offset Frequency [Hz]

8

9

10

10

Comparison theory vs. VHDL simulation for checkpoint 3.

−60 Output Clock Phase Noise PSD [dBc/Hz]

c16

−70 −80 −90 −100 −110 −120 −130

Simulation Total Theory Total Reference BPD DCO

−140 −150 −160 4 10

FIGURE 16.24

5

10

6

7

10 10 Offset Frequency [Hz]

8

10

Comparison theory vs. VHDL simulation for checkpoint 4.

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and from the discussion above we can assume also that StBPD ( f ) =

9 St ( f ) 16 r

The variance of the output jitter can be obtained as the integral of the output jitter PSD:  σt2v

=

Fv0 /2

−Fv0 /2

     Ht ,t ( f )2 St ( f ) + St df r v r BPD

resulting in σt2v =

25 Tr 0 σt2r 16



Fv0 /2 −Fv0 /2

   Ht ,t ( f )2 d f r v

(16.27)

Using Parseval’s theorem yields 

Fv0 /2

−Fv0 /2

   Ht ,t ( f )2 d f ≈ r v



Fr 0 /2 −Fr 0 /2

    Ht ,t ( f )2 d f = Fr 0 h 2tr ,tv (k) r d k

Since from inspection of Fig. 16.16, Htr ,tv = Hφr ,φv /N , it follows that h tr ,tv (k) ≈ Kβ(1 − Kβ)k if the effect of the term (1 − z −N )2 /(1 − z −1 )2 is neglected and α = 0, a = 0, and θ = 0 in (16.24). After some algebra we obtain σt2v =

25 2 Kβ σ 16 tr 2 − Kβ

(16.28)

Substituting K = K BPD K T N in (16.28) and using the approximation K BPD ≈ √ 2/ 2π σtr [see (16.20)], we obtain σt2v =

σt2r Nβ K T 25 √ 16 2π σtr − Nβ K T

(16.29)

√ If the input jitter is large enough ( 2π σtr  Nβ K T ), (16.29) can be rephrased as σtv 5 = √ 4 Nβ K T 4 2π



σtr Nβ K T

(16.30)

From this expression it can be seen that if the input jitter is larger than the minimum quantization step of the BBPLL, the output rms jitter grows linearly with the square root √ of the input rms jitter. The proportionality constant derived here analytically, 5/(4 4 2π ) ≈ 0.78, agrees with the empirical value of 0.7 found in [29] by performing extensive simulations.

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This behavior is different from that of a standard charge pump–based PLL, where the rms output jitter grows linearly with the rms input jitter. The reason is that in a BBPLL the gain of the binary phase detector is inversely proportional to the square root of the rms input jitter. Increasing the input jitter decreases the gain of the BPD, with in turns reduces the bandwidth of the input–output jitter transfer function, effectively improving the filtering of the BBPLL on the input jitter.

16.6

COMPARISON OF MEASUREMENTS AND MODELS

The output phase noise obtained applying (16.23) has been compared to phase noise measurements done on a digital BBPLL implemented in 130-nm CMOS technology (see Fig. 16.25 for a layout plot). This BBPLL, designed as a clock source for serial high-speed interfaces, features a BPD, a programmable digital filter, a triple-band LC DCO, and a feedback divider with N = 24 and has been described in [14]. The phase noise at the BBPLL output has been measured for several different settings of the loop filter constants and for operation at both 4.8 GHz (200-MHz input clock) and 2.2 GHz (91.6-MHz input clock). The measured phase noise has been plotted together with the phase noise spectra derived by the linearized model [applying (16.23)] and the VHDL simulations. In the linearized model and VHDL simulation the reference clock noise has been considered to be white with a phase noise value of −138 dBc/Hz for the 200-MHz input and −143 dBc/Hz for the 91.6-MHz input. The DCO phase noise has been set to −110 and −118 dBc/Hz at 1-MHz offset for 4.8- and 2.2-GHz operation, respectively.

FIGURE 16.25

Layout plot of the implemented BBPLL in 130-nm CMOS.

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FIGURE 16.26

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Phase noise PSD comparison for 4.8-GHz operation, α = 2−14 and β = 2−9 .

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FIGURE 16.27

VHDL Theory Meas.

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Output Clock Phase Noise PSD [dBc/Hz]

−90

FIGURE 16.28

VHDL Theory Meas.

−95 −100 −105 −110 −115 −120 −125 −130 −135 −140 4 10

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10

Phase noise PSD comparison for 4.8-GHz operation, α = 2−9 and β = 2−6 .

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FIGURE 16.29

VHDL Theory Meas.

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FIGURE 16.30

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−95 −100 −105 −110 −115 −120 −125 −130 −135 −140 4 10

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10

Phase noise PSD comparison for 2.2-GHz operation, α = 2−9 and β = 2−5 .

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FIGURE 16.31

VHDL Theory Meas.

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FIGURE 16.32

VHDL Theory Meas.

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10

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FIGURE 16.33

VHDL Theory Meas.

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These values have been derived by measuring the reference clock in front of the BPD on a test pin of the test chip and the output of the DCO in free-running condition. The values of the DCO period gain K T has been extracted from the measured tuning curves, as K T = [max(Tv ) − min(Tv )]/2, where max(Tv ) min(Tv ) are the maximum and minimum DCO clock period, respectively. For 4.8-GHz operation, K T = 6.1 ps, and for 2.2-GHz operation, K T = 5.4 ps. The loop filter latency D is 1.5 reference clock cycles. Figures 16.26 to 16.33 show the results of the comparison. In almost all cases the agreement between analytical model, simulation, and measurement is quite satisfying. The difference between measurements and the other two curves at low-frequency offsets is due to the increasing noise of the reference clock, which has not been modeled adequately. The only case where the analytical model fails to capture the real behavior of the BBPLL is for the case α = 2−9 and β = 2−8 for 2.2-GHz operation. Due to the small value of the ratio α/β, this case is quite close to the instability limit of the BBPLL and has little practical relevance.

REFERENCES 1. N. A. D’Andrea and F. Russo, “A binary quantized digital phase locked loop: a graphical analysis,” IEEE Trans. Commun., vol. 26, no. 9, pp 1355–1364, Sept. 1978. 2. S. C. Gupta, “Status of digital phase locked loops,” Proc. IEEE, vol. 63, no. 2, pp. 291–306, Feb. 1975. 3. W. C. Lindsey and C. M. Chie, “A survey of digital phase-locked loops,” Proc. IEEE, vol. 69, no. 4, pp. 410–431, Apr. 1981. 4. J. R. Cessna and D. M. Levy, “Phase noise and transient times for a binary quantized digital phase-locked loop in white Gaussian noise,” IEEE Trans. Commun., vol. 20, no. 2, pp. 94–104, Apr. 1972. 5. H. Yamamoto and S. Mori, “Performance of a binary quantized all digital phase-locked loop with a new class of sequential filter,” IEEE Trans. Commun., vol. 26, no. 2, pp. 35–44, Jan. 1978. 6. C. A. Sharpe, “A 3-state phase detector can improve your next PLL design,” EDN Mag., Sept. 1976. 7. I. C. Hwang et al., “A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition,” IEEE J. Solid-State Circuits, vol. 31, no. 10, pp. 1574–1581, Oct. 2001. 8. W. T. Bax and M. A. Copeland, “A GMSK modulator using a  frequency discriminatorbased synthesizer,” IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1218–1227, Aug. 2001. 9. A. M. Fahim and M. I. Elmasry, “A fast lock digital phase-locked-loop architecture for wireless applications,” IEEE Trans. Circuits Syst. II, vol. 50, no. 2, pp. 63–72, Feb. 2003. 10. R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara, “Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process,” IEEE Trans. Circuits Syst. II, vol. 50, no. 11, Nov. 2003. 11. B. Staszewski et al., “All digital phase domain TX frequency synthesizer for Bluetooth radios in 0.13um CMOS,” in ISSCC Digest of Technical Papers, 2004.

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12. B. Staszewski et al., “Time-to-digital converter for RF frequency synthesis in 90 nm CMOS,” in Proc. RFIC Symposium, 2005. 13. N. Da Dalt, E. Thaller, P. Gregorius, and L. Gazsi, “A low jitter triple-band digital LC PLL in 130 nm CMOS,” in Proc. ESSCIRC, 2004. 14. ——, “A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1482–1490, July 2005. 15. N. Da Dalt et al., “A 10bit 10GHz digitally controlled LC oscillator in 65nm CMOS,” in ISSCC Digest of Technical Papers, 2006. 16. T. Pittorino et al., “A UMTS-compliant fully digitally controlled oscillator with 100MHz fine-tuning range in 0.13mu CMOS,” in ISSCC Digest of Technical Papers, 2006. 17. R. Tonietto, E. Zuffetti, R. Castello, and I. Bietti, “A 3MHz bandwidth low noise RF all digital PLL with 12ps resolution time to digital converter,” in Proc. ESSCIRC, 2006. 18. A. V. Rylyakov et al., “A wide power-supply range (0.5V-to-1.3V) wide tuning range (500 MHz-to-8 GHz) all-static CMOS AD PLL in 65nm SOI,” in ISSCC Digest of Technical Papers, 2007. 19. N. Da Dalt, “A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs,” IEEE Trans. Circuits Syst. I, vol. 52, no. 1, pp 21–31, Jan. 2005. 20. N. Da Dalt, “Markov chains-based derivation of the phase detector gain in bang-bang PLls,” IEEE Trans. Circuits Syst. II, vol. 53, no. 11, pp. 1195–1199, Nov. 2006. 21. A. Weinberg and B. Liu, “Discrete time analyses of nonuniform sampling first- and secondorder digital phase lock loops,” IEEE Trans. Commun., vol. 22, no. 2, pp. 123–137, Feb. 1974. 22. J. Holmes, “Performance of a first-order transition sampling digital phase-locked loop using random walk models,” IEEE Trans. Commun., vol. 20, no. 2, pp. 119–131, Apr. 1972. 23. C. M. Chie, “Mathematical analogies between first-order digital and analog phase-locked loops,” IEEE Trans. Commun., vol. 26, no. 6, pp. 860–865, June 1978. 24. H. Risken, The Fokker–Planck Equation: Methods of Solutions and Applications. New York: Springer-Verlag, 1998. 25. H. Meyr and G. Ascheid, Synchronization in Digital Communications. New York: Wiley, 1990. 26. A. Papoulis and S. U. Pillai, Probability, Random Variables and Stochastic Processes. New York: McGraw-Hill, 2002. 27. H. Meyr, M. Moeneclaey, and S. A. Fechtel, Digital Communication Receivers. New York: Wiley, 1998. 28. Y. Choi, D. K. Jeong, and W. Kim, “Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery,” IEEE Trans. Circuits Syst. II, vol. 50 no. 11, Nov. 2003. 29. R. C. Walker, “Designing bang-bang PLLs clock and data recovery in serial data transmission systems.” In B. Razavi, Ed., Phase Locking in High-Performance Systems. Piscatecory, NJ: IEEE Press, 2003.

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Low-Power Spectrum Processors for Cognitive Radios JOY LASKAR and KYUTAE LIM Georgia Tech, Atlanta, Georgia

17.1

INTRODUCTION

Under the current license-based spectrum policy, it becomes more difficult to keep up user demand for better connectivity and higher data rate. Many spectrum segments, such as cell-phone band, are now crowded by big user groups, whereas other spectra are seldom used. Thus, advances in wireless technology have been urged to create a new wireless communication system to use spectrum more efficiently than in the past. Cognitive radio (CR) technology has been proposed as a promising solution for improving the efficiency of spectrum use by adopting a dynamic spectrum resource management concept [1–3]. The CR system is promising not only because it may improve the efficiency of spectrum use, but also because it promises improved connectivity and self-adaptability of channel environment. There are distinctive movements in standardization groups to adopt the CR concept. Figure 17.1 is a road map of CR-based wireless applications for flexible use of spectrum for various applications. In November 2008, the U.S. Federal Communications Commission (FCC) approved the unlicensed use of white space, which enforces new ways of spectrum policy by letting secondary users use locally unused TV spectrum as broadband wireless communication services [3]. IEEE 802.22 wireless regional area network (WRAN) is being developed to provide broadband data communication service in rural areas by using locally unused digital television (DTV) spectrum [4]. In Europe and Japan, ultrawideband–based personal area network (PAN) systems should have detect-and-avoidance (DAA) function to minimize the interference to WiMax and potential 4G services. The IEEE 802.16h group is also developing standards for a license-exempt band. The concept of cognitive radio network is not just about sharing spectrum, but more about how to connect people by managing radio resources intelligently. IEEE 802.11k and h are standards for improving radio resource management capability, such as transmitter power control and radio resource redistribution. Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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FIGURE 17.1

Road map of cognitive radio wireless communication applications.

IMT-Advance, considered the fourth-generation international wireless standard, has been moving to enable an all-IP network, which supports 100 Mbps and 1 Gbps for mobile (terminal can move while in use) and nomadic access (terminal may move but is stationary while in use), respectively. To achieve the goal, many innovative physical-layer technologies, such as multiple input and multiple output (MIMO) and orthogonal frequency-division multiple access (OFDMA), are expected to be adopted. To build such a complicated system in a small form, factored with low cost, and low power consumption, the innovation in a radio-frequency (RF)/analog front end must be supported. In this chapter, the new trend in front-end design for future wireless communication is presented. In Section 17.2, the paradigm shift from software-defined radio (SDR) to CR is discussed, followed by describing the efforts to overcome excessive signalprocessing burden for future wireless systems by analog signal processing in Section 17.3. After research efforts on CR are presented in Section 17.4, the challenges and trends of RF front ends are summarized in Section 17.5. 17.2

PARADIGM SHIFT FROM SDR TO CR

Software-defined radio (SDR) is a radio communication system that can tune to any frequency band and transmit or receive any modulation across a large frequency spectrum by means of programmable hardware. CR is a wireless communication in which either a network or a wireless node changes its parameters to improve connectivity and/or throughput efficiently by the active monitoring of a radio environment, such as radio-frequency spectrum, user behavior, and network state.

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CHALLENGE AND TRENDS IN RFIC/SYSTEM Cognitive Radio PHY/Network

Bandwidth

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CR TRX

Monitor & Adapt to Radio Enviroment

Digital RF / IF

Multi-Band Multi-CH-Bw Multi-band

Super Heterodyne

SDR PHY

single-band

Intelligence

FIGURE 17.2 Road map of RF front-end technology to meet the demand of wireless communication evolution.

Figure 17.2 shows the evolution of RF front ends (RFEs). The driving force for the RFE evolution comes from wireless system demands. For example, the multiband/multi-mode system let the direct conversion receiver take over the superheterodyne. The same kind of innovation is still needed to realize the cost and power effectiveness of SDR-based receivers for commercial application. The new paradigm of RFEs will be needed to support such a comprehensive and intelligent communication. One of the obvious differences from conventional RFEs is the ability to monitor the users’ environment, such as radio use, geolocation, and network usage. This type of functionality has been utilized for limited stand-alone application. However, the information from these new functions will be crucial in operating the CR network, so RFE should incorporate these functions in an integrated form. 17.3

CHALLENGE AND TRENDS IN RFIC/SYSTEM

1. New role of RFE for CR (a) Seamless support for the multi-band/multi-mode physical layer over a wide frequency range (b) Enabling multiple RF paths to accommodate MIMO architecture with a smaller form factor (c) Monitoring the spectral environment in an economical and robust way (d) Recognizing user location in an economical and robust way 2. Challenges in RFIC/system (a) Highly efficient linear transmitter (b) Multi-band/multi-mode support for receiver

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(c) High speed/high dynamic range of an analog-to-digital converter (ADC) (d) Leakage control in nano-scale device 3. New trend for RFE development (a) Linearized transmitter: polar, linear amplification with nonlinear components (LINC), digital predistortion for mobile terminal (b) Digital receiver with adaptive channel filtering (c) Digitally aided RFE: self-monitoring and adaptation/calibration for compensating in RF/analog mismatch using digital circuits (d) Direct digital frequency synthesis (DDFS) (e) Smart power management for improving system power efficiency 17.4

ANALOG SIGNAL PROCESSING

One of the key challenges in modern communication systems is the need for a vast improvement in the baseband signal processing capability. In particular, OFDM/OFDMA, spectrum sensing, geolocation, and high-throughput communication channels require large amounts of instantaneous signal processing. Moreover, computationally intensive technologies such as the MIMO system add significant challenges to an already strained baseband processing engine. Today’s approach to meeting these challenges is to utilize even more powerful digital signal processors (DSPs) in conjunction with high-resolution, high-spee ADCs. Figure 17.3 depicts the current road map of overall power consumption of signal processing blocks. Although dissipated power per instruction decreases rapidly (i.e., Gene’s law), the processing demands increase rapidly as system requirements increase, resulting in approximately constant overall power consumption. Future systems will need to implement cognitive, multi-purpose functionality with multiple antenna/RF channels that require even more comprehensive signal 10000000

Signal processing demand for system (MIPS)

100000 mW, MIPS, mW/MIPS

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10 0.1

Gene’s law (mW/MIPS)

0.001 0.00001 1998

2003

2008

2013

2018

Year

FIGURE 17.3 Road maps for Gene’s law, signal processing demand, and total system power consumption.

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Demand of future system: Cogntive/ Multiple Antena

100000 Power Consumption [mW]

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1000 100 10 1 1998

System power consumption: ISSP

2003

Sub-threshold design

2008 Year

2013

2018

FIGURE 17.4 Additional system demands due to increasing system complexity. Analogbased signal processing can be used to meet the power and performance requirement.

processing capability. To overcome the fundamental problem related to the requirement for excessive signal processing, analog and mixed signal circuit technology can be used. The concept of analog signal processing is to perform signal processing before an ADC. Figure 17.4 depicts this road map, which exhibits a quite linear increase in power consumption that accounts for the cognitive revolution. It is fundamentally different from other current technologies in that computationally intensive signal processing operations are performed in the RF/analog domain before any ADC. The key advantage of this approach is a reduction of both computational time and power consumption. As a result, the DSP can be used more effectively by reallocating part of the time/power-consuming operations into the analog-based signal processor.

17.5 17.5.1

SPECTRUM SENSING Spectrum Signal Processor Demand

The spectrum-sensing technique is a key functionality for identifying the spectrum usage status over a wide frequency range covering various communication standards. Its most critical performance requirements are the accuracy and processing time of spectrum sensing. Moreover, low power consumption and simple implementation are desired from the commercialization viewpoint of CR systems [4]. So far, various spectrum-sensing methods have been proposed [5]. They can be categorized into two groups: energy detection and feature detection. Energy detection works like a spectrum analyzer. It enables faster sensing speed and simpler implementation than feature detection. However, as its sensing accuracy depends on the selection of the threshold level, the sensing threshold level should be chosen carefully

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considering its performance. Meanwhile, the feature detection method is designed to identify the corresponding signature features inherent in each signal modulation type. Its detection capability is usually higher than that of energy detection. However, this method requires longer processing time and excessive digital hardware resources accompanying large power consumption. For example, the IEEE 802.22 working group is developing a wireless regional area network (WRAN) standard based on CR technology utilizing TV broadcasting spectrum resources (i.e., VHF and UHF bands) [4]. A dual-stage spectrum-sensing scheme [6] was suggested to meet the requirements mentioned above. First, an energy detection method, the multi-resolution spectrum-sensing (MRSS) technique [7,8], takes a snapshot of the current spectrum usage pattern. Specifically, this MRSS technique identifies the occupancy of each spectrum segment in a fast but limited resolution. Subsequently, a feature detection method scrutinizes the candidate spectrum segments determined safe from the MRSS stage. This sensing stage ensures that no primary users are interfered with by detecting noise-level signal features that are unique for each modulation type.

17.6 17.6.1

MULTI-RESOLUTION SPECTRUM SENSING Windowing Effect

To eliminate the need for a tunable filter in a receiver chain, MRSS adopted the concept of windowing. Windowing is commonly used in discrete signal processing to reduce spectral leakage [9]. Among various windows, a Gaussian window has maximum localization between the time and frequency domains. It is expressed as 1 σ 1 =
t
ω = √ √ 2 2 2σ

(17.1)

where
t and
ω represent the signal’s energy spread in the time and frequency domains, respectively, and is the standard deviation of the Gaussian window. Although it has a maximum localization, infinite time is required to produce an exact Gaussian window. Therefore, other time-confined windows, such as the Hann or Hamming window, are frequently used. In the case of the Hann window,
t
ω equals 0.5131 [10]. The virtue of this localization is that the bandwidth of the window can be adjusted only by changing the duration of the window. Having a lowpass characteristic, the cutoff frequency of the window is inversely proportional to the duration of the window. Figure 17.5(a) shows various cosα (π f w t) windows in the time domain, where α is the order of the window and f w is the window frequency, which is the same as the inverse of the duration of the window. Figure 17.5(b) is the log-scale magnitude

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(a)

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(b)

FIGURE 17.5 Various cosα (π f w t) window characteristics (a) in the time domain and (b) in the frequency domain. TABLE 17.1 Figures of Merit for the cosα (π fw t) Window Window cos(π f w t) cos2 (π f w t) cos3 (π f w t) cos4 (π f w t)

Highest Sidelobe (dBc)

Equiv. Noise BW (Hz)

3-dB BW (Hz)

6-dB BW (Hz)

−23 −32 −39 −47

1.23 f w 1.50 f w 1.73 f w 1.94 f w

1.20 f w 1.44 f w 1.66 f w 1.86 f w

1.65 f w 2.00 f w 2.32 f w 2.59 f w

response in the frequency domain when the windows. When α is 2, it is usually called the Hann window. As f w is increased from 100 kHz to 1 MHz with the same α = 2, the duration of the window is decreased from 10 µs to 1 µs, and the bandwidth of the modulated window is increased tenfold. Table 17.1 summarizes the figures of merit of various cosα (π f w t) windows. Among them, equivalent noise bandwidth shows the width of an ideal rectangular filter of the same peak gain that would accumulate the same noise power with the window. As α is increased, the sideband fall-off becomes more rapid, meaning that the selectivity is improved with the expense of a slightly increased noise bandwidth [9].

17.6.2

MRSS Overview

The basic theory of MRSS is presented as follows. Let’s say that w(t) is one pulse of a modulated window, as defined in (17.2), where f c is the modulation frequency. y(t) is the convolution of w(t) and the incoming RF signal, r (t). Equation (17.4) is obtained with t=0 in (17.3). It shows that time-domain multiplication of the RF signal and modulated window is the same as the bandpass-filtered RF signal by the

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bandpass characteristic of the modulated window. ⎧ ⎨cos4 (π f t) if − 1 < t < 1 w 2 fw 2 fw w(t) = ⎩ 0 elsewhere  y(t) =

1 r (s)w(t − s) ds = √ 2π −∞

 y(0) =

∞

∞

−∞

 r (s)w(−s) ds =

1 = √ 2π





∞

R(ω)W (ω)e jωt dω

(17.2)

(17.3)

−∞

1/(2 f w )

r (s)w(s) ds −1/(2 f w )

∞

R(ω)W (ω) dω

(17.4)

−∞

Figure 17.6 shows a possible functional block diagram of MRSS. The receiving path is split into in-phase and quadrature-phase path to eliminate the need for the synchronization process. A digital window generator (DWG) generates one pulse of a window with various waveform durations, 1/ f w . The broadband RF signal from the omnidirectional antenna is amplified with a low-noise amplifier (LNA). Then the amplified RF signal is down-converted to baseband by a mixer. The gain of LNA should be maximized to have a minimum noise figure of the system, but too large a gain will saturate the following multiplier, generating many unwanted harmonics. Therefore, an adequate gain control block is required before a multiplier. The analog correlator multiplies and integrates the amplified baseband signal and a window pulse. With adequate timing control, the integrated output is sampled and digitized to generate the bandpass-filtered amplitude information in in-phase and quadrature-phase components. A linearamplifier or a logarithmic amplifier can be

FIGURE 17.6

Functional block diagram of the MRSS system.

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placed in front of an ADC to maximize the dynamic range utilization of the ADC. The digitized result is further processed in the digital domain. The detected signal power can be processed in a logarithmic domain to have a processing gain over the Gaussian noise. There are many advantages of MRSS over existing energy detection methods. While conventional analog energy detectors require various filter banks to adjust resolution bandwidth, MRSS does not require any tunable filter components in the receiver path. The bandwidth can be easily adjusted just by changing the duration of the window. Therefore, if it is realized into the circuit, the area can be much smaller than the conventional energy detectors using filter banks. When compared with the digital energy detectors utilizing a wideband ADC to sample the signal and perform a fast Fourier transform (FFT) in the digital domain, MRSS does not require a wide-bandwidth, high-resolution ADC nor an FFT block. Therefore, the power consumption would be much smaller than the digital energy detectors. Moreover, there is no need to accumulate the signals to perform a FFT. Thus, the computation can be done in nearly real time [7,8]. Figure 17.7 shows the multi-resolution property of MRSS with two window frequencies, one with f w = 100 kHz and the other with f w = 1 MHz. The inputs to this simulation are a continuous wave (CW) signal of −50 dBm at 582 MHz, advanced television systems committee (ATSC) signal of −30 dBm at 600 MHz, and digital video broadcasting–terrestrial (DVB-T) signal of −70 dBm at 615 MHz. ATSC uses eight-level vestigial sideband (8-VSB) modulation, and DVB-T uses the orthogonal frequency-division multiplexing (OFDM) modulation scheme. The total required

FIGURE 17.7 Fine ( f w = 100 kHz) and coarse ( f w = 1 MHz) resolution property of MRSS using the cos4 (π f w t) window. Inputs are CW (−50 dBm @ 582 MHz), ATSC (−30 dBm @ 600 MHz), and DVB-T (−70 dBm @ 615 MHz).

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time in performing MRSS can be calculated as  ttotal =

  Navg f end − f start +1 f w + tsw f step Navg

(17.5)

where f start and f end represent the frequency sweep range of the local oscillator (LO), f step is the amount of frequency change in LO, Navg is the number of averaging in one LO frequency, and tsw is the maximum switching settling time of the LO. In Fig. 17.7, the LO frequency of MRSS is swept from 570 to 620 MHz with f step equaling f w . No averaging is done in this case. Therefore, when f w = 100 kHz, it will have 500 results, each representing the signal power detected at the given LO frequency. In the same way, 1 MHz will have 50 results. If tsw is assumed to be 10 µs, the total processing time is 10.02 ms and 561 µs for f w = 100 kHz and 1 MHz, respectively. From Fig. 17.7 it is evident that the duration change affects the resolution of MRSS. Coarse resolution gives only a glimpse of the spectral usage, but it can be done in a fast way. On the other hand, fine-resolution MRSS provides a more precise result as well as a reduced noise floor level. The level difference between the power detected and the input power of ATSC and DVB-T is due to the effective bandwidth of the window. The analysis of the effect of window frequency on the detection performance is dealt with in the following section.

17.7 17.7.1

MRSS PERFORMANCE System Analysis

The goal of spectrum sensing is to find whether or not the specific spectrum channel is occupied by primary users. Therefore, binary hypothesis testing with two hypotheses of (17.6) and two decisions of (17.7) can be used [11].

H0 :

channel is vacant

H1 :

channel is occupied

D0 :

channel is vacant

D1 :

channel is occupied

(17.6)

(17.7)

Three probabilities of interest are the probability of false alarm, Pfa , the probability of misdetection, PMD , and the probability of detection, PD . Pfa is the probability of deciding that the channel is occupied when it is actually vacant. On the other hand, Pmd is the probability of deciding that the channel is vacant when it is in fact occupied.

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In addition, PD is the desired detection probability when the signal is present. Pfa = P(D1 |H0 )

(17.8)

Pmd = P(D0 |H1 )

(17.9)

PD = 1 − Pmd

(17.10)

The occupancy decision is made by comparing the MRSS result and the predefined sensing threshold level, Pth . Too high a threshold will give a low false alarm, but the detection probability will decrease. On the other hand, too low a threshold would result in an increase in the false alarm rate. Therefore, the threshold level should be based on the acceptable false alarm rate, Pfa . For example, if the accepted false alarm rate is 0.1, the threshold level should be set to the point where Pfa reaches 0.1. As shown in (17.8), the false alarm rate is based on the MRSS result when there is no signal in the channel of interest. Therefore, the determination of the threshold level is affected by the MRSS result distribution on noise power detection. 17.7.2

Statistical Distribution of MRSS on Noise Power

The envelope voltage of white Gaussian noise has a Rayleigh distribution with its power density function (pdf) f v (v) as below in [12].  ⎧ 2  ⎨ v exp − v f v (v) = σ 2 2σ 2 ⎩ 0

if v ≥ 0

(17.11)

if v < 0

The envelope voltage is expressed in a logarithmic domain, especially on a decible scale. The new variable x = 20 log(v) would have a pdf f X (x), mean µx , and standard deviation σx , as shown in (17.12) to (17.14), respectively [13]. It is sometimes referred to as a log-compressed Rayleigh distribution. γ is the Euler–Mascheroni constant and about 0.5772.    x 1 x 2 2 exp − ln(2σ ) − exp − ln(2σ ) f X (x) = 10 log(e) 10 log(e) 10 log(e) (17.12) µx = 10 log σx =

2σ 2 exp(γ )

10π log(e) = 5.57 √ (6)

(17.13) dB

(17.14)

The way to reduce variation on the noise power detected is to average the individual detection results [12]. If this averaging is done in a logarithmic domain, the resulting pdf f X,avg (x), mean µavg , and standard deviation σavg obtained by averaging Navg

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independent measurements are  Navg Navg exp x − ln(2σ 2 ) f X,avg (x) = 10 log(e) 10 log(e)



Navg − exp x − ln(2σ 2 ) 10 log(e) µavg = 10 log

(17.15)

2σ 2 exp(γ )

10π log(e) 5.57 σavg = √ = Navg 6Navg

17.7.3



(17.16)

dB

(17.17)

Threshold-Level Determination

The threshold-level decision may begin with noise floor estimation. Let the inputreferred noise figure of the MRSS receiver path be NF on a decibel scale. The modulated window with a window frequency of will have an equivalent noise bandwidth of f NBW . Table 17.1 shows some f NBW values for cosα (π f w t) windows. The bandwidth f NBW is proportional to f w and a window-specific factor. The actual average power of the noise floor will be µ = −174 + NF + 10 log( f NBW )

dBm.

(17.18)

It is known that the signal processing of the envelope voltage of white Gaussian noise in a logarithmic domain causes an underresponse of −2.51 dB compared with the true noise power (see the appendix). If the result of MRSS is processed in a logarithmic domain, the noise power detected will have an underresponse of −2.51 dB. Therefore, the noise floor detected becomes µ = −174 + NF + 10 log( f NBW ) − 2.51

dBm.

(17.19)

Thus, the noise floor detected is a function of the system noise figure and the duration and shape of the window. Decreasing the duration of the window will increase the speed of MRSS but at the expense of the increased noise floor and decreased resolution. With the same duration of the window, the shape of the window will affect the noise floor detected, but the selectivity of the signal is affected as well because of its skirt characteristics.

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FIGURE 17.8 Histogram of MRSS results for noise power measurements with the cos4 ( pi f w t) window: case 1: f w = 100 kHz, Navg = 1; case 2: f w = 100 kHz, Navg = 10; case 3: f w = 1 MHz, Navg = 10. The calculated mean and standard deviation are: case 1: µ N = −113.62 dBm, σ N = 5.55 dB; case 2: µ N = −113.62 dBm, σ N = 1.74 dB; case 3: µ N = −103.63 dBm, σ N = 1.76 dB.

The averaged result of the noise power detected will have a pdf of (17.15). Therefore, the threshold level having a false alarm rate of Pfa can be found by calculating a cumulative density function of (17.15) and finding the point where it reaches (1 − Pfa ). For example, if the acceptable false alarm rate is 0.1, the threshold level can be calculated as 6.1265 pth ≈ µ N + Navg

dBm

(17.20)

Figure 17.8 shows the histogram of the detected noise power over diverse window frequencies and numbers of average. The wideband white Gaussian noise is generated with a power of −164 dBm/Hz, assuming the system noise figure of 10 dB. MRSS has simulated tests 200,000 times for each case. Therefore, the case of Navg has a total of 200,000 points, while that of Navg has a total of 20,000 points. A window of cos4 (π f w t) with f w = 100 kHz has been used, which is modulated to 594 MHz. The yaxis shows the number of occurrences over each 0.3 dB of power range detected. The distribution of the detected noise power complies with the log-compressed Rayleigh distribution. To check the validity of (17.17) and (17.19), the mean and standard deviation of each result is calculated. By comparing cases 1 and 2, the reduction of the standard deviation corresponds well to (17.17). The shift of the noise floor by 10 dB between cases 2 and 3 is due to a tenfold larger f NBW of case 3 than that of case 2.

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FIGURE 17.9 False-alarm-rate simulation with the cos4 (π f w t) window of f w = 100 kHz and various Navg .

Figure 17.9 shows the false-alarm-rate simulation result when the cos4 (π f w t) window with f w = 100 kHz is used. To find the false alarm rate, 200,000 independent MRSS results are gathered and averaged. At each threshold level, the number of averaged results that are larger than the threshold level is counted and normalized with the total number of averaged results, giving the false alarm rate at that threshold. As anticipated by (17.20), the larger the number of averaged results, the smaller the threshold level that satisfies a certain false alarm rate. Table 17.2 compares the theoretical and simulation results on the noise power distribution and threshold-level determination. The error is found to be negligible, so the validity of the theoretical model is confirmed.

TABLE 17.2 Comparison of Theoretical and Simulation Values on the ThresholdLevel Determination With the cos4 (π fw t) Window, fw = 100 kHz and PFA = 0.1.

µ (dBm) σ (dB)

Pth (dBm)

Navg

Theoretical Value from (17.20)

Simulation

Error (dB)

All 1 10 100 1000 1 10 100 1000

−113.63 5.57 1.76 0.57 0.18 −107.50 −11.69 −113.02 −113.44

−113.62 5.55 1.74 0.54 0.17 −107.40 −111.40 −112.80 −113.40

−0.01 −0.02 −0.02 −0.03 −0.01 0.10 0.29 0.22 0.04

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(a)

(b)

FIGURE 17.10 Probability of misdetection with the cos4 (π f w t) window having f w = 100 kHz with 600 MHz of LO frequency and various Navg = 1, 10, 100, and 1000. The input signal is (a) CW signal at 600 MHz and (b) ATSC signal at 600 MHz.

17.7.4

Probability of Misdetection

Once the threshold level is determined, the probability of misdetection can be simulated as shown in Fig. 17.10. In this simulation, the simulated threshold level in Table 17.2 is used as the sensing threshold level for each Navg . The window is fixed as a cos4 (π f w t) window with f w = 100 kHz and modulated to f c = 600 MHz. Figure 17.10(a) shows the case when the input is a CW signal centered at 600 MHz. The signal power is varied from −120 to −101 dBm. At each signal power, 10,000

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independent MRSS results are gathered and averaged with each Navg . As the number of averaged results is increased, the variance on the detected signal power is also reduced, so the probability of misdetection is also decreased. Figure 17.10 is when the input signal is modulated with 8-VSB according to the ATSC standard and upconverted to 600 MHz. The signal power shown in the x-axis is the total signal power over a bandwidth of 5.38 MHz. Figure 17.10 tells that with 100 averages, −113 dBm of a CW signal or −99 dBm of ATSC signal within f NBW = 194 kHz bandwidth can be detected with a probability of misdetection of 0.01. From (17.5), the total processing time would be 1 ms. The digitally modulated signals with random data having a symbol rate much faster than the resolution bandwidth of the window can be approximated to have a Gaussian distribution according to the central limit theorem. Therefore, the ATSC signal detected is also subject to the underresponse of −2.51 dB with logarithmic processing of MRSS. Thus, the signal power detected with an equivalent noise bandwidth of f NBW in the case of the digitally modulated signal which is fast enough will be µ D = ps − 10 log

f BW − 2.51 f NW

dBm

(17.21)

where µ D is the detected power, ps is the original signal power, and f BW is the signal bandwidth. In the case of the ATSC signal with the cos4 (π f w t) window having f w = 100 kHz, 

5.38 × 106 µ D = ps − 10 log 1.94 × 105

 = ps − 16.94

dBm

(17.22)

In the case of a CW signal, however, it is represented as a delta function in a frequency domain. Thus, the power detected is not altered by the equivalent noise bandwidth of the window, and the power detected itself is the signal power of a CW signal. By calculating the average of the data used for Fig. 17.10(b), the average of the detected power of the ATSC signal is within a 1-dB error of the value calculated from (17.22). This phenomenon can also be found in Fig. 17.7. When f w is increased tenfold, the detected power of a CW signal is constant, while that of ATSC and DVB-T signals are increased by approximately 10 dB. According to (17.22), the average power detected will be −46.94 dBm and −36.94 dBm for f w = 100 kHz and f w = 1 MHz, respectively. This is due to the tenfold increase in f NBW in (17.21). 17.7.5

Phase Noise Effect on the Threshold Level

To down-convert to the baseband the RF signal received, the RF signal should be mixed with a sine or cosine wave from a local oscillator. When there is no phase noise present at the output of LO, the frequency response of the window shown in Fig. 17.5(b) will be applied as the filtering characteristic of MRSS detection. In reality, however, noise from the oscillator’s building blocks and external noise make

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FIGURE 17.11 Phase noise effect on the window of cos4 (π f w t) = 100 kHz with 600 MHz LO frequency: case 1: when there is no phase noise; case 2: phase noise of −80 dBc/Hz at 20 kHz, −150 dBc/Hz at 6 MHz, and −170 dBc/Hz at 60 MHz; case 3: phase noise of −80 dBc/Hz at 20 kHz, −140 dBc/Hz at 6 MHz, and −160 dBc/Hz at 60 MHz.

the phase of the output of the oscillator noisy. These unwanted signals are expressed in decibles with respect to the carrier signal and referred to as phase noise [14]. Figure 17.11 shows the effect of phase noise on the MRSS detection characteristics. For this simulation, the cos4 (π f w t) window of f w = 100 kHz and LO frequency of 600 MHz is used. Case 1 is when there no phase noise is applied. Case 2 is when a phase noise of −80 dBc/Hz at 20 kHz, −150 dBc/Hz at 6 MHz, and −170 dBc/Hz at 60 MHz offset is applied, and case 3 is when a phase noise of −80 dBc/Hz at 20 kHz, −140 dBc/Hz at 6 MHz, and −160 dBc/Hz at 60 MHz offset is used. Once the phase noise is applied, the selectivity of the filter is degraded where phase noise presents. A 10-dB increase in the phase noise from case 2 to case 3 results in a 10-dB degradation on the selectivity of the filtering effect of the window. At the 6-MHz offset from the carrier, 594 MHz, the attenuation is about −100 dB and −90 dB for cases 2 and 3, respectively. This means that if there is a strong signal at 6 MHz apart from the LO frequency, that interference signal will be detected with the attenuation of −100 dB for the condition of case 2. Figure 17.12 shows the effect of phase noise on the threshold level with the presence of a strong interference signal nearby. In this simulation, the interference is located at 600 MHz, and the MRSS is done at 594 MHz. On each interference power, 10,000 independent results are recorded and averaged 100 times, and then the threshold level satisfying the false alarm rate of 0.1 is recorded. From Fig. 17.11, when the phase noise of −80 dBc/Hz at 20 kHz, −150 dBc/Hz at 6 MHz, and −170 dBc/Hz at 60 MHz offset is injected, the interference will be detected with approximately −100 dB attenuation. With the knowledge of −113.63 dBm of noise floor without phase noise injection from Table 17.2, we can anticipate that the signal

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FIGURE 17.12 Phase noise effect on the threshold level vs. interference power located 6 MHz apart from the MRSS detection frequency when Navg = 100. The simulation used the cos4 (π f w t) window of f w = 100 kHz with 600 MHz LO frequency with injected phase noise of −80 dBc/Hz at 20 kHz, −150 dBc/Hz at 6 MHz, and −170 dBc/Hz at 60 MHz offset (circles) and −80 dBc/Hz at 20 kHz, −140 dBc/Hz at 6 MHz, and −160 dBc/Hz at 60 MHz (squares).

having around −13.5 dBm will be reduced by the window to around −113.5 dBm, which is about the same power with the noise floor. When the noise power and the attenuated signal having equivalent power are combined, the noise floor detected will be 3 dB above the noise floor without an interferer, around −110 dBm. From (17.20), a theoretical threshold level with an average of 100 would be the noise floor detected plus 0.61 dB, about −109.4 dBm. This value matches with that of Fig. 17.12. When the interference power is below the noise floor plus the attenuation, the effect of interference is negligible within an error of 3 dB. A phase noise reduction of 10 dB results in a 10-dB increase in allowable interference power with the same thresholdlevel degradation. Therefore, once the desired system specifications on the maximum signal power and minimum sensing threshold are determined, the requirement for the phase noise of the local oscillator can be decided. 17.7.6

Circuit Implementation

Figure 17.13 shows the block diagram of our MRSS receiver, which has two operation modes: a spectrum sensing block as well as a receiver front end [7,8]. Its operating frequency is UHF band, from 470 to 862 MHz. In the receiver mode, the receiver block is configured as a direct-conversion receiver through an on-chip serial bus interface. The RF signal is received through the LNA, passive mixer, and eighth-order LPF with dc-offset cancellation block. In the receiver mode, all MRSS blocks are disabled to reduce power consumption. In MRSS mode, the RF signal is amplified by the LNA and down-converted to baseband by the mixer. The down-converted baseband signal

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FIGURE 17.13

551

MRSS receiver block diagram.

is then correlated with a window generated by the digital window generator (DWG), yielding the signal power within the band defined by the window bandwidth. All baseband filters are disabled for power-saving purposes. The analog correlator consists of a multiplier and an integrator as shown in Fig. 17.14. In the multiplier, the four upper transistors are functioning as source followers, transferring the input signal to the drain of the bottom transistors. These

FIGURE 17.14

Analog correlator architecture.

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FIGURE 17.15

DWG block diagrams.

four bottom transistors are biased in the triode region to produce the multiplication term Vgs · Vds [15]. From the simulation, the maximum input signal level of the multiplier was chosen to be 500 mVpp to ensure overall linearity. The measured multiplier output shows the multiplication of the window signal from the DWG and the downconverted sine wave at 1 and 2 MHz, respectively. The nonideal nature of the op amp results in an integrator response to have a pole above dc. The correlator simulation shows that this pole should be less than one-fifth of the window frequency, f w , to prevent the detection signal leakage [16]. The feedback capacitor value can be selected to adjust this nonideal pole position. An internal timing block generates reset signals after each correlation to initialize the integrator. Figure 17.15 is a block diagram of the DWG and its subblocks. The DWG is composed of RAM configured as four banks of 224 11b, an 11b DAC, and a LPF. The window duration can be changed by two methods: changing the RAM addressing increments or changing the clock frequency coming from the divider connected to an external crystal oscillator. The RAM address increment control block consists of serial latches and MUXs, producing low-order x-addresses, X[3:0]. These X[3:0] enable wordlines in the row decoder with high-order x-addresses. This method causes the wordlines to be enabled sequentially at desired increments. When SEQ is toggled, each, every second, and every fourth wordlines are enabled according to RES[1:0] values. The serial latch block is composed of latches and dynamic circuits. Delay cells

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FIGURE 17.16

553

DWG output examples.

are inserted in the serial latch to create sufficient delay for the next wordline-enable signal at each clock cycle. Figure 17.16 is a conceptual timing diagram of the DWG and measurement results, showing the cos4 (π f w t) window generated, f w being 25, 50, and 50 kHz, respectively. The DWG internal clock frequency can be changed from 4.8 MHz to 38.4 MHz, and the address increment can be 1, 2, or 4. A cos4 (π f w t) window was chosen because of

FIGURE 17.17

Window filtering characteristics.

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FIGURE 17.18

Comparison of (a) spectrum analyzer and (b) MRSS output.

its good sidelobe suppression property, but any other window can easily be employed using serial bus interface. To confirm that the entire MRSS chain operated correctly, the MRSS receiver was connected to an oscilloscope to collect the output data. To verify the window filtering effect, the input signal was set to generate a 603-MHz sine wave, and the PLL was swept from 600 MHz to 606 MHz. The window was generated by the DWG using 11b-quantized cos4 (π f w t) window data. As shown in Fig. 17.17, by varying the window frequency, f w , from 400 kHz to 100 kHz, the detection bandwidth was controlled without the burden of additional hardware. However, each window has a duration of 1/ f w , so the lower noise floor and narrower bandwidth are achieved at the expense of a longer correlation time.

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FIGURE 17.19

555

Die micrograph.

Figure 17.18 compares the MRSS response with that of a spectrum analyzer. An OFDMA-modulated signal with 7 MHz bandwidth and −35 dBm power at 609 MHz was combined with a −50-dBm sine wave signal at 603 MHz and input into the spectrum analyzer and the MRSS receiver. Figure 17.18(a) is from the spectrum analyzer with resolution and video bandwidth of 200 kHz. Part (b) shows the average of 100 independent MRSS measured results using a cos4 (π f w t) window with an f w of 100 kHz, having a theoretical equivalent noise bandwidth of 194 kHz. These two graphs show that the MRSS receiver can detect the rms power of an arbitrary signal within its detection bandwidth. The higher the number of output data sets averaged together, the lower the variation in the MRSS output. However, this improvement comes at the expense of a longer processing time. A spectrum-sensing energy detector integrated with a receiver was fabricated in a 0.18-µm CMOS technology. Its die micrograph is shown in Fig. 17.19. The die size is 4800 µm × 2400 µm. The MRSS receiver consumes about 180 mW for both receiver and MRSS modes with a 1.8-V supply voltage. The minimum detectable sensitivity is −74 dBm with a 32-dB dynamic range if a 100-kHz cos4 (π f w t) window is used. 17.8

CONCLUSIONS

In this chapter, the development direction for RF systems and ICs with regard to the realization of cognitive radio is presented. Various challenges exist for the realization of increasingly intelligent communications systems and networks. Of these, RF front ends will become the most important enabling technology. In the future, new functions that surpass existing RF transceiver functions (i.e., radio environment monitoring and geolocation) may be required, regardless of size or cost penalty. Because MIMO and OFDM/OFDMA technologies, as well as heterogeneous communication by spectrum sharing, will become generalized for future cognitive radio networks/systems, a level of signal processing capabilities beyond comparison to existing capabilities will be necessary. Low-power, high-speed analog signal processing employing analog/mixed circuit technology will be presented as a measure to overcome this challenge.

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REFERENCES 1. J. Mitola III, “Cognitive radio for flexible mobile multimedia communications,” in Proc. IEEE Int. Work-shop on Mobile Multimedia Communication, 1999. 2. S. Haykin, “Cognitive Radio: Brain-Empowered Wireless Communications,” in IEEE Journal on Selected Areas in Communications, vol. 23, no. 2, pp. 201–220, Feb. 2005. 3. http://hraunfoss.fcc.gov/edocs public/attachmatch/FCC-08-260A1.pdf 4. IEEE 802.22 Working Group on Wireless Regional Area Networks, “Functional Requirements for the 802.22 WRAN Standard.” [Online]. Available: http://www.ieee802.org/ 22/Meeting documents/2006 Nov/22-05-0007-48-0000 RAN Requirements.doc 5. A. Sahai, and D. Cabric, “T3 - Spectrum Sensing: Fundamental Limits and Practical Challenges,” in IEEE Dynamic Spectrum Access Networks (Dyspan) 2005, Technology Tutorials, Nov. 2005. 6. J. Benko, Y. C. Cheong, C. Cordeiro, W. Gao, C.-J. Kim, H.-S. Kim, S. Kuffner, J. Laskar, and Y.-C. Liang, “A PHY/MAC Proposal for IEEE 802.22 WRAN Systems,” Mar. 2006. [Online]. Available: http://www.ieee802.org/22/Meeting documents/2006 Mar/2206-0005-05-0000 ETRI-FT-I2R-Motorola-Philips-Samsung-Thomson Proposal.ppt 7. J. Park, T. Song, J. Hur, S. M. Lee, J. Choi, K. Kim, J. Lee, K. Lim, C.-H. Lee, H. Kim, and J. Laskar, “A Fully Integrated UHF Receiver with Multi-Resolution Spectrum Sensing (MRSS) Functionality for IEEE 802.22 Cognitive Radio Applications,” in Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, 2008, pp. 526–633. 8. J. Park, T. Song, J. Hur, S. M. Lee, J. Choi, K. Kim, K. Lim, C.-H. Lee, H. Kim, and J. Laskar, “A fully integrated UHF-band CMOS receiver with multi-resolution spectrum sensing (MRSS) functionality for IEEE 802.22 cognitive radio applications,” IEEE Journal of Solid-State Circuits, vol. 44, no. 1, pp. 258–268, 2009. 9. F. J. Harris, “On the Use of Windows for Harmonic Analysis with the Discrete Fourier Transform,” in Proc. of the IEEE, vol. 66, No. 1, Jan. 1978. 10. S. Qian and D. Chen, Joint Time-Frequency Analysis: Method and Application, New Jersey: Prentice Hall, 1996. 11. IEEE 802.22 Working Group on Wireless Regional Area Networks, “Spectrum Sensing Simulation Model.” [Online]. Available: http://www.ieee802.org/22/Meeting documents/ 2006 Sept/22-06-0028-10-0000-Spectrum-Sensing-Simulation-Model.doc 12. L. Nutting, J. Gorin, R. Cutler, D. Ballo, J. Gorin, B. Peterson, A. Moulthrop and M. Muha, “Spectrum Analyzer Measurements and Noise”, Application Note (AN) 1303, Agilent Technologies, Inc, Dec. 2006. 13. D. Kaplan and Q. Ma, “On the statistical characteristics of log-compressed Rayleigh signals: Theoretical formulation and experimental results,” in Journal of the Acoustical Society of America, vol. 95, iss. 3, pp. 1396–1400, Mar. 1994. 14. B. Razavi, RF Microelectronics, New Jersey: Prentice Hall, 1998. 15. G. Han and E. Sanchez-Sinencio, “CMOS transconductance multipliers: a tutorial,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, pp. 1550–1563, 1998. 16. J. Park, Y. Hur, K. Lim, C.-H. Lee, C. S. Kim, H. Kim, and J. Laskar, “Analog integrator and analog-to-digital converter effect on a Multi-Resolution Spectrum Sensing (MRSS) for cognitive radio systems,” in Microwave Conference, 2006. APMC 2006. Asia-Pacific, 2006, pp. 971–974.

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INDEX

Absolute delay, for reference/direct modulation point injection, 109 AC-coupling, in direct conversion receivers, 36 Accumulator, in DDS architecture, 51 ACLR degradation, 94–95. See also Adjacent channel power/leakage ratio (ACPR/ACLR) Active charge-sampling integrator, 211–212 Active core, losses in oscillator tank, 7 Active-Gm -RC cells, 19 Active integrator configuration, for transform-domain receivers, 193 Adaptive equalization, 315 Adaptive equalization algorithm, 311 least mean squares as, 312 Adaptive equalizer, 330–331 Adaptive feedforward error cancellation, 311–313 advantages of, 312 prior art related to, 313 Adaptive feedforward IM3 cancellation scheme, architectural concepts in, 313–320 Adaptive filtering, in calibrating SDR front ends, 26 Adaptive interference canceler (AIC), 478 Adaptive low-noise amplifier (LNA), in adaptive low-power RF circuit design, 67 Adaptive low-noise amplifiers/mixers, power consumption in, 68 Adaptive low-power RF circuit design, 66–67 Adaptively linearized UMTS receiver. See also Universal Mobile Telecommunications System (UMTS) experimental design of, 331–336 experimental results of, 336–341 Adaptive mixer, in adaptive low-power RF circuit design, 67 Adaptive multi-mode front-end circuits, 65–83 for image-reject down-converter, 76–80 multi-mode receiver concept for, 68–70

operation of, 65, 80 in RF front end design, 70–76 wireless RFIC design and, 66–68 Adaptive multi-mode RF circuit design, 67–68 Adaptive predistortion, 366–367, 420 Adaptive quadrature down-converter, experimental results for, 76–80 Adaptive voltage-controlled oscillators (VCOs) in adaptive low-power RF circuit design, 67 in multi-mode adaptive quadrature signal generation, 70 Adaptivity, 65 ADC closed-loop bandwidth, 266. See also Analog-to-digital conversion (ADC) ADC comparator, in SDR transceiver example, 57 Additive white Gaussian noise (AWGN) in frequency-offset estimation, 203 in TD receiver simulation, 208 Adjacent channel filtering, 335 Adjacent channel power/leakage ratio (ACPR/ ACLR), 85. See also ACLR degradation in feedback-based transmitter measurements, 152–153 Adjacent channel power ratio (ACPR), 351–352 in transmitter linearization, 46, 47 Adjacent channel selectivity test, 290–292 Adjustment factor [Adj(N)], 288–289 Advanced television systems committee (ATSC) signal, 541 Alignment. See Amplitude/phase modulation path alignments; Delay alignment; High-speed clock alignment; Multi-rate direct reference/point data modulation injection alignment; Reference/direct modulation point injection alignment; Subnanosecond amplitude/phase modulation path alignments; Time alignment effects; Time misalignment

Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Edited by Gernot Hueber and Robert Bogdan Staszewski C 2011 John Wiley & Sons, Inc. Copyright


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Alignment accuracy between amplitude and phase modulation paths, 91–96 between integer and fractional bits of amplitude and phase modulation, 93–94, 94–95, 95–96 All-digital phase-locked loop (ADPLL), 85–86 high-speed clock alignment in, 101 precise multi-rate direct/reference point data modulation injection alignment in, 101–109 for RF polar transmitters, 90, 91 for subnanosecond amplitude/phase modulation path alignments, 99 All-IP network, 534 Alternate channel power ratio (AltCPR), 351 Alternate feedforward path, error sources in, 316–320 Alternate feedforward path block design, 320–331 Alternate path analog baseband circuitry, 330 Alternate path baseband circuitry, 336 Alternate path circuit design, 336 Alternate path cubic term generator, 322–329 Alternate path enhancement, 322 Alternate path measurement results, 341 Alternate path mixer, 330 Alternative VCO-based quantizer structures, 250–251 AM/AM (AM-AM) distortion, 363, 366, 390–391 describing functions to treat, 445–446 measurement of, 402–403 Amplification for analog-to-digital conversion, 21 in signal processing, 220–221 in software-defined transceivers, 42–49 Amplifier frequency response, in feedforward receiver circuits, 129–131, 132, 133 Amplifier linearization, 364 Amplifier modeling, 476–477 Amplifiers, signal quality of, 46–47 Amplitude control word (ACW), 90 Amplitude distortion for higher-order-hold DACs, 179 of parallel-path converters, 182, 183 SDR DACs and, 173 Amplitude-encoded quadrature signals, for direct launch transmitters, 37 Amplitude feedback loop, 397 Amplitude mismatch (ε), in calibrating SDR front ends, 26 Amplitude modulation (AM), 382–383, 408, 467 alignment accuracy between phase modulation and, 93–94, 94–95, 95–96

with RF polar transmitters, 89, 90–96 subnanosecond alignment between phase modulation and, 96–101 Amplitude modulation paths alignment accuracy between phase modulation paths and, 91–96 delay alignment between phase/frequency modulation paths and, 85–111 Amplitude modulator closed-loop output impedance of, 400–401 linearity of, 389 output voltage of, 399 supply voltage of, 401 Amplitude/phase modulation path alignments fractional bits in, 93–94, 94–95, 95–96 subnanosecond, 96–101 Amplitude-to-amplitude modulation (AM/AM), 445 Amplitude-to-phase modulation (AM/PM), 445 AM-PM delay, WCDMA modulation and, 92, 93 AM-PM distortion, 90, 366, 390–392, 445 measurement of, 402–403 AM-PM effects, 356 AM-PM predistortion, 403, 404 Analog baseband circuitry, 335 Analog baseband/IF/RF parts, 454–456 Analog baseband signal processing, in adaptive low-power RF circuit design, 67 Analog circuits with delay-locked loop-based multipliers, 54 for flexible-baseband, 17–21 Analog correlator, 540 architecture of, 551–552 Analog delays, in alignment accuracy between amplitude and phase modulation paths, 91 Analog–digital solutions, 454 Analog filter bank in TD receiver complexity analysis, 207–208 for TD receivers, 204–205 Analog filtering, 283 Analog filters classes of, 220 in signal processing, 219, 220 Analog front-end complexity, in TD receivers, 204–205 Analog front-end components, optimizing, 469 Analog mixers, 427 Analog multiplier core, 428 Analog multipliers, 427–442 challenges associated with, 428–429 Analog path differences, 315

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INDEX Analog postfilter, 335 Analog power, current-steering DAC reconfigurability and, 176 Analog selectivity filtering, 469 Analog signal processing, 536–537 shortcomings of, 416–417 Analog-to-digital conversion (ADC). See also Analog-to-digital converters (ADCs) digital baseband estimators for multi-carrier signals and, 195–196 multi-mode, 68 for receivers, 35 for software-defined radio front ends, 21–23 for software-defined transceivers, 34 in TD receiver applications, 214–215 using VCO-based quantizers, 247–277 Analog-to-digital converters (ADCs), 411–412, 455–4S6. See also Analog-to-digital conversion (ADC) architecture for, 167–169 design requirements for, 159–160, 160–162 in digital deep-submicron CMOS, 189 in down-sampling, 231, 243 evaluating feasibility of, 161 high-dynamic-range, 282 hybrid, 172 in modern communications systems, 159 operating ranges of, 167 oscillator-based, 249–250 oversampled, 247–277 power and area overhead for, 166 in signal processing, 219 slope-based, 250 for software-defined radio, 159–186 topologies of, 166–167 VCO-based, 248–249 Analog varactors, implementing in circuits, 9–10 Antenna impedance, changes in, 420, 423– 424 Antennas, advances in, xiii Antialiasing, down-sampling and, 231 Antialiasing filter first-order, 254 in transconductor design, 239 Antialiasing prefilter, in single-balanced current-switching mixer, 224, 225 Application-level adaptability, in adaptive low-power RF circuit design, 67 Architecture. See also  architecture; Digital IF multi-step architecture; Pipelined architecture; Successive approximation architecture

559

charge redistribution, 21 of direct-conversion transmitters, 165 of direct digital synthesizers, 50–51 discrete-time, 86, 89–90 implementing wideband VCO, 9–10 multi-standard transceiver, 162–165, 184 SAR, 21–22 for software-defined radio front ends, 4–5 for software-defined transceivers, 34 wideband VCO, 7 Area overhead, 166 for ADCs in dual-mode GSM–WLAN transceivers, 166 ARM family processor, for single-chip polar transceiver radio, 86 Arrays, in Miller op-amp, 18–19. See also Capacitor arrays Asbeck, Peter, xi, 349 Asymmetric digital subscriber lines (ADSLs), digital baseband estimators for multi-carrier signals and, 196 ATSC standard, 548 Attenuation. See also Nyquist image attenuation (NIA) in feedforward receiver circuits, 130–131 filtering path and, 122 of RX band noise, 155–156 Autocorrelation coefficient simulation, 519–520 Autocorrelation function, 461 Automatic gain control (AGC) flexible baseband analog circuits and, 21 for software radio, 163 Average efficiency, 384–385 Average ET (AET), 357 Average output power, 403–405 Back-end circuits, in parallel transceivers, 162–163 Balun, 333–334 Balun negative terminal, 326 Band II transmitters, feedback-based measurements of, 151–152 Bandlimited transfer function, 324 Bandpass delta-sigma () modulator, 361 Bandpass-filtered RF signal, 539–540 Bandpass filters (BPFs), 154 feedforward notch filtering and, 133–134 phase noise and, 146, 147 quadrature phase and gain errors and, 144–145, 154 in transmitter stability analysis, 138–141 type I, 136–138, 138–141 type II, 136–138, 140, 141

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Bands, SDR power amplification and, 42 Band-split filtering, 478 Bandwidth for analog-to-digital conversion, 21 current-steering DAC reconfigurability and, 176 for direct launch transmitters, 40–41 of the envelope signal, 392–394 phase misalignment and, 414 Bandwidth expansion effects, 368 Bandwidth improvement in pipelined ADCs, 170–171 in successive approximation ADCs, 171–172 Bandwidth limitation, of the class S amplifier, 390 Bandwidth requirements, for ADCs and DACs, 159–160 Bang-bang PLLs (BBPLLs), 498. See also BBPLL entries; Digital bang-bang PLLs (BBPLLs) complete linear model of, 515–516 linearization of, 508–526 linear model for noise analysis, 516–518 Markov chain model of, 505–507 nonlinear dynamics of, 499–503 in the presence of noise, 503 simplified linear model for, 517 trajectory comparison for, 503 Barrel-shift DEM, using the VCO-based quantizer, 257–261 Baseband (BB) amplitude encoding, for direct launch transmitters, 37 Baseband amplitude signal, distortionless transmission of, 394 Baseband circuitry, selecting specifications for, 74 Baseband filter gain control, in SDR transceiver example, 57 Baseband signal processing, in adaptive low-power RF circuit design, 67 Baseband signal processing capability, improvement in, 536 Baseband signals, for direct launch transmitters, 36–37 Baseband transmitter block, in SDR transceiver example, 58–59 Base bias voltage, in LC-VCOs, 72 Base stations, in cellular organized systems, 38–39 Basis coefficients, computing TD, 191–192 Basis functions, transform-domain receivers and, 190–191 Battery life, transmitter efficiency and, 46 BB/IF filters, 456 BBPLL analysis, with Markov chains, 503–508 BBPLL stability, conditions for, 500–502

Bias current, in LC-VCOs, 72 Bias-current sources, in LC-VCOs, 71 Bias voltages, 296 Binary-phase detector (BPD), 498, 510–511. See also BPD entries linearized model of, 509–513 Binary search algorithm, for successive approximation ADCs, 171 Binary-weighted cascode transistors, for pre-power amplifier, 24–25 Binary weighted DACs, topologies for, 173 BiQuad filter, in SDR transceiver example, 57 Biquadratic sections, 19, 20 in Miller op-amp, 18 Bit error rate (BER), in TD receiver simulation, 209 Blind imbalance compensators, 473 Blocker cancellation, RF front ends with, 285 Blocker detection, 285 Blockers, 153 in feedforward receiver circuit implementation, 127, 129, 130–131, 132, 133 gain mismatch and, 122 I–Q imbalance and, 125 passive integration of front-end RF into systems-on-a-chip and, 114, 117 receiver translational loop and, 119–120 in signal processing, 219 in transconductor design, 240 Bluetooth adaptive multi-mode RF circuit design for, 67, 68 extended-data-rate, 85 with first-generation DRP, 103 Bluetooth receivers, 220 Bluetooth standard digital deep-submicron CMOS architecture and, 189 for input to low-noise amplifiers, 69 for TD receiver applications, 214 Bode plots, in transmitter stability analysis, 138–139, 139–140 Boltzmann’s constant, 235 Bondwires, for receivers, 13–14 BPD gain computation, for a first-order BBPLL in a closed loop, 511–513. See also Binary-phase detector (BPD) BPD noise, power spectral density expression of, 519–521 Branch filtering effects, 458 Brick-wall filter, 394 Broadband LO generation, in software-defined transceivers, 49–54

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INDEX Broadband power amplification technologies, in SDR power amplification, 43–44 Broadcasting, software-defined radio front ends for, 3 Broad operating range, for software-defined radio, 33–34 Brownian motion, 461 Buffer delays, high-speed clock alignment using, 100–101 Buffer design, 297–298 Buffer driver, 303 Building blocks in filter synthesis, 226 for software-defined radio front ends, 3 for software-defined transceivers, 34–54 transmitter, 148–150 Built-in self-test (BIST) for reference/direct modulation point injection, 109 for single-chip polar transceiver radio, 86 Butterworth-like selectivity, in lowpass filters, 19–20 Cadence SpectreRF circuit-simulation suite, noise analysis with, 236–237 Cafaro, Gio, xi, 33 Calibration, for direct conversion receivers, 36 Calibration algorithm, for TD receivers, 199–200 Calibration techniques, for software-defined radio front ends, 25–27 Candy structure, 265–266 Capacitance losses in oscillator tank and, 6–7 in transconductor design, 238 VCO sensitivity variations and, 8 Capacitance value, in wideband LC-VCO frequency tuning, 6 Capacitor arrays. See also Programmable capacitance array in Miller op-amp, 18–19 in transmitters, 150 Capacitor banks, in FIR filter synthesis, 230–231 Capacitors. See also LC entries in adaptive quadrature down-converter, 78 in analog-to-digital conversion, 22 in down-sampling, 231, 232–234 in FIR filter synthesis, 230–231 in IIR filter synthesis, 226–227, 228–229, 230 in Miller op-amp, 18–19 noise and, 235–236

561

in pipelined ADCs, 170 for receivers, 14 sampling, 417 in signal processing, 220 in wideband LC-VCO frequency tuning, 6 Carrier feedthrough, in direct launch transmitters, 37–38 Carrier phase modulation, 382 Cartesian baseband signals, for direct launch transmitters, 36–37, 40–41 Cartesian feedback, 365, 412–416 advantage of digital assistance to, 422 digital assistance for, 416–427 Cartesian-feedback-for-predistortion concept, design issues for applications of, 418–426 Cartesian feedback mixers, in SDR transceiver example, 54, 55 Cartesian feedback systems for quadrature modulator, 58–59 stability analysis for, 436–447 Cartesian format, in transmitter linearization, 47 Cascaded discrete-time integrators, in IIR filter synthesis, 227–229 Cascade gain stages, in transmitter stability, 49 Cascading integrators, for  ADCs, 167–168 Cascoded low-voltage transistors, 380 Cascode solution, 408 Cascode structure, 381 Cascode transistors in feedforward receiver circuit implementation, 126, 127, 128 for pre-power amplifier, 24–25 in transconductor design, 241 for wideband VCOs, 11, 14 CDMA-based systems, 351 CDMA power amplifier, AM-AM response of, 369 CDMA systems, power control in, 382 Cellular functionalities, software-defined radio front ends for, 3 Cellular organized systems, coverage design for, 38–39 Cellular telephones, as software-defined radios, 33 Channel estimation, 475–476 Channel filtering, for analog-to-digital conversion, 21 Channel interference, 468 Chapman–Kolmogorov (C-K) equation, 504, 507 Characterization, in calibrating SDR front ends, 25, 26

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Charge injection, in MOS switch scaling, 222 Charge packets, 224, 225 in FIR filter synthesis, 230–231 noise and, 236 in transconductor design, 239 Charge pump-based PLL, 497 Charge redistribution architecture, for analog-to-digital conversion, 21 Charge sampling op-amp gain–bandwidth product requirement and, 211–212 with transform-domain receivers, 191–192 Charge sharing, in analog-to-digital conversion, 22–23 Chebyshev filter, 335 Cherry–Hooper LO buffer, 334 Chopper stabilization, 429–430 as digital assistance, 430 for multipliers, 430–431 nested, 432–433 in SDR transceiver example, 57, 58 Chopper-stabilized multiplier output from, 431 performance limits of, 431–432 Chopper-stabilized multiplier prototype, measurement results from, 433–435 Chopping mixers, in SDR transceiver example, 55–56, 57–58 Chopping waveforms, with dc content, 431 Circuit design, for input transconductors, 237–241. See also Design requirements Circuit implementation, 550–555 for VCO-based quantizer, 267–275 for wideband VCOs, 9–10 Circuit-level challenges, for RF power amplifier integration, 378 Circular complex communications waveforms, 473–474 Circular random signal, 483 CKVD clock rates, 94, 97–100 with first-generation DRP, 103 in high-speed clock alignment, 101 with reference/direct modulation point injection alignment, 106–107, 108, 109 in subnanosecond amplitude/phase modulation path alignments, 97–100 Class AB amplifier, low-power, 408 Class E amplifier, 402 Class S amplifier, 389–390 Clipping amplifier, 464 Clock buffers, phase noise and, 146 Clock domains, for reference/direct modulation point injection, 109

Clock jitter, in transform-domain receivers, 193–194 Clocks. See also CKVD clock rates; Digital variable clock (CKV); DWG internal clock frequency; Frequency reference (FREF) clock; Retimed clock (CKR) for ADCs, 166 aligning high-speed, 100–101 in alignment accuracy between amplitude and phase modulation paths, 91, 92, 94 current-steering DAC reconfigurability and, 176 with digitally controlled oscillator, 85 in feedback-based transmitter measurements, 151 with parallel-path converters, 182 in RF polar transmitters, 88 in SDR transceiver example, 59 for single-chip polar transceiver radio, 86–87 in subnanosecond amplitude/phase modulation path alignments, 97–100 in successive approximation ADCs, 171–172 Clock tree delay, in alignment accuracy between amplitude and phase modulation paths, 91 Closed-loop poles determining, 440 in transmitter stability analysis, 140–141 CMOS architecture, digital deep-submicron, 189 CMOS DAC implementations, for wideband communication, 173, 179–181 CMOS logic levels, 268, 269 CMOS power amplifier (PA), pre-power amplifier and, 23 CMOS processes advanced, 247 circuit topologies and, 323 passive integration of front-end RF into systems-on-a-chip and, 113 in phase-locked loop design, 50 in SDR transceiver example, 54 CMOS RF power amplifiers, for mobile communications, 377–410 CMOS scaling, of MOS switches, 222. See also CMOS supply voltage scaling CMOS solution, 397 CMOS supply voltage, 408 CMOS supply voltage scaling, 378 CMOS (complementary metal-oxide semiconductor) technologies, 242, 243. See also High-speed CMOS in analog-to-digital conversion, 21, 22 class S amplifier and, 390 deep-submicron, 435–436

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INDEX for  ADCs, 168 digital circuits in, 411 in direct launch transmitters, 37 for feedforward receiver circuits, 129 flicker noise and, 36 low supply voltage and, 378–381 for receivers, 12–14 RF polar transmitters with, 87–90 in signal processing, 219, 220 SNDR limitations for VCO-based quantization and, 252 for software-defined radio front ends, 3 in software radio, 163, 164 for successive approximation ADCs, 171 CMOS transmission gates, in SDR transceiver example, 56, 57 Coarse carrier synchronization, 455 Coarse frequency tuning, for wideband VCOs, 9, 10 Code division multiple access (CDMA). See CDMA entries Cognitive radio(s) (CR) defined, 33 low-power spectrum processors for, 533–556 shift to, 534–535 Cognitive radio technology, 533 Cognitive radio wireless communication applications, 534 Common-gate amplifier, 153 Common-gate configuration in transconductor design, 241 for transform-domain receivers, 193 Common-gate design, in feedforward receiver circuit implementation, 126 Common-mode output voltage, 301 Common-mode phase fluctuations, 146–147 Common-mode rejection ratio (CMRR), 326 Common phase error (CPE), 468, 475 Communication devices, adaptive low-power RF circuit design for, 66–67 Communications systems, nonlinear distortion in, 463–466 Communication standards, for ADCs and DACs, 160–162 Comparator-based multi-level quantizers, metastability behavior of, 259 Comparator-based quantizer, VCO-based quantizer versus, 257 Comparator offset, 260–261 Comparators in analog-to-digital conversion, 21–22 in successive approximation ADCs, 171 threshold voltages for, 259

563

Compensation principle, 472–473 in calibrating SDR front ends, 25 Complementary cumulative distribution function (CCDF), 351, 352 Complete linear model, of the BBPLL, 515–516 Complex carrier, 460 Complexity analysis, for TD receivers, 206–208 Complex modulated signal, 358 Component arrays, in Miller op-amp, 18–19 Computationally intensive technologies, 536 Conductance, in MOS switch scaling, 221 Conjugate interference model, 471 Constant-envelope measurements, 402 Constant-envelope signals, efficiency versus output power for, 402 Continuous operation, of software-defined radio, 33 Continuous-time analog filters, in signal processing, 220 Continuous-time (CT) integration, VCO, 253, 254 Continuous-time  ADCs, 247. See also High-speed CT  ADC Continuous-time voltage-to-phase integrator, 248 Continuous wave (CW) signal, 541 Control bits, for wideband VCOs, 9 Controlled inductor designs, in wideband LC-VCO frequency tuning, 6 Convergent trajectory, 500 Conversion gain in multi-mode adaptive down-converter, 75 in transconductor design, 240 Converter output impedance, in current-steering DACs, 175 Converters, parallel-path, 182, 183 CORDIC algorithm, 87 with DRP ADPLL, 101 with RF polar transmitters, 90–91 in subnanosecond amplitude/phase modulation path alignments, 99 WCDMA modulation and, 92 Cornelissens, Koen, xi, 159 Corner frequencies control of, 242 in signal processing, 219, 220 Correctively distorted signals, 416 Cost-efficiency issues, for future radio systems, 453 Coupled-resonator filters, 283 Coverage, by cellular organized systems, 38–39 C++ simulator (CppSim), 263 Craninckx, Jan, xi, 3 Cross-correlation coefficient simulation, 520–521

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Cross-correlation computation, for reference/direct modulation point injection, 109 Cross-coupling, in delay-locked loop-based multipliers, 54 Crossover frequency, 438–440 Cross-point switches, in transmitter stability analysis, 138 Crosstalk attenuation, 457–458 Cubic predistortion circuits, 322–323 Cubic term generator(s), 323 block design for, 323–324 multi-stage receiver, 325–326 prior art in, 322–323 Cumulative distribution function (cdf), 506 Current-commutating mixer, in signal processing, 220 Current feedback control, 359 Current mirrors, in wideband down-conversion mixers, 17 Current-steering DACs. See also Digital-to-analog converters (DACs) performance limits of, 174–176 reconfigurability of, 176–177 topologies for, 173–174 Current steering technique, in LNAs, 14 Current-voltage characteristics, 354 Custom analog circuits, with delay-locked loop-based multipliers, 54 CW blocker amplitude, 338 CW signal, 548 D/A converters. See Digital-to-analog converters (DACs) DAC update rate, Nyquist images and, 178. See also Digital-to-analog converters (DACs) Da Dalt, Nicola, xi, 497 Darabi, Hooman, xi, 113 Data converters, with RFIC transceiver, 60 Dawson, Joel L., xi, 411 Dc content, chopping waveforms with, 431 Dc/dc converter, 359 Dc level feedback (DCFB) circuit, for pre-power amplifier, 24 Dc offset, 396 in calibrating SDR front ends, 26 in direct-conversion receivers, 315–316 Dc offset compensation loop, flexible baseband analog circuits and, 21 Dc offset correction circuitry (DCOC), in SDR transceiver example, 57 Dc offsets, in direct conversion receivers, 35–36

DCO noise model, 518 DCO period jitter, 518 DC power consumption, 388 DCS1800 standards, for input to low-noise amplifiers, 69, 70 DCS band, 281 DCS band transmitter leakage, 303 Decimation filter, 232, 233 DECT standards, for input to low-noise amplifiers, 69 Delay. See also Buffer delays; Delays excess, 269 phase mismatch and, 123 in the RF signal path, 441–445 WCDMA modulation and AM-PM, 92, 93 Delay alignment, between amplitude and phase/frequency modulation paths, 85–111 Delay alignment scheme with multiple clock domains, 97–100 for reference/direct modulation point injection, 108–109 Delay cells, 53 current drive level in, 268 in filter synthesis, 226 VCO, 251 Delay compensation, 396, 404, 405–407 Delay line for delay-locked loop-based multipliers, 53–54 in digital-to-time converter, 51, 52 Delay-locked loop (DLL)-based multipliers, for broadband LO generation, 53–54 Delays, in alignment accuracy between amplitude and phase modulation paths, 91, 92  architecture, 168, 181, 184. See also  entries for ADCs, 167–169 for hybrid ADCs, 172  modulators, 359, 361 Demanding mode adaptive quadrature down-converter in, 79–80 standards for, 69, 76 Derived phase error probability density function (pdf), 504. See also Probability density function (pdf, PDF) Describing functions, 445–446 Design requirements. See also Circuit design for ADCs and DACs, 159–160, 160–162 calibrating SDR front ends and, 25 Detect-and-avoidance (DAA) function, 533 Device selection, in linearization technology, 48

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INDEX Differential baseband inputs, in SDR transceiver example, 55 Differential broadband neutralized RF power amplifier, 49 Differential delay, 392 Differential inductors, 398 Differential-mode phase fluctuations, 146, 147–148 Differential output currents, in transmitters, 149 Differential-to-single-sided conversion, in transmitters, 150 Digital assistance for analog multipliers, 429–435 for Cartesian feedback, 416–427 chopper stabilization as, 430 effectiveness of, 433 Digital audio broadcasting (DAB), digital baseband estimators for multi-carrier signals and, 195–196 Digital bang-bang PLLs (BBPLLs) analysis techniques for, 497–532 measurement and model comparisons related to, 526–531 Digital baseband (DBB) circuitry, 335 Digital baseband design, for transform-domain receivers, 195–204 Digital baseband estimators, for multi-carrier signals, 195–196 Digital baseband/IF parts, 454–456 Digital baseband predistorters, 476 Digital baseband processor, for single-chip polar transceiver radio, 87 Digital baseband signal processing, in adaptive low-power RF circuit design, 67 Digital calibration, 429 Digital complexity analysis, for TD receivers, 206–208 Digital deep-submicron CMOS architecture, for receivers, 189 Digital delay adjust (DDA) block, 97, 98 reference/direct modulation point injection alignment and, 106 Digital frequency synthesizer, in SDR transceiver example, 59 Digital IF multi-step architecture, for DACs, 181–182 Digital integration, of front-end RF into systems-on-a-chip, 113–158 Digital-intensive RF front ends, advantages of, 189 Digitally assisted Cartesian feedback, strengths and weakness of, 426–427

565

Digitally assisted Cartesian feedback system, architecture for, 417–418 Digitally controlled crystal oscillator (DCXO) with RF polar transmitters, 89–90 for single-chip polar transceiver radio, 86 Digitally controlled oscillator (DCO), 85, 498–499 with DRP ADPLL, 102 with first-generation DRP, 104 in high-speed clock alignment, 101 impulse response of, 514 operation of, 85–86 with reference/direct modulation point injection alignment, 107 RF polar transmitter with, 88, 89–90 with second-generation DRP, 104 in subnanosecond amplitude/phase modulation path alignments, 99–100 with third-generation DRP, 105–106 Digitally controlled oscillator linear model, 513–514 Digitally controlled power amplifier (PA) circuit, in RF polar transmitter, 88 Digitally controlled pre-power amplifier (DPA) with DRP ADPLL, 102 in high-speed clock alignment, 101 operation of, 85–86 in RF polar transmitters, 88–90, 90–91 Digitally enhanced alternate path linearization, of RF receivers, 309–342 Digitally modulated signals, 548 Digital phase-locked loops (PLLs), 497–498 Markov chains in analyzing, 504–505 Digital polar transmitters envelope modulation schemes for, 85 precise delay alignment between amplitude and phase/frequency modulation paths in, 85–111 Digital postprocessing, 478 Digital power, current-steering DAC reconfigurability and, 176 Digital predistortion, 357 limitations of, 366–367 Digital processing technology, for direct launch transmitters, 37 Digital registers, for reference/direct modulation point injection, 109 Digital RF processor (DRP) ADPLL of, 101–109 phase modulation in first-generation, 103–104 phase modulation in second-generation, 104–105 phase modulation in third-generation, 105–106 Digital signal enhancement, 469–470

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Digital signal processing (DSP)-based solutions, 454 Digital signal processing chips, 411 Digital signal processors (DSPs) ADCs and DACs and, 159 current-steering DAC reconfigurability and, 176 in parallel transceivers, 162–163 powerful, 536–537 in software-defined radio, 164–165 Digital signal processing capabilities, integrating, xiii Digital subband tuning, 484 Digital television (DTV) spectrum, 533 Digital-to-analog conversion (DAC) in DDS architecture, 50, 51 in SDR transceiver example, 55, 57, 59 Digital-to-analog converters (DACs), 243, 269–270, 455 advanced techniques and implementation for, 181–184 connecting VCO-based quantizer outputs to, 258  ADCs and, 169 design requirements for, 159–160, 160–162 evaluating feasibility of, 161–162 in modern communications systems, 159 Nyquist images and, 177–178 pulse-shape-induced amplitude distortion and, 178–179 for software-defined radio, 159–186 successive approximation ADCs and, 171 topologies for high-speed CMOS, 173–177 Digital-to-frequency conversion (DFC), in RF polar transmitters, 88 Digital-to-RF-amplitude conversion (DRAC), in RF polar transmitters, 88–89 Digital-to-time converter (DTC), in DDS architecture, 51–52 Digital up-mixing, 181–182 Digital variable clock (CKV) with DRP ADPLL, 102–103 with first-generation DRP, 103 with third-generation DRP, 105–106 Digital video broadcasting-terrestrial (DVB-T) signal, 541 Digital video broadcasting–handhelds (DVB-H), adaptive multi-mode RF circuit design for, 67 Digital video broadcasting (DVB), digital baseband estimators for multi-carrier signals and, 195–196 Digital window generator (DWG), 540, 551. See also DWG entries

Direct conversion-based WCDMA, 279 Direct-conversion radio architectures, 468 statistical techniques for, 473 Direct conversion receivers, 34, 35–36, 550 DC offset in, 315–316 in SDR transceiver example, 55–58 Direct-conversion transceivers, 471 Direct-conversion transmitters, architecture of, 165 Direct digital frequency synthesizer, in SDR transceiver example, 59 Direct digital synthesis (DDS) in broadband LO generation in, 50–53 for direct launch transmitters, 40 Direct digital synthesizers (DDSs) architecture of, 50–51 in broadband LO generation in, 50–53 delay-locked loop-based multipliers for, 53–54 in SDR transceiver example, 54, 55, 59 Direct-launch transmitters in SDR transceiver example, 58–59 in software-defined transceivers, 36–42 Direct modulation, in direct launch transmitters, 42 Direct reference/point data modulation injection alignment, in ADPLL, 101–109 Direct-to-RF modulators, 182–184 “Dirty-RF” issues, 454 Discrete/continuous tuning scheme, in wideband LC-VCO frequency tuning, 6 Discrete-time architecture with RF polar transmitters, 89–90 for single-chip polar transceiver radio, 86 Discrete-time (DT) differentiation, VCO, 253, 254 Discrete-time, discrete-variable Markov chain theory, 504 Discrete-time filters, 242 synthesis of, 226–234 Discrete-time integrator in filter synthesis, 226 in IIR filter synthesis, 226–230 Discrete-time linear system, 513 Discrete-time noise process, 235–236 Discrete-time processing, of RF signals, 219–245 Distortion. See also Amplitude distortion; AM-PM distortion; Intermodulation distortion; Predistortion entries; Pulse-shape-induced amplitude distortion; Signal-to-noise-plus-distortion ratio (SNDR) AM-AM and AM-PM, 390–391 in current-steering DACs, 175–176 IM2 and IM3, 313

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INDEX in a polar-modulated power amplifier, 390–397 reducing, 48 signal, 471 in signal processing, 219 in TD receiver simulation, 209, 211 in transmitter linearization, 47 Distortion components, in-band and out-of-band, 464 Distortion curve, 397 Distortion products, 309 Distributed active transformer approach, 381 Distributed network, in SDR power amplification, 44 Distributed power amplifier, in SDR power amplification, 44 Distributed sensor relay, transform-domain, 215, 216 Dithering, in digital-to-time converter, 53 Divergent trajectory, 500 Divide-by-2 dividers in feedback-based transmitter measurements, 150–151 phase noise and, 146 Divide/multiply quadrature (DMQ), for wideband VCOs, 10–12 Dividers in feedback-based transmitter measurements, 150–151 phase noise and, 146 Doherty amplifier techniques, 355–357 Doherty power combiner, 356 Double-balanced mixer, for down-converter, 74–75 Double-sideband mixer, 386 Down-chop operation, 430 Down-conversion sample-rate, 231–234 with transform-domain receivers, 192–193 Down-conversion mixers. See also Harmonic down-conversion (HD) feedback-based transmitter noise and, 141–142 feedforward notch filtering and, 135 in feedforward receiver circuit implementation, 125, 127–128, 129 filtering path and, 122 gain mismatch and, 122 LNA noise figure degradation and, 124 phase mismatch and, 123 in RX band noise attenuation, 155–156 for transmitters, 148, 149 wideband, 16–17

567

Down-converted baseband signal, 550–551 Down-converted spectrum, 486 Down-converter circuits image-reject, 76–80 in multi-mode adaptive quadrature signal generation, 70, 73 receiver translational loop and, 119–120 selecting specifications for multi-mode adaptive, 73–76 standards for, 69, 70, 73–76 Down-mixer, in SDR transceiver example, 58–59 Down-sampling, 231–234, 243 Drain efficiency, 384 Drain–gate capacitance, losses in oscillator tank and, 8 Drain voltage, 392 Driver stage supply voltage, 388 DS-CDMA transmission, TD receivers and, 215 Dual-band low-noise amplifier (LNA), in receivers, 12–14 Dual-mode GSM–WLAN transceivers, power and area overhead for, 166. See also GSM (Global System for Mobile Communications); Wireless local area networks (WLANs) Dual-stage spectrum-sensing scheme, 538 Dummy squaring circuit, 326 Duplexer isolation, in passive integration of front-end RF into systems-on-a-chip, 117–118 Duplexers, 153 DWG block diagrams, 552. See also Digital window generator (DWG) DWG internal clock frequency, 553 DWG output, 553 Dynamic accuracy, in current-steering DACs, 175–176 Dynamic element matching (DEM). See also Implicit barrel-shift DEM for RF polar transmitters, 91 VCO-based quantizers and, 257 Dynamic matching mixers, in SDR transceiver example, 55–56 Dynamic power supply variation, 357–361 Dynamic range (DR) in ADC specifications, 161 in DAC specifications, 162 of signals, 34, 35 for software radio, 163 Dynamics, in the RF signal path, 441–445 Dynamic spectrum resource management concept, 533

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Edge combining method, with delay-locked loop-based multipliers, 54 EDGE measurements, 403–407. See also Enhanced data rates for global evolution (EDGE) EDGE modulation scheme, 85, 89, 91 for alignment accuracy between amplitude and phase modulation paths, 91–92, 93 with DRP ADPLL, 101 with reference/direct modulation point injection alignment, 106 EDGE output spectra, 403–404 EDGE PA, linearized, 401. See also Power amplifiers (PAs) EDGE receivers, passive integration of front-end RF into systems-on-a-chip and, 113, 114 EDGE signal, dynamic range of, 403 EER architecture, 387. See also Envelope elimination and restoration (EER) Effective loop transmission, 414, 437–438 system for determining, 442 Effective number of bits (ENOB), in analog-to-digital conversion, 22–23 Effective phase detector characteristic, 510–511 Efficiency enhancement, 385–386 power-amplifier, 354–362 Efficiency–linearity conflict, 387 Efficiency strategies, for next-generation wireless communications, 349–375 Encoding, for direct launch transmitters, 36–37, 40–41 Energy detection method, 537–538 Enhanced data rates for global evolution (EDGE), 279. See also EDGE entries Envelope amplifier bandwidth, 358 Envelope bandwidth, 405–407 Envelope detector, 397 Envelope dynamics, 465 Envelope elimination and restoration (EER), 355, 357–361. See also EER architecture transmitter efficiency and, 46 Envelope filter delay, 395 Envelope filtering, 392–396 Envelope following, transmitter efficiency and, 46 Envelope modulation schemes, 85 Envelope modulator, implementation of, 387–389 Envelope path bandwidth, 395 Envelope signal, 387 frequency components of, 394 Envelope tracking (ET), 355, 357–361, 385 Envelope tracking split-band amplifier, 360

Envelope voltage, 543 signal processing of, 544 Equivalent dc load resistance, 399 Equivalent input-referred jitter, 517, 518 Equivalent noise bandwidth, 544, 548 Error, in transmitter linearization, 47. See also Errors Error cancellation, adaptive-feedforward, 311–313 Error expressions, 437, 438 Error figure (EF), 321 Error-generating mechanism, 311 Error producer-to-noise ratio, 313 Error-producing signals, 311 Errors, in MOS switch scaling, 222 Error-to-noise ratio, 312–313 Error vector magnitude (EVM), 85. See also EVM degradation in transmitter linearization, 46–47 Error vector magnitude measurement, 353 ESD devices, for receivers, 13–14 Essential spectral width, 461 Estimators for multi-carrier signals, 195–196 transform-domain receivers and, 191 ETSI specifications, 406 Euler–Mascheroni constant, 543 EVM degradation, WCDMA modulation and, 92, 93, 94–95. See also Error vector magnitude (EVM) Exception handling, in subnanosecond amplitude/ phase modulation path alignments, 99–100 Extended-data-rate Bluetooth (BT-EDR), 85 False alarm rate, 543 simulation of, 546 Far-out sideband noise, in direct launch transmitters, 38 Fast Fourier transform (FFT), 541. See also Fourier entries digital baseband estimators for multi-carrier signals and, 195–196 in TD receiver complexity analysis, 207, 216 FDD-based WCDMA, 286. See also Frequency-division duplex (FDD) FDD standards, 310 FDD systems, 282 Feature detection method, 537, 538 Federal Communications Commission (FCC), 533 in radio spectrum management, 33 Feedback in linearization technology, 48 in transmitters, 48–49

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INDEX Feedback-based transmission effects of nonidealities in, 141–148 linearity requirements in, 143–144 noise requirements in, 141–143 phase noise requirements in, 145–148 quadrature phase and gain errors in, 144–145 RX-LO feedthrough and leakage in, 145 Feedback-based transmitter measurements, 150–153 Feedback-based transmitter stability analysis, 138–141 Feedback capacitor value, 552 Feedback divider, linear model of, 515 Feedback loops, 413 Feedback network, in SDR transceiver example, 55 Feedback path in feedback-based transmitter measurements, 151 linearity requirements of, 143–144 noise requirements of, 141–143 phase noise requirements in, 145–148 quadrature phase and gain errors in, 144–145 in transmitters, 149 Feedback system, for quadrature modulator, 58–59 Feed/forward, in linearization technology, 48 Feedforward approach, 365–366 Feedforward blocker, receiver translational loop and, 119 Feedforward blocker technique, 285 Feedforward current, 390–392 Feedforward distortion, 396 Feedforward error-canceling loop, 322 Feedforward linearization, 476 Feedforward loop choice of, 314–315 nonideal effects of, 122–125 Feedforward notch filtering, for WCDMA transmitter, 133–138 Feedforward receiver circuits experimental results from, 129–133 implementing, 125–129 Feedthrough, in direct launch transmitters, 37–38 Figure of merit (FOM) in ADC specifications, 161 in analog-to-digital conversion, 22–23 in DAC specifications, 162 software radio and, 163 Filter banks in TD receiver complexity analysis, 207–208

569

for TD receivers, 204–205 with transform-domain receivers, 191 Filtered complex envelope signal, 383 Filter gain control, in SDR transceiver example, 57 Filtering ADCs and DACs and, 159–160 for analog-to-digital conversion, 21 in calibrating SDR front ends, 26 in feedforward receiver circuits, 131–132 gain mismatch and, 122–123 of Nyquist images, 177–178 by receivers, 34–35 for WCDMA transmitter, 133–138 Filtering devices, 153–154. See also Filters Filtering requirements, for heterodyne transmitter, 165 Filters for  ADCs, 168, 169 SDR DACs and, 172–173 in signal processing, 219, 220 Filter synthesis, of discrete-time filters, 226–234 Fine frequency tuning, for wideband VCOs, 10 Finite impulse response (FIR) filters, 242–243, 312, 515 digital deep-submicron CMOS architecture and, 189 in down-sampling, 231–232, 234 noise generated in, 234, 236, 237 synthesis of, 226, 230–231 in transconductor design, 238 Finite OTA gain, in pipelined ADCs, 170 First-generation DRP, phase modulation in, 103–104. See also Digital RF processor (DRP) First-order antialiasing filter, 254 First-order BBPLL, BPD gain computation for, 511–513. See also Bang-bang PLLs (BBPLLs) First-order lowpass filter, 394, 395 First-order lowpass transfer function, 514 First-order noise-shaping, in VCO-based ADCs, 248–249 First-order ZC-DPLL, 504 Fixed-base station equipment, SDR power amplification for, 42 Fixed equalization, 315 Fixed-point oscillator tuning word (OTW) format, with reference/direct modulation point injection alignment, 107–108 FLASH ADC, 259, 260–261. See also Analog-to-digital conversion (ADC) multi-bit, 260

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FLASH quantizer multi-bit, 261 for  ADC, 257–261 Flat gain, in TD receivers, 198 Flexible baseband analog circuits, for software-defined radio front ends, 17–21 Flexible lowpass filters (LPFs), 19–20 Flexible op-amps, flexible baseband analog circuits for, 18–19 Flexible spectrum use, 484 Flicker noise. See also 1/f noise in direct conversion receivers, 36 in SDR transceiver example, 57 with transform-domain receivers, 192–193 Flip-flops (FFs) in subnanosecond amplitude/phase modulation path alignments, 97, 98 for wideband VCOs, 10–11 Fokker–Planck (F-P) equation, 505 Folding/folded transistors, in wideband down-conversion mixers, 16–17 Forward RF chain, in SDR transceiver example, 58, 59 Forward transfer function, in transmitter linearization, 47–48 Fourier series coefficients, 190–191. See also Fast Fourier transform (FFT) Fourier spectra, for transform-domain receivers, 195 Four-tap FIR filter, 230, 231 Fourth-order loop filter, 264 Fractional bits, of amplitude and phase modulation, 93–94, 94–95, 95–96 Fractional part of OTW (OTF), with reference/direct modulation point injection alignment, 107–108 Free-running oscillators, 460–461 Free-running oscillator spectrum, 462 Frequency-agile RF components, for mass-market applications, xiii Frequency-band-adjustable down-converter, 313 Frequency bands, of VCOs, 6 Frequency command word (FCW) format, 90 with reference/direct modulation point injection alignment, 107 with third-generation DRP, 105 Frequency-dependent I/Q imbalances, 471–472 Frequency-division duplex (FDD), 280. See also FDD entries; Frequency-domain duplex (FDD) operation Frequency-domain (FD) estimators, transform-domain receivers and, 191

Frequency-domain duplex (FDD) operation passive integration of front-end RF into systems-on-a-chip and, 115, 116 SDR power amplification and, 42, 43 of software-defined radio front ends, 4 Frequency domain model, of VCO, 253 Frequency-domain multiplication, for direct launch transmitters, 36–37 Frequency-domain PSD, 521. See also Power spectral density (PSD) Frequency-domain sampling, transform-domain receivers and, 190–191 Frequency extension, in broadband LO generation, 53–54 Frequency-independent imbalance, 474 Frequency-independent I/Q imbalances, 470–471 Frequency modulation (FM), for RF polar transmitters, 91. See also Phase/frequency (PM/FM) modulation paths Frequency offset, 268–269 in TD receiver simulation, 209, 210, 211 Frequency-offset estimation, for TD receivers, 199, 201–204 Frequency reference (FREF), for single-chip polar transceiver radio, 86 Frequency reference clock with DRP ADPLL, 102–103 with first-generation DRP, 103 with reference/direct modulation point injection alignment, 106, 107 Frequency response. See also Amplifier frequency response in down-sampling, 234 for wideband VCOs, 9–10 Frequency signal, VCO, 253 Frequency synthesizer, in SDR transceiver example, 59 Frequency tuning of VCOs, 6 of wideband LC-VCOs, 6 of wideband VCOs, 9 Front-end analog complexity, in TD receivers, 204–205 Front-end circuits adaptive multi-mode, 65–83 digital-intensive, 189 in parallel transceivers, 162–163 passive integration into systems-on-a-chip, 113–158 in software-defined radio, 164–165 Front-end passive filter, 266, 271 Full SDR implementation, front ends in, 27–29 Fully differential RF amplifier, 398

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INDEX Fully integrated linear amplitude modulator, circuit implementation of, 400 Future radio systems, RF impairment compensation for, 453–496 Gain filtering path and, 122 in SDR power amplification, 45 in wideband down-conversion mixers, 17 Gain and phase mismatch, 330–331. See also Gain mismatch Gain–bandwidth (GBW) product in Miller op-amp, 18 requirement for op-amp in charge-sampling circuit, 211–212 in TD receivers, 205 Gain blocks, in SDR power amplification, 43–44 Gain compression, 445 Gain control, variable, 243 Gain control block, 540 Gain error, 154 in feedback path, 144–145 in TD receivers, 198 Gain imbalance, I–Q, 125 Gain mismatch feedforward loops and, 122–123 in TD receiver simulation, 209 Gain settings for pre-power amplifier, 23 for wideband VCOs, 9–10 Gain stages in SDR power amplification, 44 in transmitter stability, 49 Gain switching, in LNAs, 14 Gate-drain capacitance, feedforward current through, 391 Gate electrode, in MOS switch scaling, 221 Gate length, in MOS switch scaling, 222 Gate-oxide transistor, 398 Gaussian minimum shift keying (GMSK) for RF polar transmitters, 91 for waveforms, 36 Gaussian noise. See Additive white Gaussian noise (AWGN); Wideband white Gaussian noise Gaussian reference jitter, 512 Gaussian window, 538 Gene’s law, 536 (G H G)−1 matrix sparsity of, 206, 207, 213–214 in TD receiver calibration, 200 in TD receiver complexity analysis, 206–208 Gilbert cell, in wideband down-conversion mixers, 16, 17

571

Gilbert cell multiplier, 326 Gilbert mixer RF-DAC and direct-to-RF modulators and, 183, 184 for transmitters, 149 Givens rotation, 319, 330 Global positioning system (GPS), adaptive multi-mode RF circuit design for, 67 Global positioning system receiver, 279 G matrix in TD receiver calibration, 200 in TD receiver complexity analysis, 207 Gold codes, 432 Grounding, for direct launch transmitters, 39 Group delays, 415, 441, 444 GSM (Global System for Mobile Communications). See also Dual-mode GSM–WLAN transceivers adaptive multi-mode RF circuit design for, 67 digital deep-submicron CMOS architecture and, 189, 190 direct launch transmitters for, 37–38 passive integration of front-end RF into systems-on-a-chip and, 113 SDR power amplification and, 45 software radio and, 163 GSM-EDGE, polar-modulated power amplifier for, 397–408 GSM-EDGE standard, 407 GSM/GPRS/EDGE (GGE) dual-mode system, 286 GSM receivers, FIR filters in, 232–234 GSM RF receivers, 220 GSM standard with first-generation DRP, 104 LNA noise figure degradation and, 124 with second-generation DRP, 104 for TD receiver applications, 214 GSM transmitter, passive integration of front-end RF into systems-on-a-chip and, 115 Hajimiri, Ali, xi, 309 Half-frequency FDD (HFDD), 280, 282. See also Frequency-domain duplex (FDD) operation Hammerstein model, 465 Hann window, 538, 539 Harmonic content, in SDR power amplification, 44–45, 45–46 Harmonic distortion, 463 Harmonic distortion products, 310, 478 Harmonic down-conversion (HD), feedback-based transmitter noise and, 142–143 Hessian jitter, 512

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Heterodyne receivers, 34–35 Heterodyne transmitter, filtering requirements for, 165 Heterodyne wireless handset transmitter, 350 Heterojunction bipolar transistor (HBT), 356 High-density capacitors, in signal processing, 220 High-dynamic-range RF ADC, 283. See also Analog-to-digital conversion (ADC) High efficiency, techniques to achieve, 385–386 high-efficiency envelope amplifier, 358, 359 Higher-order-hold DACs, 179. See also Digital-to-analog converters (DACs) Higher-order statistics-based techniques, 473 High frequencies, with delay-locked loop-based multipliers, 54 High-frequency component delay, 394 High-impedance transformation ratio, 379 Highly integrated GPS front end, for cellular applications in 90-nm CMOS, 299–305 High-order QAM alphabet, single-carrier modulation with, 466. See also Quadrature amplitude modulation (QAM) Highpass filter (HPF) gain mismatch and, 122 LNA noise figure degradation and, 125 phase mismatch and, 123, 124 receiver translational loop and, 119–120 High-pass filtering, 316 High peak-to-minimum signals, 358 High-Q bandpass filtering, for software-defined radio front ends, 4 High-Q bandpass filters feedforward notch filtering and, 134, 136, 137 phase noise and, 147 in transmitter stability analysis, 138–141 High-Q band-select filters, 284 High-resolution ADC, 261. See also Analog-to-digital conversion (ADC) Power supply considerations for, 261 High-speed clock alignment, using buffer delays, 100–101 High-speed CMOS. See also CMOS (complementary metal-oxide semiconductor) technologies software radio and, 163 topologies for DACs with, 173–177 High-speed CT  ADC, advantages of, 257–258. See also Continuous-time (CT) integration

High-speed DAC, architecture for, 181–182. See also Digital-to-analog conversion (DAC) High-speed multi-bit  ADC, design challenges of, 258 High-speed multi-phase VCO frequency measurement, 251 High-speed  ADC design, metastability of, 258–260 High-speed VCO quantizer structure, 251 Hold phase, of output voltage, 223–224 Hoyos, Sebastian, xi, 189 HPF time constants, 316 Hueber, Gernot, xiii Hybrid ADCs, 172 Hysteresis, 360 Hysteretic current feedback control, 359 ICI profile, 475–476. See also Intercarrier interference (ICI) Ideal linear-phase detector, 510 IIP2 performance summary, 304 IIP3 enhancement, 322. See also Third-order input intercept point (IIP3) IIP3 performance summary, 304 IIP3 specifications, 310 IIP3 test, 340 IIP3 turning range (IIP3TR), for down-converter, 74 IM2 distortion, 313 IM2-error-canceling alternate path, 313 IM2 products, 324 IM3 distortion, 313. See also Third-order (IM3) distortion IM3 distortion interference, 314 IM3 interference products, 313–314 IM3-producing signals, 313 IM3 products, 324, 327, 330, 338 IM3-to-error ratio, 317–318 IM3-to-noise ratio, 317–318 Image frequency, for receivers, 34–35 Image-reject down-converter, adaptive multi-mode front-end circuit for, 76–80 Image-rejection ratio (IRR) of adaptive quadrature down-converter, 78 for LC-VCOs, 73 Imbalance models, 471 Imbalance parameters, 472 Impaired signal spectrum, 461 Impairment mitigation principles, 469–470 Impairment mitigation task, 454 Impairment mitigation techniques, potential and opportunities associated with, 488

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INDEX Impairments, RF, 454–480 Impedance transformation network, 378–380 Imperfections, in TD receivers, 198–199 Implicit barrel-shift DEM, using VCO-based quantizer, 257–258. See also Dynamic element matching (DEM) Impulse responses, 458–459 feedforward notch filtering and, 135 of RF filtering path, 121 Impulse sensitivity function (ISF), losses in oscillator tank and, 7 IMS-producing blocker signals, 317 IMT-Advance wireless standard, 534 In-band blockers, passive integration of front-end RF into systems-on-a-chip and, 114 In-band blocking test, 289–290 In-band distortion components, 464 “In-band” mitigating techniques, 477 In-band noise, in current-steering DACs, 174–175. See also INR (in-band noise ratio) “In-band” problem, 459 Inductive degeneration, 296 Inductor quality, in broadband LO generation, 50 Inductors. See also LC entries in implementing VCO architecture, 9 in LC-VCOs, 71, 72–73 in phase-locked loop design, 50 in wideband LC-VCO frequency tuning, 6 Infinite impulse response (IIR), 315 Infinite impulse response filters, 242–243, 315 in down-sampling, 232–234 noise generated in, 234, 236, 237 synthesis of, 226–230 in TD receiver applications, 214–215 in transconductor design, 238 In-phase inputs, in SDR transceiver example, 55 In-phase signal component, 197 Input amplitude, SNR/SNDR versus, 273–274 Input impedance, 296–297 Input–output voltage conversion gain, in IIR filter synthesis, 227 Input-referred error, 337, 340 Input-referred error specification, 322 Input-referred noise power (PN+I), 287–288 Inputs, for LNAs, 14 Input signal, “error-free” amplification of, 365 Input transconductor circuits, design of, 237–241 INR (in-band noise ratio), 317, 323, 326–327. See also In-band noise INR performance, 341

573

Instability due to dynamics in the RF path, 414–416 due to phase misalignment, 413–414 Instantaneous nonlinear distortion, 464–465 Integer bits, of amplitude and phase modulation, 93–94, 94–95, 95–96 Integer part of OTW (OTI), with reference/direct modulation point injection alignment, 107–108 Integral non-linearity/differential non-linearity (INL/DNL) ratio, in analog-to-digital conversion, 22–23 Integrated inductors, in phase-locked loop design, 50 Integrated on-chip inductors, 398–399 Integrated transceivers, 377 Integration in charge-sampling circuit, 211–212 of front-end RF into systems-on-a-chip, 113–158 in TD receiver complexity analysis, 207 in TD receiver simulation, 208 for transform-domain receivers, 192–195 windowed, 191–192 Integrator cascade, for  ADCs, 167–168 Integrators continuous-time voltage-to-phase, 248 in IIR filter synthesis, 226–230 in transconductor design, 238 Intercarrier interference (ICI), 463, 475 Intercarrier interference distortion, 468 Interference in direct launch transmitters, 37, 38–39 due to nonlinear distortion products, 309–311 in-band and out-of-band, 461 self-generated, 309 Interference power, 549–550 Interference robustness, of receivers, 12 Interleaving in pipelined ADCs, 171 for transform-domain receivers, 194 Intermediate frequency (IF) filtering, 154. See also Digital IF multi-step architecture feedforward notch filtering and, 134–135, 136 receiver translational loop and, 119–120 Intermediate frequency signal for receivers, 34–35 standards for, 70, 74 Intermodulating blockers, power level of, 304 Intermodulation, 466 Intermodulation distortion, 394, 463–464 in transmitter linearization, 47

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Intermodulation distortion products, 478 Intermodulation intercept point (IPx), in transmitter linearization, 47 Interpolation methods, polynomial-based, 479 Interstage external filter, 286 Interstage gain, in IIR filter synthesis, 229–230 Interstage noise, 327 Intersymbol interference (ISI), 383, 419 I/Q calibration, transmitter, 480 I/Q imbalance (mismatch), 313, 456–459, 468 compensation principles in, 470–474 feedforward loops and, 125 impact and compensation performance in an LTE uplink, 485–487 I/Q imbalance compensation case studies of, 480–487 receiver, 482–483 I/Q imbalance effects, 459 IQ mixer design, 301–303 I/Q mixing, 456–457 I/Q mixing stages, 458 I/Q model, 471 I/Q operation of pipelined ADCs, 170 of quadrature modulator, 58 in SDR transceiver example, 59 in TD receiver simulation, 208 I/Q statistics techniques, 473 ISM band, 281–282 Jitter BBPLL, 503 equivalent input-referred, 517, 518 Hessian, 512 output, 522–526 sampling, 466–467 Jittered time instants, extracting, 479 Jitter mitigation, 479–480 Jitter noise, as white noise, 467 Jitter requirements, 467 Kahn transmitter, 387 Keehr, Edward A., xi, 309 Kimball, Donald, xi, 349 Laplace transform, 212 Large-constellation signals, 419 Larson, Lawrence, xi, 349 Laskar, Joy, xi, 533 LC-matched common-source (CS) LNAs, in receivers, 14, 15. See also Low-noise amplifiers (LNAs) LC (inductor-capacitor) tank, in VCOs, 71–72

LC-tuned oscillators, in broadband LO generation, 50 LC-VCOs. See also Voltage-controlled oscillators (VCOs) design of adaptive, 71 in integrated circuits, 6 Least-mean-squares (LMS) algorithm, in TD receiver calibration, 199–200, 208–211. See also LMS entries Least mean squares (LMS)-based adaptive equalizers, 312 Least significant bit (LSB), 171 in current steering DACs, 173, 174 Least-squares (LS) estimator in TD receiver calibration, 199–200 in TD receiver complexity analysis, 207 transform-domain receivers and, 191, 196–197 Least-squares model fitting, 472 Leff function, 438 License-based spectrum policy, 533 Lim, Kyutae, xi, 533 Limiter, 397 Linear amplifier, 540–541 Linear amplitude modulator, design and implementation of, 399–401 Linear and time-invariant (LTI) system feedforward notch filtering as, 135 receiver translational loop and, 121 Linear control of delta modulation (LCDM), 359 Linear feedback, 363–365 Linear feedback shift registers (LFSRs), 432 Linearity degradation, avoiding, 393–394 Linearity enhancement techniques, 362–371 Linearity improvement techniques, for polar-modulated power amplifiers, 396–397 Linearity limits, on current-steering DACs, 175–176 Linearity performance of adaptive quadrature down-converter, 78, 79 of flexible baseband analog circuits, 20–21 of multi-mode adaptive down-converter, 75–76 Linearity requirements, 390 of feedback path, 143–144 Linearity strategies, for next-generation wireless communications, 349–375 Linearization, 385–386 of the BBPLL, 508–526 transmitter, 46–48 Linearization bandwidth, 415 Linearization improvement, 420–422 Linearization strategies, power savings from, 425–426 Linearization techniques, 412

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INDEX Linearized BPD gain, 511 Linearized model, of the binary-phase detector, 509–513 Linearly modulated signals, 471 Linear model of the digitally controlled oscillator, 513–514 of the feedback divider, 515 for noise analysis, 516–518 Linear modeling, of the VCO-based quantizer, 252–254 Linear power amplifier, 349. See also Power amplifiers (PAs) Linear RF driver stages, 385 Linear term feedthrough, 316–317 Linear time-variant circuit analysis, losses in oscillator tank and, 7 Linear voltage regulator, transmitter efficiency and, 46 L-match impedance transformation network, 398 L-match network, 378–380 LMS-based adaptive equalizers, 331. See also Least mean squares entries LMS-based algorithm, 318 LMS equalization, 318–320 LNA design, 294–295, 300. See also Low-noise amplifiers (LNAs) LNA frequency response, in feedforward receiver circuits, 129–131, 132, 133 LNA gain settings, 295 LNA input matching, in feedforward receiver circuit implementation, 126, 127, 128 LNA input return loss, in feedforward receiver circuit implementation, 126, 127, 128 LNA noise figure degradation, feedforward loops and, 124–125 LNA to VGA measured performance, 299 Load, in transconductor design, 240 LO buffers, 330, 334–335, 336. See also Local oscillator entries Local area networks (LANs), software-defined radio and, 33 Local oscillator (LO), 542. See also LO entries Local oscillator feedthrough, 154. See also RX-LO feedthrough in direct launch transmitters, 37 Local oscillator generation, in software-defined transceivers, 49–54 Local oscillator phase noise, passive integration of front-end RF into systems-on-a-chip and, 114 Local oscillator signals, 458 for direct launch transmitters, 36–37 in feedback-based transmitter measurements, 151

575

feedback-based transmitter noise and, 143 feedforward notch filtering and, 134–135 for receivers, 34–35 receiver translational loop and, 120–121 for TD receivers, 196–197, 198–199 in TD receiver simulation, 209 in transconductor design, 240 Local oscillator synthesis, 3 for software-defined radio front ends, 5–12, 30 LO clocks, in feedback-based transmitter measurements, 151. See also Local oscillator entries LO divider, 297–298, 303 LO frequency, 542 for wideband VCOs, 11 Long term evolution (LTE). See LTE entries Look-up table (LUT) predistortion, 420–425 Look-up table training, 417, 420 Loop bandwidth, 412 Loop delay, 263–264 Loop filter, 272, 441 Loop filter op-amp, 271 Loop gain in RX band noise attenuation, 156 RX-LO feedthrough and leakage and, 145 in transmitter stability analysis, 140–141 Loop gain drops, in feedback-based transmitter measurements, 152 Loop transmission, 440–441, 443 effective, 437–438 LO signal feeding, 436 Loss factor in IIR filter synthesis, 227 interstage gain versus, 229–230 in transconductor design, 238–239 Lossless discrete-time integrator, in IIR filter synthesis, 226–227 Loss variations, in oscillator tank, 6–8 Lossy discrete-time integrator, in IIR filter synthesis, 226–230 Low-bandwidth applications, Cartesian feedback and, 415 Low-dropout (LDO) voltage regulators, for single-chip polar transceiver radio, 86 Low-frequency delta-sigma modulator, 361 Low-frequency model, 461 Low-IF principle, 469. See also Intermediate frequency (IF) filtering Low-IF radio architectures, statistical techniques for, 473 Low-IF transceivers, 471 Low-IF transmitter, 459 Low-jitter digitally controlled oscillator, 497

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Low-loss lowpass filter, 389 Low-noise amplifiers (LNAs), 154, 281, 293, 332–334, 540. See also LNA entries adaptive, 67 external, 299 in feedforward receiver circuit implementation, 125, 126–127, 128 for feedforward receiver circuits, 129–133 filtering path and, 122 gain mismatch and, 122 input standards for, 69 I–Q imbalance and, 125 passive integration of front-end RF into systems-on-a-chip and, 114, 115, 116 in receivers, 12–14, 14–16 receiver translational loop and, 120, 121 in SDR transceiver example, 55–56 with transform-domain receivers, 192 wideband, 14–16 wideband resistive feedback, 15, 16 Low-offset amplifiers, 429–435 chopper stabilization for, 430 Low on-resistance bypass switches, 19 Lowpass filters (LPFs), 154, 242. See also LPF spectral behavior in DDS architecture, 50, 51 feedforward notch filtering and, 134–136 flexible-baseband, 17–21 in RX band noise attenuation, 155–156 standalone flexible, 19–20 in transconductor design, 240 for transmitters, 148, 149 in transmitter stability analysis, 139–140 Low-power adaptive RF circuit design, 66–67 Low-power spectrum processors, for cognitive radios, 533–556 Low-power wireless RFIC design, adaptive multi-mode, 66–68 Low supply voltage, 378 solving for PA 380 LPF spectral behavior, in calibrating SDR front ends, 26–27. See also Lowpass filters (LPFs) LTE (long term evolution) base-station receiver, 485–487 LTE transmitters, with reference/direct modulation point injection alignment, 106 LTE uplink, I/Q imbalance impact and compensation performance in, 485–487 Main path circuit design, 332–336 Main path performance, 320 Markov chain model, of the BBPLL, 505–507

Markov chains BBPLL analysis with, 503–508 in digital PLL analysis, 504–505 Markov chain theory, application of, 508 Mass-market applications, frequency-agile RF components for, xiii Matching network, 378–380 efficiency of, 380 MATLAB postprocessing, 340 MATLAB tool, 331 matrix sparsity and, 213 for software-defined radio front ends, 5 in TD receiver simulation, 208 Matrices sparsity of, 206, 207, 213–214 in TD receiver calibration, 200 in TD receiver complexity analysis, 207 Maximum-likelihood (ML) estimator in TD receiver calibration, 199–200, 201–204 in TD receiver simulation, 209 Maximum oscillator frequency, VCO, 252 Memory effects, 367–371, 419–420, 421 in PAs, 446–447 Memoryless nonlinear functions, 464–465 Memoryless nonlinear phase detector linearization, 509–511 Memoryless PA nonlinearity, 445–446 MEMS-based RF filtering, 284–285. See also Microelectromechanical system (MEMS) switches MEMS-enabled dual-band low-noise amplifier (LNA), in receivers, 12–14 Metastability, of high-speed  ADC design, 258–260 Microelectromechanical system (MEMS) switches, in receivers, 12–14. See also MEMS entries Microprocessors, with RFIC transceiver, 60 Military communications, software-defined radio and, 33 Miller-compensated topology, 271 Miller op-amp, flexible baseband analog circuits for, 18–19 MIMO-OFDM systems. See also Multiple input and multiple output (MIMO) technology multi-antenna, 472 PAPR reduction in, 478 Minimum-mean-squared-error (MMSE) estimator, transform-domain receivers and, 191 Minor loop DAC, 270 Minor loop feedback, 272 Mirror-frequency attenuation, 457–458, 487

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INDEX Mirror-frequency components, cross-correlations of, 473–474 Mirror-frequency crosstalk, 459 Mirror-frequency interference, 472, 482 Misdetection, probability of, 547–548 Mismatches. See also Amplitude mismatch (ε); Gain mismatch; Phase mismatch (ϕ); Static mismatches; Transistor mismatch in TD receivers, 198–199 in TD receiver simulation, 208–209, 210 Mismatch-induced errors, in current-steering DACs, 175 Mismatch limitations, ADCs and DACs and, 159–160 Mitigation processing, receiver-side, 477 Mixed discrete/continuous tuning scheme, in wideband LC-VCO frequency tuning, 6 Mixed-signal dc offset compensation loop, flexible baseband analog circuits and, 21 Mixer circuits, for down-converter, 74–75, 76 Mixers, 334, 456 alternate path, 330 analog multipliers in, 427 design of, 295–297, 301–303 feedforward notch filtering and, 134–135 in feedforward receiver circuit implementation, 125, 127–129 in feedforward receiver circuits, 130–132 filtering path and, 122 gain mismatch and, 122 LNA noise figure degradation and, 124–125 phase mismatch and, 123 in RX band noise attenuation, 155–156 RX-LO feedthrough and leakage and, 145 in signal processing, 220 for transform-domain receivers, 192–195 Mobile communications, CMOS RF power amplifiers for, 377–410 Mobile terminals, increasing complexity of, xiii Mobile wireless equipment, user and application demands of, 66 Moderate mode, standards for, 69 Modes, SDR power amplification and, 42 Modulated signal, 429 accuracy of, 352 Modulation, role of, 467–468 Modulation schemes, 85. See also Amplitude modulation entries; Direct modulation; EDGE modulation scheme; Envelope modulation schemes; Frequency modulation (FM); Multi-rate direct reference/point data modulation injection alignment; Phase/frequency (PM/FM) modulation paths;

577

Phase modulation entries; Polar modulation format; Quadrature amplitude modulation (QAM); Reference/direct modulation point injection alignment; Remodulation entries; Second-order intermodulation (IM2) performance;  modulation; Subnanosecond amplitude/phase modulation path alignments; TETRA narrowband digital modulation; WCDMA modulation scheme; WiMAX modulation scheme; WLAN modulation schemes Modulator output, 262 Modulator unit cell, in transmitters, 150 MOM capacitors, in analog-to-digital conversion, 22 Monotonicity, 260–261 MOS (metal-oxide semiconductor) switches, 242 in analog-to-digital conversion, 22 in FIR filter synthesis, 230–231 in Miller op-amp, 18 noise generated in, 234–236 scaling of, 221–223 in signal processing, 220 MOS device transconductance, 323 MOSFETs, 411, 429, 430 MOS sampling switch, in transconductor design, 240 MOS squaring transconductor, 325–326 MOS transistors, 301 flicker noise and, 36 Most significant bit (MSB), 171, 172 in current steering DACs, 173 M-QAM systems, pulse shaping in, 419 MRSS detection characteristics, phase noise effect on, 549. See also Multi-resolution spectrum-sensing (MRSS) technique MRSS histogram, 545 MRSS performance, 542–555 MRSS receiver block diagram, 550–551 MRSS resolution, 542 MRSS system, functional block diagram of, 540 Multi-antenna waveforms, 468 Multi-band challenge, 281 Multi-band filtering blocks, in receivers, 12 “Multi-band, multi-mode” capability, 279, 280–283 Multi-band/multi-mode functionality, achieving, xiii Multi-band products, SDR power amplification for, 42 Multi-band receiver, research directions toward, 282–286

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Multi-band RF receiver, without preselect filters, 285–286 Multi-bit quantizers,  ADCs and, 169 Multi-bit VCO quantizer, 258 Multi-carrier modulations, 468 Multi-carrier OFDM signals, for TD receivers, 196–197, 203 Multi-carrier receivers, TD receivers versus, 204–208 Multicarrier waveform, 465 Multi-channel analog filter bank in TD receiver complexity analysis, 207–208 for TD receivers, 204–205 Multi-channel sinc filter bank in TD receiver complexity analysis, 207–208 for TD receivers, 204–205 Multi-channel transceiver, 469 Multifunctional receiver blocks, for software-defined radio front ends, 3 Multifunctional transmitter blocks, for software-defined radio front ends, 3 Multifunctional wireless devices, adaptive multi-mode RF circuit design for, 67 Multi-mode adaptive quadrature down-converter, selecting specifications for, 73–76 Multi-mode adaptive quadrature signals, generation of, 70–73 Multi-mode adaptive RF circuit design, 67–68 Multi-mode analog-to-digital converters, 68 Multi-mode challenge, 281–282 Multi-mode front-end circuits, adaptive, 65–83 Multi-mode/multi-band mobile terminals, 349 Multi-mode oscillator design, 70–73 Multi-mode products, SDR power amplification for, 42 Multi-mode receivers, 68–70 Multi-mode RF front-end circuits, adaptivity to, 69 Multiple circuits, implementing multi-standard modules as, 68 Multiple clock domain delay alignment scheme, 97–100 Multiple input and multiple output (MIMO) technology, 534. See also MIMO-OFDM systems Multiple-input, multiple-output (MIMO) transmission schemes, 468 Multiplexers, in wideband VCOs, 11 Multipliers, 427–429 chopper stabilization for, 430–431 delay-locked loop-based, 53–54 digital assistance for, 429–435 Multi-rate direct reference/point data modulation injection alignment, in ADPLL, 101–109

Multi-resolution spectrum-sensing (MRSS) technique, 538–542. See also MRSS entries advantages of, 541 basic theory of, 539–542 multi-resolution property of, 541–542 required time in performing, 542 statistical distribution of, 543–544 Multi-section gain stages, in SDR power amplification, 44 Multi-stage cubic term generator, 323 quantitative theoretical performance of, 326–329 Multi-stage receiver cubic term generator, implementation of, 325–326 Multi-standard communications, OFDM transform-domain receivers for, 189–217 Multi-standard modules, implementing, 67–68 Multi-standard receiver, software-defined radio, 214–215 Multi-standard transceivers ACD/DAC requirements for, 160–161 architectures of, 162–165, 184 Multi-tone input signals, 47 Nanoscale CMOS, RF polar transmitters in, 87–90. See also CMOS (complementary metal-oxide semiconductor) technologies Narrowband approximation, 444–445 Near-Nyquist input, in analog-to-digital conversion, 22–23 Negative frequency rejection (NFR), in calibrating SDR front ends, 26 Negative resistance, losses in oscillator tank and, 6–7, 8 Nested chopper stabilization, 432–433 Neutralization, in transmitter stability, 49 Neutralized RF power amplifier, 49 Next-generation wireless communications, linearity and efficiency strategies for, 349–375 NF tuning range (NFTR), for down-converter, 74 Nikoli´c, Borivoje, xi, 219 900-MHz transmitter prototype, 420 90-nm CMOS cellular applications, highly integrated GPS front end for, 299–305 NLMS equalizers, 331. See also Normalized-LMS (NLMS) algorithm NMOS gates, in Miller op-amp, 18, 19 NMOS input pairs, in wideband down-conversion mixers, 16–17 nMOS switch, gate-drain capacitance of, 396. See also nMOS transistor switches nMOS transistor drain, 392

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INDEX NMOS transistors flicker noise and, 36 losses in oscillator tank and, 8 in low-band LNAs, 16, 17 nMOS transistor switches, in single-chip polar transceiver radio, 86 Noise, 154. See also Jitter noise; Quantization noise; White noise in adaptive quadrature down-converter, 78, 79 ADCs and DACs and, 159–160 BBPLL in the presence of, 503 in current-steering DACs, 174–175 in direct conversion receivers, 35–36 in direct launch transmitters, 37–38 in feedback-based transmitter measurements, 151, 152 flexible baseband lowpass filters and, 17–18 in full SDR implementation, 27–28 in LC-VCOs, 71–72 multiplicative, 474 passive integration of front-end RF into systems-on-a-chip and, 113–114, 118 in pipelined ADCs, 170–171 RX band, 155–156 in signal processing, 219, 220–221 in single-chip polar transceiver radio, 87 in switched-capacitor filters, 234–237 in TD receivers, 205 in wideband down-conversion mixers, 17 Noise analysis linear model of the BBPLL for, 516–518 in transform-domain receivers, 194–195 Noise-canceling approach, in receivers, 15 Noise figure (NF), 285, 286, 288 standards for, 69, 74 with transform-domain receivers, 192 Noise figure degradation, feedforward loops and, 124–125 Noise floor, 550 estimation of, 544 Noise level, in SDR power amplification, 44–45 Noise power reducing variation on, 543–544 statistical distribution of MRSS on, 543–544 Noise requirements, of feedback path, 141–143 Noise shaping in current-steering DACs, 175 for  ADCs, 167–168, 169 in VCO-based ADCs, 248–249 techniques for, 361 Noise transfer function (NTF), 270 Noncausal filter, 415 Non-data-aided compensators, 473

579

Nonidealities in feedback-based transmitters, 141–148 in feedforward loop, 122–125 on quantizer output spectrum, 256 Nonlinear analysis techniques, 445 Nonlinear distortion, 463–466 memory in, 465 reducing, 48 Nonlinear distortion products, interference due to, 309–311 Nonlinearities. See also Nonlinearity in current-steering DACs, 175–176 VCO, 255, 257 Nonlinearity in analog-to-digital conversion, 22–23 from front-end small-signal components, 466 suppression of, 261–263 Nonlinearity transfer function, 262 Nonlinear map, 499 Nonlinear memory effects, 419–420, 421 Nonlinear terms, higher-order, 318 Nonlinear transfer function, in transmitter linearization, 47–48 Normalization equation, 507, 508 Normalized-LMS (NLMS) algorithm, 315, 332, 336, 338. See also Least mean squares entries; NLMS equalizers Notch filtering in passive integration of front-end RF into systems-on-a-chip, 119 receiver translational loop and, 119–120, 121–122 for WCDMA transmitter, 133–138 Notch filters feedback-based transmitter noise and, 141–142 on-chip, 150–151 in transmitters, 149, 150 NRZ structure, 270 Nyquist frequency, 167 Nyquist image attenuation (NIA), DACs and, 177–178, 179, 180, 181 Nyquist images DACs and, 177–178, 179, 180, 181, 184 parallel-path converters and, 182 RF-DAC and direct-to-RF modulators and, 182–183 Nyquist plots, 439, 443 Nyquist sampling theorem, 163 OFDMA transmission, linearization performance for, 424–425. See also Orthogonal frequency-division multiple access (OFDMA) technology

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OFDM-based standards, 349. See also Orthogonal frequency-division multiplexing (OFDM) OFDM-based systems, 351 OFDM multicarrier waveforms, 459 OFDM signals, 471 OFDM systems, PAPR reduction in, 478 OFDM transform-domain receivers, 189–217 OFDM waveforms, 474–475 symbol error rate of, 463 Off-chip inductor quality, in phase-locked loop design, 50 Offset performance, for a chopper-stabilized multiplier, 433, 435 Offsets in an analog multiplier, 427–429 in TD receivers, 198–199 in TD receiver simulation, 208–209, 210, 211 On-chip bandpass filters, feedforward notch filtering and, 134 On-chip capacitors, for receivers, 14 On-chip filters, in passive integration of front-end RF into systems-on-a-chip, 118–119 On-chip inductor quality, in broadband LO generation, 50 On-chip inductors, in LC-VCOs, 71, 72–73 On-chip notch filters, 150–151 feedforward notch filtering and, 136–138 On-chip RF filtering, 283–284 On-conductance, in MOS switch scaling, 221 1/f noise, in direct conversion receivers, 35–36. See also Flicker noise Op-amps for analog-to-digital conversion, 21 in charge-sampling circuit, 211–212 flexible baseband analog circuits for, 18–19 output from, 399 in SDR transceiver example, 57 Open-loop operation, of EER and ET, 371 Operating range, for software-defined radio, 33–34 Operational transconductance amplifiers (OTAs), in pipelined ADCs, 170, 171 Optimization adaptive multi-mode RF circuits for, 65–83 in transmitter stability, 49 Optimum compensator coefficient, 472 Orthogonal frequency-division multiple access (OFDMA) technology, 484, 534. See also OFDMA transmission Orthogonal frequency-division multiplexing (OFDM), 462–463, 468. See also OFDM entries digital baseband estimators for multi-carrier signals and, 195–196

full SDR implementation and, 28–29 multi-antenna, 476 Orthogonal spreading codes, 431–432 Oscillator-based ADC, 249–250. See also VCO-based ADCs Oscillator bias point, in LC-VCOs, 72 Oscillator frequency/phase instability, 459 Oscillator performance, of adaptive quadrature down-converter, 78 Oscillator phase noise, effects of, 463 Oscillators, 456 design of multi-mode, 70–73 feedback and, 48–49 Oscillator spectral width, 463 Oscillator tank loss variations in, 6–8 in wideband LC-VCO frequency tuning, 6 Oscillator tuning word (OTW), with reference/direct modulation point injection alignment, 107–108 OTA sharing, in pipelined ADCs, 170. See also Operational transconductance amplifiers (OTAs) Out-of-band blockers passive integration of front-end RF into systems-on-a-chip and, 114, 117 receiver translational loop and, 119, 121 Out-of-band blocking test, 290 Out-of-band distortion components, 464 Out-of-band signals, second-order intermodulation of, 466 Output impedance, in current-steering DAC converters, 175 Output jitter standard deviation of, 522–526 variance of, 525 Output phase noise, power spectral density of, 521–522 Output power amplifier efficiency and, 384–385 current-steering DAC reconfigurability and, 176–177 PDF functions of, 384 Output resistance, in transconductor design, 239–240 Outputs, for LNAs, 14 Output spectra, 403–405 of chopper-stabilized multipliers, 433, 435 Output voltage in IIR filter synthesis, 227 from single-balanced current-switching mixer, 223–224, 225 Overlapping time, for transform-domain receivers, 193–194

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INDEX Oversampled analog-to-digital converter (ADC), using VCO-based quantizers, 247–277 Oversampling ratio (OSR), 262–263, 283 current-steering DAC reconfigurability and, 176 in current-steering DACs, 175 for  ADCs, 168, 169 in hybrid ADCs, 172 Nyquist images and, 178, 179, 180, 181 software radio and, 163 Oversized stages, in pipelined ADCs, 171 PA distortion compensation techniques, 476. See also Power amplifiers (PAs) Pad parasitics, for receivers, 13–14 PA drivers, 154. See also Power amplifier entries feedback-based transmitter noise and, 142– 143 feedforward notch filtering and, 133 RX-LO feedthrough and leakage and, 145 for transmitters, 148, 150 in transmitter stability analysis, 138 PA linearization, 412 Palmers, Pieter, xi, 159 PA memory effects, 436 PA nonlinearities envelope dynamics and, 465 memoryless and quasi-memoryless, 445–446 PAPR values, high, 468. See also Peak-to-average-power ratio (PAPR) Parallel low-voltage power amplifiers, 380 Parallel-path converters for DACs, 182, 183 with transform-domain receivers, 191 Parallel transceivers, architectures of, 162–163, 184 Parallel Wiener model, 446–447 Parasitics losses in oscillator tank and, 7–8 in MOS switch scaling, 222 for receivers, 13–14 RX-LO feedthrough and leakage and, 145 in wideband down-conversion mixers, 17 Parseval’s theorem, 525 Passband gain, I–Q imbalance and, 125 Passive charge sharing for analog-to-digital conversion, 21 in successive approximation ADCs, 172 Passive component technology, in transmitter stability, 49 Passive FET mixers, with transform-domain receivers, 192–193 Passive filter, 266 Passive filtering, in IIR filter synthesis, 229

581

Passive integration, of front-end RF into systems-on-a-chip, 113–158 Passive mixers with transform-domain receivers, 191 for transmitters, 148 Passive off-chip matching, for receivers, 12 Passive quadrature mixers, in SDR transceiver example, 55–56, 57–58 Passive switched-capacitor filters noise generated in, 234–237 perspective and outlook for, 242–243 Peak power output, transmitter efficiency and, 46 Peak-to-average-power ratio (PAPR), 465–466. See also PAPR values Peak-to-average power ratio reduction/mitigation, 477–478 Peak-to-average ratio (PAR), 280, 291, 351 Peak-to-minimum ratio (PMR), 351 Percentage power in-band, 85 Performance of adaptive quadrature down-converter, 76–80 of multi-mode adaptive down-converter, 73–76 receiver, 154 of SDR transceiver example, 59–60 of software-defined transceivers, 34 transmitter, 155 Performance improvement, of digital-to-time converter, 52–53 Performance limits, of current-steering DACs, 174–176 Performance parameters, in adaptive low-power RF circuit design, 67 Performance specifications, for software-defined radio front ends, 4–5, 28, 29 Periodic noise (PNOISE) analysis, 236–237 Periodic steady-state (PSS) analysis, of noise, 236–237 Perrott, Michael H., xi, 247 Personal area network (PAN) systems, 533 Personal communications service (PCS) band, passive integration of front-end RF into systems-on-a-chip and, 114 Phase, filtering path and, 122 Phase accumulator, in DDS architecture, 50, 51 Phase encoding, transmitter efficiency and, 46 Phase error performance, with reference/direct modulation point injection, 109 Phase exception handling, in subnanosecond amplitude/phase modulation path alignments, 99–100 Phase exponential, 461 Phase feedback loop, 397

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Phase/frequency modulation (PM/FM) paths, delay alignment between amplitude modulation paths and, 85–111 Phase imbalance, I–Q, 125 Phase-locked loop (PLL)-based synthesizers, 460–461 Phase-locked loop (PLL) design all-digital, 85–86 in broadband LO generation, 49–50 delay-locked loop-based multipliers for, 53–54 for direct launch transmitters, 39, 40 with hybrid ADCs, 172 passive integration of front-end RF into systems-on-a-chip and, 115 with reference/direct modulation point injection alignment, 107 in wideband LC-VCO frequency tuning, 6, 10 Phase margin (PM), 440 in transmitter stability analysis, 139 Phase misalignment bounds on, 445 stability and, 436–441 Phase misalignment instability, 413–414 Phase mismatch (ϕ), 330–331, 458 feedforward loops and, 123–124 in calibrating SDR front ends, 26 in TD receiver simulation, 209 Phase modulation (PM) alignment accuracy between amplitude modulation and, 93–94, 94–95, 95–96 in first-generation DRP, 103–104 with RF polar transmitters, 88, 89, 90–96 in second-generation DRP, 104–105 subnanosecond alignment between amplitude modulation and, 96–101 in third-generation DRP, 105–106 Phase modulation paths, alignment accuracy between amplitude modulation paths and, 91–96 Phase noise (PN), 459–463 in adaptive quadrature down-converter, 79–80 impact of, 461 standards for, 69 in VCO, 253 VCO tuning range and, 6 in wideband LC-VCOs, 6 in wideband VCOs, 10, 11 Phase noise dynamics, 462 Phase noise effect, 548–550 Phase noise mitigation approaches, 474–476 Phase noise model, 475 Phase noise output expressions, validation of, 522–524

Phase noise power spectral density (PSD), 518 Phase noise PSD comparisons, 526–531 Phase noise requirements, in feedback path, 145–148 Phase noise theory, losses in oscillator tank and, 7 Phase noise tuning range (PNTR) of adaptive quadrature down-converter, 78, 79 in LC-VCOs, 72 Phase plane trajectories, 499–500 Phase response, 394 Phase response approximation, 444 Phase rotation, 475 Phase shift, 365, 441 amplitude-dependent, 446 Phase signal injection, 396 Phase trajectory error (PTE), 85 Physical-layer technologies, cutting-edge, xiii Physical resource block (PRB), 484 Pipelined architecture for ADCs, 167, 170–171, 184 with hybrid ADCs, 172 PMOS gates, in Miller op-amp, 18, 19 PMOS transistors, 400 flicker noise and, 36 losses in oscillator tank and, 8 in low-band LNAs, 16, 17 pre-power amplifier and, 23–24 PN sequences, 432 Polar baseband signals, for direct launch transmitters, 40–41 Polar feedback, 397 Polar-modulated architecture, major benefit of, 390 Polar-modulated power amplifiers distortion in, 390–397 for GSM-EDGE, 397–408 linearity improvement techniques for, 396–397 transmit architecture for, 387 Polar modulation, 370, 386–390 Polar modulation format, transmitter efficiency and, 46 Polar operation, of quadrature modulator, 58 Polar transmitters envelope modulation schemes for, 85 in nanoscale CMOS, 87–90 precise delay alignment between amplitude and phase/frequency modulation paths in, 85–111 Polar transmitter with exception handling, in subnanosecond amplitude/phase modulation path alignments, 99–100 Polynomial mapping, 465 Polynomial predistorters, 323–324

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INDEX Polyphase filters (PPFs) in LC-VCOs, 73 for wideband VCOs, 11–12 Portability, for software-defined radio, 33–34 Portable battery-operated equipment, SDR power amplification for, 42 Positioning systems, software-defined radio front ends for, 3 Positive feedback, in transmitters, 48–49 Post-mixer amplifier (PMA), in SDR transceiver example, 57 Postprocessing coefficients, 470 optimum solution for, 482 Power-added efficiency (PAE), high-speed clock alignment and maximizing, 101 Power amplification, in software-defined transceivers, 42–49 Power amplifier (PA) circuit. See also PA entries feedforward notch filtering and, 133 in RF polar transmitter, 88, 91 Power amplifier distortion compensation, 476–478 Power amplifier efficiencies, 351 Power amplifier efficiency enhancement, 354–362 Power amplifier function, 349–353 Power amplifiers (PAs), 445. See also PA entries AM-AM and AM-PM behavior of, 367 memory effects in, 419–420, 446–447 nonlinear distortion from, 464–465 waveform requirements for, 350–353 Power combining circuitry, 381 Power-combining techniques, 408 Power consumption in adaptive low-power RF circuit design, 66–67 of adaptive quadrature down-converter, 79–80 current-steering DAC reconfigurability and, 176–177 lowpass filters and, 20 in signal processing, 219 VCO tuning range and, 6 Power control, 382 Power control dynamic range (PCDR), 351 Power density function (pdf), 543, 545. See also Probability density function (pdf, PDF) Power dissipation, in software-defined transceivers, 34 Power output, transmitter efficiency and, 46 Power overhead, 166 for ADCs in dual-mode GSM–WLAN transceivers, 166 PowerPC microprocessor, with RFIC transceiver, 60 Power spectral density (PSD), 467 of the output phase noise, 521–522

583

Power spectral density expression, of the BPD noise, 519–521 Power spectrum oscillator, 461 Power supply, VCO, 261 Power supply voltage, changing, 386 Predistorted spectrum, 426 Predistortion, 363, 396–397, 405, 408, 476 feedforward, 365 linearity advantage of, 423–424 in linearization technology, 48 piecewise linear, 404 real antennas and, 420 Predistortion approaches, problems associated with, 365 Predistortion filter, 480–481 Predistortion measurements, 417 Predistortion parameters, 470 Prefilter in single-balanced current-switching mixer, 224, 225 in transconductor design, 239 Pre-power amplifiers (PPAs) digitally controlled, 85–86 as transmitter building blocks, 23–25 Printed-circuit boards (PCBs) passive integration of front-end RF into systems-on-a-chip and, 113 for receivers, 13 Probability density function (pdf, PDF), 384, 510. See also Power density function (pdf) Process, voltage, and temperature (PVT) in high-speed clock alignment, 101 transmitters and, 148 Programmable capacitance array, in feedforward receiver circuit implementation, 126. See also Capacitor arrays Programmable elements, SDR power amplification and, 42–43, 44 Programmable gain settings, for pre-power amplifier, 23 Propagation delay, VCO, 251 Prototype, measurement results from, 420–426 Prototype  ADC example with VCO quantizer, 265–275 Pseudodifferential configuration, in transconductor design, 241 Pseudo-random sequences, 433 Pseudo-random waveforms, 430 correlation properties of, 432 Pulse shape, with RF-DAC and direct-to-RF modulators, 183–184 Pulse-shape-induced amplitude distortion, DACs and, 178–179

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Pulse shaping, 419 Pulse-shaping filters, with RF polar transmitters, 90, 91 Pulse-width modulation (PWM) modulators, 359 Pure delay, 443–444 Q branch signal, filtering, 457 Q-enhancement, feedforward notch filtering and, 134 Quad-band GSM/EDGE transceiver, passive integration of front-end RF into systems-on-a-chip and, 114, 115, 116, 117 Quadrature amplitude modulation (QAM), RF polar transmitter with, 88 Quadrature baseband signals, in feedback-based transmitter measurements, 151 Quadrature mixers, for transmitters, 149 Quadrature generation, 303. See also Multi-mode adaptive quadrature signals divide/multiply quadrature for, 10–12 Quadrature imbalance, in calibrating SDR front ends, 25–26 Quadrature inputs, in SDR transceiver example, 55, 56 Quadrature local oscillator signals, for direct launch transmitters, 36–37 Quadrature LO clocks, in feedback-based transmitter measurements, 151 Quadrature mismatch, 318–320 Quadrature mixers feedforward notch filtering and, 135 second-order intermodulation performance of, 74 Quadrature modulator, in SDR transceiver example, 58–59 Quadrature oscillator (QOSC), phase noise and, 146 Quadrature phase error, 154 in feedback path, 144–145 Quadrature signal component, 197 Quadrature signals, phase noise and, 146 Quadrature square waves, 432 Quality monitors, for reference/direct modulation point injection, 109 Quantization error signal, in VCO-based ADCs, 249 Quantization noise, 361 in current-steering DACs, 174–175 for  ADCs, 167–168 in VCO, 253 VCO SNDR and, 256

Quantization performance, of digital-to-time converter, 52–53 Quantizer output spectrum, key nonidealities on, 256 Quantizers multi-bit, 169 VCO-based, 247–277 Quasi-memoryless PA nonlinearity, 445–446 Radio architecture, 468–469 RF impairments and, 468 for software-defined radio front ends, 4–5 for software-defined transceivers, 34 Radio equipment, cost-efficiency of, 453 Radio-frequency (RF) analog electronics, impairments in, 453–454. See also RF entries Radio-frequency band support, 280 Radio-frequency front end technology, 534, 535 Radio frequency integrated circuit (RFIC). See also RFIC interface adaptive multi-mode low-power design of, 66–68 feedforward notch filtering and, 133 integration into SDR transceiver, 55, 60 passive integration of front-end RF into systems-on-a-chip and, 113 Radio frequency transmitters envelope modulation schemes for, 85 in nanoscale CMOS, 87–90 Radio front ends, software-defined, 3–32 Radio receivers, 454–456 Radio resource management (RRM), 484 Radio spectrum management of, 33 for software-defined transceivers, 34 Radio transceiver functionalities, 456 Radio transmitters, 454–456 RAM addressing increments, 552 Random phase fluctuations, 460 Rauch biquadratic sections, 19 Rauch cells, 19 Rayleigh distribution, log-compressed, 543, 545 Real antennas, predistortion and, 420 Real-time time-alignment technique, 371 Receiver (RX) amplification stages, 456. See also RX entries Receiver-based processing, 477 Receiver blocks, for software-defined radio front ends, 3 Receiver budget/performance, in full SDR implementation, 27, 28–29 Receiver desensitization, in passive integration of front-end RF into systems-on-a-chip, 118

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INDEX Receiver front end, WCDMA, GSM/GPRS/EDGE, 292–299. See also RX front end entries Receiver IIP3 measurement results, 336–339 Receiver inputs, in SDR transceiver example, 55–56 Receiver I/Q imbalance compensation, 482–483 Receiver noise figure, feedforward loops and, 124–125 Receiver nonlinearities, 468 compensation for, 478–479 Receiver quadrature imbalance, in calibrating SDR front ends, 25–26 Receivers (RXs). See also RX entries in adaptive low-power RF circuit design, 66 building blocks for, 12–23 feedforward notch filtering and, 133 multi-mode, 68–70 OFDM transform-domain, 189–217 SAW-less, 310 in SDR transceiver example, 58–59 in single-chip polar transceiver radio, 85, 86–87 in software-defined transceivers, 34–36 Receiver sensitivity measurement results, 340 Receiver signal strength indicators (RSSIs), in SDR transceiver example, 54 Receiver translational loop, 119–122 Receiving (RX) path, of transceiver, 159 Recirculating method, with delay-locked loop-based multipliers, 54 Reconfigurability, 408 of current-steering DACs, 176–177 of  ADCs, 168–169 of pipelined ADCs, 170–171 of SDR transceiver hardware, 165–166 of software-defined radio front ends, 3 of successive approximation ADCs, 171–172 Reconstruction filters, SDR DACs and, 172–173 Reconstruction matrix, 197 Reference/direct modulation point injection alignment, 106–109 Reference sensitivity test, 287–289 Relative output power, 406, 407 Relaxed mode, standards for, 69 Remodulation, within direct launch transmitters, 39–40 Remodulation rejection system, for direct launch transmitters, 39–40 Reset operation, VCO, 250–251 Residual chopping tones, 430 Residue feedback, in pipelined ADCs, 170–171 Resistance, in transconductor design, 238, 239–240

585

Resistive feedback LNAs, 15, 16 Resistor arrays, in Miller op-amp, 18–19 Resistors, in multi-mode adaptive down-converter, 75 Resonant-inductive noise-reduction method, for LC-VCOs, 73 Resonant tank losses in oscillator tank and, 6–7 in wideband LC-VCO frequency tuning, 6 Retimed clock (CKR) with DRP ADPLL, 103 with first-generation DRP, 103 with reference/direct modulation point injection alignment, 106, 107, 108, 109 with second-generation DRP, 104, 105 with third-generation DRP, 105 Reynaert, Patrick, xi, 377 RF ADC, high-dynamic-range, 283. See also Analog-to-digital conversion (ADC); Radio frequency entries RF amplifier, design and implementation of, 398–399 RF architectures, digitally assisted, 411–449 RF band down-conversion, 481–482 RF carrier envelope variations, 382–383 RF class BE amplifier, 398 RF components, for mass-market applications, xiii RF-DAC design, 182–184. See also Digital-to-analog conversion (DAC) RF devices, user and application demands of, 66 RF filtering MEMS-based, 284–285 tunable on-chip, 283–284 RF filtering path, impulse response of, 121 RF filter passband, receiver translational loop and, 120 RF filters, 283 passive integration of front-end RF into systems-on-a-chip and, 113–114 passive integration of front-end RF into systems-on-a-chip and, 115 RF frequency bands, of VCOs, 6 RF front-end design, high-dynamic-range, 286 RF front end measurement results, 303–305 RF front end, multi-mode, 279 RF front ends (RFEs), 535, 555 with blocker cancellation, 285 RFIC interface, passive integration of front-end RF into systems-on-a-chip and, 116. See also Radio frequency integrated circuit (RFIC) RFIC/system, challenge and trends in, 535–536 RF impairment compensation, for future radio systems, 453–496

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RF impairments, 454–480 impact of, 468 sensitivity to, 468 RF imperfections, controlling, 469–470 RF-LO leakage, 468 RF multistage cubic term generator, 342 RF PA efficiency, 399 RF path, 436 RF path dynamics instability, 414–416 RF phase signal injection, 396 RF polar transmitters amplitude and phase modulation with, 88, 89, 90–96 in nanoscale CMOS, 87–90 RF power amplification, in software-defined transceivers, 42–49 RF power amplifiers CMOS, 377–410 component values of, 399 integration of, 377 in SDR power amplification, 43, 45–46, 49 RF power transistor, collector-drain supply of, 358 RF preselect filter, 279 RF receivers digitally enhanced alternate path linearization of, 309–342 signal processing in, 219–221 RF signal path, dynamics and delay in, 441–445 RF signals discrete-time processing of, 219–245 for receivers, 34–35 SDR power amplification and, 42–43 RF spectrum. See Radio spectrum RF system analysis, summary of, 292 RF systems, development direction for, 555 RF transceivers, 411 Ring oscillator-based dividers, phase noise and, 146 Ring oscillators, in broadband LO generation, 50 Ring-oscillator structure, 250 RMS output jitter, 525 ROM lookup table, in DDS architecture, 50, 51 Root-locus plots, in transmitter stability analysis, 140–141 RX-band noise. See also Receivers (RXs) attenuation of, 155–156 in feedback-based transmitter measurements, 152 RX bands, passive integration of front-end RF into systems-on-a-chip and, 115, 116, 118 RX frequency, feedforward notch filtering and, 133

RX front end. See also Receiver front end performance of, 305 in software-defined radio, 164–165 with transform-domain receivers, 192 RX-induced effects, 470 RX-induced imbalances, 472 RX-LO feedthrough. See also Local oscillator feedthrough feedback-based transmitter noise and, 143 in feedback path, 145 in transmitters, 149 RX-LO leakage in feedback path, 145 phase noise and, 147 RX-LO signals, phase noise requirements for, 145–148 RX quadrature LO clocks, in feedback-based transmitter measurements, 151 RX signal enhancement, 470 RX signal level, 337 RZ DAC element core, 269 RZ DAC switching waveforms, 269–270 RZ topology, 269 Sample-and-hold circuit, control of, 242 Sampled data, in TD receivers, 196–197 Sampled signal spectrum, DACs and, 177 Sample phase, of output voltage, 223–224 Sample-rate conversion block, 231–232 Sample rate converter (SRC), in subnanosecond amplitude/phase modulation path alignments, 97, 98 Sample-rate down-conversion, 231–234 Samplers, 455–456 Sampling bandpass signals, 467 Sampling capacitor, 417 Sampling frequency, for  ADCs, 167 Sampling jitter, 466–467 in bandpass sampling, 479–480 Sampling mixers, operation of, 223–225 Sampling receivers, 34, 35 Sampling speeds, for analog-to-digital conversion, 21 SAR architecture, for analog-to-digital conversion, 21–22 SAW filter elimination, 287. See also Surface acoustic wave (SAW) filter SAW-less receivers, 321 SAW-less UMTS receivers, 310, 342. See also Universal mobile telecommunications system (UMTS) Scalability, flexible baseband lowpass filters and, 17–18 Scaling, of MOS switches, 221–223

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INDEX Scattering parameters, in transmitter stability, 49 SDR application signal set, encoding format for, 40–41. See also Software-defined radio (SDR) SDR chip, microphotograph of, 27 SDR implementation, front ends in, 27–29 SDR transceiver front end, schematic of, 4 SDR transceivers. See Software-defined transceivers Second-generation DRP, phase modulation in, 104–105. See also Digital RF processor (DRP) Second-generation (2G) receivers, receiver translational loop and, 121 Second-order input intercept point (IIP2). See IIP2 performance summary Second-order intermodulation (IM2) performance, of quadrature mixers, 74 Second-order loop filter, 264 Second-order nonlinear distortion, 466 Second-order statistics-based techniques, 473 Second-order ZC-DPLL, 504 Segmented weighted DACs, topologies for, 173, 174. See also Digital-to-analog converters (DACs) Self-generated interference, 309 in direct launch transmitters, 37 issues in, 311 Self-mixing, 466 Sensitivity variations, among VCOs, 8–9 Sensor networks, TD receivers in, 215, 216 Sensor relay, transform-domain distributed, 215, 216 Serial latch block, 552 Series loss resistance, 379 Series regulator, 388 Sharp bandpass filter, feedforward notch filtering and, 133–134 Shielding, for direct launch transmitters, 39–40 Sideband fall-off, 539 Sideband noise level in direct launch transmitters, 37, 38 in SDR power amplification, 44–45  ADC, VCO quantizer versus comparator-based FLASH quantizer for, 257–261. See also Analog-to-digital conversion (ADC)  ADC architecture, 265–267 for VCO-based quantizer, 257–265  ADC design, metastability of high-speed, 258–260  feedback loop, 257

587

 modulation, 94, 243. See also Continuous-time  ADCs;  architecture for RF polar transmitters, 90–91 in TD receiver applications, 214 Signal bandwidth for analog-to-digital conversion, 21 current-steering DAC reconfigurability and, 176 for direct launch transmitters, 40–41 Nyquist images and, 178 Signal-dependent nonuniform sampling schemes, 479 Signal distortion, 471 spectral illustrations of, 462 Signal enhancement, 469–470 Signal estimation blind imbalance compensation schemes, 473 Signal expansion coefficients, transform-domain receivers and, 190 Signal-flow-graph diagram, IIR filter synthesis and, 229 Signal power, 547–548 Signal processing, in RF receivers, 219–221 Signal processing capabilities future of, 555–556 integrating digital, xiii Signal quality, amplifier, 46–47 Signals nonlinear relationship between, 392 transform-domain receivers and, 190 Signal selection, by receivers, 34 Signal-to-interference coverage, by cellular organized systems, 38–39 Signal-to-noise coverage, by cellular organized systems, 38 Signal-to-noise-plus-distortion ratio (SNDR), 317. See also SNDR limitations in ADC specifications, 161 in analog-to-digital conversion, 22–23 in full SDR implementation, 27 VCO quantization noise and, 256 Signal-to-noise ratio (SNR), 317, 504. See also SNR/SNDR for analog-to-digital conversion, 21 current-steering DAC reconfigurability and, 176 of current-steering DACs, 174–175 for  ADCs, 168, 169 in direct launch transmitters, 37 flexible baseband lowpass filters and, 18 LNA noise figure degradation and, 124 in SDR power amplification, 45 for software-defined transceivers, 34 in transform-domain receivers, 194

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Signal-to-quantization noise ratio (SQNR) theoretical, 254–255 VCO, 254–255 Simple charge integration circuit, for transform-domain receivers, 194 Simulated threshold level, 545–546, 547 Sinc filter bank in TD receiver complexity analysis, 207–208 for TD receivers, 204–205 Single-balanced current-switching mixer, operation of, 223–225 Single-carrier frequency-division multiple access (SC-FDMA), 484 Single-carrier modulation methods, 467 Single-channel direct-conversion transceiver, I/Q imbalances in, 468 Single-chip polar transceiver radio, operation of, 85–87 Single-ended output, from single-balanced current-switching mixer, 223–225 Single-pole dual-throw (SPDT) MEMS switches, for receivers, 12–13 Single RF power amplifier, in SDR power amplification, 43 Single-side band (SSB) mixers, for wideband VCOs, 11–12 Sinusoids, in the baseband signal, 414 Sinusoid signal processing, transmitter efficiency and, 46 Slope-based ADC, 250. See also Analog-to-digital conversion (ADC) Small-signal loop gain, in LC-VCOs, 72 Small-signal polar transmitters (TXs), 91 SNDR limitations, for VCO-based quantization, 252–257 SNR/SNDR, versus input amplitude, 273–274. See also Signal-to-noise-plus-distortion ratio (SNDR); Signal-to-noise ratio (SNR) Software-defined radio (SDR), 279, 411. See also SDR entries; Software-defined transceivers; Software radio (SR) ADCs and DACs for, 159–186 ADCs for, 166–172 DACs for, 172–179 defined, 33 low-noise amplifiers for, 12–14, 14–16 in modern communications systems, 159 multi-standard receiver with, 214–215 reconfigurable hardware for, 165–166 shift to cognitive radio, 534–535 in signal processing, 220 standard compliance by, 3 transceiver architecture of, 164–165

Software-defined radio front ends, 3–32 adaptive multi-mode RF circuits for, 65–83 analog-to-digital conversion for, 21–23 calibration techniques for, 25–27 in full SDR implementation, 27–29 receiver building blocks in, 12–23 reconfigurability of, 3 system-level considerations for, 4–5 transmitter building blocks in, 23–25 wideband LO synthesis and, 5–12, 30 Software-defined transceivers, 33–63. See also Software-defined radio (SDR); Software radio (SR) broadband LO generation in, 49–54 building blocks for, 34–54 direct launch transmitters in, 36–42 example of, 54–60 operating principles of, 33–34 radio architectures for, 34 receivers in, 34–36 reconfigurable hardware for, 165–166 RF power amplification in, 42–49 Software radio (SR), transceiver architecture of, 163–164 Solid-state amplifier (SSA) model, 464 Source follower, for transmitters, 148, 149 Source–gate capacitance, losses in oscillator tank and, 8 s-parameters, in transmitter stability, 49 Spectral behavior, of lowpass filters, 26–27 Spectral broadening, 461–462 Spectral efficiency, 412 Spectral leakage, 463 noise-induced, 468 Spectral mask, 404 Spectral mask margin, 405 Spectral regrowth, 352, 464, 468 Spectral replicas, for RF polar transmitters, 89–90 SpectreRF circuit-simulation suite, noise analysis with, 236–237 Spectrum analyzer output, versus MRSS output, 554–555 Spectrum sensing, 537–538 goal of, 542 Spectrum-sensing energy detector, 555 Spectrum signal processor demand, 537–538 Spectrum use, improving the efficiency of, 533 Split-band envelope amplifier, 359 Spreading codes, 431–432 Spurious free dynamic range (SFDR), in DAC specifications, 162 Spurious performance, reducing in digital-to-time converter, 52–53

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INDEX SQNRpeak , of VCO-based quantizer, 255 Squarers, 427 Square waves, 433 SRAM memory, for single-chip polar transceiver radio, 86 Stability of Cartesian feedback systems, 412–416 phase misalignment and, 436–441 transmitter, 48–49 Stability analysis, 447. See also Transmitter stability analysis for Cartesian feedback systems, 436–447 for feedforward notch filtering, 136–138 Stability potential, 49 Stacked device solution, 381 Stage bypass, in pipelined ADCs, 170–171 Stages in pipelined ADCs, 170–171 in transform-domain receivers, 194 Stand-alone adaptive circuits, implementing multi-standard modules as, 68 Stand-alone circuits, implementing multi-standard modules as, 67 Stand-alone flexible lowpass filters (LPFs), 19–20 Standards for ADCs, 167 for ADCs and DACs, 160–162 for calibrating SDR front ends, 25 compliance with, 3 for input to low-noise amplifiers, 69 Staple design technique, 309 Staszewski, Robert Bogdan, xi, xiii, 85 Static accuracy, in current-steering DACs, 175 Static mismatches, in TD receiver simulation, 209, 210 Stationary-phase error probability density function (pdf), 504. See also Probability density function (pdf, PDF) Stationary probability distribution, 507–508 Steady-state pdf, 510. See also Power density function (pdf) Stengel, Bob, xi, 33 Steyaert, Michiel, xi, 159 Stochastic differential equation (SDE), 505 Stopband filtering, gain mismatch and, 122–123 Stopband rejection in feedforward receiver circuits, 129–130 I–Q imbalance versus, 125 phase mismatch and, 123, 124 Straayer, Matthew Z., xi, 247 Subband control, 484 Subcarriers

589

for TD receivers, 197 in TD receiver simulation, 208–209 Subcarrier spacing, 462–463, 484 Subnanosecond amplitude/phase modulation path alignments, 96–101 Successive approximation architecture, for ADCs, 167, 171–172, 184 Superposition principle, 521 Supply voltage, 407–408 in LC-VCOs, 72 Surface acoustic wave (SAW) filter, 154, 292, 310, 412, 415, 424–425, 441, 443. See also SAW entries feedback notch filtering versus, 133, 134 in feedforward receiver circuits, 130–131 passive integration of front-end RF into systems-on-a-chip and, 114, 115, 116, 117–119, 153 receiver translational loop and, 119, 120, 121–122 in software-defined radio, 165 Switchable gain, in wideband down-conversion mixers, 17 Switchable Miller op-amp, flexible baseband analog circuits for, 18–19 Switched-capacitor analog filters, in signal processing, 220 Switched-capacitor filters advantages and disadvantages of, 242 in down-sampling, 231, 232–234 noise generated in, 234–237 perspective and outlook for, 242–243 in transconductor design, 240 Switched-capacitor networks, 226 Switched capacitors, in pipelined ADCs, 170 Switched inductor designs, in wideband LC-VCO frequency tuning, 6 Switches losses in oscillator tank and, 7 in Miller op-amp, 18 Switching amplitude modulator, 389–390 Switching frequency, 360, 390 Switching gain, gain mismatch and, 122 Switching mixers, for transmitters, 148 Switching-mode power amplifiers, digital modulation of, 361–362 Switching-mode RF power amplifiers, 361, 362 Switching waveforms, 269–270 Switch stage, 361 Switch transistors losses in oscillator tank and, 8 for transmitters, 149 System analysis, MRSS, 542–543

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System-level analysis, for software-defined radio front ends, 4–5 System-level analysis tool, for software-defined radio front ends, 5 System offsets, in TD receivers, 198–199 System requirements, translation of specification to, 320–322 Systems-on-a-chip (SoCs), passive integration of front-end RF into, 113–158 Tank capacitance, VCO sensitivity variations and, 8 Tapped delay line (TDL) for delay-locked loop-based multipliers, 53–54 in digital-to-time converter, 51, 52 with DRP ADPLL, 102 in high-speed clock alignment, 100–101 Tap selection process, in digital-to-time converter, 52–53 Tasic, Aleksandar, xii, 65 Taylor series, 318, 323 Taylor series expansion, 467 TDD systems, 282–283. See also Time-domain duplex (TDD) operation TDMA systems, power control in, 382 Technology scaling, ADCs and DACs in, 159–160 TETRA narrowband digital modulation, in linearization technology, 48 Thermal memory effects, 396 Thermal noise, 422 in switched-capacitor filters, 234–235 in wideband down-conversion mixers, 17 Thermometer-code converter, current-steering DAC reconfigurability and, 176 Third-generation (3G) applications, 153 Third-generation cellular wireless services, 349 Third-generation DRP, phase modulation in, 105–106. See also Digital RF processor (DRP) 3rd Generation Partnership Project (3GPP), 281. See also 3GPP long-term evolution Third-generation (3G) receivers, receiver translational loop and, 121–122 Third-order (IM3) distortion, 289, 290. See also IM3 entries Third-order input intercept point (IIP3), standards for, 69, 74, 78. See also IIP3 entries Third-order intercept point measurement, in analog circuit performance, 20–21 Third-order noise shaping, 265 Third-order nonlinearity, of feedback path, 143–144

3GPP long-term evolution, 484–485. See also 3rd Generation Partnership Project (3GPP) Three-state Markov chain, 512 Three-tap predistortion filter, 485 Three-tone test, 324 Threshold level, phase noise effect on, 548–550 Threshold-level determination, 544–547 Threshold voltage, comparator, 259 Time alignment effects, in direct launch transmitters, 41 Time-confined windows, 538 Time delays, in alignment accuracy between amplitude and phase modulation paths, 91, 92 Time-domain duplex (TDD) operation. See also TDD systems passive integration of front-end RF into systems-on-a-chip and, 113 SDR power amplification and, 42, 43 Time-domain multiplication, 539–540 Time misalignment, EDGE spectrum and, 92, 93 Time slot, 484 Time-switching, for direct launch transmitters, 36 Time-to-digital converter (TDC) with DRP ADPLL, 103 with reference/direct modulation point injection alignment, 107 Total system efficiency, 358 Training, of a look-up table, 417, 420 Training data sequences, transmission of, 422–423 Trajectories, phase plane, 499 Transceiver concepts, developing novel, xiii Transceivers. See also Software-defined transceivers ACD/DAC requirements for, 160–161 ADCs and DACs in, 159 architectures of multi-standard, 162–165, 184 for software-defined radio front ends, 3 Transconductance losses in oscillator tank and, 7 in TD receivers, 205 Transconductance amplifier design, 295–297 Transconductance transistors, for transmitters, 149 Transconductor circuits, design of, 237–241 Transconductor phase, of output voltage, 223 Transfer functions in feedback-based transmitter measurements, 151, 152 in IIR filter synthesis, 226 of lowpass filters, 27 Transform-domain basis coefficients, computing, 191–192

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INDEX Transform-domain distributed sensor relay, 215, 216 Transform-domain (TD) receivers, 189–217 advantages of, 215–216 applications of, 214–215 background/principles of, 190–191 block diagram of, 191 calibration algorithm for, 199–200 comparative study of, 204–208 digital baseband design for, 195–204 frequency-offset estimation for, 199, 201–204 gain/bandwidth requirement for, 211–212 with input OFDM signal, 196–197 sampling in, 191–195 simulations of, 208–211 sparsity of (G H G)−1 and, 206, 207, 213–214 Transformer balun, 333 Transformer independence, 381 Transistor mismatch, in direct conversion receivers, 36 Transistors losses in oscillator tank and, 7, 8 in multi-mode adaptive down-converter, 75 in pre-power amplifier, 23 for transmitters, 149 Transition probability matrix, 506–507 Transmission gate ring switching mixer, design of, 37–38 Transmitter blocks, for software-defined radio front ends, 3 Transmitter building blocks, in software-defined radio front ends, 23–25 Transmitter efficiency, SDR power amplification and, 46 Transmitter frequency-domain mask, 47 Transmitter imperfections, TX-based mitigation of, 470 Transmitter I/Q calibration, 480–482 Transmitter linearization, 476 SDR power amplification and, 46–48 Transmitter measurements, feedback-based, 150–153 Transmitter mixers, 150 Transmitter performance, 94–95, 95–96 in full SDR implementation, 28–29 Transmitter power amplifiers, 456 Transmitter quadrature imbalance, in calibrating SDR front ends, 25–26 Transmitters (TXs). See also Digital polar transmitters; Direct-launch transmitters; Polar transmitters; Radio frequency (RF) transmitters; TX entries building blocks for, 148–150

591

in close proximity, 38–39 in a digitally modulated wireless link, 417 envelope modulation schemes for, 85 feedforward notch filtering for, 133–138 in single-chip polar transceiver radio, 85, 87 small-signal polar, 91 in software-defined transceivers, 36–42 Transmitter stability, SDR power amplification and, 48–49 Transmitter stability analysis, feedback-based, 138–141 Transmitter transfer functions, in feedback-based transmitter measurements, 151, 152 Transmitting (TX) path, of transceiver, 159 Traveling-wave network, in SDR power amplification, 44 Traveling-wave tube amplifier (TWTA) model, 464 Tri-band WCDMA radio, passive integration of front-end RF into systems-on-a-chip and, 116 Triple-source configuration, 269–270 Tunability, in phase-locked loop design, 50 Tunable on-chip RF filtering, 283–284 Tuning ranges, for down-converter, 74 TV tuners, in broadband LO generation, 50 Two-tap FIR filter, 232 “Two-tone” blocker scenario, 320 Two-tone IIP3 test, 336–339 Two-tone signal, 392–395 time waveforms and spectra of, 395 Two-tone test, 314 TX bands, passive integration of front-end RF into systems-on-a-chip and, 115, 116, 117–118. See also Transmitters (TXs) TX calibration, 150 TX constellation, in full SDR implementation, 28–29 TX front end, in software-defined radio, 164–165 TX-induced effects, 470 TX-induced imbalances, 472 TX leakage, 153, 310, 336, 337, 338 phase noise and, 147 TX modulator, 150 TX notch filter, in passive integration of front-end RF into systems-on-a-chip, 119 TX output leakage, 314 TX power leakage, 286–287, 289 TX quadrature LO clocks in feedback-based transmitter measurements, 151 in RX band noise attenuation, 155–156 TX signal, linearity requirements of feedback path and, 143–144

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TX waveform baseband model, 480 Type I bandpass filters, 136–138 in transmitter stability analysis, 138–141 Type II bandpass filters, 136–138 in transmitter stability analysis, 138, 140, 141 Ultrahigh-speed clocks, in RF polar transmitters, 88 Ultrawideband-based personal area network (PAN) systems, 533 Ultrawideband (UWB) radio digital baseband estimators for multi-carrier signals and, 196 in TD receiver applications, 214–215 Ultrawideband RF receivers, transform-domain, 189–190 Ultrawideband standards, 444 UMTS blocker profile, 321. See also Universal mobile telecommunications system (UMTS) UMTS FDD standard, 309–310 UMTS receiver, adaptively linearized, 331–336, 336–341 UMTS spreading gain, 340 Unary weighted DACs, topologies for, 173. See also Digital-to-analog converters (DACs) Unfiltered complex envelope signal, 383 Unintended feedback, in transmitters, 48–49 Unity gain frequency, 415, 438–440 Universal mobile telecommunications system (UMTS), adaptive multi-mode RF circuit design for, 67. See also UMTS entries Up-chop operation, 430 Up-chopping waveforms, 431, 432 Up-conversion mixers feedback-based transmitter noise and, 141–142, 143 feedforward notch filtering and, 135 in feedforward receiver circuit implementation, 125, 128–129 filtering path and, 122 gain mismatch and, 122 LNA noise figure degradation and, 125 in RX band noise attenuation, 155–156 RX-LO feedthrough and leakage and, 145 in transmitters, 149 Update rate limits, of current-steering DACs, 174 Up-mixing, digital, 181–182 Valkama, Mikko, xii, 453 Varactors implementing in circuits, 9–10 in LC-VCOs, 71, 72–73 losses in oscillator tank and, 8

VCO sensitivity variations and, 8–9 in wideband LC-VCO frequency tuning, 6 Variable-delay element, 267–268 Variable-gain amplifier (VGA), 293–294, 427 flexible baseband analog circuits and, 21 Variable-gain amplifier stage, for pre-power amplifier, 24 Variable gain control, 243 Variable phase shift, 365 VCO-based ADCs, 248–249. See also Analog-to-digital converters (ADCs); Voltage-controlled oscillators (VCOs) measured performance of, 272–275 VCO-based quantization, SNDR limitations for, 252–257 VCO-based quantizer. See also VCO quantizer entries alternative structures for, 250–251 background/operation of, 248–252 circuit implementation for, 267–272 comparator-based quantizers versus, 257 comparator offset effect on, 260 connecting outputs to DAC elements, 258 example design of, 255–256 high-speed structure for, 251 implicit barrel-shift DEM using, 257–258 linear modeling of, 252–254 metastability of, 260 multi-bit, 258 oversampled ADC using, 247–277 properties of, 266 VCO delay cells, 251 VCO frequency signal, 253 VCO nonlinearity, 255, 257 error in, 262 suppression of, 261–263 VCO output frequency, 248 VCO output signal changes, 248 VCO power supply, 261 VCO quantizer, monotonicity of, 260. See also VCO-based quantizer VCO quantizer  ADC architecture, 257–265 VCO-quantizer nonlinearity suppression modeling, 261–263 Vector combined signal processing elements, in transmitter stability, 49 Vector-distributed multi-section gain stages, in SDR power amplification, 44 Velocity saturation, 302 Very high speed digital subscriber lines (VDSLs), digital baseband estimators for multi-carrier signals and, 196 VGA design, 298–299

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INDEX VHDL simulation, validation of phase noise output expressions via, 522–524 Voltage, comparator threshold, 259. See also Voltages Voltage-controlled oscillators (VCOs), 303. See also LC-VCOs; VCO entries in adaptive low-power RF circuit design, 67 in adaptive quadrature down-converter, 78 in broadband LO generation, 49–50 for direct launch transmitters, 39–40 divide/multiply quadrature for, 10–12 in multi-mode adaptive quadrature signal generation, 70 passive integration of front-end RF into systems-on-a-chip and, 115 reset operation for, 250–251 in SDR transceiver example, 59 sensitivity variations among, 8–9 3 to 5-GHz, 6–10 in wideband LO synthesis, 5–12, 30 Voltage-driven quadrature down-converter, performance of, 75 Voltage-gain amplifier (VGA) in ADC specifications, 161 in SDR transceiver example, 57 Voltage regulators for single-chip polar transceiver radio, 86 transmitter efficiency and, 46 Voltages, in LC-VCOs, 72. See also Voltage Voltage sampling, in transform-domain receivers, 194–195 Voltage standing wave ratios (VSWRs), 423–424 Voltage-to-frequency relationship, 248 Voltage-to-frequency tuning, 268 Voltage-to-frequency tuning curve, VCO, 255 Voltage-to-phase relationship, 248 Waheed, Khurram, xii, 85 Walsh codes, 432 Waveform quality metric, 353 Waveforms in analog-to-digital conversion, 21–22 Gaussian minimum shift keying for, 36 WCDMA, GSM/GPRS/EDGE receiver front end, minus interstage SAW filter, 292–299. See also Wideband code-division multiple access (WCDMA, W-CDMA) WCDMA modulation scheme, 85, 91 for alignment accuracy between amplitude and phase modulation paths, 91, 92, 93–94 for alignment accuracy between integer and fractional bits of amplitude and phase modulation, 93–94, 94–95, 95–96

593

with DRP ADPLL, 101, 102 passive integration of front-end RF into systems-on-a-chip and, 115, 116, 117 with reference/direct modulation point injection alignment, 106, 108 with third-generation DRP, 105 WCDMA receiver, 281. See also WCDMA RX multi-mode receiver principles and RF system analysis for, 286–292 WCDMA RF receiver system analysis, 287–289 WCDMA RX, 286. See also WCDMA receiver WCDMA standards, for input to low-noise amplifiers, 69 WCDMA transmitters, 154 feedback-based measurements of, 151–152 feedforward notch filtering for, 133–138 in transmitter stability analysis, 141 WCDMA TX leakage, 292. See also WCDMA transmitters White noise, jitter noise as, 467. See also Additive white Gaussian noise (AWGN); Wideband white Gaussian noise White space, unlicensed use of, 533 Wide area networks (WANs), passive integration of front-end RF into systems-on-a-chip and, 114 Wideband (WB) RF receivers, transform-domain, 189–190 Wideband code-division multiple access (WCDMA, W-CDMA), 279. See also WCDMA entries Wideband communication, CMOS DAC implementations for, 173, 179–181 Wideband communications systems, 436 Wideband down-conversion mixers, 16–17 Wideband ET techniques, 358 Wideband LC-VCOs, in integrated circuits, 6 Wideband LO synthesis, for software-defined radio front ends, 5–12, 30 Wideband low-noise amplifiers (LNAs), in receivers, 14–16 Wideband multicarrier, 469 Wideband resistive feedback LNAs, 15, 16 Wideband signal injection, 396 Wideband VCO architecture, 7 implementing, 9–10 Wideband white Gaussian noise, 545 Wide-bandwidth ET (WBET), 357 Wide-bandwidth telecommunication DACs, 173 Wide-dynamic-range signals, 358 Wiener–Hammerstein model, 465 Wiener model, 465 Wiener process, 461

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WiMAX modulation scheme, 85 digital baseband estimators for multi-carrier signals and, 195–196 with reference/direct modulation point injection alignment, 106 Windowed integration, with transform-domain receivers, 191–192 Windowing in charge-sampling circuit, 211–212 in TD receiver complexity analysis, 207 in transconductor design, 239 for transform-domain receivers, 192–195 Windowing effect, 538–539 Winoto, Renaldi, xii, 219 Wireless communication standards, 160–161 for ADCs, 167 Wireless communications future of, 453 next-generation, 349–375 Wireless communication systems, this book and, xiii Wireless devices, multi-mode receivers in, 68–70 Wireless LAN standards, in broadband LO generation, 50 Wireless local area networks (WLANs). See also Dual-mode GSM–WLAN transceivers adaptive multi-mode RF circuit design for, 67, 68 digital baseband estimators for multi-carrier signals and, 195–196 software-defined radio front ends for, 3 software radio and, 163

Wireless mobile terminals challenges related to, 280–282 reduced external hardware and reconfigurable RF receiver front ends for, 279–308 Wireless regional area network (WRAN), 533 Wireless regional area network standard, 538 Wireless RFIC design, adaptive multi-mode low-power, 66–68. See also Radio frequency integrated circuit (RFIC) Wireless standards newer generations of, 353 signal characteristics of, 350 Wireless systems ADC/DAC requirements in, 160–162 user and application demands of, 66 Wireless technology, advances in, 533 WLAN modulation schemes, 85 with third-generation DRP, 105 WPANs, software-defined radio front ends for, 3 Xilinx FPGA, with RFIC transceiver, 60 XOR gates, with delay-locked loop-based multipliers, 54 Yanduru, Naveen K., xii, 279 Zero-crossing digital PLL (ZC-DPLL), 504 Zero-IF receivers, 34 Zero/low-IF TD receivers, 191 Zeroth-order-hold DAC, 178