Nanoscaled Semiconductor-On-Insulator Structures and Devices

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Nanoscaled Semiconductor-on-Insulator Structures and Devices

NATO Science for Peace and Security Series This Series presents the results of scientific meetings supported under the NATO Programme: Science for Peace and Security (SPS). The NATO SPS Programme supports meetings in the following Key Priority areas: (1) Defence Against Terrorism; (2) Countering other Threats to Security and (3) NATO, Partner and Mediterranean Dialogue Country Priorities. The types of meeting supported are generally "Advanced Study Institutes" and "Advanced Research Workshops". The NATO SPS Series collects together the results of these meetings. The meetings are coorganized by scientists from NATO countries and scientists from NATO's "Partner" or "Mediterranean Dialogue" countries. The observations and recommendations made at the meetings, as well as the contents of the volumes in the Series, reflect those of participants and contributors only; they should not necessarily be regarded as reflecting NATO views or policy. Advanced Study Institutes (ASI) are high-level tutorial courses intended to convey the latest developments in a subject to an advanced-level audience Advanced Research Workshops (ARW) are expert meetings where an intense but informal exchange of views at the frontiers of a subject aims at identifying directions for future action Following a transformation of the programme in 2006 the Series has been re-named and re-organised. Recent volumes on topics not related to security, which result from meetings supported under the programme earlier, may be found in the NATO Science Series. The Series is published by IOS Press, Amsterdam, and Springer, Dordrecht, in conjunction with the NATO Public Diplomacy Division. Sub-Series A. B. C. D. E.

Chemistry and Biology Physics and Biophysics Environmental Security Information and Communication Security Human and Societal Dynamics

http://www.nato.int/science http://www.springer.com http://www.iospress.nl

Series B: Physics and Biophysics

Springer Springer Springer IOS Press IOS Press

Nanoscaled Semiconductor-onInsulator Structures and Devices Edited by

S. Hall University of Liverpool Liverpool, United Kingdom

A.N. Nazarov Lashkaryov Institute of Semiconductor Physics NAS of Ukraine, Kyiv, Ukraine

V.S. Lysenko Lashkaryov Institute of Semiconductor Physics NAS of Ukraine, Kyiv, Ukraine

Published in cooperation with NATO Public Diplomacy Division

Proceedings of the NATO Advanced Research Workshop on Nanoscaled Semiconductor-on-Insulator Structures and Devices Big Yalta, Ukraine 15–19 October 2006

A C.I.P. Catalogue record for this book is available from the Library of Congress.

ISBN 978-1-4020-6379- 4 (PB) ISBN 978-1-4020-6378-7 (HB) ISBN 978-1-4020-6380-0 (e-book)

Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands.

www.springer.com

Printed on acid-free paper

All Rights Reserved © 2007 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.

INTRODUCTION This proceedings volume constitutes an archive of the contributions of the key-speakers who attended the NATO Advanced Research Workshop on “Nanoscaled Semiconductor-On-Insulator Structures and devices” held in the Tourist and Recreation Centre “Sudak” (Crimea, Ukraine) from 15 to 19 October 2006. The semiconductor industry has sustained a very rapid growth during the last three decades through impressive technological developments which have resulted in products with higher performance and lower cost per function. After many years of development it is now confidently predicted that semiconductor-on-insulator materials will enter and increasingly be used by manufacturing industry. The wider use of semiconductor (especially silicon) on insulator materials will not only enable the benefits of these materials to be demonstrated but, also, will drive down the cost of substrates which, in turn, will stimulate the development of other novel devices and applications. Thus the semiconductor-on-insulator materials of today are not only the basis for modern microelectronics but also for future nanoscale devices and ICs. In itself this trend will encourage the promotion of the skills and ideas generated by researchers in the Former Soviet Union and Eastern Europe. Indeed, one of the goals of this Workshop is to promote the development of SOI technologies worldwide. This volume contains mainly the review manuscrips composed on the basis of oral and poster papers presented during the four-day meeting, under the heading of: •

Nanoscaled SOI Material and Device Technologies;

•

Physics of Novel Nanoscaled SOI Devices;

•

Reliability and Characterization of Nanoscaled SOI devices;

•

Theory and Modeling of Nanoscaled Devices.

These high-quality papers were presented by researchers from Japan, USA, Western Europe and the Eastern European countries of the Former Soviet Union thereby fulfilling a key objective of the Workshop which was the development of world-wide contacts between researchers in the attendees countries.

v

vi

INTRODUCTION

The meeting thus successfully achieved its scientific and networking goals and the attendees wish to express their gratitude to the NATO Programme Security through Science and Network of Excellence Project of European Community “Silicon-Based Nanodevices”, whose financial support made the meeting possible; and National Academy of Sciences of Ukraine, Ministry of Science and Education of Ukraine and the Lashkaryov Institute of Semiconductor Physics, NASU who provided local support. We would like to thank the Agency of International Cooperation “Optima” whose Director Mariya Miletska helped us to organize this Workshop in a professional manner. Our sincere gratitude also goes to Dr. Ya. Vovk, A. Rusavsky, Dr. V. Kilchytska, V. Stepanov, V. Torbin, Dr. A. Stronskii, Dr. Yu. Gomenyuk, Dr. I. Osiyuk, Dr. T. Rudenko, Dr. I. Tyagulskii, V. Smirnaya, J. Cowan and A. Winker for their clerical and technical assistance. A final special thanks to Mr. Yurii Houk for his dedication in compiling this book and for many other practical contributions.

Steve Hall Liverpool, United Kingdom

Alexei Nazarov and Vladimir Lysenko Kyiv, Ukraine

INTRODUCTION

vii

viii

INTRODUCTION

INTRODUCTION

ix

CONTENTS

INTRODUCTION .............................................................................. v Nanoscaled SOI Material and Device Technologies Status and trends in SOI nanodevices................................................. 3 F. Balestra Non-planar devices for nanoscale CMOS ........................................ 19 M.C. Lemme, H.D.B. Gottlob, H. Kurz High-κ dielectric stacks for nanoscaled SOI devices ....................... 33 S. Hall, O. Buiu, I.Z. Mitrovic, Y. Lu, W.M. Davey Nanoscaled semiconductor heterostructures for CMOS transistors formed by ion implantation and hydrogen transfer......... 59 V. Popov, I. Tyschenko, A. Cherkov, M. Voelskow Fluorine –vacancy engineering: A viable solution for dopant diffusion suppression in SOI substrates............................................ 73 H.A.W. El Mubarek and P. Ashburn Suspended Silicon-On-Insulator nanowires for the fabrication of quadruple gate MOSFETs ............................................................ 89 V. Passi, B. Olbrechts, J.-P. Raskin, J. Bolten, T. Mollenhauer, T. Wahlbrink, M.C. Lemme, H. Kurz Physics of Novel Nanoscaled SemOI Devices Integration of silicon single-electron transistors operating at room temperature.............................................................................. 97 T. Hiramoto SiGe nanodots in electro-optical SOI devices ................................ 113 A.V. Dvurechenskii, A.I. Yakimov, N.P. Stepina, V.V. Kirienko, P.L. Novikov Nanowire quantum effects in trigate SOI MOSFETs..................... 129 J.-P. Colinge

xi

xii

CONTENTS

Semiconductor nanostructures and devices .................................... 143 J. Knoch and H. Lüth MuGFET CMOS process with midgap gate material .................... 159 W. Xiong, C.R. Cleavelin, T. Schulz, K. Schrüfer, P. Patruno and J.-P. Colinge Doping fluctuation effects in multiple-gate SOI MOSFETs .......... 165 C.A. Colinge, W. Xiong, C.R. Cleavelin and J.-P. Colinge SiGeC HBTs: impact of C on device performance ........................ 171 I.Z. Mitrovic, H.A.W. El Mubarek, O. Buiu, S. Hall, P. Ashburn, J. Zhang Reliability and Characterization of Nanoscaled SOI Devices Noise research of nanoscaled SOI devices ..................................... 181 N. Lukyanchikova Electrical characterization and special properties of FINFET structures......................................................................................... 199 T. Rudenko, V. Kilchytska, N. Collaert, A. Nazarov, M. Jurczak, and D. Flandre Substrate effect on the output conductance frequency response of SOI MOSFETs ........................................................................... 221 V. Kilchytska, D. Levacq, D. Lederer, G. Pailloncy, J.-P. Raskin and D. Flandre Investigation of compressive strain effects induced by STI and ESL .............................................................................. 239 S. Zaouia, S. Cristoloveanu and A.H. Perera Charge trapping phenomena in single electron NVM SOI devices fabricated by a self-aligned quantum dot technology........ 251 A. Nazarov, V. Lysenko, X. Tang, N. Reckinger, V. Bayot

CONTENTS

xiii

Theory and Modeling of Nanoscaled Devices Variability in nanoscale UTB SOI devices and its impact on circuits and systems ........................................................................ 259 A. Asenov, K. Samsudin Electron transport in Silicon-on-Insulator nanodevices ................. 303 F. Gámiz, A. Godoy, C. Sampedro All quantum simulation of ultrathin SOI MOSFETs...................... 323 A. Orlikovsky, V. Vyurkov, V. Lukichev, I. Semenikhin, A. Khomyakov Resonant tunneling devices on SOI basis....................................... 341 B. Majkusiak Mobility modeling in SOI FETs for different substrate orientations and strain conditions ................................................... 357 V. Sverdlov, E. Ungersboeck, H. Kosina Three-dimensional (3-D) analytical modeling of the threshold voltage, DIBL and subthreshold swing of cylindrical gate all around MOSFETs........................................................................... 363 H.A. El Hamid, B. Iñiguez, J. Roig AUTHORS INDEX ........................................................................ 369

Nanoscaled SOI Material and Device Technologies

STATUS AND TRENDS IN SOI NANODEVICES FRANCIS BALESTRA* Institut de Microélectronique, Electromagnétisme et Photonique IMEP (CNRS-INPG-UJF), INP Grenoble-Minatec, BP 257, 38016 Grenoble, France *

email: [email protected]

Abstract. A review of recently explored new materials and architectures for SOI nanodevices is given. Recent advances in the understanding of the sensitivity of electron and hole transport to the tensile or compressive uniaxial and biaxial strains in thin film SOI are presented. The electrical properties in multi-gate Si, SiGe, Ge and GaAs MOSFETs and Nanowires realized with various channel orientations are also addressed. The impact of gate misalignment or underlap, as well as the use of the back gate for charge storage in double-gate nanodevices and of capacitorless DRAM are also outlined.

Keywords: SOI nanodevices, Multi-gate MOSFETs, Nanowires, Strain, Channel orientation, Memories

1. Introduction SOI devices are the best candidates for the ultimate integration of integrated circuits on silicon. The flexibility of the SOI structure and the possibility to realize new device architectures allow to obtain optimum electrical properties for low power and high performance circuits. These transistors are also very interesting for high frequency and memory applications [1-3]. In this paper, an overview of recently explored new materials and device architectures is given. The advantages and drawbacks of a number of SOI nanodevices are also addressed.

3 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 3-18. © 2007 Springer.

4

STATUS AND TRENDS IN SOI NANODEVICES

2. Influence of strain and surface orientation on the electrical properties of thin layers on insulators Compressive and tensile biaxial and uniaxial stress silicon technologies are promising for enhancing CMOS performance in bulk and SOI MOSFETs. The combination of strained layers and ultra thin films SOI structures is one of the best candidate for decananometer MOSFETs. Figure 1 is a plot of the dependence of electron and hole mobilities as a function of the charge density [4]. The strained Si layer is fabricated with sacrificial thin relaxed SiGe and smart cut. In the sSOI devices, substantial enhancements of both electron (about 100%) and hole (about 50%) mobilities are obtained compared with the control SOI device at intermediate charge densities for long channel transistors. An enhancement of the electron mobility of about 15-20% has been obtained for short channels (70nm technology) SGOI MOSFETs (strained Si on SiGe on insulator) together with superior short channel control [5,6]. Fig. 2 shows the enhancement of the drain current for sub-0.1µm devices. 1000

200

NMOS 20 × 20

PMOS 20 × 20 150

SSOI

600

µeff (cm2/Vs)

µeff (cm2/Vs)

800

400

0 0

100 SOI 50

SOI

200

SSOI

3 6 9 Charge density (× 1012 cm-2)

12

0 0

3 6 9 Charge density (× 1012 cm-2)

Figure 1. Effective mobility comparison between SSOI and SOI MOSFETs

Drain current (mA)

1.0

VG (V)= Vth + 0, 0.25, 0.5, 0.75, 1

0.8

Strained-SOI

SOI

0.6 0.4 0.2 0.0 0

0.6 0.2 0.4 Drain voltage (V)

Figure 2. Id-Vd of 70nm MOSFETs (W=1um)

0.8

12

STATUS AND TRENDS IN SOI NANODEVICES

5

In Fig. 3, the electron mobilities are represented for various Ge content of the SiGe layer and different Si film thicknesses. The electron mobility enhancement is maximum for 30% of Ge due to the increase in alloy scattering and/or surface roughness and the hole mobility continuously increases with Ge up to 50% [6]. It is also worth noting that the enhancement of carrier mobility is reduced in thinner strained Si films due to interface states and fixed charges induced by the diffusion of Ge atoms to the interfaces. Figure 4(a,b) shows Idsat and Gmsat as a function of channel length for SGOI and SOI MOSFETs. An enhancement of Id is outlined down to sub50nm transistors for SGOI, but the difference diminishes at smaller channel length due in particular to larger self-heating (SH) in SiGe than in Si. This SH effect in SGOI degrades Gmsat, which is more sensitive to SH than Id. Therefore the transconductance appears degraded in SGOI as compared to SOI but after correction of the self-heating a similar increase is obtained for Id and Gm in the SGOI structure [7]. Electron mobility enhancement over universal mobility

2.0 1.8 1.6 TsSi (nm) = 25 15 10

1.4 1.2 1.0 0.8

Ge content = 10% 15%

20%

30%

40%

50%

0.2 0.7 0.2 0.7 0.2 0.7 0.2 0.7 0.2 0.7 0.2 0.7 Eeff (MV/cm)

Figure 3. Eeff dependence of electron mobility enhancement as a function of Ge content and film thickness 750 1200

SGOI

SOI gmsat (µS/µm)

ID, SAT (µA/µm)

700 650 SOI 600 550 500 20

1100 1000

SGOI

900

VGS - VT = 0.7 V 40

60 LGATE (nm)

80

800 20

100

(a)

40

60 LGATE (nm)

Figure 4. Comparison of Idsat and Gmsat at a constant gate overdrive

80

100

(b)

6

STATUS AND TRENDS IN SOI NANODEVICES

Mobility enhancement factor*

The HOI structure (strained Si/strained SiGe/ strained Si heterostructure on insulator) presents also substantial electron and hole mobility enhancements [8]. In particular, hole mobilities are very high for thin Si cap layer (enhancement of about 100%) compared with the universal SOI mobility and are also significantly larger that the best SSDOI mobility (Strained Si Directly On Insulator) due to the compressively strained buried SiGe channel (Fig. 5). Uniaxial strain engineering is also useful for mobility enhancement for Si film thickness in the sub-10nm range [9]. A similar enhancement of electron mobility in 3.5nm SOI devices under biaxial and uniaxial tensile strain has been obtained. The electron mobility is also enhanced in 2.3nm Si layer under uniaxial tensile strain (Fig. 6), and the hole mobility increases in 2.5nm film under uniaxial compressive strain. 2.2

PMOS, 46/24

tcap = 2 nm

2.0 5.4 nm 1.8 1.6 1.4

"best SSDOI"

7.1 nm * reference is "universal" SOI 1.2 0.5 1 0 1.5 Hole density (× 1013 cm-2)

2

Electron mobility (cm2/Vs)

Figure 5. Mobility enhancement in HOI compared with the best SSDOI curve relative to the “universal” SOI mobility

TSOI = 2.3 nm 200

2% 5% initial (W/O stress) 0.083% <110> tensil 0.083% <110> compressive

100 0.1

0.2 0.3 0.5 0.7 1 Effective field (mV/cm)

2

Figure 6. Electron mobility in 2.3-nm ultra-thin-body MOSFET under <110> uniaxial strain

STATUS AND TRENDS IN SOI NANODEVICES

7

It has recently been shown that the use of a metal gate (TiN) can induce significant compressive stress along the channel direction. This stress is increased as the gate length decreases. This phenomenon progressively degrades electron mobility while hole transport is improved. Similar behaviors are obtained in single and double gate SOI devices, and the use of <110> channel orientation is the most favorable in terms of electrical performance [10]. Pure Ge channel MOSFETs are also considered as one promising option for future high performance CMOS. A compressively strained Ge channel is expected to further enhance hole mobility due to the very small effective hole mass [11]. Figure 7(a) shows the linear current of s-Ge PMOS with Hf02 gate dielectrics along with the Si control device. A 2.5x performance enhancement is observed (similar enhancement for the transconductance). For s-Ge P-type devices with SiO2 gate oxide, a 3x drive current and transconductance is obtained (Fig. 7(b)). 10

TMs-Ge/HfO2

2.5X

L = 10 µm VDS = -50 mV Remote Plasma Oxide

8 IDS (µA/square)

IDS (µA/square)

8 6

10

L = 10 µm VDS = -50 mV

4 2

6

~3X

s-Ge

4 Si control 2

Si/HfO2 control 0 -3

-2.5

-2

-1.5 -1 VGS (V)

-1.5

0

0 -3 -2.5 -2 -1.5 -1 -1.5 VGS (V)

0.5

(a)

0

0.5

1

(b)

SR limited mobility

(cm2/Vs)

Figure 7. a) Drain current of PMOSFETs with HfO2 gate oxide on 60% Ge channel formed by local thermal mixing compared with Si PMOS control with HfO2; b) Drain current of PMOSFETs with remote plasma oxide on 100% Ge channel formed by selective UHVCVD compared with Si channel PMOS control with the same oxide @Hole density 5×1011 cm-2 104

@Hole density 5×1011 cm-2 104

Si<110>

r6

dy T bo

e

103

y

d T bo

pow

6 er pow

Ge<111>

103

Si<111> Si<100>

Ge<100>

102

102 SILICON

2

Ge<110>

3 4 Body thickness (nm)

GERMANIUM 5

2

3 4 Body thickness (nm)

5

Figure 8. Simulated Surface Roughness limited hole mobility for Si and Ge with various orientations

8

STATUS AND TRENDS IN SOI NANODEVICES 600 <100> <110>

µ (cm2/Vs)

500 400 300 200 100 0 0

1.5

0.5 1 VG - Vth (V)

Figure 9. Electron mobility of FinFETs with <100> and <110> fin orientation. Tox=2nm, 4.5x1013 cm-2 channel implantation

The influence of surface roughness (SR) in ultra-thin films is very important. Figure 8 shows the SR limited hole mobility as a function of body thickness for Si (SOI) and Ge (GOI) channels. The variation of hole mobility is outlined for various surface orientations [12]. Figure 9 represents electron mobilities in FinFETs with various fin orientations. An improvement of electron mobility is observed for <100> and an enhancement of hole mobility has also been shown for <110> orientation [13]. 3. Comparison of the performance and physical mechanisms in multi-gate devices Multi-gate MOSFETs realized on thin films are the most promising devices for the ultimate integration of MOS structures due to the volume inversion in the conductive layer [14]. 0.7 LG

BR = ION/IBL

0.6 0.5 SOI DG 45 SOI DG 65 SOI DG 90 Bulk 65 Bulk 90 Bulk 130

0.4 0.3 0

50

100 150 DIBL (mV/V)

200

250

Figure 10. Ballisticity ratio at Vg=Vd=Vdd vs. DIBL. Filled symbols represent transistors with the nominal gate length for the high-performance MOSFET of each technology node

STATUS AND TRENDS IN SOI NANODEVICES

9

The on-current Ion of the MOSFET is limited to a maximum value IBL that is reached in the ballistic transport regime. Figure 10 reports the selfconsistent MC simulation of the ballistic ratio BR=Ion/IBL versus DIBL showing that one can increase the BR by scaling the gate length, thus increasing the longitudinal field at the source, but this comes at the cost of a larger DIBL. For a given DIBL, an increased ballisticity is obtained for low doping double gate SOI devices [15]. The transfer characteristics of several multiple-gate (1, 2, 3 and 4 Gates) MOSFETs, calculated using the 3D Schrödinger-Poisson equation and the Non-Equilibrium Green’s Function formalism for the ballistic transport or Monte Carlo simulations, have shown similar trends. The best performance (drain current, subthreshold swing) is outlined for the 4-gates (QG or GAA) structure [16,17] (Fig. 11). However, Fig. 12 demonstrates that the propagation delay in triple gate (TG) and quadruple gate (QG) MOSFETs are degraded due to a strong rise of the gate capacitance. A properly designed double-gate (DG) structure appears to be the best compromise at given Ioff [17]. 2500 2000

10 2 10 1

1500

TSi = 5 nm VGS = 0.7 V

SG

10 0

Drain current (A/m)

Drain current (A/m)

10 3

DG

1000

10-1 10-2 10-3

500

QG

TG

-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Gate voltage (V)

0

Figure 11. Id(Vgs) at Vds=0.7V in thin layers for different multi-gate architectures

Delay CGVDD/Ion (ps)

1.2 1.0

QG

Lch / TSi 15 nm / 10 nm 15 nm / 5 nm 25 nm / 10 nm

TG 0.8 DG 0.6 0.4 0.2 -3 10

QG

DG

10-2

QG

TG

TG SG SG DG

10-1 100 101 Current Ioff (A/m)

SG 102

103

Figure 12. Propagation delay versus Ioff for single-gate and multi-gate SOI devices

10

STATUS AND TRENDS IN SOI NANODEVICES

Figure 13 compares the calculated ballistic drive current for Si and Ge double-gate MOSFETs at the operation point of each generation as predicted by ITRS [18]. Si barely satisfies the ITRS requirement, whereas Ge offers much higher current drive. However, the simulated value of the real drain current of 2G SOI transistors is not able to satisfy the ITRS objectives, even for intrinsic devices without parasitic S/D resistances. 2G GOI MOSFETs are able to provide the needed current drive, but parasitic resistances drastically affect the drain current (not shown here). For a double gate device, the impact of a gate misalignment on the leakage current is important. This current is mainly due to GIDL. This off-current is enhanced with increasing the misalignment and it is higher for a shift of the bottom gate to the drain due to a larger Vgd compared to Vgs [19]. Drian current density (µA/µm)

5000 4000

GOI

3000 SOI 2000

ITRS'03

1000

10

20 Gate length (nm)

30

Figure 13. Ballistic drive current for different technology nodes for SOI and GOI devices

Off-state current (A/µm)

10- 5 10- 6 10- 7

simulations experience

FD

10- 8 10- 9 10-10 10-11 10-12 10-13 -20

0

20 40 Misalignment (nm)

Figure 14. Evolution of Ioff with misalignment (experimental and simulations results, Vd=1.2V). Single gate FD results are represented in dashed line

STATUS AND TRENDS IN SOI NANODEVICES

11

The impact of a gate misalignment is also significant for Ion in 2G MOSFETs [20]. A large back gate (BG) shift reduces the saturation current compared to the aligned case, whereas a slight BG shift towards the source increases Ion. This is due to a lower source access resistance. In terms of short channel effects, aligned transistors exhibit the best control while highly misaligned MOSFETs operate like single gate ones. Ioff is much more influenced by the misalignment than Ion due a degradation of the electrostatic control (Fig. 14). The oversized transistor shows attractive static performance (right hand side of Fig. 14) and a larger tolerance to misalignment but the dynamic performance is rapidly degraded as the overlap length increases. In decananometer MOSFETs, gate underlap is a promising solution in order to reduce the DIBL effect. Figure 15 presents the variations of the driving current, the subthreshold current and the gate direct tunneling current versus gate underlap [21]. The on-current is almost not affected by the gate underlap whereas the leakage currents are substantially reduced due to a decrease in DIBL and drain to gate tunneling current. A reduction of the effective gate capacitance Cg for larger underlap values at iso Ion has also been shown. This reduction of Cg leads to a decrease in the propagation delay and power. Multi-bridge-channel MOSFETs (MBCFET) present very high performance larger than those of GAA devices and exceeding the ITRS roadmap requirements (Fig. 16) [22].

10 - 2 Ion

log I (A/µm)

10 - 4 10 - 6 10 - 8 Isub 10-10 10-12

Igdt 0

2

4 6 8 10 Gate underlap (nm)

12

14

Figure 15. Ion, subthreshold (Isub) and gate direct tunneling (Igdt) currents as a function of gate underlap

12

STATUS AND TRENDS IN SOI NANODEVICES

BOX Figure 16. Schematic diagram of MBCFET on SOI 4

3

CNW CNT RNW FinFET

10 4

2

10 4 1 10-4

0

0.25

0.5 0.75 Gate voltage (V)

1

Electron density (107 cm-1)

Electron density (cm-1)

10 8

0

Figure 17. Electron density per unit length for various devices (FinFET, nanowires and carbon-nanotube FET). 65nm technology node data (EOT=0.9nm, tSi=5nm)

It is also interesting to compare FinFETs with cylindrical and rectangular nanowires and with gate-all-around carbon nanotubes – CNT-FET. It is shown that the CNT-FET exhibits superior performance (Fig. 17) due to electron charge confinement at the surface of the nanotube, whereas in the Sibased nanowires the charge confinement at the center of the wire is responsible for an additional depletion capacitance in series with the oxide capacitance, which reduces the overall effectiveness of the gate [23]. Finally, sub-10nm nanowires are compared for various channel materials and orientations using 3D quantum-mechanical simulations in pure ballistic regime [24]. Figure 18 shows the transfer current-voltage characteristics for a 9nm nanowire with a 4nm diameter, the gate workfunctions being adjusted to provide identical off-current. The Si and Ge nanowires provide similar on-current, whereas the GaAs nanowire suffers from a high source-to-drain tunneling in the subthreshold region leading to a smaller Ion/Ioff ratio.

STATUS AND TRENDS IN SOI NANODEVICES

13

Figure 18. Id(Vg) characteristics calculated for Si, Ge and GaAs gate-all-around nanowires oriented along the [100] direction, with 4nm wire diameter and 9nm gate length; 1nm gate oxide; Vds=0.4V

Figure 19. Id(Vd) characteristics calculated for n- and p-types Si nanowire FETs with four different channel orientations; 3nm wire diameter, 8nm gate length; 1nm gate oxide; Vds=0.4V

14

STATUS AND TRENDS IN SOI NANODEVICES

Figure 20. Id(Vd) characteristics calculated for Si and Ge nanowires FETs with [110] channel orientation; 3nm wire diameter, 8nm gate length; 1nm gate oxide; V ds=0.4V

In Fig. 19, the output Id-Vd characteristics are calculated using full-band simulations with a ballistic FET model for Si n- and p-type nanowire FETs with four different channel orientations, 8nm gate length and 3nm wire diameter [25]. Due to the behavior of the transport effective-mass and valley degeneracy, it is demonstrated that [110] is the best orientation for n- and p-channels that offers the highest Ion for the same off-current for this 3nm wire diameter. For this optimum channel orientation, Ge nanowires leads to an increase of Id between 30 and 40% for p- and n-type devices, respectively, compared to Si nanowires (Fig. 20). The variation of the intrinsic device delay with the wire diameter is shown in Fig. 21 for Si and Ge n- and p-type nanowires and various channel orientations [25]. P-channel nanowires displays a monotonically increasing speed with decreasing the wire diameter, while the performance of n-channel nanowires highly depends on wire orientation and material. 4. Advanced SOI DRAMs and NVMs It is becoming difficult for memories to be scaled down. Indeed, traditional embedded DRAM requires a complicated stack capacitor or a deep strench capacitor in order to obtain a sufficient storage capacitance in smaller cells. This leads to more process steps and thus less process compatibility with logic devices.

STATUS AND TRENDS IN SOI NANODEVICES

15

Figure 21. Intrinsic device delay as a function of wire diameter for n and p Si and Ge nanowires FETs with various channel orientations; 8nm gate length; 1nm gate oxide; Vds=0.4V

Capacitor-less 1T-DRAM or Floating body cells have shown promising results. The operation principle is based on excess holes which can be generated either by impact ionization or by Gate-Induced Leakage Current in partially-depleted SOI MOSFETs. The GIDL current is due to band-toband tunneling and occurs in accumulation leading to a low drain current writing and reduced power consumption together with a high speed operation. However, conventional PD SOI MOSFETs require high channel doping to suppress short-channel effects, which induces a degradation in retention characteristics. In order to overcome this problem, a DGFinDRAM has been proposed showing superior memory characteristics (Fig. 22) [26].

16

STATUS AND TRENDS IN SOI NANODEVICES

Drain current (µA/µm)

200 "0" state "1" state 150

VDS = 0.2 V VBG = 1.5 V

100

50

0 0.2

ID difference

0.4

0.6 0.8 Gate voltage (V)

1

Figure 22. Id(Vg) characteristics of the DG-FinDRAM

Conventional floating-gate flash memory has also scaling difficulties due to nonscaling of gate-insulator stack and inefficient hot carrier injection processes at sub-50nm gate dimensions. Back-floating gate flash memory overcomes these limitations by decoupling read and write operations and independent positioning and/or sizing of the storage element (back-floating gate) under the Si channel (Fig. 23). The charge in the back gate affects the field and the potential at the bottom interface and thus changes the threshold voltage of the device. The back-floating gate is charged by applying –10V to the source, the drain and the front gate simultaneously, and the charges are removed from the back floating gate (erasing) with the same method but with a bias of +10V [27]. Back-Floating Memory Gate Source

Read oxide Drain

Floating Substrate

Conventional Flash Gate Floating

Injection oxide Control oxide

Source

Drain Substrate

Figure 23. Cross-sections of back floating gate and conventional front-floating gate memories

STATUS AND TRENDS IN SOI NANODEVICES

17

5. Conclusion In this paper, a review of recent advances in the understanding of the sensitivity of electron and hole transport to the tensile or compressive uniaxial and biaxial strains in thin film SOI has been given,. The performance and physical mechanisms have also been presented in multigate MOSFETs and Nanowires realized with various channel materials and orientations. The impact of gate misalignment or underlap, as well as the use of the back gate for charge storage in double-gate nanodevices and of capacitorless DRAM have also been outlined. ACKNOWLEDGEMENTS

This work was partially supported by the European Network of Excellence SINANO (Silicon-based Nanodevices, FP6, IST-1-506844-NE).

References 1.

J.-P. Colinge, Silicon-On-Insulator technology: materials to VLSI (Kluwer Academic Publishers, 1991). 2. S. Cristoloveanu and S.S. Li, Electrical characterization of Silicon-On-Insulator materials and devices (Kluwer Academic Publishers, 1995). 3. F. Balestra, SOI devices (Wiley Encyclopedia of Electrical and Electronics Engineering, 1999). 4. J.J. Lee, J.S. Maa, D.J. Tweet et al, Mobility enhancement of SSOI devices fabricated with sacrificial thin relaxed SiGe, in: Proc. IEEE Intern. SOI Conf., (2004), p. 139. 5. M. Sadaka A.V.-Y. Thean, A. Barr et al, Fabrication and operation of sub-50nm strained-Si on Si1-xGex on insulator (SGOI) CMOSFETs, in: Proc. IEEE Intern. SOI Conf. (2004), p. 209. 6. T. Numata, T. Irisawa, T. Tezuka et al, Performance enhancement of partially- and fully-depleted strained-SOI MOSFETs and characterization of strained-Si devices parameters, in: Proc. IEDM (2004), p. 177. 7. J. Cai, K. Rim, A. Bryant et al, Performance comparison and channel length scaling of strained Si FETs on SiGe-on-Insulator (SGOI), in: Proc. IEDM (2004), p. 165. 8. I. Aberg, C.N. Chléirigh, O.O. Olubuyide et al, High electron and hole mobility enhancements in thin-body strained Si/strained SiGe/strained Si Heterostructures on Insulator, Proc. IEDM (2004), p. 173. 9. K. Uchida, R. Zednik, C.H. Lu et al, Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultra-thin-body SOI MOSFETs, in: Proc. IEDM (2004), p. 229. 10. T. Guillaume, M. Mouis, S. Maîtrejean et al, Influence of the mechanical strain induced by a metal gate on electron and hole transport in single and double-gate SOI MOSFETs, in: Proc. IEEE Intern. SOI Conf. (2004), p. 42. 11. H. Shang, Selectively formed high mobility strained Ge PMOSFETs for high performance CMOS, in: Proc. IEDM (2004), p. 157.

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12. T. Low, Impact of surface roughness on silicon and germanium ultra-thin-body MOSFETs, in: Proc. IEDM (2004), p. 151. 13. E. Landgraf, W. Rösner, M. Staedele et al, Influence of crystal orientation and body doping on trigate transistor performance, in: Proc. ULIS (2005), p. 15. 14. F. Balestra, S. Cristoloveanu, M. Benachir et al, Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance, IEEE Electron Dev. Lett., EDL-8, 410 (1987). 15. S. Eminente, D. Esseni, P. Palestri et al, Enhanced ballisticity in nano-MOSFETs along the ITRS roadmap: a Monte Carlo study, in: Proc. IEDM (2004), p. 609. 16. M. Bescond, K. Nehari, J.L. Autran et al, 3D quantum modeling and simulation of multiple-gate nanowire MOSFETs, in: Proc. IEDM (2004), p. 617. 17. J. Saint-Martin, A. Bournel, P. Dollfus, Comparison of multiple-gate MOSFET architectures using Monte Carlo simulation, in: Proc. ULIS (2005), p. 61. 18. A. Khakifirooz, O.M. Nayfeh, D.A Antoniadis, Assessing the performance limits of ultra-thin double-gate MOSFETs: Silicon vs. Germanium, in: Proc. IEEE Intern. SOI Conf. (2004), p. 79. 19. C. Yin, P.C.H. Chan, Characterization and edge direct tunneling leakage of gate misaligned double gate MOSFETs, in: Proc. IEEE Intern. SOI Conf. (2004), p. 91. 20. J. Widiez, F. Daugé, M.Vinet et al, Experimental gate misalignment analysis on double gate SOI MOSFETs, in: Proc. IEEE Intern. SOI Conf. (2004), p. 185. 21. A. Bansal, B.C. Paul, K. Roy, Impact of gate underlap on gate capacitance and gate tunneling current in 16nm DGMOS devices, in: Proc. IEEE Intern. SOI Conf. (2004), p. 94. 22. E.-J. Yoon, S.Y. Lee, S.M. Kim et al, Sub-30nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application, in: Proc. IEDM (2004), p. 627. 23. A. Marchi, E. Gnani, S. Reggiani et al, Investigating the performance limits of siliconnanowire and carbon-nanotube FETs, in: Proc. ULIS (2005), p. 99. 24. M. Bescond et al, Ballistic transport in Si, Ge and GaAs nanowire MOSFETs, in: Proc. IEDM (2005). 25. J. Wang et al, Bandstructure and orientation effects in ballistic Si and Ge nanowire FETs, in: Proc. IEDM (2005). 26. T. Tanaka, E. Yoshida, T. Miyashita, Scalability study on a capacitorless 1T-DRAM: from single-gate PD-SOI to double-gate FinDRAM, in: Proc. IEDM (2004), p. 919. 27. U. Avci, A. Kumar, S. Tiwari, Back-floating gate non-volatile memory, in: Proc. IEEE Intern. SOI Conf. (2004), p. 133.

NON-PLANAR DEVICES FOR NANOSCALE CMOS M.C. LEMME*, H.D.B. GOTTLOB, H. KURZ Advanced Microelectronic Center Aachen (AMICA), AMO GmbH, 52074 Aachen, Germany * To whom correspondence should be addressed: Max Lemme, tel.: +49-241-8867-207, fax: +49-2418867-571, e-mail: [email protected]

Abstract. In this paper, various concepts of multi-gate transistors are discussed with regards to their technological feasibility and manufacturability. In addition, non-standard fabrication process modules for triplegate nanoscale MOSFETs and sub-10 nm nanowires are presented. Alternatives to costly extreme ultraviolet (EUV) lithography are proposed as well as a self-aligned nickel silicide module to reduce inherent parasitic access resistances.

Keywords: SOI, FinFET, Tri-Gate, triple gate, Nano-CMOS, Nanowire

1. Introduction Moore’s Law1, the famous scaling rule-of-thumb turned dogma has been the dominating driver for the enormous success of the semiconductor industry for the last four decades. It was quickly and continuously transformed into a precise set of guidelines2,3,4 and is now manifested in the International Technology Roadmap for Semiconductors (ITRS)5, the benchmark against which any new development is judged. Today, physical gate lengths have reached dimensions in the 50 nm range, with gate oxide thicknesses well below 3 nm. At these dimensions, further performance gains through geometric downscaling are no longer viable. Instead, Moore’s law requires a host of innovative transistor architectures and the introduction of novel materials to continue on the path sketched in 1965. Silicon on insulator (SOI) material yields a number of potential advantages for nanoscale MOSFETs compared to bulk silicon. The list includes reduced parasitic capacitances and leakage currents, increased packing density, inherent ultra-shallow junctions or latch-up suppression. There is a number of excellent books that describe the advantages of SOI material and devices in great detail6,7,8. 19 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 19-32. © 2007 Springer.

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Fully depleted SOI transistors are of particular interest, as they exhibit near ideal device behavior and strongly reduced short channel effects. The first fully depleted SOI transistors were published in the 1980’s and these single gate devices promised already superior characteristics compared to bulk silicon MOSFETs 9,10,11 . Multiple gate SOI transistors have an even greater potential for short channel control. They enable ideal gate swings of S = 60 mV/dec even with undoped channels. This potentially results in higher carrier mobilities and higher drive currents. In addition, band-toband tunneling in extremely short devices can be avoided using undoped channels12. Finally, undoped channels will become a necessity as highly doped 10 nm devices would suffer from statistical variations in the number of doping atoms. Each doping atom would literally determine the threshold voltage and off-current of a transistor13. Therefore, multi gate FETs with undoped channels, where the switching behavior is governed by electrostatics and threshold voltages are adjusted through the gate electrode work functions can be considered the ideal switches for end of the ITRS CMOS circuits. 2. Multi gate SOI transistors The first double gate SOI MOSFETs, named XMOS, were proposed in 198414, with an experimental demonstration in 199015. Since then, a range of double and multi gate device architectures has been investigated, with a schematic overview shown in Figure 1. In this section, the different multi gate FETs are briefly described. In planar double gate MOSFETs, a second gate electrode is placed underneath the regular gate. The effective gate width is twice the transistor width. A clear advantage of this concept from a circuit point of view is its similarity to conventional SOI MOSFETs. Overlay accuracy of the two gates, however, is the major drawback of planar double gate devices. At nanoscale gate lengths, even a misalignment of only a few nanometers would render these devices unfeasible. While self-aligned fabrication processes have been proposed to overcome this limitation16,17 , these schemes increase the complexity and therefore the cost and reliability of the fabrication process. This could be a major obstacle in commercializing these devices. FinFETs are a variation of double-gate MOSFETs and consist of thin silicon wires (or fins)18,19 , typically with a height to width ratio greater than one. The gate stacks are fabricated on the sidewalls of the fins and the top of the fins is covered in a thick dielectric to keep it electrically inactive. The effective gate width of each fin is twice its height, and therefore limited by the initial top silicon thickness. The total gate width and the total drive

NON-PLANAR DEVICES

21

Figure 1. Schematic of multi gate SOI transistor concepts.

current can be controlled by using multiple parallel channels20,21. A possible disadvantage of FinFETs is their quantized drive current or device width quantization, as the total current is determined by the number of parallel fins22,23. Triangular gate MOSFETs, a variation of the FinFET concept, have been demonstrated experimentally24,25. However their manufacturability and CMOS process compatibility is not demonstrated on an industrial level. Triple gate or Tri gate transistors are related to FinFETs, but have an additional gate on top of the silicon wire26. The effective gate width of triple gate FETs is equal to the wire width plus two times the silicon thickness, as shown in the schematic in Fig. 2 (Weff = W + 2H). Triple gate FETs require only a moderate aspect ratio which translates into good manufacturability. The aspect ratio and the densities of wires can be carefully optimized to achieve higher circuit performance compared to planar devices27. Concerns about kinks in the subthreshold characteristics of triple gate devices due to a corner effect have been dismissed experimentally28,29 and through simulation30. Device width quantization on the other hand is of concern from a circuit point of view as in FinFETs.

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Figure 2. Schematic of a triple-gate SOI transistor with critical parameters.

Vertical multigate transistors have been considered for their potential to define the gate length by highly accurate thin film deposition methods such as molecular beam epitaxy 31,32,33, which can be controlled in the subnanometer range. In addition, three dimensional integration of vertical transistors has been proposed and demonstrated for memory applications34. For logic circuits, calculations show distinct performance gains by three dimensional integration35, but while experimental data is available from bonded multi-layer chips, the technological and design challenges for true 3D integration using vertical transistors seems overwhelming at this point in time. An extensive overview including a “family tree” of multi gate devices can be found in36 . 3. Future options for device fabrication Ultimately, the critical dimensions in non-planar, end of roadmap transistors will be in the range of 5 to 10 nm. Extreme UV (EUV) lithography with a wavelength of λ = 13.5 nm is an obvious option for such devices. The projected cost of EUV systems, however, may not permit their use for anything but very high volume memory and logic products. ASICs and other rather specific integrated circuits, which may well benefit from non-planar devices, could be denied this technology unless a low cost solution is found. Direct write electron beam lithography (EBL) and UVnanoimprint lithography (UV-NIL) are two contenders with a potential to deliver affordable processes for ultimately scaled MOSFETs.

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23

3.1. PROSPECTS OF ELECTRON BEAM LITHOGRAPHY

Electron beam lithography is a flexible method to fabricate structures and devices at the nanometer scale. It is widely applied to prototype and to evaluate nanoscale electron devices before conventional lithography methods are available. The application of e-beam lithography to production does, however, require the existence of high-throughput systems. Conventional Gaussian beam e-beam lithography systems use a highly serial technique to write patterns, but with limiting throughput. To overcome this obstacle several techniques to de-serialize the writing procedure have been proposed. Variable shaped-beam systems are already in wide use and offer the accuracy needed for the 32nm node37. Other solutions like cell-projection electron beam lithography38 or multi-beam approaches39 are still in a research and development phase. All these approaches have their special strengths and downsides. In order to utilize the full potential of electron beam lithography in the future, a careful choice of the adequate method will have to be made for each given application. Here, Gaussian beam e-beam lithography is used in an experimental CMOS process flow to demonstrate the benefits of triple gate control and to investigate the ultimate limit of scaling. Triple gate MOSFETs with different channel widths W and multiple parallel channels have been investigated. All devices have been fabricated on UNIBOND SOI material with various top silicon layer thicknesses tSi, buried oxide thicknesses of tBOX = 200 nm, gate oxide thicknesses of tox = 8 nm. The channels have been implanted and activated prior to structuring. A Leica EBPG-5000 e-beam system has been used to define the channel region40 with the negative tone e-beam resist hydrogen silsesquioxane (HSQ)41. The channels have been etched in a two-step process with an Oxford Plasmalab 100 inductively coupled plasma reactive ion etching system (ICP-RIE) using hydrogen bromide (HBr) based chemistry. The first step has been optimized for smooth vertical sidewalls, while the second step ensures a high selectivity of the silicon etch rate over BOX etch rate (50:1)42,43. Gate oxidation to tox = 8 nm has been followed by low pressure chemical vapor deposition (LPCVD) of tpoly = 100 nm undoped polysilicon. The gate electrode has again been defined by EBL (Leica EBPG 5000) with HSQ resist with modified parameters to account for the three dimensional topography. Etching of non-planar gate electrodes poses additional problems compared to planar technology. The selectivity of the polysilicon etch rate over gate oxide etch rate must be sufficient to allow for an adequate overetch to avoid the formation of parasitic spacers or the partial removal of the silicon source and drain leads (see schematic in Fig. 3).

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Figure 3. Schematic of undesired etching results in non-planar devices due to insufficient selectivity (after deposition (a), parasitic spacer (b) and removal of source/drain leads (c)).

The gate stack has therefore been patterned with a different HBr-based two-step process in the ICP-RIE system with an even higher etch selectivity. The source, drain and gate doping has been accomplished with a self aligned ion implantation and rapid thermal activation with temperature and duration depending on the respective n- and p-type dopants. A scanning electron microscope (SEM) image of a processed multi-channel triple gate MOSFET with L = 70 nm and W = 40 nm is shown in Fig. 4). Ultimate triple gate MOSFETs with dimensions below 10 nm are essentially gated silicon nanowires. It is an open question whether conventional, top-down fabrication methods can deliver such devices in an industrial scale, or whether bottom-up self-organized growth mechanisms can be maturated to the requireed degree. The limits of top down lithography have been explored by fabricating nanowires thin SOI material down to 7 nm. The process technology has been identical to the MOSFET fabrication descibed above, including the Leica EBPG 5000 e-beam system, HSQ resist and HBr-based reactive ion etching. An SEM image of a silicon nanowire with a width below 7 nm is shown in Fig. 5).

Source

BOX Gate

Drain Figure 4. SEM image of a multi-channel triple gate transistor (L = 70 nm, W = 40 nm).

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Figure 5. SEM image of a silicon nanowire fabricated with e-beam lithography.

3.2. FEASIBILITY OF UV NANOIMPRINT LITHOGRAPHY

UV-based nanoimprint is a low cost, high resolution nanolithography technique, which has recently been added to the ITRS roadmap as a contender for end of roadmap technology5. One of the crucial requirements for any such lithography is alignment accuracy of the different layers. To demonstrate the feasibility, functional triple gate MOSFETs have been fabricated, where both critical lithography steps for the top silicon wire and the gate electrode have been carried out by UV-NIL44. SOI wafers with a top silicon thickness of tSi = 40 nm and a buried oxide of tBOX = 400 nm have been implanted with a dose of 5e12 boron ions/cm² and annealed at 1000°C for 1h. UV-nanoimprint lithography has been used to define the transistor channels and alignment markers in layer 1. A 5 mm thick quartz mold with a diameter of 2.5 cm and a feature depth of 150 nm has been printed into the resist at a pressure of 300 mbar at reduced ambient pressure of 20 mbar45. The resist has then been cured in UV light and the mold has been detached. A CHF3-based reactive ion etching (RIE) process has been chosen to etch the residual resist layer, followed by an SF6/O2 process to form the silicon wires. The gate stack has been formed by thermal oxidation to tox = 8 nm and LPCVD of 100 nm undoped poly silicon. The poly silicon has been implanted with arsenic to 1e20 ions/cm². Lithography of the second layer has been carried out once more by UVnanoimprint with a 160 nm deep pattern of gate electrodes and level 2 alignment markers. Pre-alignment has been achieved with circular moiré markers to half of the interferometric grating pitch46. After coarse alignment, the maximum imprint pressure has been applied and a high precision interferometric technique with cross-gratings of 1 µm pitch in x- and ydirection has been used in contact for fine alignment. The alignment errors

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achieved after curing in UV-light are an order of magnitude lower than those achieved via optical markers. Again, the CHF3-based RIE process has been used to etch the residual resist layer, while the polysilicon gate electrodes have been etched with the highly selective HBr ICP-RIE process described elsewhere42,43. An implantation of arsenic followed by rapid thermal activation has resulted in a source and drain doping concentration of 2e20 ions/cm². Fig. 6 shows a scanning electron microscope image of a triple gate FET fabricated with two UV nanoimprint processes. The width of the silicon wire is W = 20 nm and the gate length is L = 200 nm. The misalignment of the gate electrode layer and the channel layer is below 20 nm. A detailed description of the fabrication process, the alignment routine and the UV-imprint process can be found elsewhere44,45. 3.3. SELF ALIGNED SILICIDATION

An inherent problem of nanoscale multi gate devices is their high parasitic access resistance. Simulations of such ultimately scaled devices have revealed that this leads to severely reduced on-currents and performance compared to theoretically achievable values47. Promising solutions to reduce the resistivity are raised source and drain areas manufactured by selective epitaxy48, by self aligned polysilicon49 or by self aligned silicidation50-52. Here, a self aligned nickel silicide process for source and drain leads of ultra thin body MOSFETs on SOI is investigated.

Figure 6. SEM image of a triple gate MOSFET fabricated with nanoimprint lithography.

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27

UTB MOSFETs have been fabricated using SOI-material with a 100 nm thick top-silicon film. After channel implantation to a concentration of 5e17 ions/cm³ and rapid thermal activation, the top-silicon layers have been thinned down to 80, 60, 30 and 15 nm using dry oxidation and subsequent HF wet etch. The channel has been etched with an HBr-based process in an Oxford Instruments RIE tool. An 8 nm thermal gate oxide has been grown and a 150 nm LPCVD polysilicon gate has been deposited. Similar to the triple gate FETs, a highly selective HBr etch process has been used to define the active gate areas42,43. Self-aligned arsenic source/drain implantations, tuned to correlate with the top-silicon-thicknesses, and rapid thermal annealing have been performed to achieve doping concentrations of 1e20 ions/cm3. A silicon nitride (Si3N4) spacer has then been formed by an LPCVD Si3N4-layer and subsequent highly anisotropic RIE etching with CHF3 and O2. A precise sputter process has been performed to deposit well controlled nickel films to match the respective top-silicon layers according to the reaction equation (1)51. 1 nm Ni + 1,84 nm Si –> 2,2 nm NiSi.

(1)

The NiSi has been formed by rapid thermal processing at 500°C and the unreacted nickel on buried oxide and the Si3N4 spacers have been removed by selective wet chemical etching. In Figure 7, an SEM image of a nickelsilicided MOSFET structure is shown. The source and drain of the transistor are fully silicided, while the thicker polysilicon gate is partially silicided, reducing the gate resistivity is as a beneficial side effect. If nickel silicide leads are to be used for ultimately scaled triple gate MOSFETs or FinFETs, they will have to withstand an extremely high current density. Current-voltage characteristics of NiSi nanowires have

Figure 7. SEM image of a nickel silicided MOSFET structure.

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2

current density J [A/cm ]

therefore been studied for various wire widths and lengths. As shown in Figure 8(a), NiSi nanowires exhibit ohmic behavior up to a certain current density, but are limited by destructive breakdown, indicated by the sharp current decrease. The SEM image in Figure 8(b) shows an example of a NiSi wire after destructive breakdown. Independent of device geometry, a typical maximum current density of J > 2·108 A/cm² has been reached, which corresponds well with results obtained from grown silicon nanowires53. In order to put the results for NiSi wires into perspective, we have compared them to on-current targets for future MOSFET generations defined in the ITRS. A rule of thumb for triple gate MOSFETs has been used to calculate current densities from on-currents: Triple gate transistors have been assumed to have equal values for with, height and length. The results are plotted in Figure 9 up to the 9 nm node, which translates into a current density of J = 1.2·108 A/cm² in 2020. Indicated by a black star, the maximum current density in NiSi exceeds ITRS requirements for final CMOS generations by a small margin. 8

5x10

8

8

4x10

8

3x10

FUSI NiSi Width: 36nm Heigth: 15nm Length: 90nm

2

Jmax = 3.8*10 [A/cm ]

8

2x10

8

1x10

0 0.0

0.2

0.4

0.6

voltage V [V]

0.8

1.0

Figure 8. Current density - voltage characteristic of a NiSi nanowire (a) and SEM image of an electrically destroyed NiSi nanowire. 8

2.0x10

this work: NiSi Jmax 8

2

J [ A/cm ]

1.5x10

8

1.0x10

7

ITRS HP devices

5.0x10

0.0 45

40

35

30

25

20

15

10

ITRS Tech. Generation [nm]

Figure 9. Comparison of maximum current densities of future technology generations derived from the ITRS with results obtained in this work.

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4. Conclusion The ITRS defines technology requirements until fifteen years from now and down to the sub-10 nm range. While it is questionable for economic reasons, whether electron devices with such dimensions will ever be mass produced, enabling technologies should be investigated today. In this paper, some options for future non-planar device architectures have been discussed with regards to their manufacturability. As EUV lithography may be only available to very few large companies, other less costly options may be considered. Direct write electron beam and nanoimprint lithography are therefore proposed to fabricate triple gate MOSFETs. In addition, parasitic source and drain access resistance may limit the performance of end-ofroadmap CMOS circuits. Nickel silicidation has therefore been investigated as one option to overcome this limitation. While some technological options for the final scaling chapters of CMOS have been suggested, the decision for or against such technologies will certainly be taken out of the hands of engineers and physicists and made solely based on economical reasoning. ACKNOWLEDGEMENTS The authors would like to thank their colleagues J. Bolten, T. Echtermeyer, J.E. Efavi, T. Mollenhauer, M. Schmidt and T. Wahlbrink for fruitful discussions and device processing. Financial support by the German Federal Ministry of Education and Research (BMBF) within the research projects “HSOI”, “KrisMOS” and “MINALI” is gratefully acknowledged.

References 1. 2. 3. 4. 5. 6. 7. 8.

G.E. Moore, “Cramming more components onto integrated circuits”, Electronics, 38(8), April 1965. s:R. H. Dennard, F. H. Gaensslen, L. Kuhn, H. N. Yu, “Design of micron MOS switching devices,” Tech. Dig. IEDM, 1972. G. Baccarani, M.R. Wordeman, R.H. Dennard, “Generalized Scaling Theory and Its Application to a 1/4 Micrometer MOSFET Design”, IEEE Trans. on Electron Devices, 31(4): 452-462 1984. P. Packan, “Pushing the Limits”, Science, (285), 1999. International Technology Roadmap for Semiconductors, “Front End Processes”, 2005 edition. J.-P. Colinge, “Silicon-on-Insulator Technology: Materials to VLSI, 3rd Edition”, Kluwer Academic Publishers, Boston, Dordrecht, London, 2004. S. Cristoloveanu, S.S. Li, “Electrical Characterization of Silicon-On-Insulator Materials and Devices”, Kluwer Academic Publishers, Boston, Dordrecht, London, 1995. J.B. Kuo, S.-C. Lin, “Low-Voltage SOI CMOS VLSI Devices and Circuits”, John Wiley & Sons, New York, 2001.

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31. J.M. Hergenrother et al., “The Vertical Replacement-Gate (VRG) MOSFET: A 50-nm Vertical MOSFET with Lithography-Independent Gate Length”, IEDM Tech. Dig., 7578, 1999. 32. A.C. Lamb, L.S. Riley, S. Hall, V.D. Kunz, C.H.d. Groot, P. Ashburn, “A 50nm channel vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket”, 31st European Solid-State Device Research Conference, ESSDERC 2001, 347-350, 2001. 33. J. Moers, S. Trellenkamp, L. Vescan, M. Marso, P. Kordoš, H. Lüth, “Vertical DoubleGate MOSFET based on epitaxial growth by LPCVD” 31st European Solid-State Device Research Conference, ESSDERC 2001, 191-194, 2001. 34. B. Goebel, J. Lutzen, D. Manger, P. Moll, K. Mummler, M. Popp, U. Scheler, T. Schlosser, H. Seidl, M. Sesterhenn, S. Slesazeck, S. Tegen, “Fully depleted surrounding gate transistor (SGT) for 70 nm DRAM and beyond”, IEDM Tech. Dig., 275-278, 2002. 35. A. W. Topol, D. C. La Tulipe, Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, M. Ieong, “Three-dimensional integrated circuits”, IBM J. Res. & Dev. 50(4/5): 491-506, 2006. 36. J.P. Colinge, “Multiple-Gate SOI MOSFETs”, Solid-State Electron, 48(6): 897-905, 2004. 37. I. Stolberg, P. Hahmann, J. Gramss, “Variable-Shaped-Beam Direct Writing In Semiconductor Manufacturing”, Semiconductor Manufacturing Magazine, April 2006. 38. Y. Sohda, H. Ohta, F. Murai, J. Yamamoto, H. Kawano, H. Satoh, H. Itoh, “Recent progress in cell-projection electron-beam lithography”, Microelectronic Eng., 67-68: 78-86, 2003. 39. T. H. P. Chang, M. Mankos, K. Y. Lee and L. P. Muray, “Multiple electron-beam lithography”, Microelectronic Eng., 57-58: 117-135, 2001. 40. B.E. Maile, W. Henschel, H. Kurz, B. Rienks, R. Polman, P. Kaars, “Sub-10nm Linewidth and Overlay Performance Achieved with a Fine-Tuned EBPF-5000 TFE Electron Beam Lithography System”, Jpn. J. Appl. Phys., 39: 6836-6842, 2000. 41. W. Henschel, Y.M. Georgiev, H. Kurz, “Study of a high contrast process for hydrogen Silsesquioxane as a negative tone electron beam resist”, J. Vac. Sci. Technol. B 21(5): 2018-2025, 2003. 42. M.C. Lemme, T. Mollenhauer, H. Gottlob, W. Henschel, J. Efavi, C. Welch, H. Kurz, “Highly selective HBr etch process for fabrication of Triple-Gate nano-scale SOIMOSFETs”, Microelectronic Eng., 73-74, 346-350, 2004. 43. T. Wahlbrink, T. Mollenhauer, Y.M. Georgiev, W. Henschel, J.K. Efavi, H.D.B. Gottlob, M.C. Lemme, H. Kurz, J. Niehusmann, P. Haring Bolivar, “Highly selective etch process for silicon-on insulator nano-devices”, Microelectronic Eng., 78-79: 212217, 2005. 44. A. Fuchs, M. Bender, U. Plachetka, L. Kock, T. Wahlbrink, H.D.B. Gottlob, J.K. Efavi, M. Moeller, M. Schmidt, T. Mollenhauer, C. Moormann, M.C. Lemme, H. Kurz, “Nano-wire FinFETs via UV-based Nanoimprint Lithography”, J. Vac. Sci. Technol. B 24(6): 2964-2967, 2006. 45. A. Fuchs, M. Bender, U. Plachetka, U. Hermanns, H. Kurz, “Ultraviolet-based nanoimprint at reduced environmental pressure”, J. Vac. Sci. Technol. B 23(6): 29252928, 2005. 46. K. Patorski, M. Kujawinska, “Handbook of the Moiré Fringe Technique”, Elsevier, Amsterdam, 1993. 47. S. Hasan, J. Wang, M. Lundstrom, “Device design and manufacturing issues for 10 nmscale MOSFETs: a computational study”, Solid-State Electron, 48(6): 867-875, 2004. 48. R. Chau, J. Kavalieros, B. Doyle, A. Muthy, N. Paulsen, D. Lionberger, D. Barlage, R. Arghavani, B. Roberds, M. Doczy, “A 50nm Depleted-Substrate CMOS Transistor (DST)”, IEDM Tech. Dig., 621-624, 2001.

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49. Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, C. Hu, “Ultrathin-Body SOI MOSFET for Deep-Sub-Tenth Micron Era”, IEEE Electron Dev. Let., 21(5), 2000. 50. F. Deng, R.A. Johnson, P.M. Asbeck, S.S. Lau, W.B. Dubbelday, T. Hsiao, J. Woo, “Salicidation process using NiSi and its device applications”, J. Appl. Phys., 81(12), 1997. 51. B. Froment et al., “Nickel vs. Cobalt Silicide integration for sub-50 nm CMOS”, 33rd European Solid-State Device Research Conference, ESSDERC 2003, 215-218, 2003. 52. M. Schmidt, T. Mollenhauer, H.D.B. Gottlob, T. Wahlbrink, J.K. Efavi, L. Ottaviano, S. Christoloveanu, M.C. Lemme and H. Kurz, “Nickel-Silicide Process for Ultra-ThinBody SOI-MOSFETs”, Microelectronic Eng., 82(3-4): 497-502, 2005. 53. Y. Wu, J. Xiang, C. Yang, W. Lu, C.M. Lieber, “Single crystal metallic nanowires and metal/semiconductor nanowire heterostructures”, Nature, 430(July): 61-65, 2004.

HIGH-κ DIELECTRIC STACKS FOR NANOSCALED SOI DEVICES S. HALL*, O. BUIU, I.Z. MITROVIC, Y. LU, W.M. DAVEY Department of Electrical Engineering & Electronics, Brownlow Hill, University of Liverpool, L69 3GJ UK *To whom the correspondence should be addressed: [email protected]

Abstract. The combination of ultra-thin body (UTB), undoped silicon-oninsulator films to control short channel effects and high permittivity (κ) gate dielectric with metal gate to control gate leakage current, can provide a highly scaleable technology to address challenges towards the end of the road map. This paper sets out the basic issues and physics associated with both hi- κ/metal gate and UTB from a device perspective, and establishes the advantages associated with merging the two approaches. A review of the state-of the art devices is undertaken also which serves to emphasize the great potential and progress of this technology.

Keywords: high-κ dielectric stacks, nanodevices, SOI

1. Introduction The silicon microelectronics revolution has been largely driven by continuing miniaturisation of the devices and associated interconnections as directed by Moore’s Law. The law predicts an exponential relationship between, for instance, the number of components on a chip with time. A number of related parameters such as delay and power consumption also follow the general trend. The industry has encapsulated these trends together with indications of solutions to potential roadblocks in the ITRS roadmap1. The roadmap document constitutes a reference manual which informs research directions for the community engaged in Si related research. The scaling of devices for the immediate future seems to be feasible with relatively conventional approaches together with the ‘technology booster’ of local strain to compensate for degradation in the charge carrier mobility which is incurred as a result of the channel engineering required to avoid excessive short channel effects (SCE). In particular, a 33 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 33-58. © 2007 Springer.

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nitrided silicon dioxide gate oxide of the order 1.5 nm can control adequately the electrostatic integrity of the MOSFET channel at least in the short term although there is a case for heavily nitrided silicon dioxide to further generations2. Looking then to subsequent generations, the gate oxide must become vanishingly thin; in fact, the ITRS roadmap predicts equivalent oxide thicknesses of 1 nm in 2007, reducing to 0.35 nm for the 22 nm node1. Notwithstanding other issues, at least three mono-layers of SiO2 are required so that ‘bulk’ like properties can be achieved giving a lower limit for the native oxide in any event, of about 0.7 nm3. Of course, such oxide thickness reduction comes at a price because the quantum mechanical current leakage through the gate becomes prohibitively high and so therefore is the stand-by power dissipation in chips which even now can contain a billion individual transistors. Moreover, the gate leakage must be reduced without compromising the current drive (ION) of the transistor therefore materials with higher dielectric constant (κ) are sought to allow a thicker oxide for the same gate capacitance, so mitigating the leakage problem. It is likely that hi-κ will enter the mainstream technology at the 45 nm technology node although there is a possibility also for a heavily nitrided SiO2 layer. Any replacement for silicon dioxide as a gate material must satisfy stringent requirements which can be summarised4 as relating to: a) thermodynamic stability in contact with Si; b) a high enough κ to warrant the cost of R&D – including a propensity to be scaled; c) band offsets for electrons and holes >1 eV which translates to band gap energies (Eg) > 5 eV taking into account the inverse relationship between Eg and κ; d) stability through a high temperature CMOS manufacturing process and finally, acceptable reliability and wear-out attributes to achieve industry standard product lifetimes, typically ten years. With these constraints in mind, the periodic table reveals, perhaps not surprisingly, relatively few contenders. In the short to medium term, taking account of ITRS performance requirements, the metallic oxide hafnium oxide (HfO2 or hafnia) is the main contender and its silicates and aluminates can reduce the tendency for crystallisation occurring at temperatures beyond about 450oC, at the expense of a slight reduction in the κ values. Looking at the requirements for the 22 nm node, contenders such as Pr, La look to be promising, while Gd, Ce and Sm oxides are also worthy of consideration in many respects. Alongside the challenges of the gate leakage, is the need to maintain the electrostatic integrity of the device; that is to say, the electric field imposed by the gate electrode must win in the competition with the drain field encroachment, to minimise undesirable short channel effects. Solutions require either double gate architectures such as the FINFET or fully depleted (FD), ultra-thin body (UTB) silicon-on-insulator (SOI) devices5,6. It has been

HI-κ AND UTB-SOI

35

proposed that the excellent electrostatic integrity brought with the FINFET architecture brings the potential for scaling to the 22 nm node whilst maintaining nitrided SiO2 for the gate oxide7. The FINFET however faces major challenges not least due to the challenges around the large parasitic source and drain series resistance. The UTB-SOI device with hi-κ gate oxide and metal gate then provides a potential solution for the 22 nm node and it is worth noting that a study is made in these proceedings whereby a comparison between bulk and UTB-SOI is made8. The paper is organised as follows. Section 2 describes briefly the dielectric physics underlying the increase of the permittivity, κ. The section also includes a brief summary of the metrology challenges for characterising these gate materials and a description of the enhanced charge trapping evident in the films. Section 3 includes a review of the hafnium oxide system which is the most widely studied material for this application. Hafnia has the disadvantage of relatively poor thermal stability in the context of a CMOS process. Introduction of either aluminium or silicon to form aluminates and silicates respectively allow higher thermal stability and a review of important results are presented in the section also. Section 4 includes consideration of some basic issues associated with the combination of hi-k gate dielectric and metal with UTB-SOI and also contains a review of state-of-the art results for this technology. The paper is concluded in section 5. 2. Physics and metrology of hi-κ dielectrics 2.1. DIELECTRIC PHYSICS

Figure 1, reproduced from Ref. 9, presents a useful description of the frequency dependence of the dielectric function over a wide range of frequencies. In general, the ‘zero frequency’ value of the dielectric constant can be seen to have two components: a ‘high – frequency’ one, where the contribution of electronic polarization dominates and one related to the ionic contribution10. In the CMOS frequency window, we can see that electronic and ionic processes contribute to κ and we consider that the permittivity is given by the relation:

ε ox = ε ∞ + ε latt

(1)

where εox is equivalent to κ. The electronic component, which arises from simple polarisation of the atoms, is the main component for SiO2 and the simple relationship n ~ ε ∞ links the refractive index, readily measurable

36

HI-κ AND UTB-SOI

Figure 1. The frequency spectrum of permittivity: εr’ is the real part and determines the gate capacitance, εr’’ is the imaginary part and reflects the losses in the dielectric layer9.

in ellipsometry, to the permittivity, giving ε ox ~ ε ∞ . The essence of increasing κ then is to choose materials that can contribute a large lattice component. Table 1 shows some values of these parameters for different crystalline forms of hafnia. We can see that εox can vary from less than 10 to about 25 depending on the crystalline form. Without going into details of the crystallography, we can simply make the point that the permittivity can vary over a wide range depending on the form of the material and hence the method used to prepare it. Furthermore, amorphous forms are preferred for processing in any event. The variability of κ with the structure of various metallic oxides is pointed out from another perspective in Ref. 11, by consideration of the Clausius-Mossotti (C-M) theory which links the κ to the polarizability α, and the volume of the unit cell, Vm as described in Eq. 2: TABLE 1. Differing structural forms of hafnia can result in wide variations of permittivity indicating the dependence on deposition process and subsequent manufacturing conditions Crystalline phase

ε∞

εlatt

εox (k)

c-HfO2 t-HfO2: parallel t-HfO2:perpendicular m-HfO2: yy m-HfO2: xx m-HfO2: zz m-HfO2:xz

5.37 5.13 5.39

20.80 14.87 27.42 10.75 11.70 7.53 1.82

26.17 20.00 32.81

⎛ 2 α ⎞ ⎜⎜1 + 4π ⎟ 3 V M ⎟⎠ ⎝ . εr = 1 α 1 − 4π 3 VM

(2)

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HI-κ AND UTB-SOI

In essence, larger atoms yield more polarization and hence higher κ values. The C-M equation reveals that κ raises steeply as the ratio α/Vm increases demonstrating the strong connection with the structure and nature of the material. The form of Eq. 2 is simplified so to illustrate the basic point and assumes homogeneity of the material but can readily be extended to encompass greater complexity of the dielectric layer morphology and related polarization phenomena9. A similar approach can be applied to the case of mixed oxides, i.e. MxOy+M’pOq, resulting in so called “additivity rule” where the polarizability of the mixed oxide MAxM’BpOay+Bq can be expressed as follows:

(

)

(

' α m M Ax M Bp O Ax + By = Aα m (M x O y ) + Bα m M 'p O q

)

(2a)

Using Eq. (2a) a similar expression for ε r of mixed oxides can be written, with Vm now being the volume of the complex molecule12. It is obvious that in such a case the dielectric constant of the mixed oxide has precise high and low limits, given by the dielectric constants of the oxides being mixed. However, there are situations when abnormal variations in the dielectric constant can result from molecular volume modifications induced during the alloying process especially when low and high coordination metal oxides are concerned (such as Hf and Zr oxides versus SiO2). 2.2. PARASITIC CHARGE AND RELATED METROLOGY CHALLENGES

A key advantage of the SiO2 system is the excellent electrical properties in terms of parasitic electron and hole traps. As-grown and appropriately annealed thermal oxide contains very low trap concentrations with relatively small capture cross-sections, which translate to time constants for oxide charging under normal operation. As well as being virtuous for integrated circuit engineering, the excellent and relatively stable intrinsic properties has made far easier the characterisation and study of the properties of these traps. Investigation of trapping in SiO2 has been a major activity for nearly 50 years. For the hafnia system, and some other high-κ dielectrics, electron trapping is extremely severe and a need arose for specialized measurement configurations to characterise the extremely fast trapping kinetics. Figure 2 shows a typical set-up of an analogue based technique whereby the drain current is monitored across a small drain load resistance and fed to an oscilloscope13 although the technique has been refined further14.

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Figure 2. Typical set-up to measure transfer characteristics of hi-k gate stack MOSFETs.

A study by Zhang15 illustrates effectively the trapping time constants and it can be seen that data capture of the order of 10’s of microsecond are required to capture the full extent of the trapping. Translating the timedependence of the voltage shifts with first order trapping theory reveals for as-grown electron traps, two effective capture cross-sections of the order of 10-15 cm2 with concentrations of the order of 1012 cm-2; these being very large values relative to SiO2. Considering an associated ‘capture radius’ of σ / π gives trap ‘sizes’ of the order of 2 nm which are only about a factor of two less than typical film thicknesses. Furthermore, the concentrations of defects imply average trap separations of a similar order. It’s worth noting also that breakdown in SiO2 occurs when defect levels rise to concentrations of this order with commensurate similarity in trap spacing. The propensity for percolation paths in such hi-k films is therefore high and the films are also likely to be more prone to parasitic stress-induced leakage currents. It is important to point out that such closely spaced traps makes the use of the first order trapping theory somewhat controversial. However, the values at least convey the rapid nature of the trapping and are useful for providing a representation of the time constants associated with the phenomenon. Other trapping studies show also that the films are rich in fixed positive charge with similar concentrations. It is possible also to create positive charge by stressing, with similar concentrations to the as-grown ones16. The measurements are usually carried out on MOSTs but there is a great advantage to employing MOS capacitors due to the simplicity of the structure. Capacitor based measurements can be employed for rapid screening of new materials. We have developed a novel measurement system based on pulsing MOS capacitors17 and is depicted in Fig. 3.

HI-κ AND UTB-SOI

39

Figure 3. The MOSC is pulsed from accumulation to deep depletion and as electrons are detrapped from the film, a positive charge centroid is developed which causes an undershoot in the capacitance transient.

Using this technique, which involves a deep-depleting voltage step, we can detect the presence of positive charge which would not readily be apparent from transistor based measurements which involve an inverted surface with a ready supply of minority carriers. Fast pulse techniques allow the C-V plot to be constructed to obviate the effects of electron trapping which compromises the standard, dc sweep technique18. 3. A review of hafnium oxide and its aluminates and silicates 3.1. HAFNIUM OXIDE

The hafnia system is the most widely studied and offers many of the necessary attributes in terms of both manufacture and electrical properties to satisfy the industry. It is likely to be adopted for low-stand-by power (LSTP) technology at the 45 nm node, by a number of companies. Hafnia is detailed in the various excellent reviews of hi-k dielectrics2,4,19,20 and in particular, generic challenges are described in Ref. 21. Surface preparation involving growth of a chemical oxide (SiOx) is paramount although this does add to the equivalent oxide thickness (EOT) and presents a scaling limitation. Problems of Fermi-level pinning between a poly gate electrode and the high-k film makes metal gate mandatory for this system to yield sub 1 nm EOT. Channel mobility is reduced significantly by the high levels of oxide charge and associated coulombic scattering: the remote charge scattering (RCS) effect. The large traps give rise to electron trap charging/discharging instabilities but these may be mitigated at very high digital switching speeds. Reliability issues are prevalent and in particular, as mentioned in section 2.2, SILC arising from the large traps in these thin films both as-grown and generated by voltage stress. The other key

HI-κ AND UTB-SOI

40

reliability issues such as negative bias instability and time-to-breakdown represent ongoing challenges. There is considerable evidence both experimental and theoretical, that the physical origin of the transient charge trapping behaviour in HfO2 may be attributed to oxygen vacancies since their energy levels appear above the silicon conduction band22. Using density functional theory methods, Gavartin et al.23 pointed out that negatively charged oxygen vacancies in HfO2 should be responsible for the trap discharging behaviours. This result is consistent with the electrical results observed by Ribes et al.24 who concluded that the threshold voltage, Vt instability is due to an equilibrium balance of electron tunneling from channel to traps and detrapping by Poole–Frenkel conduction towards the electrode although the basic model, shown in Fig. 4, was first proposed in Ref. 25 and further in Ref. 13. A trap level about 0.7 eV from the conduction band edge of the hafnia film was deduced in Ref. 25 whereas in the work of Ribes24 a trap energy of 0.35 eV was extracted. Both can be considered to link to negatively charged oxygen vacancies. Tse26 and Xiong27 respectively proposed strategies for the passivation of oxygen vacancies in HfO2, namely incorporation of fluorine and nitrogen. Their ab initio calculation showed that these two elements should be effective passivants for oxygen vacancies in hafnia. Another question associated with defects in HfO2 is their spatial distribution. Heh et al.28 applied the charge pumping technique to extract the spatial distribution of traps in SiO2/HfO2 gate stacks. They found that electron traps accessible by CP measurements are located within or near the interfacial SiO2 layer rather than in the bulk of the high k film. It is believed that hydrogen is also responsible for the anomalous positive charge creation in HfO2. Work by C. Zhao et al.16 demonstrated HfO2/SiO2 MOS transistors As-grown e-traps e Ec Ef Ev

EFm

Et=0.5∼0.8eV

e Et

Gate

HfO2

SiO2 Si

(a) e trapping at Vg>0

(b) e detrapping at Vg<0

Figure 4. Model for electron trapping in hafnia films with transitional layer25.

HI-κ AND UTB-SOI

41

with TaN electrode under positive stresses showed significant higher positive charge than those with poly-Si gate, which was presumed due to the higher density of hydrogen confined in the TaN gated devices. 3.2. ALUMINATES

It has been reported29,30 that the incorporation of Al into HfO2 forming a HfAlO alloy can greatly increase the crystalline temperature of HfO2. The inclusion of Al not only increases the thermal stability but also the band gap of the film, due to the large band gap (~9 eV) of Al2O331. Using spectroellipsometry we demonstrated that the band gap of HfAlO films deposited by MOCVD can be increased up to 7.9 eV with 38% Al32. All these features are achieved at the cost of lower dielectric constant. Our results33 showed that the dielectric constant of the layers deceased from 17 to 9, when the Al concentration increased from 4.5% to 38%. This result is consistent with the results of W. J. Zhu et al.34, who also reported the dielectric constant of HfAlO films (3 nm) deposited by Jet Vapour Deposition (JVD) decreased from 19.6 for HfO2 to 7.6 for Al2O3, while Al concentration varied from 6.8 to 31.7%. Uedono et al.35 conducted Doppler broadening spectra measurement of annihilation radiation and the lifetime spectra of positrons on HfAlO films (3–7 nm) deposited by ALD. The results showed intrinsic oxide traps attributed to strong oxygen deficiency in the layer. They pointed out that the oxide traps may induce additional leakage and therefore the advantages of larger band gap and thermal stability may be traded off. C. Driemeier et al.36 used nuclear reaction analyses and Rutherford backscattering spectrometry to investigate HfAlO films deposited by ALD. They found the

Figure 5. Variation in band-gap and permittivity with Al-concentration34.

42

HI-κ AND UTB-SOI

oxygen deficiency increases with increasing Al/Hf ratio and the oxygen deficiencies can be removed by a rapid thermal anneal in O2. M. H. Cho et al.37 carried out annealing studies in an NH3 atmosphere at 700°C for 60 s, of ultra thin (1.3 nm) HfAlO films deposited by ALD. They found that the near-edge x-ray absorption fine structure spectra of the HfO2 components remained the same while the spectra of Al2O3 were changed after the anneal. This result indicates that the change in the bonding characteristics as the result of N incorporation is mainly caused by N incorporation into Al oxide. An encouraging attempt of employing HfAlO as MOSFET gate dielectric was reported by M. Kadoshima et al.38. They successfully demonstrated the attainment of symmetrical threshold voltages in HfAlO based complementary MOSFETs by adjusting the Hf/Al ratio. They found that symmetrical Vt values could be obtained in HfAlO(N) MOSFETs with about 25 and 7% of Al for the poly-Si and single FUSI-NiSi gate electrodes, respectively. Successful integration of HfAlO/SiON stack as gate dielectric into a standard CMOS has been demonstrated by Torii et al.39. With 2.4 nm HfAlO on 1 nm SiO2 as gate dielectric, the transistor achieved encouraging properties such as low EOT (1.1 nm), low leakage (~10-2 A/cm2), low interface density (2x1011 eV-1cm-2), symmetrical threshold voltage and 92% electron mobility (Vg = 1.1V) compared to those for control devices with SiO2 gate dielectric. 3.3. SILICATES

Hafnium silicate films, (HfO2)x(SiO2)(1-x), are being studied as an alternative to pure hafnium oxide due to comparable advantages such as an increased crystallisation temperature19, stable amorphous structure40,41,42 which is resistant to oxygen diffusion40,19, reduced growth of interfacial layers at the silicon/high-k interface and higher values of bandgap and electron effective mass resulting in reduced leakage40. Hafnium silicate films do however have the disadvantage of a lower κ value (~11 – 15)43,44 than the pure oxide (~21 – 25)45,46 reducing the scalability of the material. Takeuchi and King in 200447 compared the compositional dependency of the electrical properties of hafnium silicate films from published studies and found a non-linear dependence of permittivity, decreasing with increasing concentration of incorporated silicon. The same work also reviewed experimental bandgap results for hafnium silicate films of varying composition and observed that the compositional dependence of the bandgap of hafnium oxide films has two distinct regions. The bandgap of hafnium silicate films decreases linearly at an approximate rate of 50 meV/% when the hafnium oxide content is increased, until the hafnium oxide content reaches 64%. At this stage the bandgap becomes independent

HI-κ AND UTB-SOI

43

of hafnium oxide content and stays constant at a value of 5.7 eV. The theoretical conduction and valence band offsets for an Hf0.5Si0.5O2 film were shown to be 1.5 eV and 3.4 eV respectively. Cho et al. (2005)48 studied the dependence of hafnium silicate phase separation on the composition of the film using XPS finding that a silicondioxide-rich hafnium silicate sample (x = 0.25) could withstand temperatures greater than 900ºC for 1 minute in a nitrogen ambient without phase separation but that a hafnium rich hafnium silicate sample (x = 0.75) phase-separates at a temperature of 800ºC. Thermal stability is a required property for high-k dielectrics due to current processes requiring the gate oxide to remain unaffected by an annealing temperature of 1000ºC for 5 s to activate the polysilicon gate49. Wilk, Wallace and Anthony (2000)50 were able to anneal silicon-rich (i.e., x = 0.2) hafnium silicate samples of thickness 3 nm for 20 s at temperatures of 1050ºC in nitrogen without visible grain boundaries formation and proposed the resistance to crystallisation may continue even for hafnium silicate films of hafnium content up to 30%. Nitrogen incorporation into hafnium silicate films is known to be beneficial to their electrical properties such as further increase of the phase separation temperature of hafnium silicates51, increased permittivity46 and reduced boron penetration52. Cho et al.48 annealed ~3.5 nm thick hafniumrich (x = 0.75) hafnium silicate samples for 1 minute at 900ºC in either NH3 or N2. The sample annealed in pure nitrogen was seen to contain monoclinic HfO2 grains, whereas the sample annealed in NH3 remained stable with no visible phase separation53. It was seen that annealing in both conditions caused an increase in the Si/high-κ interfacial layer by less than 1 nm, however annealing in N2 caused the growth of a 1.4 nm overlayer which increased significantly the effective oxide thickness (EOT) of the film. In the same paper, Results from 3 nm hafnium silicate samples of hafnium content (x = 0.5) annealed for 60s in either NH3 at a temperature of 750ºC or N2 at a temperature of 950ºC indicated that N2 increased the EOT compared to the as-deposited film whereas NH3 reduced the EOT. The samples annealed in N2 however had superior electrical qualities with leakage currents an order of magnitude (~10-9 A/cm2) lower than those of the NH3 annealed samples (~10-8 A/cm2) and a higher effective carrier mobility in transistors46. Nitrogen incorporation has, however, also been reported to reduce the conduction band and valence band offsets for a (HfO2)0.40(SiO2)0.60 by 0.33 eV and ~1.2 eV respectively and reduce the bandgap of the film by ~1.50 eV49. The reduction in band offsets is not serious enough to affect the viability of nitrogen incorporating films, however leakage current will increase through such a film.

44

HI-κ AND UTB-SOI

Figure 6. Optical band gap (a) and permittivity (b) for hafnium silicate concentrations.

In our own laboratories, (HfO2)x(SiO2)1-x/SiO2 (0<x<1) gate stacks grown by MOCVD at IMEC were investigated using spectroscopic ellipsometry and electrical characterization techniques54. The optical constants, thickness of the layers and optical bandgap for hafnium silicates of four concentrations were assessed using UV – NIR and deep UV spectral regions. The permittivity was seen to decrease from ~21 for HfO2 layer to ~8 for Hf-silicate with x = 0.3. The results suggest that Hf content above 60% is required to achieve technologically relevant permittivity higher than 10. Figures 6 show the optical band-gap and permittivity as a function of Si concentration, measured from a range of manufacturing techniques.

HI-κ AND UTB-SOI

45

4. Hi-κ on Ultra-thin body (UTB) SOI: Issues and review 4.1. ISSUES

SOI technology has a number of attractive advantages to replace bulk in certain areas and in particular the LSTP application. Firstly, the presence of the buried oxide results in low parasitic drain and source capacitance to substrate. Secondly, because most of the surface potential falls across the buried oxide, the sub-threshold slope is near to ideal and this translates into lower threshold voltage for the same IOFF as a bulk counterpart. A third main advantage is that the reduced surface field causes less confinement of the charge carriers to the interface between gate oxide and channel resulting in less surface scattering and hence higher effective mobility. These advantages need to be weighed against the disadvantages of increased substrate cost and circuit design challenges associated with floating body instabilities and, to a lesser extent, self-heating effects. A schematic diagram of an UTB FD-SOI device architecture is shown in Fig. 7. It is now well established that scaling SOI to decananometer channel lengths will require silicon film thicknesses of < 10 nm55,56; in fact, as a ruleof-thumb, the ratio of channel length, Lmin to SOI film thickness, tb needs to be Lmin/tb ~ 456 which leads to the need for ultra-thin Si films. Very high doping levels for adequate threshold voltage control are required if polysilicon gate electrodes are to be employed. Such high doping levels, in excess of 1018 cm-3, compromise performance in terms of channel mobility and adds to the other significant problem of poly-Si gate depletion. Furthermore, fluctuations in doping level and spatial location within the tiny

Figure 7. Schematic diagram of ultra-thin body SOI device illustrating key issues.

46

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volume of the channel will result in unacceptably large associated variations in threshold voltage as described in these proceedings57. In principle, these undesirable effects can be mitigated by the use of devices built on fully depleted, nominally undoped, ultra thin body (UTB) SOI films. For the same reasons as for bulk technology, the highly scaled SOI devices will require a hi-k metal gate to maintain gate leakage at an acceptable level. This requirement for a hi-k gate dielectric then provides further motivation to introduce also a metal gate electrode due to the incompatibility of poly-Si with hi-k materials such as HfO2. The use of an intrinsic channel and a metal gate both serve to reduce the influence of channel doping fluctuations on threshold voltage. Furthermore, symmetrical threshold voltages for both pchannel and n-channel devices can be realized if the Fermi level of the gate lies midway between the valence- and conduction-band edges of the silicon, that is, at midgap. We can observe also that the use of intrinsic channels and mid-gap metal gate removes the influence of silicon film thickness on threshold voltage, but not however on mobility especially as the film is scaled aggressively. A further major advantage of using metal gate with gate relates to its influence on mobility degradation due to soft optical phonons associated with the hi-k layer. The phonons arise from the very ionicity which gives rise to the higher k-value, making the degradation effect intrinsic to the system. These phonons can be considered as electrical dipoles which interact with channel charge carriers. The interaction constitutes additional surface phonon scattering mechanisms. For doped poly-Si gate, the gate doping influences the interaction causing further degradation for Npoly ~ 1018 cm-3 but recovering for doping 1020 cm-3. It has been shown however, that the metal gate is effective for screening this intrinsic phonon scattering and significant improvement in channel mobility has been measured58. The remote charge scattering effect (RCS), mentioned in section 3.1 may still cause mobility reduction. We have already stated that the reduced vertical electric field in UTBSOI MOSTs compared to bulk devices, brings an increase of mobility for ultra thin bodies and a detailed account is provided in these proceedings59. In particular for double gate SOI devices, the quantisation of charge carriers into the centre of the film means that mobility reduction associated with scattering at the hi-κ/Si interface is significantly reduced. The latter effect together with a quantum mechanical modulation of the carrier effective mass yields a distinct mobility enhancement. A comparison between symmetrical-gate and asymmetrical-gates was conducted in Ref. 60 wherein the superior performance of symmetric devices was shown. The Monte

HI-κ AND UTB-SOI

47

Carlo simulations demonstrated that electron mobility is mainly determined by the increase in the phonon scattering rate as the silicon thickness is reduced, that is, thinner films exhibit lower electron mobility, while velocity overshoot effects for ultrathin DG SOI inversion layers are dominated by the reduction of the average conduction effective mass, that is, the thinner the silicon thickness the higher the velocity overshoot peak. Thus this intrinsic property of enhanced mobility in FD-SOI can balance any reduction due to mobility degradation arising from the use of hi-κ which is known to yield a poorer interface with Si than the native oxide. However, as shown in Fig. 8, Monte Carlo simulation has indicated that for Si film thickness less than about 5 nm, the mobility falls of very significantly for both single and double gate devices due to enhanced scattering arising from acoustic phonon confinement caused by roughness of the two surfaces which can also be considered as film thickness variation in this context60. 600 Phonon+S.R.+Coulomb

Electron Mobility (cm2/V s)

400

200

E

EFF

=5x105 V/cm

0 375 DGSOI SGSOI

300 225 150 75 0

E 0

10

20

=1x106 V/cm

EFF

30

40

50

Silicon Thickness (nm) Figure 8. Monte-Carlo simulations showing mobility degradation with SOI film thickness (thanks to Prof. Gamiz for the data).

48

HI-κ AND UTB-SOI

Figure 9. Electron mobility versus effective field with SOI film thickness as a parameter, at 300K and 25K61.

Such a mobility reduction has been observed experimentally in Ref. 61 (and references therein). It was demonstrated61 that carrier scattering induced by the thickness fluctuations in films of less than 4 nm at room temperature is the dominant scattering mechanism at low temperatures. The effect arises from large potential variations due to the difference of quantum-confinement effects in different regions of the channel, which serve to scatter the carriers and so degrade the mobility. Ultra smooth interfaces are required to minimise the effects which may make a thickness ~4-5 nm a fundamental limit for practical UTB-SOI films. The experimental data is reproduced in Fig. 9. Such thin films however, lead to very high series resistances in source and drain regions62. The solution, as indicated in Fig. 2, is to incorporate raised source – drain structures possibly by selective epitaxy. This strategy is effective in maintaining drive capability but can introduce further problems in terms of fringing capacitance which will have an impact on speed63. The effect is exacerbated in devices with ultra short channel lengths and the rather thicker gate oxide thicknesses associated with hi-κ. The fringing capacitance influences the coupling from gate to source such

HI-κ AND UTB-SOI

49

that the barrier against carrier injection is lowered, that is to say, an additional short channel effect is imposed. A recent study has indicated that the phenomenon is no less severe for UTB-SOI with hi-κ and in particular an anomalous increase in gate-source capacitance is evident as the device enters saturation64. A compact model solution for fringing capacitance for UTB-SOI with hi-κ has been developed by Kumar65. A study of ultimate gate capacitance limits by Ge et al investigated the influence of inversion layer screening when the SOI film is thinned to be vanishingly small66. The choice of material for side-wall spacer is crucial in optimizing the gate stack for fringing capacitance as pointed out in Refs. 63-65. Spacer materials with low-κ need to be used to reduce this effect. A scaling study for UTB technology was presented in Ref. 67 and the key results are summarized in Fig. 10. It was demonstrated that an ultimate channel length of ~13 nm was achievable with tSi = 2 nm and κ = 15 ~ 20. Although the study indicates a fundamental physics limit, an SOI film thickness of 2 nm is probably not feasible due to both manufacturing considerations and also the mobility degradation phenomenon mentioned above for such film thicknesses. As pointed out in the study, film thicknesses of less than 2 nm would cause severe threshold voltage variations due to quantum confinement. The study by Engstrom reported in these proceedings8 indicates that a film thickness of 5 nm can be used with a hafnia gate oxide to provide a characteristic natural length (λ)55 of about 5 times the channel length which should ensure electrostatic integrity.

6.0

Vd2=1V, N+poly gates tBOX=100nm

5.5

Gate insulator thickness tI [mn]

5.0

4.0

3.0 2.5

I

Si

Lmin =20nm, undoped body and ε =3.9 I

Lmin =10nm, undoped body Lmin =15nm, varied Na

Vγ too high due to QM effect

Lmin =10nm, N =2.8x1019cm-3 a

Na=2.8x1019cm−3

2.0 1.5 1.0 0.5

=3.9

BOX

Lmin =15nm, undoped body

Na=3.5x1019cm−3

4.5

3.5

ε =35.1,ε =11.7,ε

Na=1.4x1019cm−3 Gate tunneling limit for εI =35.1 Gate oxide tunneling limit

0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Silicon film thickness t Si [nm]

Figure 10. Design space of sub-20-nm undoped and doped-body ultrathin gate oxide and high-κ gate insulator67.

50

HI-κ AND UTB-SOI

4.2. REVIEW OF THE STATE-OF-THE ART

Feasibility for integration of FD-SOI with hi-κ was presented for the first time in Ref. 68 and a micrograph of the structure is reproduced in Fig. 11. Both nMOS and pMOS devices were realised with channel lengths down to 50 nm; raised source and drain extensions were used to reduce series resistance. The films were undoped of thickness 14 nm and the gate stack comprised TiN midgap metal gate and 3 nm thick HfO2. This architecture produced symmetrical threshold voltages, at least in long channel nMOS and pMOS devices. Devices with channel length of 50nm and CET = 3nm, exhibited competitive performance with ION = 500 µm/µm for IOFF = 10 nA/µm with supply voltage of 1.2V for the nMOSFET and ION = 212 µA/µm for IOFF = 44 pA/µm at the same supply voltage, for the pMOSFET. Subthreshold slope values down to 77 mV/decade with DIBL of 70 mV/V were achieved together. Interface states were found to be high (mid 1011 cm-2eV-1) but an electron mobility only 15% lower than a bulk device equivalent was demonstrated, indicating the advantages of the lower surface field for UTB-SOI. Importantly, a hole mobility enhancement of 30% over bulk was achieved. The latter values were for long channel devices. The same team reported the use of a TaSiN gate oxide69 built on a gate stack with 1.2 nm transition layer and 3.5 nm HfO2. Long channel devices exhibited 62mV/decade subthreshold swing and +0.26V and -0.51V threshold voltages for nMOST and pMOSTs respectively. The results suggest a work function value of 4.4 eV for TaSiN. Interface state densities were gauged to be low 1011 cm-2eV-1 at both front and back interfaces. A gate leakage of 1 pA/µm2 was measured at (VT + 1V) with a 104 factor reduction compared to a poly/SiO2 stack. Some preliminary stressing experiments indicated +50 mV shift in VT (10 MV/cm for 100s at 300K)

Figure 11. UTB-SOI device with hi-κ gate stack and raised source and drains68.

HI-κ AND UTB-SOI

51

and no shift thereafter up to 1000s. This result is encouraging compared to that of poly-gate/HfO2. The ability to operate the devices over a range of temperatures without degradation was illustrated in the work of Ref. 70. In 2004, Thean et al.71 have also shown the feasibility to integrate HfO2 gate dielectric and metal gates with FD-SOI without adversely affecting the noise and reliability of the devices, while maintaining the benefits of undoped ultra-thin Si channel operation. The channel length was sub100nm. In 2005, Doris et al.72 at IBM, demonstrated a high performance FD-SOI replacement gate CMOS with HfO2/TaN gate stack formed totally by ALD. The work demonstrated good operation at LG = 22 nm with subthreshold slope, S= 95 mV/dec, DIBL = 200 mV/V @ VDS = 50 mV – 1V and with greater than 100 times reduction in gate leakage compared to a SiON/poly-Si control sample. A simple process that can tune the work function of ALD TaCN gate electrode on HfO2 from 4.47eV to 4.77eV by adding a CVD TiN overlayer is described in Ref. 73. Gottlob et al.74 described a ‘gate first’ platform process on SOI which allows for direct evaluation of hi-κ gate dielectrics. The gate stack is realised prior to lithography steps and the process therefore provides a rapid route to transistors and can be used for rapid screening of hi-κgate. The process has been demonstrated for gate lengths down to 40 nm on a fully depleted 25 nm thin SOI film. The process is particularly suited to epitaxially grown gate dielectrics as a perfect Si surface is presented at the growth stage and has been used to successfully integrate Gd2O3 into SOI MOSFETs74 and also into full CMOS75. Germanium on Insulator is also a proposed solution to maintain high channel mobility for ultimate scaling although there are many challenges around leakage, doping and other issues. The lack of a robust native oxide makes the use of a deposited hi-k

Figure 12. A gate first process for rapid screening of hi-κ gate stack MOSFETs74.

52

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gate material mandatory. Krishnamohan et al.76 have reported a study of high mobility UTB Ge SOI MOSTs and compared them with bulk counterparts. The tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunnelling (BTBT) leakage have been investigated. Strained SiGe MOSFETs having UTB of Ge less than 3nm, very high Ge fraction (~80%) channel and Si cap less than 3 nm have been successfully fabricated on thin relaxed SOI substrates. The fabricated device shows very high mobility enhancements of greater than a factor of 4 compared to bulk Si devices and 2.5 compared to strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and greater than 1.5 times that of 60% strained SiGe (on relaxed bulk Si) devices. The influence of statistical fluctuations even with undoped channels and metal gate should not be understated as it is likely to become the major obstacle along the roadmap and this has been demonstrated in a comparative study using statistical circuit simulation methodology, in these proceedings57. It is shown that the static noise margin for 6T SRAM cells based on 10 nm UTB SOI MOSFETs is more stable than the operation of cells based on 35 nm bulk MOSFETs. Therefore, the transition to UTB SOI technology could extend the benefits of SRAM scaling beyond the 25 nm technology node. However, the intrinsic parameter fluctuations introduced by discrete random dopants in the source/drain region in both single and double gate UTB SOI devices must be governed to warrant the introduction of these novel devices in the technology roadmap.

Figure 13. Static transfer characteristics of 200 statistical SRAM cells utilising 10 nm UTB MOSFET and 35 nm bulk MOSFET57.

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53

5. Conclusions We have presented an overview of the ultra-thin body SOI technology with hi-κ gate stack in the context of the Si roadmap. Pertinent points regarding dielectric physics, issues and challenges for realizing mature hi-κ gate stacks are made, leading into a detailed account of UTB-SOI technology. The inter-relation between materials, devices and associated electrical performance are discussed in some detail. Finally, the recent progress to date in UTB-SOI technology is presented both in terms of theoretical scaling studies and experimental devices. The feasibility for widespread adoption of the technology is fast emerging and the ability to realise electrostatic integrity at advanced technology nodes whilst maintaining acceptable drive currents makes it a very promising option. Perhaps most significantly, the increased immunity to atomistic level fluctuations compared to bulk device counterparts, particularly for embedded memory, may prove to be decisive in the wider adoption of the technology. ACKNOWLEDGMENTS

The work has been funded by EPSRC, UK with contributions from EU SINANO and PULLNANO. The authors acknowledge their collaborators within the SINANO framework for useful discussions. We also acknowledge IMEC (Belgium) for supplying silicate samples and Prof. Paul Chalker and Dr R. J. Potter of Liverpool University, Materials Science Division for the hafnium aluminate samples associated with our results within the paper.

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58. R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, High-k/Metal-Gate Stack and Its MOSFET Characteristics, IEEE Electron Device Letters 25(6), 408-410 (2004). 59. F. Gamiz, A. Godoy, J. Roldán, C. Sampedro, and L. Donetti, Charge transport in nanoscaled SOI devices, in: Proceedings of NATO Advanced Research Workshop, (Crimea, Ukraine, 2006), pp. 73-75. 60. L. Donetti, F. Gámiz, J.B. Roldán, and A. Godoy, Acoustic phonon confinement in silicon nanolayers: Effect on electron mobility, Journal of Applied Physics 100, 0137011-7 (2006). 61. K. Uchida and S. Takagi, Carrier scattering induced by thickness fluctuation of siliconon-insulator film in ultrathin-body metal-oxide-semiconductor field-effect transistors, Applied Physics Letters 82, 2916-2919 (2003). 62. S.-D. Kim, C.-M. Park, and J.C. Woo, Advanced model and analysis of series resistance for CMOS scaling into nanometer regime-part II quantitative analysis, IEEE Transactions on Electron Devices 49(3), 467-472 (2002). 63. N.R. Mohapatra, M.P. Desai, S.G. Narendra, and V. Ramgopal Rao, The Effect of HighK Gate Dielectrics on Deep Submicrometer CMOS Device and Circuit Performance, IEEE Transactions on Electron Devices 49(5), 826-831 (2002). 64. Y.-S. Lin, C.-H. Lin, J.B. Kuo, and K.-W. Su, Gate capacitances behavior of nanometer FD SOI CMOS devices with HfO2 high-k gate dielectric considering vertical and fringing displacement effects using 2-D simulation, IEEE Transactions on Electron Devices 53(6), 1373-1378 (2006). 65. M.J. Kumar, S.K. Gupta, and V. Venkataraman, Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs, IEEE Trans. on Electron Devices 53(4), 706-711 (2006). 66. G. Lixin, F. Gámiz, G.O. Workman, and S. Veeraraghavan, On the Gate Capacitance Limits of Nanoscale DG and FD SOI MOSFETs, IEEE Transactions on Electron Devices 53(4), 753-758 (2006). 67. W.-Y. Lu and Y. Taur, On the scaling limit of ultrathin SOI MOSFETs, IEEE Transactions on Electron Devices 53(5), 1137-1141 (2006). 68. A. Vandooren, S. Egley, M. Zavala, T. Stephens, L. Mathew, M. Rossow et al., 50-nm fully depleted SOI CMOS technology with HfO2 gate dielectric and TiN gate, IEEE Transactions on Nanotechnology 2(4), 324-327 (2003). 69. A. Vandooren, A. Barr, L. Mathew, T.R. White, S. Egley, D. Pham et al., Fully-Depleted SOI Devices With TaSiN Gate, HfO2 Gate Dielectric, and Elevated Source/Drain Extensions, IEEE Electron Device Letters 24(5), 342-345 (2003). 70. J. Pretet, A. Vandooren, and S. Cristoloveanu, Temperature Operation of FDSOI Devices with Metal Gate (TaSiN) and High-k Dielectric, in: Proceedings of ESSDERC (2003), pp. 573-576. 71. A.V.-Y. Thean, A. Vandooren, S. Kalpat, Y. Du, I. To, J. Hughes et al., Performance and reliability of sub-100nm TaSiN metal gate fully-depleted SOI devices with high-k (HfO2) gate dielectric, in: Symposium on VLSI technology (2004), pp. 106-107. 72. B. Doris, B. Linder, V. Narayanan, S. Callegari, E. Gousev, D.G. Park et al., Ultra-thin SOI replacement gate CMOS with ALD TaN / high-k gate stack, IEEE VLSI-TSA, in: International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers (2005), pp. 101-102. 73. Z.B. Zhang, S.C. Song, K. Choi, J.H. Sim, P. Majhi, and B.H. Lee, An Integratable Dual Metal Gate/High-k CMOS Solution for FD-SOI and MuGFET Technologies, IEEE International SOI Conference (2005), pp. 157-158.

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74. H.D.B. Gottlob, T. Mollenhauer, T. Wahlbrink, M. Schmidt, T. Echtermeyer, J.K. Efavi, M.C. Lemme, and H. Kurz, Scalable gate first process for silicon on insulator metal oxide semiconductor field effect transistors with epitaxial high- k dielectrics, Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures 24(2), 710-714 (2006). 75. H.D.B. Gottlob, J.K. Efavi, M. Schmidt, T. Wahlbrink, M.C. Lemme, H. Kurz, M. Czernohorsky, E. Bugiel, H.-J. Osten, and A. Fissel, CMOS integration of epitaxial Gd2O3 high-k gate dielectrics, Solid-State Electronics 50(6), 979-985 (2006). 76. T. Krishnamohan, Z. Krivokapic, K. Uchida, Y. Nishi, and K.C. Saraswat, High-mobility ultrathin strained Ge MOSFETs on Bulk and SOI with low band-to-band tunneling leakage: Experiments, IEEE Transactions on Electron Devices 53(5), 990-999 (2006).

NANOSCALED SEMICONDUCTOR HETEROSTRUCTURES FOR CMOS TRANSISTORS FORMED BY ION IMPLANTATION AND HYDROGEN TRANSFER VLADIMIR POPOV1*, IDA TYSCHENKO1, ALEXANDER CHERKOV1, MATTHIAS VOELSKOW2 1 Institute of Semiconductor Physics 630090 Novosibirsk, Russia 2 Institute of Ion Beam Physics and Material Research, 01314 Dresden, Germany * To whom the correspondence should be addressed: Vladimir Popov, Institute of Semiconductor Physics 630090 Novosibirsk, Russia; e-mail: [email protected]

Abstract. Bulk silicon devices are unlikely to be feasible for the planar 22 nm technological node due to commensurate degradation of carrier mobility. New types of substrate are therefore needed for further scaling in CMOS microelectronics. We consider here semiconductor heterostructure on insulator (HOI) which are compatible with current silicon planar CMOS technology. Specfically, we investigate effects associated with interface mediated endotaxial (IME) growth of thin semiconductor film at Si/SiO2 bonded interface which are experimentally observed and investigated for the first time. The semiconductor material stack was obtained by hydrogen transfer of one layer material (silicon) and a second one (germanium or indium antimonide) placed on amorphous silicon dioxide film. Firstly, thin film dual layer Si-Ge heterostructure properties were considered. Si-Ge HOI structures were obtained using Ge ion implantation into silicon dioxide followed by Ge segregation to the interface between the directly bonded silicon and silicon dioxide wafers. The method is also compatible with A3B5 thin film formation, as shown for an InSb film. Thermodynamic, kinetic and lattice mismatch parameter influences on IME process are considered.

Keywords: hydrogen transfer, silicon film, Si/SiO2 bonded interface, implanted impurities, segregation, endotaxy.

59 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 59-72. © 2007 Springer.

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1. Introduction Tera-scale integration of silicon CMOS transistors with channel length less than 10 nm is difficult due to decreasing carrier mobility, increasing leakage currents, and enhanced heat-generation resulting from the low dimensions. In the last few years, a number of structures that promote an increase in the carrier mobility in the channel were proposed. Examples are stressed siliconon-insulator films and a pure germanium channel instead of silicon. Integration of thin (a few nm’s) germanium or semiconductor compounds with silicon and silicon dioxide, promise to overcome the limitations of silicon based CMOS technology in volume production. Recent publications1-4 have shown that SiGe quantum well (QW) device structures have great advantages relative to volume silicon devices. The SiGe thin film dual channel (TF DC) MOSFET may provide even higher performance than that required for the current 45 nm technology node2. Other important aspects are concerned with the stress in such layers. As was published in a recent review4, correct tuning of stress for SiGe TF DC MOSFETs provides a factor of five times lower delay time for inverters with symmetrical electron and hole mobilities in comparison with pure silicon MOSFET inverters. Such tuning should be more easer for the case of TF DC SiGe on insulator than in the case of a buffer layer with stepped Ge distribution on bulk silicon. We have shown in earlier work5, that Ge accumulation and thin pure Ge layer formation takes place at the Si/SiO2 interface after Ge implantation into thermal dioxide, followed by a thermal anneal. We propose here the use of the hydrogen transfer of a Si layer onto a wafer implanted with Ge or other semiconductor ions. Bonding of the wafers produces a semiconductor heterostructure on insulator (HOI) using the transferred layer as a matrix for monocrystalline heterolayer endotaxy. Film growth may be mediated by implanted hydrogen and a vacancy-rich bonded interface. In this work, silicon-germanium (Si-Ge) heterostructures were produced by endotaxial growth of nanometer thick Ge layer at the bonding Si/SiO2. Properties of this Si-Ge Heterostructure on Insulator (HOI) are presented. Clear evidence for Ge film formation for the structures was obtained by XTEM and HREM methods as well as by RBS with channeling. Electrical measurements on test MOSFET structures also prove that a Ge nanolayer has been formed. We observe 20% higher hole mobility for a PMOSFET and Ge QW formation at the interface according to data from I-V and C-V measurements. The concept of Interface Mediated Endotaxy (IME) is also compatible with A3B5 heterolayer formation. The same experimental methods gave us evidence of InSb film formation by IME, despite the much lower melting

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61

temperature ~527oC than for Ge (938oC). But in the latter case, tensile strain in the top Si layer is needed to form the InSb film at the bonded Si/SiO2 interface. 2. Experiment and results 2.1. SI-GE HETEROSTRUCTURES ON INSULATOR

2.1.1. Experimental procedure The scheme used for formation of SiGe heterostructure on insulator (SGOI) was as follows. Ge ions were implanted with fluence in the range (0.51.5)x1016 cm-2 and energy 40 keV, into thermally grown silicon dioxide of 200 nm thickness on a handle wafer, prior to bonding. Then the transfer of the Si film on Ge implanted dioxide onto the handle wafer was made by direct bonding and slicing. Different thermal treatments of 700 to 1100oC in inert or oxidation atmosphere for times 0.5 to 5 hr were used after Si film transfer, to obtain the required Ge epitaxial layer thickness at the bonding interface. 2.1.2. Structural measurements by RBS and TEM Random and aligned RBS spectra (He+ ions, 1.8 MeV) were measured after thermal treatment at 700 to 1100oC for 1h. According to the spectra, there are no changes in the profile of Ge atoms, which cluster inside the buried dioxide layer at this temperature. Figure 1a shows the results of RBS with channeling measurements for the structures annealed at a temperature of 1000oC. The analogue spectra were obtained for the highest temperature of 1100oC, which is much higher than the melting temperature of 938oC for bulk Ge crystal. Approximately all the Ge atoms (>90%) at these temperatures are in regular positions for the upper Si lattice, and we observed by cross-section TEM (XTEM) and HREM (Fig. 1b), that in this case the thickness of the Ge containing film was about 1.3 nm, which is consistent with a pure Ge film. In the case of SiGe alloy, we expect a thicker layer but our previous results and those published in the literature, suggest that these alloys should have a Ge content close to unity. In order to investigate the electronic properties of our HOI structures, field effect transistors (FETs) were produced by a standard CMOS process The FETs were partially depleted with 0.5 – 5.0 µm channel length and a top silicon layer of 500 nm thickness6. A 20% higher hole mobility was obtained in the case of back side P-MOSFETs compared to transistors made on structures without an epitaxial Ge layer, as shown in Fig. 2a.

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The lower side electron mobility, which coincides with the interface, was about 25% lower for N-MOSFETs, possibly due to an increase in interface state density at the back gate.

Figure 1. RBS spectra (a) and cross-section TEM (HREM on insert) images (b) of SOI with Ge film with 1.5 nm thickness at Si/SiO2 interface after annealing at 1100oC 1 h.

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63

-5

x10

3

L/W=5/25 Wafer number: 1 2 / Ge

Ids, A

2 1

-120 -80 -40

Capacitance, pF

1.00

0 40 Vg, V

80 120

(a)

2

0.95 0.90 0.85

-40

1 -20

0 Voltage, V

20

40

(b)

Figure 2. Back side PD CMOS transistors Ids-Vg2 characteristics (a) and Cd-Vg2 characteristics (b) for transistor source (drain) region with (2) or without (1) 1.5 nm Ge film at Si/ SiO2 interface.

To prove this explanation, capacitance–voltage (C-V) measurements were made and the results are shown in Figure 2b. The C-V measurements revealed also the differences in Si-Ge HOI capacitances for the p- and n- doped top Si layer. In the first case, strong carrier accumulation was observed for large negative bias on the substrate while for the n- doped Si layer, we observed depletion at all negative biases. 2.1.3. Results The width of such Ge QW layers depends on the implanted Ge sheet concentration and the thermal budget which drives the Ge atom segregation

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NANOSCALED SEMICONDUCTOR HETEROSTRUCTURES

Ge atoms in epilayer, cm

-2

-14

10

Ge in Epilayer Linear Fit

-15

10

Ea = 3.73 ± 0.13 eV

8

9

10 11 -1 1/kT, eV

12

Figure 3. Monotonic temperature dependence with activation energy (Ea), determined by slope for lattice part of Ge atoms at Si/ SiO2 interface during 1h annealing.

and accumulation at the interface as well as subsequent diffusion into the cap Si layer. We have shown by RBS, that after the highest temperature annealing, the monocrystalline Ge layers with 1.0-1.5 nm thickness are formed between the transferred silicon layers and buried silicon dioxide films due to endotaxy and they are coherent with the crystalline lattice of top Si layer. According to the temperature dependence of the coherent part of the Ge atoms, measured by RBS with channeling and presented in Fig. 3, the activation energy Ea for Ge epitaxial growth is 3.7±0.1 eV. This value is quite different from the activation barrier for Ge atom diffusion through SiO2, which is very high7, but it is close to the wellknown barrier for diffusion of Si atoms through a Ge film8. This suggests that the possible driving force and mechanism for Ge endotaxy are governed by atomic Si diffusion through the interface into silicon dioxide to fill the voids therein, after the implantation. These voids can form after germanium nanocluster dissolution and Ge atom out-diffusion and segregation to the interface. Another explanation for the low Ea value relates to hydrogen induced enhancement of Ge atom diffusivity inside silica. 2.2. SI-INSB HETEROSTRUCTURE ON INSULATOR

2.2.1. Experimental procedure The scheme used for InSb HOI formation was the same as that for Ge. In and Sb ions were implanted with fluence (0.5-0.7)x1016 cm-2 and energy

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65

100 keV, into 200 nm of silicon dioxide thermally grown on the handle wafer. Bonding and then transfer of the Si film onto implanted dioxide on the handle wafer was made. Different thermal treatments of 500 to 1100oC in inert atmosphere for durations 0.5 to 2 h were used after Si film transfer to synthesise InSb semiconductor. 2.2.2. Structural measurements by RBS and TEM Random and aligned RBS spectra were also measured to identify the InSb distribution and crystalline properties. According to the spectra in Figure 4,

RBC Yield, counts

2000 Random Aligned

1000 o

Ta = 800 C 0

InSb S-32 200

400 Channels

600

(a)

RBC Yield, counts

2000 Random Aligned

1000

o

Ta = 900 C 0

InSb S-24 200

400 Channels

600

(b)

Figure 4. RBS/channeling spectra of SOI with InSb in buried oxide SiO2 (BOX) after annealing at 800oC (a) and 900oC (b).

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the InSb crystal region is coherent with the upper Si lattice but does not exhibit the monotonic dependence with temperature observed for Ge atoms (Figure 3). The InSb region is thin, grows slightly at 700oC, has its highest value at 900oC and practically coincides after annealing at 800 and 1100oC, in quantity and in form with most of the InSb atoms in the middle of BOX. There is a clear accumulation of InSb atoms at both interfaces at 900oC. RBS data are consistent with TEM/HREM cross-section images as shown in Figure 5. Many of the InSb nanocrystals are seen as bright spots on dark field images (Figure 5 b,c) with sizes less than 20 nm. They appear in the BOX with orientations differing from that of the upper Si lattice. They are partially coherent with the Si lattice only at the Si/SiO2 interface after annealing at higher temperature 900oC, as shown in Figure 5c). There is no evidence of InSb atoms at the Si/SiO2 interface after higher temperature anneals (1000 and 1100oC). All InSb nanocrystals with larger sizes (up to 30 nm) appear in the middle of the BOX, similar to the case at 800oC. The strong difference in behaviour of InSb in comparison with Ge atoms may be attributed to the extremely large lattice mismatch of Si and InSb atoms (>18%), whereas for Si and Ge lattices, this value is near to 4%. To increase the upper Si lattice parameter we use Sb implantation and solid state epitaxial regrowth of the upper Si layer prior to bonding. We suggest that this increase in Si lattice constant would serve to accommodate stress for the InSb film growth at the Si/SiO2 interface. All other treatments were the same as for the case of In and Sb ion implantation into BOX.

Figure 5. XTEM bright (a) and dark (b,c) field images of SOI with InSb atoms in buried oxide (BOX) after annealing at 800oC (a,b) and 900oC (c). Bright strip on image (b) is due to an InSb film incoherent with the upper Si lattice.

NANOSCALED SEMICONDUCTOR HETEROSTRUCTURES

67

RBC Yield, counts

2000 Random Aligned

1500 1000 500 o

InSb S-10 - 500 C 0

200

400

600

Channels

(a)

RBC Yield, counts

2000 Random Aligned

1500 1000 500 o

InSb S-10 - 500 C 0

200

400 Channels

600

(b)

Figure 6. RBS/channeling spectra of SOI with InSb in BOX and at upper Si/SiO2 interface after annealing at 500oC (a) and 800oC (b).

The RBS/channeling results are presented on Figure 6. Evidence of strong InSb accumulation at the upper Si/SiO2 interface is seen as a peak at channel number 750 on Figure 6b. In this case we observed a larger region (~30%) of InSb atoms coherent with the upper Si lattice; 5-7 monolayers of InSb film at the Si/SiO2 interface. The high resolution image of Figure 7a confirms this estimation. The InSb film looks like a dark strip of coherent atoms at the interface. Dark spots in the BOX are due to incoherent InSb nanoclusters near the interface. The HREM image in Figure 7b shows a transition from a flat to rough InSb film and a growth of strain in the Si crystal after higher temperature treatment at 900oC. Lose of pseudomorphism is also observed in thicker parts of the InSb film with the highest contrast.

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(a)

(b)

Figure 7. HREM image of SOI with InSb atoms at upper Si/SiO2 interface and in buried oxide SiO2 (BOX) after annealing at 800oC (a) and 900oC (b) for tensile strained upper Si layer.

Higher temperature treatments at 1000 and 1100oC completely destroy pseudomorphic InSb films and lead to semi-coherent InSb islands placed exactly at the top Si/SiO2 interface, as shown in Figure 8. The BOX and bottom Si/SiO2 interface are free from InSb nanoparticles, as shown on the XTEM and HREM images in Figure 8a. Semi-coherent InSb islands appear at both sides of the top Si/SiO2 interface and have (111) planes inclined from (111) planes of the upper Si layer with inter-plane spacing equal to 0.365 nm, which corresponds to the value for pure InSb. These InSb islands have elliptical form with dimensions 20-30 nm along the Si/SiO2 interface and 10-20 nm across, with moiré fringes on the Si side (Figure 8b). Incorporation of tensile strain into the top Si layer produces quite different InSb atom distributions including a thin pseudomorphic film in SOI structure as can be seen in Figures 5, 7 and 8. Semi-coherent InSb islands at the top Si/SiO2 interface, with different orientations with respect to top Si layer are also evident. This approach may be useful in the case of huge lattice mismatch for HOI formation by an IME process.

(a)

(b)

Figure 8. Bright XTEM (a) and HREM (b) images of SOI with InSb nanocrystals at top Si/SiO2 interface after annealing at 1100oC during 1 h. Dark strip on image (b) is due to InSb lattice moiré fringes with Si.

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3. Discussion 3.1. THERMODYNAMICS AND KINETICS OF THE IME PROCESS

3.1.1. Thermodynamic and kinetic driving forces A monotonic increase in Ge film thickness for increasing growth time or temperature is not consistent with the disappearance of the InSb film for similar conditions. This disparity may be connected with the more thermodynamically stable configuration of Ge films at an Si/SiO2 interface compared to InSb. Consider thermodynamic quantities connected with new layer formation. It is known that for epitaxial growth of a new film in vapour or in liquid, that a stable layer requires that the following relationship between interfacial energies should take place (Frank – Van der Merwe growth): γBC > γAB + γAC ,

(1)

where γBC is an initial interface energy between B and C materials, and A is a new material with interfacial energies γAB and γAC between them. We suggest that the same relation is true for the case of endotaxy or oriented solid state regrowth without elastic stresses. According to the published data (see work9 and references therein), γBC (or interfacial Si/SiO2 energy) is equal to 1.44 J⋅m-2, γAB = 1.10 J⋅m-2 for the silicon-germanium interface, γAC ~ 0.8 J⋅m-2 for the germanium-silicon dioxide interface. These values do not satisfy the condition of Eq.1 suggesting that the driving force for Ge film formation is kinetic rather than thermodynamic. The observed dissolution of the Ge layer at longer annealing times supports this suggestion. Unfortunately, the interfacial energy data for InSb in the Si and SiO2 system is not complete in the literature so we cannot draw a conclusion about the mechanism, but it is clear that the preference for InSb nanocrystal growth within the BOX rather than at the Si/SiO2 interface may be due to the large lattice mismatch for pseudomorphic growth. 3.1.2. Phase transition during IME process We have mentioned before in Section 2.1.3, that Ge atom diffusivity in silica may be high due to the presence of hydrogen. Thus diffusion of Ge atoms in silicon may be a limiting factor for germanium segregation in silicon where the solubility is much higher. Accumulation of Ge atoms should take place at the Si/SiO2 interface causing melting of the SiGe alloy if the Ge content exceeds the equilibrium value for melting at a given annealing temperature. In the case of the Ge film melting, γAB , γAC should

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NANOSCALED SEMICONDUCTOR HETEROSTRUCTURES

fall to γAB =0.26 Jm-2 and γAC ~ 0.8 J⋅m-2 9, with the result that equation 1 is satisfied when the Ge film grows in liquid form. However this explanation is still not fully justified because we observed Ge film growth even at temperatures ≤900oC, which is much lower than the pure Ge melting temperature. We conclude that interface vacancies and implanted hydrogen mediated lowering of the interfacial energy may be responsible for the IME process. 3.2. ROLE OF STRESS IN THIN FILM GROWTH AND MOBILITY ENHANCEMENT

3.2.1. Lattice mismatch and metamorphic growth Pseudomorphic growth of a strained heterolayer of n monolayer (ML) thickness is thermodynamically favorable when the contribution of the elastic energy σ(n) to the total energy remains lower than that of the previous interfacial layer: γBC > γAB + γAC + σ(n),

(2)

If inequality 2 is not satisfied, metamorphic growth of an InSb film other than (100) silicon orientation is still possible. Such growth can be realised using patterned implantation or as a result of tensile stress in the top Si film. Even light tensile stress (a few percent) obtained by Sb implantation and solid state re-growth has allowed us to grow very thin (5-7 ML) InSb films at the moderate temperature of 800oC. Such tensile deformation can be introduced using a silicon nitride capping layer or silicide growth on a thin top Si layer. Metamorphic InSb nano-islands with other orientations than that of the Si can form during a high temperature treatment, by melting and recrystallization at the Si/SiO2 interface. 3.2.2. Mobility enhancement The trapping of negative charge by the Ge nanocrystals within the SiO2 layer was suggested as a possible reason for the observed effect of strong carrier accumulation6. Another explanation for this phenomenon is filling of the Ge QW layer by holes from the p- doped Si cap layer. The last explanation is more probable because in the case of n- doped silicon, carrier depletion was observed at the same fields even when the electrons were the majority carriers. This means that previously unexplained6 positive charge accumulation in dioxide with Ge nanocrystals, may be connected with Ge QW layer formation at the interface after high temperature annealing. Such a layer exhibits higher mobility for holes and may serve as a high mobility channel in the next generation of PMOS FETs. The InSb QW layer may be

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71

a promising candidate for increasing electron mobility for NMOS FETs using the dual channel structure proposed by Fitzgerald10. 4. Conclusion We proposed a simple CMOS compatible approach named Interface Mediated Endotaxy (IME) for heterostructure-on-insulator (HOI) formation. IME is based on ion-implantation of semiconductor elements and subsequent endotaxial synthesis of an interfacial heterolayer combined with a proximal silicon layer, transferred and placed above the synthesized heterolayer at the bonding Si/SiO2 interface. Such an approach allows the use of the cost-effective CMOS planar technology for high mobility dual channel or quantum well FETs based on SiGe HOI structures. We speculate that an upper Si film on a few nanometer thin A3B5 layer allows the use of semiconductor heterostructures for CMOS volume production. The dual channel device design proposed by E. Fitzgerald can be employed also in dual gate HOI FETs and will allow better tuned characteristics than the dual channel devices on bulk silicon with buffer layer. Results presented here allow us to conclude that the proposed IME method can be an attractive alternative for integration of germanium or other semiconductors into new generations of CMOS technological nodes. ACKNOWLEDGMENTS

The authors thank Olga Naumova and Daniel Nikolaev for their help in electrical measurements; Gregory Pokhil and Vladimir Fridman for RBS measurements.

References 1. 2. 3. 4. 5. 6.

C. W. Leitz, M. T. Currie, M. L. Lee, Z.-Y. Cheng, D. A. Antoniadis, E. A. Fitzgerald, J. Appl. Phys. 92, 3745 (2002). S. Takagi, T. Mizuno, T. Tezuka et al., N. Sugiyama, S. Nakaharai, T. Numata, J. Koga, K. Uchida, Solid-State Electronics, 49, 6844 (2005). Z. Cheng, J. Jung, M. L. Lee, A. J. Pitera, J. L. Hoyt, D. A. Antoniadis and E. A. Fitzgerald, Semicond. Sci. Technol., 19, L48 (2004). M. L. Lee, E. A. Fitzgerald, M. T. Bulsara, M. T. Currie, and A. Lochtefeld, J. Appl. Phys. 97, 011101 (2005). L. Rebohle, I. E. Tyschenko, J. von Borany, B. Schmidt, R. Grötzschel, A. Markwitz, R. A. Yankov, H. Fröb, W. Skorupa, Mater. Res. Soc. Symp. Proc. 486, 175 (1998). I. E. Tyschenko, A. A. Franzusov, O. V. Naumova, B. I. Fomin, D. V. Nikolaev, V. P. Popov, Solid State Phenomena, 108-109, 77 (2005).

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J. W. Fleming, S. R. Kurkjian, U.-C. Paek, Journ. Amer. Ceram. Soc., 68, C-246 (1985). 8. H. A. Bracht, H. H. Silvestri, E. E. Haller, Advanced diffusion studies with isotopically controlled materials (November 14, 2004); http://repositories.cdlib.org/lbnl/LBNL-56924. 9. Q. Xu, I. D. Sharp, C. W. Yuan, D. O. Yi, C. Y. Liao, A. M. Glaeser, A. M. Minor, J. W. Beeman, M. C. Ridgway, P. Kluth, J. W. Ager III, D. C. Chrzan, E. E. Haller, Phys. Rev. Lett. 97, 155701 (2006). 10. E. Fitzgerald. Dual layer Semiconductor Devices, (US Patent 6,974,735, December 13, 2005).

FLUORINE–VACANCY ENGINEERING: A VIABLE SOLUTION FOR DOPANT DIFFUSION SUPPRESSION IN SOI SUBSTRATES HUDA ABDEL WAHAB EL MUBAREK* AND PETER ASHBURN Nanoscale Systems Integration Group, School of Electronics and Computer Science University of Southampton, Highfield, Southampton, SO17 1BJ, United Kingdom * To whom correspondence should be addressed: H.A.W. El Mubarek, e-mail: [email protected], tel: +44 2380593777, fax: +44 2380593029

Abstract. This paper reviews progress in vacancy engineering using a silicon implant into SOI substrates and considers the prospects for vacancy engineering using fluorine implantation. Vacancy engineering using a silicon implant comprises a high energy silicon implant into an SOI substrate, to separate the excess vacancies in the SOI layer and the excess interstitials below the buried oxide. Results on vacancy-engineering show that a properly optimized high energy silicon implant is able to suppress boron transient enhanced diffusion. Results are also presented on the behaviour of fluorine in bulk silicon and it is shown that a high energy fluorine implant not only completely suppresses boron transient enhanced diffusion but also significantly reduces boron thermal diffusion. The suppression of boron thermal diffusion is due to the formation of vacancyfluorine clusters that form at approximately half the range of the fluorine implant. Finally, fluorine implantation is applied to SOI wafers, with the aim of separating the vacancy-fluorine clusters in the active layer from interstitial dislocation loops below the buried oxide layer. These results show a high energy fluorine implant into SOI substrates is also effective in suppressing boron diffusion.

Keywords: Vacancy engineering, Fluorine, SOI

1. Introduction Silicon-on-Insulator (SOI) substrates are rapidly replacing bulk silicon substrates and opening a wide range of novel applications. According to 73 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 73-87. © 2007 Springer.

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Soitec, SOI will enable a $12 billion share of the worldwide IC market in 2006 [1]. SOI substrates have been driven deep into petroleum wells in SOI-MEMS pressure sensors and flown high into the sky in commercial aircraft circuitry and even taken to Jupiter and Mars in radiation hard data acquisition systems by Honeywell [1]. SOI substrates are now in all the new major electronic games. Microsoft has signed a contract with Chartered Semiconductor to migrate the IBM and Microsoft designed SOI microprocessor used in the Xbox 360 to the 65nm process node in the first quarter of 2007 [2]. Strained SOI is rapidly evolving. Soitec have recently released news of the commercial availability of their global strained SOI substrates in both 200mm and 300mm wafer sizes [3]. These are being used in the recently reported Freescale’s 45nm node CMOS technology for low power portable gaming electronics applications [3]. The SOI substrates rapid overtake of the semiconductor market is creating an urgent demand for ultra shallow junction solutions for the next generation SOI CMOS devices. Applying a Si or Ge preamorphisation implant prior to the dopant atom implant followed by solid phase epitaxial regrowth (SPER) and dopant activation of the layer, has long been used as a solution to eliminate channelling of light atoms such as boron and to improve dopant activation. However, preamorphisation and SPER are not suitable for the current and future ultra thin SOI substrates, because of the limitation introduced by the minimum thickness of a silicon seed layer to allow regrowth of the SOI layer [4]. This paper reviews progress in techniques used to suppress dopant diffusion in semiconductors such as vacancy engineering and fluorine co-implantation. Recent results on the prospects for vacancy engineering using fluorine are also presented.

Figure 1. A schematic of the defects distribution in an SOI substrate after a vacancy engineering implant.

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2. Vacancy engineering using Si implantation Vacancy engineering is an alternative solution to the problem of dopant diffusion suppression, which is directly applicable to SOI substrates. The basic concept is by applying a high energy silicon implant into an SOI substrate prior to the dopant implant a vacancy rich layer is created in the SOI layer, which is separated from the deeper interstitial rich layer via the buried oxide as illustrated in figure 1. The first group to experimentally study the decoupling of the vacancy and interstitial rich regions of an implant using a buried oxide layer in an SOI substrate were Roth et. al. [5]. They used a 2MeV silicon implant in an SOI substrate, which positioned most of the excess interstitials below the buried oxide layer and reported a reduction in boron transient enhanced diffusion. However, it was not possible to clearly identify the role of the excess vacancies as the boron itself was implanted and introduced excess interstitials. Later on Venezia et. al. [6] repeated Roth’s experiment using epitaxially grown boron marker layers. This proved conclusively that excess vacancies were responsible for the reduction in boron TED. Figure 2 shows the simulated vacancy and interstitial distributions caused by a 1MeV silicon implant before (a) and after (b) a 600s anneal at 790°C, after Venezia et. al. [6]. This shows clearly the excess vacancies region in the SOI layer and the excess interstitials region below the buried oxide.

Figure 2. (a) Simulation of the vacancy and interstitial distribution created after a 1 MeV, 1016cm-2 Si+ implant. (b) Simulation of the vacancy and interstitial distribution created after a 1 MeV, 1016cm-2 Si+ implant followed by a 600s anneal at 790°C. After Venezia et. al. [6].

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The diffusion of the epitaxially grown six boron marker layers in the top SOI layer was used to study the effects of the Si implants on B diffusion. A low energy 40keV Si+ implant was used to introduce excess interstitials into the top SOI layer and hence induce boron transient enhanced diffusion similar to a B+ implant. As seen from figure 3 (a) there is enhanced diffusion in the first three boron marker layers which had a 40keV Si+ implant. Hence, the excess interstitials introduced by the 40KeV Si+ implant have caused boron transient enhanced diffusion. In comparison in figure 3 (b) when the material has been exposed to a 1MeV Si+ implant prior to the 40keV Si+ implant no excess boron diffusion is observed. Hence, the excess vacancies introduced by the 1MeV Si+ implant have completely eliminated the excess interstitials introduced by the low energy Si+ implant.

Figure 3. (a) boron SIMS profiles of marker layers implanted with 40keV, 5×1013cm-2 Si+ followed by a 600s anneal at 790°C. (b) boron SIMS profiles of marker layers implanted with 1 MeV, 1016cm-2 Si+ followed by a 600s anneal at 790°C with and without a 40keV, 5×1013cm-2 Si+ implant prior to the anneal After Venezia et. al. [6].

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Recently, Nejim et. al. [7] reported a study of vacancy engineering using a 1 MeV Si+ implant to suppress boron transient enhanced diffusion. Various B+ implant energies were studied both in bulk and SOI substrates. It was shown that complete TED elimination occurred at 10keV B+. As seen in figure 4, the combination of the 1 MeV Si+ implant and the 5keV B+ implant in the SOI substrate results in less diffusion compared with the bulk silicon. More recently, Smith et. al. [4] reported an optimised vacancy engineering Si+ implant condition of 300keV which is more suitable for

Figure 4. High resolution SIMS boron profiles of a 5keV B+ implant; after implant (S0), after implant and anneal in a bulk Si substrate (S1) and co-implanted with 1MeV 1×1016cm-2 Si+ implant in an SOI substrate after anneal (S14). After Nejim et. al. [7].

(a)

(b)

Figure 5. (a) B SIMS profiles after implant and after a 300keV Si+ implant and anneal at 700C. (b) Boron sheet resistance after implant and anneal, for B+ only, B+ and 300keV Si+ and B+ and 1MeV Si+ implanted samples. After Smith et. al. [4].

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industrial applications compared with the high energy Si+ implant. Boron activation with minimal diffusion was obtained annealing at 700°C as seen in figure 5(a). Sheet resistance measurements were reported, as shown in figure 5(b), the boron sample which had a 300keV Si+ implant has the lowest sheet resistance followed by the boron sample which had a 1MeV Si+ implant and the B+ only implanted sample. 3. Fluorine co-implantation Fluorine co-implantation is an alternative technique for boron diffusion suppression which is gaining a lot of interest. There have been several reports in the literature of fluorine co implantation suppressing boron transient enhanced diffusion [8-11]. Fluorine implantation has been applied to MOS transistors to reduce boron diffusion in critical areas of the source and drain [12] [13]. It was reported that fluorine implantation resulted in reduced junction capacitance, an improved Ion - Ioff trade-off [13] and improved threshold voltage roll-off characteristics [13]. Recently, we have reported silicon bipolar transistors with a record cut off frequency fT of 110GHz, which were fabricated using a high energy fluorine implant to suppress boron diffusion in the base [14]. 3.1. ELIMINATION OF BORON TED BY F+ IMPLANTATION

In this section we review our previous work on the elimination of boron transient enhanced diffusion and the suppression of boron thermal diffusion in silicon using F+ implantation as reported in [11]. As grown Annealed (P+& F+ implanted)

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Figure 6. Boron SIMS profiles of (a) P+ implanted and P+ & 2.3×1015cm-2 F+ implanted samples and (b) unimplanted and F+ implanted samples after a 30s anneal at 1000ºC in nitrogen. The as-grown boron profile is added for reference.

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Figure 7. Comparison of fluorine profiles before and after anneal for 30s at 1000°C in nitrogen for (a) the P+ & 2.3×1015cm-2 F+ implanted sample and (b) the 2.3×1015cm-2 F+ implanted sample . The corresponding annealed boron profiles are added for reference.

Figure 6(a) shows the effect of a 185keV, 2.3×1015cm-2 F+ implant on boron transient enhanced diffusion in samples implanted with P+. It is clear that there is dramatically less boron diffusion in the sample implanted with both P+ & F+. Comparing the boron profiles at a concentration of 1×1017cm-3, we observe that the diffusion of boron into the substrate in the P+ & F+ implanted sample (14nm) is 42nm less than that in the P+ implanted sample (56nm). Figure 6 (b) shows the effect of a 185keV, 2.3×1015cm-2 F+ implant on boron thermal diffusion in samples not given a P+ implant. It can be seen that there is considerably less diffusion in the sample implanted with F+ than in the unimplanted sample. Comparing the boron profiles at a concentration of 1x1017cm-3 we find that the diffusion of boron into the substrate for the F+ implanted sample (11nm) is 20nm less than that in the unimplanted sample (31nm). This indicates that the F+ implant has not only eliminated boron transient enhanced diffusion but has also dramatically reduced the boron thermal diffusion by 65%. Figure 7 compares the fluorine profiles of the (a) P+ & F+ implanted sample and of the (b) F+ implanted sample discussed in figure 6, before and after anneal at 1000ºC for 30s in nitrogen. The corresponding boron profiles are shown for reference. The annealed fluorine profiles of the P+ & F+ implanted sample and the F+ implanted sample are very similar. Both are considerably different than the as-implanted profile and show two broad peaks. The deeper broad peak lies within a depth range of 0.29µm to 0.73µm with a peak concentration of 8.31x1019cm-3 at a depth of 0.42µm for the (a) P+ & F+ implanted sample and with a peak concentration of 9.11x1019cm-3 at a depth of 0.43µm for the (b) F+ implanted sample. For the

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Surface

Dislocation loops

(a)

(b)

Figure 8. Cross sectional transmission electron microscopy micrographs of 2.3×1015cm-2 F+ implanted and annealed Si MBE layers (a) P+ & F+ implanted sample and (b) F+ implanted sample.

(a) P+ & F+ implanted sample; this peak almost coincides with the asimplanted peak concentration of 8.32x1019cm-3 at a depth of 0.42µm. The shallower peak lies between 0.055µm and 0.232µm, coinciding with the boron profile, and shows several small peaks. The integrated dose of the asimplanted fluorine SIMS profile is 2.3×1015cm-2 and the integrated fluorine doses after anneal are 1.5×1015cm-2 and 1.6×1015cm-2 indicating that 35% and 30% of the implanted fluorine has been lost during annealing for the P+ & F+ implanted sample and the F+ implanted sample respectively. The majority of the fluorine lost comes from the surface side of the fluorine peak, but there is also some loss of fluorine from the substrate side. Figure 8 shows cross sectional transmission electron microscopy micrographs of the P+ &F+ implanted sample (a) and the F+ implanted sample (b) after an anneal at 1000°C for 30s in nitrogen, samples discussed in figures 7(a) and (b) respectively. In both figures 8(a) and (b) the region from the surface to a depth of 0.29µm is smooth with no visible defects and a band of dislocation loops is seen from a depth of 0.29µm to a depth of 0.73µm, centred around the implantation range of 0.42µm. 3.2. EFFECT OF F+ IMPLANTATOTION DOSE ON BORON DIFFUSION

In this section we review our previous work on the effect of F+ implantation dose on boron thermal diffusion in silicon as reported in [15].

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Figure 9. Boron SIMS profiles in F+ implanted and unimplanted samples after a 30s anneal at 1000°C in nitrogen ambient. An as-grown boron profile is also included for reference. Results are shown for fluorine implantation doses of (a) 5×1014cm-2, (b) 9×1014cm-2 and (c) 1.4×1015cm-2.

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Figure 9 shows a comparison of boron SIMS profiles in F+ implanted and unimplanted samples after an anneal at 1000°C for 30s in nitrogen. The as-grown boron profile is also included for reference. Results are shown for fluorine implantation doses of 5×1014cm-2 (figure 9 (a)), 9×1014cm-2 (figure 9 (b)) and 1.4×1015cm-2 (figure 9 (c)). For the lowest fluorine dose of 5×1014cm-2 the fluorine implanted boron profile width (100nm) at a concentration of 1x1017cm-3 is 8nm wider than that of the unimplanted profile (92nm), perhaps indicating a slight enhancement in boron diffusion. The width of the boron profile of the 9×1014cm-2 fluorine implanted sample (92nm) is exactly the same as that of the unimplanted sample, indicating that the fluorine implant had no effect on the boron thermal diffusion. The width of the boron profile of the 1.4×1015cm-2 fluorine implanted sample (78nm) is 14nm less than that of the unimplanted sample (92nm) indicating that the fluorine has suppressed the boron thermal diffusion. The boron diffusion length into the substrate at a concentration of 1x1017cm-3 of the 1.4×1015cm-2 fluorine implanted sample (10nm) is 9nm less than that of the unimplanted sample (19nm) indicating a 47% reduction in thermal diffusion. The reduction in thermal diffusion in the 2.3×1015cm-2 fluorine implanted sample is 65%, as seen from figure 6 earlier. These results show that a critical fluorine dose between 9×1014cm-2 and 1.4×1015cm-2 is needed before fluorine shows a reduction effect on the thermal diffusion of boron in silicon at 1000°C and that the reduction in thermal diffusion increases as the fluorine dose increases. Figure 10 compares the fluorine SIMS profiles before and after an anneal at 1000°C for fluorine implantation doses of 5×1014cm-2 (figure 10 (a)), 9×1014cm-2 (figure 10 (b)), 1.4×1015cm-2 (figure 10 (c)) and 2.3×1015cm-2 (figure 10 (d)). The corresponding boron profiles are added for reference. For all the implanted doses the as-implanted fluorine profile is approximately gaussian with an implantation range of 0.41µm. For the lowest fluorine implantation dose of 5×1014cm-2, negligible fluorine is present (SIMS background level) in the vicinity of the boron profile after anneal. The majority of the fluorine is located in a broad double peak at a depth corresponding approximately with the range of the fluorine implant (0.41µm). This deep fluorine peak extends from a depth of about 0.3µm to 0.64µm. For a fluorine implantation dose of 9×1014cm-2, negligible fluorine is again visible in the vicinity of the boron profile, but a small shoulder can be seen on the surface side of the deep fluorine peak between about 0.22 and 0.28µm. This shoulder was not present for the lower fluorine dose of 5×1014cm-2 in figure 10 (a). For the highest fluorine dose of 1.4×1015cm-2, an additional shallow, fluorine peak can be clearly seen in the vicinity of the boron marker layer, extending from about 0.07µm to 0.22µm.

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Figure 10. Fluorine SIMS profiles before and after a 30s anneal at 1000°C. Boron profiles after anneal are also included for reference. Results are shown for fluorine implantation doses of (a) 5×1014cm-2, (b) 9×1014cm-2 and (c) 1.4×1015cm-2.

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The shape of this shallow fluorine peak is complex and comprises two small ripples at depths of 0.16 and 0.18µm. A substantial shoulder can also be seen at a similar depth as the shoulder seen in figure 10 (b) (≈0.220.28µm). The results in figure 6 show that the high energy F+ implant has not only completely eliminated boron transient enhanced diffusion, but has also given a substantial reduction in the thermal diffusion of boron. The results in figure 9 clearly show that no reduction of boron thermal diffusion is seen at F+ doses of 5×1014 and 9×1014cm-2, whereas significant reduction is seen at a F+ dose of 1.4×1015cm-2. Furthermore, the results in figure 10 show that a shallow fluorine peak is present in the vicinity of the boron marker layer for a F+ dose of 1.4×1015cm-2, but is not present for lower doses. Thus there is a correlation between the appearance of the shallow fluorine peak in the vicinity of the boron marker layer and the reduction of boron thermal diffusion. This reduction of boron thermal diffusion occurs above a critical F+ dose between 9×1014 and 1.4×1015cm-2. The shallow fluorine peak in figure 10 (c) lies at a depth of about 0.070.22µm, which corresponds to 0.17-0.53Rp, where Rp is the range of the fluorine implant. Simulations of vacancy and interstitial profiles after implantation [16] have predicted a vacancy-rich region extending from the surface to a depth approaching the implantation range, Rp, and a deeper interstitial-rich region peaking at a depth just beyond Rp. This indicates that the shallow fluorine peak lies in the vacancy-rich region of the damage profile. The presence of the shallow fluorine peaks in figures 7 and 10 (c) after anneal therefore suggests that fluorine has been trapped at defects created by the fluorine implant. The TEM micrograph in figure 8 shows no evidence of extended defects down to a depth of 0.29µm, and hence the trapping of fluorine at the shallow fluorine peak must be due to defects that are too small to resolve by TEM. There is considerable evidence in the literature for the formation of vacancy-fluorine clusters [17, 18] that are too small to resolve by TEM. Our results are consistent with this work, and hence we propose that the shallow fluorine peak is due to the trapping of fluorine at vacancy-fluorine clusters. The strong correlation between the suppression of boron thermal diffusion and the appearance of the shallow fluorine peak in the vicinity of the boron marker layer at a fluorine implantation dose of 1.4×1015cm-2 provides clear evidence that this peak is responsible for the suppression of boron thermal diffusion. The presence of vacancy-fluorine clusters in the vicinity of the boron marker layer would be expected to give an undersaturation of the local interstitial concentration, since any interstitials in the vicinity would be able to recombine and annihilate with vacancies at or near the vacancy-fluorine clusters. Since boron diffusion in silicon is mediated

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by interstitials, an under-saturation of the interstitial concentration would give rise to a suppression of the boron thermal diffusion. A comparison of the SIMS profiles in figures 7(a) and (b) with the TEM micrographs in figures 8(a) and (b) respectively, shows that the deep fluorine peak correlates with the band of dislocation loops. The deep fluorine peak extends from about 0.28µm to 0.70µm, which compares with the band of defects in figure 8 extending from about 0.29µm to 0.73µm. Given the location of the deep fluorine peak in the interstitial-rich region of the fluorine damage profile, we suggest that the deep fluorine peak is due to fluorine trapping at interstitial type dislocation loops. Interstitials trapped at these dislocation loops will not backflow to the boron marker layer as in the case of the P+ implant only and hence boron transient enhanced diffusion is suppressed. However, the presence of these dislocation loops in the depletion regions of a transistor could result in leakage which is detrimental for the device performance. Hence, we propose the combination of the two concepts vacancy engineering and fluorine co-implantation in SOI substrates. The aim is to separate the vacancy-fluorine clusters needed to suppress the boron diffusion from the potentially detrimental fluorine induced dislocation loops using the buried oxide layer of the SOI wafers as a barrier between the two regions. This will result in a vacancy-fluorine clusters rich SOI layer maximising dopant diffusion reduction for future ultra shallow junction device applications. 1.0E+20

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Figure 11. Boron profiles in SOI samples after a 10s anneal at 1000°C, comparison of profiles of unimplanted (no F), 185keV F+ implanted (185keV F) and 400keV F+ implanted (400keV F) samples. Results are shown for an implanted boron dose of 1×1014cm-2.

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4. Fluorine-vacancy engineering in SOI substrates Figure 11 shows boron SIMS profiles of 5keV, 1×1014cm-2 B+ implanted into SOI samples and annealed at 1000°C for 10s in nitrogen. Results are shown for an unimplanted (no F+ implant) sample and a sample implanted with 185keV F+. The boron profiles show that the 185keV F+ implant gives a significant suppression of the boron diffusion. The junction depths measured at a doping concentration of 1×1017cm-3 are 96nm for the F+ implanted sample, compared with 133nm for the unimplanted sample. This indicates that fluorine vacancy engineering is effective in SOI substrates in suppressing boron diffusion.

5. Conclusions A review has been presented of recent progress in vacancy engineering using silicon implantation into SOI wafers and fluorine implantation into both bulk and SOI wafers. The use of a 1MeV silicon implant creates excess vacancies close to the surface, which eliminate excess interstitials created by dopant and other silicon implants. High energy silicon implants into SOI wafers have the additional advantage of the separation of interstitial and vacancy defects by the buried oxide layer. Consequently excess boron diffusion in boron marker layers is eliminated. Results on high energy fluorine implantation into bulk silicon have been shown to completely suppress boron transient enhanced diffusion and also significantly reduce boron thermal diffusion. The boron thermal diffusion suppression has been explained by the creation of vacancyfluorine clusters in the vacancy-rich region of the fluorine damage profile. Fluorine implants into SOI substrates have the additional advantage that the buried oxide layer separates the vacancy-fluorine clusters from deeper lying interstitial dislocation loops. Hence, this technique is very effective in suppressing boron diffusion in SOI substrates. ACKNOWLEDGEMENTS

The authors acknowledge the European Union (SINANO Project) for partially funding this project. Dr. H. A. W. El Mubarek (Royal Academy of Engineering and EPSRC Research Fellow) wishes to thank the Royal Academy of Engineering and the Engineering and Physical Sciences Research Council (EPSRC) for funding her research.

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SUSPENDED SILICON-ON-INSULATOR NANOWIRES FOR THE FABRICATION OF QUADRUPLE GATE MOSFETS VIKRAM PASSI1*, BENOIT OLBRECHTS1, JEAN-PIERRE RASKIN1, JENS BOLTEN2, THOMAS MOLLENHAUER2, THORSTEN WAHLBRINK2, MAX C. LEMME 2, HEINRICH KURZ 2 1 Université catholique de Louvain, Microwave Laboratory, Maxwell building, Place du Levant, 3, B–1348 Louvain-la-Neuve, Belgium 2 Advanced Microelectronic Center Aachen, AMO GmbH, Otto-Blumenthal strasse 25, 52074 Aachen, Germany * Vikram Passi, Microwave Laboratory, Université catholique de Louvain, Maxwell building, Place du Levant, 3, B–1348, Louvain-la-Neuve, Belgium. E-mail: [email protected]

Abstract. Scaling of MOSFET physical dimensions is approaching the nanoscale regime, which causes increase of short-channel effects such that the electrical performance of classical MOSFET structure is becoming seriously degraded. The limits of silicon scaling have been the major challenge for technologists for the past years. With the 90 nm generation in production and despite many roadblocks, the latest International Roadmap for Semiconductors 2005 expects that CMOS can be scaled down to 16 nm, by introducing new transistor architectures and materials. In this paper, we propose fabrication of a non-classical device architecture namely the “Quadruple-Gate MOSFET” which is based on definition of narrow, suspended silicon fins defined by electron-beam lithography into the topsilicon film of a Silicon-on-Insulator (SOI) wafer.

Keywords: Electron-beam lithography, Quadruple-Gate, Silicon-on-Insulator

1. Introduction After over thirty years of downscaling for increased packing density and speed of operation, CMOS technology has survived the hardships and continues to lead technology in today’s era of Very Large Scaling Integration (VLSI). The limits of silicon scaling are the major challenge that 89 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 89-94. © 2007 Springer.

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technologists are facing today. The International Roadmap for Semiconductors (ITRS) predicts that MOS transistors in the year 2020 will have printed gate lengths of 9 nm1. Traditionally, the control of short-channel effects in bulk devices has been achieved with the use of thin gate dielectrics, reduced junction depths and channel engineering. All these parameters are approaching their physical limits, which will render further scaling of device dimensions difficult. The need arises therefore for new device architectures such as multiple-gate MOS (Double-Gate, FinFET, Pi-Gate and Gate-AllAround/Quadruple-Gate) and materials (high-k dielectrics and metal gates) along with the transition from bulk-silicon to SOI MOSFET. By such means it is hoped that Moore’s law can be continued. In this paper, we propose a fabrication method for a Quadruple-Gate MOSFET based on suspended silicon fins defined by electron beam (E-beam) lithography into the top-silicon film of an SOI wafer. Critical steps in the fabrication process are discussed. 2. Device fabrication A three-dimensional structure of suspended SOI nanowires which are the starting material for the fabrication of Quadruple-gate device is shown in Fig. 1a. Figure 1b shows the desired cross section of the suspended nanowires surrounded by silicon dioxide and a polysilicon gate. The complete process steps for the fabrication of quadruple-gate MOSFET are illustrated in Fig. 2 (a - l).

Figure 1. (a) 3-D structure of suspended SOI nanowires; starting structure for the fabrication of Quadruple-Gate device, (b) Cross section of silicon fins surrounded by the gate oxide and material gate

FABRICATION OF QUADRUPLE-GATE MOSFET

91

The starting SOI wafer is composed of a top-silicon layer of 145 nm, buried-oxide (BOX) of 400 nm and a silicon-bulk substrate of 800µm (Fig. 2a). The first step begins with the thinning of the top-silicon layer from 145 nm down to 50 nm using a pre-heated bath (75°C) containing a mixture of ammonium-hydroxide (20 ml), hydrogen-peroxide (160 ml), and water (1280 ml). After six thinning and cleaning steps the desired topsilicon thickness of 50 nm was achieved all over the wafer (Fig. 2b), as confirmed by ellipsometer measurement. After standard cleaning, the thinned wafer is spin-coated with hydrogen-silsesquioxane (HSQ) (Fig. 2c), a negative tone E-beam resist, and E-beam lithography is performed. After exposure and development of HSQ the structure looks like as presented in Fig. 2d. After the development of the unexposed resist, the top-silicon and buried-oxide are etched using HSQ as a mask (Fig. 2e and 2f ). The topsilicon layer is etched using HBr chemistry in a two-step process followed by partial buried-oxide (100 nm) etching using C4F82,3. Ellipsometry measurements were performed to confirm the thickness of the remaining buried-oxide which was measured to be TBOX = 298 nm.

Figure 2. Process flow for fabrication of Quadruple-Gate device

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FABRICATION OF QUADRUPLE-GATE MOSFET

The remaining BOX layer underneath the silicon fins is removed by a HF-5% dip for 30s. Silicon fins over the remaining BOX are completely suspended (Fig. 2g). Gate-oxidation and polysilicon deposition are then done followed by implantation of source/drain, deposition of passivation layer, definition of contacts and finally the metallization of contacts which are common CMOS process steps (Fig. 2h – 2k). Figure 2l shows the final device fabricated after the above mentioned steps. 3. Critical fabrication steps The critical steps in the fabrication process are: •

Silicon fins definition

•

Release of nanowires (fins)

•

Conformal deposition of polysilicon (future metal gates) around fins

•

Alignment of gates

3.1. SILICON FIN DEFINITION AND ETCHING

Tests were made on small samples to determine the dose of exposure (pads dose = 2700 µC/cm², fins dose = 2100µC/cm²), and definition of silicon fins with the desired widths and spacing between them. Silicon fins of 50 nm width and a spacing of 300 nm and 500 nm were defined. Figures 3a and 3b show silicon fins of 50 nm width (Wfin) and spacing (Sfin) of 300 nm and 500 nm, respectively. 3.2. RELEASE OF SILICON FINS

After the removal of the oxide between the fins using RIE etching, the remaining oxide under the fins has to be removed using wet etching. This

Figure 3. Nanowires with desired fin width and spacing

FABRICATION OF QUADRUPLE-GATE MOSFET

93

was done by placing the samples in HF-5% for 30s. The fins were completely suspended over the remaining buried-oxide. There is an overetch (the lighter area in Fig. 4a) of almost half the fin width, which is not significant in long channel devices, but for deep submicron devices, this etch can result in poor device performance. This problem can be avoided by the use of implantation and highly selective etching of implanted oxide4. Figures 4a and 4b show the damaged silicon fins due to Nitrogen blow drying, and undamaged fins, dried using a critical point drying machine, respectively. 3.3. CONFORMAL DEPOSITION OF POLYSILICON AROUND FINS

Filling of buried cavities by polysilicon for building planar double gate devices was already demonstrated in5, as shown in Fig. 5a. In Fig. 5b, we can see the polysilicon deposited over the oxidized silicon fins.

Figure 4. Suspended nanowires over remaining BOX

Figure 5. Conformal deposition of polysilicon around oxidized fins

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FABRICATION OF QUADRUPLE-GATE MOSFET

3.4. ALIGNMENT OF GATES

Misalignment occurs when multiple lithographic steps are performed to define the gate. This can be avoided with the use of implantation to tune the oxide etch rate. The use of vapour HF (VHF) to selectively etch implanted oxide combined with damascene gate definition could avoid misalignment problems that occur from lithography4. 4. Conclusion In the race to follow Moore’s law, a novel fabrication process for a multiple gate device is proposed. The device is a quadruple gate MOSFET and critical steps of fabrication are discussed. Pictures showing the process steps performed so far are presented. Critical point drying was used to carefully release the silicon fins without damage. An improvement in the process by avoiding etching under the source and drain pads is proposed. The use of multiple gate architectures along with high-k dielectric and/or metal gates can extend the lifetime of silicon CMOS in the coming years. ACKNOWLEDGEMENTS

The authors would like to acknowledge the European Network of Excellence SINANO for funding and the cleanroom staff at UCL for their support. References 1. 2.

3.

4. 5.

International Roadmap for Semiconductors. M. C. Lemme, T. Mollenhauer, W. Henschel, T. Wahlbrink, M. Baus, O. Winkler, B. Spangenberg, H. Kurz, “Subthreshold Behavior of Triple-Gate MOSFETs on SOI Material”, Solid State Electronics, 48(4), 529-534 (2004). M. C. Lemme, T. Mollenhauer, H. Gottlob, J. Efavi, C. Welch, H. Kurz, “Highly Selective HBr Etch Process for Fabrication of Triple-Gate Nano-Scale SOI MOSFETs”, Proceedings of Microelectronics Engineering, 72-73, 346-350 (2004). R. Charavel, J.-P. Raskin, “Etch Rate Modification of SiO2 by Ion Damage”, Electrochemical and Solid State Letters, 9, G245-248 (2006). T. M. Chung, B. Olbrechts, J.-P. Raskin, D. Flandre, Planar Double-Gate SOI MOS Devices: Fabrication by Wafer Bonding over Pre-Patterned Cavities and Electrical Characterization, in Proceedings of EUROSOI (2006), pp. 111-112.

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Physics of Novel Nanoscaled SemOI Devices

INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS OPERATING AT ROOM TEMPERATURE TOSHIRO HIRAMOTO* Institute of Industrial Science, University of Tokyo, Japan Collaborative Institute for Nano Quantum Information Electronics, University of Tokyo, Japan * To whom correspondence should be addressed. Toshiro Hiramoto, Institute of Industrial Science and Collaborative Institute for Nano Quantum Information Electronics, University of Tokyo, 4-6-1, Meguro-ku, Tokyo 153-8505, Japan; Email: [email protected]

Abstract. Recent research and development of silicon single-electron transistors are reviewed. The fabrication process of extremely small silicon dot in the channel of MOS transistors has been advanced, and the dot size is now as small as 2 nm. Consequently, the single-electron transistors operate at room temperature and the peak-to-valley current ratio of the Coulomb blockade oscillations reaches as high as 480 at room temperature. The attempts to integrate the single-electron transistors and to develop new circuit applications are also described.

Keywords: Coulomb blockade, quantum effect, quantum dot, single electron, resonant tunneling, CMOS, MOSFET, nano device

1. Introduction The metal-oxide-semiconductor field-effect transistors (MOSFET) that compose very large scale integrated circuits (VLSI) have been miniaturized to achieve higher integration, higher performance, lower power consumption, and lower cost for more than 35 years. The size of the state-of-the-art MOSFETs in mass production has reached less than 35 nm, and the MOSFETs will be further scaled down for even more performance of VLSI. Therefore, silicon MOSFETs are now in the nanometer regime. Although the VLSI technology has been generally called “microelectronics”, it should be called “nanoelectronics”. However, it is generally recognized that simple scaling of MOSFETs does not work in the nanometer regime. To enhance the performance of 97 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 97-112. © 2007 Springer.

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VLSI, new transistor structures and new materials for nanoscale MOSFETs have been widely studied and developed. These are the grand challenges in the development of silicon nanodevices. On the other hand, when the transistor size is in the nanometer regime, a lot of new physical phenomena, such as quantum effects and single-electron charging effects, are emerging. Some of these phenomena will have a unique feature in current-voltage characteristics that conventional MOSFETs do not have, and they appear even at room temperature when the transistor size is extremely small. When these physical phenomena are incorporated in VLSI, they offer the great potential to add new functionalities to future VLSI. One of the most promising new devices based on new nanoscale physics is the single-electron transistor (SET)1-2. A SET has an extremely small quantum dot in the channel. The number of electrons in the dot is precisely controlled by the Coulomb blockade, and a SET shows unique oscillatory I-V characteristics that are expected to have new functionalities. SETs have been studied using various materials, including metals,3-4 GaAs,5 carbon nanotube (CNT)6, and silicon7-8. Among them, silicon SETs are most attractive for future VLSI applications, because nearly all state-ofthe-art VLSI processes can be utilized to fabricate silicon SETs and silicon SETs may be easily integrated into conventional CMOS circuits.9 In this chapter, recent developments of silicon SETs are reviewed. Firstly, silicon nanodevices are classified in three categories and the position of SETs in these categories is discussed. Then, the development of the characteristics of silicon SETs is described. Special emphasis will be placed on the room temperature operation and the integration of SETs. 2. Position of SET in nanodevice categories 2.1. THREE CATEGORIES OF NANODEVICES

There are numerous types of nanodevices that have been actively studied. Figure 1 shows examples of nanodevices and their classifications. The horizontal axis is the approximate time when each nanodevice will be practically realized. Note that this figure illustrates the nanodevices in future VLSI for information processing applications; memory devices and interconnect technologies are not included.

INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS

99

Figure 1. Examples of nanodevices and their classifications. The horizontal axis shows approximate time when each nanodevices is practically realized.

2.1.1. CMOS extension In the near future, complementary MOS (CMOS) transistors will be certainly dominant in VLSI. New transistor structures, such as fully depleted (FD) silicon-on-insulator (SOI) MOSFETs and three-dimensional structures, and new materials, such as high-k/metal gate technology and Ge channel, are the promising technologies. Suppression of characteristic variations and obtaining high yield are also important technical issues. These CMOS devices are fabricated by so-called “top-down” process (see (a) CMOS in Figure 1). Next, some devices fabricated by so-called “bottom-up process” such as self-assembly technology will emerge. CNT FETs10 and silicon nanowire FETs11 are included (see (b) bottom-up FET in Figure 1). In the author’s opinion, these devices are “CMOS-based”, because if these devices are realized, the circuit scheme that will be utilized may be that of conventional CMOS. These devices, that may be smaller than the lithography limit, will extend the life of the CMOS platform technology. A small step between (a) and (b) in Figure 1 shows a technological paradigm shift in the fabrication process from top-down fabrication to bottom-up fabrication. These two types of nanodevices, (a) CMOS and (b) bottom-up FET, are classified into the “CMOS Extension” category.

100 INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS

2.1.2. Beyond CMOS In time, new devices that are not CMOS-based, such as a resonant tunnel device (RTD) and a SET, will appear. They utilize “charges” as the state variables, but the circuit scheme and device operation principles are not CMOS ((c) charge-based devices in Figure 1). After these devices, even newer devices that utilize the state variables other than charges will emerge, such as the spin transistor12 ((d) non-charge devices in Figure 1). These two types, (c) and (d), are classified into “Beyond CMOS”. There is a huge technological gap between CMOS Extension and Beyond CMOS. There is also a huge gap between (c) charge-based devices and (d) non-charge devices. 2.1.3. New functions added to CMOS There is one more category in nanodevices. This is “New Functions added to CMOS”, where non-CMOS devices, such as MEMS, sensors, and bio devices, are integrated into a CMOS chip and new functionalities that cannot be attained by CMOS is added to the CMOS technology. The technology is mainly CMOS-based, but the non-CMOS technologies are merged into CMOS. This combination has huge potential to enhance the overall performance of CMOS-based systems, and this kind of technological approach is very different from the “Beyond CMOS” approach. 2.2. POSITION OF SET

A SET is a charge-based device, but is not CMOS-based. Therefore, a SET is classified in Beyond CMOS and also in (c) charge-based device, as shown in Figure 1. Many proposals of single-electron circuits, which are exclusively composed of SETs, have been made so far13. However, as pointed out in the previous subsection, there is a large technological gap between CMOS Extension and Beyond CMOS, and the single-electron circuits will not be realized in the near future as long as a SET is utilized as a beyond-CMOS device. To make the SET a more practical device, we should take the “New Functions Added to CMOS” approach. A SET has very unique I-V characteristics that are not achieved in conventional CMOS. When SETs are integrated in a CMOS chip, new functionality can be added to the CMOS technology. An example of the “New Functions Added to CMOS” approach of a SET is described in Section 5.

INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS 101

3. Structure and fabrication of silicon SETs 3.1. OPERATION PRINCIPLE OF SET

Figure 2 shows schematics of a SET. The structure of a SET is very similar to that of a FET. A SET has source, drain, and gate electrodes. The only difference between a SET and a FET is the existence of a quantum dot between source and drain in a SET as shown in Figure 2(a). The quantum dot is connected to source and drain via tunnel barriers. The potential of the dot is controlled by the gate voltage. Electrons flow from source to drain via a quantum dot, by tunneling. The equivalent circuit of a SET is shown in Figure 2(b). When one electron is injected from the source to the dot, the potential of the dot is raised by the electron charge. When the potential increase of the dot is larger than the thermal energy, the second electron cannot tunnel to the dot because of the potential barrier and the current does not flow. This is the Coulomb blockade. When the dot potential is raised by the gate, the second electron can tunnel to the dot and the current flows, but when the potential is raised by the gate further, then the third electron is forbidden to tunnel and the current stops again. Consequently, the current oscillates periodically as a function of the gate voltage as shown in Figure 2(c). This is referred to as the Coulomb blockade oscillations. The potential increase of the dot by one electron is called the charging energy and is given by e2/Ctotal, where e is the electron charge and Ctotal is the total capacitance of the dot. In order for the Coulomb blockade to appear at room temperature, the charging energy should be larger than the Gate Cg

Source

e

Drain

Cd

Cs

Cs Dot Cd

Id

Cg

Vg

(a)

Dot = /

Csub Vds

Vsub Vg (c)

(b)

Figure 2. (a) A schematic of the structure of a SET. (b) An equivalent circuit of a SET. (c) A schematic of I-V characteristics of a SET.

102 INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS

thermal energy at room temperature (26 meV). A simple calculation shows that the dot size should be smaller than roughly 10 nm to observe the Coulomb blockade oscillations at room temperature. Note that the Coulomb blockade is a classical phenomenon. When the dot size is very small and the quantum effect appears, the characteristics of the Coulomb blockade oscillations will be changed. 3.2. FABRICATION OF THE SILICON SET

Figure 3(a) shows a schematic structure of SETs we have fabricated.14 The transistors are fabricated on a silicon-on-insulator (SOI) substrate and are in the form of a point-contact MOSFET15, where a part of the channel is extremely narrow. The silicon quantum dot is self-formed in the very narrow channel, and therefore, the transistor acts as a SET16. Some of the single-electron transistors are in the form of an ultra-narrow wire MOSFET, as shown in Fig. 1(b), where multiple quantum dots are formed in the channel. The most small quantum dot dominates the electrical characteristics and most of the transistors operate as SETs.17 Moreover, some of the transistors are p-type MOSFETs, and therefore, these transistors act as single-hole transistors (SHT). The point-contact silicon channel and extremely narrow silicon nanowire channels were fabricated by electron-beam (EB) lithography and reactive ion etching on SOI substrates. The silicon channels were further narrowed by SC1 (NH4OH/H2O2/H2O2) wet etching. Thin thermal oxide was grown and chemical vapor deposition (CVD) oxide was deposited for the gate oxide. The total gate oxide thickness is approximately 20 nm. The rest of the fabriccation process was completed by single-layer polycrystalline-silicon gate electrode deposition, gate etching, BF2+ ion implantation into the gate and source/drain regions, dopant activation annealing, passivation oxide deposition, and the formation of contact holes and an Al electrode.

Figure 3. Structures of silicon SETs. (a) A SET in the form of a point contact MOSFET. (b) A SET in the form of ultra-narrow wire MOSFETs.

INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS 103

4. Room temperature operation of SETs/SHTs 4.1. EVOLUTION OF COULOMB BLOCKADE OSCILLATIONS

Figure 4 shows the current-gate voltage characteristics of a SET15 at a very early stage of the SET research in our group (in 1997). The Coulomb blockade oscillations are clearly observed at low temperatures below 77 K. When the temperature increases, the oscillations become broad and finally the oscillations are almost smeared out at room temperature. The values of capacitances in Figure 2(b) can be derived from the contour plot of the current as functions of drain voltage and gate voltage (not shown). Dot diameter and charging energy are estimated using these values to be approximately 6 nm and 90 meV, respectively. It is found that the dot size of 6 nm is not small enough to observe the large Coulomb blockade oscillations at room temperature. The size of the quantum dot should be further reduced by the improvement of the fabrication technology. The oscillations in Figure 4 are not periodic. According to the classical Coulomb blockade theory, periodic oscillations are expected. It has been found that the aperiodic oscillations are due to the dot size being too small, where the quantum level spacing in the dot is comparable to the charging 2.0 Dot size = 6 nm Ec = 90 meV

300 K

Id (nA)

1.5

240 K 1.0

160 K Vds = 1.0 mV Vsub = 0 V

0.5

77 K 21 K 15 K

0 0

1

2

3

4 5 Vg (V)

6

7

8

Figure 4. Measured current-gate voltage characteristics of a SET fabricated in 1997. The clear Coulomb blockade oscillations at low temperatures are almost smeared out at room temperature.

104 INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS

Id [pA]

150

100

150K 240K 300K

50

PVCR ~ 2 Ec ~ 250 meV Dot size ~ 4 nm

0

1

2

3

4

5

V [V] g

Figure 5. Measured current-gate voltage characteristics of a SET fabricated in 2000. The clear Coulomb blockade oscillations are observed at room temperatures. The PVCR at room temperature is 2.

energy.15 This fact indicates that a quantum dot in a SET that shows large Coulomb blockade oscillations at room temperature also shows the quantum effects. The examples of the quantum effects will be described later. Figure 5 shows the current-gate voltage characteristics of a SET18 fabricated in 2000. Larger oscillations are clearly observed at room temperature. The ideality of the oscillations is generally characterized by the peak-to-valley current ratio (PVCR). The PVCR of the oscillations in Figure 5 at room temperature is approximately 2, which is not enough for the practical applications. The estimate quantum dot diameter and the charging energy is 4 nm and 250 meV, respectively. The dot size of 4 nm is still too small to observe the large Coulomb blockade oscillations at room temperature. Great efforts have been made to further reduce the quantum dot size. One technique to make the dot size small is the removal of the buried oxide (BOX) layer of the SOI substrate just under the silicon nanowire channel by HF before SC1 etching.19 As a result, the wet etching of the nanowire channel by SC1 proceeds from both the top and the bottom, and the channel thickness and width are effectively reduced. Moreover, we fabricated SHTs,

INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS 105

instead of SETs, because we found that larger oscillations can be obtained in a hole system than in an electron system.20 Figure 6 shows the current-gate voltage characteristics at room temperature of a SHT19 fabricated in 2003. PVCR reaches as high as 40. The estimated dot size is as small as 2 nm. From the smooth curve shape of the oscillations, it is estimated that the number of the dominant dots in the channel is unity. In the multiple-dot system in which the curve has some shoulders or multiple peaks, we observed a PVCR of 1280.21 4.2. MECHANISM OF DOT FORMATION

In our SETs and SHT, the quantum dots are self-formed in the ultra-narrow channel. It is considered that the silicon narrow channel is not separated but the silicon channel is continuous. Figure 7 shows a schematic of the band structure of the ultra-narrow channel.20 The two tunnel barriers may be formed by expansion of the band gap due to the quantum confinement effect, and the quantum dot may be formed by the band gap shrinkage due to the compressive strain during thermal oxidation.22 The local channel width fluctuations may also be responsible for the dot formation.16,20 The exact origin of the dot formation mechanisms is not clear at present.

Drain Voltage : -1 mV PVCR ~ 40 Dot size ~ 2nm

10-10 10-11

0.3 0.2

10-12 0.1

10-13 10-14

|Drain Current (nA)|

10-9

0.4 | Drain Current (nA) |

| Drain Current (A) |

10-8

0 0

-1

-2 -3 -4 -5 Gate Voltage (V)

-6

Figure 6. Measured current-gate voltage characteristics of a SHT fabricated in 2003 at room temperature. The PVCR is 40. Note that left vertical axis is in the logarithmic scale and the right vertical axis is in the linear scale. The two curves are identical data.

106 INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS

Tunneling barriers

Bottom of econduction band

Top of valence band

Dot

h+

Tunneling barriers Figure 7. A schematic of the band structure of a quantum dot in the narrow channel. The band gap expands by the quantum confinement and the gap shrinks due to the compressive strain by the thermal oxidation.

4.3. LARGEST COULOMB BLOCKADE OSCILLATIONS AND NDC

Figure 8 shows the current-gate voltage characteristics at room temperature of a SHT23 fabricated in 2005. The PVCR of the Coulomb blockade oscillations is as high as 395. Since the dot is extremely small, the quantum level spacing in the dot is not negligible and some quantum effects appear even at room temperature, as mentioned above. One of the examples is the negative differential conductance (NDC). Figure 9 shows the current-drain voltage characteristics of the SHT.23 Note that the horizontal axis is not the gate voltage but the drain voltage. When the drain voltage increases at the gate voltage of -0.4V, the current increases but starts to decrease soon. This decrease in the current is NDC. The observed NDC is attributable to resonant tunneling through one quantum level in the extremely small quantum dot.19 The PVCR of NDC is as large as 106 at room temperature. It is clearly shown in Figure 9 that the amplitude of NDC is controlled by the gate voltage. More recently, we have intensively investigated the charge polarity dependence and nanowire direction dependence of the Coulomb blockade oscillations and NDC.24 It has been found that the [100]-directed SHT is the best to obtain a large PVCR. Actually, the fabricated SHT in the [100] direction shows PVCR of 480 in the Coulomb blockade oscillations and

INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS 107

PVCR of 300 in NDC,24 both of which are the highest ever reported at room temperature.

20

PVCR 395 -11

10

| IDS | (A)

| IDS | (pA)

15

Room Temp. VDS = -1mV

-12

10

10

5

10

-13

0 0.0

-14

-0.4

10 -1.2

-0.8

VGS (V)

Figure 8. Measured current-gate voltage characteristics of a SHT fabricated in 2005 at room temperature. The PVCR is 395.

VGS

Room Temp.

IDS (nA)

1.5 PVCR = 106

-0.2 V -0.4 V -0.6 V -0.8 V

1.0 0.5 0.0 0.0

0.2

0.4

0.6

VDS (V) Figure 9. Measured current-drain voltage characteristics of the SHT. The PVCR of NDC is 106.

108 INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS

5. Integration and circuit application of SETs 5.1. DIGITAL CIRCUIT APPLICATION

Great efforts have also been made to integrate room-temperature operating SETs and SHTs. A directional current switch has been formed by two integrated SHTs that show the Coulomb blockade oscillations at room temperature21 (not shown). This was the first integration of the roomtemperature operating SETs/SHTs, and the operation of directional current switch has been successfully demonstrated. Although some digital applications of SETs/SHTs have also been successfully demonstrated at room temperature14, it is known that digital circuits that are composed of SETs/SHTs have problems such as small gain, small drive current, and high bit error rates. Although the problem of the small gain has been partly solved recently25, the highest gain of a SET/SHT obtained at room temperature is 5.2,23 which is too small for practical digital applications. 5.2. ANALOG CIRCUIT APPLICATION

One of the best applications of SETs/SHTs is an analog circuit application. An example is the analog pattern matching application. The bell-shaped current-gate voltage characteristics can be utilized for analog pattern matching circuits.26 The Coulomb blockade oscillations have certainly the bell-shaped current-gate voltage characteristics, so we have applied them to the analog pattern matching.27 Figure 10 shows the operation principle of analog pattern matching.27 A device that exhibits the bell-shaped current-gate voltage characteristics is utilized. The gate voltage of the oscillation peak, a1 corresponds to a stored datum and is changed by programming. When input voltage, x1 is provided to the gate, input x1 and stored a1 are compared. When x1 and a1 are close, the output current is high because of the bell-shaped characteristics. On the other hand, if x1 and a1 are far away, the output current is very small. Therefore, the output current shows the similarity between input x1 and stored a1. SHTs are utilized as devices that have the bell-shaped current-gate voltage characteristics. Moreover, each SHT has silicon nanocrystals embedded in the gate oxide. When the pulse voltage is applied to the gate, charges are injected to the nanocrystals and the device acts as a non-volatile memory.28 Therefore, the peak position of the Coulomb blockade oscillations can be controlled by programming,28 and stored datum a1 can be easily changed.

INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS 109

Active range 0% 100%

Id

Data are stored by the peak shift

Vg

a1 x1

Figure 10. A schematic to show the principle of analog pattern matching. The output current represents the similarity between stored data a1 and the input x1.

Three SHTs that operate at room temperature are successfully integrated,27 as shown in Figure 11. The three SHTs correspond to three elements of a vector. For simplicity, the three elements are fitted to the three basic elements of colors (RGB) in this example, and color “orange” is stored by programming. The characteristics in Figure 11 are the curves after the programming. Then, various other colors are input. The results are shown in Figure 12. The largest output current is clearly obtained when the input is “orange”, indicating that “orange” is successfully read out.27 -20 0 % Active 100 % Range

Drain Current (pA)

Room Temp.

-15

Drain Voltage : -1 mV

-0.4V -0.6V -0.8V

B-SHT

-10

G-SHT R-SHT with a series MOS

-5

0 0.5

0

-0.5

-1

-1.5

Gate Voltage (V) Figure 11. Measured current-gate voltage characteristics of three integated SHTs operating at room temperature.

110 INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS

Figure 12. Measured output current at room temperature. The output is the sum of drain current in three SHTs. When the input is orange, the highest output current is obtained.

In this application, the matching is performed by the SHTs and other calculations are done by conventional CMOS circuits. Therefore, this new circuit scheme that utilizes SETs/SHTs and adds new function to CMOS is the “New Functions Added to CMOS” approach in Figure 1. Please note that the output of this analog pattern matching circuit is not deterministic.26 The output current represents the “similarity” between the stored data and the input data. Therefore, some errors are allowed in the circuits. The SETs/SHTs are suitable for this kind of applications. 6. Conclusion Recent developments of room temperature operating silicon SETs and SHTs are reviewed. The PVCR of the Coulomb blockade oscillations is as high as 480 and the PVCR of NDC is as high as 300 at room temperature. It is shown that “New Functions Added to CMOS” approach is very effective, and the analog pattern matching application is successfully demonstrated using integrated SHTs. SETs/SHTs are promising devices for future VLSI and add new functions to conventional CMOS circuit systems.

INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS 111 ACKNOWLEDGMENTS

The author would like to thank Prof. H. Ishikuro, Dr. M. Saitoh, Mr. K. Miyaji, and Mr. M. Kobayashi for performing experiments. This work was partly supported by Grant-in-Aid for COE (Center of Excellence) Research, the IT program, and Special Coordination Funds for Promoting Science and Technology from the Ministry of Education, Culture, Sports, Science and Technology, Japan.

References 1. 2. 3.

4.

5.

6.

7.

8.

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SiGe NANODOTS IN ELECTRO-OPTICAL SOI DEVICES A.V. DVURECHENSKII*, A.I. YAKIMOV, N.P. STEPINA, V.V. KIRIENKO, P.L. NOVIKOV Institute of Semiconductor Physics, Siberian Branch of Russian Academy of Science, Novosibirsk ∗ Anatoly V. Dvurechenskii. Institute of Semiconductor Physics, Siberian Branch of Russian Academy of Science, Lavrentiev Prospect13, 630090 Novosibirsk, Russia.

Abstract. The electronic and optical phenomena, as well as possible device-oriented application in Ge/Si and Ge/SiO2 nanodots that have been synthesized by molecular-beam growth are the scope of this article. We focus on the fundamental aspects and device applications of the small size dots whose electronic states resemble those of an atom even at room temperature.

Keywords: quantum dots, germanium, silicon, field effect transistor, infrared photo detector, memory device.

1. Introduction A new branch of semiconductor physics that studies the behavior of electrons confined in precisely tailored potential emerged during the last 20 years. This field has developed from the progress in technology that now allows for the routine fabrication of nanometer-scale solid state structures that contain small numbers of conduction electrons (<100) in geometries of size comparable to their de Broglie wavelength. Usually they are called “quantum dots” (QDs), referring to their quantum confinement properties in all three spatial dimensions1. This three-dimensional confinement leads to the formation of a discrete carrier energy spectrum, resembling that of an atom. Alongside this purely quantum effect, an important element of artificial atom filling is Coulomb blockade. An extra electron can only be added to the dot if enough energy is provided to overcome the Coulomb repulsive force between the electrons. Studying the QD systems shows in striking ways, the interplay of the discreteness of charge carried by a single electron and the quantum effects2,3.

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2. Quantum dot field-effect transistor In a single quantum dot weakly coupled by tunneling barriers to two contacs, the interplay of single-electron charging effects and resonant tunneling through quantized states leads to conductance oscillations as the electrochemical potential of the dot is tuned. This phenomenon underlies working of nano-scale single-electron transistors. The behavior of double dot systems is found to be mainly affected by electrostatic coupling between the two dots inside the artificial molecule. The next step is to engineer large arrays of QDs in close proximity, allowing Coulomb interaction and tunneling between them. The behavior of a multi-dot structure is more complicated for several reasons: (i) the QDs are inevitably not sufficiently identical in size, causing smearing of their atomic-like properties; (ii) in contrast to a single dot, the interaction of the dots in an ensemble can be significant; (iii) transport through the system may be dominated by thermally assisted hopping between the dots rather than by resonant tunneling between source and drain electrodes. Little work has been done on the Ge/Si quantum-dot field-effect transistors (QDFETs), which use the quantum transport through discrete energy states in zero-dimensional systems4. To date, most work in the field of QDFETs has concentrated on InAs/GaAs SAQDs and on Si-based quantum dots defined by very sophisticated patterning techniques, such as electron-beam lithography in combination with anisotropic etching and selective oxidation or by tunable gates3. The most promising approach to reveal the phenomena of charge transport through the array of QDs based on a few key technological processes. First, the drain current leakage should be reduced by using the isolated Si layer thickness in a silicon-on-insulator (SOI) structure. Second, the average QDs size should be in the nanoscale range to provide stronger carrier confinement in the dots and a larger energy level separation, resulting in a clearer resolution of the current peaks at high temperatures. In order to raise the operation temperature of QDFETs up to 300 K, the size of QDs has to be smaller than 10 nm. This requirement considerably restricts the possibility of using the lithographic processes for fabrication of ultrasmall QDs. Third, inhomogeneous broadening due to dot size variations and long-range random Coulomb potentials may be reduced by decreasing the dimensions of the QDFET and by using a gate recess configuration. A Si layer of 47 nm thick in an SOI structure has been used in experiments. The Ge self-assembled dots were grown with density 4 × 1011 cm-2 and subsequently capped by a Si layer. The average in-plane diameter and height of the Ge dots are 10 and 1 nm, respectively. To supply holes

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onto the dots, a boron delta-doping (6 × 1012 cm-2) Si layer was grown above the Ge layer (Fig. 1). The channel was patterned by photolithography to form a Si island of 4-µm length and 1-µm width, etched down to the underlying SiO2. Source and drain electrodes were made using Al evaporation and annealing at 450oC in N2 atmosphere. A silicon dioxide layer of 60 nm thicknesses was deposited by plasma-enhanced chemicalvapor deposition as the gate insulator and finally, Al gate of 4 µm width and 1 µm length was formed. The amount of gate oxide charge, estimated from the admittance measurements, was about 3×1010 cm-2. Figure 1 shows an atomic force microscopy picture of the transistor. Several samples with channel widths W, ranging from 1 to 2 um were fabricated. The sidewall depletion width is determined to be 0.9 um from measurements of drain current versus W at zero gate voltage. Assuming a uniform density of 4000 dots per um2 these different gate areas of the samples contain numbers of active dots from 400 to 4000. The hole concentration in the boron δ-doping Si layer is sufficient to fill, after spatial transfer, all hole bound states in the Ge islands and to populate two-dimensional states in the Ge wetting layer. As a result, the channel conductance at zero gate voltage is found to show non-activated behavior and depend only slightly on temperature. The drain current (Id) as a function of the gate voltage (Vg) was measured at different temperatures with the drain voltage fixed at 5 mV.

Figure 1. Atomic force microscopy image and schematic cross section of the transistor channel. The source, drain, and the gate are labeled by S, D, and G, respectively.

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Figure 2 shows the typical Id-Vg characteristics of the 1 um gate QD transistor. When a positive bias is applied to the gate the channel is depleted and current flow between the source and drain contacts is suppressed. Above the threshold voltage Vth ≈ 4 V the deep hole states in the dots come into resonance with the Fermi energy and the current starts to oscillate as shown in Fig. 3.

Figure 2. Gate voltage dependence of drain current at various temperatures.

Figure 3. Top of the valence band of the transistor for positive gate bias. The SOI substrate is not shown. The holes reside in the Ge dots. When the Fermi level is aligned with the quantum levels in the Ge dots at a certain gate voltage, holes will flow through that quantum level in the plane of Ge SAQDs.

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At room temperature, a current bump is clearly observable around 6 V. As the temperature decreases, four well-pronounced equidistant peaks with a gate voltage separation ∆Vg ≈ 1.1 V appear after onset of the conductance. The number and relative position of the peaks are well reproducible for different cold cycles and in different samples of similar sizes. Four equidistant current peaks is suggested to be due to tunneling through fourfold-degenerate excited state in the Ge QDs. One may estimate the position of two additional peaks corresponding to transport through the twofold-degenerate hole ground state. Due to confinement and the Coulomb effect, the energy difference between loading the second hole into the ground state and the first hole into the excited state of the used Ge SAQDs is approximately 200 meV. The filling of the ground state is expected to be at Vg ≈16 V, but, in this region, large leakage current through the gate insulator prevents measurements of Id–Vg characteristics. For larger sizes of QDs the ground states were observed5. The charging energy (Ec) of the dots can be determined by using the expression, Ec =ηe∆Vg, where the gate modulation coefficient η relates the gate voltage to the hole energy inside the dots. This coefficient can be calculated from the temperature dependence of the full-width at half maximum (FWHM) of the current peaks, which, for a single dot showing Coulomb blockade oscillations, should be broadened with T as 3.5 kBT /(ηe)6. On the basis of this estimation the charging energy is 43±3 meV. Figure 4 shows the temperature dependence of the current maxima. A clear thermally enhanced transport through the dots with the activation energy Ea =21 ± 3 meV is evident. Possible mechanisms of charge transport may be 1) thermal activation of holes from the dots over the barriers or 2) hole tunneling between neighboring dots7. In the latter case, the activation energy is typical of that for disorder energy in the system, which comes from dispersion of the dot sizes and potential fluctuations caused by random distribution of the charged dots and interface states. Because the experimental value Ea is the same for all peaks, that is, it does not depend on the effective barrier height, the conduction mechanism is attributed to the nearest-neighbour hopping of holes between the dots. When the gate voltage is scanned, the Fermi level moves across the zero-dimensional density of states. The maximum current occurs when the given hole level in the dots is half-filled because this maximizes the product of possible initial and final states for a tunneling process and avoids increasing the energy of the system due to appearance of extra charge in a final dot.

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Figure 4. Temperature dependence of the current maxima at different gate voltages. Inset: Temperature dependence of the average FWHM of four current maxima with a linear .t to the data. To obtain the FWHM of each peak, the observed current oscillations were decomposed into four Gaussians.

The disorder energy, Ed, in the ensemble of dots can be found from the residual full width at half maximum (FWHM) of current peaks. The value of Ed was found to be 19±3 meV, which is consistent with the experimental value of activation energy observed. 3. Quantum dot infrared photodetectors The potential advantages of quantum dot infrared photodetectors (QDIPs) for near infrared operation as compared with two-dimensional systems are (i) increased sensitivity to normally incident radiation as a result of breaking of the polarization selection rules, so eliminating the need for reflectors, gratings or optocouplers, (ii) the expected large photoelectric gain associated with a reduced capture probability of photo excited carriers due to suppression of electron-phonon scattering, (iii) small thermal generation rate, resulting from the zero-dimensional character of the electronic spectrum, that renders a much improved signal-to-noise ratio, (iv) possibility for narrow-band detection due to the discreteness of the density of states. Furthermore, since the spatial extent of the electron or carrier wavefunction in QDs is in the order of their size (about 10 nm) or more, the

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dipole matrix element for the inter-subband transitions can be large, which is not the case for natural deep impurities in semiconductors. To provide a high performance of QDIPs, the photosensitive region of detectors should consist of a dense array of QDs. In this way more advantageous and hence more relevant for application in QDIPs, are selfassembled Ge/Si QDs, in which the surface density of the dots as high as 1011-1012 cm-2 can be achieved by choosing appropriate growth conditions. The concept of QDIP using intersubband transitions was proposed and analyzed theoretically8-11. Figure 5 shows a Ge/Si QDIP with vertical photocurrent, consisting of a p+–p–n+ silicon structure with a planar array of Ge quantum dots embedded in the undoped or lightly doped (with boron) p-Si region. The structures p+–p–n+ and n+–p–n+ were used for mid-and near-infrared12-18. The integration of Si/Ge heterostructures on a Si chip and their compatibility with Si based electronic circuitry presents a high potential for designing low-cost optoelectronic modules, operating at the 1.3 µm and 1.55 µm telecommunication wavelength (bound-to-continuum interband transition from Ge to Si). A fundamental feature of staggered QDs Ge/Si is the spatial separation of electrons and holes resulting in formation of spatially indirect excitons. An example of a near infrared Ge/Si p–i–n photodetector operating at the 1.3 µm and 1.55 µm telecommunication wavelengths is shown in Fig. 6. To increase the interaction length between the light and the QDs layers and to provide the intra-chip interconnections, a vertical stacking of 36 layers of coherent Ge nano-islands was inserted into a waveguide obtained with an SOI structure. The sample was processed into ridge waveguide. Devices

Ge dots

300 nm n+Si 100 nm Si 20 nm Si 100 nm Si

SiO2

SiO2

Al

} x36

500 nm p + Si Silicon-on-Insulator Figure 5. Schematic of the Ge/Si photodetector structure.

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with lengths going from L = 0.1 to 5 mm were fabricated18. The roomtemperature quantum efficiency of a 4 mm device versus reverse bias Ub is shown in Figure 7. The light is coupled through the edge of the detector. The maximum external quantum efficiency achieved is 16% for λ=1.55 µm and 21% for λ=1.3 µm at L>3 mm and Ub >3 V. p+ Si bottom contact

Sio2

Al contacts n+Si top contact Ge dots Si

Figure 6. Schematic layout of waveguide near-infrared photodetector on a silicon-oninsulator substrate.

Figure 7. Quantum efficiency of a 4 mm waveguide photodetector as a function of reverse bias.

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To the best of our knowledge, the first observation of mid-infrared photoconductivity in Ge QDs has been reported in 199915. The QDIP under investigation was a p+–p–n+ silicon diode embedded with a single layer of pyramidal Ge SAQDs. The average size of the dot base length is 15 nm, the height is 1.5 nm. As the heterostructure was growth at low temperature (Ge layer was grown at 300 C and covered with Si at 500 C), the segregation and inter-diffusion effects are negligible and the Ge islands contain no silicon atoms. The large areal density of Ge QDs (3×1011 cm-3) was responsible for the high absorption coefficient. 4. Ge nanodots on SiO2 for non-volatile memory devices A nanocrystal in a dielectric matrix has attracted much attention as a promising candidate for a charging node in a single-electron memory device (SEMD). An advantage of the nano-floating gate memory over the continuous floating gate is its improved endurance due to the prevention of lateral charge movement. Faster writing/erasing time, lower operating voltage and longer retention time have been demonstrated in a memory device based on Si islands embedded in SiO219. Recently it was shown that a Ge-based SEMD has superior properties over Si-based SEMD in terms of the writing /erasing time and the operating voltage. Since then, different methods were used for fabrication of Ge nanodots in a dielectric matrix, such as ion beam synthesis20, oxidation and reduction of Ge/Si islands21, rapid thermal annealing of co-sputtered22 and chemical-vapor-deposition layers, and pulsed-laser deposition23. However practically all of these techniques create the random distribution of nanodots inside the dielectric, that yields the ensemble-averaged information only. To suppress the tunneling distance fluctuation and allow carrying out the detail analysis of tunneling-out mechanism it is necessary to form in-plane distribution of nanodots. Moreover, when used nanodots for charge storage devices, the general requirements that can be placed upon the control are the size of nanodots, theirs density and homogeneity in growth plane, that is the problem for most of above-mentioned growth methods. In other work24 pulsed low-energy (100-200 eV) ion-beam-induced nucleation was found to stimulate Ge nanocrystal formation on relatively thick films of SiO2 (about 100 nm) prepared by thermal oxidation of Si. It was shown that the ion-beam action causes an increase in nanocrystal density and size homogeneity. The idea of using the ion-beam action is that each ion impact into the SiO2 surface (a) produces a vacancy depression with surface steps being nucleation sites for nanocrystal growth; (b) generates adatoms assisting in nuclei growth; c) stimulates surface adatom diffusion. Ion energy should be low enough to avoid introduction of defects

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into the SiO2 film, but high enough in comparison to the thermal energy of deposited atoms. The regime of pulsed ion-beam irradiation allows synchronous nucleation of new phases, favorable for highly homogeneous nanocrystal size distributions. The pulsed low-energy (200 eV) ion-beam-induced nucleation during Ge deposition on SiO2 was used to study the formation of Ge nanocrystals arrays on thin films of dielectric which are usually tunnel layers in memory devices. A 4.5 nm thick SiO2 film tunnel insulator was grown by thermal oxidation on (111) p-type silicon substrates at 850o C. After dioxide formation, the wafers were washed, dried and inserted into the ultrahighvacuum (UHV) chamber. About a 1 nm-thick SiO2 layer was removed from the top surface in-situ using a Si flux at 820o C, before Ge deposition. Molecular beam deposition (MBD) of Ge was carried out in an UHV chamber of a molecular beam epitaxy set-up equipped with a boron nitride crucible effusion cell. The system of ionization and acceleration of Ge+ ions provided a degree of ionization of the Ge molecular beam from 0.1% to 0.5%. A pulse accelerating voltage supply unit generated ion-current pulses with duration of 0.5-1 s and ion energy of 200 eV. The angle of incidence of the molecular and ion beams on the substrate was 54o out of the surface normal. The analytical assembly of the chamber included a reflection high energy (20 keV) electron diffraction (RHEED) unit. The substrate temperature of Ge deposition was varied from 250 to 400o C. In all experiments, the nominal Ge layer thickness was targetted as 20 monolayers (ML). The rate of Ge deposition was varied between 0.08 - 0.19 ML/s. Two different regimes of ion stimulation were studied. In the first case (regime 1) three ML of Ge were deposited without ion-beam action. Pulsed ionbeam actions were applied in series at the effective Ge layer thickness of 3 ML, 4 ML and 5 ML. In the second case, ion implantation was commenced simultaneously with Ge deposition in series, at the effective thickness of 1ML, 2 ML and 3ML (regime 2). Ge nanocrystal density and size distribution were studied with high resolution electron microscopy (HREM), both plan-view and cross-sectional geometries. To prevent Ge oxidation, some samples were capped by a thin Si layer (~5 nm) in the same UHV chamber. The chemical composition of the uncapped samples and tunnel insulator thickness variation were studied with the Electron Spectroscopy for Chemical Analysis (ESCA) technique by transferring samples via ambient atmosphere to the ESCA spectrometer. An Al source with K line 1486.6 eV was used for exciting X-ray photoelectron spectra with an energy resolution of 0.7 eV and probing depth from 1 to 4 nm, independent of photoelectron energy.

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Figure 8. The HREM image (plane view) of Ge nanocrystals on SiO2.

Figure 9. Cross-section HREM image of Ge nanocrystals on SiO2.

To determine the influence of the ion beam on the thickness of the tunneling insulator during Ge deposition, the intensity of the Si 2p line was analyzed. The thickness of the tunneling insulator was evaluated from the intensity ratio of the oxide component Si 2p (103.0 eV) to substrate component Si 2p (98.7 eV). A significant decrease of tunneling insulator thickness (from 4.2 to 2.4 nm) was observed, when ions irradiate an uncapped SiO2 surface (regime 2). When ion action takes place on the surface capped by Ge (the regime 1) the tunneling insulator thickness was unaffected. In both cases there are no any changes in stoichiometry of SiO2 layers. As a measure of the germanium content, the line intensity of Ge 2p x-ray photoelectron yielded the probing depth; about 0.89 nm in our

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experiment. This reflects the inelastic mean free path of photoelectrons. The Ge 2p states are clearly resolved with a spin-orbit splitting of 31.1 eV. Both Ge 2p1/2 and Ge 2p3/2 lines show pronounced superposition of two components with an energy shift of 2.3 eV. These two components have peak positions of binding energies at 1217.7 eV and at 1220.0 eV and are related to the germanium in pure and partially oxidized states, correspondingly. The origin of the GeOx fraction relates to the unintentional oxidation during the transfer of samples to the ESCA spectrometer in the ambient atmosphere. The HREM image of Fig. 8 shows homogeneous Ge nanocrystals of 7 nm average size on the SiO2 surface. An additional cross-section study depicted in Fig. 9, shows the spherical shape of the Ge nanocrystals. The density of nanocrystals increases with top value up to 1012 cm-2 as the substrate temperature goes down (Fig. 10). Strong Ge desorption was observed during deposition as the substrate temperature was increased. The pulsed ion beam nucleation in regime 1 was found to gives rise to suppression of Ge desorption. This effect is clearly demonstrated with ESCA measurements of Ge peak intensity and HREM studies of nanocrystal size distribution, as seen in Fig. 11. At a substrate temperature of 300o C, the pulsed ion beam action in regime 1 results in an increase in the total amount of Ge deposited on SiO2 by a factor 1.7, as compared with conventional MBD. However, even in this case the effect of desorption still dominates. From 20 effective Ge MLs intended for deposition, just 2 MLs remain on the SiO2 surface.

Figure 10. Density of Ge nanocrystals on SiO2 versus the substrate temperature.

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Figure 11. Ge nanocrystal’s size distributions: 1 – Ge deposition with pulsed ion-beam action (regime 1); 2 – no ion-beam action during Ge deposition.

The growth procedure was optimized with respect to a uniform dot-size distribution around 6 nm and a dot density about 1012 cm-2. The main parameters determining these regimes are the deposition temperature and Ge flux. To clarify the mechanism of Ge nanocrystal formation and the role of ion irradiation, we have carried out Monte Carlo (MC) simulations of the reaction kinetics. The kinetics of nanocrystsl formation was calculated using the “lattice gas” model25, which includes Ge atoms deposition on SiO2 surface, their surface diffusion, desorption, precipitation, and ion-beam action. The sites occupied by Ge atoms and SiO2 were restricted to a facecentered cubic (FCC) lattice, which is well suited to describe precipitation in isotropic amorphous matrices such as SiO2. The lattice includes 128×128×32 sites with cylindrical boundary conditions in the lateral plane. The number and type of nearest neighbours to a Ge atom determine its interaction energy with other Ge atoms and the SiO2 matrix. The energy per one Ge-Ge bond in the FCC lattice was taken to beequal to 0.2 eV, which corresponds to an activation surface diffusion energy of 0.8 eV at a free Ge surface as obtained from molecular dynamics calculation26. For Ge in the SiO2 environment, the interaction energy per one neighbour site occupied by SiO2 was chosen to be as high as 0.076 eV, which provides the reproduction of the experimental dependence of residual surface compared to the amount of Ge deposited.

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The simulated nanocrystals were found to have isotropic shape. This result was not expected in advance, since the growth proceeds under nonequilibrium conditions. An irradiation effect was described by the concept of collisional mixing, that is, the displacement of atoms. In the simulation process each Ge atom has a probability P, to be displaced by a distance R, during one MC step. Ion-beam action results in the smaller nanocrystal size and the higher density due to precipitation and nucleation of new nanocrystals by atoms knocked out from initial ones to the SiO2 surface. 5. Conclusions We have shown that pulsed low-energy ion beam nucleation during Ge deposition on SiO2 films allows us to suppress Ge desorption, increase the density of Ge nanocrystals and decrease the average nanocrystal size and size dispersion. The pre-deposition of Ge before the pulsed ion beam action was found to allow excellent control of the thickness of the thin SiO2 film which forms the tunnel insulator in memory device. The C-V curves of the structures with control insulator over Ge nanocrystals show hysteresis with memory windows up to 7 V, indicating the charge storage effect in Ge nanocrystals. ACKNOWLEDGMENTS

This work was supported by the Russian Foundation for Basic Research (Grant No.06-02-08077).

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doped structures with embedded Ge quantum dots, Phys. Rev. B 59, 12598-12603 (1999). B. W. J. Beenakker, Theory of Coulomb blockade oscillations in the conductance of quantum dot, Phys. Rev. B 44, 1646 (1991). N. F. Mott and E. A. Davis, Electronic Processes in Non-Crystalline Materials, 2nd ed. (Clarendon Press, Oxford 1979). V. Ryzhii, The theory of quantum-dot infrared phototrasistor, Semicond. Sci. Technol. 11, 759-765 (1996). V. Ryzhii, V. Pipa, I. Khmyrova, V. Mitin, and M. Willander, Dark current in quantum dot inrared photodetectors, Jpn. J. Appl. Phys., 39, part 2, No 12B, L1283–L1285 (2000). V. Ryzhii, I. Khmyrova, V. Mitin, M. Stroscio, and M. Willander, On the detectivity of quantum-dot infrared photodetectors, Appl. Phys. Lett., 78(22), 3523-3525 (2001). R. A. Suris, Prospects for quantum dot structures applications in electronics and optoelectronics, in: Future Trends in Microelectronics, edited by S. Luryi, (Kluwer Academic Publishers, Netherlands 1996), pp. 197-208. D. Bougeard, K. Brunner, G. Abstreiter, Interaband photoresponse of SiGe quantum dot/quantum well multilayers, Physica E, 16, 609-613 (2003). P. Boucard, T. Brunhes, S. Sauvage, N. Yam, V. Le Thanh, D. Bouchier, N. Rappoport and E. Finkman, Midinfrared photoconductivity in Ge/Si self-assembled quantum dots, Phys. Stat. Sol. (b), 224(1), 233-236 (2001). P. Schittenhelm, C. Engel, F. Findeis, G. Abstreiter, A. A. Darhuber, G. Bauer, A. O. Kosogov, and P. Werner, Self-assembled Ge dots: Growth, characterization, ordering and application, J. Vac. Sci. Technol. B 16, 1575 (1998). A. I. Yakimov, A. V. Dvurechenskii, Yu. Yu. Proskuryakov, A. I. Nikiforov, O. P. Pchelyakov, S. A. Teys, A. K. Gutakovskii. Normal-incidence infrared photoconductivity in Si p-i-n diode with embedded Ge self-assembled quantum dots. Appl. Phys. Lett., 75(19), 1413-1415 (1999). A. I. Yakimov and A. V. Dvurechenskii, Germanium self-assembled quantum dots for mid-infrared photodetectors, International Journal of High Speed Electronics and Systems, 12(3), 873-889 (2003). A. I. Yakimov, A. V. Dvurechenskii, A. I. Nikiforov, S. V. Chaikovskii, and S. A. Tiis, Ge/Si photodiodes with embedded arrays of Ge quantum dots for the near infrared region, Semiconductors, 37(11), 1345-1349 (2003). A. I. Yakimov, A. V. Dvurechenskii, V. V. Kirienko, N. P. Stepina, A. I. Nikiforov, V. V. Ulyanov, S. V. Chaikovskii, V. A. Volodin, M. D. Efremov, M. S. Seksenbaev, T. S. Shamirzaev, K. S. Zhuravlev. Ge/Si waveguide photodiodes with built-in layers of Ge quantum dots for fiber-optic communication lines, Semiconductors, 38(10), 1225-1229 (2004). S. Tiwari, F. Rana, H. Hanati, A. Hartstein, E. F. Crabble and K. Chan, A silicon nanocrystals based memory, Appl. Phys. Lett., 68(8), 1377-1379 (1996). P. Normand, E. Kapetanakis, D. Tsoukalas, G. Kamoulakos, K. Beltsios, J. Van Den Berg, S. Zhang, Effect of annealing environment on the memory properties of thin oxides with embedded Si nanocrystals obtained by low-energy ion- beam synthesis, Mat. Sci. and Eng. C, 83(1), 168-170 (2003). T. Sass, V. Zela, A. Gustafsson, I. Pietzonka and W. Seifert, Oxidation and reduction behavior of Ge/Si islands, Appl. Phys. Lett. , 81(18), 3455-3457 (2002).

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22. W. K. Choi, W. K. Chim, C. L. Heng, L. W. Teo, Vincent Ho, V. Ng, D. A. Antoniadis and E. A. Fitzgerald, Antoniadis and E.A.Fitzgerald, Effect of structure ordering on charge carrier mobilities in green-emitting poly(phenylene vinylene)s, Appl. Phys. Lett., 81(11), 2014-2016 (2002). 23. X. B. Lu, P. F. Lee and J. Y. Dai, Synthesis and memory effect study of Ge nanocrystals embedded in LaAlO3 high-k dielectrics, Appl. Phys. Lett., 86, 203111203113 (2005). 24. A. V. Dvurechenskii, P. L. Novikov, Y. Khang, Zh. V. Smagina, V. A. Armbrister, V. G. Kesler, A. K. Gutakovskii. Dense arrays of Ge nanoclusters induced by low-energy ion-beam assisted deposition on SiO2 films, Proc. SPIE, 6260, 626006-626006A8 (2006). 25. P. Novikov, K.-H. Heinig, A. Larsen, A. Dvurechenskii, Simulation of ion-irradiation stimulated Ge nanocluster formation in gate oxides containing GeO2, Nucl. Instum. Methods in Physics Research B, 191, 462-467 (2002). 26. D. Srivastava and B. J. Garrison, Adsorption and diffusion dynamics of a Ge adatom on the Si{100}(2×1) surface, Phys. Rev. B, 46(3), 1472-1479 (1994).

NANOWIRE QUANTUM EFFECTS IN TRIGATE SOI MOSFETS JEAN-PIERRE COLINGE* Dept. of Electrical and Computer Engineering, Univ. of California, Davis, CA 95616, USA *

To whom the correspondence should be addressed.

Abstract. This paper describes low-dimensional nanowire quantum effects that occur in small trigate SOI MOSFETs. 2D numerical simulation is used to calculate the electron concentration profile as a function of gate voltage in devices with different cross sections. The smaller the section, the higher the threshold voltage. A dynamic increase of threshold voltage with electron concentration is observed. Inter-subband scattering causes oscillations of the transconductance when measured as a function of the gate voltage. These oscillations are visible at low temperature (< 30K) in samples with a 45 × 82nm cross section and at room temperature in devices with a 11nm × 48nm cross section.

Keywords: Silicon-on-Insulator, SOI MOSFET, multiple-gate MOSFET

1. Introduction The Multi-Gate SOI MOSFET (or MuGFET) structure is being considered as a replacement to the single-gate MOSFET as it prolongs the life of silicon CMOS beyond the limits of classical scaling. MuGFETs can be realized with gate length well below 10 nm without suffering from the short-channel effects that plague single-gate MOSFETs. The MuGFET category includes devices such as the FinFET, a two-gate device, the trigate FET, and the gate-all-around device. Due to the presence of several channels operating in parallel at the top and the sidewalls of the device, multi-gate SOI MOSFETs can have a current drive that is significantly larger than that of planar MOSFETs1,2,3,4. Empirically, and to a first-order approximation, it is found that, in order to avoid short-channel effects, the width and height of a trigate MOSFET must be smaller than the effective gate length1. As a result, the width and height of these devices are predicted to reach values smaller than 20 nm in the near future5,6. The influence of film thickness reduction on the threshold voltage of single and double-gate SOI MOSFETs has been reported in the literature. It is found that, due to 129 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 129-142. © 2007 Springer.

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quantum confinement of carriers in the thin silicon layer, the minimum energy for electrons in the conduction band increases when the thickness of the silicon film is reduced. As a result, the threshold voltage increases as the film thickness is reduced. This effect was first predicted by Y. Omura et al. in 1993, and has been simulated and observed experimentally by several groups since7,8,9. It is included in modern thin-film SOI and double-gate MOSFET simulators10,11. It is also predicted that when the silicon film is sufficiently thin and/or narrow, energy subbands form, and inter-subband scattering effects should affect carrier mobility. Such effects have been reported in double-gate devices where transconductance oscillations have been observed when the gate voltage is increased12,13. In this paper, we report several effects occurring in trigate SOI MOSFETs that can directly be attributed to the formation of energy subbands and to inter-subband scattering. Firstly, the formation of subbands and the increase of the minimum subband energy when the section of the device is decreased yields an increase of the threshold voltage. Furthermore, the minimum energy for the electrons in the conduction energy subbands increases with the electron concentration, which dynamically increases the threshold voltage as the inversion charge builds up14. This effect reduces the current drive of the device and is not predicted by classical simulators. Secondly, increasing the gate voltage increases the number of subbands that are populated with electrons. As a result, inter-subband scattering increases with gate voltage and drain current oscillations are observed as gate voltage is increased15,16. 2. Device fabrication The first set of devices has a final fin width, Wsi, and height, tsi, of 45 nm and 82 nm, respectively. The gate oxide thickness is 2 nm. A polysilicon layer was then deposited and doped n-type by phosphorus ion implantation to form the gate. Arsenic was implanted to form source and drain regions and titanium silicide was formed on source and drain regions to reduce parasitic resistance. Figure 1 shows a close up TEM cross-section of one fin from such a Trigate SOI MOSFET. A second set of devices has silicon fins with a width of 11nm. A 1.7-nm gate oxide was grown by wet oxidation. A 6 nm-thick TiSiN gate layer was then deposited by LPCVD on the gate oxide, and capped with a 100nm polysilicon layer. The work function of the TiSiN gate is 4.65eV, which makes it a “midgap” gate material. Gate electrodes were patterned using lithography and etched. A combination of dry and wet chemistry was used to etch the poly capping layer and metal gate. Significant over etch was used to ensure all poly and metal are clear in

QUANTUM EFFECTS IN TRIGATE SOI MOSFETS

131

Figure 1. TEM cross section of a device with a fin width and height of 45 nm and 82 nm (left) and a device with a fin width and height of 11 nm and 58 nm (right).

the undercut region under the fin. As a result the devices are more of the Pigate type than straight Trigate devices. Figure 1 shows a close up TEM cross-section of one fin from such a Trigate SOI MOSFET. The fin width, Wsi, is 11 nm and the fin height, tsi, is 58 nm. 3. Device modelling The devices were modeled using a self-consistent Poisson-Schrödinger 2D simulator implemented in Comsol MultiphysicsTM. The electron concentration is obtained by adding the electron concentrations of subbands with energies ranging from EC to EC+10kT. The electron concentration is thus given by:

n ( x, y ) = ∑ ⎡ Ψ ( x, y ) × Ψ * ( x, y ) × ∫ ⎢ EC j ⎣

EC +10 kT

ρ j ( E ) f FD ( E )dE ⎤ (cm-3) ⎥⎦

(1)

where ρj(E) is the density of states in the j-th subband and fFD(E) is the Fermi-Dirac distribution function. The density of states used in the simulations corresponds to that of a one-dimensional structure: 17

ρ j (E) =

1 πAsi

2m ds* =2

1 E − Ej

(cm-3 J-1)

(2)

132

QUANTUM EFFECTS IN TRIGATE SOI MOSFETS Gate electrode

A

B

Gate oxide

tsi

Silicon

y x

Wsi

Buried oxide

Back gate electrode

Figure 2. A: Cross section of the simulated device; B: Typical simulation mesh.

where Asi = Wsi×tsi is the cross-sectional area of the silicon fin. Figure 2 shows the schematic cross-section of the simulated device and a typical simulation mesh. Self-consistency of the calculation is obtained by using the following algorithm: The Poisson equation is first solved with n(x,y)=0 as the initial condition. The resulting potential distribution is fed into the Schrödinger equation to calculate the 2D wavefunctions and their energy levels. Using this information the electron concentration n(x,y) is calculated using Equation (1). The electron concentration is then introduced in the Poisson equation and a Newton-Raphson iteration process is used until convergence of the electron concentration is obtained. The criterion for convergence is a variation of electron concentration less than 0.1% between two iterations. The electron concentration profile for different values of the gate voltage (VG = 0, 0.7 and 1.5 V) is shown in Figures 3 and 4. The results are shown when using either a Poisson solver only (left columns) or a Poisson + Schrödinger solver (right columns). In Figure 3, the width and height of the silicon fin is 20 nm, while Wsi and tsi are equal to 5 nm in Figure 4. In the device with the larger cross section (Figure 3), the electron profiles obtained by the Poisson solver are very similar to those yielded by the Poisson + Schrödinger solver. This is because the section is too large for confinement effects to be of significant importance. It is worth noticing, however, that the electron concentration is lower in the Poisson + Schrödinger solutions than in the Poisson only simulations because of a bandgap widening effect predicted by the Poisson + Schrödinger simulations.

QUANTUM EFFECTS IN TRIGATE SOI MOSFETS Electron concentration (cm-3)

Poisson only

Electron concentration (cm-3)

A2

x1014 Electron concentration (cm-3)

Poisson only

x1013 Electron concentration (cm-3)

VG = 0.7V

B1

Poisson + Schrödinger VG = 0.7V

B2 20

x10

Electron concentration (cm-3)

Poisson only

x1019 Electron concentration (cm-3)

VG = 1.5V

C1

Poisson + Schrödinger VG = 0V

VG = 0V

A1

133

Poisson + Schrödinger VG = 1.5V

C2

Figure 3. Poisson only (A1, B1, C1) and Poisson + Schrödinger (A2, B2, C2) simulation of the electron concentration profile in a trigate device with Wsi=tsi= 20 nm, ΦMS=0V, VG2=0V, 17 -3 tox=2nm and Na=5x10 cm at T=300K. A1 and A2: VG= 0V; B1 and B2: VG= 0.7V; A1 and A2: VG= 1.5V.

In the device with the smaller cross section (Figure 4), the electron profiles obtained by the Poisson solver and the Poisson + Schrödinger solver are very different. In this case, the section of the device is small enough to show confinement effects. Once again, the electron concentration is lower in the Poisson + Schrödinger solutions than in the Poisson only simulations because of the widening of the bandgap predicted by the Poisson + Schrödinger simulations.

134

QUANTUM EFFECTS IN TRIGATE SOI MOSFETS Electron concentration (cm-3)

Poisson only

Electron concentration (cm-3)

VG = 0V

VG = 0V

A1

A2

x1013 Electron concentration (cm-3)

Poisson only

x1013 Electron concentration (cm-3)

VG = 0.7V

B1

Poisson + Schrödinger VG = 0.7V

B2 20

x10

Electron concentration (cm-3)

Poisson only

x1019 Electron concentration (cm-3)

VG = 1.5V

C1

Poisson + Schrödinger

Poisson + Schrödinger VG = 1.5V

C2

Figure 4. Poisson only (A1, B1, C1) and Poisson + Schrödinger (A2, B2, C2) simulation of the electron concentration profile in a trigate device with Wsi=tsi= 5 nm, ΦMS=0V, VG2=0V, 17 -3 tox=2nm, and Na=5x10 cm at T=300K. A1 and A2: VG= 0V; B1 and B2: VG= 0.7V; A1 and A2: VG= 1.5V.

Figure 5 shows the variation of the minimum energy in the first electron subband as a function of device dimensions and as a function of the average electron concentration. Clearly the energy of the lowest subband increases with the electron concentration, i.e., when the concentration of electrons increases the local electron charge increases and the repulsive forces between these electrons increases. More energy is thus required to further increase the electron concentration and, as a result, the energy of the subbands increases.

QUANTUM EFFECTS IN TRIGATE SOI MOSFETS

135

Energy above Ec (eV)

0.25

0.2

W = tsi = 2 nm 20 nm

0.15

3 nm 4 nm

0.1

5 nm

0.05

10 nm 0 13 10

10

14

10

15

10

16

10

17

10

18

10

19

Average electron concentration (cm-3) Figure 5. Minimum energy of first subband vs. average electron concentration in devices with different cross sections. NA =5x1017 cm-3. The small circles represent the average electron concentration at threshold.

3.1. THRESHOLD VOLTAGE AND SUBTHRESHOLD SLOPE

The current, calculated as a function of gate voltage, is shown in Figure 6. The acceptor doping concentration is 5x1017 cm-3 and the gate oxide thickness is 2 nm in all devices. The graph compares devices simulated by classical means (Poisson’s equation (P)) and using the self-consistent Poisson-Schrödinger solver (P+S). The increase of threshold voltage brought about by the reduction of device dimensions can be appreciated by comparing the P and P+S curves. The increase of threshold voltage is negligible in the largest devices but becomes quite significant in the devices with the smallest cross sections. The threshold voltage is not the only parameter influenced by the increase of subband energy levels with gate voltage and electron concentration; the subthreshold slope and the current drive are affected as well. The subthreshold slope is close to 60 mV/decade at T = 300K in the devices with the largest cross sections. The PoissonSchrödinger solver predicts an increase of subthreshold slope in small devices due to the dynamic increase of subband energy levels (and thus threshold voltage) when the electron concentration is increased. The current drive is affected as well. Because of the rapid increase of the subband energy levels (and thus the threshold voltage) with increased electron concentration above threshold, the drain current predicted by the P+S

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QUANTUM EFFECTS IN TRIGATE SOI MOSFETS

simulator is lower than the drain current calculated using a classical Poisson solver. The drive current is approximately 15% smaller in the P+S calculations for a gate voltage overdrive (VG – VTH) of 300 mV in all devices. The study of the evolution of threshold voltage with device dimensions is more complicated than that of the subthreshold slope. Since devices with different cross sections have different average electron concentrations and different shapes of electron distributions at “threshold”, the classical definition, based on ΦS=2ΦF cannot be used. Furthermore the presence of volume inversion complicates the definition of threshold voltage. Here we will define the threshold voltage as the gate voltage for

d 2ID which reaches a maximum18. The threshold calculated using dVG2 Poisson’s equation only (P) increases as the device section decreases. This effect is due to the need for a higher electron concentration to build up a charge that varies linearly with gate voltage in smaller device, (Figure 6) and to the reduction of volume-inversion subthreshold current in devices with a reduced cross section. A similar effect is observed in thin, doublegate devices19. An additional increase in threshold voltage increase is observed when quantum effects are taken in consideration (P+S) because of the increase of the energy levels at reduced dimensions. 10

10

-6

W = tsi = 20 nm

-7

Drain current (A)

10 nm 10

10

10

10

10

-8

-9

5 nm 3 nm

-10

2 nm .. Schrodinger P Poisson P+S

-11

-12

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

Gate voltage (V) Figure 6. Drain current vs. gate voltage in trigate MOSFETs with different cross sections. Devices are simulated using either Poisson’s equation only (P) or the Poisson+Schrödinger solver (P+S). VDS = 50 mV, tox = 2 nm, NA = 5x1017 cm-3.

QUANTUM EFFECTS IN TRIGATE SOI MOSFETS

137

4. Mobility Effects The density of states (DoS) of the devices shown in Figure 1 is shown in Figure 7. The energy levels are relative to the 3D conduction band minimum when the device is biased under flatband conditions, EC0. The energy values are negative because of the downward band bending due to the application of a positive gate bias (VG=VTH) during the simulation. In the sample with Wsi = 45 nm and tsi = 82 nm, the typical energy difference between subbands (or at least between the two first ones) is on the order of 150 µeV. On the other hand, in the sample with Wsi = 11 nm and tsi = 58 nm, the energy separation is much larger, typically of the order 2 meV. When the gate voltage is increased above threshold the number of populated subbands increases. Intersubband scattering increases with each new subband that becomes populated, which results in mobility reduction and, therefore, oscillations of drain current when gate voltage is increased as shown in Figure 8. Current oscillations can be observed as long as the drain voltage is not significantly larger than the energy separation between subbands, ∆E, divided by the electron charge, q. When the drain voltage is very small (ideally zero) electrons flow from source to drain in parallel “channels” corresponding to the different subbands. When the drain voltage is increased, the number of “channels” decreases near the drain, which smears out the oscillations. However, damped oscillations are still visible when qVDS is a few times larger than ∆E. In Figure 8 the subband energy separation is equal to 0.15 mV when Wsi=45nm and tsi=82nm and oscillations are observed at VDS=0.2mV (Figure 8). -0.75

-0.558

Wsi = 45 nm tsi = 82 nm

Energy above ECo (eV)

-0.5582

Energy above Eco (eV)

Wsi = 11 nm tsi = 58 nm

-0.755

-0.5584 -0.5586 -0.5588 -0.559

-0.76

1 meV

-0.765

-0.5592 -0.5594 -0.5596

150 µeV

5 meV

-0.77

-0.5598 -0.56 0

1

2

3

4

Density of states (cm-3 eV-1)

5 x 10

20

-0.775

0

2

4

6

Density of states (cm-3 eV-1)

8

10 x 10

20

Figure 7. Density of states at VG=VTH calculated for a Trigate SOI MOSFETs with dimensions corresponding to the cross sections shown in Figure 1. Left: Device with Wsi=45nm and tsi=82nm; Right: Device with Wsi=11nm and tsi=58nm.

138

QUANTUM EFFECTS IN TRIGATE SOI MOSFETS -7

x 10

Current (A)

3.5

T=4.4K, VDS=0.2mV

3 2.5 2

T=8K, VDS=0.2mV T=5K, VDS=50mV (x 0.004)

1.5 1

T=150K, VDS=0.2mV

0.5 0 0

Effective mobility (cm 2 V-1 s -1 )

4

T=28K, VDS=0.2mV 0.1

0.2

1200

800

T=8K

600 T=28K

400 T=150K 200 0 0.05

0.3

Gate Voltage (V)

T=4.4K

1000

0.1

0.15

0.2

Gate Voltage (V)

0.25

0.3

Figure 8. Drain current vs. gate voltage for different temperature and drain voltage values in the device with Wsi=45nm and tsi=82nm (Left). The amplitude of the curve for VDS=50mV is multiplied by a factor 200µV/50mV=0.004 to fit in the same graph as the curves measured at VDS=200µV. Right: effective mobility calculated from g = µ C Weff V . m

eff

ox

L

DS

Figure 9 shows the conductance, defined as the drain current divided by the drain voltage, measured as a function of gate voltage in a device with Wsi=11nm and tsi=58nm. The measurement was carried out at room temperature. Oscillations can clearly be seen when the drain voltage is 100 µV. The magnitude of the oscillations decreases when the drain voltage is increased, but they are still visible at VDS=1mV. When the drain voltage is 5 mV however, the oscillations are no longer present. This result supports that the average subband energy separation is indeed the 2 meV, predicted by the simulation result shown in Figure 7.

Drain conductance (S)

20

x 10

-4

VDS = 100 µV

15

200 µV 400 µV 10

500 µV 1 mV

5

5 mV 0

-5

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Gate voltage (V)

Figure 9. Drain conductance, ID/VD, vs. gate voltage measured for different drain voltage values, in a device with Wsi=11nm and tsi=58nm.

QUANTUM EFFECTS IN TRIGATE SOI MOSFETS

139

The oscillations measured in an individual device are reproducible from measurement to measurement and are independent of the integration time (short, medium or long). The oscillations, however, differ from device to device. This is not surprising since each device is made of 20 fins in parallel and since any variation in device width or height will affect the position of the energy levels. It can be noted that the conductance drops when drain voltage is increased. When the drain voltage is equal to zero the electron concentration in the different subbands is constant along the channel. When the drain voltage is increased, the population in the higher subbands decreases near the drain. This forces some electrons to jump from higher to lower subbands, which increases intersubband scattering and reduces the mobility. 5. One- vs. Two-dimensional behaviour The calculations presented in this paper are all based on the assumption that a one-dimensional Density of States (DOS) can be used. If a device is significantly taller than it is wide (e.g. in a FinFET), one may wonder if this assumption is still valid, or if a two-dimensional DoS should be used. Onedimensional DoS is characterized by a series of spikes described by Equation (2). Each spike corresponds to an electron energy level. Figure 10 shows the electron concentration profile and the DoS in devices with a width of 5 nm and thicknesses of 5, 25 and 100 nm. The simulations were carried out for a gate voltage equal to the threshold voltage. Threshold was determined by measuring the gate voltage at which d 2 I D dVG2 reaches a maximum18. The electron concentration is approximately equal to 5×1017 cm-3 in all cases. In the device with the smallest cross section (5nm × 5nm), the electron distribution is clearly one-dimensional. The density of states is clearly composed of a succession of individual peaks. When the silicon thickness is increased to 25 nm, the energy separation between the different peaks decreases and “group of peaks” start to form in the DoS. When the fin height is increased to 100nm (the width is still 5nm) the electron distribution takes a definite two-dimensional shape as shown in Figure 10. The 1D peaks of the DoS clearly regroup in bundles that give the overall DoS distribution a definite 2D appearance, i.e. a staircase-like function. In this case, the device could be simulated using a simpler 2D DoS, but the results obtained from Equation (2) are still valid, and the 1D DoS distribution naturally converges to a 2D-like distribution. Figure 10 shows that the 1D or 2D nature of a sample can simply be deduced from looking at the shape of the DoS.

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QUANTUM EFFECTS IN TRIGATE SOI MOSFETS

Figure 10. Electron concentration profile at VG=VTH in trigate MOSFETs with a width, Wsi, of 5 nm and a thickness, tsi, of 5, 25, and 100 nm. The corresponding DoS (Density of States) is shown.

QUANTUM EFFECTS IN TRIGATE SOI MOSFETS

141

6. Conclusion This paper describes low-dimensional nanowire quantum effects that occur in small trigate SOI MOSFETs. 2D numerical simulation is used to calculate the electron concentration profile as a function of gate voltage in devices with different cross sections. The smaller the section, the higher the threshold voltage. A dynamic increase of threshold voltage with electron concentration is observed. Inter-subband scattering causes oscillations of the transconductance when measured as a function of the gate voltage. These oscillations are visible at low temperature (< 30K) in samples with a 45 × 82nm cross section and at room temperature in devices with a 11nm × 48nm cross section.

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3. 4. 5.

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10. J.G. Fossum, L. Ge, M.H. Chiang, V.P. Trivedi, M.M. Chowdhury, L. Mathew, G.O. Workman, B.Y. Nguyen, A process/physics-based compact model for nonclassical CMOS device and circuit design, Solid-State Electron. 48(6), 919-926 (2004) 11. V.P. Trivedi, J.G. Fossum, Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs, IEEE Electron Device Letters, 26(8), 579-582 (2005) 12. J.P. Colinge, X. Baie and V. Bayot, Evidence of two-dimensional carrier confinement in thin n-channel gate-all-around (GAA) devices, IEEE Electron Device Letters 15, p. 193 (1994) 13. X. Baie and J.P. Colinge, Two-dimensional confinement effects in gate-all-around (GAA) MOSFETs, Solid-State Electron. 42(4), 499-504, (1998) 14. J.P. Colinge, J.C. Alderman, W. Xiong, and C.R. Cleavelin, Quantum-Mechanical Effects in Trigate SOI MOSFETs, IEEE Transactions on Electron Devices 53(5), 11311136 (2006) 15. J.P. Colinge, A.J. Quinn, L. Floyd, G. Redmond, J.C. Alderman, W. Xiong, C.R. Cleavelin, T. Schulz, K. Schruefer, G. Knoblinger, P. Patruno, Low-Temperature Electron Mobility in Trigate SOI MOSFETs, IEEE Electron Device Letters 27(2 ), 120122 (2006) 16. J.P. Colinge, W. Xiong, C.R. Cleavelin, T. Schulz, K. Schrüfer, K. Matthews, P. Patruno, Room-Temperature Low-Dimensional Effects in Pi-Gate SOI MOSFETs, IEEE Electron Device Letters, 27(9), 775-777 (2006) 17. J.H. Davies, The physics of low-dimensional devices (Cambridge University Press, 1998) p. 163 18. P. Francis, A. Terao, D. Flandre, and F. Van de Wiele, Modeling of ultrathin doublegate nMOS.SOI transistors, Solid-State Electron. 41(5), 715-720 (1994) 19. A. Ortiz-Conde, F. García Sánchez, J. Muci, Rigorous analytic solution for the drain current of undoped symmetric dual-gate MOSFETs, Solid-State Electron. 49, 640-647 (2005)

SEMICONDUCTOR NANOSTRUCTURES AND DEVICES JOACHIM KNOCH* AND HANS LÜTH* Institute of Bio- and Nanosystems, IBN-1, Forschungszentrum Jülich, D-52425 Jülich, Germany * To whom the correspondence should be addressed: : Joachim Knoch, IBM Research GmbH, Zurich Research Laboratory, Säumerstrasse 4, 8803 Rüschlikon, Switzerland, [email protected]; Hans Lüth, Institute of Bio- and Nanosystems, IBN-1, Forschungszentrum Jülich, 52425 Jülich, Germany, [email protected].

Abstract. In this paper we present semiconductor nanostructures and devices for future nanoelectronics applications. New device architectures for advanced CMOS as well as novel concepts for a beyond CMOS scenario are presented and discussed. We study SOI Schottky-barrier MOSFETs and show methods for improving the device performance using dopant segregation during silicidation as well as ultrathin body SOI and ultrathin gate oxides. Furthermore, electronic transport in GaN and InN nanowire structures is discussed. In addition, novel device concepts are also introduced and the electronic transport in such structures is studied. In particular, nanoscale resonant tunneling diodes with improved peak-to valley ratio and a band-to-band tunneling transistor based on a nanowire/ nanotube that allows for subthreshold swing smaller than 60mV/dec are presented.

Keywords: Nanowire; band-to-band tunneling; tunneling FET; SB-MOSFET; RTD

1. Introduction The continued down-scaling of bulk-silicon MOSFETs will become increasingly difficult and eventually come to an end in the near future. A loss of gate control over the channel, high gate leakage currents and increasing parasitic resistances of the source and drain electrodes, for instance, will strongly deteriorate the device performance. A continuation of CMOS technology thus makes the introduction of new device architecttures and new materials necessary. Beyond todays CMOS technology, novel concepts have to be introduced that either rely on different switching mechanisms in CMOS circuitry or even on completely new logic functionality. 143 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 143-158. © 2007 Springer.

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In the present paper we elaborate on both aspects, that is, new architectures as well as novel concepts. Examples of some solutions to the aforementioned issues are presented and discussed. 2. New device architectures Scaling MOSFETs to the smallest dimensions makes necessary the introduction of new materials not only to facilitate suppression of short channel effects but also for the source/drain electrodes. In the following we discuss Schottky-barrier (SB)-MOSFETs with metallic source and drain electrodes and show ways to significantly improve their performance. In addition, GaN and InN nanowires and their electronic transport properties are discussed as examples for more general one-dimensional semiconductor devices structures. 2.1. SOI SCHOTTKY-BARRIER MOSFETS

Schottky-barrier (SB) MOSFETs offer solutions associated with a number of issues related to source/drain engineering (Dubois and Larrieu, 2004; Fritze et al., 2004) such as very low extrinsic parasitic resistances, ideally abrupt contact-channel interfaces and ultra-shallow junction depths. However, Schottky contacts to date exhibit significant barrier heights much larger than kBT at the interface between the metal and the silicon and it is found that negative SBs are needed for a SB- MOSFET to exhibit a similar performance as a conventional MOSFET (Guo and Lundstrom, 2002). As a result, over a rather large gate voltage range, the drain current is determined by tunneling of carriers through the Schottky-barriers leading to poor subthreshold behavior and lower on-currents compared to conventional type devices (Knoch and Appenzeller, 2002). Therefore, improving the tunneling probability through the SB is mandatory if SB-MOSFETs are to become a viable alternative to conventional MOSFETs. In the following sections we will show two approaches to improve the carrier injection using dopant segregation during silicidation and ultrathin body (UTB) SOI and gate oxides. 2.1.1. Dopant segregation during silicidation Ohmic metal-semiconductor contacts are usually realized by heavily doping the semiconductor which leads to a thin SB through which carriers can easily tunnel. However in the fully-depleted SOI devices considered here,

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10

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doping the channel leads to a shift of the threshold voltage Vth but does not increase the tunneling probability through the SB. Therefore, non uniform doping profiles have to be generated with a highly doped layer only at the contact channel interface as depicted in Fig. 1 (a). As a result, strong band bending occurs yielding an increased tunneling probability through the SB without shifting Vth. Such a doping profile can be realized by dopant segregation during silicidation. Here, dopants redistribute during the silicidation process and are piled up at the silicide-silicon interface (Kinoshita et al., 2004; Zhang et al., 2006). We have confirmed this pile-up with a detailed SIMS study of the dependence of the arsenic segregation in bulk-silicon samples on initial implantation energy, silicide thickness and process flow. Figure 1 (b) displays a typical SIMS spectrum showing that indeed arsenic dopant concentrations ≥ 1020 cm-3 can be realized with an initial implantation dose of 5×1014 cm-2 and larger. In order to study the impact of dopant segregation on the Schottky barriers, SB-MOSFETs have been fabricated as schematically shown in Fig. 2. After thinning the SOI to a thickness of ≈25 nm, a gate oxide was grown and poly-silicon deposited. Subsequently, the source and drain areas were implanted with arsenic at a dose of 5×1014 cm-2 and an energy of 5keV. Then, without activation, spacers were formed and samples were coated with nickel. The last steps include a full silicidation of the contacts at 450°C for 20s and the removal of superficial nickel. The silicidation conditions are such that the silicide encroached underneath the spacer towards the beginning of the gated area as can be seen in the right panel of Fig. 2, whereby the dopants in the spacer regions are piled up at the silicidesilicon interface.

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Figure 2. Fabrication process of SB-MOSFETs with dopant segregation. The right panel shows a cross-sectional TEM image of a real device.

Figure 3. Transfer (a) and output (b) characteristics of a SB-MOSFET with dopant segregation.

Figure 3 shows transfer characteristics of a SB-MOSFET with dopant segregation. The device with segregation exhibits a rather n-type behavior with one order of magnitude larger on-currents compared to control samples without dopant segregation (not shown here). The most prominent feature of the characteristics however is, that the subthreshold swing S for electron injection is 70mV/dec which is close to the thermal limit and indicates that the off-state of the device incorporating dopant segregation is determined by thermal emission rather than tunneling. This is also supported by the output characteristics of Fig. 3 (b), which show a linear current increase for small bias. This means that the device with dopant segregation behaves like

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an SB-MOSFET with very low SB heights. The reason for this behavior is displayed in Fig. 4 which shows schematically the conduction band profile at the source channel interface for four different gate voltages (1-4V); the two dashed lines belong to the device off-state whereas the other two are for gate voltages in the on-state. For a sufficiently high doping level in the segregation layer, the band bending at the contact-channel interface is strong enough to render the tunneling probability so high that the device off-state is determined by the bulk potential in the channel rather than the SB; that is, the situation is similar to a conventional MOSFET. In a fullydepleted SOI device, a change of gate voltage leads to a commensurate change of the bulk potential barrier and as a result S ≈ 60 mV/dec is obtained. For each gate voltage an effective SB ΦeffSB for thermal emission can be associated with the resulting conduction band profile. In order to find out the dependence of ΦeffSB on Vgs we performed temperaturedependent measurements of the I-V characteristics and extracted ΦeffSB for several Vgs (Zhang et al., 2005). The result of this analysis is shown in Fig. 4(a). In the device off-state ΦeffSB indeed changes on a one-to-one basis with changing gate voltage, i.e. the effective SB in this case is the bulk potential as has been discussed above. For larger Vgs, that is in the device on-state, ΦeffSB can be manipulated by the gate only slightly leading to a certain on-state current. Looking again at Fig. 4(a) one can extract a new, reduced SB due to dopant segregation from the point where the curve deviates from the one-to-one behavior (Appenzeller et al., 2004). In the present case this barrier is ~0.1 eV much lower than the original barrier of 0.64 eV, meaning that by using dopant segregation, the SB can be lowered very effectively. source

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2.1.2. Impact of the gate oxide and SOI thickness In a recent publication we investigated the impact of the SOI and gate oxide thicknesses (dsoi and dox, respectively) on the electrical behavior of SBMOSFETs (Knoch and Appenzeller, 2002). It was found that both ultrathin dsoi and dox are beneficial for the injection of carriers through the SB. In order to show this performance improvement experimentally, we fabricated a number of devices with different SOI and gate oxide thicknesses. Figure 5 shows typical results where (a) displays devices with a constant dox and varying dsoi whereas (b) shows transistors with varying gate oxide thickness and constant initial SOI thickness. In both cases, the on-state current and the off-state in terms of the subthreshold, are improved consistent with our simulation study (Knoch and Appenzeller, 2002). To quantify the impact of a varying dox and dsoi on the carrier injection through the SB we chose the subthreshold swing as a relevant figure of merit since the value of S is insensitive to parasitic source/drain resistances and also - in case of SB heights larger than several kBT, is insensitive to variations of the actual SB height. It is important, however, to keep in mind that a steeper S implies increased carrier injection and hence an improved on-state of the devices. The S-values of various devices where extracted and are plotted in Fig. 5(c) (for details on the device fabrication and the extraction procedure of S, see Zhang et al., 2006). It can be seen that indeed S depends increasingly on dsoi as dox becomes larger. The straight lines indicate an analytical calculation of S where we employed the surface potential model of Young (Young, 1989) (see eqn. (2)) and replaced the actual potential

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distribution of the Schottky barrier with a lower effective SB for thermal emission only. As a result (Knoch et al., 2006) ⎛ ⎞ ε si S ≈ k BT / q ln(10) ⎜⎜ 1/ 2 + d soi d ox / d ⎟⎟ ε ox ⎝ ⎠

(1)

where, d is a tunneling distance/thickness of the SB beyond which tunneling can be neglected; all other symbols have their usual meaning. Since d only very weakly depends on dox and dsoi it is considered as constant; d = 3.7 nm in the present case. The obvious agreement between experimental data and calculation shows that indeed S and hence the injection of carriers through the Schottky barrier strongly depends on dsoi and dox. Using UTB SOI and ultrathin gate oxides allows realization of an effectively thinner SB thereby increasing the tunneling probability which in turn improves the on- and offstate of SB MOSFETs. We can consider an upper limit for acceptable S values, then from Fig. 5(c) it becomes apparent that this can be achieved by making dox ultrathin relaxing the requirement for the SOI body thickness and vice versa. A special class of SB-MOSFETs with ultimately thin body are carbon nanotube FETs. Due to their inherent small diameter in the few nanometer range, excellent carrier injection even for larger gate oxide thicknesses is obtained. For instance, in CNFETs S-values of 100mV/dec were found in the case of a device with a gate oxide as thick as 10nm (Lin et al., 2005). CNFETs with metallic source/drain contacts behave as Schottky-barrier FETs and thus exhibit a strong dependence of S on dox as was recently shown experimentally (Appenzeller et al., 2002). In such ultrathin body FETs the carrier injection is high and hence it can be expected that the effective SB height will be rather small. We therefore took temperature dependent measurements using the same procedure as described above and extracted ΦeffSB using thermal emission theory (Appenzeller et al., 2004). It turns out that the effective Schottky-barrier in such an ultimate UTB SB-MOSFET can be influenced by the gate even well into the on-state; that is, the barrier is significantly lowered even in the device on-state. It is therefore interesting to combine dopant segregation with UTB SOI and gate oxides. In order to investigate such a combined approach we have performed quantum simulations of SOI SB-MOSFETs (Knoch and Appenzeller, 2002) using the surface potential model mentioned above. In this model, the two-dimensional potential distribution in MOSFET devices is well described by a 1D, modified Poisson equation (Young, 1989) given by

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d 2Φ f dx

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λ

2

e ( ρ ( x) + N seg )

=

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ε 0ε si

where Φf, Φg and Φbi are the surface potential, the gate potential and the builtin potential, respectively; λ = ε si ε ox d ox d si is the relevant length scale over which potential variations are screened. The effect of dopant segregation is accounted for by a step-function like doping profile of spatial extension lseg and doping concentration Nseg right at the contact-channel interfaces. The charge ρ(x) in and current through the channel is calculated self consistently employing the non-equilibrium Green’s function formalism (NEGF) (Datta, 1995). For simplicity, ballistic transport is assumed in order to give an upper estimate of the possible device performance. Although simple, the model reproduces the main experimental observations (for more details see Ref. (Knoch et al., 2005) and references therein). We have simulated transfer characteristics of SB-MOSFETs with DS (Nseg = 2×1020 cm-3, lseg = 2 nm) and a fixed SB of 0.64eV for two different body and oxide thicknesses, namely (1) dox = 1 nm, dsi = 5 nm and (2) dox = 5 nm, dsi = 25 nm. A channel length of L = 60 nm in case of (1) and L = 160 nm in the case of (2) was found to be sufficient to ensure long-channel behaviour. Figure 6(a) shows ΦeffSB as extracted from the simulations as a function of gate voltage. The one-to-one change of ΦeffSB with Vgs for small gate voltages, that is in the device off-state, shows that the effective SB is not determined by the actual SB but rather by the bulk potential in the channel as in a conventional MOSFET. Hence an almost ideal off-state can be expected as indeed observed in the simulations of Fig. 6(b). However, for larger gate voltages in the on-state, it is obvious for the case of device (1) that the effective SB can be further reduced in contrast to the transistor (2). This is due to the improved gate control over the potential distribution of the SB in the case of (1) which as a result leads to much larger 0.6

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Figure 6. (a) vs. Vgs extracted from the simulations and transfer characteristics (b) for a device of type (1) with thin dsoi,ox (black curve) and (2) with thick dsoi,ox (gray curve).

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on-currents as can be seen in Fig. 6(b). Therefore, combining dopant segregation with UTB SOI and ultrathin gate oxides is a promising approach to make the intrinsic SB-MOSFET performance comparable to that of conventional devices. 2.2. NANOWIRE DEVICES

Semiconductor nanowires are an attractive material for future ultimately scaled devices as their geometrical shape is ideally suited for surround-gate FETs. However, as nanowire diameter decreases, the surface plays an increasingly important role. Due to Fermi level pinning at semiconductor surfaces, a depletion layer builds up with an extension of the same order as the wire diameter for thin nanowires. Hence completely depleted wires can be obtained. Thus the influence of the diameter on the electronic transport through GaN and InN MBE-grown nanowires has been investigated (Calarco et al., 2005; Meijers et al., 2006).

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Figure 7. (a) I-V characteristics of GaN nanowires with different diameters. The insets show schematically the Fermi level pinning in the wires with respect to the band edges Ec,v. (b) SEM image of self-assembled GaN wires. (c) shows an SEM image of a nanowire contacted with metallic electrodes.

Figure 7(b) shows an SEM image of self-assembled GaN nanowires grown in MBE under nitrogen-rich conditions (Meijers et al., 2006). After growth, the nanowires are dispersed on an oxidized silicon wafer and contacted with metal electrodes using e-beam lithography and a lift-off process, as displayed in Fig. 7(c). Current-voltage characteristics of GaN nanowires exhibiting different diameters were measured. As can be seen in Fig. 7(a), in the case of GaN wires the thinner nanowire exhibits a drastically lower current compared to the nanowire with larger diameter. The reason for this has already been mentioned above and is displayed in the inset of Fig. 7(a). The Fermi level pinning within the band gap leads to a completely depleted wire in the case of a thin GaN wire, thus setting a lower limit for diameter reduction. Recently, InN nanowires exhibiting very

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promising properties were investigated (Stoica et al., 2006). Due to surface accumulation, the current through an InN nanowire is insensitive to diameter variation (Calarco and Marso, 2006). This property together with a band gap of approximately 0.75eV makes InN nanowires an attractive material for future electronics applications. 3. Novel concepts Beyond the scaling of today’s CMOS technology, novel device concepts have to be introduced either leading to a completely new logic or making use of CMOS logic but employ alternative switching mechanisms. In the following we will discuss two examples namely a band-to-band tunneling FET and nanoscale resonant tunneling devices. 3.1. TUNNELING FIELD-EFFECT TRANSISTORS

The power consumption of highly integrated circuits becomes more and more the central issue calling for high-performance, low power transistor devices. In this respect the limitation of conventional-type FETs to a subthreshold swing of 60mV/dec is a major obstacle to further reduce the supply voltage while maintaining constant device on/off-current ratio. The reason for this is that all conventional devices rely on the modulation of carrier transport injected from a thermally broadened Fermi function. Tunneling FETs (t-FETs) on the other hand have recently attracted a great deal of interest due to their potential of providing S < 60 mV/dec (Appenzeller et al., 2005; Knoch and Appenzeller, 2005). In fact, employing a dual-gate device architecture, a t-FET based on carbon nanotubes was demonstrated for the first time to exhibit an S = 40 mV/dec (Appenzeller et al., 2004). A t-FET consists of an n-doped source(drain), an intrinsic channel and a p-doped drain(source). In such a device, the carrier injection into the channel is mediated by band-to-band tunneling (BTBT) through the potential barrier at the source-channel junction. Hence, in order to obtain a large on-state current it is necessary that the BTBT barrier is as thin as possible. However, from the analysis in section 2.1.2 we know that an ultrathin channel layer together with a thin gate dielectric leads to a screening of potential variations on the length scale, λ. The BTBT barrier is such a potential variation and hence can be made thin if the device architecture is chosen so as minimise λ. It has been shown that a cylindrical surround-gate transistor layout based on a nanowire/tube yields the best electrostatic control over the channel and hence the smallest possible λ

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(Auth and Plummer, 1997). Therefore we will consider only nanowire t-FETs as follows. The switching mechanism of a t-FET is illustrated in Fig. 8 which shows the conduction and valence bands in the device off-state (a), around threshold (b) and in the on-state (c). The respective current spectra are shown as well (gray lines). In the off-state the band gap of source, channel and drain effectively block current transport leading to a low off-state leakage. However, once the valence band in the channel is lifted above the conduction band in the source, a conducting channel via BTBT is opened up. Looking at the current spectra in the device on-state it becomes apparent that a significant current contribution stems exclusively from the energetic window between the valence band edge in the channel and the conduction band edge in the source contact, that is, the band gap in the source and channel represent a bandpass filter cutting off the high and low energy tails of the Fermi function which can be considered as an effective cooling of f(E). This bandpass filter behaviour is the reason why t-FETs can exhibit an S < 60 mV/dec at room temperature. We have simulated a nanowire t-FET using the NEGF on a finite difference grid. For the electrostatics we use the modified Poisson equation (2) given above (for more details on the calculations see Ref. (Knoch and Appenzeller, 2006)) and rather aggressively scaled geometrical parameters are chosen in the present case as shown in Fig. 9(b). Figure 9(a) displays a gray-scale plot of the local density of states which shows a large DOS in the BTBT barrier yielding in turn a large tunneling probability. Figure 9(b) shows the transfer characteristic of the simulated t-FET with S = 15 mV/dec over several decades of current. For comparison, S = 60 mV/dec is shown as well. It is apparent that in a t-FET a superior off-state can be realized compared to conventional FET devices. On the other hand the BTBT barrier also leads to lower on-state currents than achievable in conventional transistors. However, from the intrinsic device point of view, the on-state Vgs = -0.2V channel

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Figure 9. (a) Local DOS in a t-FET and (b) transfer characteristic for the simulated t-FET.

current is not the best metric to qualify a device. A better measure is the device delay time τ = CgVdd/Id where Cg is the total gate capacitance and Vdd the supply voltage. In a one-dimensional system the so-called quantum capacitance limit can be reached, i.e. Cox >> Cq with Cq being the quantum capacitance (Luryi, 1988) and as a result, Cg ≈ Cq. Using the WKB approximation for the BTBT probability it can be shown that to first order Cq as well as Id are proportional to the BTBT probability (Knoch et al., 2007); that is, Cg is decreased directly with Id for decreasing tunneling probability (if for example, dox is increased). As a result, the tunneling probability to first order does not affect τ. Note that this is a specific feature of one-dimensional t-FETs and together with the small geometry makes nanowires ideally suited for the realization of such devices since a superior off-state can be combined with an excellent on-state performance. 3.2. NANOSCALE RESONANT TUNNELING DEVICES

Resonant tunneling devices have recently attracted an increasing interest as quantum devices which operate at room temperature. The interest stems from the fact that due to the particular electric characteristics, RTDs allow for more complex logic circuits with fewer electronic parts. As a general feature, RTDs exhibit a current peak and a region of negative differential resistance (NDR). This behavior results from a peaked transmission coefficient of the double barrier structure in conjunction with the injection electron distribution from the emitter. The ratio between the peak current and the valley current in the NDR region, the peak-to-valley ratio (PVR), serves as a figure of merit of the RTD. The impact of the geometrical size of RTDs on their electronic transport was investigated by fabricating nanocolumn RTDs with varying diameters in the range of 1µm down to 50nm using a top-down approach. For the present experiments, vertical

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Figure 10. PVR vs. column diameter of nanoscale RTDs. The data points represent average results measured on 5-6 equally prepared devices. (b) displays the I-V-characteristic of an RTD with 50nm column diameter; the inset shows an SEM of the same column.

GaAs nanocolumns with two embedded AlAs barriers were processed by e-beam lithography from an MBE-grown layer stack. The heterostructure exhibits a symmetrical layer sequence with an undoped part around the quantum well which in turn is cladded with highly n-doped regions (for details see Ref. (Wensorra et al., 2005)). The heterostructure is capped by a thin layer of low-temperature grown GaAs enabling excellent non-alloyed ohmic contacts using a Ti/Au metallization. Nanocolumns were patterned out of this heterostructure/metal stack using e-beam lithography followed by ion beam and reactive ion etching. The inset of Fig. 10(b) shows a fabricated nanocolumn with a diameter of 50nm. DC measurements at room temperature have been carried out on the processed nanodevices and the PVR has been extracted from the measurements. Figure 10(a) displays the extracted PVRs as a function of column diameter. Reducing the diameter first leads to a decrease of the PVR due to a relative increase of surface scattering. However, below ∼80nm the PVR strongly increases again. This unusual behavior can be explained by looking at the conduction band profile in the nanocolumn. As it turns out, the large depletion length in the undoped region of the column leads to the formation of a potential barrier when the column diameter is of the same order as shown in Fig. 11(b). Due to the highly doped regions cladding the intrinsic part, a saddle point is formed in the undoped region that acts as a quantum point contact. Under bias the saddle point is formed in front of the double barrier and hence the quantum point contact (saddle point) leads to a pre-selection of allowed kz-values as shown schematically in Fig. 11(a). It is this filter behaviour that leads to the increasing PVR with decreasing column diameter (Wensorra et al., 2005). As a result, employing particular doping profiles in combination with nanoscale dimensions

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Figure 11. (a) Schematics of the pre-selection mechanism of kz-values by differently spaced subbands. (b) Conduction band profile Ec in nanscaled RTDs.

enables the creation of a potential landscape that is beneficial for the performance of RTDs and allows for improved PVR in such nanosized resonant tunneling devices. More generally, similar doping profiles with saddle points might improve the performance of all kinds of quasi 1Dnanodevices by quantum collimation of propagating electrons. 4. Conclusion In the present paper we elaborated on semiconductor nanostructures and devices for future nanoelectronics applications. SB-MOSFETs as well as nanowire structures were presented as possible solutions to issues related to advanced CMOS devices. Two ways of increasing the carrier injection in SB-MOSFETs were shown that allow for high performance devices. In addition, GaN and InN nanowire structures were presented and discussed as possible future channel material. Moreover, we also studied novel device architectures, in particular a BTB tunneling FET that allows for an off-state superior to any conventional FET and a resonant tunneling diode. Here the use of nanoscale dimensions together with a particular doping profile enabled an improved PVR in such RTD devices.

References Appenzeller, J., Knoch, J., Derycke, V., Wind, S., and Avouris, Ph., 2002, Field-modulated carrier transport in carbon nanotube transistors. Phys. Rev. Lett., 89:126801-1 – 4. Appenzeller, J., Knoch, J., Radosavljevic, M., and Avouris, Ph., 2004, Multi-mode transport in schottky barrier carbon nanotube field-effect transistors. Phys. Rev. Lett., 92:226802-1 – 4. Appenzeller, J., Lin, Y. M., Knoch, J., and Avouris, Ph., 2004, Band-to-band tunneling in carbon nanotube field-effect transistors. Phys. Rev. Lett., 93:196805-1 – 4.

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Appenzeller, J., Radosavljevic, M., Knoch, J., and Avouris, Ph., 2004, Tunneling versus thermionic emission in one-dimensional semiconductors. Phys. Rev. Lett., 92:048301-1 – 4. Appenzeller, J., Lin, Y. M., Knoch, J., Chen, Z., and Avouris, Ph., 2005, Comparing carbon nanotube field-effect transistors - The ideal choice: A novel tunneling device design. IEEE Trans. Electron Dev., 52:2568 – 2576. Auth, Ch. P. and Plummer, J. D., 1997, Scaling theory for cylindrical, fully depleted, surrounding-gate MOSFET’s. IEEE Electron Dev. Lett., 18:74 – 76. Calarco, R., Marso, M., Richter, Th., Aykanat, A. I., Mejers, R., Hart, v.d., A., Stoica, T. and Lüth, H., 2005, Size-dependent Photoconductivity in MBE-grown GaN-nanowires. Nano Lett., 5:981 – 984. Calarco, R. and Marso, M., GaN and InN nanowires grown by MBE: a comparison, 2005, cond-mat/0611674. Datta, S., 1995, Electronic Transport in Mesoscopic Systems, Cambridge University Press. Dubois, E. and Larrieu, G., 2004, Schottky-barriersource/drain MOSFETs on ultrathin SOI body with tungsten metallic midgap gate, IEEE Electron Dev. Lett., 25:801 – 803. Fritze, M., Chen, C. L., Calawa, S., and Yost, D., 2004, High-speed Schottky-barrier pMOSFETs with fT = 280GHz, IEEE Electron Dev. Lett., 25:220 – 222. Guo, J., and Lundstrom, M. S., 2002, A computational study of thin-body, double-gate Schottky barrier MOSFETs, IEEE Trans. Electron Dev., 49:1897 – 1902. Kinoshita, A., Tsuchiya, Y., Yagishita, A., Uchida, K. and Koga, J., 2004, Solution for highperformance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique, in: 2004 Symp. VLSI Technol., 168 – 169. Knoch, J., Lengeler, B., and Appenzeller, J., 2002, Quantum simulations of an ultrashort channel single-gated n-MOSFET on SOI. IEEE Trans. Electron Dev., 49:1212 – 1218. Knoch, J. and Appenzeller, J., 2002, Impact of the channel thickness on the performance of Schottky barrier metal-oxide-semiconductor field-effect transistors. Appl. Phys. Lett., 81:3082 – 3084. Knoch, J., Zhang, M., Zhao, Q. T., Lenk, St., Appenzeller, J., and Mantl, S., 2005, Effective Schottky-barrier lowering in silicon-on-insulator Schottky-barrier metal-oxidesemiconductor field-effect transistors using dopant segregation, Appl. Phys. Lett., 87:263505-1 – 3. Knoch, J., and Appenzeller, J., 2005, A novel concept for field-effect transistors - the tunneling carbon nanotube FET, in: Device Research Conf., Conference Digest, 153 – 156. Knoch, J., Zhang, M., Mantl, S., and Appenzeller, J., On the performance of single-gated ultrathin body SOI Schottky-barrier MOSFETs. IEEE Trans. Electron Dev., 53:1669 – 1674, 2006. Knoch, J., and Appenzeller, J., 2006, Carbon nanotube FETs – the importance of being small, in: Hardware Technology Drivers for Ambient Intelligence, Kluwer Academic Publisher. Knoch, J., Mantl, S., and Appenzeller, J., 2007 (in press), Impact of the dimensionality on the performance of tunneling FETs: Bulk- versus one-dimensional devices. Solid-State Electron. Knoch, J., Zhang, M., Appenzeller, J., and Mantl, S., 2007 (in press), Physics of ultrathinbody silicon-on-insulator Schottky-barrier field-effect transistors. Appl. Phys. A. Lin, Y. M., Appenzeller, J., Knoch, J., and Avouris, Ph., 2005, High performance carbon nanotube field-effect transistors with tunable polarities. IEEE Trans. Nanotechnol., 4:1536 – 1544. Luryi, S., 1988, Quantum capacitance devices. Appl. Phys. Lett., 52:501 – 503.

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Meijers, R., Richter, T., Calarco, R., Stoica, T., Bochem, H.-P., Marso, M. and Lüth, H., 2006, GaN-nanowhiskers: MBE-growth conditions and optical properties. J. Crystal Growth, 289:381 – 386. Stoica, T., Meijers, R., Calarco, R., Richter, T., Sutter, E., and Lüth, H., 2006, Photoluminescence and intrinsic properties of MBE-grown InN nanowires. Nano Lett., 6:1541 – 1547. Wensorra, J., Indlekofer, K. M., Lepsa, M., Förster, A. and Lüth, H., 2005, Resonant tunneling in nanocolumns improved by quantum collimation. Nano Lett., 5:2470 – 2475. Young, K. K., 1989, Short-channel effect in fully depleted SOI MOSFET's. IEEE Trans. Electron Dev., 36:399 – 402. Zhang, M., Knoch, J., Zhao, Q. T., Fox, A., Lenk, St. and Mantl, S., 2005, Low temperature measurements of Schottky-barrier SOI-MOSFETs with dopant segregation. Electronics Lett., 41:1085 – 1086. Zhang, M., Knoch, J., Zhao, Q. T., Lenk, St., Breuer, U., and Mantl, S., 2006, Impact of dopant segregation on fully depleted Schottky-barrier SOI-MOSFETs. Solid-State Electron., 50:594 – 600. Zhang, M., Knoch, J., Mantl, S. and Appenzeller, J., 2007 (in press), Improved carrier injection in SOI Schottky-barrier MOSFETs. IEEE Electron Dev. Lett.

MuGFET CMOS PROCESS WITH MIDGAP GATE MATERIAL W. XIONG1*, C. R. CLEAVELIN1, T. SCHULZ2, K. SCHRÜFER2, P. PATRUNO3 AND J.P. COLINGE4 1 SiTD, Texas Instruments Incorporated, Dallas, TX 75265, USA 2 Infineon Technologies, Am Campeon 1-12, 85579 Neubiberg, Germany 3 SOITEC S.A., Parc Technologique des Fontaines – 38190 Bernin, France 4 Dept. of Electrical and Computer Engineering, Univ. of California, Davis, CA 95616, USA *

To whom correspondence should be addressed. [email protected]

Abstract. An increase in threshold voltage is observed in ultra-thin body MuGFET (multi-gate FET) devices. The threshold increase is due to of lack of carriers at the classical threshold definition. A sufficient amount of carrier build-up requires additional gate voltage (0.12V in our experiment).

Keywords: Silicon-on-Insulator, SOI MOSFET, multiple-gate MOSFETs

1. Introduction Advanced transistor structures, such as the Multi-Gate FET (MuGFET), offer improved control of short-channel effects compared to the planar bulk-Si MOSFET. Hence they may be adopted in CMOS technology nodes toward the end of the roadmap. To control the Short Channel Effect (SCE), fins need to be thin, typically less than 2/3 of the gate length1. For the 32nm node, fin width is expected to be <20nm. In this paper we report an increase in threshold voltage for a thin body MuGFET that is not predicted by classical-long channel Vth theory or by the quantum confinement. 2. Device fabrication Standard Unibond® SOI with 60nm silicon top layer, TSi and 150nm buried oxide were used as the starting substrate. The silicon film is p-type with a doping concentration of 2x1015cm-3. Some wafers received additional boron channel implants of 7x1012cm-2. Both inversion-mode N-channel and 159 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 159-164. © 2007 Springer.

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Figure 1. Cross sectional TEM of 11nm fins under the TiSiN gate and polySi capping layer.

Flat Band Voltage, Vfb [V]

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accumulation-mode P-channel devices were made. Fins down to 11nm in width were patterned with 193nm lithography and RIE. A 7nm-thick TiSiN gate layer was deposited by LPCVD on 2nm gate oxide, and then capped with 100nm poly-Si, as shown in Fig. 1. The work function of the TiSiN gate was extracted using the wedding-cake method2. The TiSiN gate has a midgap work function of 4.65eV as depicted in Fig. 2. Gate electrodes down to 50nm were formed. Implanted source/drain dopants were activated by a 1000oC, 10s anneal. BEOL process is conventional AlSi. 3. Electrical measurements Classical single-gate, long-channel inversion-mode n-channel and accumulation-mode p-channel Vth are given by the expressions:

MuGFET CMOS PROCESS WITH MIDGAP GATE MATERIAL Vth _ inv = Φ MS + 2Φ F −

QD 2Cox

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(1)

and

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(2)

respectively. In these equations the oxide charge density, Qox, was neglected.

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Figure 3. CV curve for Lg=10µm with 20, 11nm-fins in parallel. The extracted Qox is 7x1010cm-2.

Figure 3 shows the CV curve of a long channel device. The extracted Qox is less than 1x1011cm-2, a negligible value. Neglecting the QD term which amounts to only a few mV in the n-channel device and the body current in the p-channel device, one finds that the use of a mid-gap gate material yields symmetrical Vth values equal to ±ΦF. The value of ΦF is 0.33V for Na=2x1015 cm-3, which should thus yield long channel Vth=0.33V for nMOS and -0.33V for pMOS transistors. Figure 4 shows the measured threshold voltage roll-off curve. For a long channel device, the threshold voltage is ±0.45V for nMOS and pMOS, respectively. This is 0.12V higher than predicted by the above equations. These values change little with fin width as shown in Fig. 5. When the doping concentration is increased, however, Eqn. (1) becomes valid again. More generally, the following observations can be made: 1. In inversion-mode, for devices with low doping concentration, the electron concentration must be much higher than that at ΦS=2ΦF to reach threshold and Equation (1) is invalid. 2. In inversion-mode devices with high doping concentration, the condition ΦS=2ΦF represents fairly well the inversion threshold and Eq. (1) is valid.

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Figure 5. Linear threshold voltage vs. fin width.

3. In accumulation-mode devices with low doping concentration, the hole concentration must be much higher than that at ΦS=0 to reach accumulation threshold and Eq. (2) is invalid. 4. In accumulation-mode devices with high doping concentration, the condition ΦS=0 represents fairly well the accumulation threshold and Equation (2) is valid.To understand this apparent contradiction we turn to 2D using a self-consistent Poisson-Schrödinger solver3. Figure 6 shows the electron concentration in an n-channel device with fin width=11nm, when the surface potential is equal to 2ΦF and at threshold. When the potential in the silicon is equal to 2ΦF the integrated electron concentration is too low to create any significant potential drop in

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the gate oxide and thus the potential increases linearly with gate voltage, which is typical of subthreshold operation. The gate voltage needs to be increased ~0.12V above this value to produce an electron concentration that varies linearly with gate voltage. This effect is not due to the bandgap widening effect that occurs in devices with dimensions <10nm.3 This effect leads to an increase of threshold voltage with reducing fin width at low doping concentrations and is not found in more heavily doped devices where the 2ΦF threshold criterion corresponds to the existence of a large inversion electron concentration. A similar behavior is found in wider devices as shown in Fig. 7. Accumulation-mode devices are quite insensitive to doping concentration and because the increase of Vth predicted by (1) when Na is increased, is compensated by an increase of body current. Furthermore, an accumulation charge density of several 1017 cm-3 is required to reach a practical threshold value, making it impossible to attain Vth values lower than ~-450 mV.

Figure 6. Electron concentration in 11nm-wide device for different doping and bias conditions.

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Figure 7. Electron concentration in 29nm-wide device for different dopings and biases.

4. Conclusion An increase in threshold voltage is observed in ultra-thin body MuGFET devices. Such threshold increase is due to a lack of carriers at nominal threshold. A significant amount of carrier build-up requires additional gate voltage; 0.12V in our experiments. This increase in threshold voltage dictates that metal gate with mid-band gap work function is required for high-Vth, low-power (LP) applications. For high performance and LP SoC applications, a minimum of three metal gate work functions would be required.

References 1. 2. 3.

J.P. Colinge, Multiple-gate SOI MOSFETs, Solid-State Electronics, 48(6), 7-905 (2004) SEMATECH Engineers Develop Colorful Testing Device to Ease High-k/Metal Search (March 14, 2005); http://www.physorg.com/news3380.html J.-P. Colinge, J.C. Alderman, W. Xiong, and C.R. Cleavelin, Quantum-Mechanical Effects in Trigate SOI MOSFETs, IEEE Trans. on Electron Dev., 53(5), 1131-1136 (2006)

DOPING FLUCTUATION EFFECTS IN MULTIPLE-GATE SOI MOSFETS C.A. COLINGE1*, W. XIONG2, C. R. CLEAVELIN2 AND J.-P. COLINGE3 1 SiTD, Texas Instruments Incorporated, Dallas, TX 75265, USA 2 Infineon Technologies, Am Campeon 1-12, 85579 Neubiberg, Germany 3 Dept. of Electrical and Computer Engineering, Univ. of California, Davis, CA 95616, USA *

To whom the correspondence should be addressed.

Abstract. Random doping fluctuation effects are studied in multiple-gate SOI MOSFETs (MuGFETs) using numerical simulation. The presence of a single doping impurity atom increases threshold voltage. Electrical parameters vary with the physical location of the impurity atom.

Keywords: Silicon-on-Insulator, Doping fluctuations, SOI MOSFET, multiple-gate MOSFETs

1. Introduction Random doping fluctuation effects are known to cause variations of the electrical parameters of short-channel MOSFETs1,2. A trigate device with a channel length, width and height of 1µm, 11nm and 58nm respectively and a doping concentration of 2x1015 cm-3 has a single dopant atom in its channel, on average. If the channel length is 100nm, a doping atom will statistically be found in 10% of the devices. 2. Device simulation In order to evaluate the impact of the presence of individual doping atoms in a trigate MOSFET, three-dimensional simulations were carried out. The Poisson equation is solved numerically in the channel of the devices numerically using Comsol MultiphysicsTM 3. The gate oxide thickness is 2 165 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 165-170. © 2007 Springer.

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nm and the silicon in the channel is nominally intrinsic. The silicon film tsi and device width, Wsi, are variable. A single P-type doping atom is represented by a small sphere with a diameter of 0.5 nm containing an equivalent doping concentration NA=1/V, where V is the volume of the sphere. The doping atom can be moved around and placed at any location (x,y) in the silicon. A midgap gate material is used for all devices. Figure 1 shows the 3D geometry and mesh used in the simulation.

−6

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Figure 1. Channel region of the a trigate device. Left: geometry; Right: simulation mesh.

Figure 2. Electron concentration contours in an undoped trigate device (left) with tsi=Wsi=10nm and VG=0.2V, and concentration contours for a single acceptor doping atom, and VG=0.5V (right).

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Figure 2 shows the electron concentration in an undoped trigate device with tsi=Wsi=10nm biased at threshold (VG=0.2V). It also shows the electron concentration in the same device with a single acceptor doping atom located at (x,y,z)=(5nm,5nm,9nm) (at the top left corner) for a gate voltage of 0.5 V. The doping atom was moved to different positions and the drain current was simulated as a function of gate voltage. Taller devices with tsi=58 nm and Wsi=11nm were simulated as well. Figure 3 shows electron iso-concentration contours for single doping atoms placed at various locations inside such devices. The electrical characteristics of undoped transistors and devices with a single doping atom are shown in Figure 4 (left). The increase of VTH brought about by the presence of a doping atom depends on the position of the atom in the device, as illustrated by Figure 4 (right). In general, ∆VTH is maximum if the atom is near the center of the device cross section and it decreases as tsi or Wsi increases. This was to be expected since the average doping concentration is equal to (L×tsi×Wsi)-1, which increases as the device cross section decreases. Considering the device with an 11nm × 58nm cross section, the introduction of single dopant atom randomly located in the channel increases VTH by 4 to 11 mV. Thus, 2 doping atoms will increase the threshold voltage by up to 22 mV, 3 atoms to 33 mV, etc.

Figure 3. Electron concentration contours for a single acceptor doping atom at different positions in a device with tsi=60 nm, Wsi=10nm and VG=0.5V.

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Figure 4. Drain current vs. gate voltage for trigate devices with L=10nm and VDS=50mV (left) and ∆VTH (mV) relative to undoped device vs. position of a single doping atom in the channel (right).

3. Device fabrication Standard SOI wafers with 60nm silicon top layer and 150nm buried oxide were used as the starting substrate. The silicon film is p-type and the boron doping concentration is 2x1015 cm-3. Silicon fins with a width of 11nm were patterned with 193nm lithography and RIE. A 1.7-nm gate oxide was grown by wet oxidation. A 6 nm-thick TiSiN gate layer was then deposited by LPCVD on the gate oxide, and capped with a 100nm polysilicon layer. The work function of the TiSiN gate is 4.65eV, which makes it a “midgap” gate material.

Figure 5. TEM cross section of a device with tsi=58 nm and Wsi=11nm.

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169

Gate electrodes were patterned using lithography and etched. A combination of dry and wet chemistry was used to etch the poly capping layer and metal gate. Significant over-etch was used to ensure all poly and metal are clear in the undercut region under the fin. The etch selectivity to gate oxide was over 100:1. Source and drain regions were formed by arsenic implantation followed by a 1000o C, 10s anneal step. Classical aluminum/silicon metallization was used to complete the process. The effective gate length of the devices used in this study is 0.25 µm and each device consists of 20 fins operating in parallel. Figure 5 shows a TEM cross-section of one fin from such a trigate SOI MOSFET. The fin width, Wsi, is 11 nm and the fin height, tsi, is 58 nm. 4. Electrical measurements Tri-gate devices with a 11nm × 58nm cross section and different gate lengths were measured. Threshold voltage distributions for gate lengths of 0.09, 0.1 and 1 µm are shown in Figure 6. The VTH mean value and variation increases with gate length, which is consistent with an increased number of doping atoms in longer devices. A more careful observation of the curves reveals that the VTH distribution is not perfectly random, but that VTH tends to increase by “leaps”. Each leap probably corresponds to an additional doping atom in the channel. The average threshold voltage variation between two leaps is 13 mV, which is consistent with the 11 mV of VTH increase produced by the introduction of a doping atom (Figure 4). Counting the number of leaps in Figure 6 (right)

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suggests that having one, two, three or four three doping atoms in the channel are rather equally likely events in devices with L=1µm. 5. Conclusion Random doping fluctuation effects have been modeled and measured in MuGFETs. Typical increase of VTH per doping atom is on the order of 10 mV, and the VTH fluctuation due to the random variation of the atom location is on the order of a few mV. The threshold voltage distribution measured in trigate MOSFETs shows shows “leaps” that can be attributed to the discrete increase of the number of doping atoms on the channel of the devices.

References 1. 2. 3.

H.-S.Wong and Y. Taur, in: Tech. Digest of IEDM (1993), pp. 705-708 A. Asenov, G. Slavcheva, A.R. Brown, J.H. Davies and S. Saini, IEEE Trans. Electron Devices, 48(4) 722-729 (2001) COMSOL MULTIPHYSICS™ (COMSOL, Inc.); http://www.comsol.com/products/multiphysics/

SiGeC HBTs: IMPACT OF C ON DEVICE PERFORMANCE I.Z. MITROVIC1,*, H.A.W. EL MUBAREK2, O. BUIU1, S. HALL1, P. ASHBURN2, J. ZHANG3 1 Dept. of Electrical Engineering & Electronics, University of Liverpool, Brownlow Hill, Liverpool L69 3GJ, UK 2 School of Electronics & Computer Science, University of Southampton, Southampton SO17 1BJ, UK 3 Dept. of Physics, Imperial College London, 908b Blackett Laboratory, Prince Consort Rd, London SW7 2BW, UK *To whom correspondence should be addressed: [email protected]

Abstract. Our UK consortium has recently reported advanced RF platform technology, which includes SiGe Heterojunction Bipolar Transistors (HBT) on Silicon-On-Insulator (SOI). The study in this paper is the continuation of the consortium work, focused on fabricating SiGeC HBTs and on the impact of C (up to 1.6%) on device performance. The devices with low C content (0.45%) exhibit excellent performance and gain up to 500. The results indicate that C content to be used in these devices should be less than 1%.

Keywords: SiGeC HBTs, carbon, Gummel plots, bandgap, leakage currents

1. Introduction The state-of-the-art BiCMOS technologies for wireless and wireline circuits demand SiGeC HBTs with high cut-off frequencies (fT, fmax). An impressive 300 GHz fmax has been reported1 for a self-aligned SiGeC HBT device sustaining high thermal budget. The integration of a high performance SiGeC HBT on a thin film SOI substrate has been reported recently2,3. An addition of carbon into the SiGe epitaxy dramatically reduces the base layer boron diffusion through subsequent thermal processing and thus reduces charge transit time by retaining narrow base layers4. However, introducing carbon atoms may be detrimental to the crystal quality and the epitaxial growth conditions. Carbon related deep levels can be introduced into the

171 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 171-178. © 2007 Springer.

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bandgap, enhancing recombination and hence reducing the carrier diffusion length5, as well as exacerbating carrier generation and hence reverse-bias leakage currents in junctions. The objective of this paper was to study the impact of C content (up to 1.6%) on electrical properties of SiGeC HBT devices. The results show that indeed C contents ≥1% severely degrade transistor performance as indicated by a material study6. 2. Device fabrication SiGeC HBTs were fabricated on (100) 2-3 µm thick n on n+ Si wafers (with a resistivity of 0.8-1.2 Ωcm) at the Southampton University INNOS facility. The active area was defined using a LOCOS process with a 400 nm thick thermal oxide. The active device layers were grown using Molecular Beam Epitaxy (MBE) at Imperial College London7. A 380 nm thick silicon collector layer with a low arsenic doping concentration of 8×1016 cm-3 was grown at 750°C. This thickness was chosen so that the Si collector layer extended over the LOCOS active area. The temperature was then dropped to 550°C for the growth of the SiGe base layer with an average Ge content of 11±2%. An undoped collector base spacer layer with a nominal thickness of 10±5 nm was grown first. This was followed by a 1.5×1019 cm-3 boron doped SiGe base layer with a nominal thickness of 35±5 nm. Then an undoped emitter base spacer layer was grown with a nominal thickness of 14 nm. Finally, a Si cap with a nominal thickness of 50±5 nm and a 5x1017 cm-3 boron concentration, low doped emitter (LDE) layer, was grown. Wafers 9, 10, 11 and 12 also had carbon deposited in the boron doped SiGe base layer with nominal carbon contents of 0.45%, 1.0%, 1.45% and 1.6% respectively. After the deposition of the active device layers, the left half of each wafer received a Selective Implanted Collector (SIC) implant (P+, energy – 288 keV and dose - 6×1013cm-2). The emitter window (EW) was then defined and a 200 nm thick amorphous silicon layer was deposited. This layer was implanted with a 1×1016 cm-2 arsenic dose at 70 keV. The polysilicon emitter was defined with an isotropic polysilicon dry etch. The extrinsic base was implanted with 5×1015 cm-2 boron at 80 keV. The implant was self-aligned to the polysilicon emitter edge. The extrinsic base polysilicon layer was then defined using a dry etch. The collector plug was formed using a 1x1016 cm-2 phosphorus implant at 60 keV. A nominally 600±60 nm thick LTO layer was deposited before an emitter drive-in anneal was done for 60s at 1025°C in nitrogen. This anneal was chosen to allow As diffusion from the emitter polysilicon through the 50 nm thick p-type layer to form the low doped N-emitter. The process was completed by the contact window etch and metallisation as shown in Fig. 1.

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Figure 1. Schematic diagram of SiGeC HBT device layout – final step in the process flow.

3. Results and discussion 3.1. ELECTRICAL ASSESSMENT

The forward and reverse Gummel plots for SiGeC HBTs (transistor T#23, EW size 10x10 µm2) are shown in Fig. 2a)-c) for devices with SIC and no SIC (labelled as inert). Both forward and reverse collector currents for all wafers show ideal characteristics over approximately five decades of current (bias ~ -0.5V), with an associated ideality factor of 1.02. There is a clear shift downwards for collector currents of devices with higher C content (>1% C). This is visible for both types of devices: with and without SIC. The base currents exhibit higher ideality factor (1
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SiGeC HBTs: IMPACT OF C 10

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Figure 2. a) – c) Forward and reverse Gummel plots for SiGeC HBTs with and without SIC (full line – collector current, dashed line – base current).

SiGeC HBTs: IMPACT OF C

175

Gain, β

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Figure 3. Gain vs. collector current.

3.2. EFFECT OF C ON THE BANDGAP – TEMPERATURE ANALYSIS

The temperature dependence analysis of collector current is performed to ascertain the bandgap of C-containing base in HBT devices. The background theory behind this analysis can be found elsewhere8. The resulting Arrhenius plots are shown in Fig. 4. A consistent increase of activation energy (equal to bandgap) from 1.12 eV for SiGe HBT to 1.16 eV for SiGeC HBT with 1% C is evident. This constitutes an increase of bandgap of ~40 meV/at. % C (nominal). The same ratio is obtained from both forward and reverse collector current Arrhenius plots. A total bandgap change of 21-26 meV/% C has been reported9. Note that from the electrical assessment presented here, the nominal C content is taken into account and not the substitutional. 10 10

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SiGeC HBTs: IMPACT OF C

3.3. LEAKAGE CURRENT MECHANISMS IN SIGEC HBTS

Four main reverse leakage current mechanisms are apparent in HBT devices10: (i) Shockley-Read-Hall thermal generation (SRH), (ii) trapassisted-tunnelling (TAT), (iii) Poole-Frenkel aided generation (PF) and (iv) band-to-band tunnelling (BBT). The temperature dependences for reverse emitter/base junction of SiGeC HBT device accompanied by the associated reverse diode plot taken at room temperature and fitted according to theoretical curves for SRH, TAT and BBT are shown in Fig. 5. The reverse leakage current study of SiGe and SiGeC HBT devices shows the following: (i) better quality of the emitter/base junction, (ii) no evidence of Poole-Frenkel conduction, (iii) the combination of TAT and BBT mechanisms with low activation energies (up to 0.4V) seen for all 10

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Figure 5. a) Arrhenius plot & b) reverse E/B diode characteristic with fitted mechanisms for SiGeC HBT (1% C).

SiGeC HBTs: IMPACT OF C

177

wafers, and (iv) the associated carrier lifetime values used for fitting of emitter/base junction are found to be in nanosecond range (4 ns) for SiGe HBT, and in microsecond range (5 µs) for SiGeC HBTs, while for collector/base junction the lifetimes are in picosecond range (~30 ps). The TAT mechanism is frequently observed in epitaxial base SiGe HBTs11 and can be taken as an indication that the junction is of reasonable quality. 4. Conclusion A study has been conducted into the impact of carbon on SiGeC HBT device performance. The SiGeC HBTs with 11±2% Ge and 0.45-1.6% C have been fabricated using a LOCOS process and molecular beam epitaxy for defining the active layers. The best SiGeC HBTs operation is found to be for low carbon contents (<1%). ACKNOWLEDGEMENTS

The authors would like to thank EPSRC (UK) for financial support.

References 1.

2.

3.

4.

5.

6.

7.

P. Chevalier, B. Barbalat, L. Rubaldo, B. Vandelle, D. Dutartre, P. Bouillon et al., 300 GHz fmax self-aligned SiGeC HBT optimized towards CMOS compatibility, in: IEEE Proc. BCTM (2005), pp. 120-123. G. Avenier, P. Chevalier, B. Vandelle, D. Lenoble, F. Saguin, S. Frégonèse et al., Investigation of fully- and partially-depleted self-aligned SiGeC HBTs on thin film SOI, in: Proc. ESSDERC (2005), pp. 133-136. H. Rucker, B. Heinemann, R. Barth, D. Bolze, J. Drews, O. Fursenko et al., Integration of high-performance SiGe:C HBTs with thin-film SOI CMOS, IEEE Proc. IEDM Tech. Dig. (2004), pp. 239-242. I.M. Anteney, G. Lippert, P. Ashburn, H.J. Osten, B. Heinemann, G.J. Parker, D. Knoll, Characterization of the effectiveness of Carbon incorporation in SiGe for the elimination of parasitic energy barriers in SiGe HBT’s, IEEE ED Lett. 20(3), 116-118 (1999). S.K. Samanta, G.K. Dalapati, S. Chatterjee, C.K. Maiti, Minority carrier lifetime and diffusion length in Si1-x-yGexCy and Si1-yCy heterolayers, Appl. Surf. Sci. 224(1-4), 283287 (2004). I.Z. Mitrovic, O. Buiu, S. Hall, J. Zhang, Y. Wang, P. L. F. Hemment et al., Electrical and materials characterization of GSMBE grown Si1-x-yGexCy layers for heterojunction bipolar transistor applications, Semicond. Sci. Technol. 20, 95-102 (2005). R.W. Price, E.S. Tok, N.J. Woods, J. Zhang, Growth dynamics of Si 1–yCy and Si1–x– y GexCy on Si(001) surface from disilane, germane, and methylsilane, Appl. Phys. Lett. 81, 3780-3782 (2002).

178 8.

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A.S. Grove, Physics and technology of semiconductor devices (John Wiley & Sons, 1967). 9. C.L. Chang, A.St. Amour, J.C. Sturm, Effect of carbon on the valence band offset of Si1-x-yGexCy/Si heterojunctions, in: IEEE Proc. IEDM (1996), 257-60. 10. J.F.W. Schiz, A.C. Lamb, F. Cristiano, J. Bonar, P. Ashburn, S. Hall, P.L.F. Hemment, Leakage current mechanisms in SiGe HBTs fabricated using selective and nonselective epitaxy, IEEE Trans ED 48(11), 2492-9 (2001). 11. G.A.M. Hurkx, H.C. De Graaff, W.J. Kloosterman, M.P.G. Knuvers, A novel compact model description of reverse-biased diode characteristics including tunnelling, Proc. ESSDERC (1990), pp. 49-52.

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Reliability and Characterization of Nanoscaled SOI Devices

NOISE RESEARCH OF NANOSCALED SOI DEVICES N. LUKYANCHIKOVA V. Lashkaryov Institute of Semiconductor Physics, Prospect Nauki 45, 03028 Kyiv, Ukraine Abstract. The changes in the low-frequency noise of SOI MOSFETs accompanying their nanoscaling are considered. The behaviour of the 1/f noise in the course of downscaling as well as the influence of the additional noise sources appearing in the nanoscaled devices on their noise characteristics are explained. It is shown that the drastic changes in the noise performance of the devices can take place as a result of their nanocsaling.

Keywords: low-frequency noise; 1/f noise; LKE Lorentzian; BGI Lorentzian; EVB tunneling current; surface quantization; SOI MOSFET; nanoscaling

1. Introduction The intense interest in the behaviour of the low-frequency noise in nanoscaled semiconductor devices is driven by a number of reasons. First of all, such a noise determines the device sensitivity and affects the phase fluctuations of high-frequency oscillators and mixers. Therefore, it is important to understand and hence control the noise characteristics in the course of the device scaling. On the other hand, noise measurements have shown themselves as the basis of very effective metrology for controlling the technological processes and device reliability. Moreover, a correct interpretation of the noise results helps to elucidate the physical mechanisms responsible for the behaviour of the non-noise device characteristics including their changes caused by the device nanoscaling. The paper considers the influence of the device nanoscaling on the lowfrequency noise in SOI MOSFETs. 2. The 1/f noise in MOSFETs and nanoscaling The 1/f noise is the most typical low-frequency noise for semiconductor devices. In the case of MOSFETs the origin of this noise is the tunneling electron exchange between the channel and the traps located in the gate 181 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 181-198. © 2007 Springer.

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oxide at different distances from the Si/SiO2 interface1-4. The 1/f noise is also referred to as the McWhorter noise. The shot fluctuations of trapping and detrapping events give rise to fluctuations in the number of free charge carriers in the channel and of the concentration of charge captured in the oxide traps. The latter modulate the carrier mobility due to Coulomb scattering. As a result, the drain current noise arises due to the correlated number and mobility fluctuations in the channel. The drain current noise spectral density corresponding to the exchange with traps located at a given distance x from the Si/SiO2 interface, SIx( f ), is described by a Lorentzian distribution2 S Ix = S Ix (0) /[1 + ( 2πfτ x ) 2 ]

(1a)

τ x = τ 0 exp( x / λ )

(1b)

where SIx(0) and τx are the Lorentzian amplitude and time constant, respectively, τ0=10-10 s, λ=0.1 nm is the tunneling parameter and SIx(0)~τx. Since the Lorentzians characterized by different SIx(0) and τx corresponding to different x contribute into the spectral density of the drain current noise, SI (f), the value of SI (f) is the result of the integration of all such contributions. It has been found that in the case where the traps and their energy levels are distributed uniformly over the distance x and the energy E, the noise spectrum is characterized by the 1/f portion that has to be observed in the wide frequency range for which the lowest frequency, fmin, is determined as f min = [2πτ 0 exp( x max / λ )]

−1

(2)

where xmax≤ tox is the maximum distance of traps from the Si/SiO2 interface, tox is the gate oxide thickness. At the same time the value of SI has to become independent of f at f
2 S I q 2 N ot kT λ ⎡⎣1 ± α SC µ CoxV * / q ⎤⎦ , = 2 2 gm fZLCox

(3)

where SVG is the equivalent gate voltage noise spectral density, gm is the transconductance, q is the electron charge, Not is the density of the noisy oxide traps per cm3 per eV, k is the Boltzmann constant, T is the absolute temperature, Z and L are the channel width and length, respectively, Cox=(εox/tox), εox is the oxide dielectric constant, αSC=(α0-α1lnNS) is the scattering parameter, α0=10-13 V⋅s and α1=3.2⋅10-15 V⋅s4, NS is the free charge density in the channel, V*=(VGF-Vth) is the overdrive gate voltage, VGF and Vth are the front gate and threshold voltages, respectively. The

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183

value of SVG is used for determining the value of Not and for comparing the levels of the 1/f noise in different devices. The first term in the square brackets of Eq. (3) corresponds to the contribution of the NS-fluctuations (the so-called number fluctuations) whilst the second one is connected with the correlated µ-fluctuations where signs “+” and “–” correspond to traps of acceptor and donor types respectively. The decrease of αSC with increasing NS takes place due to the screening of the charge in the oxide traps by the free carriers in the channel5. It should be noted that the buried Si/SiO2 interface in SOI MOSFETs is an additional source of the 1/f noise in such devices6. It follows from Eq. (3) that SVG≠SVG(VGF) for “pure” number fluctuations in the case where the noisy traps are distributed uniformly. The observation of the dependence of SVG on VGF in this case can be the result of the contribution of the correlated mobility fluctuations. However, the non-uniform distribution of the trap levels over energy can be responsible for the dependence of SVG on VGF as well. Note also that the model predicts the (1/f )γ noise spectrum where γ differs from unity if the oxide traps are distributed non-uniformly over the distance x from the interface2. Consider which changes have to occur in SVG due to device downscaling that consists not only in decreasing L and Z but also in a commensurate decrease of tox and increase of the doping level Nd of the Si film. It follows from Eq. (3) that SVG increases with decreasing channel length and width as [1/(LZ)]. However, such behaviour has to be observed only under conditions where the full number of the noisy oxide traps in a device is sufficiently high7. As to the behaviour of SVG with decreasing tox, one obtains from Eq. (3) that SVG decreases with decreasing tox, as SVG ∝ (tox ) m ,

(4)

where m=2 for the number fluctuations related 1/f noise and 1≥m≥0 in the case where the noise is determined by the correlated µ-fluctuations. The decrease of SVG with decreasing tox from 20 nm to 2 nm was observed experimentally for n- and p-channel bulk MOSFETs of Z×L=10×4 µm28. It has been found that m=2.2 and 2.7 for the nMOSFETs of Nd=5×1016 cm-3 and 5×1017 cm-3, respectively. The corresponding values of m for the pMOSFETs were 1.8 and 1.4. It has also been found that the value of m decreases with increasing V*. For the SOI MOSFETs, the reduction of SVG with decreasing tox from 10.5 nm to 5 nm has been also observed9. In addition, the McWhorter model predicts the following changes in the noise spectra for nanoscaled MOSFETs. 1. The decrease of the device area Z×L up to the values at which only one noisy trap is present in the gate oxide of a given device means that only one Lorentzian (see Eq. (1)) corresponding to that trap determines the

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drain current noise of that device. In other words, the 1/f noise observed for the same devices of larger areas has to decompose into separate Lorentzians for separate devices of sufficiently small areas7. In this case the noise is a two-level phenomenon where one level corresponds to the filled trap and another level corresponds to the empty trap. Such a noise is called the Radio-Telegraph-Signal (RTS) noise. Since the value of Z×L is small, this noise is characterized by a high intensity. Since the noisy traps are located at different x in different devices, the values of SIx(0) and τx in Eq. (1) are also different and, hence, the RTS noise is characterized by a high dispersion of its levels that can reach 7 orders of magnitude7. This can make the devices of a sufficiently small area unusable for a low-noise application. 2. The decrease of the gate oxide thickness decreases the maximum possible distance xmax of the noisy traps from the Si/SiO2 interface. As a result, the lowest frequency fmin at which the 1/f noise has to be observed (see Eq. (2)) increases with decreasing tox. It follows from Eq. (2) that while fmin≈1.6×10-6 Hz for tox≥3.5 nm=xmax, one obtains fmin≥100 Hz for tox=2.07 nm≥xmax and fmin≥455 Hz for tox=1.5 nm≥xmax. This means that for the devices of tox≤2.07 nm, the low-frequency plateau has to be observed in the McWhorter noise spectra at f<100 Hz that is followed by the 1/f portion at f ≥100 Hz and the turnover frequency for that plateau shifts to 455 Hz in the case of tox=1.5 nm. It is clear that a significant decrease of the low-frequency noise would take place due to this effect. However, it has not been observed up to now. Even in MOSFETs of tox=1.5 nm the McWhorter 1/f noise manifests itself up to f=1 Hz. The possible reason for this could be the quantum-mechanical shift of the charge centroid (see below) that increases the maximum distance of the oxide traps from the channel. Another reason could be the contribution of the 1/f noise due to the µ-fluctuations considered by Hooge10. 3. Effects of surface quantization It is well known that the increase of the Si film dopant concentration necessary for correct downscaling of MOSFETs gives rise to high surface transverse electric fields FS and steep potential wells near the Si/SiO2 interface. As a result, the inversion layer quantization that takes place at FS≥105 V/⋅cm11-13 can influence the behaviour of SVG. The following quantum effects are of importance in this respect:

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185

1. the inversion layer charge centroid is a finite distance ZC away from the Si/SiO2 interface resulting in a decrease of the effective value of Cox12: Cox ,eff = ε ox /(tox + Z C / 3) < ε ox / tox = Cox ,

(5)

where the value of ZC increases with decreasing FS and can be higher than 2 nm at sufficiently low VGF13; 2. the bottom of the conduction band increases by a value of ∆E0 that rises with increasing FS and can be higher that 100 mV at sufficiently high FS11,13. The decrease of Cox,eff increases the value of SVG and overestimated values of Not can be obtained by using Eq. (3)14. It should also be noted that the decrease of ZC with increasing FS results in the decrease of the exchange time between the channel and the oxide traps located at a given distance from the Si/SiO2 interface with increasing gate voltage. This means that the contribution of those traps to the noise spectrum is shifted to higher frequencies. In the case where the traps are not distributed uniformly over the oxide depth, this shift can be seen as a change in the shape of the noise spectra with increasing VGF, namely, the exponent γ in (1/f )γ can change. A similar effect can take place due to the dependence of ∆E0 on FS in the case where Not is distributed non-uniformly over the trap energy levels. 4. Traps near the gate/SiO2 interface It should be noted that the traps located near the gate/SiO2 interface can serve as an additional source of McWhorter noise in ultra-thin gate oxide MOSFETs. The corresponding additional noise has been found for SOI and bulk MOSFETs with a 2.5 nm nitrided gate oxide where it manifests itself as the (1/f )1.7 component of the noise spectra observed at 0.7 Hz≤f≤50 Hz (Fig. 1)15,16. It has been shown that this noise decreases with increasing tox, behaves like the McWhorter noise for increasing VGF and is explained in the framework of the model supposing that the oxide traps of a high concentration Ntg are distributed near the gate/SiO2 interface over a distance Xg from that interface. The (1/f )1.7 noise is due to the electron exchange between the channel and the traps located in a thin layer around Xg. The exponent “1.7” corresponds to a relatively stepless decrease of Ntg near Xg. with increasing distance from the gate/SiO2 interface. By applying the model to the experimental results, the following values of Xg and Ntg have been found: Xg<1.36 nm and Ntg>2×1020 cm-3eV-1.

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The increase of SVG with decreasing tox due to the contribution of the high concentration of traps near the gate/SiO2 interface has been observed also for the pMOSFETs with the ultra-thin nitrided gate oxide where the additional nitrogen related traps were located near the gate interface17. Therefore, the quality of the gate/SiO2interface becomes of a special importance when considering the low-frequency noise in nanoscaled MOSFETs. This conclusion is supported by the influence of the gate material on the level of the low-frequency noise18. Note that the use of high-k dielectrics can mitigate many problems connected with MOSFET nanoscaling19. However, as a rule, such dielectrics are characterized by a very high concentration of noisy traps20. 5. Gate leakage current effects The gate tunneling currents that become dominant when tox is decreased to the direct tunneling limit, can contribute considerably to the low-frequency noise of nanoscaled MOSFETs21-23. The tunneling of electrons from the n-channel through the gate oxide to the conduction band (c-band) of a polySi gate in nMOSFETs is responsible for the so-called Electron Conduction Band (ECB) tunneling current IECB that makes the main contribution into the gate leakage current IG: IG≈IECB. This current decreases the drain current I in a linear mode of operation since IG and I are flowing in opposite directions. Moreover, the 1/f noise accompanying the ECB gate current can

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187

significantly increase the level of the low-frequency drain current noise. However, it should be noted that those effects decrease with decreasing channel length. It is important that while in some cases the gate current effects become negligible only for L<0.35 µm, for the devices of tox=1.5 nm21, it has been found that their contribution depends significantly on the technology used for the gate oxide processing and can be negligible even for L=10 µm for the devices of tox=1.2 nm22,23. 6. The EVB tunneling effects: 1/f noise and LKE Lorentzian noise Consider now the noise effects due to the other component of the tunneling gate current called the Electron Valence Band (EVB) tunneling current IEVB that flows due to electron tunneling from the valence band (v-band) of the Si film to the c-band of the poly-Si gate in nMOSFETs or from the v-band of the poly-Si gate to the c-band of the Si film in pMOSFETs24. It should be noted that the direct EVB tunneling between the Si/SiO2- and poly-Si/SiO2interfaces can occur only when the energy positions of the top of the v-band at the Si/SiO2- (or poly-Si/SiO2-) interface and of the bottom of the c-band at the poly-Si/SiO2- (or Si/SiO2-) interface coincide. The following condition has to be fulfilled for the appearance of such current24:

| V * |≥| ( E g / q) |≈ 1V

(6)

where Eg is the energy of the silicon forbidden band. In spite of the fact that IEVB<
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It is necessary to note that while the increase of 1/f noise due to EVB tunneling can occur in bulk and SOI ultra-thin oxide devices, the appearance of the Lorentzian components in the noise spectra takes place only for SOI MOSFETs, being one of the floating-body effects. The majority carriers appearing at the Si/SiO2 interface of SOI devices drift through the depletion layer to the body of the Si film where they are accumulated increasing the absolute value of the body-source potential |VBS|. Since this potential biases the source junction in the forward direction, the forward current IJ of the source junction increases until IJ=IEVB which corresponds to the steady state. Therefore, two additional currents, IJ and IEVB, flow in a SOI MOSFET under the condition of EVB tunneling and the shot fluctuations of those currents are the sources of an additional noise in this situation. The corresponding shot current noise generators being in parallel with the body-source impedance give rise to fluctuations of the body-source potential. These fluctuations are characterized by the Lorentzian spectra because of the capacitive character of the body-source impedance determined by the capacitances of the depletion layer and source and drain junctions. The Lorentzian noise of the body-source potential modulates the threshold voltage and, hence, the drain current giving rise to the so-called LKE Lorentzian component in the drain current noise spectra. The name “LKE” is connected with the fact that the increase of |VBS| due to the EVB tunneling current is responsible for the Linear Kink Effect (LKE) characterized by a kink observed in the dependence gm(VGF) measured in the linear regime31 and the correlation takes place between the appearance of that kink and the Lorentzian noise component. The following formulae describe the LKE Lorentzian amplitude and time constant29,30: S I (0) = [S I (0)]LKE = 4kTm ′τ LKE β 2 g m2 / C eq ,

(7)

τ = τ LKE = C eq ( m ′kT / qI EVB ) ,

(8)

where β=(∂Vth/∂VBS) is a body factor, Ceq=(CWZL+Cjs+Cjd) is the bodysource capacitance, CW is the capacitance of the depletion layer per cm2, Cjs and Cjd are the capacitances of source and drain junctions, m’=0.7 to 1. The LKE Lorentzians typical for the partially depleted (PD) SOI MOSFETs of tox=2.5 nm fabricated in a 0.1 µm SOI process are presented in Fig. 2a where we observe the appearance of the LKE Lorentzian in the drain current noise spectra at VGF≥1.1 V. Figure 2b shows that τLKE decreases with increasing V*. This decrease is predicted by Eq. (8) since IEVB increases with increasing V*. The decrease of τLKE is the reason for the decrease of the Lorentzian amplitude (see Eq. (7)) with increasing VGF in Fig. 2a. Good

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189

agreement between the experimental results and the theoretical values found with the help of Eq. (7) and Eq. (8) has been seen29,30. At the same time, it is seen from Fig. 2 that the LKE Lorentzians enter the noise spectra at VGF=1.1 V, corresponding to V*≈0.55 V<1 V but not to V*≈1 V. Therefore, the experiments have shown that the condition | VGF |≥ 1V ≈ ( E g / q )

(9)

is enough for observation of the LKE Lorentzians. This suggests that the appearance of free majority carriers at the Si/SiO2 interface (see Eq. (6)) is not a necessary condition for the generation of such -16

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0.5

0.6 0.7 0.8 0.9 1.0 1.1 1.2 * Gate Overdrive Voltage |VG |, V

Figure 2. Drain current noise spectra where the LKE Lorentzians are observed at VGF≥1.1 V measured for the PD SOI nMOSFET (a) and the dependences of the LKE Lorentzian time constants on the overdrive gate voltage for n-channel (1) and p-channel (2) devices (b); VGB=0 V, |VDS|=25 mV

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Lorentzians and for observation of the LKE itself. In addition, Fig. 2b shows that τp<<τn at a given V* where τp and τn are the LKE Lorentzian time constants for p-channel and n-channel MOSFETs, respectively. This also suggests that the LKE Lorentzians are not connected with the appearance of free majority carriers at the Si/SiO2 interface since in the latter case the values of τp and τn have to be equal at a given V*29. The following modification of the above model can be proposed to overcome these discrepancies. For simplicity, consider an n-channel MOSFET. The condition |VGF|≈1 V under which the LKE Lorentzians enter the noise spectra corresponds to the situation where the energy of the top of the v-band in the neutral Si film body coincides with the energy of the bottom of the c-band at the poly-Si/SiO2 interface. This means that the EVB tunneling takes place from the body of the Si film to the poly-Si/SiO2 interface. The most probable mechanism for such tunneling seems to be a multi-step tunneling through the depletion layer to the surface centers at the Si/SiO2 interface followed by the tunneling from those centers through the oxide (Fig. 3). It is clear that in this case the value of IEVB depends not only on V* but also on the depletion layer thickness W and the concentration of the traps NW in the depletion layer responsible for the multi-step tunneling through it, as well as on the density of the surface centers DSS. Then we can write,

τ LKE = τ LKE ( I EVB ) = τ LKE (V * ,W ,VW , DSS )

(10)

Therefore, τLKE depends not only on V* but also on the parameters of the Si film and Si/SiO2 interface. This could explain the difference in the values of τLKE observed for n-channel and p-channel MOSFETs.

V*=1 V

V*=0.75 V

V*=0.5 V

IEVB

IEVB

IEVB

Figure 3. Multi-step EVB tunneling at V*=0.5 and 0.75 V and direct EVB tunneling at V*=1 V in an n-channel MOSFET

NOISE RESEARCH OF NANOSCALED SOI DEVICES

191

Consider now the behaviour of the LKE Lorentzian noise with decreasing channel length. It follows from Eq. (8) that in the case where the density jEVB of the EVB tunneling current is distributed uniformly over the gate area the following relations are valid:

[S I (0)]LKE ∝ (Z / L3 )β 2 ,

τ LKE ∝ [CW + (C js + C jd ) / ZL] ,

(11) (12)

where (Cjs+Cjd)∝Z. Therefore, [SI(0)]LKE has to increase with decreasing L as (1/L)3 while τLKE has to be independent of the gate area for ZL>(Cjs+Cjd)/CW and can increase with decreasing L at sufficiently small L. For the nMOSFETs of Fig. 2 such an increase can take place for L<0.14µm32. Figure 4 shows the experimental dependences of τLKE and [SI(0)]LKE on the channel length. It is seen that Eqs. (11) and (12) describe the behaviour of τLKE and [SI(0)]LKE only for L>0.6 µm. To explain the short-channel effects observed for L<0.6 µm, one should consider the lateral nonuniformity of the EVB tunneling current density which is related to the local variations of the threshold voltage and the decrease of β due to charge sharing and junction leakage32. Note that it follows from Eq. (10) that the situation where jEVB=jEVB(L) at |V*|<1 V can take place due to a non-uniform distribution of DSS and the depletion layer parameters over the channel length. It should be noted that the contribution of the LKE Lorentzians into the noise spectra for the fully depleted (FD) MOSFETs is considerably lower than for the partially depleted ones. For example, the values of τLKE and [SI(0)]LKE measured under the same operation conditions for the nMOSFETs of the same L and Z fabricated on UNIBOND wafers appear to be three times lower for FD devices than for their PD counterparts29. Moreover, no LKE Lorentzians have been observed in the case of the FD pMOSFETs made on UNIBOND wafers29. The opposite behaviour is typical for the FD MOSFETs fabricated on ELTRAN wafers, namely: relatively weak Lorentzians have been observed for the p-channel devices and no Lorentzians have been detected for the n-channel ones28. At the same time, the application of back-gate voltage to induce an accumulation layer in the SOI body, promotes observation of the LKE Lorentzians in the ELTRAN nMOSFETs28 and increases considerably the level of those Lorentzians in the FD UNIBOND nMOSFETs29. As to the p-channel UNIBOND devices, all attempts to stimulate the LKE Lorentzians by increasing the accumulation back-gate voltage were ineffective29. The possible reason for this could be high leaky source and drain junctions in those devices.

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PD MOSFETs, HALO * -2 1 - nMOSFETs, V *= 0.8V 2 - pMOSFETs, V =-0.8V

τn,p, s

10

1: τn

2: τp

-3

10

(a) -1

10

L, µm

PD MOSFETs, HALO 1 - nMOSFETs 2 - pMOSFETs τ=10ms

1

-16

10

2

2

SI(0), A s

0

10

-2.6

L

-17

10

-2.4

L -18

10

(b) -1

10

L, µm

-3

L

0

10

Figure 4. Dependences of the LKE Lorentzian time constant (a) and amplitude (b) on the channel length for PD SOI nMOSFETs (1) and pMOSFETs (2) of 2.5 nm gate oxide; VGB=0 V, |VDS|=25 mV

7. Effects of an accumulated back-gate voltage in PD MOSFETs and BGI Lorentzians

It is interesting to note that while the accumulated back-gate voltage increases the LKE Lorentzians and the linear kink effect itself in FD MOSFETs28,29,31, the considerable reduction of both effects by the accumulation back-gate voltage takes place in the case of PD devices33. This is demonstrated in Fig. 5 and Fig. 6a. A comparison of Fig. 5a and 5b shows that the accumulated back gate voltage VGB=-49.5 V suppresses the LKE Lorentzians observed at VGF=1.1 – 1.3 V in the case of VGB=0 V. As a result, a significant decrease of the low-frequency noise takes place in the LKE regime.

NOISE RESEARCH OF NANOSCALED SOI DEVICES

193

-15

10

5

-16

2

SI, A s

10

PD nMOSFET VGB= 0 V

4

3

5

6 7

1

6

-17

10

2

VGF,V I,µA 1 0.9 124 2 1.0 161 3 1.1 200 -18 4 1.2 232 5 1.3 264 6 1.4 288 7 1.5 315

7

10

(a)

0

1

10

2

10

10

f, Hz -15

10

-16

1-5

10 2

SI, A s

PD nMOSFET VGB=-49.5 V 5

6 -17

10

-18

10

1 2 3 4 5 6 7

VGF,V 0.9 1.0 1.1 1.2 1.3 1.4 1.5

0

10

I,µA 125 158 189 219 249 275 300

7

6 7 1-5

(b) 1

10

2

10

f, Hz Figure 5. Drain current noise spectra for the PD SOI nMOSFET of 2.5 nm gate oxide measured at VGB=0 V (a) and VGB=-49.5 V (b); VGF=0.9 to 1.5 V, VDS=25 mV

It has been found that τLKE as well as the value of {[SI(0)]LKE/τLKE} are also decreased by the accumulation back-gate voltage33,34. Since [SI(0)]LKE∝τLKE, the decrease of {[SI(0)]LKE/τLKE} is responsible for the reduction of the LKE Lorentzian level not only at f<(2πτLKE)-1 but also at f>(2πτLKE)-1 observed at the accumulation back-gate voltage (Fig. 5).

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NOISE RESEARCH OF NANOSCALED SOI DEVICES 2

-16

10

(a)

3

0

-18

-2

2

SI, A s

(∆I/I), %

10

-4

-20

-22

-6 -8

0.8

1

1 2 3 4 -24 5

PD nMOSFETs VGB=-49.8 V 0.4

2

10

10

1.2

|-VGF|, V

1.6

10

(b)

4,5

VGF,V I,µA 0.30 0.17 0.40 1.65 0.50 8.78 0.69 54.0 0.90 124.0 0

10

PD nMOSFET VGB=-49.5 V 1

10

2

10

f, Hz

Figure 6. Dependence of the relative change of the drain current by the accumulated backgate voltage on the front gate voltage measured for different PD SOI nMOSFETs (a) and the BGI Lorentzians corresponding to VGB=-49.5 V and observed at VGF=0.3V (1), 0.4 V (2), 0.5 V (3), 0.69 V (4) and 0.9 V (5); VDS=25 mV

Figure 6a shows the influence of VGB on the value of ∆I/I where ∆I=IVacc-I and IVacc and I are the drain currents measured at the accumulation back-gate voltage and at VGB=0 V, respectively. As can be seen, the backgate bias does not change the drain current at VGF≤0.9 V where the EVB tunneling is absent. However, at VGF≥1 V (that is under conditions of EVB tunneling) the value of ∆I/I becomes negative and the curve |∆I/I| vs. VGF passes through a maximum. In other words, in this regime, the channel current also suffers from the accumulation back-gate voltage. The front-back-gate coupling effects described above may seem to be surprising because they occur in PD devices where the front and back interfaces are separated by a body region. The reason for these unexpected effects is related to the increase of the source/drain leakage currents in the presence of the accumulation back-gate voltage33, 34. Moreover, it has been found that the increase of those leakage currents increases the differential conductivity G0 of the source and drain junctions to such a value that the Nyquist fluctuations corresponding to this conductivity begin to serve as an intensive additional noise source modulating the body-source potential. As a result, the so-called Back-Gate-Induced (BGI) Lorentzians are observed at VGF<1 V in the noise spectra under conditions of the accumulation back interface (Fig. 6b) instead of the 1/f noise observed at VGB=0 V33,34. The following formulas describe the parameters of such Lorentzians:

NOISE RESEARCH OF NANOSCALED SOI DEVICES

195

S I (0) = [S I (0)]BGI = 4kTτ BGI β 2 g m2 / C eq ,

(13)

τ = τ BGI = C eq / G0 ,

(14)

where τBGI and, hence, [SI(0)]BGI decreases with increasing accumulation back-gate voltage due to the increase of G0 and τBGI is independent of VGF. It should be noted that the BGI Lorentzians can be observed also at VGF≥1 V at sufficiently high accumulation back-gate voltage (curves 2 to 4 in Fig. 5b) and transform into the LKE Lorentzians at sufficiently high IEVB as seen in curves 5 to 7 in Fig. 5b. The following formula describes the Lorentzian time constant at VGF≥1 V and |VGB|acc>0 V:

τ = C eq /(γI EVB + G0 ) ,

(15)

where γ >(m’kT/q)33. It is seen that Eq. (15) corresponds to the BGI Lorentzian for γIEVBG0 where τLKE=(Ceq/γ IEVB). The inequality γ >(m’kT/q) explains the decrease of τLKE by the accumulated back-gate voltage. There are two reasons for the increase of G0 considered above, namely: 1) an increase of the majority-carrier concentration in the body region near the buried interface that gives rise to tunneling leakage currents in the source and drain junctions; 2) an increase of the minority-carrier concentration in the highly doped source and drain regions near the buried interface that enhances the diffusion leakage currents flowing from the body to the source and drain regions. Note that the front-back-gate coupling effect considered can be regarded as a consequence of the increasing film doping required as devices are scaled, which in turn results in a higher body-source conductance under the back-gate accumulation condition. 8. Conclusions

The nanoscaling of SOI MOSFETs is accompanied by drastic changes in their noise performance. There are at least two reasons for those changes, namely: 1) the dependence of characteristics of the noise observed in the non-scaled devices (for example, of the McWhorter noise) on the scaled parameters (Z, L, tox); 2) the appearance of additional noise sources in the downscaled devices (the gate/SiO2 interface, gate leakage current, EVB tunneling current, tunneling currents in source (drain) junction). The inversion layer quantization typical for the nanoscaled MOSFETs has to be taken into account when interpreting those changes.

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ACKNOWLEDGEMENTS

The author would like to thank E. Simoen, C. Claeys, A. Mercha, N. Garbar and M. Petrichuk for the use of (co)authored results and for many stimulating discussions.

References 1. 2. 3. 4. 5. 6. 7. 8. 9.

10. 11. 12. 13.

14.

A. L. McWhorter, in: Semiconductor Surface Physics, edited by R. H. Kingston (Univ. Pennsylvania Press, Philadelphia, PA, 1957), pp. 207-228. R. Jayaraman and C. G. Sodini, A 1/f technique to extract the oxide trap density near the conduction band edge of silicon, IEEE Trans Electron Devices 36(9), 1773-1782 (1989). K. K. Hung, P. K. Ho, C. Hu, and Y. C. Chang, A unified model for the flicker noise in metal-oxide-semiconductor field effect transistors, IEEE Trans. Electron Devices 37(3), 654-665 (1990). A. Pacelli, S. Villa, A. L. Lacaita, L. M. Perron, Quantum effects on the extraction of MOS oxide traps by 1/f noise measurements, IEEE Trans. Electron Devices 45(5), 1029-1035 (1999). E. P. Vandamme and L. K. J. Vandamme, Critical discussion on unified 1/f noise models for MOSFETs, IEEE Trans. Electron Devices 47(11), 2146-2152 (2000). E. Simoen, A. Mercha, C. Claeys, N. Lukyanchikova, and N. Garbar, Critical discussion of the front-back gate coupling effect on the low-frequency noise in fully depleted SOI MOSFET, IEEE Trans. Electron Devices 51(6), 1008-1016 (2004). G. Ghibaudo, Impact of the device scaling on LF noise in CMOS technologies, in: Proc. of the 17th Int. Conf. “Noise and Fluctuations”, edited by J. Sikula (CNRL s.r.o., Prague, 2003), pp. 301-308. M. J. Knitel, P. H. Woerlee, A. J. Scholten, and A. T. A. Zegers-Van Duijnhoven, Impact of process scaling on 1/f noise in advanced CMOS technologies, in: Tech. Dig. IEDM (IEEE, 2000) pp. 463-466. Y-C. Tseng, W. M. Huang, M. Mendicino, D. J. Monk, P. J. Welch, and J. C. S. Wo, Comprehensive study of low-frequency noise characteristics in surface channel SOI CMOSFETs and device design optimization for RF ICs, IEEE Trans. Electron Devices 48, 1428-1437 (2001). F. N. Hooge, 1/f noise is no surface effect, Phys. Lett. 29A, 139-140 (1969). R. R. Siergiej, M. H. White, and N. S. Saks, Theory and measurement of quantization effects on Si-SiO2 interface trap modeling, Solid-St. Electron. 35 (6), 843-854 (1992). Y-Ch. King, H. Fujioka, S. Kamohara, K. Chen, and C. Hu, Dc electrical oxide thickness model for quantization of the inversion layer in MOSFETs, Semicond. Sci. Technol.13, 963-966 (1998). N. Lukyanchikova, M. V. Petrichuk, N. P. Garbar, E. Simoen, C. Claeys, Influence of the substrate voltage on the random telegraph signal parameters in submicron n-channel metal-oxide-semiconductor field-effect transistors under a constant inversion charge density, Appl. Phys. A70, 345-353 (2000). A. Mercha, E. Simoen, G. Richardson, and C. Claeys, Inversion layer quantization impact on the interpretation of 1/f noise in deep submicron CMOS transistors, IEEE Trans. Electron Devices 50, 2520-2527 (2003).

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15. N. Lukyanchikova, M. Petrichuk, N. Garbar, E. Simoen, A. Mercha, C. Claeys, H. van Meer, and K. DeMeyer, The 1/f1.7 noise in submicron SOI MOSFETs with 2.5 nm nitrided gate oxide, IEEE Trans. Electron Devices 49(12), 2367-2370 (2002). 16. N. Lukyanchikova, M. Petrichuk, N. Garbar, E. Simoen, A. Mercha, C. Claeys, H. van Meer, and K. DeMeyer, The origin of the 1/f1.7 noise in deep submicron partially depleted SOI transistors, in: Proc. ESSDERC 2002, edited by G. Baccarani, E. Gnani and M. Rudan (Univ. of Bologna, Bologna, 2002), pp. 75-78. 17. F. Martinez, C. Leyris, M. Valenza, A. Hoffmann, F. Boeuf, T. Skotnicki, M. Bidaud, D. Barge, B. Tavel, Effect of oxide thickness and nitridation process on PMOS gate and drain low frequency noise, in: Noise and Fluctuations:18th Int. Conf. On Noise and Fluctuations-ICNF 2005, edited by T. Gonzalez, J. Mateos, and D. Pardo (American Institute of Physics, 2005), pp. 323-326. 18. P. Srinivasan, E. Simoen, L. Pantisano, C. Claeys, and D. Misra, Impact of gate material on low-frequency noise of nMOSFETs with 1.5 nm SiON gate dielectric; testing the limits of the number fluctuation theory, in: Noise and Fluctuations:18th Int. Conf. On Noise and Fluctuations-ICNF 2005, edited by T. Gonzalez, J. Mateos, and D. Pardo (American Institute of Physics, 2005), pp. 231-234. 19. A. V-Y. Thean, A. Vandooren, S. Kalpat, Y. Du, I. To, J. Hughes, T. Stephens, Goolsby B, White T, Barr A, Mathew L, Huang M, Egeley S, Zavala M, Eades D, K. Sphabmixay, J. Schaeffer, D. Triyoso, M. Rossow, D. Roan, D. Pham, R. Rai, S. Murphy, B-Y. Nguyen, B. E. White, A. Duvallet, T. Dao, J. Mogab, Performance and reliability of sub-100nm TaSiN metal gate fully-depleted SOI devices with high-k (HfO2) gate dielectric, in: Proc Symp on VLSI Technol Dig Techn Papers, (The IEEE, New York, 2004) pp. 106-107. 20. M. J. Deen and O. Marinov, Noise in advanced electronic devices and circuits, in: Noise and Fluctuations:18th Int. Conf. On Noise and Fluctuations-ICNF 2005, edited by T. Gonzalez, J. Mateos, and D. Pardo (American Institute of Physics, 2005), pp. 3-12. 21. H. S. Momose, H. Kimijima, S. Ishizuka, Y. Miyahara, T. Ohguro, T. Yoshitomi, E. Morifuji, S. Nakamura, T. Morimoto, Y. Katsumata, and H. Iwai, A study of flicker noise in n- and p-MOSFETs with ultra-thin gate oxide in the direct-tunneling regime, Tech. Dig. IEDM (IEEE, 1998), pp. 923-926. 22. T. Contaret, K. Romanjek, G. Ghibaudo, J. A. Chroboczek, F. Boeuf, and T. Skotnicki, Drain and gate current LF noise in advanced CMOS devices with ultrathin gate oxides, in: Noise and Fluctuations:18th Int. Conf. On Noise and Fluctuations-ICNF 2005, edited by T. Gonzalez, J. Mateos, and D. Pardo (American Institute of Physics, 2005), pp. 315-318. 23. J. Jomaah and G. Ghibaudo, Low frequency noise in Si-based MOS devices, in: Noise and Fluctuations:18th Int. Conf. On Noise and Fluctuations-ICNF 2005, edited by T. Gonzalez, J. Mateos, and D. Pardo (American Institute of Physics, 2005), pp. 181-184. 24. W-C. Lee and C. Hu, Modeling CMOS tunneling current through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling, IEEE Trans. Electron Devices 48 (7), 1366-1373 (2001). 25. J. W. Wu, J. W.You, H. C. Ma, C. C. Cheng, C. S. Chang, G. W. Huang, and T. Wang Valence-Band Induced Low Frequency Noise in Ultra-Thin Oxide (15 Å ) Analog nMOSFETs, in: Int. Reliability Physics Symp. (2005), pp. 260-264. 26. J. W. Wu, J. W. You, H. C. Ma, C. C. Cheng, C. F. Hsu, C. S. Chang, G. W. Huang, and T. Wang, Excess low-frequency noise in ultrathin oxide n-MOSFETs arising from valence-band electron tunneling, IEEE Trans. Electron Devices 52 (9), 2061-2066 (2005). 27. F. Dieudonné, J. Jomaah, and F. Balestra, Gate-induced floating body effect excess noise in partially depleted SOI MOSFETs, IEEE Electron Device Lett 23, 737-739 (2002).

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28. A. Mercha, E. Simoen, H. van Meer, and C. Claeys, Low-frequency noise overshoot in ultrathin gate oxide silicon-on-insulator metal-oxide-semiconductor field-effect transistors, Appl. Phys. Lett. 82(11), 1790-1792 (2003). 29. N. B. Lukyanchikova, M. V. Petrichuk, N. Garbar, A. Mercha, E. Simoen, and C. Claeys, Electron valence-band tunneling-induced Lorentzian noise in deep submicron silicon-on-insulator metal-oxide-semiconductor field-effect transistors, J. Appl. Phys. 94(7), 4461-4469 (2003). 30. E. Simoen, A. Mercha, J. M. Rafi, C. Claeys, N. Lukyanchikova, and N. Garbar, Explaining the parameters of the electron valence-band tunneling related Lorentzian noise in fully depleted SOI MOSFETs, IEEE Electron Device Lett 24(12), 751-754 (2003). 31. J. Pretet, T. Matsumoto, T. Poiroux, S. Cristoloveanu, R. Gwoziecki, C. Raynaud, A. Roveda, and H. Brut, New mechanism of body charging in partially depleted SOIMOSFETs with ultra-thin gate oxides, in: Pro. ESSDERC 2002, edited by G. Baccarani, E. Gnani and M. Rudan (Univ. of Bologna, Bologna, 2002), pp. 515-518. 32. N. Lukyanchikova, N. Garbar, A. Smolanka, E. Simoen, A. Mercha, C. Claeys, Shortchannel effects in the Lorentzian noise induced by the EVB tunneling in partiallydepleted SOI MOSFETs, Solid-St. Electron. 48(5), 747-758 (2004). 33. N. Lukyanchikova, N. Garbar, A. Smolanka, M. Lokshin, E. Simoen, C. Claeys, Origin of the front-back-gate coupling in partially depleted and fully depleted silicon-oninsulator metal-oxide-semiconductor field-effect transistors with accumulated back gate, J. Appl. Phys. 98(11), 114506-1-11 (2005). 34. N. Lukyanchikova, N. Garbar, A. Smolanka, E. Simoen, C. Claeys, Excess Lorentzian noise in partially depleted SOI nMOSFETs induced by an accumulation back-gate bias, IEEE Electron Device Lett 25(6), 433-435 (2004).

ELECTRICAL CHARACTERIZATION AND SPECIAL PROPERTIES OF FINFET STRUCTURES

T. RUDENKO1*, V. KILCHYTSKA2, N. COLLAERT3, A. NAZAROV1, M. JURCZAK3, AND D. FLANDRE2 1 Institute of Semiconductor Physics, National Academy of Sciences of Ukraine Prospect Nauki 45, 03028 Kyiv, Ukraine; 1* 2 Laboratoire de Microélectronique, Université catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium 3 InterUniversity Microelectronics Center (IMEC), Kapeldreef 75, 3001 Leuven, Belgium *Presenting author. Tel: +380445257022. Fax: +380445256177. E-mail: [email protected].

Abstract. This paper presents a review into the experimental studies of the effective channel mobility and intrinsic gate leakage current in triple-gate FinFET structures with doped- and undoped-channels and different gate stacks. The characteristics of narrow-fin devices are studied as compared to those of quasi-planar (very-wide fin) devices, and as a function of the fin width. Special features in the behavior of narrow FinFETs are analyzed.

Keywords: Silicon-on-insulator (SOI); FinFET; multi-gate FETs; effective channel mobility; split CV-technique; gate tunneling current.

1. Introduction

In the last few years, FinFETs have been widely studied because of their tremendous potential for nano CMOS technologies1-4. However, most of these studies are devoted to technological aspects and short-channel performance, while physical properties of FinFETs still lack extensive experimental investigations. The purpose of this work is to gain knowledge

199 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 199-220. © 2007 Springer.

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ELECTRICAL CHARACTERIZATION OF FINFET STRUCTURES

and understanding of physical properties of FinFETs, using extensive measurements. The main attention is concentrated on two important characteristics of FinFETs, namely, the effective channel mobility and intrinsic gate leakage current. The effective channel mobility is the key parameter for any CMOS technology, nevertheless, only a few measurements of the effective mobility in FinFETs up to now have been reported4-7. The intrinsic gate leakage current (gate-to-channel leakage current) is an important parameter for CMOS devices because it determines power consumption and the limits for the gate oxide scaling. However, so far it has not received sufficient research attention in the case of FinFETs. In this work, the investigations of the effective mobility and gate leakage current are performed for both doped- and undoped-channel FinFETs and for different gate stacks. For better understanding of the FinFET behaviour, the above characteristics in narrow-fin devices are studied as compared to those in quasi-planar (very wide-fin) devices, and also as a function of the fin width, and mechanisms responsible for special features of narrow FinFETs are analyzed. 2. Device fabrication

All the devices studied were processed at IMEC. Triple-gate FinFETs were fabricated on SOI wafers, with top and lateral channels lying, respectively, in (100) and (110) crystallographic planes. In this study, devices from three different batches of the samples described below were used. 2.1. POLY-SI GATE DEVICES

Using e-beam lithography, 95nm tall fins with a 150nm pitch were patterned. After the mesa etch of the active area, the wafers received a 15 nm oxidation at 1150°C to provide sufficient corner rounding and also to reduce the fin width. After removing the 15 nm oxide, a 100 nm poly–Si was deposited on top of nitrided oxide with about 2-nm equivalent oxide thickness (EOT). The gate was patterned using 248 nm optical lithography with resist trimming. Next, high angle extension implantations, 70 nm RTCVD nitride spacers, As+P and B deep S/D implants and NiSi as a salicide were used. Tested devices were multiple-narrow-fin FETs consisting of 66 fins with the fin width WFin=35nm and height HFin=95 nm, and single-wide-fin FETs with WFin=0.2-10 µm. The channel doping in wide-fin devices was about 6x1018 cm-3.

ELECTRICAL CHARACTERIZATION OF FINFET STRUCTURES

201

2.2. TaN GATE DEVICES

Triple-gate transistors were fabricated using processes described earlier8,9. The active area fins were patterned using 193nm litho with resist and oxide hard mask trimming. Hydrogen anneal and sidewall oxidation were used for surface smoothening and corner rounding. Part of the wafers received a channel implant to provide channel doping of 1018 cm-3, while in another part, the channel was left undoped. Gate dielectrics of 1.6 nm EOT were fabricated by either oxidation in O2 followed by plasma nitridation or deposition of HfO2 on a chemical oxide surface by ALD. A 10nm layer of TaN was deposited via ALD. Gate stack formation was completed with a 100nm amorphous silicon deposition. After the gate etch, the extensions and HALOs were implanted with a high angle. Next, RTCVD spacers with a width of 55 nm were fabricated followed by HDD implants and NiSi silicidation. The measured devices were 30-fin FETs with HFin=50 nm and WFin=45 nm. The TEM cross-section and top view of the multiple-fin device after gate patterning are shown in Fig. 1. Comparative measurements were performed on very wide single-fin structures with WFin=10 µm. 2.3. TiN GATE DEVICES

Triple-gate FETs with Omega configuration were fabricated on Unibond SOI wafers featuring a 65 nm-thick Si film and 145-nm thick buried oxide. Fins were patterned using 193-nm optical lithography and dry etched. Details of fabrication processes are given in the previous work9. A nitrided oxide (SiON) with 1.8 nm EOT, or ALD HfO2 with 1.6 nm EOT were used

100 nm poly

fin

BOX

(a)

(b)

Figure 1. Cross section (a) and top view (b) of a multi-fin TaN gate device.

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ELECTRICAL CHARACTERIZATION OF FINFET STRUCTURES

as the gate dielectrics. MOCVD TiN was used as the gate electrode. The metal was capped with 100nm poly-Si. As and BF2 extensions were implanted with high angle and 45 nm PECVD nitride spacers were formed. No selective epitaxial growth was used to reduce the source/drain resistance. After spacer etch, HDD implantations were done, followed by a spike anneal and a standard NiSi process and Cu BEOL metallization. No fin doping was used in these devices. Tested devices were 5-fin FETs with HFin=60 nm and WFin varying from 25 nm to 3 µm. 3. Effective channel mobility 3.1. MOBILITY EXTRACTION PROCEDURE

The effective channel mobility µeff in a MOSFET is usually defined from drain current Id at a low drain voltage Vd as:

µ eff =

Id , (W L) ⋅ Vd ⋅ Qinv

(1)

where W and L are, respectively, channel width and length, Qinv is the inversion charge density per unit gate area. In this work, Qinv was experimentally determined using a split C-V technique10. In the split C-V technique, Qinv is determined experimentally from the gate-to-channel capacitance measurements, normalized to the gate area: Vg

Qinv =

∫

C gc (Vg )

Vacc

W ⋅L

dVg ,

(2)

where Cgc is the gate-to-channel capacitance per whole gate area, Vg is the gate voltage (measured relative to the source), and Vacc is the gate voltage in accumulation, i.e. where Qinv=0. Substituting Eq. (2) into Eq. (1) gives:

L2 ⋅ I d

µ eff (Vg ) =

Vg

Vd ⋅

∫C

gc

.

(3)

(V g )dV g

Vacc

From Eq. (3) it follows that with the split C-V measurements, µeff(Vg) can be determined without knowledge of either the dielectric thickness or channel width, which is particularly important in the case of FinFETs, in which neither are known reliably. However, plotting µeff as a function of the inversion carrier density Ninv=Qinv/(q·W·L) requires knowledge of the

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203

device channel width. As a consequence, the accuracy of the determination of the channel width in a FinFET can affect the slope of the obtained µeff(Ninv)-dependence. We define the channel width W in a FinFET as:

W=number of fins ×(2HFin + WFin).

(4)

Such a channel width definition will be justified in Section 4.5. When evaluating mobility in FinFETs, special care should be taken in accounting for series resistance. This is evident from the analysis of normalized on-current or normalized transconductance in the devices with different gate lengths. Figure 2 shows the normalized drain current (Idnorm=Id/(W/L)) versus gate voltage characteristics in the N-channel 5-fin FETs with WFin=55 nm and 25 nm and different gate lengths varying from 10 µm to 0.35 µm. It is seen that, even in rather long devices (with Lg=1-3 µm), the characteristics are noticeably degraded due to parasitic series resistance, and this degradation is more pronounced for narrower fins. Thus neglecting the series resistance dependence on WFin would result in underestimated mobility values and an artificial µeff(WFin)-dependence. Parasitic series resistance Rsd for a particular WFin can be evaluated from the Id(Vg)-measurements for different Lg. Figure 3 shows the electron mobility extracted for Lg=10 µm and 1 µm with and without Rsd-correction. It is seen that for Lg=10 µm, the obtained results are unaffected by the series resistance, while for Lg=1 µm, the value of electron mobility without the Rsd-correction turns out to be strongly underestimated. In this work therefore, to avoid series resistance effect, only very long-channel devices (Lg=10-20 µm) were used for mobility evaluation. However, in very longchannel devices, the drain current suffers more degradation due to gate leakage. In this work, the drain current was corrected for gate leakage, as proposed by P. Zeitzoff 11.

Figure 2. Degradation of the normalized on-current with decreasing gate length in narrow FinFETs with WFin: (a) 55 nm, and (b) 25 nm (a 5-fin structure, TiN/SiON, Vd=50 mV).

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Figure 3. Effect of the Rsd correction on the electron mobility evaluation in a 5-fin device with Lg=10 µm and 1 µm (WFin=25 nm, TiN/SiON).

Measurements used for mobility evaluation were performed with zero back-gate (substrate) bias, except as otherwise noted. This is justified by the fact that, due to strong electrostatic gate control, long-channel narrow FinFETs are virtually insensitive to substrate bias5,12. The effect of substrate bias on µeff is important only in wide-fin devices with undoped (low-doped) channel, operating in the fully-depleted (FD) regime. 3.2. MOBILITY RESULTS FOR DOPED-CHANNEL POLY-Si GATE DEVICES

As follows from the device geometry, conduction of our poly-Si gate narrow-fin devices with HFin=95 nm and WFin=35 nm, is dominated by the sidewall channels having a (110) surface orientation. Very wide-fin devices operate in partially-depletion (PD) mode due to the high channel doping (∼6x1018 cm-3) and large body thickness (fin height). Therefore their conduction is determined by the (100) top channel. It should be noted that mobility extraction in very wide-fin poly-Si gate devices is complicated by the presence of very high gate leakage and earlier side and corner inversion, revealed as a hump on the Id (Vg)-characteristics in the subthreshold region. To avoid these problems, we used two medium-wide devices with two different fin widths WFin1, and WFin2, and by subtracting the corresponding capacitances and currents, we eliminated edge and sidewalls contributions. In a given case, the top channel mobility µeff top is determined as follows6:

ELECTRICAL CHARACTERIZATION OF FINFET STRUCTURES

µ efftop =

L2 ⋅ ( I dWFin 2 − I dWFin1 ) Vg

Vd ⋅ ∫ (C gcW Vacc

Fin 2

.

205

(5)

− C gcW )dVg Fin 1

Figure 4 shows the effective electron and hole mobilities as a function of the gate voltage in poly-Si gate narrow-fin FETs obtained with Eq. (3) and the top channel mobilities extracted with Eq. (5) in wide-fin FETs. In Fig. 5, the effective mobilities are presented as a function of the inversion carrier density Ninv, obtained from Cgc-measurements with W defined by Eq. (4).

Figure 4. Effective mobility as a function of the gate voltage in poly-Si gate devices. Open symbols present mobility in narrow-fin devices (WFin=35 nm, HFin=95 nm); full symbols present top channel mobility obtained with two wide-fin devices using Eq. (5).

Figure 5. The effective hole (a) and electron (b) mobility in poly- Si gate devices plotted as a function of the inversion carrier density.

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As can be expected, hole mobility in narrow-fin devices determined mainly by the (110)-oriented fin sidewalls is significantly higher than the (100) top- channel hole mobility, due to anisotropy of the effective masses. For the same reason electron mobility in narrow-fin devices is expected to be degraded compared to the top-channel electron mobility. However, as is seen from Fig. 4 and Fig. 5(b), contrary to expectations, electron mobility in narrow-fin devices is also significantly higher than the (100) top channel electron mobility, at least, at low and moderate Ninv. 3.3. MOBILITY RESULTS FOR DOPED-CHANNEL TaN GATE DEVICES

Figure 6 shows the effective mobilities as a function of gate voltage in dopedchannel TaN gate narrow-fin devices (WFin=45 nm) and quasi-planar (QP) very wide-fin devices (WFin=10 µm) with two types of gate dielectrics. In Fig. 7 the effective mobilities are plotted as a function of Ninv. Comparison with the results for poly-Si gate (Figs. 4, 5) and TaN gate devices (Figs. 6, 7) shows that mobility values in TaN gate devices are much higher than those in poly-Si gate devices. This can be attributed to different device processing. In terms of the behavior of narrow-fin devices versus QP very wide-fin devices, both poly-Si gate and TaN gate devices reveal the same common features. These features are strong enhancement of hole mobility in narrow-fin devices (more than a factor of two) compared to their counterpart quasi-planar devices, over the whole measurement range of Ninv, and enhancement of electron mobility in narrow-fin devices at low and moderate Ninv.

Figure 6. Effective mobility as a function of gate voltage in doped-channel TaN gate narrowfin devices (WFin=45 nm) and quasi-planar (QP) very wide-fin devices (WFin=10 µm) with two types of the gate dielectrics (full symbols – HfO2; open symbols – SiON).

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207

Figure 7. Effective hole (a) and electron (b) mobility as a function of the inversion carrier density obtained in doped-channel TaN gate narrow-fin FETs (WFin=45 nm) and quasi-planar (QP) very wide-fin FETs (WFin=10 µm).

Figure 8. The improvement factor of the effective electron and hole mobilities in dopedchannel TaN gate narrow FinFETs (WFin=45 nm) as compared to quasi-planar (QP) very wide-fin FETs (WFin=10 µm).

Figure 8 shows the ratio between µeff in doped-channel TaN gate narrowfin devices and QP very wide-fin devices obtained from the results presented in Fig. 7. It can be seen that, in the case of doped channel, the µp enhancement in the FinFET is ∼2.5 in the whole measurement range of Ninv, while the µn enhancement reaches a factor of 3 at low Ninv and vanishes at high Ninv. We have explained the surprising enhancement of the electron mobility in narrow FinFETs by two factors13: 1) lower doping of fin

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ELECTRICAL CHARACTERIZATION OF FINFET STRUCTURES

sidewalls compared to the top channel, resulting in lower Coulomb scattering and a lower transverse electric field, and 2) fully-depleted (FD) double-gate (DG)-type operation of narrow FinFETs, also resulting in a lower transverse electric field and deeper inversion charge centroid. These two factors also improve hole mobility in doped-channel narrow FinFETs at low Ninv. 3.4. MOBILITY RESULTS FOR UNDOPED-CHANNEL DEVICES WITH TiN GATES

When comparing µeff in narrow-fin and quasi-planar SOI devices with undoped or low-doped channel, it should be taken into account that µeff in quasi-planar SOI devices depends on the back-gate conditions, while in narrow long-channel FinFETs, it is virtually insensitive to back-gate effects5, 12. Figure 9 shows the comparison between µn eff in a narrow-fin FET (with 25-nm-wide fins) and QP very wide-fin device (with 3-µm-wide fins) with a HfO2 gate dielectric. Shaded area in Fig. 9 shows the range of the µn variation in the QP device with Vsub in the single-gate (SG) regime. It can be seen that µn in a narrow FinFET is lower than the maximum µn in the QP device achieved in the SG-regime at Vsub =0. Figure 10 presents µp and µn extracted at Vsub=0 in undoped-channel FETs with various WFin. For undoped channel, the enhancement of µp and

Figure 9. Comparison between electron mobility, µn in a narrow-fin FET and quasi-planar (QP) wide-fin FET with undoped channel. Shaded area shows the range of the µn variation in the QP device with Vsub in the single-gate regime (HFin=60 nm, Lg=10 µm).

ELECTRICAL CHARACTERIZATION OF FINFET STRUCTURES

209

degradation of µn is observed in narrow FinFETs, as compared to QP widefin devices. This can be attributed to the surface orientation effect of the top and lateral channels. The improvement of µp and degradation of µn depend on both WFin and Ninv, which is demonstrated in Figure 11, which shows the ratio between µeff in FinFETs with various WFin and QP 3-µm-wide-fin FETs. As is seen from Fig. 11(a), at low Ninv, the µp improvement factor in undoped-channel FinFETs is much lower than in doped-channel FinFETs (Fig. 8). However, in undoped-channel FinFETs the µp improvement factor increases with Ninv, and at Ninv >1013 cm-2 it approaches that for doped channel. The ratio of µneff in a FinFET to that in a quasi-planar device exhibits a maximum at Ninv=2.6x1012 cm-2 equal to 0.85 (Fig. 11(b)). At high Ninv (>6x1012 cm-2), the fin width dependence of both µp and µn with

Figure 10. The effective hole (a) and electron (b) mobilities in undoped-channel devices with various WFin (TiN/HfO2, HFin=60 nm, Lg=10 µm).

Figure 11. The improvement factor of µp (a) and degradation factor of µn (b) in undopedchannel FinFETs with various fin widths as compared to the QP 3-µm-wide fin FET (TiN/HfO2, HFin=60 nm, Lg=10 µm).

210

ELECTRICAL CHARACTERIZATION OF FINFET STRUCTURES

WFin can be attributed to variation of the relative contributions of top and lateral conduction channels, having different mobilities due to different surface orientation. In this high Ninv region, the FinFET mobility is presumably controlled by the surface roughness scattering. However, at lower Ninv, the µn behavior in a FinFET is more complicated, in other words, the conduction of the device cannot be presented simply as a sum of the top and lateral conduction channels. It is assumed that in the Ninv range of the maximum µn in FinFETs (where µn slightly increases with decreasing WFin from 75 nm to 25 nm), µn is governed mainly by phonon scattering, while at lower Ninv, where µn strongly decreases with decreasing Ninv and WFin, the dominant scattering mechanism is Coulomb scattering, by analogy with DG devices14,15. A stronger degradation of µn with decreasing WFin at low Ninv, as compared to the predicted and measured degradation in ultra-thin body and DG devices for the same body thickness range 16-17, might be attributed to the fact that in tri-gate FinFETs, carriers can be simultaneously affected by four Si-SiO2 interfaces. 4. Gate-to-channel tunneling current

Before considering the experimental results, it is pertinent to note several factors which can affect the gate tunneling currents in FinFETs. Among these are possible different dielectric thicknesses on the fin top and sides due to different surface orientation, different dielectric quality (because fin etching can degrade the dielectric quality on fin sides), and quantum mechanical (QM) effects. It is known that, for effective suppression of the short-channel effects, multi-gate SOI devices should have sufficiently thin Si bodies and ultra-thin gate dielectrics, which makes QM effects more important in these devices. One of such QM effects, which has been recently predicted from QM simulations, is the reduction of gate tunneling current in ultra-thin body and DG SOI devices compared to planar bulk Si devices, due to reduced transverse electric field and carrier confinement18,19. The above gate current reduction was predicted to be enhanced for increased physical dielectric thickness and hence for higher-k dielectrics. This is a promising finding since it may relax the restrictions on the gate oxide thickness scaling or reduce power consumption. However, so far no experimental verification of this effect has been reported. In this work, we present experimental evidence for the lowering of gate tunneling currents in narrow FinFET structures, as compared to quasi-planar very wide-fin

ELECTRICAL CHARACTERIZATION OF FINFET STRUCTURES

211

structures. This lowering is observed for both N- and P-channel devices, and is found to be stronger for HfO2 than for SiON. The impact of the fin width and fin doping on the above phenomenon is presented next. 4.1. EXPERIMENTAL DETAILS

The gate current Ig was measured as a function of the gate voltage, with drain and source grounded, or with a very low drain voltage (Vd=5 mV). Most of the measurements were performed with the substrate grounded, except where mentioned otherwise. All the measurements were carried out at room temperature. The gate current density, Jg (A/cm2), was obtained by normalizing the measured gate current Ig to the gate area: Jg=Ig/(W×L), where L and W are respectively the effective channel length and width. The width, W was defined using Eq. 4. The effective channel length was determined using Cgcmeasurements for different gate lengths in strong inversion. Moreover, Jg has also been extracted from the difference between Ig for two devices with different gate lengths, Lg1 and Lg2 and its normalization to W×(Lg1-Lg2). Such a procedure allows elimination of the contribution of the gate overlap current and also uncertainty related to the definition of the effective channel length. 4.2. THE EFFECT OF SUBSTRATE BIAS ON THE GATE CURRENT IN WIDE-FIN DEVICES

When comparing gate-to-channel leakage current in wide- and narrow-fin devices, one should take into account that, in a FD wide-fin SOI structure, the electric field distribution depends on the back-gate bias, and thus the gate leakage current can be affected by the back-gate (substrate) bias. The effect of substrate bias on Ig in a very wide-fin (WFin=1 µm) undoped N-channel device is shown in Fig. 12. It can be seen that substrate bias has a pronounced effect on Ig only for Vg<0, and a slight effect for low positive Vg, while in strong inversion (at high positive Vg), Ig is unaffected by substrate bias. In narrow-fin structures, due to strong electrostatic control of the lateral gates, substrate bias has no effect on the electric field distribution in the device body 12 and thus on the gate-to-channel leakage current. This gives us grounds to analyze the leakage current in inversion region, using only measurements with Vsub=0.

212

ELECTRICAL CHARACTERIZATION OF FINFET STRUCTURES

Figure 12. Effect of substrate bias on the gate leakage current in a very wide-fin N-channel device with an undoped body (Lg=1 µm, 5 fins, tbox=145 nm, Vd=5 mV).

4.3. GATE LEAKAGE CURRENTS IN THE DEVICES WITH TaN/SiON AND TaN/HfO2 GATE STACKS

Figure 13 shows the comparison of gate current density Jg in undopedchannel narrow-fin devices with WFin=45 nm (solid lines) and QP very widefin (WFin=10 µm) devices (dashed lines) with TaN/SiON and TaN/HfO2 gate stacks. From the data in Fig. 13 it is seen that in strong inversion, Jg in narrow-fin devices is noticeably lower than in counterpart quasi-planar devices, and this lowering is stronger for HfO2, than for SiON. For undoped N-channel device, at Vg=1.8 V, the above Jg lowering is 2.6 for SiON, and 7.7 for HfO2, and for P-channel it is 2.5 for SiON, and 3.2 for HfO2. The behavior of Jg for doped-channel devices is presented in Fig. 14. In this case, at low Vg, both P- and N-channel narrow FinFETs show higher Jg than their counterpart QP wide-fin devices. This is attributed to a lower threshold voltage for narrow FinFETs due to their FD quasi-DG operation and lower doping of fin sidewalls compared to the top channel13, which implies a larger supply of carriers available for tunneling in the inversion layer for the same gate bias. However, at high gate biases, Jg in narrow FinFETs is significantly lower than in wide devices, and this lowering is much more pronounced for HfO2 than for SiON, similar to that in the devices with an undoped-channel.

ELECTRICAL CHARACTERIZATION OF FINFET STRUCTURES

213

Figure 13. Comparison between gate current density in narrow-fin and wide-fin devices with an undoped body and TaN/SiON and TaN/HfO2 gate stacks (Lg=10 µm).

Figure 14. Comparison between gate current density in narrow-fin and wide-fin devices with doped body and TaN/SiON and TaN/HfO2 gate stacks (Lg=10 µm).

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ELECTRICAL CHARACTERIZATION OF FINFET STRUCTURES

4.4. GATE CURRENT DENSITY IN UNDOPED-CHANNEL FINFETS WITH TIN/SION GATE STACK AND VARIOUS FIN WIDTHS

Figure 15 shows the experimental gate current density in undoped Nchannel narrow-fin (WFin=20 nm) and very wide-fin (WFin=1 µm) devices with TiN/SiON gate stack, obtained by the two procedures described in Section 4.1. The full symbols in Fig. 15 show Jg obtained with one long device, and open symbols show Jg obtained by the difference between two devices. One can see that in the inversion region, both procedures yield the same Jg, indicating that in given long devices, the gate overlap component is small compared to the gate-to-channel current. Hence from Fig. 15 it follows that the density of the gate leakage current between the gate and inversion layer in a narrow FinFET is substantially lower than that in a counterpart very wide-fin SOI device. Figure 16 presents Jg(Vg)-characteristics of undoped P- and N-channel devices with various fin widths. It is seen that in respect to the fin width, the behavior of Jg in P- and N-channel devices is similar. In particular, both P- and N-channel narrow-fin devices show reduced Jg compared to a widefin (WFin=1 µm) device, and the smaller WFin, the stronger the reduction. The insets in Fig. 16 show the reduction factors of Jg in FinFETs compared to a very wide-fin device with WFin=1 µm plotted as a function of the fin width. One can see that, for a given gate stack, the reduction factor increases more than twice when WFin decreases from 80 nm to 20 nm.

Figure 15. Gate current density vs. gate voltage in wide-fin (WFin=1 µm) and narrow-fin (WFin=20 nm) N-channel devices obtained with one 2 µm-long device (full symbols), and by difference between two long devices with Lg1=2 µm and Lg2=1 µm (open symbols).

ELECTRICAL CHARACTERIZATION OF FINFET STRUCTURES

215

Figure 16. Gate current densities vs. gate voltage in undoped P- and N-channel devices with TiN/SiON gate stack and various fin widths. The insets show the reduction factors of Jg in FinFETs compared to a very wide-fin (WFin=1 µm) device taken at |Vg|=2 V and plotted as a function of the fin width.

Figure 17. Normalized gate-to-channel capacitance vs. gate voltage obtained in undoped Nchannel devices with a TiN/SiON gate stack and different fin widths (f=100 kHz, Lg=1 µm). The channel width was defined using Eq. (4).

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ELECTRICAL CHARACTERIZATION OF FINFET STRUCTURES

4.5. GATE-TO-CHANNEL CAPACITANCE MEASUREMENTS IN UNDOPED-CHANNEL DEVICES WITH VARIOUS FIN WIDTHS

It would appear sensible to explain the observed gate current reduction in narrow-fin devices by a larger dielectric thickness on the fin sidewalls as compared to the top channel due to different surface orientation. In that case, the WFin-dependence of Jg presented in Fig. 16 could be explained by a variation of the relative contributions of the top and lateral channels. To verify this assumption, we performed measurements of the gate-to-channel capacitance in the devices with various fin widths. Figure 17 shows the normalized Cgc(Vg)-characteristics of undoped N-channel devices with a TiN/SiON gate stack and different fin widths varying from 1 µm down to 30 nm. The channel width in Fig. 17 was defined using Eq. 4. As is seen from the figure 17, the normalized Cgc in a very wide-fin device (with WFin=1 µm), in which the top channel is prevailing, is exactly the same as in narrow FinFETs, in which lateral channels dominate. This indicates that, in spite of the different surface orientations, the top and lateral channels have the same gate dielectric thickness, which is in agreement with results of the TEM analysis. This also is consistent with recent studies showing that, in the ultra-thin oxide range (<2 nm), the oxidation rate is almost the same for different crystallographic orientations20. Moreover, the data presented in Fig. 17 support the validity of the channel width definition being used, at least for our WFin range. 4.6. DISCUSSION OF FINFET GATE LEAKAGE FEATURES

As follows from the previous section, the observed Jg reduction in FinFETs cannot be explained by the different dielectric thickness on the fin top and sides. Another probable reason may be related to the electric field distribution and carrier confinement in the channel region. In general, our experimental data are in a qualitative agreement with recently published QM simulations, predicting the reduced gate tunneling currents in ultra-thin body SG and DG SOI devices compared to planar bulk-Si devices due to a lower transverse electric field and broader inversion charge distribution in the channel region, which lowers the eigen-energies and thus tunneling probability18,19. The largest improvement is predicted for a symmetrical DG device structure. In such a structure, no electric field exists in the center of the Si body, which reduces the depth of the potential well, resulting in a lowering of the eigen-energies in the channel region and thus in a reduction of the gate tunneling current19. Similar reasoning can be applied for explanation of the reduced Jg in narrow FinFETs featuring symmetric DGtype nature compared to very wide-fin devices, being much like asymmetric SG devices.

ELECTRICAL CHARACTERIZATION OF FINFET STRUCTURES

217

The observations of a much stronger effect for HfO2 than for SiON (Figs. 13, 14) are in complete agreement with QM simulation results19, which predict an enhancement of the above advantage of DG devices for the increased physical dielectric thickness, and thus for higher-k gate dielectrics. Other factors such as different crystallographic orientation of the top and lateral fin surfaces prevailing, respectively, in wide- and narrow-fin devices, and possible floating body effects in wide-fin devices hardly can play an important role in the observed effect, since, as shown by simulations19 and experiments20, the surface crystallographic orientation has only a minor effect on gate tunneling currents. The floating body effect, which can arise in wide-fin devices at proper conditions (for example, in PD doped-channel devices, or accumulation at the back interface in FD devices), would result in a reduction of the effective field in the gate dielectric and hence of the gate current in wide-fin devices. Thus floating body effects, even though they were present, cannot explain the observed difference between narrow-fin and very wide-fin devices. As to the impact of the fin width on Jg, it apparently should be similar to the effect of the body thickness in a DG device, in which the variation of the body thickness affects gate tunneling currents through the variation of both the width and, in strong inversion, the depth of the potential well 18,19. However, QM simulations predict a nearly invariant gate tunneling current in DG devices with body thickness for our thickness range (≥20 nm) and a noticeable increase for thicknesses below 5 nm19. This differs from our observations of a lowering of the gate current density with decreasing WFin shown in Fig. 16. However, the above QM simulations have been performed for DG device structures, while our devices are triple-gate structures for which a DG-approximation is valid only when WFin<< HFin. The explanation for the observed increase of Jg with increasing WFin in our tri-gate FinFETs might be a gradual transition from the DG-like structure to the asymmetric SG-like structure. However, such explanation requires confirmation with QM simulations of the gate tunneling currents in tri-gate FinFET structures. 5. Conclusions

The behavior of the effective mobility and gate-to-channel leakage current in narrow FinFET structures was studied and compared to that of quasiplanar very wide-fin structures, and as a function of the fin width. It is found that doped-channel narrow FinFET structures with different gate stacks reveal the same special features of the mobility behavior. These features are strong enhancement of hole mobility (more than twice) in

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ELECTRICAL CHARACTERIZATION OF FINFET STRUCTURES

narrow FinFET devices compared to their counterpart quasi-planar very wide-fin devices, as expected due to a (110) orientation of fin sidewalls, and also unexpected enhancement of electron mobility, which we attribute to the lower doping of the fin sides compared to the fin top and FD DG-type operation of narrow FinFETs. We found that undoped-channel narrow FinFETs exhibit higher hole mobility and lower electron mobility, as compared to the maximum mobility achievable in counterpart quasi-planar SOI devices in the singlegate regime. This is attributed to different surface orientation of the fin top and sides. Hole mobility improvement and electron mobility degradation in undoped-channel FinFETs depends on both fin width and inversion carrier density. At high carrier densities, the impact of the fin width on the effective mobility in undoped-channel triple-gate FinFETs can be explained in terms of (100)-top and (110)-lateral conduction channels. However, at low carrier densities, the behaviour of the FinFET mobility is more complicated. At low densities, the effective electron mobility strongly decreases with decreasing fin width, presumably due to Coulomb scattering. The observed degradation is stronger than that in ultra-thin body SG and DG devices for the same body thickness range, which might be attributed to the fact that in tri-gate FinFETs, carriers can be simultaneously affected by four Si-SiO2 interfaces. Based on the comparative study of the gate-to-channel leakage current in narrow-fin devices and quasi-planar devices, it is found that in strong inversion, narrow FinFETs exhibit reduced gate current densities compared to their counterpart quasi-planar devices. This reduction was observed for both N- and P-channel devices, and was found to be dependent on the fin width, increasing more that twice with decreasing fin width from 80 nm to 20 nm. It is assumed that the observed gate current reduction in FinFETs is associated with the electric field and carrier distributions in the channel region. ACKNOWLEDGMENTS

This work has been partly funded by the European Commission under the frame of the Network of Excellence “SINANO” (Silicon-based Nanodevices, IST-506844). T. Rudenko thanks “SINANO” for the special (personal) exchange grant.

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219

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J. P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI (3-rd ed. Boston. MA: Kluwer, 2004). D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, FinFET – A self-aligned double-gate MOSFET scalable to 20 nm”, IEEE Trans. Electron Devices, vol. 47, 2320-2325 (2000). J.-T. Park, and J.-P. Colinge, Multi-gate SOI MOSFETs: Device design guidelines, IEEE Trans. Electron Devices, vol. 49, 2222-2229 (2002). B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, FinFET scaling to 10 nm gate length, in IEDM Tech. Dig., 251-254 (2002). F. Daugé, J. Pretet, S. Cristoloveanu, A. Vandooren, L. Mathew, J. Jomaah, and B.-Y. Nguyen, Coupling effects and channel separation in FinFETs, Solid-State Electronicss, vol. 48, 535-542 (2004). V. Kilchytska, T. Rudenko, N. Collaert, R. Rooyackers, M. Jurczak, J.-P. Raskin and D. Flandre, Mobility characterization in FinFETs using split C-V technique, Proceedings of the ULIS 2005 Conference, Bologna, Italy, April 7-8, 2005, 117-120. T. Rudenko, N. Collaert, S. De Gendt, V. Kilchytska, M. Jurczak, and D. Flandre, Effective mobility in FinFET structures with HfO2 and SiON gate dielectrics and TaN gate electrode, Microelectronic Engineering, vol. 80, 386-389 (2005). K. Henson, N. Collaert, M. Demand et al., NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics, VLSI-TSA-TECH, April 2005, pp. 136-137. N. Collaert et al., Tall triple-gate device with TiN/HfO2 gate stack, Symposium on VLSI Technology, 108-109 (2005). K. Romajek, F. Andrieu, T. Ernst, and G. Ghibaudo, Improved split C-V method for effective mobility extraction in sub-0.1-µm Si MOSFETs, IEEE Electron Device Letters, vol. 25, 583-585 (2004). P. Zeitzoff, C. Young, G. Brown, and Y. Kim, Correcting effective mobility measurements for the presence of significant gate leakage current, IEEE Electron Device Letters, vol. 24, 275-277 (2003). R. Ritzenthaler, S. Cristoloveanu, O. Faynot, C. Jahan, A. Kuriyama, L. Brevard, and S. Deleonibus, Lateral coupling and immunity to substrate effect in ΩFET devices, SolidState Electronics, vol. 50, 558-565 (2006). T. Rudenko, V. Kilchytska, N. Collaert, S. De Gendt, R. Rooyackers, M. Jurczak, and D. Flandre, Specific features of the capacitance and mobility behaviors in FinFET structures, Proceedings of ESSDERC 2005 Conference, Grenoble, France, 12-16 September 2005, 85-88 (2005). F. Gámiz, J. B. Roldán, J. A. López-Villanueva, P. Cartujo-Cassinello, J.E. Carceller, P. Cartujo, F. Jiménez-Molinos, Electron transport in silicon-on-insulator devices, SolidState Electronics, vol. 45, 613-620 (2001). F. Gámiz, and M. V. Fischetti, Monte Carlo simulation of double-gate silicon-oninsulator inversion layers: The role of volume inversion, J. Appl. Phys. 89(10), 54785487 (2001). D. Esseni, M. Mastrapasqua, G.K. Celler, F.H. Baumann, C. Fiegna, L. Selmi and E. Sangiorgi, Low field mobility of ultra-thin SOI n- and p-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs, in IEDM Tech. Dig., 671-674 (2001).

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17. K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata, and S. Takagi, Experimental study on carrier transport mechanism in ultrathin-body SOI n- and pMOSFETs with SOI thickness less than 5 nm, in IEDM Tech. Dig., 47-50 (2002). 18. L. Chang, K. J. Yang, Y.-C. Yeo, Y.-K. Choi, T.-J. King, and C. Hu, Reduction of direct-tunneling gate leakage current in double-gate and ultra-thin body MOSFETs, in IEDM Tech. Dig., 99-102 (2001). 19. L. Chang, K. J. Yang, Y.-C. Yeo, I. Polishchuk, T.-J. King, and C. Hu, Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs, IEEE Trans. Electron Devices, vol. 49, pp. 2288-2295 (2002). 20. H. S. Momose, T. Ohguro, S.-I. Nakamura, Y. Toyoshima, H. Ishiuchi, and H. Iwai, Ultra-thin gate oxide CMOS on (111) surface oriented Si substrate, IEEE Trans. Electron Devices, vol. 49, 1597-1605 (2002).

SUBSTRATE EFFECT ON THE OUTPUT CONDUCTANCE FREQUENCY RESPONSE OF SOI MOSFETS

VALERIA KILCHYTSKA*, DAVID LEVACQ, DIMITRI LEDERER, GUILLAUME PAILLONCY, JEAN-PIERRE RASKIN AND DENIS FLANDRE Microelectronics and Microwave Laboratories, Université catholique de Leuven, Place de Levant 3, 1348 Louvain-la-Neuve, Belgium *

To whom the correspondence should be addressed: [email protected]

Abstract. The paper analyzes the influence of the Si substrate on the AC characteristics of silicon-on-insulator (SOI) MOSFETs through 2D Atlas simulations and measurements. It is shown that the presence of the Si substrate underneath the buried oxide (BOX) results in two transitions in the frequency response of the output conductance, caused by the variation of the potential at substrate-BOX interface. A first-order small-signal model is proposed to support the obtained results. It is demonstrated that the appearance of “substrate-related” transitions, their position and amplitude depend strongly on the substrate doping, space-charge conditions at substrate-BOX interface, temperature and moreover become more pronounced with device downscaling.

Keywords: SOI MOSFETs, output conductance, frequency response, device simulation, device scaling

1. Introduction

As thin-film short-channel silicon-on-insulator (SOI) technology is becoming a major contender for low-power systems-on-chip including microwave functions1, a deeper understanding of the frequency behavior of SOI MOSFETs is needed. For example, the output conductance can be low (or

221 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 221-238. © 2007 Springer.

222

SUBSTRATE EFFECT ON THE AC OUTPUT CONDUCTANCE

even negative due to the self-heating (SH) effect) at low frequency and then rise with frequency, leading to unforeseen gain and phase variations. As a consequence, small-signal amplifier gain will be relatively high at low frequencies and fall as frequency increases. Most of the studies devoted to the SOI MOSFET specific small-signal characteristics have been focused on the impact of SH2-4 and floating-body (FB)4-5 effects, but very little attention has been paid to the influence of the Si substrate on these characteristics. More practical motivation for this work came from experimental results6, which demonstrated an unexpected increase of the output conductance of 0.25µm FD SOI MOSFET in the GHz range, which could not be related either to SH or FB effects. In this invited paper we discuss the question: “how does the presence of the Si substrate underneath the buried oxide (BOX) in SOI MOSFETs influence their output conductance frequency response?”, summarizing the results of original research performed in our laboratory during the last years6-7 which have recently extended to downscaled devices and the influence of temperature. 2. 2-D simulation results

To understand the physical origin of the experimentally observed highfrequency output conductance increase, 2D numerical device simulations of FD SOI MOSFETs have been run using Atlas software8. The simulated structure is schematically presented in Fig. 1. Contrary to most previous studies2-5 we took into account the underlying p-type Si substrate. Thickness was set at 20 µm and doping levels of 6.5·1014 cm-3 and of 2·1012 cm-3 for standard and low-doped substrates, respectively. Before simulating the AC characteristics, exhaustive DC simulations were performed to carefully select the correct physical models and adjust the model parameters. The conductances and capacitances were calculated by applying an AC signal in turn to each j-electrode and taking real and imaginary parts of the admittance matrix between i and j electrodes, i.e. Gij=Re(Yij), Cij=Im(Yij/ω)8. The AC simulations were performed in the saturation regime but avoiding kink effect. Figure 2 presents typical simulated output conductance vs. frequency curves. Three transitions are clearly distinguished. The transition with a characteristic frequency fc of ~ 105-106 Hz widely discussed in literature2-4

SUBSTRATE EFFECT ON THE AC OUTPUT CONDUCTANCE

L eff=0.16 - 0.91 µm gate LDD source LDD

N ++

N+

P

N a= 8·10 17cm -3

N+

drain

gate oxide d ox=5 nm

N ++

d film =30 nm, FD

Buried oxide

d BOX =400 nm

p-Si substrate

d SUB =20 µm

223

N a=6.5·10 14 cm -3 (standard) or 2·10 12 cm -3 (low-doped)

Figure 1. Schematic view of the simulated structure. H = 5.75 cm, W = 10.21 cm.

Conductance G

DS

(µS/µm)

was proven to be related to the SH and hence will not be discussed here. We focus our attention on the low frequency (LF) transition with fc ~ 10-102 Hz and high frequency (HF) transition with fc ~ 109 Hz transitions which we demonstrate to be caused by the feedback through the Si substrate. Simulations performed without taking SH into account (Fig. 2) indeed confirm that these two transitions have no relation to the self-heating. Moreover, simulations without a substrate region, i.e. setting a back contact directly below BOX (as in most CAD simulators), demonstrate that neither standard substrate, with SH standard substrate, no SH no substrate, with SH

38

2nd transition

36

SH transition st

1 transition

34

32

10 2

10 4

10 6

Frequency (Hz)

10 8

10 10

Figure 2. Simulated frequency dependence of GSD for FD SOI MOSFET with Leff = 0.16 µm, VD = VG = 1 V, with and without substrate or self-heating. H = 7.24 cm, W = 9.21 cm.

224

SUBSTRATE EFFECT ON THE AC OUTPUT CONDUCTANCE

transition at ~102 Hz nor transition at ~109 Hz appear, proving their relation to the Si substrate. The observed low-frequency increase of the output conductance in our FD simulations may look similar to what was previously observed in PD devices and attributed to floating body4-5. But for FD devices the floating-body effects should be eliminated and, moreover, the internal coupling between device accesses and body node is not expected to be sensitive to the presence of the Si substrate as we observed (Fig. 2). 3. Physical origin of the “substrate-related” transitions

To have a deeper understanding of the reasons why the presence of the Si substrate can modify the output conductance of SOI MOSFET, the analogy with a simple MOS capacitor can be useful. In fact, in SOI MOSFETs, under the Si film there is a structure very similar to that of MOS capacitor, whose capacitance is very sensitive to frequency as well as to silicon-oxide interface conditions and applied bias. Reduced Conductance, G DS(f)-G DS(10Hz) (µS/µm)

2.0

a

1.6 1.2 0.8 0.4

Capacitance C SUB-D (fF/µm)

0

Vg=Vd=1.5V, standard Vg=Vd=1V, standard Vg=Vd=1.5V, low-doped Vg=Vd=1V, low-doped

b

0.08

0.04

0

10 2

10 4

10 6

10 8

10 10

Frequency (Hz)

Figure 3. Simulated frequency dependence of the output conductances (a) and substratedrain capacitances (b) of FD SOI MOSFETs with standard- or low-doped substrate under different biases. SH was not taken into account. Leff = 0.16 µm. Other parameters as in Fig. 1. H = 11.11 cm, W = 9.5 cm.

SUBSTRATE EFFECT ON THE AC OUTPUT CONDUCTANCE

225

Figure 3 presents the simulated drain to substrate capacitances, CSUB-D, and output conductances for the cases of different substrate dopings and applied biases. It can be seen that similarly to the case of the MOS capacitor, the CSUB-D reveals two transitions as frequency increases: the first one, when minority carriers can no longer the AC signal and the second, when the same applies to majority carriers. It is worth emphasizing that the characteristic frequencies, as well as both bias and doping dependences of these transitions in substrate-to-drain capacitances, are exactly correlated with those in the output conductances (Fig. 3). This understanding allows us to propose a first-order small-signal model for the Si substrate and include it in the equivalent circuit of SOI MOSFETs as follows. 4. Substrate model and equivalent circuits

Figure 4a presents the first-order substrate model which has to be included into equivalent circuits to correctly describe the small-signal parameter variations with frequency caused by the feedback through the substrate. The substrate frequency response is introduced by means of two RC networks9. The first one is related to the minority carriers and is represented by the space-charge capacitance CSC and the resistance related to the generation recombination processes, RGR. Generally, RGR includes three components related to: generation in the space-charge region RSC, generation in a quasineutral region with further diffusion Rqnr and generation through the surface states.

a

g mv GS C inv

C sub R GR

R Si

b

G

BG

C SC

C Si

S

C GS

g mbv BGS

C GD

D

g ds C SBG

C GBG

C BGD

BG C sub Figure 4. (a) Small-signal model of Si substrate in inversion (in depletion, Cinv and RSC should be removed10, 11; in accumulation, Cinv, CSC and RGR should be substituted by the accumulation capacitance Cacc7), (b) small signal equivalent circuit of FD SOI MOSFET. Back-gate (BG) corresponds to the substrate-BOX interface. BOX capacitance is included in gate-back gate, source-back gate and drain-back gate capacitances (CGBG, CBGD, CSBG). H = 6.55 cm, W = 12.38 cm.

226

SUBSTRATE EFFECT ON THE AC OUTPUT CONDUCTANCE

Corresponding resistance and capacitance can be given as follows7, 9-11 neglecting the generation-recombination through the surface states:

C SC =

ε 0 ⋅ ε Si Xd

,

τ g ⋅ϕ s

RGR = RSC + R gnr =

q ⋅ ni ⋅ X d

+

N A ⋅ Ln q ⋅ µn ⋅ ni2

(1a)

where Xd = √(2ε0 εSiφs/qNA) is the depletion width, φs the surface potential, τg the generation lifetime, Ln the diffusion length, µn the electron mobility and other symbols have their usual meaning. The characteristic frequency of the LF transition fsub1 is given by7, 9:

f sub1 = (RGR ⋅ C SC )

−1

(1b)

It is worth pointing out that at room temperature, generation in a spacecharge region usually dominates in RGR and other terms can be neglected. The second RC network introduces the frequency response of majority carriers by pure dielectric capacitance of the Si substrate CSi and its resistance RSi7, 9:

C Si = ε 0 ⋅ ε Si / d Si

RSi = ρ Si ⋅ d Si / S

(2a)

yielding the characteristic frequency, fsub2 7, 9:

f sub 2 = (RSi ⋅ C Si )

−1

(2b)

At low frequencies, in inversion, the total substrate capacitance Csub tends to infinity as defined by the inversion capacitance, Cinv. With frequency increase higher than fsub1, minority carriers can no longer follow the AC signal and the total substrate capacitance decreases to the space charge capacitance, Csub → CSC. Then, when the frequency approaches the value defined by fsub2, the majority carriers also are no longer able to follow the AC signal, the Si substrate behaves as a dielectric and Csub reduces to the pure dielectric capacitance CSi. A full equivalent circuit of the FD SOI MOSFET taking into account the Si substrate6, 7 is shown in Fig. 4b. According to this circuit, the total output conductance, GDS, including the intrinsic part, gds, and substrate-related part, gDSsub, can be described to the first order by the following equations6, 7:

SUBSTRATE EFFECT ON THE AC OUTPUT CONDUCTANCE

227

v BGS v = (n − 1) ⋅ g m ⋅ BGS , v DS v DS

(3a)

GDS = g ds + g DSsub ,

with

v BGS ≅

C BGD

g DSsub = g mb ⋅

C BGD ⋅ v DS + C SBG + CGBG + C sub

(3b)

where gmb is the substrate transconductance, gm the gate transconductance,

νDS and νBGS are the drain-to-source and back gate-to-source voltage variations, respectively, n is the body factor. The variation of the total substrate capacitance with frequency according to Eq. (3b) results in the potential variation at the back gate, i.e. BOX-substrate interface. This in turn results in change of the total output conductance through the variation of its “substrate-related” part (Eq. (3a)). Matlab simulations of this complete equivalent circuit agree well with 2D Atlas simulations6. 5. Factors which influence the substrate related transitions 5.1. SPACE-CHARGE CONDITIONS AT THE SUBSTRATE-BOX INTERFACE

The total output conductance of the MOSFET is strongly dependent on the space-charge condition at substrate-BOX interface through the sensitivity of its substrate related part to the change of substrate capacitance for different conditions. Let us first consider two limit conditions at the interface: strong inversion and accumulation. We can expect that for accumulation at the substrate-BOX interface, there is only an HF transition related to the majority carriers; a LF transition related to the minority carriers does not appear since there are insufficient minority carriers present. In the case of strong inversion, both transitions appear with their maximum possible amplitudes defined by the substrate doping and thickness. It is worth mentioning that the total change in the output conductance with frequency should be about the same in both cases, since the total substrate capacitance decreases in both cases from the infinite value (defined by Cinv or Cacc) to the minimal pure dielectric value CSi. All these predictions are indeed confirmed by 2D Atlas simulations presented in Fig. 5.

228

SUBSTRATE EFFECT ON THE AC OUTPUT CONDUCTANCE

g DS sub , µS/µm

1.2

inv LF HF UHF

0.8

BOX-substrate interface in inversion

acc

LF

0.4

HF UHF

0 0 10

BOX-substrate interface in accumulation

102

10 4

106

10 8 10 10 Frequency, Hz

Figure 5. 2D Atlas simulations of the gDSsub (obtained as GDS(f) – GDS(1Hz)) of SOI MOSFET when substrate-BOX interface is under: inversion and accumulation. SHE is not included. Standard-doped Si substrate. VG = VD = 1 V. Leff = 0.16 µm. Insert schematically presents the analogy with MOS capacitor.

H = 5.98 cm, W = 10.48 cm.

Another difference can be expected to be observed between strong inversion and weak inversion conditions. Contrary to the strong inversion case, for which the peak amplitudes are maximized and bias insensitive, under weak inversion condition the first peak amplitude is rather sensitive to the applied bias. The reason lies in a strong dependence of low-frequency Csub on the applied bias (recalling the analogy with the MOS capacitor). In addition, we should take into account that the substrate related variation of the output conductance has not 1D, but 2D origin. We should keep in mind that application of drain bias will create different space charge conditions at the BOX-substrate interface along the channel from drain to source, as will be discussed in the next section. 5.2. SUBSTRATE DOPING

Figure 3 demonstrates the influence of substrate doping on the behavior of the substrate related transitions in the output conductance as well as the associated substrate-to-drain capacitances. The influence of substrate doping on the amplitude of the first transition is partially related to the different space-charge conditions at the substrate-BOX interface.

e-, h+ concentrations in the SUB, cm-3

SUBSTRATE EFFECT ON THE AC OUTPUT CONDUCTANCE LDD channel LDD

source

229

drain

10 16

10 12

N a standard doping N a low doping

10 8

Vg=Vd=1.5V Vg=Vd=1V Vg=Vd=0.75V

10 4 0

1

2

3

Distance along transistor, µm

Figure 6. Electrons (dashed lines) and holes (solid lines) concentrations in standard- (open symbols) and low-doped (filled symbols) Si substrates near substrate-BOX interface along MOSFET length at different applied biases. H = 7.24 cm, W = 11.43 cm.

This is confirmed by the simulation of electron and hole concentrations in the Si substrate near to the substrate-BOX interface (Fig. 6). It is seen that under the same bias conditions, the substrate-BOX interface is always inverted everywhere from drain to source for the case of the low-doped substrate, but is only slightly inverted near the drain in the case of a standard doped substrate, and moreover, the level of inversion is biassensitive. Such differences in the space charge conditions results are reflected in the observed substrate capacitance. In addition to this space-charge related influence of the substrate doping, we have pure doping influences on both amplitude and characteristic frequencies of substrate-related transitions. According to the proposed model, we can deduce (Eqs. 1) that with as doping is increased both amplitude and frequency of the first substrate-related transition decrease, since Xd decreases and hence both RSC and CSC increase. On the contrary, both amplitude and characteristic frequency of the second substrate-related transition increase with an increase in doping, according to Eqs. (2). Such expectations from the model are fully confirmed by the 2D Atlas simulations as shown in Fig. 3.

230

SUBSTRATE EFFECT ON THE AC OUTPUT CONDUCTANCE

5.3. TEMPERATURE

Figure 7 demonstrates the influence of temperature on the behavior of substrate-related transitions for the cases of standard- and low-doped substrates. In both cases, temperature increase results in an increase of characteristic frequencies. The behavior of transition amplitudes with temperature increase looks radically different at a first glance: increase for the case of standard-doped substrate and decrease for the case of the lowdoped one. However, this difference is again related to the space-charge conditions at the substrate-BOX interface. As already mentioned above, for the case of low-doped substrate, the substrate-BOX interface is always inverted from the drain to the source under such biases, and hence the situation is invariant with temperature increase. On the contrary, for the standard-doped substrate, the substrate-BOX interface being only slightly inverted near drain at room temperature becomes increasingly more inverted with temperature increase as seen in Fig. 8. The strong inversion region extends, and finally at high temperature, the strong inversion conditions are provided everywhere from source to drain, as in the case of the low doped substrate. The simulations, in which the substrate-BOX interface is intentionally put into a strong inversion condition for both standard- and low-doped substrates, confirm this explanation as depicted in Fig. 9. In this case, both standard- and low-doped substrates behave in a similar way. We now discuss in more detail the variation of characteristic frequencies and transition amplitudes with temperature increase.

g DS sub , µS/µm

0.8 0.6

0.4 0.2 0

100

1.6

a

VG=VD=1V no SH

1.2

300K 350K 400K 500K 600K

102

b

0.8 0.4

104

106

108

1010

0

100

Frequency, Hz

102

104

106

108

Figure 7. Temperature influence on the substrate-related part of the output conductance of SOI MOSFET with standard (a) and low (b) doped substrate. Leff = 0.16 µm. gDS sub obtained as in Fig. 5. SH effect was not taken into account. H = 5.02 cm, W = 11.75 cm.

e -, h + concentrations in the SUB, cm -3

SUBSTRATE EFFECT ON THE AC OUTPUT CONDUCTANCE LDD channel LDD

source

231

drain

V g=V d=1V

10 15

N

su b

=6.5x10

14

cm

-3

10 13 10 11 10 9 e- h+ 10 7 10 5

x

+

T=300K T=350K T=400K T=500K T=600K

0

1

2

3

Distance along transistor, µm Figure 8. Electron and hole concentrations in standard-doped Si substrate near substrateBOX interface along MOSFET at different temperatures. H = 7.4 cm, W = 10.8 cm.

g DS sun , µS/µm

0.8

1.6

a

0.6

T↑

1.2

0.4

0.8

0.2

0.4

0

100

b

102

104

106

108

0

T↑

102

Frequency, Hz

104

106

Figure 9. Temperature effect on the substrate-related output conductance of SOI MOSFET with standard (a) and low (b) doped substrate when substrate-BOX interface is inverted. SH effect was not taken into account. gDS sub obtained as in Fig. 5. Leff = 0.16 µm. VG = VD = 1 V. H = 4.82 cm, W = 11.43 cm.

5.3.1. 1st substrate-related transition In the case of a wide temperature range, when defining the characteristic frequency of the 1st transition, we should consider a complete equation for the RGR (Eq. (1)) taking into account the resistance related to the generationrecombination processes in the quasi-neutral region. After substituting (1a) in (1b) we can obtain:

f sub1 =

2 ⋅ ni N A ⋅τ g

(4a)

232

SUBSTRATE EFFECT ON THE AC OUTPUT CONDUCTANCE

f sub1

q ⋅ µ n ⋅ ni2 ⋅ X d = ε s ⋅ ε 0 ⋅ N A ⋅ Ln

(4b)

107

a

~ni2

~ni ~ni2

fsub1 1SUB , Hz

105 low-doped

~ni

103

∆ g DS sub 1 , µS/µm

for the cases when generation-recombination processes in a space charge region and in a quasi-neutral region dominate, respectively. These equations predict the strong temperature dependence of fsub1 reflecting the temperature dependence of the intrinsic carrier density ni, and hence proportionality to ni or ni2 depending on the dominating mechanism. The 2D Atlas simulations, presented in Fig. 10a, confirm these modeling predictions. Firstly, at lower temperatures fsub1 increases proportionally to ni, i.e. generation in the space charge region dominates, and then, at higher temperature it becomes proportional to ni2, i.e. generation in quasi-neutral region starts to dominate. In addition, for a lower doping level the term related to the quasi-neutral region becomes dominant at lower temperatures, because the fsub1 related to the space charge generation decreases more strongly with NA increase, that is, ~1/NA for the space-charge term and ~1/√NA for the quasi-neutral region term, according to Eqs. (4)). The amplitude of this 1st transition ∆gDSsub1 is related to the difference between the low-frequency Csub, which is infinite in the case of an inverted or accumulated substrate-BOX interface, and high-frequency Csub when minority carriers can not follow the signal; that is, space-charge capacitance CSC given by Eq. (1a). Two effects influence the evolution of ∆gDSsub1 with 1.6

b

low-doped

~Xd

1.2

0.8

standard-doped

~Xd and gm

0.4 standard-doped 10 300 330 360

----- ~ Xd variation with T ~ both Xd and gm variation with T

390

420

450

Temperature, K

0 300

340

380

420

Temperature, K

Figure 10. Temperature dependence of the transition frequency (a) and amplitude (b) of the 1st “substrate-related” transition. Leff = 0.16 µm, VG = VD = 1 V. H = 4.86 cm, W = 11.75 cm.

SUBSTRATE EFFECT ON THE AC OUTPUT CONDUCTANCE

233

temperature: 1) increase of the depletion capacitance with temperature increase (as Xd decreases) and 2) after a certain temperature, there are enough minority carriers to provide an inversion layer at any frequency and the first transition disappears. However, the 2D simulations of Fig. 10b demonstrate that the temperature dependence of ∆gDSsub1 is stronger than can be expected from the variation of depletion width with temperature alone. But the reason for this is not related to another dependence of capacitance variation with temperature, which corresponds to the Xd increase with temperature. Rather, the reason is that according to Eq. (3) the amplitude of substrate-related transitions in GDS is defined not only through Csub, but is also proportional to the temperature-dependent gate transconductance gm. Taking into account both effects: Xd increase and gm decrease with increasing temperature, a good correlation between model and simulations results is obtained as shown in Fig. 10b. Here we assumed that gm ~ T -α according to the usual mobility degradation with temperature14, with α = 1.35 in our case. 5.3.2. 2nd substrate-related transition To separate the 2nd transition from the 1st, the substrate-BOX interface was put in the accumulation condition, so that only the 2nd transition appears. Characteristic frequency of the 2nd transition. The only temperaturedependent parameter in fsub2 (Eqs. (2)) is the Si resistivity, which is inversely proportional to the carrier concentration, n, and carrier mobility, µn: ρ ~ n⋅µn. At room temperature, n is fixed by the doping level NA, but with temperature increase ni can become larger than NA and so defines the resistivity of the Si substrate making it strongly temperature dependent. Therefore, fsub2 which is practically constant at lower temperatures starts to increase at higher temperatures following the temperature dependence of ni. For low-doped substrates, ni becomes dominant over NA already at ~380 K and the curves start to shift to higher frequency, while for standard doped substrates we have to reach much higher temperatures (~500 K) to attain ni larger than NA. These expectations agree well with simulation results (Fig. 11a). The slight decrease of fsub2 at lower temperatures, where it is expected to be a constant is especially visible in the case of standard-doped substrate. This is explained by the increase of substrate resistivity with temperature15 due to mobility degradation.

SUBSTRATE EFFECT ON THE AC OUTPUT CONDUCTANCE

109 standard-doped

a

1.6

~ni

∆ g DS sub 2, µS/µm

234

fSUB2, Hz

108

1.4

107 106

b low-doped

low-doped

105 300

1.2

1

350

400

450

500

550

Temperature, K

300

Symbols - simulation Line ~µ(T), i.e. ~T-1.35 340

380

420

Temperature, K

Figure 11. Temperature dependence of the transition frequency (a) and amplitude (b) of the 2nd substrate-related transition. Leff = 0.16 µm, VG = VD = 1 V. H = 4.9 cm, W = 12.07 cm.

According to Eqs. (2), for the accumulation condition at the substrateBOX interface, no variation of the 2nd transition amplitude ∆gDSsub2 with temperature is expected due to the nature of Csub. However, similarly to the 1st transition, we can predict a decrease in ∆gDSsub2 with temperature due to the temperature dependence of gm in Eqs. (3). 2D simulations (Fig. 11b) indeed confirm such explanations demonstrating the good correspondence between the decrease of ∆gDSsub2 and inverse power low of temperature; that is ~T -α with α = 1.35, the same as was used to explain the decrease of ∆gDSsub1. 5.4. MOSFET DOWNSCALING

It should be emphasized that device downscaling results in a strongly enhanced frequency variation of the device output conductance due to the presence of the Si substrate. Such scaling of course implies the use of ultrathin body SOI devices with thin BOX for improving control of shortchannel effects and for attenuating the SH effect. 2D Atlas simulations performed without taking into account SH demonstrate the strong increase of the amplitudes of substrate-related transitions with both channel length scaling (Fig. 12a) and BOX thickness reduction (Fig. 12b), suggesting that these transitions will be more prevalent in the next device generations. 6. Experimental verification

Below we present experimental results, which confirm the simulation and modeling observations shown above. 1st (or low-frequency) “substrate related” transition. Figure 13 presents the variation of the output conductance versus frequency in a FD SOI MOSFET (in reality, a very wide-fin undoped FinFET which can be

SUBSTRATE EFFECT ON THE AC OUTPUT CONDUCTANCE

235

considered as quasi-planar FD SOI device) with 90nm gate length at different substrate and gate biases. It can be seen that in agreement with 2D Atlas simulations presented above, the LF transition disappears when the substrate-BOX interface is accumulated (Vsub > 1 V) and the amplitude of the 1st transition is maximal when the substrate-BOX interface is inverted (Vsub < 0 V) as seen in Fig. 13a. In addition, the amplitude of the transition is practically independent of the gate bias and hence on the drain current as seen in Fig. 13b, which proves that this transition is not related to the SH effect.

g DS sub , µS/µm

10

a

TBOX=150nm Tsi=60nm 8 V =0.7V; V =1.5V G D

L=0.17µm Tsi=60nm VG=VD=1.5V

L=0.17µm

6

b TBOX=150nm

4 L=1µm

2 0 100

102

104

106

TBOX=400nm 108

1010 100

102

Frequency, Hz

104

106

108

Figure 12. Influence of the channel length (a) and BOX thickness (b) on the frequency response of substrate-related conductance gDSsub (gDSsub is obtained as in Fig. 5) in FD SOI MOSFETs. SH effect was not included. Standard-doped p-Si substrate thickness was 20 µm. H = 4.99 cm, W = 11.75 cm.

Figure 13. Experimental substrate (a) and gate (b) bias dependences of the frequency response of the gDSsub in a wide (1 µm) undoped FinFET with L = 90 nm, Hfin = 60 nm, TBOX = 145 nm, Tgox = 1.6 nm. The gDSsub is obtained from the measured total output conductance reduced to its LF value, i.e. gDSsub = GDS(f) - GDS (1 Hz). H = 4.94 cm, W = 11.75 cm.

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Output Conductance (µS/µm)

38

FD SOI nM OSFET

V G =V D = 1.125 V I D = 8.3 mA

36 W=16x6.6µm L eff =0.16µm 34

V G =V D =1 V I D = 6.4 mA

32 30 28

V G = V D =0.875 V I D = 4.5 mA

26 24 22 0

0.5

1

1.5

2

2.5

3

3.5

4

Frequency (GH z) Figure 14. Total output conductance measurement vs frequency for FD SOI MOSFET with Leff=0.16 µm, W = 16x6.6 µm at different biases. H = 6.31 cm, W = 7.94 cm.

2nd (or high frequency) substrate-related transition. Figure 14 shows the variations of the output conductance at high frequencies measured at different drain currents. It is evident that the amplitude of this HF transition is independent on the drain current flow through the MOSFET, which confirms that this transition has no relation to the SH effect similarly to the LF one. Moreover, the characteristic frequency of the transition (~1GHz) corresponds well to the simulation predictions. 7. Conclusions

In this paper we demonstrated both by simulations and experiments that the electrical coupling through the Si substrate underneath the BOX in SOI MOSFETs results in two additional transitions in the output conductance vs frequency curve. The first of these transitions is caused by the inertia of minority carriers in the substrate; the second is due to the inertia of the majority carriers. This conduction variation can be considered as an additional short channel effect, degrading the device performance for digital as well as analog/RF applications in which it can cause gain lowering or increased low-frequency noise, stability or offset problems. We analyzed the dependence of both absolute value and characteristic frequency of these transitions on a number of factors, such as the substrate doping, substrateBOX interface space charge conditions, and temperature. We proposed a

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first-order analytical model to account for the influence of the substrate on the AC characteristics of FD SOI MOSFETs and demonstrated its validity over a wide temperature range. The strong increase of the amplitudes of substrate-related transitions with both channel length scaling and BOX thickness reduction suggests that these transitions will be increasingly prevalent in next generation devices. ACKNOWLEDGEMENTS

Authors thank the CEA-LETI (France) and IMEC (Belgium) for providing experimental devices. This work was partially funded by Walloon Government through the 4G-Radio project and by the European Commission through the Network of Excellence “SINANO” (Silicon-based Nanodevices, IST-506844) and “SPRING” (IST-1999-12342).

References 1.

D. Flandre, J.-P. Raskin, and D. Vanhoenacker, SOI CMOS Transistors for RF and Microwave Applications, Int. Journal of High Speed Electronics and Systems 11, 11591248 (2001). 2. B.M. Tenbroek, et al., Self-heating effects in SOI MOSFET’s and their measurement by small signal conductance techniques, IEEE Trans. Electron Devices 43 (12), 2240-2248 (1996). 3. W. Jin, W. Liu, S.K.H. Fung, P.C.H. Chan, and C. Hu, SOI thermal impedance extraction methodology and its significance for circuits simulation, IEEE Trans. Electron Devices 48( 4), 730-735 (2001). 4. B.M. Tenbroek, et al., in: Proceedings of the 23rd European Solid-State Device Research Conference, edited by J. Borel, P. Gentil, J.P. Noblanc, A. Nouailhat, M. Verdone (Editions Frontieres, Grenoble, 1993), pp. 189-192. 5. R. Howes, and W. Redman-White, A small-signal model for the frequency-dependent drain admittance in floating-substrate MOSFET’s, IEEE Journal of Solid-State Circuits 27(8), 1186-1192 (1992). 6. V. Kilchytska, D. Levacq, D. Lederer, J.-P. Raskin, and D. Flandre, in: Proceedings of the 32nd European Solid-State Device Research Conference, edited by G. Baccarani, E. Gnani, and M. Rudan (University of Bologna, Firenze, 2002), pp. 519-522. 7. V. Kilchytska, D. Levacq, D. Lederer, J.-P. Raskin, and D. Flandre, Floating Effective Back-Gate Effect on the Small-Signal Output Conductance of SOI MOSFETs, IEEE Electron Device Letters 24(6), 414-417 (2003). 8. Atlas Manual (2005). 9. J.-P. Raskin, A. Viviani, D. Flandre and J.-P. Colinge, Substrate Crosstalk reduction using SOI technology, IEEE Trans. on Electron Devices ED-44(12), 2252-2261 (1997). 10. S. Sze, Physics of Semiconductor Devices (Wiley, New-York, 1981). 11. S. Hofstein, and G. Warfield, Physical limitations on the frequency response of a semiconductor surface inversion layer, Solid State Electronics 8, 321-341 (1965).

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12. E.H. Nicollian, and J.R. Brews MOS Physics and Technology (A John Wiley & sons INC. publication, New Jersey, 2003). 13. D.K. Schroder, et al., Frequency domain lifetime characterization, IEEE Trans. on Electron Devices 47(8), 1653-1661 (2000). 14. G. Reichert, T. Ouisse, J. L. Pelloie and S. Cristoloveanu, Mobility modeling of SOI MOSFETs in the high temperature range, Solid-State Electron. 39(9), 1347-1352 (1996). 15. D. Lederer, and J.-P. Raskin, in: Science and Technology of Semiconductor-Oninsulator structures devices operating in a harsh environment, ed. by D. Flandre, A. Nazarov, P. Hemment, (NATO ASI Series, Kluwer Acad. Publishers, 2004), pp. 191196.

INVESTIGATION OF COMPRESSIVE STRAIN EFFECTS INDUCED BY STI AND ESL

S. ZAOUIA1,2*, S. CRISTOLOVEANU2 and A.H. PERERA1 1 Freescale semiconductor, 850 rue Jean Monnet, 38926 Crolles, France 2 IMEP, MINATEC, 3 parvis Louis Néel, BP 257, 38016 Grenoble Cedex 1, France *

To whom the correspondence should be adressed: <[email protected]>

Abstract. Two types of mechanical stress, induced by compressive etch stop layer (c-ESL) and/or shallow trench isolation (STI), are examined in advanced p-channel partially depleted SOI MOSFETs. Systematic measurements show that c-ESL significantly enhances the performance of PMOS devices without degrading the short-channel effects. The mechanical stress induced by c-ESL is inhomogeneous through the Si film, decreasing from the top to the bottom interface. We demonstrate that the combination of c-ESL and STI stress is a complex 3-D mechanism, which depends on the layout parameters: channel width (from 0.1 to 1 µm), channel length (down to 23 nm) and source/drain active surface.

Keywords: SOI, MOSFET, stress, etch-stop layer, STI, GIFBE

1. Introduction

It is clear that SOI technology is the best candidate for future generations of MOSFETs due to multiple advantages1-2 most noteably, scalability, performance, lower junction capacitance, soft error immunity, perfect vertical isolation and absence of latch-up. SOI technology is also very attractive for low-power, high-speed applications. Partially depleted (PD) CMOS is currently used for high performance circuits. It offers superior speed/power performance relative to the bulk-Si CMOS. The PD/SOI advantage over bulk-Si is mainly due to reduced junction capacitance and to floating-body effects.

239 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 239-250. © 2007 Springer.

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In previous technology nodes, the performance enhancement was achieved by device scaling. In recent advanced technologies, a number of ingredients are used to gain additional speed. An attractive solution to improve CMOS performance is to take advantage of the process- induced mechanical stress3,4. Since the stress is a natural consequence of isolation and gate stack processes, the idea is to control and exploit it instead of trying to eliminate it. The stress optimization and variation with device scaling are still open questions that motivate our work. In this paper, we investigate the characteristics of advanced partially depleted p-channel MOSFETs with an ultra high compressive etch-stop layer. The c-ESL basically results in uniaxial stress in x-direction, as shown in Fig. 1. The shallow trench isolation (STI) induces an additional compressive strain in both longitudinal (x) and lateral (y) directions. STI stress is therefore likely to depend on the layout parameters: gate length (Lg), width (W) and source/drain length (Sa). The c-ESL devices were compared to reference samples (Ref ), where only STI stress subsisted. 2. Background on holes transport

The valence band is composed of degenerated heavy hole (HH) and light hole (LH) bands. The band occupation ratio is in favour of heavy holes, therefore hole transport in p-channel MOSFETs is governed by the proprieties of HH band5. There are two types of stress. Bi-axial stress is usually obtained at the wafer level, by growing strained silicon on relaxed silicon germanium substrates. The smart-Cut process enables the transfer of a thin strained silicon film on insulator. Wang et al reported that a possible disadvantage of such stress is the loss of the mobility enhancement at high lateral field6. The second option is to use the uniaxial stress, induced at the device level. Very promising is the uniaxial stress generated by ESL. Note that waferlevel and device-level stress can be combined. The hole mobility is anisotropic: it depends on the conduction orientation as well as on the stress type and direction. In our devices, the conduction orientation is [110]. In this case, the favoured stress configuration to enhance hole mobility is a compressive stress in the x-direction and a tensile stress in y-direction3. When applying the appropriate stress in the appropriate direction, the proportion of LH and HH is modified so that the contribution of light holes is reinforced. The drain current conduction involves more carriers with lighter effective mass, hence the average mobility is enhanced.

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3. Device technology

The transistors studied in this work have a gate length of 1µm down to 23 nm and a gate width of 1 µm down to 0.3 µm. They were fabricated on 300 mm SOI wafers. The buried oxide (BOX) thickness is 145 nm, and the Si layer is 50 nm thick. The transistors are isolated by shallow trench isolation (STI) and have a 100 nm thick poly-Si gate and a 1.2 nm nitrided gate oxide7. They have offset spacers for extension and pocket implants, and a thick nitride spacer. The devices received a high tilt boron pocket implantation. The pocket implant is used to control the short-channel effect and the off-state leakage. In addition, the devices received a lightly doped drain (LDD) implantation which serves to reduce the high electric fields and the hot-carrier injection, thus enhancing the MOSFETs reliability8. The source/drain received NiSi silicidation. NiSi has a low reaction temperature for salicide formation and offers relatively low sheet resistance9. Consequently, NiSi is well integrated in a low temperature process conceived to reduce undesired implant diffusion. Two types of devices were investigated and compared. The c-ESL transistors feature a high compressive etch-stop layer, combined with the compressive STI stress. In reference (Ref) transistors, the etch-stop layer is relaxed (no strain), while the STI stress is maintained. The STI induced stress was evaluated by varying the device layout parameters: W and Sa.

Lg Sa

y

Source

x

z

Sa

Gate

Drain

Compressive stress in channel

W

c-ESL

Gate

x STI

S

D

STI

BOX

Figure 1. Schematic of SOI MOSFET showing the mechanical stress induced by the c-ESL and STI. The layout parameters are Lg, W and Sa.

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4. Experiment

Systematic measurements were carried out on various devices. The MOSFET parameter extraction was made in the linear mode of operation at Vd = 10 mV. The method of extraction is based on the combined exploitation of the drain current and the transconductance. The Y-function technique denoted by Eq. 1, avoids the effects of the mobility reduction with gate voltage and minimizes the impact of series resistance10:

Y=

Id gm

= β .Vd ⋅ (V g − Vth )

(1)

Figure 2 shows that a linear dependence of Y with Vg is clearly observed in strong inversion. The low-field mobility, µ0 is calculated from the slope value, where β = µ0.Cox. W/Lg. The threshold voltage Vth is determined by the intercept of the fit line and the x-axis. This method was already validated by comparison with split-capacitance-voltage (C-V)11 and magnetoresitance methods12. The characteristics of our devices shown in Fig. 2, did not make it necessary to use the more advanced Y-technique where the quadratic mobility attenuation factor is accounted for13.

1,0

Fit

Normalized Y

0,8 0,6 0,4

Vth

0,2 0,0 0,0

0,2

0,4

Low-field extraction domain

0,6

0,8

1,0

1,2

1,4

Vg (V) Figure 2. Normalized Y-function versus gate voltage showing the domain for low-field mobility extraction (Lg = 36 nm, W=1µm).

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5. Results 5.1. SHORT-CHANNEL EFFECT

The variation of Vth versus the gate length (Lg) of Fig. 3(a), shows the shortchannel effect (SCE). Two competing mechanisms can be observed: (i) the usual decrease in Vth for Lg < 36 nm, due to charge sharing, and (ii) the Vth roll-off compensation by the increase in the effective doping due to the pocket implant14 (Vth increases from 1 µm to 36 nm gate length). The key point, shown in Fig. 3(a), is that the mechanical stress induced by c-ESL has no impact on Vth roll-off.

Ref c-ESL

T hreshold voltage (V )

0.45

0.40

0.35

0.30

W = 1 µm 0.25 0.01

0.1

1

S u b th re s h o ld s w in g (m V /d e c )

Lg (µm) 220

(a)

Ref c-ESL

200 180 160 140 120

W = 1 µm

100 80 60 0.01

0.1

Lg (µm)

1

(b)

Figure 3. (a) Linear threshold voltage versus gate length showing the short-channel effect for the Reference (Ref) and c-ESL PMOS devices (W=1µm, Vd = 10 mV). (b) Subthreshold swing versus gate length for Reference and c-ESL PMOS devices (W=1µm, Vd = 10 mV).

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Figure 3(b) depicts the variation of the subthreshold swing versus the gate length. The channel is very well controlled by the gate for transistor lengths longer than 36 nm whilst the subthreshold swing is maintained under 100mV/decade. In long channels, the swing is exceptionally low (~65 mV/decade) thanks to the aggressive thickness of the gate dielectric. But, for very short devices (23 nm) the gate control is gradually lost. The interesting point here is the perfect match between the c-ESL and Reference transistors. We can conclude by saying that the mechanical stress induced by c-ESL has no impact on SCE. 5.2. GEOMETRY EFFECTS

5.2.1. Gate length Figure 4(a) illustrates the main achievement of this technology. The lowfield mobility (µ0) is clearly enhanced by c-ESL due to mechanical stress. We note the better roll-off of the mobility which is explained by the competition between the increase of the mechanical stress level in shorter channels (for the same c-ESL), the increase of the effective doping level due to pocket implant, and the series resistance degradation. Figure 4(b) shows the hole mobility gain offered by c-ESL, versus the gate length. The enhancement is accentuated when scaling the device length. This demonstrates that the mechanical stress, induced by c-ESL and transmitted to the channel, increases in short devices. The benefit of the ESL techniques is clearly amplified with device scaling. In saturation mode, the impact of the mechanical stress induced by c-ESL is qualitatively preserved. Figure 4(a) depicts the saturation current (Idsat) variation versus the Lg. The Idsat values are normalised to Vg-Vthsat to Hole mobility enhancement (%)

80

c-ESL

2

Hole mobility (cm /Vs)

100

60 40

Ref 20

W =1 µm 0 0,01

0,1

Lg (µm)

1

(a)

250

W = 1 µm

200 150 100 50 0 0,01

0,1

Lg (µm)

1

(b)

Figure 4. (a) Low-field mobility versus gate length, showing enhancement of hole mobility due to the increased contribution of the compressive c-ESL stress in shorter channels. (b) Hole mobility enhancement versus gate length, showing the net increase of the c-ESL stress transmited to the channel when Lg decreases.

PROCESS-INDUCED STRAIN

Normalized IdSat (µA/V)

30

245

c-ESL

25 20 15

Ref

10 5 0 0,01

W = 1 µm 0,1

1

Lg (µm) Figure 5. Normalized saturation current (Idsat) versus gate length, demonstrating the gain in performance of PMOSFETs due to c-ESL stress.

eliminate the influence of threshold voltage variations. The comparison of Figures 4(a) and 5 confirms that Idsat follows the variation of µ0, which stands as the main parameter for stress-induced optimization. However, the low-field mobility enhancement is larger than the gain in saturation current. This can be explained by the role of series resistances, which increases in shorter devices and affects primarily the current. Indeed, the Y function offers a mobility value which is basically free from series resistance effects. Another mechanism that can come into play is the increase of the ballisticity rate in shorter MOSFETs. 5.2.2. Gate width Figure 6(a) shows the variation of the mobility versus the gate width for cESL and Ref devices. When the gate is narrower, the mobility decreases for both devices. For reference devices, the mobility decreases slightly in narrow channels (5-10%, Fig. 6(b)) because the STI compressive stress in y-direction increases15. When STI and c-ESL are combined the mobility exhibits more degradation for W < 1 µm, probably due the addition of the two stresses in the y-direction. Hence c-ESL does not induce just a compressive uniaxial stress in the x-direction, but also a residual compressive stress in the y-direction. The latter y-stress becomes relevant in narrow devices exclusively.

246

PROCESS-INDUCED STRAIN 80

60

2

Hole mobility (cm /Vs)

c-ESL

40

Ref

20

Lg = 36 nm 0 0,0

0,2

0,4

0,6

0,8

1,0

W (µm)

(a)

Mobility change (%)

0

Ref -5

-10

c-ESL

-15

Lg= 36 nm -20 0.0

0.2

0.4

0.6

W (µm)

0.8

1.0

(b)

Figure 6. (a) Low-field mobility versus gate width, showing enhancement of hole mobility due the compressive c-ESL stress. (b) Relative degradation rate of low-field mobility versus gate width, by comparison to W = 1 µm (Lg = 36 nm, Vd = 10 mV).

5.2.3. Source/drain length The STI stress in x-direction varies according to the Sa distance as shown in Figure 7. For shorter Sa, the compressive stress increases leading to a mobility improvement, by up to 20%. In c-ESL devices, the same trend is obtained although the absolute mobility value is higher. This shows the general benefit of optimizing Sa.

PROCESS-INDUCED STRAIN

Mobility change (%)

20

247

Lg= 36 nm_Ref Lg= 240 nm_Ref Lg= 240 nm_c-ESL

15 10

W = 1 µm

5 0 0.0

0.5

1.0

1.5

2.0

Sa (µm) Figure 7. Relative enhancement of low-field mobility versus Sa by comparison with Sa = 1.675 µm, for long and very short devices.

3,0

W = 1 µm

Front channel Back channel

2,5

µ0_c-ESL µ0_Ref

2,0 1,5 1,0 0,5 0,0

Lg= 36 nm

Lg= 75 nm

Figure 8. Ratio of hole mobilities in c-ESL and Reference PMOSFETs for front and back channels.

5.3. FRONT/BACK CHANNEL COMPARISON

An interesting comparison between the mobility values at front and back channels is given in Fig. 8. The back-channel mobility was resolved from the Y function by using the substrate bias as a back gate. The c-ESLinduced gain in mobility is significantly larger at the top channel, implying that the stress is not uniform in the vertical direction. The difference in the mobility enhancement can reach one order of magnitude (from 300% at top channel to 30% at the bottom channel). This result is reasonable because

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1,0

Ref

gm/gmmax

0,8 0,6 0,4

c-ESL L g = 75 nm

0,2 0,0 0,0

W = 1 µm 0,2

0,4

0,6

0,8

1,0

1,2

1,4

V g (V) Figure 9. Normalized transconductance versus gate voltage showing the GIFBE effect (for Vg = 1.1 V) in Reference and c-ESL MOSFETs.

the c-ESL stress results from the top-gate processing. It indicates the possible difference between inhomogeneous process-induced stress and homogeneous stress in sSOI plain wafers. 5.4. GIFBE

The gate-induced floating body effect (GIFBE) is reflected by a second peak in the transconductance gm of PD transistors16. The normalization of the transconductance (Fig. 9), allows comparing gm peaks in several transistors. The GIFBE is more important in Reference devices than in cESL devices. This result tends to indicate that the floating body effect is reduced in c-ESL MOSFETs, as a consequence of carrier lifetime degradation by strain and/or reduction of the tunneling current from the Si valence band into the gate (i.e., band gap modification). 6. Conclusion

Compressive etch-stop layer strain is an efficient tool to enhance the hole mobility in sub-100nm long PD SOI MOSFETs. STI-induced strain results in an additional gain in mobility, in particular if the source/drain active surface (Sa) is short enough. The c-ESL stress is mainly uniaxial in the longitudinal x-direction, with a transversal component (in y-direction) which appears in very narrow channels. The combination of the STI and cESL stress is a complex 3-dimensional mechanism which depends on the transistor layout and the transistor surrounding pattern. The mobility decreases however in narrow devices (W < 1 µm). The stress is

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inhomogeneous in the vertical direction, and is also responsible for a reduction of floating-body effects. It would be interesting to explore how these effects may change when combining wafer-level biaxial stress with device-level technology-induced stress.

References 1.

J. P. Colinge, Silicon-On-Insulator Technology: Materials to VLSI (Kluwer, Boston, 1991). 2. S. Cristoloveanu and S.S. Li, Electrical Characterization of Silicon-On-Insulator Materials and Devices (Kluwer Academic. Boston; 1995). 3. S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N. Ikezawa, T. Suzuki, T. Saitoh, and T. Hiriuchi, Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design, in: Tech. Dig. IEDM (2000), pp. 247-250. 4. R.A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance, in: Tech. Dig. IEDM (2002), pp. 117-120. 5. X.-F. Fan, L. F. Register, B. Winstead, M. C. Foisy, W. Chen, X. Zheng, B. Ghosh, and S. K. Banerjee, Hole Mobility and Thermal Velocity Enhancement for Uniaxial Stress in Si up to 4 GPa, IEEE Trans. Electron Devices, 54(2), 291-296 (2007). 6. E. X. Wang, P. Matagne, L. Shifren, B. Obradovic, R. Kotlyar, S. Cea, M. Stettler, and M. D. Giles, Physics of Hole Transport in Strained Silicon MOSFET Inversion Layers, IEEE Trans. Electron Devices, 53(8), 1840-1851, (2006). 7. B. Tavel, M. Bidaud, N. Emonet, D. Barge, N. Planes, H. Brut, D. Roy, J. C. Vildeuil, R. Difrenza, K. Rochereau, M. Denais, V. Huard, P. Llinares, S. Bruyere, C. Parthasarthy, N. Revil, R. Pantel, F. Guyader, L. Vishnubotla, K. Barla, F. Arnaud, P. Stolk, and M. Woo, Thin oxynitride solution for digital and mixed-signal 65nm CMOS platform, in: Tech. Dig. IEDM (2003), pp. 27.6.1-27.6.4. 8. A. F. Tasch, Best Structures for Deep Submicrometer (0.1-0.3 pm) MOS Devices. IEEE Trans. Electron Devices, 38(12), 2688 (1991). 9. B. Froment, M. Muller, H. Brut, R. Pantel, V. Carron, H. Achard, A. Halimaoui, F. Boeuf, F. Wacquant, C. Regnier, D. Ceccarelli, R. Palla, A. Beverina, V. DeJonghe, P. Spinelli, O. Leborgne, K. Bard, S. Lis, V. Tirard, P. Morin, F. Trentesaux, V. Gravey, T. Mandrekar, D. Rabilloud, S. Van, E. Olson, J. Diedrick, Nickel vs. cobalt silicide integration for sub-50nm CMOS, in: ESSDERC proc. (2003), pp. 215-218. 10. G. Ghibaudo, New method for the extraction of MOSFET parameters, Electronics Lett. 24(9), 543-545 (1988). 11. Y. M. Meziani, J. Lusakowski, W. Knap, N. Dyakonova, F. Teppe, K. Romanjek, M. Ferrier, R. Clerc, G. Ghibaudo, F. Boeuf, and T. Skotnicki, Magnetoresistance characterization of nanometer Si metal-oxide-semiconductor transistors, J. Appl. Phys. 96(10), 5761-5 (2004). 12. W. Chaisantikulwat, M. Mouis, G. Ghibaudo, C. Gallon, C. Fenouillet-Beranger, D. K. Maude, T. Skotnicki, S. Cristoloveanu, Differential magnetoresistance technique for mobility extraction in ultra-short channel FDSOI transistors, Solid-State Elect. 50(4), 637-43 (2006).

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13. P. K. McLarty, S. Cristoloveanu, O. Faynot, V. Misra, J. R. Hauser, and J. J. Wortman, A simple parameter extraction method for ultra-thin oxide MOSFETs, Solid-State Elect. 38(6), 1175-1177 (1995). 14. S. Zaouia, S. Goktepeli, A.H. Perera, and S. Cristoloveanu, Short-channel, narrow channel and ultra-thin oxide effects in advanced SOI MOFETS, in: ECS proc. 3 (2005), pp. 309-16. 15. Y. Luo, and D. K. Nayak, Enhancement of CMOS performance by process-induced stress, IEEE Trans. Semi. Manuf. 18(1), 63-68 (2005). 16. J. Pretet, T. Matsumoto, T. Poiroux, S. Cristoloveanu, R. Gwoziecki, C. E. Raynaud, A. Roveda, H. Brut, New Mechanism of Body Charging in Partially Depleted SOIMOSFETs with Ultra-thin Gate Oxides, in: ESSDERC Proc. (2002), pp. 515-8.

CHARGE TRAPPING PHENOMENA IN SINGLE ELECTRON NVM SOI DEVICES FABRICATED BY A SELF-ALIGNED QUANTUM DOT TECHNOLOGY

ALEXEI NAZAROV1*, VLADIMIR LYSENKO1, XIAOHUI TANG2, NICOLAS RECKINGER2, VINCENT BAYOT2 1 Lashkaryov Institute of Semiconductor Physics, NAS of Ukraine, Prospekt Nauki 45, 03028 Kyiv-28, Ukraine. 2 Microelectronics Laboratory (DICE), Université Catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium * To whom correspondence should be addressed: A. N. Nazarov, Lashkaryov Institute of Semiconductor Physics, NAS of Ukraine, Prospekt Nauki 45, 03028 Kyiv-28, Ukraine, e-mail: [email protected].

Abstract. Сharge trapping in self-aligned single-dot memory devices fabricated by UCL technology based on arsenic-assisted etching and oxidation effects is investigated. The devices demonstrate room-temperature single-electron trapping in the Si nanodot floating gate circa 16 nm in size. The pulse transfer (Id -Vg) characteristics and time evolution of the drain current (Id - t) technique are employed for determination of the total charge storage in the Si nanodot floating gate and the gate-nanodot capacitance of the devices.

Keywords: Single-electron memory, charge trapping, self-aligned quantum dot technology

1. Introduction

Single-electron (SE) non-volatile memory (NVM) devices are considered to be a driver for the semiconductor industry for coming decades.1 Furthermore and importantly, SE NVM can be easily integrated in the modern CMOS SOI technology which will allow a reduction of gate length in the nanoscale region. SE NVM is characterized by the presence of a

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single-nanodot floating gate which is self aligned with the MOSFET channel. However in main cases1-3 fabrication of such devices demands very high-resolution lithography tools. Employing a technique developed in UCL4,5 based on arsenic-assisted etching and oxidation effects, allows us to realize self-aligned single-dot memory devices using current optical lithography tools. This paper is devoted to the study of single-electron charging of Si nanodots formed using the above mentioned technology and development of electrical characterization methods of such NVM devices. 2. Samples and measurement technique

A detailed process fabrication flow for the SE NVM devices can be found in the paper of X.Tang et al.4 Briefly, an SOI wafer was doped by arsenic at an energy of 110 keV and dose of 1015 cm-2. The arsenic-assisted etching resulted in trench formation at the sidewalls of the silicon wire. After wet oxidation, a tunnel oxide has been formed in the trench region as shown in Figure 1. The floating gate has an equivalent diameter of 16 nm and the channel has a height and a base width of 80 nm. The fabricated device is an inversion mode (IM) p-channel MOSFET with a gate oxide thickness of 27 nm. The room temperature charging processes of the nanodot floating gate were studied based on the shifting of drain current – gate voltage (Id-Vg) characteristics in sweep and pulse modes and the measurements of drain current – time (Id-t) characteristics. To avoid channel heating effects, drain voltage during our measurements was held at 10 mV.

Figure 1. SEM cross-section of a fabricated nano memory device with a single-dot floating gate which is self-aligned to the channel. The floating gate has an equivalent diameter of 16 nm.

CHARGE TRAPPING IN SINGLE ELECTRON NVM DEVICES

253

3. Experimental results and discussion 3.1. DRAIN CURRENT – GATE VOLTAGE CHARACTERISTICS

Figure 2 presents the Id-Vg characteristics measured by sweeping gate voltages forward and back with a long integration time. Noticeable hysteresis is observed with three jumps in the forward current curve (measured at the gate voltages swept from +1V to –7.5V). The hysteretic behavior indicates that the floating gate is charged by holes during the sweeping of gate voltage from positive to negative values, while the appearance of the current jumps can be associated with single hole injection from the inversion channel to the floating gate. In order to obtain the Id-Vg characteristic without charging of the floating gate, we used the sweep pulse measurement (Fig. 2) over the range of gate voltage from 0V to -7.5V. In this measurement, the pulse width was 10 ms with period 1 s. This set-up assists the discharge of the device at 0V just after applying the charging pulse voltage. Unlike the Id-Vg characteristics measured in sweep mode, the pulse Id-Vg characteristics have not shown hysteresis effect but shift a little towards the direction of positive gate voltage. This is evidence of a lack of charge trapping in the floating gate during the 10 ms applied gate bias. To determine the largest number of holes trapped on the nanodot floating gate, we compare this pulse IdVg characteristic with one measured in sweep mode with a long integration time after charging. The comparison shows that the maximal threshold voltage shift of the Id-Vg characteristic MAX during the hole charging is equal to ∆VTH =0.75V.

Figure 2. ISD-VG characteristics of the p-channel MOSFETs with nanoscale floating gate measured both in pulse and sweep regimes (VSD = 10 mV).

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CHARGE TRAPPING IN SINGLE ELECTRON NVM DEVICES

3.2. CHARGE TRAPPING DYNAMICS

To study charge trapping dynamics, we performed the time evolution of drain current in which a constant gate voltage of –5.8 V is set and held. Several abrupt reductions of drain current are observed during the first 40 s as shown in Fig. 3. Such current reductions are a characteristic feature of single electron (hole in our case) trapping in the floating nanodot embedded in the gate oxide. It is found that the hole trapping is stochastic, but the number of reductions is reproduced in different measurements. Statistical analysis of the dependence of all drain current reductions on the associated generation time was performed for an applied gate voltage of –6.0V. The results are presented in Fig. 4. On average we observed three groups of hole charge trapping: the first group appears in the range from 0 to 10 s, the second group is from 10 to 20 s, and third one, from 25 to 40 s. The probability of charge trapping can be estimated using the following expression: P ∝ exp(−time / τ C ) .

(1)

Employing Eqn. (1) for the first charge trapping group we calculated a charging time (τC) for our device, which was found to be 1.68±0.21 s. This value is much smaller than that of Molas6 (50s) and Yano7 (12.9s) at a gate voltage of 12 V. It is worth noting that the level of drain current after current reductions, is different. This may be associated either with current fluctuations or injection of different numbers of holes onto the floating gate. It was assumed that every drain current increment corresponds to the injection of one hole, and using Eqn. (2) obtained by Molas and others6 an average number of injected holes can be estimated:

Figure 3. Drain current vs. time at -5.8V applied gate voltage for the p-channel MOSFETs with nanoscale floating gate.

Figure 4. Bar graph of drain current jumps number vs. its time appearance.

CHARGE TRAPPING IN SINGLE ELECTRON NVM DEVICES

log(

I D0 q , )= I D 0 − ∆I D sC2

255

(2)

where 1/s is the slope of the logID(VG) curve and C2 is the capacitance between the floating gate and the control gate; ID0 is the initial drain current before the charging. Equation (2) can be presented in a form for n trapped charges:

I D (n ) qn = exp( − ). I D0 log(esC 2 )

(3)

Equation (3) demonstrates that we can determine C2 from a linear plot of ln(ID/ID0) versus qn. From Fig. 5, we estimate the capacitance C2 to be 1.9 aF according to log(esC2) = 6.2, here s is equal to 1.2 V determined from experimental log(ID) - Vg curve and e is 2.7. From Fig. 5 we can see that maximum number of trapped holes is 10. Thus, the threshold voltage shift due to one trapped hole, ∆Vth , can be calculated as 0.075V. Since 7 ∆Vth = q CGC , where CGC is the capacitance between gate and channel , herefore CGC can be estimated as 2.1aF. Finally, it should be noted that the maximal probability of charge trapping depends on the gate voltage. In Fig. 6 both the experimental and simulation results are presented. The simulation shows that the maximal probability of charge trapping is increased exponentially with the increase of gate voltage: Pm = P0{1- exp[-K(V-V0)]},

(4)

where K is the coefficient connected with tunneling probability through the tunnel oxide and V0 is the threshold voltage Vth, which is 5.4V in our case.

Figure 5. Normalized drain current as a function of number of current jumps.

Figure 6. Probability of maximal charging value appearance as a function of gate voltage.

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CHARGE TRAPPING IN SINGLE ELECTRON NVM DEVICES

4. Conclusions

The SOI NVM devices with Si self-aligned single-dot floating gate of 16 nm present room-temperature single-hole trapping. The total charge trapped onto the Si nanodot floating gate consists of 10 holes. The charging time of the first hole is 1.68s. The results obtained confirm the possibility to fabricate SE NVM by technology based on arsenic-assisted etching and oxidation effects. ACKNOWLEDGMENTS

This work has been partly funded by the European Commission under the frame of the Network of Excellence “SINANO” (Silicon-based Nanodevices, IST-506844).

References 1.

2.

3.

4.

5.

6.

7.

L. Guo, E. Leobandung, and S. Y. Chou, A room-temperature silicon single-electron metal-oxide-semiconductor memory with nanoscale floating-gate and ultra narrow channel, Appl. Phys. Lett. 70 (7), 850-852 (1997). A. Nakajama, T. Fatatsugi, K. Kosemura, T. Fukano, and N. Yokoyana, Roomtemperature operation of Si single-electron memory with self-aligned floating dot gate, Appl. Phys. Lett. 70 (13), 1742-1744 (1997). W. Wu, J. Gu, H. Ge, Ch. Keimel, and S.Y. Chou, Room-temperature Si single electron memory fabricated by nanoimpront lithography, Appl. Phys. Lett. 83 (11), 2268-2270 (2003). Xiaohui Tang, X. Baie, J.-P. Colinge, A. Crahay, B. Katschmarsyj, V. Scheuren, D. Spôte, N. Reckinger, F. Van de Wiele, and V. Bayot, Self-aligned silicon-on-insulator nano flash memory device, Solid-State Electron. 44, 2259-2264 (2000). Xiaohui Tang, N. Reckinger, V. Bayot, C. Krzeminski, E. Dubois, A. Aillaret, and D. C. Bensahel, Room-Temperature Single-Electron Operation and Fabrication Reproducibility of Self-Aligned Single-Dot Memory Devices, IEEE Trans on Nanotechnology 5 (6), 649-655 (2006). G. Molas et al., Single electron charging and discharging phenomena at room temperature in a silicon nanocrystal memory, Solid-State Electronics 47, 1645-1649 (2003). K. Yano, T. Ishii, T. Hashimoto. T. Kobayashi, F. Murai, and K. Seki, Roomtemperature single-electron memory, IEEE Trans. Electron. Devices 41 (9), 1628-1638 (1994).

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Theory and Modeling of Nanoscaled Devices

VARIABILITY IN NANOSCALE UTB SOI DEVICES AND ITS IMPACT ON CIRCUITS AND SYSTEMS

ASEN ASENOV1*, KHAIRULMIZAM SAMSUDIN2 1 Department of Electronics and Electrical Engineering The University of Glasgow, Glasgow G12 8LT Scotland, UK 2 Department of Computer & Communication Systems Engineering, University Putra 43400 Serdang, Selangor, Malaysia *Tho whom the correspondence should be addressed: Asen Asenov

Abstract. We have studied, using 3D statistical simulation, the variability in UTB SOI MOSFETs with sub 10nm dimensions introduced by random discrete dopants in the source/drain region, body thickness variation and line edge roughness. We have shown that the random dopants in the source/drain regions are the main source of variability in the studied devices. The results of the physical drift-diffusion simulation with quantum corrections are captured into statistical BSIMSOI compact model which are then used for statistical SRAM simulation. We have shown that SRAMs based on 10 nm UTB SOI transistor have less variability and better yield compared to SRAM based on 35 nm conventional (bulk) MOSFETs. However the scaling of the UTB SOI MOSFETs below 7.5 nm will cause significant yield and reliability problems in the corresponding UTB SOI SRAMs.

Keywords: UTB SOI, MOSFET, SRAM, Intrinsic Parameter Variation

1. Introduction

The concept of device scaling has been consistently applied over the past three decades, increasing the density, the performance, and reducing cost

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per function of the corresponding integrated circuits and systems [1]. However, the scaling of conventional device architectures such as bulk MOSFETs is approaching fundamental physical limits. As device dimensions shrink to the nanometre regime, the limitations of conventional bulk MOSFETs are becoming more pronounced due to increasing short-channel effects causing threshold voltage roll-off, lack of performance due to increasing access resistance, material limitations of conventional gate stack and technological difficulties [2]. One of the most challenging by-products of feature scaling that is proving extremely difficult to manage, are the increasing variations of the transistor characteristics due to intrinsic parameter fluctuations. This problem is associated with the fundamental discreteness of charge and matter [3, 4] and cannot be removed by better processing steps or improved equipment [5]. Important sources of intrinsic parameter fluctuations include random discrete dopants [4-7], gate line edge roughness [8-10] and oxide thickness variations [11]. It has been demonstrated experimentally at device and circuit level that with the continuing scaling of conventional MOSFETs, the random variation in numbers and positions of discrete dopant atoms in the channel region induce threshold voltage and drain-current fluctuations which adversely affect the circuit performance [12, 13]. These atomic-scale intrinsic fluctuations cannot be eliminated by tighter manufacturing process control and have already become one of the major stumbling blocks to scaling and integration. The International Technology Roadmap for Semiconductors (ITRS) [1] introduces several novel device architectures to secure the continuation of the MOSFET scaling near the end of the roadmap. Ultra-thin body siliconon-insulator (UTB-SOI) MOSFETs are one of the promising emerging devices that offer better control of short-channel effects compared to conventional bulk MOSFET. In SOI devices, short-channel effects are controlled by the thickness of the silicon film, thus allowing for gate length scaling below 10 nm [14]. Tolerating low doped or intrinsic channels, UTB devices have negligible depletion charge and capacitance, which yields a steep subthreshold slope. In addition, by dielectrically isolating the body region from the substrate, the SOI technology significantly reduces the junction capacitance contribution to the device capacitive load. 2. UTB-SOI MOSFET

Working UTB-SOI transistors with a channel length of 6 nm [14] and body thickness down to 3 nm [15] have already been successfully demonstrated.

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However, the optimal scaling of the UTB-SOI MOSFETs to such dimensions requires a body thickness in the range of nanometres. At such body thicknesses and device dimensions local variations in body thickness, geometry variations, due to line edge roughness and random discrete dopants in the source and drain region, will have a dramatic impact on the device parameter variations. Although UTB-SOI transistors can tolerate very low doping concentration in the channel region and therefore are more resistant to intrinsic parameter fluctuations induced by random discrete dopants compared to the conventional MOSFETs, there are unavoidable discrete random dopants in the source/drain regions. While UTB-SOI devices offer a potential solution to the ultimate MOSFET scaling, a reliable early estimate for the magnitude of the corresponding intrinsic parameter fluctuations becomes extremely important. From an integration and systems perspective, an in-depth investigation of realistic UTB-SOI MOSFET behaviour in the presence of intrinsic parameter fluctuations is also important to understand at which technology generation such fluctuations will affect the UTB-SOI circuit robustness yield and performance. The increasing device variability is especially critical for SRAM due to the use of minimum geometry devices to minimize cell area in combination with the requirement of adequate stability and high performance. 2.1. THE SIMULATED STRUCTURE

Most simulation studies of IPF have been restricted to devices corresponding to one particular technology node. In this work, the study of IPF has been extended to UTB-SOI MOSFETs corresponding to three technology generations near the long-term end of the current edition of the ITRS [1]. This follows in detail both the magnitude and trend of parameter fluctuations in next generation MOSFETs technology. This work only considers high performance devices, which are typical for microprocessor cache and System on Chip (SoC) applications. The generic structure of the simulated devices is illustrated in Figure 1. The summarised device parameters for the investigated family of UTB-SOI MOSFETs are depicted in table 1. The 10 nm, 7.5 nm and 5 nm channel length UTB-SOI MOSFETs correspond to the 25 nm, 20 nm and 14 nm

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Figure 1. Diagram of the generic UTB-SOI MOSFET simulated in this work.

TABLE 1. UTB-SOI MOSFETs physical parameters considered. Channel length/width [nm]

10/10

7.5/7.5

5/5

Gate oxide thickness, tox [nm]

0.67

0.50

0.33

Body thickness, tSi [nm]

2.5

2.25

2

Buried oxide thickness, tbox [nm]

50

Channel doping, Na [cm-3]

1014

Source/Drain doping, Ns/d [cm-3]

2x1020

technology generations respectively. Another simplification of our simulations is the use of silicon dioxide (SiO2) thickness and dielectric constant to achieve the electrostatic requirement. However, it is believed that such equivalent oxide thickness (EOT) with the application of high-k gate dielectric will become feasible in the near future [2]. In order to investigate the impact of intrinsic parameter fluctuations on UTB-SOI MOSFETs, the Glasgow device simulator has been employed [16, 17]. This three-dimensional atomistic device simulator is based on the drift diffusion approach to the solution of the semiconductor equations (Poisson and current continuity), employing density gradient quantum corrections. The simulations only capture fluctuations induced by electrostatics and the quantum confinement effect, and do not include transport variations due to scattering from different impurity and body thickness configurations effects or tunnelling through the gate oxide.

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2.2. SIMULATION STRATEGY

2.2.1. Random discrete doping One major advantage of UTB-SOI is the tolerance to very low doping concentrations in the channel. This minimises the impact of intrinsic parameter fluctuations caused by random discrete channel dopants. However, unavoidable random discrete dopants in the source/drain regions will still result in nanometer scale variations of the effective channel length and variations in the source/drain access resistance both contributing to variations in drive current. Thus, the impact of RDD has a different nature in UTB-SOI devices compared to their bulk counterparts. RDD simulation in this work only considers dopants in the source/drain regions of the UTB-SOI MOSFETs. Although the most realistic way for introducing the random source/drain doping distributions into the atomistic simulations would be the use of the output from a Monte Carlo process simulations [18; 19], here we apply a simpler approach. Given the continuous doping distribution obtained from conventional process simulation tools, the probability that there is a dopant in each cell of the 3D simulation mesh is calculated. Then, using a rejection technique, the dopants are placed randomly in the source/drain regions 5. The doping concentration in the channel region has a continuous distribution with a doping concentration of 1014 cm-3. A typical potential distribution obtained from RDD simulation of a 10 nm UTB-SOI MOSFET is illustrated in figure 2. The heavily doped source and drain regions are clearly visible in the potential landscape. Strong potential fluctuations at the source/drain and channel interface associated with the discrete dopants can be observed. The equiconcentration contour in figure 2(a) highlights the basic features of the discrete dopants in the source/drain region. The discrete dopants render unusable the concept of a metallurgical junction introducing variation of effective channel length across the width of each simulated UTB-SOI MOSFET. Although the fluctuations in a conventional bulk MOSFET parameters are dominated by the randomness of dopants in the channel region [5], atomistic doping in the source and drain of UTB-SOI will introduce variations in the effective length of the channel, even for a perfectly defined gate pattern.

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Figure 2. A typical simulation domain for a 10×10 nm channel UTB-SOI MOSFET due to random discrete dopants at threshold. The gate and buried oxide is removed to show the fluctuations in (a) electrostatic potential and (b) carrier concentration contour at the source/drain and channel interfaces. The actual location of random discrete dopants in the source/drain regions is also illustrated.

2.3. BODY THICKNESS VARIATION

It has been experimentally demonstrated [20] that when silicon body thickness is reduced below 4 nm, slight (even single atomic layer) body thickness variations have a significant impact on the threshold voltage and carrier mobility of UTB-SOI MOSFETs. At such thickness, the atomic scale roughness of the top and bottom Si/SiO2 interfaces, on the scale of ±1 atomic layer (≈0.3 nm), will introduce appreciable variation in the silicon

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body thickness. Body thickness variation is introduced into simulations using statistically generated interface roughness patterns with RMS amplitude, (∆) of 0.3 nm and correlation length, (Λ) of 1.8 nm for the top and bottom Si/SiO2 interfaces. The Fourier synthesis technique used to generate the random interfaces [11] utilises a power spectrum which corresponds to an exponential autocorrelation function [21]. Figure 3 shows a typical rough interface generated using this approach, and the same surface digitised to ±0.15 nm in respect of the originally position of the smooth interface in the simulations.

(a)

(b) Figure 3. (a) Rough surface generated from the Fourier synthesis technique (Λ=0.3 nm, ∆=3 nm) and (b) the surface quantised to ±0.15nm to give the actual interface used in simulations. Reference [21].

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Figure 4. A typical simulation domain for a 10×10 nm channel UTB-SOI MOSFET with tsi=2.5 nm due to body thickness variations at threshold. The gate and buried oxide is removed to show the fluctuations in (a) electrostatic potential and (b) carrier concentration contour at the top and bottom Si/SiO2 interfaces. The silicon body thickness is also illustrated at the top of the images.

When studying the impact of body thickness variations, it is important to include quantum confinement effects which push the inversion layer away from the rough interface and also introduce variations in the position

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of the ground state depending on the local body thickness [22; 23]. In this work the simulations only capture fluctuations induced by the electrostatics and quantum effects, and do not include variations in the quantum confinement scattering introduced by variations in the effective quantum potential. Typical potential and carrier concentration distributions obtained in the simulation of a 10×10 nm channel UTB-SOI MOSFET are illustrated in figure 4 with the gate and buried oxide removed. The silicon body thickness is 2.5 nm and illustrated in the same figures. The potential fluctuations associated with the body thickness variations are visible in the figure 4(a). The variation in carrier concentration near the top and bottom interface due to the surface roughness and the corresponding body thickness variation is clearly depicted in figure 4(b). 2.3.1. Line edge roughness The contribution of line edge roughness in the gate pattern definition to the variation of electrical parameters will be significantly increased below the 80 nm technology generation [24]. In this work the investigation of LER is carried out by device simulation where the nominally straight edged gate is replaced by a randomly generated rough line pattern. The LER modelling approach used to generate random junction patterns is based on a Fourier synthesis technique and generates gate edges from the power spectrum corresponding to Gaussian autocorrelation functions [9, 25]. The expected smearing of the high frequency features in the edge profile due to implantation and subsequent diffusion is the reason for choosing to use a smoother edge profile generated from the power spectrum corresponding to a Gaussian autocorrelation function [25]. The LER parameters used to define the gate edges are the RMS amplitude, (∆) and correlation length, (Λ). However, unlike BTV simulations that use a constant RMS amplitude for each UTB-SOI MOSFETs investigated, the LER modelling uses the RMS amplitude predicted for each MOSFET generation by the ITRS [1]. It should be noted that the value quoted as LER is traditionally defined to be 3σ RMS amplitude. Starting from the 2003 ITRS edition, a new LER definition has been introduced. The term LER has been replaced by line width roughness (LWR) defined by the relationship:

LER = LWR / 2

(1)

The ITRS lithography guidelines for LER corresponding to the 10 nm, 7.5 nm and 5 nm UTB-SOI MOSFETs are given in table 2. The other parameter needed to characterise the gate LER is the correlation length. In contrast with the numerous values of RMS amplitude published in the literature for different lithography processes, significantly less is known about the corresponding correlation length [25], which is reported to vary.

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TABLE 2. ITRS 2005 edition LWR and LER guidelines. Year of Production

2015

2017

2020

DRAM ½ Pitch [nm]

25

20

14

MPU Physical Lg [nm]

10

8

5

Line Width Roughness (3σ) [nm]

0.8

0.6

0.5

Line Edge Roughness (3σ) [nm]

0.56

0.42

0.35

Figure 5. A typical simulation domain for a 10×10 nm channel UTB-SOI MOSFET due to gate line edge roughness at threshold. The gate and buried oxide is removed to show the fluctuations in (a) electrostatic potential and (b) carrier concentration contour at the source/drain and channel interface.

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between 10 nm and 50 nm. For the LER simulations presented in this work, the correlation length is assumed to be 30 nm. The potential and carrier concentration distributions for a 10×10 nm UTB-SOI MOSFET with randomly generated gate edges are illustrated in figure 5. The LER parameters are ∆=3 nm and Λ=30 nm. The potential in this MOSFET approximately follows the metallurgical pn junction as shown in the same figure. 2.4. IMPACT OF IPV ON UTB-SOI

The magnitude of intrinsic parameter fluctuations due to random discrete dopants, body thickness variations and line edge roughness using simulations of statistical samples of 200 UTB-SOI MOSFETs for each device design are presented in this section. The sources of intrinsic parameter fluctuations which can be separated in simulations, will occur simultaneously within a single MOSFET. To understand the magnitude of IPF in actual devices, simulations with all sources of intrinsic parameter fluctuations simultaneously present have also been performed. 2.4.1. ID-VG characteristic Figure 6 illustrates ID-VG characteristics obtained from the simulation of statistical samples of 200 macroscopically different 10 nm UTB-SOI MOSFETs in the presence of different sources of IPF. The simulations show that each microscopically different UTB-SOI MOSFET has different characteristics in the presence of random discrete dopants, body thickness variations and gate line edge roughness. Each source of IPF has a marked effect in the subthreshold regime leading to current fluctuations with large magnitude, but has a smaller impact on the on-current. The spread in the subthreshold characteristics due to RDD is largest compared to the spreads due to BTV and LER. The gate voltage dependence of the normalized difference between the average current, obtained from the statistical simulation of different sources of IPF and the current obtained from a continuously doped uniform device, ID is depicted in figures 7(a)-(c) for each of the simulated UTB-SOI MOSFETs. This comparison is important because continuously doped devices are still the basis of TCAD simulation in device design. In all cases, we observe an increase in the average current compared to the continuously doped uniform device. The difference between the average current and the current from the continuously doped uniform device is reduced at higher gate voltage.

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Figure 6. ID-VG characteristics from an ensemble of 200 macroscopically different 10 nm UTB-SOI due to (a) random discrete dopants (b) body thickness variations and (c) line edge roughness, along with the average . VG=50 mV.

RDD is the dominant source of IPF for the 10 nm, 7.5 nm and 5 nm UTB-SOI MOSFETs. Below the threshold voltage, random discrete dopants result in an approximately 60 percent increase of average “atomistic” current compared to the continuously doped devices. This is caused by the stochastic shortenings of the physical channel length and results in an overall reduction of the threshold voltage. Above threshold, the series resistance of the source and drain becomes large compared to the

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Figure 7. ID percentage difference for (a) 10 nm, (b) 7.5 nm and (c) 5 nm UTB-SOI MOSFETs between the average device characteristics and the continuously doped uniform device. The average current, are obtain from simulation of different sources of intrinsic parameter fluctuations individually and in combination.

channel resistance resulting in a relative reduction in the percentage difference of the average “atomistic” current and the current from a continuously doped device. BTV in UTB-SOI MOSFETs also results in an increase in the leakage current. This is due to local areas that have a reduced oxide thickness which facilitates the inversion and increases the amount of leakage current. Below threshold, there is approximately 40 percent “atomistic” current increase for the 10 nm and a further increase of approximately 45 percent for the 7.5 nm

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and 5 nm channel length devices. Above threshold, the variations of the body thickness have a less pronounced effect on the device characteristics due to the well-developed inversion layer throughout the device. In the case of LER, the spread in the characteristics is smaller compared to the case of RDD and BTV. Below threshold, there is approximately 30 percent increase in average current for the 10 nm devices and approximately 35 percent and 40 percent increase for the 7.5 nm and 5 nm channel length devices respectively. Although LER also causes shortening of the physical channel length similar to the case of random discrete dopants, the magnitude of the difference is smaller as the RMS amplitudes are reduced according to the ITRS requirement. Similar to the case of body thickness variation, the effect of LER becomes less pronounced above threshold. The impact of the three sources of IPF occurring simultaneously in an actual device is also illustrated in figures 7(a)-(c). As expected, the combined effect is larger compared to the effect of each individual source of IPF. Below threshold, the combined sources of IPF (RDD+BTV+LER) cause an approximately 70 percent average current increase for the 10 nm devices. As illustrated in figure 7(b) and 7(c) the increase of average current further rises to 75 percent and 90 percent for the 7.5 nm and 5 nm UTB-SOI MOSFETs respectively for combined sources of IPF. 2.4.2. Threshold voltage Threshold voltage VT, is an important parameter in MOSFET design. In concert with the subthreshold slope it determines the off-state leakage current. A well defined, steady and stable threshold voltage is crucially important for analogue and digital circuits, i.e., less variation of VT is highly desirable. Therefore, it is important to keep VT within an acceptable degree of tolerance in order to deliver a reliable integrated circuit and properly working systems. However in real nano-scale MOSFETs, the different sources of IPF introduce VT fluctuations. Moreover, the fluctuations increase significantly as the gate length decreases. Figure 8 illustrates the channel length dependence of the shift in the average threshold voltage, corresponding to different IPF sources compared to the threshold voltage of a continuously doped uniform device, VT0. Each source of IPF individually or in combination cause threshold voltage lowering compared to a continuously doped uniform device. The shift in the average threshold voltage increases almost linearly with the reduction in the channel length for all sources of IPF. In the case of combined sources of IPF, the average threshold voltage for 10 nm UTBSOI MOSFETs is reduced by 68 mV, while the 7.5 nm and 5 nm devices have a threshold voltage shift of 72 mV and 79 mV respectively. The

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Figure 8. Threshold voltage shift, ( - VT0) in 10 nm, 7.5 nm and 5 nm UTB-SOI MOSFETs due to different sources of intrinsic parameter fluctuations.

Figure 9. Standard deviation of threshold voltage in an ensemble of 200 distinct 10 nm, 7.5 nm and 5 nm UTB-SOI MOSFETs due to different sources of intrinsic parameter fluctuations.

results, along with the effects of each single source of fluctuations is shown in detail in figure 8. Figure 9 compares the standard deviation in the threshold voltage (σVT) introduced by different sources of IPF for all UTB-SOI MOSFETs investigated in this work. The results follow an intuitively expected trend as the fluctuations increase with decreasing channel length. BTV and LER cause a standard deviation increasing from approximately 10 mV to 30 mV as the channel length is scaled from 10 to 5 nm. However, in the RDD case the standard deviation of threshold voltage increases non-linearly from 14 mV in the 10 nm devices to approximately 75 mV in the 5 nm one. Assuming the 6σ spread of a normal distribution, often used for industrial yield calculation, 75 mV gives approximately a 450 mV range of threshold voltage bearing in mind an expected target VT of 200 mV. Such variations will significantly affect SRAM cells and peripheral circuit noise margins. It is also evident that the magnitude of fluctuations resulting from RDD in the source/drain regions will become a dominant source of intrinsic parameter

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fluctuations, especially for the 5 nm UTB-SOI MOSFETs compared to characteristic fluctuations due to BTV and LER in the gate pattern definition. The results for combined sources of IPF for each of the UTBSOI MOSFETs investigated are included in the same figure. The combined effects of three statistically independent variables on the standard deviation is given by the relationship σ1+ 2 + 3 = σ12 + σ 22 + σ 32 . Table 3 compares the standard deviation in the threshold voltage (σVT) from their addition as statistically independent entities to the results of simulations combining all three sources of intrinsic parameter fluctuations. The statistical summations of the standard deviations from individual sources of IPF are very close to the value obtained from the simultaneous simulation of the three fluctuation sources. This provides some evidence that these sources of fluctuations are uncorrelated. The simulations use SiO2 thickness and dielectric constant to secure the electrostatic integrity of the devices. The SiO2 thickness of 0.67 nm, 0.5 nm and 0.33 nm for the respective 10 nm and 7.5 nm and 5 nm channel length devices are unrealistic due to the exponential increase of tunnelling current through the gate dielectric with decreasing physical thickness [27]. Tunnelling currents in SiO2 layers thinner than 0.8 nm cannot be tolerated, even for high-performance devices [28]. To understand better the impact of intrinsic parameter fluctuations in the next generation UTB-SOI MOSFETs, a statistical simulation of the three devices with physically thicker high-k layers are necessary. Simulations with HfO2 gate dielectric were carried out keeping the same equivalent oxide thickness. A dielectric constant k=20 was assumed in this case and the thickness of the gate dielectric of the 10 nm and 7.5 nm and 5 nm have been increased by the ratio of the HfO2 on the SiO2 dielectric constants to TABLE 3. Summary of the standard deviations of threshold voltage, σVT for the case of individual and combined sources of intrinsic parameter fluctuations. Calculated σVT from the individual sources of intrinsic parameter fluctuations are also included. Intrinsic Parameter Variations

10 nm

7.5 nm

5 nm

RDD σVT [mV]

14.2

26.0

73.9

BTV σVT [mV]

7.4

13.4

23.2

LER σVT [mV]

11.9

17.6

28.6

Calculated σVT [mV]

20.0

34.1

82.5

RDD + BTV + LER σVT [mV]

22.8

35.2

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3.35 nm, 2.5 nm and 1.65 nm respectively. Figures 10(a) and (b) show the average threshold voltage shift and standard deviation of threshold voltage for the three UTB-SOI MOSFETs with SiO2 and HfO2 as gate insulators. The simulations are performed considering all sources of intrinsic parameter fluctuation in combination. Figure 10 shows a reduction between 5 and 10 percent average threshold voltage shift for devices with HfO2 gate insulator compared to devices with SiO2 gate insulator. This is caused by proximity effects associated with the five times increase of the HfO2 physical thickness. It should be noted that the physical thickness of the high-k insulator becomes more important as k increases and has to be taken into account in the simulations. Figure 11 indicates approximately 5 percent increase in σVT of devices with HfO2 gate insulator compared to devices with SiO2 gate insulator. The results show that, without considering the gate leakage effects, the use of SiO2 as gate insulator gives reasonably accurate results for the purpose of this work. The LER simulations carried out in this work follow the values prescribed by the ITRS according to the 10 nm, 7.5 nm and 5 nm UTB-SOI MOSFETs technology generations given in table 2. As shown in figure 11, the LER induced threshold voltage standard deviation for this scenario is well-controlled, increasing from 11 mV for the 10 nm channel length, rising to 23 mV for the 5 nm UTB-SOI MOSFET. However, the reduction of the LER in accordance with the ITRS requirements will be a very difficult task due to the molecular structure of the photo-resist the corpuscular nature of the light and the limitation of optical lithography. Therefore as a second scenario, simulations with a constant value of ∆=0.7 nm at all channel lengths were carried out keeping the correlation length at 30 nm. In this case, the LER threshold voltage standard deviation becomes worse than that of RDD. In this second scenario the LER results in a standard deviation of 36 mV at 10 nm channel length which increases to 103 mV at the 5 nm channel length.

Figure 10. (a) Average threshold voltage shift and (b) standard deviation of threshold voltage in 10 nm, 7.5 nm and 5 nm UTB-SOI MOSFETs from simulation of combined sources of intrinsic parameter fluctuations with different gate dielectric.

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Figure 11. Standard deviation of threshold voltage for 10 nm, 7.5 nm and 5 nm UTB-SOI MOSFETs due to different line edge roughness criteria. The simulation result considering RDD in the source/drain region as source of IPF is also included for comparison.

3. Statistical circuit simulation methodology

Until now, SRAM cell sizes have benefited in full from the technology ground rules and device dimension scaling [1]. However, it is now well recognized that the increasing variability in device parameters with scaling due to intrinsic parameter fluctuations [30; 31], can lead to less aggressive scaling of the SRAM cell in future technology nodes. This is bad news since microprocessors and System-on-Chip (SoC) applications require large SRAM arrays occupying an increasing fraction of the chip real estate. Around the 65 nm technology node, intrinsic parameter fluctuations start to eliminate much of the available noise margin and erode the overall speed in SRAM based on conventional MOSFETs. In general it is expected that UTB-SOI MOSFET SRAMs will outperform conventional MOSFETs due to superior electrostatic integrity. The steeper subthreshold slope permits also a better trade-off between power consumption and performance in the SRAM cell design. The significant reduction in junction capacitance of UTB-SOI MOSFETs also reduces a major component of bit-line capacitance, which is a critical parameter limiting SRAM performance [33]. UTB-SOI transistors can operate without dopant within the channel region, which improves the variability compared to conventional MOSFETs and will have a beneficial impact on SRAM yield. However at nanoscale dimensions the discreteness and randomness of the dopants in the source/drain regions together with atomic scale interface roughness and body thickness fluctuations in combination with LER will introduce variations in the UTB-SOI transistors. From a circuit and systems point of view, the intrinsic transistor variability must be captured in compact models which can be used in circuit simulators like SPICE [34]. This will ensure that the very important

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information related to the intrinsic parameter fluctuations is communicated to the circuit and system designers. At the other end, circuit designers must understand what range of variances the device will exhibit, to ensure that the circuit will function properly and deliver reasonable yield. This requires the development of statistical circuit simulation methodology taking into account the variability in the device characteristic at present and future MOSFET generations. In this section, a new statistical circuit simulation methodology is presented, that realistically takes into account the impact of intrinsic parameter fluctuations in transistors on the corresponding circuits. The methodology incorporates intrinsic parameter fluctuations information into Berkeley BSIMSOI [35] SPICE [34] compact model and is applied to the 10 nm, 7.5 nm and 5 nm channel length UTB-SOI MOSFETs simulated earlier. Statistical circuit simulation analysis consists of a series of statistical device-level and circuit-level simulations. The robust statistical circuit simulation methodology that has been developed for this work is depicted in figure 12. Critical ingredients of any statistical circuit modelling

Figure 12. Flowchart of statistical circuit simulation methodology.

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approach are the device data sets employed for parameter extraction, the MOSFET compact model and the parameter extraction process itself. The reliability and accuracy of the statistical circuit spread prediction scheme is ultimately determined by the suitability of these three components. The accuracy of MOSFET parameter extraction is determined by the quality of the collected electrical data sets coming from either simulations or from measurements. Current-voltage characteristic data sets for different bias condition enable the extraction of the core model parameters and estimates for the drain and source access resistances. In this work, data sets required for the compact model parameter extraction are obtained from the simulation of the previously described 10 nm, 7.5 nm and 5 nm UTB-SOI MOSFET. These data sets comprise of current-voltage characteristics from ideal devices simulation and devices with different sources of intrinsic parameter fluctuations individually or in combination. The selected MOSFET compact model must be capable of accurately reproducing the characteristics of the devices. In this work Berkeley BSIMSOI [35] which is an accurate and computationally efficient industry standard SOI MOSFET compact model has been chosen. BSIMSOI is a derivative of the industry-standard bulk MOSFET compact model BSIM3 [36] with SOI specific features including floating-body model, body-contact model and self-heating model. However, because of the chosen UTB-SOI architecture, it is safe to initially focus on extraction of basic MOSFET parameters as UTB-SOI structure is less affected by history effects, unlike its PD-SOI [37] counterpart. However, UTB-SOI MOSFETs are still susceptible to the local thermal heating generated in the channel because of the low thermal conductivity of the buried oxide. Extracting model parameters without considering ‘self heating’ will overestimate circuit speed in SPICE simulation. However, under dynamic operation conditions (e.g. digital circuits), the self-heating effect is generally insignificant, since the average power consumption per device is low and its switching time, is much shorter than the thermal time constant [38,39]. A small difference between 3 to 6 percent delay for inverter circuit has been observed [39]. Compact models used in circuit simulation comprise of equations with associated parameters that need to be determined using parameter extraction procedures. Without a good parameter-extraction strategy a compact model is not complete and useful. Due to the device physics based nature of BSIMSOI, extraction is not merely a curve fitting process compared to some of the earlier generation SPICE compact models. Parameter extraction routes must be chosen carefully to prevent unphysical MOSFET device parameter identification and to capture completely the behaviour of the DC

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current characteristic observed at the device-level modelling stage. In general, the applicability of DC current-voltage characteristics to characterize device mismatch introduced by intrinsic parameter fluctuations is widely accepted [40]. The compact model parameter extraction was carried out using AuroraTM[41], a general purpose optimisation program for fitting SPICE compact models such as BSIMSOI to device electrical data. The program fits a model to a set of data points by adjusting one or more parameters of the model. The complete set of optimisation steps constitutes the parameter extraction strategy. Not only the extraction steps but also their order is very important. The accuracy of the parameter extraction procedure is limited only by the accuracy of the model and the correct choice of parameters. The parameters are extracted by minimizing the root mean square (RMS) error between each point of data and the corresponding compact model value as defined in (2).

RMS = ∆I0 + ... + ∆In

(2)

The BSIMSOI compact model has been developed for deterministic (not statistical) device operating prnciples and does not explicitly include effects associated with intrinsic parameter fluctuations. For example, in a deterministic model, for two devices with the same dimensions, identical process and transport parameters give rise to identical device characteristics. In reality they will have different characteristics due to different sources of IPF that affect their electrical behavior. Although, the BSIMSOI compact model does not explicitly consider intrinsic parameter fluctuation effects, it has a number of empirical parameters introduced to model process variation conditions. It has been observed that, although a large number of compact model parameters are needed to accurately model MOSFET behaviour at circuit level, process fluctuations influence only a handful of parameters [42]. Therefore, a carefully chosen subset of parameters can be used to model the fluctuation in UTB-SOI MOSFET characteristics introduced by random discrete dopants, body thickness variations and gate line edge roughness. Figure 13 illustrates the basic idea of the two-stage statistical parameter extraction strategy developed in this work. In the first parameter extraction stage, a number of key BSIMSOI parameters are extracted from the ID-VG and ID-VD characteristics of an ideal UTB-SOI MOSFETs. The ideal devices have continuously doped source/drain regions, uniform body thickness and straight gate line edge. Therefore only one extraction procedure is required for a particular UTB-SOI MOSFETs generation of interest.

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Figure 13. Flowchart of a two-stage statistical compact model parameter extraction methodology.

The proposed extraction strategy accurately fits simulation data with RMS error less than two percent for the ideal 10 nm, 7.5 nm and 5 nm channel length UTB-SOI MOSFETs. The good overall agreement between the ideal device simulation results and the extracted BSIMSOI model parameters is illustrated in figure 14. The quality of IG-VG fits for the 10 nm, 7.5 nm and 5 nm devices is shown in figure 14 (a), (b) and (c) respectively while ID-VD fit quality is illustrated in figure 14 (d), (e) and (f ) respectively. Parameters which are insensitive to intrinsic fluctuations are fixed after this parameter extraction phase while a few BSIMSOI parameters are selected for extraction in the second-stage, to represent the variations in MOSFET characteristics due to intrinsic parameter fluctuations.

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Figure 14. Quality of BSIMSOI extraction compared to ideal device simulation for equal body characteristics of uniformly doped 10 nm, 7.5 nm and 5 nm channel length UTB-SOI MOSFETs.

The extracted parameters are then grouped into two parts. Parameters which are considered insensitive to intrinsic fluctuations are fixed after the first stage while several BSIMSOI parameters are selected to represent the impact of different sources of intrinsic parameter fluctuations in the second statistical extraction stage. The stochastic nature of mismatch caused by IPF makes it necessary to use a large sample of electrical characteristics in order to have high confidence in the statistical circuit simulation. The data sets required for the statistical compact model extraction are from the simulations of 200 macroscopically identical, but microscopically different 10 nm, 7.5 nm and 5 nm channel length UTB-SOI MOSFETs. Using the

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extracted model parameters from the ideal device as base parameters, seven parameters are re-extracted using only IG-VG characteristics during the statistical extraction strategy. This data and parameter selection is based on previous findings that the impact of IPF characteristics can be accurately captured in compact models from IG-VG characteristics only [40, 43]. This approach reduces the computational burden of the 3D device simulation, making the simulation of ID-VD characteristics unnecessary. The focus of the statistical extraction strategy is on adjusting drain saturation current and threshold voltage because they play a dominant role in the simulation of digital circuits [43, 44]. To assess the accuracy of the device model and the statistical parameter extraction strategy, the IG-VG RMS relative percentage error is calculated between atomistic simulation data and the corresponding BSIMSOI results. We compare the average and standard deviation of IG-VG RMS percentages error from the statistical extraction strategy for the 10 nm, 7.5 nm and 5 nm channel length UTB-SOI MOSFET including each source of IPF individually or in combination. The mean RMS errors of the statistical compact model extraction from all channel lengths are less than two percent for each source of IPF for both extraction step. The IG-VG RMS errors have a very narrow normal distribution for the ensembles of 200 microscopically different transistors of each channel length and for each source of IPF. These results clearly demonstrate that the choice of seven key parameters adequately describes the effect of IPF over the whole range of device operation for all samples of devices with channel length of 10 nm, 7.5 nm and 5 nm. It is worth mentioning that the RMS error for the whole sample of transistors with a particular channel length depends on the accuracy of the ideal device parameter extraction and could be further improved by improving the extraction strategy. Figure 15 shows the histograms of the selected BSIMSOI parameters from the statistical extraction of the 10 nm channel length UTB-SOI MOSFET with body thickness variations. Each parameter has a different distribution with distinct characteristics. Although BSIMSOI is developed with a physical foundation, it still relies on smoothing functions, which are not physical. Therefore, acquiring a set of parameters which are uncorrelated is almost impossible. Figure 16 illustrates scatter plots of the selected BSIMSOI parameters from the same device as above. The figure clearly illustrates that there are correlations between the selected BSIMSOI empirical process parameters chosen to reflect the body thickness fluctuation effects.

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Figure 15. Distributions of selected BSIMSOI parameters from statistical extraction of 10 nm channel length UTB-SOI MOSFET with body thickness variations from an ensemble of 200 devices.

The statistical extraction strategy introduced in this work captures accurately the IPF information from actual devices in compact model libraries. This has implications for statistical circuit design. Rather than varying unphysical parameters or their corresponding ambiguous principal components, it is now possible to perform statistical circuit design using real devices. The compact model libraries built from ensembles of 200 microscopically different devices using the statistical extraction strategy described are then used in circuit-level simulations. There are four different libraries for each of the 10 nm, 7.5 nm and 5 nm channel length UTB-SOI MOSFETs corresponding to each source of IPF investigated. Devices in a statistical circuit simulation can be randomly selected from the library of a corresponding channel length device and source of IPF, which guarantees that the devices used in circuit simulations correctly represent realistic intrinsic parameter fluctuation effects.

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Figure 16. Scatter plots of selected BSIMSOI parameters from statistical extraction of 10 nm channel length UTB-SOI MOSFET with body thickness variations from an ensemble of 200 devices.

4. Impact of IPV on SRAM

Intrinsic parameter fluctuations (IPF), introduced as a result of the underlying discreteness of charge and matter in ultra-small devices, will be one of the major challenges for the semiconductor industry in the next decade [1]. In most cases, the transistors used in SRAM cells are among the minimal size for each particular technology generation, and thus are critically sensitive to intrinsic parameter fluctuations [31; 45]. These intrinsic variations cannot be eliminated by tightening the manufacturing process control, and will have an increasing impact on SRAM performance and yield [12]. Failures due to the cumulative impact of various sources of IPF in an SRAM cells, are principally caused by mismatch between the

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neighbouring active transistors in the cell. Mismatch in the characteristics of different transistors result in different types of failure event that includes destructive read or unsuccessful write, an increase in access time of the cell resulting in a violation of delay requirements, and destruction of the cell content in standby mode [30]. Increased failure rates in the cells of a memory array will reduce the yield of the associated chip. 4.1. SIMULATED SRAM SETUP

This work is primarily concerned with high-performance microprocessor cache, a market that has been totally dominated by the standard 6-transistor (6T) SRAM. With the projected growth in the percentage of chip area devoted to cache [46] in high-performance microprocessors, the impact of IPF on SRAM circuitry must be considered during the design cycle. A schematic of the 6T SRAM cells simulated in this work is shown in figure 17. The storage nodes (node A and node B) consists of two load PMOS transistors (M1 and M3) and two driver NMOS transistors (M2 and M4) with two access NMOS transistors (M5 and M6). The specifications for supply voltage are obtained from the ITRS [1]. A supply voltage of 800 mV is used for the 10 nm transistor and 700 mV for both the 7.5 nm and 5 nm transistors. In order to study the statistical characteristics of SRAM cells subject to the intrinsic parameter fluctuations, a total of 200 unique SRAM cells are simulated in this work for each statistical simulation experiment. SRAM cells corresponding to 10 nm, 7.5 nm and 5 nm channel length UTB-SOI MOSFETs are constructed using randomly selected devices from the compact models library prepared

Figure 17. Circuit schematic of the 6-transistor SRAM.

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earlier. Each compact model library comprises of 200 “atomistic” devices. So far in this work, only NMOS devices have been considered. In these simulations, PMOS devices are assumed to have an identical statistical distribution as a result of intrinsic parameter fluctuations, with a mobility half that of NMOS devices. The impact of intrinsic parameter fluctuations on SRAM yield and performance is a strong function of the cell ratio, r defined as the ratio of the driver transistors (M2 and M4) width/length (W/L) to the access transistors (M5 and M6) W/L (3).

r = (W d /Ld ) /(W a /La )

(3)

It will be shown that the probability of failure for any particular memory cell can be minimized by an optimal choice of r, achieved by appropriate sizing of these transistors. However, any such optimization has an impact on the overall silicon area, the static leakage and eventually the static power dissipation of the SRAM array. The impact of intrinsic parameter fluctuations on UTB-SOI devices is quantified by varying the SRAM cell ratio, r and measuring the stability and performance of the SRAM during read and write operations. The cell ratio is altered by increasing the driver transistor width, while keeping the other transistor dimensions constant. High W/L ratio devices are often used in design, particularly when high drive currents are required. In this work, the load and access transistors have a W/L ratio of one while the driver transistor W/L ratio is determined by the choice of r. Larger W/L ratio devices are built by connecting in parallel randomly selected transistors from the compact models library, as the library contains only device with W/L=1. Neglecting edge effects, this technique correctly captures the statistics of wider devices. To clearly illustrate the impact of intrinsic parameter fluctuations on SRAM cells, the peripheral read and write circuitry is omitted from the circuit simulation and ideal complementary signals are directly applied to the bit-lines. SRAMs are frequently placed near active logic circuits where the temperature of the die is high, and subthreshold leakage current will dominate cell leakage [47]. To distinguish IPF effects from temperature effects the 6T SRAM circuit was simulated at 300 K. 4.2. CELL STABILITY

In SRAM design, the stability of the cell is a critical factor in determining its sensitivity to process tolerances and operating conditions. Thus, is a critical factor in obtaining the desired yield of a chip. Each 6T SRAM cell contains two sets of matched inverters, as shown in figure 17 and for a

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given cell design, higher threshold voltage for each cell transistor improves cell stability. Any mismatch between the transistors caused by intrinsic parameter fluctuations between the pair degrades the stability of the whole cell. Reading information from an SRAM cell should be non-destructive. After the read operation, the logic state of the cell must remain unaltered. The 6T SRAM cell is most unstable at the onset of the read access. The read operation begins with the word-line being raised to the power supply voltage, VDD and bit-lines initially precharged high. This causes the logic low node within the cell to rise due to the voltage division between driver transistors and access transistors. If the cell design allows the nominal value of this node voltage to come close to the nominal threshold voltage of the driver transistors, IPF caused by process variations may result in the node voltage passing the critical point where the state of the cell is flipped. The Static Noise Margin (SNM) [48], which is the minimum DC noise voltage needed to flip the cell state, is often used to measure the cell stability. SNM is a function of threshold voltage and depends on the relative strength of the two cross-coupled inverters in the cell. A large threshold voltage improves SNM and the cell state could only be flipped by large DC noise. However, as the electrical parameters of the transistors in these inverters are prone to intrinsic fluctuations, the SNM varies from memory cell to memory cell. An SRAM cell can be represented by a flip-flop comprising of two inverters as shown in figure 18(a). SNM is simulated by using two voltage sources (Vout1 and V out2) which are placed inside the memory cell to obtain the static transfer curve of each inverter. The static noise margin can be obtained graphically by drawing and mirroring the inverter characteristics and fitting the maximum possible square between the two curves as depicted in figure 18(b). For well-matched transistors, the curves are symmetrical and the two SNMs are the same. However, when intrinsic parameter fluctuations are included, the two maximum squares are different

Figure 18. (a) SRAM cell represented by two inverters with static noise voltage sources included. (b) Graphical representation of SNM.

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and the smaller of the two is defined as the SNM. Increasing cell ratio [49] and other circuit techniques such as dynamic-threshold SRAM [50] that push both of the static transfer curves away from each other, will improve cell SNM, but will never eliminate the impact of IPF altogether. Static transfer curves for an ensemble of 200 distinct SRAM cells with a cell ratio of one, considering transistor parameter variations resulting from RDD, BTV and LER, are shown in figure 19. The fluctuations of the static transfer curves increase as the corresponding UTB-SOI MOSFETs are scaled from the 10 nm to the 5 nm channel length. Detailed quantitative analysis of the results will be presented below, but even from the groups of figure 19 it can clearly be seen that IPF will become a major source of SRAM cell instability near the ultimate scaling limits. To better visualize and compare the overall effects of different sources of IPF on the stability of 6T SRAM cells, SNM distributions for SRAM cells with 10 nm, 7.5 nm and 5 nm transistors are illustrated in figure 20. For all three sets of devices, the distribution of the SNM is close to a normal distribution, with an increasing standard deviation with channel length reduction. As noted above, the SNM fluctuations due to RDD shown in the first row are the worst for all UTB-SOI MOSFET channel lengths. RDD

Figure 19. Static transfer curves of 200 distinct SRAM cells with a cell ratio of one. The columns represent UTB-SOI MOSFET channel lengths while the rows indicate the corresponding sources of intrinsic parameter fluctuations.

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Figure 20. SNM distributions due to different sources of IPF in UTB-SOI based SRAM cells with a cell ratio of one. The columns represent UTB-SOI MOSFETs channel lengths while the rows are the corresponding sources of intrinsic parameter fluctuations.

also causes a considerable proportion of devices at the 7.5 nm and 5 nm channel length fail to operate even under otherwise ideal conditions. RDD caused a threshold voltage standard deviation, σVT of 25 mV and 75 mV for the 7.5 nm and 5 nm UTB-SOI MOSFET. As SNM is a function of threshold voltage, noise margin will be eliminated if SRAM cell are built from transistors with extreme threshold voltage lowering. Approximately 10 percent failure rate at 7.5 nm channel length and a 13 percent failure rate at 5 nm channel length were observed. The channel length dependence of SNM standard deviations, due to different sources of IPF for different cell ratio configuration is illustrated in figure 21. For all case of cell ratio configuration, SRAM cells built from transistors with the presence of all IPF source have the largest standard deviation. In the presence of all IPF sources, SRAM cells with minimum cell ratio (r=1), have a standard deviation of 14 mV for the 10 nm channel length device, increasing to 34 mV for the 5 nm device. The impact of each individual source of IPF on the SNM standard deviation is depicted in figure 21 (a) to figure 21 (c). SRAM cells built from transistors with the presence of BTV and LER have a standard deviation of less than 10 mV. For all case of cell ratio configuration, LER dominates at longer channel length. However, there is a crossover below 7.5 nm channel length.

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Figure 21. Standard deviation of SNM due to different sources of IPF in SRAM cells that utilises 10 nm, 7.5 nm and 5 nm UTB-SOI MOSFETs, with SRAM cell ratios of (a) 1/1, (b) 2/1 and (c) 3/1.

To facilitate the comparison of standard deviation between different channel lengths, the normalised standard deviation (σ/µ) of the SNM is calculated. Figure 22 illustrates the normalised standard deviation of the SNM due to different sources of IPF as a function of UTB-SOI MOSFETs channel length for SRAM cells with different cell ratios. The magnitude of the fluctuations increases as the UTB-SOI MOSFETs are scaled to shorter channel lengths. Although SNM fluctuations remain well under control for the 10 nm channel length device, at minimum cell ratio, primarily as a result of increasing variation due to RDD the normalised SNM standard deviation for 7.5 nm and 5 nm channel length devices are considerably degraded. Compared to combined sources of IPF, the steep degradation of the average SNM of RDD causes a rapid growth and crossover of the SNM

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normalised standard deviation at minimum cell ratio. BTV and LER result in less than 15 percent normalised standard deviation for the 10 nm and the 7.5 nm devices but increases to more than 20 percent for the the 5 nm SRAM. The magnitude of fluctuations for transistors with combined sources of IPF (RDD+BTV+LER) increases from approximately 10 percent at 10 nm channel length to more than 31 percent at 5 nm channel length, for SRAMs with a cell ratio of one despite the effect of BTV and LER continuing to be well controlled for the 7.5 nm device.

Figure 22. Normalised standard deviation of SNM due to different sources of IPF in SRAM cells that utilises 10 nm, 7.5 nm and 5 nm UTB-SOI MOSFETs, with SRAM cell ratios of (a) 1/1, (b) 2/1 and (c) 3/1.

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The negative impact of the IPF increase with the transistor scaling can be compensated by increasing the SRAM cell ratio. Increasing the cell ratio not only improves the average SNM as discussed earlier, but also reduces the magnitude of its fluctuations which is partly reflected by the reduced normalized standard deviation. The increase of the cell ratio delivers between 10 and 30 percent reduction of the SNM fluctuation for 7.5 nm and 5 nm UTB-SOI MOSFETs for different sources of IPF. However increasing cell ratio delivers less improvement of the SNM with the reduction of the channel length. For the 5 nm transistors, the need to increase cell ratio will reduce the benefit of the device scaling compared to 10 nm and 7.5 nm channel length transistors. As the number of transistors per chip continues to increase, SNM fluctuations must be small enough to satisfy future yield requirements. For example, a 4 MB (32 Mbit) cache, including error correction, usually contains almost 38 million memory cells and requires a tolerance of 5.44σ to have only one cell failure per cache [45]. A common technique when considering yield is to apply the six-sigma (6σ) approach, adopted by Motorola [26]. Devices operating outside 6σ from the mean value (µ-6σ) will occur on average only 3.4 times per million devices. Calculated values of µ6σ from ensembles of 200 distinct SRAM cells built from 10 nm and 7.5 nm UTB-SOI MOSFETs are plotted in figure 23 as a function of cell ratio. It is clear that an increase in cell ratio leads to an improvement in µ-6σ which implies improved SRAM cell yield. As a guideline for SRAM, µ-6σ should exceed 4 percent of the supply voltage to achieve 90 percent yield on 1 Mbit

Figure 23. µ-6σ of Static Noise Margin (SNM) as a function of cell ratio for 10 nm, and 7.5 nm UTB-SOI MOSFET SRAMs. Lines: µ-6σ>32 mV for 10 nm and >28 mV for 7.5 nm.

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SRAMs [51]. This criteria is satisfied for a cell ratio of one for 10 nm channel length devices for any individual source of IPF. However, if the combination of sources of IPF is taken into account, the 10 nm channel length device will require at least a cell ratio of two. The 7.5 nm channel length UTB-SOI MOSFET SRAM requires a cell ratio of two if only BTV or LER are considered in isolation and a cell ratio of three for either RDD, or a combination of all sources of IPF. SRAM cells based on 5 nm channel length devices could not fulfill the required guideline even at higher cell ratios. Resorting to higher cell ratios only increases cell area, negating the improved storage density that is one of the main reasons for scaling devices to shorter channel length. This implies that 6T SRAMs will not gain the full benefits from further UTB MOSFET scaling to channel lengths smaller than 10 nm. To show the practical advantages of UTB-SOI MOSFET based SRAM cells with respect to stability in the presence of IPF, a comparison is made between 10 nm channel length UTB-SOI MOSFET memory cells and cell structured from well calibrated 35 nm bulk devices [32]. The static transfer curves for an ensemble of 200 SRAM cells built from 10 nm channel length UTB MOSFETs, considering the combination of IPF sources (RDD+BTV+LER) is shown in figure 24(a). The opening of the butterfly

Figure 24. Static transfer characteristics of 200 distinct SRAM cells utilising (a) 10 nm UTB-SOI MOSFETs and (b) 35 nm bulk MOSFETs.

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transfer curves for 10 nm UTB-SOI can be clearly compared to the results obtained for SRAM constructed from 35 nm conventional bulk MOSFETs shown in figure 24(b). The worse bulk MOSFET performance for an identical cell ratio configuration is due to larger fluctuations resulting from the random discrete dopants in the channels of the bulk devices. A recent experimental study [12] has confirmed the adverse effect of random doping fluctuations on the yield and stability of SRAM cells. Normalised standard deviation of the SNM as a function of cell ratio for SRAM constructed from UTB-SOI MOSFETs and bulk devices is depicted in figure 25. The UTB-SOI MOSFET cells are simulated for cell ratios from r=1 to r=3. Bulk MOSFET cells cannot operate with a cell ratio of one and are simulated with cell ratios from r=2 to r=4. The trend of increased SNM stability is observed for 35 nm bulk MOSFET based memory cells as the cell ratio is increased. However, SRAM cells based on 35 nm bulk MOSFETs are more sensitive to the random doping effects compared to 10 nm UTB-SOI MOSFETs with the combination of all IPF sources. The calculated µ-6σ dependence on cell ratio is compared in figure 26 from SRAM cells utilising 10 nm UTB-SOI and 35 nm bulk MOSFET. It is clear that for both devices the increase of the cell ratio leads to improvement in µ-6σ which implies that a larger fraction of SRAM cells for each geometry achieve stability threshold. A memory cell based on 35 nm bulk MOSFETs requires a cell ratio of at least three, considering only intrinsic fluctuations caused by discrete random dopants. According to figure 26, from the SNM point of view, 10 nm UTB-SOI MOSFET SRAM

Figure 25. Normalised standard deviation of SNM as a function of cell ratio for 10 nm UTBSOI MOSFET based SRAM due to different sources of IPF. Equivalent results for SRAM constructed from 35 nm bulk MOSFETs are also shown. The bulk devices are only subjected to random discrete dopants.

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Figure 26. µ-6σ for SNM as a function of cell ratio for SRAM constructed from 10n m UTB-SOI MOSFETs and 35 nm bulk MOSFETs with different sources of intrinsic parameter fluctuations. Lines: µ-6σ >32 mV for 10 nm UTB-SOI MOSFETs and >48 mV for 35 nm bulk MOSFETs.

cells are more stable even though operated at 80 percent of the supply voltage of 35 nm bulk MOSFET based SRAM. 4.3. CELL PERFORMANCE

The performance of an SRAM array is determined by the read and write operation of its slowest cell. A read operation is performed by holding both bit-lines high and selecting the desired word-line. Once the word-line is enabled, data in the cell will pull one of the bit-lines low through the access transistor (M5, M6) and driver transistor (M2, M4). The differential signal on the bit-lines is detected, amplified and read out through the output buffer [52]. One important performance parameter is the read access time which represents the propagation delay from the time when the address is presented at the memory chip until the time when data become available at the memory output. In this work, in order to obtain the relative read operation speed, the discharge time for the bit-line is estimated from the simulation of an ensemble of 200 6T SRAM cells for each of the investigated UTB-SOI MOSFETs. The read discharge time (RDT) is a major component in determining array access time, and the overall chip speed is fundamentally limited by the cell discharge time. The RDT will be affected by the bit-line capacitance which depends on both the architectural configuration of the memory array and the UTB-SOI MOSFETs choosen. However, in the following statistical circuit simulations a constant 0.05 pF bit-line

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capacitance is assumed. In order to secure a sufficient noise margin, the threshold for the sense amplifier is assumed to be half of the supply voltage. The read discharge time is defined by the bit-line voltage drop to the sense amplifier threshold after the access transistors are switched on as shown in figure 27. The histogram of the read discharge time distributions for different channel lengths of UTB-SOI MOSFETs with different sources of IPF are presented in figure 28. Each source of IPF has a different impact on the

Figure 27. A typical read discharge-time simulation waveforms. Both bit-lines are initially precharged at supply voltage and RDT is measured when bit-line voltage drop to VDD/2.

Figure 28. Read discharge time distributions for UTB-SOI MOSFET based SRAM cells with a cell ratio of one. The columns represent UTB-SOI MOSFET channel lengths while the rows are the corresponding sources of intrinsic parameter fluctuations.

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average read performance of the SRAM cells, but more importantly, IPF causes significant performance differences between the fastest and slowest SRAM cell accesses and may cause a violation of the delay requirements for reliable memory cell operation at a specific clock frequency. Under nominal conditions, the discharge time for each UTB-SOI MOSFET investigated improves between 17 and 25 percent with the increase of the cell ratio to two, and between 31 and 75 percent with the increase of the cell ratio to three considering all sources of IPF in combination. These results, together with the effects of each single source of fluctuations are illustrated in figure 29. Larger cell ratios reduce the cell pull down time due to increasing current drive from larger driver transistor, 1.8

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which will help to improve general read access performance. However it is also clear that IPF have a negative impact on SRAM cell read access time. From the three individual sources of IPF investigated in this work, RDD has the worst impact on read discharge time with performance degradation greater than the effect of any other single source of fluctuations. The normalised standard deviation illustrated in figure 30 shows that even though nominal speed improves due to larger cell ratios, there is no significant reduction in the variations of the read access between SRAM cells even at a cell ratio of three. The read performance difference for devices in the individual presence of BTV or LER is less than 5 percent for any UTB-SOI MOSFETs. RDD considered either solely or in combination with other IPF sources result in the worst variations in read discharge time 1.8

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of approximately 6 percent for the 10 nm transistors, raising to 24 percent for the 5 nm devices. 5. Conclusions

For all investigated UTB-SOI MOSFETs, the intrinsic parameter fluctuations are dominated by random discrete dopants in the source/drain region. However, the effects of body thickness variation and line edge roughness could not be disregarded. The specific design parameters of the scaled UTB-SOI MOSFET devices will determine which of these two sources of fluctuations will dominate in the future. The simulation results also demonstrate that fluctuations caused by failing to scale line edge roughness become more critical compared to the fluctuations induced by random discrete dopants. The simulation results indicate that the scaling of UTB-SOI MOSFET below 10 nm channel length will be extremely difficult from intrinsic parameter fluctuations point of views. As expected, random discrete dopants in the source/drain regions dominate the SRAM variability compared to other sources of intrinsic parameter fluctuations. The SNM of the simulated SRAM cells can be improved by increasing the cell ratio, r. The increase of the cell ratio also reduces the fluctuations of the SNM. However, the improvement is less pronounced at shorter channel lengths. Simulation result demonstrate that 10 nm UTB-SOI MOSFETs are more stable than 35 nm bulk MOSFET even though operated at 80 percent of the expected supply voltage. Intrinsic parameter fluctuations caused significant disparity in access performance between fastest and slowest SRAM cells which may cause violation of delay requirement for reliable memory cell operation. It is also anticipated that intrinsic parameter fluctuations will increase the overall leakage of cache memory contributing to an increase in static energy consumption.

References 1. 2. 3. 4.

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ELECTRON TRANSPORT IN SILICON-ON-INSULATOR NANODEVICES

F. GÁMIZ*, A. GODOY, C. SAMPEDRO Departamento de Electrónica y Tecnología de Computadores. Facultad de Ciencias. Universidad de Granada, 18071 Granada, SPAIN *

To whom the correspondence should be addressed. Francisco Gámiz; e-mail: [email protected]

Abstract. We have studied the electron transport properties of two sets of Silicon on Insulator (SOI) nanodevices: i) quantum-well based devices where carriers are quantized in one dimension (1D) and ii) quantum-wire based devices, where carriers are quantized in two dimensions (2D). In the first group, namely quantum-well based devices, the electron mobility dependence on the silicon thickness, Tw in double-gate SOI devices was compared with that in Single-Gate SOI structures. Thus, we determined the existence of a range of silicon layer thicknesses in which electron mobility in DGSOI inversion layers is significantly improved as compared to bulksilicon or SGSOI inversion layers, due to the volume inversion effect. We have also shown that electron mobility is greatly improved in strained Si/SiGe-OI devices, in comparison with unstrained SOI devices. We can conclude that strained-Si/SiGe-on-Insulator inversion layers efficiently combine the improved mobility of strained-Si/SiGe devices with the advantages offered by SOI devices. With regard to quantum-wire based devices, we have analyzed the phonon-limited mobility in silicon quantum wires by means of a one-particle Monte Carlo simulator. It has been observed that an increase of the phonon scattering produces a noticeable reduction of the electron mobility observed when the device dimensions are reduced. Therefore, we have observed that the transition from 2D to 1D electron gas produces a degradation of the electron transport properties.

Keywords: Electron transport, mobility, Monte Carlo, Silicon-on-Insulator, quantum well, quantum wires

1. Introduction

For many years, Silicon-on-Insulator (SOI) devices have been considered as a serious alternative for the fabrication of future integrated circuits (SIA, 303 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 303-322. © 2007 Springer.

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2005). Many reasons have contributed to this status, namely easy CMOS processing, excellent device scalability, tremendous cost/performance advantages over Si and Si/SiGe technologies, very good device and circuit performance, strong radiation tolerance, etc. (Colinge, 2004), (Cristoloveanu and Li, 1995), (Gamiz and Fischetti, 2001). Today, SOI technology is already incorporated in the semiconductor technology mainstream because of the many critical physical limitations of conventional silicon technology as device dimensions become ever smaller. For this reason, a lot of research has been carried out in recent years to try to foresee the actual properties of these devices. The goal of this work is to review our latest results into the study of electron transport properties in different SOI devices: i) In a first group we considered quantum well based devices. These devices consist of an ultrathin silicon layer sandwiched between two oxide layers. Both singlegate and double-gate devices have been considered. Electrons are quantized in the direction perpendicular to both Si/SiO2 interfaces, but they can move freely in the plane parallel to them. This confinement of the carriers in the direction perpendicular to the channel greatly modifys their behavior, and as a consequence, in addition to the advantages mentioned above, ultrathin SOI devices specifically present other benefits, as highlighted below. ii) Another advantage of SOI technology is the possibility of building non-conventional devices such as multiple-gate devices, and in particular FinFETs, Trigates, Pi and Omega-gate MOSFETs and Gate-all-around (GAA) devices (Colinge, 2004). When the dimensions are scaled down in these structures, carriers become confined not in only one dimension (1D) as in previous SOI structures, but in two dimensions (2D), moving freely in only one direction. Electron transport properties will be also modified by this confinement as we will show. The scheme of the paper is as follows. The first section is devoted to the study of quantum-well SOI structures. First of all, we calculate the spatial and energetic distribution of the carriers by self-consistently solving 1D Poisson and Schrödinger equations, and then the Boltzmann transport equation (BTE) is solved by the Monte Carlo method. Different structures have been studied and compared. In the second section we studied the electron transport in quantum-wire based SOI devices where the carriers are confined in two-dimensions. Therefore, we self-consistently solve the 2DPoisson and 2D-Schrödinger equations in devices with different geometric and electrical cross-sections, to study the space and energetic distribution of the carriers. Then a drift electric field is applied normal to the device quantization plane, and the BTE is solved again using a one-electron Monte Carlo simulator. Different scattering mechanisms are considered, and the electron mobility is evaluated as a function of the quantum-wire cross section size. Finally the main conclusions are drawn.

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2. Quantum-well SOI devices (1D-Confined states) 2.1. ELECTRON DISTRIBUTION QUANTUM EFFECTS

In these devices, an undoped silicon layer is sandwiched between two oxide layers. The maximum extension of the electrons in the direction perpendicular to both Si/SiO2 is limited by the silicon thickness which is comparable to the De Broglie wavelength of the carriers. As a consequence, to accurately evaluate the electron distribution in these structures we must self-consistently solve the 1D-Schrödinger and Poisson equations in the direction perpendicular to both Si/SiO2 interfaces. The actual band-bending through the whole structure and the finite height of the barrier at the Si/SiO2 interfaces have been considered. A simple non-parabolic band model for the silicon has been taken into account assuming α=0.5eV-1, α being the parameter of non-parabolicity (López-Villanueva et al., 1993). The reduction of the silicon film thickness sandwiched between the two oxide layers causes important effects on the electron distribution and on electron transport properties: 2.1.1. Subband modulation effect The size quantization in the (100) silicon inversion layer produces a redistribution of the carriers between the two subband ladders which arise from the split of the degeneracy of the six equivalent valleys of bulk silicon (Ando et al., 1982), (Gamiz et al., 1999a). In SOI inversion layers, the redistribution of the inversion electrons is more acute as the silicon layer shrinks and the following consequences are observed (Gamiz and Fischetti, 2001): 1. A reduction in the conduction effective mass of electrons in the inversion layer as Tw is reduced. A lower effective conduction mass means a greater electron velocity for the same drift field value, and thus a greater mobility (Gamiz et al., 1999b). The reduction of the conduction effective mass of electrons as the silicon layer thickness decreases can clearly be observed in Figure 1, where the average conduction effective mass versus the total electron concentration for different silicon layer thicknesses is shown. 2. A reduction of the intervalley scattering rate between non-equivalent valleys (f-scattering) due to the greater separation of the energy levels related to prime subbands with respect to the non-prime ones as the silicon film thickness is reduced. Both effects, 1 and 2, simultaneously contribute to an electron mobility increase.

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0.36 0.34 0.32 0.30 0.28 0

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Electron Concentration (cm-2) Figure 1. Average conduction effective mass versus the inversion charge concentration for different silicon layer thicknesses in a SGSOI inversion layer. (■ Tw=50nm, ▲ Tw=25nm, ●Tw=15nm, (solid)Tw=10nm, (dashed)Tw=5nm).

2.1.2. Phonon scattering increase Another important effect that appears in SOI-inversion layers as the silicon layer thickness is reduced is an increase in the phonon-scattering rate (Price, 1981). The electron confinement in ultrathin SOI-inversion layers is greater than in bulk-inversion layers (Gamiz and Fischetti, 2001), (Gamiz et al., 1999b). Thus, the uncertainty concerning the location of the electrons in the direction perpendicular to the interface is less in SOI samples than in bulk samples. In accordance with the uncertainty principle, there is a wider distribution of the electron momentum perpendicular to the interface. In other words, due to size quantization, the electron interface-directed momentum does not have a single value (as in 3-D electrons), but a distribution of likely values that expands as the silicon layer thickness is reduced. Taking into account the momentum conservation principle, there are more bulk phonons available that can assist in transitions between electron states, and therefore an increase in the phonon-scattering rate is expected. As a consequence, for the same inversion-charge concentration, the phonon-scattering rate is greater in thinner films than in thicker ones (since the confinement is greater), and therefore a mobility reduction can be expected (Gamiz and Fischetti, 2001). Points 2.1.1. and 2.1.2. above indicate that two opposing trends appear in electron mobility as the silicon layer thickness is reduced. However, the

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contribution of these two trends varies depending on the considered structure and on the temperature. It would be interesting to know which of these trends, if either, is dominant, and whether there is a critical silicon layer thickness at which a change in mobility behaviour is observed: in other words, if a change is produced in the trend of electron mobility as the silicon layer thickness is reduced. 2.2. ELECTRON MOBILITY

One of the key issues for further improvement of CMOS (Complementary Metal-Oxide-Semiconductor) technology is the enhancement of carrier mobility in the device channel (SIA, 2005). To study electron mobility behavior in ultrathin SOI inversion layers, we used a one-electron Monte Carlo simulator. Phonon and surface-roughness scattering have been taken into account in this work. In these structures, the silicon layer is usually left undoped, and, if in addition, the Si/SiO2 interfaces are of good quality (which is desirable) the interface charge concentration is also quite small and in consequence, Coulomb scattering is much less important than phonon and surface-roughness scattering, especially at intermediate and high inversion charge concentrations. We used bulk electron-phonon scattering models considering acoustic deformation potential scattering and intervalley scattering (between both equivalent and non-equivalent valleys) (Gamiz et al., 1998a), (Gamiz et al., 1998b). The coupling constants for the intervalley phonons and the acoustic deformation potential were the same as in bulk silicon inversion layers. If the scattering mechanisms related to the presence of the Si/SiO2 interface significantly affect the electron transport properties in bulk silicon inversion layers, one can easily understand that this effect should, at least a priori, be taken into account in those physical systems where electrons are simultaneously affected by two such Si-SiO2 interfaces. This is the case of the ultrathin SOI inversion layers studied here. We have recently shown that in ultrathin SOI inversion layers the presence of a second interface plays a very important role, both by modifying the surface roughness scattering rate due to the gate interface, and by itself providing a non-negligible scattering rate. In addition, we have shown that the usual surface roughness scattering model in bulk silicon inversion layers overestimates the effect of surface roughness scattering arising from one of the interfaces as a consequence of the presence of the other (Gamiz et al., 1999a), (Gamiz et al., 2001).

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Therefore, it was necessary to improve the surface roughness model in order to calculate the scattering rate due to both interfaces (which are assumed not to be correlated). By using this simulator, we were able to calculate electron mobility in SOI inversion layers for different silicon film thicknesses Tw. Our attention was focused on evaluating the stationary drift velocity and the low-field mobility. A comprehensive description of this simulator can be found elsewhere (Gamiz et al., 1999a), (Gamiz et al., 1998a), (Gamiz et al., 1998b). Various ultrathin SOI structures have been studied: single-gate SOI (SGSOI) devices, symmetrical double-gate SOI (DGSOI) devices, and strained Silicon-on-SiGe-on-insulator (Si/SiGeOI) devices. The behavior of electron mobility in these structures has been studied at different temperatures as the silicon film thickness is reduced. 2.2.1. Single-Gate Silicon-on-Insulator devices The first structure considered is the Single-Gate Silicon-on-Insulator device (SGSOI). This structure basically consists of an undoped silicon layer sandwiched between two oxide layers, the gate oxide and the buried oxide. A silicon substrate was assumed under the buried oxide and a P+ polysilicon gate was assumed as the control electrode. Different thicknesses of the silicon film, Tw, were considered. Figure 2 shows mobility curves versus the electron

2

Electron Mobility(cm/Vs)

1000 (20) (15)

800

(2.5)

(3.0)

600

(2.0) (8.0)

400 (5.0)

(10.0) (1.5)

200

0 11

10

12

13

10 10 Inversion Electrons(cm-2)

Figure 2. Electron mobility curves in a SGSOI MOSFET at room temperature versus the inversion electron concentration for different values of the silicon layer thickness (Tw). Phonon scattering and surface-roughness scattering due to both interfaces (Δm1=Δm2=0.1nm), (L1=L2=1.5nm) have been considered. The thickness of the silicon layer is expressed in nanometers between parentheses.

ELECTRON TRANSPORT IN SOI NANODEVICES

309

Electron Mobility(cm2/Vs)

1000

Δsr=0.1nm

SG SO I

900

T=300K 800 12

N inv=1x10 cm

700 600

12

-2

N inv=5x10 cm

-2

500 13

400

N inv=1x10 cm

-2

300

0

5

10

15

20

Silicon Thickness(nm) Figure 3. Evolution of electron mobility in a SGSOI MOSFET with the silicon layer thickness for different values of the inversion charge concentration at room temperature.

concentration for different values of silicon layer thicknesses at room temperature. Phonon-scattering and surface roughness scattering were taken into account. The following surface-roughness parameters were assumed: Δm1=Δm2=0.1nm, L1=L2=1.5nm, where Δmi and Li are the rms value and the autocovariance length of the roughness fluctuations, respectively. We have seen that the effect of surface roughness scattering is more acute at high inversion charge concentrations and in the thinnest samples. In the latter case, the effect of surface roughness scattering is noticeable even at very low transverse effective fields. There is more than one trend in the electron mobility as the silicon thickness is reduced, and this behavior strongly depends on the electron concentration. To see this more clearly, we studied the evolution of electron mobility with the silicon layer thickness for different values of the transverse effective field (Figure 3). Three regions can be distinguished: 1. For high silicon thickness values, electron mobility tends towards the mobility value in bulk inversion layers. 2. As Tw decreases, electron mobility gradually decreases until a minimum is reached around 5 nm. 3. Then it quickly increases until a maximum at 3 nm is reached, and then abruptly falls. This behavior is a direct consequence of the opposing trends mentioned in Section 2.1.

310

ELECTRON TRANSPORT IN SOI NANODEVICES

Normalized Mobility

1.5 SG SO I

1.0

0.5

T=25 K T=77 K T=300 K

0.0 0

5

10

15

20

Silicon Thickness(nm) Figure 4. Evolution of electron mobility in a SGSOI MOSFET with the silicon layer thickness for different temperatures. For the sake of comparison, the mobility has been normalized by the bulk value at each temperature.

We have also analysed the effect of the temperature on electron mobility. Figure 4 shows the evolution of electron mobility with the silicon layer thickness for different temperatures (25 K, 77 K, and 300 K). For the sake of comparison, mobility has been normalised by the bulk value in all the cases. In contrast to what happens at room temperature, at low temperatures the normalized mobility curves have an almost monotonic behavior: the maximum value observed at room temperature almost disappears and is displaced to higher values of Tw. This is a consequence of the balance between the two trends mentioned above. At low temperatures, and even for bulk silicon inversion layers, electrons massively populate non-prime subbands, where they have a conduction effective mass equal to mt. Therefore, at low temperatures, the subband modulation effect consequence of the silicon layer thickness reduction is less important than the increase in phonon scattering produced by the carrier confinement. 2.2.2. Double Gate Silicon-on-Insulator Devices The second structure studied is the Double-Gate Silicon-on-Insulator (DGSOI) MOSFET. This device consists of an undoped (100)-silicon film sandwiched between two oxide layers. The oxide thickness was taken as 1 nm in both cases. Polycrystalline Si (poly-Si) gates were assumed as front and back electrodes. The structure is assumed to work under symmetrical operation conditions. Each gate electrode (front and back gate) generates an

ELECTRON TRANSPORT IN SOI NANODEVICES

311

inversion region near the Si-SiO2 interfaces if an appropriate bias is applied. Thus, we have two MOSFETs sharing substrate, source and drain. However, the outstanding feature of these structures lies in the concept of volume inversion, introduced by Balestra et al. (Balestra et al., 1987). If the Si film is thicker than the sum of the depletion regions induced by the two gates, no interaction is produced between the two inversion layers, and the operation of this device is similar to that of two conventional MOSFETs connected in parallel. However, if the Si thickness is reduced, the whole silicon film is depleted and an important interaction appears between the two potential wells. In such conditions the inversion layer is formed not only at the top and bottom of the silicon slab (i.e., near the two siliconoxide interfaces), but throughout the entire silicon film thickness. The device is then said to operate in ‘volume inversion’, i.e., carriers are no longer confined at one interface, but distributed throughout the entire silicon volume. We have calculated mobility curves in DGSOI structures for different thicknesses of the silicon slab taking into account phononscattering and the effect of the surface-roughness scattering of both interfaces. Once more, silicon is left undoped, and therefore Coulomb scattering can be considered negligible. Figure 5 shows the evolution of electron mobility with the silicon layer thickness for different values of the inversion electron concentration Ninv is evaluated integrating the electron concentration from the Si-SiO2 interface to the middle of the silicon slab). Note that for higher inversion charge concentrations there is a region of Tw values where electron mobility is higher than the bulk mobility, as a consequence of volume inversion. Δsr=0.1nm

900

T=300K

2

Electron Mobility (cm /Vs)

1000

800

12

Ninv=1x10 cm

-2

700 12

Ninv=5x10 cm

600

-2

500 13

400

Ninv=1x10 cm

D G SO I

-2

300

0

5

10

15

20

Silicon Thickness(nm) Figure 5. Evolution of the electron mobility in a DGSOI MOSFET with the silicon layer thickness for different values of the inversion charge concentration at room temperature.

312

ELECTRON TRANSPORT IN SOI NANODEVICES

Electron Mobility(cm2/Vs)

1000

SG SO I D G SO I

900

Δsr=0.1 nm

800 700 600 500 400

12

Ninv=5x10 cm

-2

300

0

5

10

15

20

Silicon Thickness (nm) Figure 6. Comparison of electron mobility for SG-SOI and DG-SOI MOSFETs at room temperature. Only phonon and surface roughness scattering (Δm1=Δm2=0.1nm, L1=L2=1.5nm) have been considered.

D G SO I

Normalized Mobility

2.0

1.5

1.0

25 K 77 K 300 K

0.5 12

Ninv=5x10 cm 0.0 0

5

10

15

-2

20

Silicon Thickness(nm) Figure 7. Evolution of electron mobility in a SGSOI MOSFET with the silicon layer thickness for different temperatures. For the sake of comparison, the mobility has been normalized by the bulk value at each temperature.

Another important consequence of volume inversion is the fact that electron mobility increases for a given thickness in the range 6-7 nm as inversion charge concentration is increased. Out of this Tw range (Tw>6-7nm and Tw<6-7nm), the mobility behavior is the opposite, that is to say, the higher the inversion charge concentration, the lower the mobility; as happens

ELECTRON TRANSPORT IN SOI NANODEVICES

313

in SGSOI devices and seen in Figure 3. To illustrate the effect of volume inversion more clearly, Figure 6 compares the evolution of electron mobility with the silicon thickness Tw for a SGSOI (solid line) and for a DGSOI (dashed line) inversion layer. In the region 5nm-20nm, electron mobility in the DGSOI sample is much higher than that in the SGSOI inversion layer. We also studied the effect of the temperature. Figure 7 shows the evolution of electron mobility in a DGSOI inversion layer for different temperatures. For the sake of comparison, mobility values have been normalized by the bulk mobility value at each temperature. The inversion charge concentration was considered to be Ninv=5× 1012cm-2 in the three curves. In the case of SGSOI devices, decreasing the temperature does not substantially increase the mobility compared to the bulk value (Figure 4). However, Figure 7 shows that, due to volume inversion, the mobility in DGSOI devices is almost twice the bulk value in the range 5nm-15nm at low temperatures. 2.2.3. Strained Si/SiGe-on-Insulator devices Both theoretical and experimental studies have shown spectacular electron mobility enhancements when silicon is grown pseudomorphically on relaxed Si1-xGex (Roldán et al., 1997). The combination of a lower effective mass and reduced intervalley scattering gives rise to higher electron mobility. In spite of these important advantages, strained Si/Si1-xGex CMOS technology still suffers from some of the limitations of standard silicon CMOS technology for sub-0.1μm applications. As we have just seen, another candidate for sub-0.1μm devices is the Silicon-on-Insulator (SOI) structure, due to the advantages of SOI devices compared to their conventional silicon counterparts. In contrast to strained-Si/SiGe technology, SOI technology is fully compatible with existing standard silicon fabrication facilities and, a priori, CMOS circuit designs could be translated to SOI technology without much difficulty. One may wonder whether it would be possible to combine the two structures (strained silicon inversion layers and SOI inversion layers) to enjoy the advantages of both and at the same time, overcome each ones deficiencies. From the point of view of technology the answer is affirmative. Recent studies have reported the feasibility of the fabrication of SiGe-based SOI substrates by separation-by-implanted-oxygen (SIMOX) techniques (Fukatsu et al., 1998), (Ishikawa et al., 1999). Fabrication of high-quality SiGe layers with a thickness of less than 10nm on SiO2 has been demonstrated (Fukatsu et al., 1998). Using these structures as a starting point, both n- and p-channel strained-SOI MOSFETs have been fabricated and successfully operated, showing very high electron and hole mobilities with a Germanium mole fraction as low as 0.1 (Mizuno et al., 1999), (Mizuno et al., 2000). Other techniques such as solid-phase epitaxy (Yeo et al., 2000) have also shown the feasibility of fabricating Si/SiGe structures

314

ELECTRON TRANSPORT IN SOI NANODEVICES

on insulator substrate. We have studied the electron transport properties in strained-Si/Si1-xGex On Insulator (SiGeOI) structures by Monte Carlo simulation, taking a SiGe-OI substrate as a starting point, and using an undoped ultrathin strained-silicon layer pseudomorphically grown on the SiGe layer. The thickness of the strained silicon layer was assumed to be, in all cases, less than that of the relaxed SiGe layer. Electron quantization in the inversion layer was properly taken into account by self-consistently solving the Poisson and Schrödinger equations. The effect of strain in the silicon layer is included only in the band structure as the valley splitting energy ΔE=0.67x (x being the Germanium mole fraction), assuming that the strain does not modify the shape of the valleys. Changes in non-parabolicity with strain have been neglected as second-order effects. The effective mass of the electron is, as usual, assumed to be the same as in unstrained silicon and only phonon scattering has been taken into account. The first result obtained is an important increase in electron mobility, in agreement with experimental observervation. Figure 8 shows curves of phonon-limited mobility versus electron concentration, for a strained-SOI inversion layer for different germanium mole fractions (symbols). In all cases, both the relaxed-SiGe layer and the strained silicon layer were assumed to be 5nm-thick. For the sake of comparison, the electron mobility for unstrained SOI layers with different silicon layer thicknesses is also shown (no symbols). Figure 8 also shows a mobility curve corresponding to a strained-Si/SiGe bulk inversion layer (no buried oxide). The following facts can be observed from the comparison of the curves of Figure 8: 1. The strained-SOI structure obtains a higher electron mobility than that provided by unstrained SOI samples. This increase is estimated as being 69% for x=0.1, 118% for x=0.15 and 172% for x=0.3 at Eeff=1×105V/cm. For stronger electric fields, although the mobility increase is reduced for the high germanium mole fraction, it is still very significant: 66% for x=0.1 and 73% for x=0.15 and 83% for x=0.3 at Eeff=1×106V/cm. This behavior is explained in terms of the combination of the low conduction effective mass and the reduced intervalley scattering rate produced by the strain in the silicon film. A higher mobility increase than has been experimentally reported (Mizuno et al., 2000) is obtained in strained-SOI MOSFETs when higher Ge mole fractions are used and when the technological limits (related to non-ideality of interfaces) are suppressed. 2. If we compare electron mobility for strained-SOI silicon inversion layers (Fig. 8 solid squares) with the corresponding mobility for bulk strained Si-SiGe inversion layers (Fig. 8 open squares), we observe a slight degradation at low transverse effective fields in the mobility curve

315

1800

2

Phonon-limited Mobility (cm /Vs)

ELECTRON TRANSPORT IN SOI NANODEVICES

1600 1400 1200 1000 800 600 400

11

10

12

10

13

10

-2

Inversion Electrons (cm ) Figure 8. Evolution of electron mobility in a SGSOI MOSFET with the silicon layer thickness at different temperatures. For the sake of comparison, the mobility has been normalized by the bulk value at each temperature.

corresponding to the strained Si-SiGeOI sample as a consequence of a greater confinement of electrons, which produces a phonon scattering increase (Gamiz et al., 1998a). 3. Quantum wire SOI devices (2D-Confined states) 3.1. ELECTRON DISTRIBUTION QUANTUM EFFECTS

Multiple-gates in FETs provide good electrostatic control of the channel and therefore offer the possibility of a greater reduction of the channel length compared to traditional bulk MOSFETs. It has been demonstrated that for DGSOI transistors operating correctly, it is necessary to set the silicon thickness Tw to be lower than half the channel length Lch/2. The use of several gates can relax this condition without degradation of the device performance. Therefore, since the characteristic dimensions for the next node generations is well below 100nm, the silicon fin cross-section will reach the nanometer scale, thus confining the carriers in the two directions perpendicular to that of the transport. As a consequence, the 2D electron gas is transformed in a 1D one. The density of states experiences an important transformation due to their different energy dependence. Under these circumstances, a change of fundamental electrical parameters such as the threshold voltage (Majima et al., 2000) has been experimentally observed.

316

ELECTRON TRANSPORT IN SOI NANODEVICES

However, there are few results concerning the transport properties in silicon nanowires. In order to study the electrostatic behavior of these devices, we have developed an iterative method for obtaining self-consistent solutions to the coupled system of the Schrödinger and Poisson equations in two dimensions, specifically in a plane perpendicular to carrier transport. This simulator employs finite elements and provides enough flexibility to analyze different structures such as: FinFETs, Trigates, Gate-All-Around, Pi and Omega-gate MOSFETs. First the nonlinear Poisson equation for the electrostatic potential is:

∇ ( ε∇φ ) = q ( N A− − N D+ + n − p ) ,

(1)

where ε is the dielectric constant, q the electron charge, p and n the hole and electron concentrations, and N A− and N D+ the ionized acceptor and donor density respectively. The 2D Schrödinger equation can be written as:

−

=2 ⎛ 1 ⎞ ∇ ⎜ ∇ψ n ⎟ + Vψ n = Enψ n , 2 ⎝m ⎠

(2)

where ψ n is the wave function corresponding to energy level En. It was assumed that the silicon devices have been fabricated on (100) wafers with the transport direction along the principal axes. Therefore the 1/m is the electron effective mass tensor in the plane perpendicular to the transport direction. Since we are dealing with a 1D electron gas, the quantum electron density (QED hereafter) can be calculated from the solution of (1) and (2) using the following expression: 1

1 ⎛ 2mkT ⎞ 2 ⎛ E − En ⎞ nq = ⎜ 2 ⎟ ∑ψ n2ℑ 1 ⎜ F ⎟, − kT ⎠ π⎝ = ⎠ n 2 ⎝

(3)

where EF is the Fermi level, and ℑ− 1 the complete Fermi-Dirac integral of 2 order -1/2. To get fast convergence, both equations have been solved using the predictor-corrector scheme proposed by Trellakis et al. (Trellakis et al., 1997). This algorithm has been proven as reliable and robust in all the structures considered in our study as long as a sufficient number of energies and wave-functions were included in the QED calculation. Due to the small dimensions of the devices under study, it has been considered that the substrate is undoped since in the nanometer range the random impurity effects are not negligible, producing a dispersion of fundamental parameters like the threshold voltage (Asenov et al., 2001).

ELECTRON TRANSPORT IN SOI NANODEVICES 6

x 10−7

6

4

4

2

2

0

0

−2

−2

−4

−4

−6 −6

−4

−2

0

2

4

317

x 10−7

−6 6 −6 x 10−7

−4

−2

0

2

4

6 x 10−7

Figure 9. Quantum electron density in a GAA cross section of 10×10nm with applied gate voltage of 0.2V (left) and 1.5V (right). At low VG the electrons are concentrated in the centre of the substrate producing volume inversion and at high VG the electrons are shifted next to the interface with the insulator.

Moreover, in all the simulated devices we have considered that the silicon width (WSi) is equal to the silicon height (HSi) and a metal gate with midgap workfunction (4.61eV). As a first result we show in Figure 9 the QED in a silicon quantum wire with dimensions WSi=TSi=10nm. Quantum effects produce a carrier distribution totally different than that could be expected from a classical study. In the first figure, VG=0.2V and we can observe an example of the socalled volume inversion since the peak electron density is found in the center of the silicon body, far from the interfaces. In the second figure, gate voltage is increased to 1.5V, and the electron distribution is shifted to the interfaces with a maximum occurring next to each one of the corners. 3.2. ELECTRON MOBILITY

It has been predicted that a significant improvement of electron mobility would be observed in quasi-one-dimensional systems due to the reduction of the momentum space to a single dimension and the consequent reduction of available final scattering states. To study this possibility a Monte Carlo simulator has been developed where acoustic and intervalley phonons have been considered as scattering mechanisms. Thus, we restrict our study to phonon-limited mobility which is dominant in low effective fields. The corresponding expressions of the scattering rates and also the algorithm have been modified to take into account the characteristics of the 1D structures.

318

ELECTRON TRANSPORT IN SOI NANODEVICES

The rate of electron scattering by acoustic phonons is calculated following the elastic approximation which was shown accurate enough at room temperature (Mickevicius and Mitin, 1993): acus Γυυ ' (kx ) =

Dac2 kT 1D ⎡ ⎤ D1D ( E ) Jυυ ' ⎣δ ( k xf − kυυ ' ) + δ ( k xf + kυυ ' ) ⎦ , 2 8π =ρ ul

(4)

where ρ is the silicon density, Dac is the deformation acoustic potential, and ul the sound velocity in the silicon. Subscripts υ and υ’ refer to the initial and final subbands respectively. After a comprehensive study, we have observed that electron mobility is a strong function of Dac. If the typical 3D value of Dac=9eV is used in the calculations, the mobility reaches abnormally high values. Moreover, it has been demonstrated that in order to reproduce experimental results in ultrathin body DGSOI transistors it was necessary to employ higher values of Dac (Gamiz et al., 2005) due to the increasing influence of the confined acoustic phonons. Thus, in this study we considered Dac=12.9eV for all the geometries, although this parameter could be a function of the device cross section. A study about the influence of the confined acoustic phonons on the transport properties of electrons in silicon nanowires would be very interesting, however, it is beyond the scope of this work. The intervalley scattering rate can be expressed as: int Γυυ ' ( kx ) =

Dij2

1 1⎞ 1D ⎛ D1D ( E ) Jυυ ± ⎟× ' ⎜ N ij + 16πρωij 2 2⎠ ⎝

⎡δ ( k xf − kυυ ' ) + δ ( k xf + kυυ ' ) ⎤ , ⎣ ⎦

(5)

where Dij is the deformation potential, ωij is the intervalley phonon frequency, Nij is the excited phonon number. Subscripts i and j refer to the initial and final valleys respectively. From expressions (4) and (5) we can observe several characteristics. Firstly, the energy conservation coming from Fermi’s golden rule has been transformed into a wave-vector conserving δ-function. It is interesting to remember that in a 1D system, the final scattering state is limited to a backward or forward process from an initial ki state to a final one kf depending whether the scattering event reverse (or not) the carrier momentum. Secondly, the scattering probability is proportional to the 1D density of states (D1D(E)) that spikes in correspondence with the subband levels (Godoy et al., 2005). This means that the scattering rate reaches a maximum when the electron energy equals the energy of a subband.

ELECTRON TRANSPORT IN SOI NANODEVICES

319

1D Thirdly, the scattering rates depend on the integral Jυυ ' defined as: 1D Jυυ ' ≡ ∫

∞

∫

∞

−∞ −∞

( * ∫ψ υ ' ( y , z ) e

i q y y + qz z

)

2

ψ υ* ( y , z )dydz dq y dqz .

(6)

If a rectangular quantum wire with an infinitely deep potential well is assumed, the wave functions can be calculated as sin or cos functions. In that case, the integral (6) can be calculated analytically (Mickevicius and Mitin, 1993). In a bulk material, this integral reduces to a δ function due to the momentum conservation. However, in the 1D situation considered here, this term is responsible for the uncertainty of momentum conservation in the confined directions. In our MC simulator we numerically calculated the 1D value of Jυυ ' with the wave functions obtained after the simulation of the semiconductor structure under study, without any a priori approximation. Considering the above mentioned factors, the phonon-limited mobility has been calculated as a function of the gate voltage at different crosssections. The devices studied have a size length of 5, 10 and 15nm. The number of energy levels involved in the calculation makes unviable the simulation of higher cross sections. As can be observed in Figure 10 the phonon mobility is reduced for lower silicon cross-sections and also when the gate voltage increases. This result agrees with that presented by Kotlyar et al. (Kotlyar et al., 2004) making use of the Kubo—Greenwood formalism in a cylindrical Si gated wire. Figure 10 represents the calculated values of the electron mobility as a function of the gate voltage for three different values of the cross section (WSi=HSi= 15nm (); 10nm (○); 5nm (◊)). Devices with the higher cross section show quite similar phonon-limited mobility. However, when the lateral size is reduced to 5nm, an important mobility reduction is noticed. To explain these results we have analyzed the behavior of the overlap 1D integral (6). The following table shows the value of Jυυ ' only for the fundamental subband (υ = υ ' = 1 ) at three different cross sections and two different gate voltages: 1D Jυυ '

15nm 10nm 5nm

VG=0.2V 13

2.51×10 8.02×1013 2.94×1014

VG=1.5V 1.39×1014 1.36×1014 2.17×1014

At low gate voltages, the smaller the device size the higher the overlap factor. Therefore, we can expect a reduction of the electron mobility when the influence of the confinement is increased. At low gate voltages, the electron density reaches a maximum in the center of the silicon body, rather than near to the interfaces. Thus, the reduction of the dimensions produces a

320

ELECTRON TRANSPORT IN SOI NANODEVICES

Figure 10. Phonon-limited electron mobility calculated for three different silicon quantum wires with cross sections, 15nm (), 10nm (○), and 5nm (◊) as a function of the gate voltage.

strong spatial confinement and, as a consequence, an increasing overlap between the wave functions and then of the scattering rates. For higher VG 1D values the differences are clearly reduced and the calculated values of Jυυ ' when WSi=HSi=15 or 10nm are quite similar. Phonon-limited electron mobility follows the same trend, as can be observed in Figure 10. Finally, for an accurate calculation, the surface roughness scattering should be considered since its effect is quite important at high effective fields. 4. CONCLUSIONS

We have studied electron mobility behavior in Single-Gate and DoubleGate Silicon-on-Insulator silicon inversion layers, and in strained Si-SiGeon-Insulator inversion layers by Monte Carlo simulation. The electron mobility in DGSOI devices as Tw decreases was compared with the mobility in SGSOI structures. Thus, we determined the existence of a range of silicon layer thicknesses in which electron mobility in DGSOI inversion layers is significantly improved as compared to bulk-silicon or SGSOI inversion layers, due to the volume inversion effect. We have also shown that electron mobility is greatly improved in strained Si/SiGe-OI devices, in comparison with unstrained SOI devices. Moreover, when these strainedSOI devices are located side-by-side with strained silicon devices, the degradation in electron mobility due to electron confinement is very weak. Therefore, we can conclude that strained-Si/SiGe-on-Insulator inversion layers efficiently combine the improved mobility and velocity overshoot of strained-Si/SiGe devices with the advantages offered by SOI devices.

ELECTRON TRANSPORT IN SOI NANODEVICES

321

Finally, we have analyzed the phonon-limited mobility in silicon quantum wires by means of a one-particle Monte Carlo simulator. It has been observed that increasing the phonon scattering produces a noticeable reduction of the electron mobility when the device dimensions are reduced. Therefore, we have observed that the transition from a 2D to a 1D electron gas produces a degradation of the electron transport properties. ACKNOWLEDGMENTS

The authors would like to thank the European Commission and the Spanish Government for their support, given in the framework of the EUROSOI (IST-1-506653-CA), and SINANO (IST-1-506844) and National Project FIS-2005-6832.

References Ando, T., Fowler, A., and Stern, F., 1982, Electronic properties of two-dimensional systems, Review of Modern Physics 54:437–672. Ando, Y. and Cappy, A., 1993, Ensemble Monte Carlo simulation for electron transport in quantum wire structures, Journal of Applied Physics 74:3983–3992. Asenov, A., Slavcheva, G., Davies, A.B.J., and Saini, S., 2001, Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum eﬀects: a 3-D density-gradient simulation study, IEEE Transactions on Electron Devices 48:722–729. Balestra, F., Cristoloveanu, S., Benachir, M., Brini, J., and Elewa, T., 1987, Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance, IEEE Electron Device Letters EDL9:410–412. Colinge, J.-P., 2004, Silicon-On-Insulator Technology: Materials to VLSI, 3rd. ed., Kluwer, Boston. Cristoloveanu, S., 2001, Silicon on insulator technologies and devices: from present to future, Solid State Electron. 45:1403–1411. Cristoloveanu, S. and Li, S., 1995, Electrical Characterization of Silicon-on-Insulator Materials and Devices, Kluwer, Boston. Fischetti, M. and Laux, S., 1993, Monte Carlo study of electron transport in silicon inversion layers, Physical Review B B48:2244–2274. Fukatsu, S., Ishikawa, Y., Saito T., and Shibata, N., 1998, SiGe-based semiconductor-on insulator substrate created by low-energy separation-by-implanted-oxygen, Applied Physics Letters 72:3485–3487. Gamiz, F., Cartujo-Cassinello, P., Roldan, J., Sampedro, C., and Godoy, A., 2005, Influence of confined acoustic phonons on the electron mobility in ultrathin silicon-on-insulator layers, in: Proc. Intern. Symp. on Silicon-on-Insulator Tech. and Devices, pp. 39–44. Gamiz, F. and Fischetti, M. V., 2001, Monte Carlo simulation of double-gate silicon-on insulator inversion layers: The role of volume inversion, Journal of Applied Physics 89:5478–5487.

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Gamiz, F., Lopez-Villanueva, J., Roldán, J., Carceller, J., and Cartujo, P., 1998, Monte Carlo simulation of electron transport properties in extremely thin SOI MOSFET’s, IEEE Transactions on Electron Devices ED45:1122–1126. Gamiz, F., Roldan, J., Cartujo-Cassinello, P., Lopez-Villanueva, J., and Cartujo, P., 2001, Role of surface-roughness scattering in double gate silicon-on-insulator inversion layers, Journal of Applied Physics 89:1764–4770. Gamiz, F., Roldan, J., and Godoy, A., 1998, Phonon-limited electron mobility in ultrathin silicon-on-insulator inversion layers, Journal of Applied Physics 83:4802–4806. Gamiz, F., Roldan, J., Lopez-Villanueva, J., Cartujo-Cassinello, P., and Carceller, J., 1999, Surface roughness at the SiSiO2 interfaces in fully depleted silicon-on-insulator inversion layers, Journal of Applied Physics 86:6854–6863. Gamiz, F., Roldan, J., Lopez-Villanueva, J., Cartujo-Cassinello, P., Carceller, J., and Rodriguez, S., 1999, Electron mobility in extremely thin single-gate silicon-on-insulator inversion layers, Journal of Applied Physics 86:6269–6275. Godoy, A., Yang, Z., Ravaioli, U., and Gamiz, F., 2005, Eﬀects of nonparabolic bands in quantum wires, Journal of Applied Physics 98:013702. Ishikawa, Y., Shibata, N., and Fukatsu, S., 1999, SiGe-on-insulator substrate using SiGe alloy grown Si(001), Applied Physics Letters 75:983–985. Kotlyar, R., Obradovic, B., Stettler, P.M., and Giles, M., 2004, Assessment of room temperature phonon-limited mobility in gated silicon nanowires, Journal of Applied Physics 84:5270–5272. Lopez-Villanueva, J., Melchor, I., Cartujo, P., and Carceller, J., 1993, Modified Schrödinger equation including nonparabolicity for the study of a two-dimensional electron gas, Physical Review B 48:1626–1631. Majima, H., Ishikuro, H., and Hiramoto, T., 2000, Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFET’s, IEEE Electron Device Letters 21:379–382. Mickevicius, R. and Mitin, V., 1993, Acoustic-phonon scattering in a rectangular quantum wire, Physical ReviewB 48:17194. Mizuno, T., Takagi, S., Sugiyama, N., Koga, J., Tezuka, T., Usuda, K.,T. Hatakeyama, Kurobe, A., and Turiumi, A., 1999, High performance strained-Si p-MOSFETs on SiGeon insulator substrates fabricated by SIMOX technology, in: International Electron Device Meeting (IEEE.IEDM-99), pp. 934–936. Mizuno, T., Takagi, S., Sugiyama, N., Satake, H., Kurobe, A., and Turiumi A., 2000, Electron and hole mobility enhancement in strained-Si MOSFET’s onSiGe-on-insulator substrates fabricated by SIMOX technology, IEEE Electron Device Letters 21:230–232. Price, P., 1981, Two-dimensional electron transport in semiconductor layers. I. Phonon scattering, Annals of Physics 133:217–239. Roldan, J., Gamiz, F., Lopez-Villanueva, J., and Carceller J.E., 1997, Understanding the improved performance of strained SiGe channel MOSFETs, Semiconductor Science and Technology 12:1603–1607. SIA, 2005, International Roadmap for Semiconductors, Technical report (Semiconductor Industry Association); http://itrs.net Trellakis, A., Galick, A., Pacelli, A., and Ravaioli, U., 1997, Iteration scheme for the solution of the two-dimensional, Journal of Applied Physics 81:7880–7884. Yeo, Y. C., Subramanian, V., Kedzierski, J., Xuan, P., King, T., Bokor, J., and Hu, C., 2000, Nanoscale ultrathin-body silicon-on-insulator P-MOSFET with a SiGe/Si heterostructure channel, IEEE Electron Device Letters 21:161–163.

ALL QUANTUM SIMULATION OF ULTRATHIN SOI MOSFETS A. ORLIKOVSKY, V. VYURKOV*, V. LUKICHEV, I. SEMENIKHIN, A. KHOMYAKOV Institute of Physics and Technology RAS, Nakhimovsky avenue 34, Moscow, 117218, Russia * V. Vyurkov. Institute of Physics and Technology RAS, Nakhimovsky avenue 34, Moscow, 117218, Russia. e-mail: [email protected]

Abstract. The procedure for all-quantum 3D simulation of a nanometer scale silicon-on-insulator MOSFET is proposed. It is based on the BüttikerLandauer approach realized via a self-consistent solution of the Schrödinger and Poisson equations. The stabilization of the numerical solution of the Schrödinger equation is achieved by a finite wave-guide mode presentation of a wave function. We also propose a method to avoid the need for numerical solution of Schrödinger equation for most of the particles (waves) moving from contacts CHECK but those which surmount the selfconsistent barrier and contribute to current. This approach brings greater speed of the simulation program.

Keywords: quantum simulation; nanometer field effect transistor

1. Introduction: why we stand for SOI MOSFETs In spite of many detailed reviews on the topic (see, for instance1) we would like her, to reinforce our opinion that the future for silicon VLSI technology lies in the transition to silicon-on-insulator (SOI) wafers. First of all, these structures offer excellent control of the short channel effects which gravely impair bulk silicon MOSFET performance. The continuing employment of bulk silicon even at the 65nm technological node, and also below, entails a heavily doped transistor channel to suppress leakage source-drain current in the OFF-state. Doping inevitably degrades mobility and diminishes the maximum achievable frequency for the device. In other words, one has to sacrifice a high frequency in favour of low leakage current. It is worth noting that the present situation differs from that in the era of micrometer and sub-micrometer transistors. The transit time delay is no more the main cause to restrict the frequency. Charging of source, drain and gate 323 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 323-340. © 2007 Springer.

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capacitances become more crucial. Hopefully, the introduction of high conducting materials (silicides and metals) for electrodes will eliminate that predominance. In our opinion, the ultra-thin (1-5nm) fully depleted silicon will be a structure to take ultimate advantage of SOI wafers and provide an advancement of silicon technology to the most extreme channel lengths which is set by unacceptably high direct tunneling current between source and drain in the OFF-state. Different theoretical estimations set a limit at 5-10nm. Until then we have a preference for ultra-thin SOI because of the following reasons which are partially based on Monte Carlo simulation performed by the program BALSOI2,3. The program accounts for transversal quantization inside a channel. It was an intermediate model stepping to allquantum simulation of a nanoscale transistor. This looks to be quite adequate for the simulation of silicon-on-insulator MOSFETs with channel length down to 50nm. The model is based on factorization of the electron motion inside the channel into quantum transversal and classical longitudinal motion. The main advantages of the ultra-thin SOI MOSFET are as follows. 1. The silicon channel can be undoped, and the high carrier mobility gives an opportunity to achieve a ballistic regime for 10-100nm channel length. The corresponding transit delay time for the thermal velocity 107cm/s at room temperature is equal to 10-13-10-12 s, respectively. 2. In the ballistic regime the channel conductivity in the ON-state is restricted solely by a conductance quantum G0= (26kOhm)-1. For ultimate one-mode channel and technological node of 10nm for source/drain contacts (corresponding capacitance is about 10-18F) the RC-delay time attains 10-14s which is much smaller compared to the foregoing transit delay time.

Figure 1. SOI MOSFET structure to be simulated.

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325

3. For silicon body thicknesses much smaller than gate length the subthreshold slope tends to its theoretical limit 60 mV/dec at room temperature. This avoids the need for multi-gate technology. Incorporating high-k gate dielectrics enhances this effect. 4. The influence of charged traps inside the gate dielectric and interface, on threshold voltage is much suppressed for a thin channel and employment of high-k gate dielectric. Nowadays the dispersion of threshold voltages is the main reason preventing low voltage operation in large integrated circuits. Evidently, lower voltage results in lower power consumption. 5. The quantum surface scattering in spite of an extremely strong influence on mobility in thin layers may not degrade mobility until body thickness 3-5nm. This is confirmed by experimental data4-6 and theoretical considerations7. 6. The main effect of transversal confinement in a thin channel is the threshold voltage shifted arising from the confinement energy. The latter substantially depends on the silicon band structure. The confinement energy is determined by the highest longitudinal electron mass 0.98m0, whereas the mass of motion along the channel is the transversal one, 0.19m0. This results in enhancement of mobility. 7. According to our estimations, the quantum channel-gate capacitance caused by the wave function “step back” from the Si/SiO2 interface is negligible down to 0.3nm effective gate oxide thickness. 8. Hopefully, the interference of charged impurities and quantum reflections do not substantially deteriorate ON-state current. The reason is that the self-consistent potential turns out to be fairly smooth. Meanwhile, the Coulomb potential of impurities is screened by nearby source/drain contacts and gate. No doubt, rigorously it could be confirmed only by all-quantum simulation. To complete the picture it is worth comparing the SOI MOSFET with its probable rivals, often mentioned in publications. 1. Unlike the SOI MOSFET a single electron transistor (SET) has a fundamental restriction on channel conductance: G << G0 required for the Coulomb blockade to be realized. Therefore, this kind of transistor will be always slower in a logic circuit than a SOI MOSFET of the same size. Indeed, switching in logic circuits occurs when one transistor by its ON-state current, changes the state of another via loading associated with the capacitance of contacts and interconnects. 2. The small diameter of a channel compared to the size of contacts is a big shortcoming of a carbon nanotube transistor. It precludes high frequency operation of a transistor in logic circuit. In addition, carbon nanotubes form non-Ohmic contacts with metals.

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We have outlined here only fundamental disadvantages regardless of the progress of technology. We hope that the foregoing statements confirm that SOI MOSFETs are feasible candidates for high-performance devices and, therefore, they are really worthy to be simulated (Fig. 1). All requirements assigned to transistors are controversial. As a rule, when one characteristics is improved by some means another becomes impaired. Therefore, thorough optimization is necessary and computer simulation plays a key role in this respect. Our allquantum 3D model of SOI MOSFET and associated program QUASOI is presented below. 2. Buttiker-Landauer formalism to simulate SOI MOSFETs The carriers (electrons and holes) in a nanotransistor behave as de Broglie waves in a wave-guide rather than classical rigid particles. Their simulation requires a rigorous description of open quantum systems. The solution of the problem is now in progress. There are various approaches so far proposed: Wigner function formalism8,9, non-equilibrium Green functions10-12, Pauli quantum kinetic equation13 and the Landauer-Buttiker approach14-19 which is to some extent, similar to the S-matrix approach20-21. Amongst those methods, we favour the Buttiker-Landauer approach. It has a distinct physical sense and, besides, it is quite compatible with the classical ballistic model. Furthermore, it is clearly based on the conception of a transistor channel as a quantum wire or quantum wave-guide. The main disadvantages of other methods, in our opinion, are as follows. The Wigner equation has a very complicated field term. All calculations made up to date were timeconsuming especially when interference was substantial. The Green function approach in its present form,fails to give an adequate description of MOSFET contacts. However, this is just a vital point of the whole description as a MOSFET’s operation, in fact, is based upon a thermal current over a selfconsistent potential barrier. It seems that Green function formalism will make advances to extreme technologies: molecular and atomic ones. Thus we maintain that we have made the best choice for today. The all-quantum 3D simulation program QUASOI is now described. It is based on a self-consistent solution of the Schrödinger and Poisson equations. We calculate the transmission coefficients Tij associated with the incident i-th waveguide mode to the out-going j-th waveguide mode from the Schrödinger equation and then evaluate the dependence of drain current, ID upon the source-drain voltage, VD via the Buttiker-Landauer formula upgraded to the situation:

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327

Figure 2. Schematic view of a SOI MOSFET with unintended random impurities inside a channel.

I (VD ) =

2e ∑ h ν

∑ ∑ ∫ dET ( E ) [ f ij

i

S

( E ) − f D ( E )] ,

(1)

j

where fS and fD are Fermi-Dirac distribution functions in a source and drain contact shifted by drain bias eVD, respectively; E is the total energy consisting of transversal quantization and longitudinal motion components. There is a summation over all wave-guide modes i and j involved in the simulation and all conduction band valleys υ. The pre-summation factor originates in the quantum wire conductance quantum for spin-unpolarized current G0=2e2/h, where h is Planck constant. The main goal of all-quantum simulation is to clarify the impact of interference on unintended charged impurities in a channel (Fig. 2), and quantum reflection from the self-consistent potential to allow I-V curve reproducibility for different randomly doped transistors in a circuit. Hopefully, the interference due to charged impurities and quantum reflection do not substantially deteriorate the ON-state current; the reason being that the self-consistent potential turns out to be fairly smooth. Meanwhile, the bare Coulomb potential of impurities is really screened by nearby source/drain contacts and the gate. No doubt, this could be confirmed rigorously only by practical simulation and is addressed in Section 7. 3. Rigorous description of contacts As already outlined above, MOSFET operation is mainly based upon the mechanism of thermal current flow over a self-consistent potential barrier. To give an adequate description of this barrier, it is vital to take the influence of the contacts into consideration. There is an additional reason for the latter; any approaches to simulation of open systems (quantum as

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Figure 3. Transverse mode presentation for unbiased channel. There are lots of occupied modes in contacts, but only few of them are conducting. Electrons in other modes are reflected back from the barrier and do not contribute to current.

well as classical ones) must start from a boundary where the distribution function of incoming particles is known. For instance, considering the above expression of the Buttiker-Landauer formalism (Eqn.1), the only region where this function is known with a good degree of accuracy is at the quasi-equilibrium, heavily doped source/drain contacts. However, the simulation becomes very much complicated and time-consuming when contacts are involved. The reason is the strong scattering and large number of occupied modes inside a contact, as depicted in Fig. 3. The main contribution of our approach is based on the study of a high self-consistent potential barrier originating at the boundary between heavily doped source/drain contacts and an undoped channel as shown in Fig. 42,3. Most of the particles (or waves) are reflected back by the barrier and return to the contact. They are in equilibrium with the contact reservoir whatever intensive scattering occurs therein. The particle distribution can be described using via Fermi-Dirac statistics and the Poisson equation for a self-consistent field. Herewith, no dynamic equations (neither quantum, or classical) need to be solved. The numerical solution of dynamic equations (Schrödinger equation in the case) is only required for particles which surmount the barrier and contribute to the current. The portion of those particles in realistic structures is about one in a hundred, so this method results in an essential acceleration of the simulation program, by at least a factor of 100.

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Figure 4. The self-consistent potential inside a channel backscatters most of the carriers coming from contacts.

4. Solution of Schrödinger equation The direct solution of the stationary Schrödinger equation using a finite difference scheme is known to encounter an instability caused by evanescent modes. These modes inevitably originate from errors of truncation in a computer. Moreover, the upper evanescent modes grow much faster than lower ones. In fact, the exponential growth of upper modes makes computation impossible. We endeavor to circumvent such a shortcoming and achieve stabilization by quite explicit means. Namely, only several evanescent modes are involved into calculation. In brief, what we do is as follows. The exact solution of the Schrödinger equation is presented as an infinite sum of all transversal modes (either, running and evanescent ones) with amplitudes depending on a longitudinal coordinate. The rate equations for amplitudes bind different modes via matrix elements of the potential in the channel. First of all the transfer matrix for a finite number of modes is calculated and then transition coefficients for conducting (running) modes are determined after the proper boundary conditions are imposed at the channel ends. Since matrix elements for upper modes rapidly regress with rising mode number, this allows them to be restricted to a fairly small amount. Actually, an suitably efficient quantity is determined during practical simulation. The detailed

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description of the procedure is presented below. Hereafter we follow the common strategy which has been widely used for a non-uniform electromagnetic wave-guide description, for many years. The stationary Schrödinger equation is ⎡ = 2∂ 2 ⎤ = 2∂ 2 = 2∂ 2 − − − + U ( x, y, z)⎥ψ ( x, y, z) = Eψ ( x, y, z) , ⎢ 2 2 2 ⎣⎢ 2mx∂x 2my∂y 2mz∂z ⎦⎥

(2)

where U(x,y,z)=-eφ(x,y,z) is a potential energy inside the channel, mx, my, mz are electron effective masses along corresponding axes of the silicon conduction band structure (Fig. 5). The exact wave function in any cross-section x is expended over all transversal modes ϕ i ( y , z ) for the uniform wave-guide: ∞

ψ ( x, y , z ) = ∑ ci ( x ) ⋅ ϕi ( y , z ) .

(3)

i =1

The complete set of functions ϕi ( y , z ) obey the two-dimensional Schrödinger equation

⎡ ∂2 ∂2 ⎤ − − ⎢ ⎥ ϕi ( y , z ) = ε iϕi ( y , z ) . 2 2mz ∂z 2 ⎥⎦ ⎢⎣ 2my ∂y

(4)

The functions ϕi ( y , z ) turn to zero on the wave-guide walls. The solutions of equation (4) give rise to mode energies εi. For the uniform rectangular wave-guide the transversal functions are trivial

ϕi ( y, z) = εi =

2 π ny π mz sin sin , W d Si W d si

π 2= 2 ⎛ n 2

⎜ 2 ⎜⎝ m yW 2

+

m2 mz d Si2

⎞ ⎟⎟ , ⎠

(5)

(6)

where W is the channel width (y-axis), D is the channel thickness (z-axis), i=(n,m), n and m are integers. The functions ϕi ( y , z ) are real, orthogonal, and normalized per unity so that

∫ dy ∫ dzϕ ( y, z )ϕ ( y, z ) = δ i

where δij is the Kronecker delta.

j

ij

(7)

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331

Figure 5. Six valleys in silicon conduction band structure for [100] orientation of the wafer. Waves in the channel are running in x-direction.

After substituting equation (3) into the Schrödinger equation (2), then multiplying it by ϕ j ( y , z ) and integrating over the transversal coordinates y and z one arrives at the set of equations for amplitudes

∂ 2ci ( x ) − + ∑U ij ( x )c j ( x ) = [ E − ε i ] ci ( x ) , 2mx ∂x 2 j

(8)

U ij ( x ) = ∫ dy ∫ dzϕi ( y , z )U ( x, y , z )ϕ j ( y , z )

(9)

where

is a matrix element of the potential. We retain a finite number of modes in expansion (3). The justification of such a reduction lies in behavior of matrix elements of the bare Coulomb potential U(r) ~ 1/r for upper modes j=(n,m), n >> 1, m >> 1,

U ij ( x ) ~

1 n2 + m2

.

(10)

Therefore, the transformation of the incident mode i into upper modes j is negligible. The necessary number of modes involved into consideration could be determined immediately during simulation. The equation is to be solved on a uniform mesh with nodes in x=xk, k=-1, 0, 1..N, N+1, N+2 and step ∆x. The finite difference approximation of Eq. (8) is

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ci (xk −1 ) = −ci (xk +1) + 2ci (xk ) + ⎛ ⎞ +2mx ⋅ ∆x 2 ⎜ ∑ U i , j ( xk )c j ( xk ) − [ E − ε i ] ci ( xk ) ⎟ . ⎝ j ⎠

(11)

The same in vector presentation looks like

c( xk −1 ) = −c( xk +1 ) + 2c( xk ) +

+2mx ⋅ ∆x 2 ( U( xk )c( xk ) − [ E − ε ] c( xk ) ) =

= −c( xk +1 ) + A( xk )c( xk ) ,

(12)

where c=(ci) and ε=(εi) are vectors, U=(Uij) and A=(Aij) are matrices. Then we rewrite equation (12) as

⎛ c( xk −1 ) ⎞ ⎛ A ( xk ) − I ⎞⎛ c( xk ) ⎞ ⎛ c ( xk ) ⎞ = T( xk ) ⎜ ⎟ ⎟, ⎜ c( x ) ⎟ = ⎜ I ⎟⎜ 0 ⎠⎝ c( xk +1 ) ⎠ k ⎝ ⎝ c( xk +1 ) ⎠ ⎠ ⎝

(13)

where I is a unity matrix. The solution is

⎛ c( x−1 ) ⎞ N +1 ⎛ c( xN +1 ) ⎞ ⎛ c( x N +1 ) ⎞ ⎜ c( x ) ⎟ = ∏ T( xk ) ⎜ c( x ) ⎟ = Ttot ⎜ c( x ) ⎟ . k =0 0 ⎠ ⎝ ⎝ N +2 ⎠ ⎝ N +2 ⎠

(14)

The Eqn. 14 relates the coefficients c at the left boundary with that at the right-hand one via the total transfer-matrix Ttot being a product of individual transfer-matrices for particular nodes xk. To pose boundary conditions one should express the coefficients, c in terms of amplitudes of waves going to the right and the left in the extreme nodes placed fairly deeply in the contacts

ci ( x−1 ) = ciL+ + ciL− , i 2 m x ( E − ε i ) ∆x + = iL

ci ( x0 ) = c e

(15a) − iL

+c e

−

i 2 m x ( E − ε i ) ∆x =

ci ( x N ) = ciR+ + ciR− , i

ci ( xN +1 ) = ciR+ e = + ciR− e

2 mx ( E − eVD −ε i )∆x

−

,

(15b) (15c)

+

i 2 mx ( E − eVD −ε i )∆x =

,

(15d)

where VD is the drain voltage. There is an assumption that the potential φ does not vary between nodes which is valid sufficiently deep in the contacts. For the left (source) contact, φ=0, meanwhile for the right (drain)

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333

contact φ=VD. For evanescent modes which correspond to negative energy of longitudinal motion, the sign of the square root in Eqn. (15b) and (15c) is chosen according to the rules

i E − εi = − | E − εi | ,

(16a)

−i E − ε i = + | E − ε i | ,

(16b)

i E − eVD − ε i = − | E − eVD − ε i | ,

(16c)

−i E − eVD − ε i = + | E − eVD − ε i | .

(16d)

To calculate the transmission coefficients Tij one should pose the boundary conditions in source (left) and drain (right) contacts, that is, ascribe

c +jL = 0 for all j ≠ i and ciL+ = 1 ,

(17a)

c −jR = 0 for all j including j = i .

(17b)

Actually, this condition implies unity amplitude of an incident wave from one contact and zero amplitude of incident waves from another. After substituting boundary conditions (17) in Eqn. (15), then in Eqn. (14) one obtains a system of linear equations. The solution produces the requisite transmission coefficients

Tij =| c −jR |2 .

(18)

These coefficients are further employed for calculation of the current using the Buttiker-Landauer formulism. Moreover, the direct employment of Eqn. (14) in intermediate nodes xk inside the channel, allows the reconstruction of the wave function amplitude c(xk) everywhere in the channel and thus the electron density can be determined. The latter could be further used for iteration with the Poisson equation. 5. One-dimensional classical ballistic simulation Classical ballistic simulation can be regarded as an approximate step towards quantum simulation. When a bias is absent (VD=0) the electron density is calculated according to

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ρ tot ( x ) = −4e∑ i =0

∞

dk

∫ 2π = f ( E ) + eN

D

( x) ,

(19)

0

where the factor of 4, arises from two possible spin states and two possible directions of motion; ND(x) is the doping profile. The summation is really extended over a finite number of modes i. The equilibrium Fermi-Dirac distribution function is

f (E) =

1 . E − εF 1 + exp kT

(20)

The Fermi energy is calculated in the usual way via the neutrality condition ρ=0 which is realized fairly deep in the contacts. The total energy is composed of the transversal quantization energy (mode energy) εi, potential energy eφ(x), and longitudinal kinetic energy depending on a wave number k(x):

E = εi +

= 2k ( x )2 − eϕ ( x ) . 2m x

(21)

The computed density of free carriers is substituted into the Poisson equation to allow calculation of the potential, φ(x). The iteration procedure stops when the required accuracy is achieved. Surprisingly, the self-consistent solution of the Poisson equation with the equilibrium distribution function is sufficient to simulate a steady current regime for one-dimensional motion. As a matter of fact, it is simply an extension of the Landauer approach to classical ballistic longitudinal motion. The particles (waves) are divided into those moving from the left contact and those moving from the right one. The corresponding densities produced are calculated in accordance with the relations ∞

ρ `L ( x ) = 2 ∑ i =0 ∞

ρ `R ( x ) = 2 ∑ i =0

∞

dk ( x ) f ( E )(2 − Ti ( E )) , 2π = 0

∫

(22)

∞

dk ( x ) f ( E )(2 − Ti ( E )) , 2π = 0

∫

ρ tot ( x ) = ρ L ( x ) + ρ R ( x ) + eN D ( x ) .

(23) (24)

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335

The transmission coefficient T(E) equals 0 if the particle is reflected from the barrier, otherwise it equals 1. If the particle is reflected, the density is doubled. If at the potential barrier top, the condition –eφm < E - εi is satisfied, that particle is reflected back from the barrier and T=0. If the condition is not satisfied, the particle passes through the barrier and T=1. The expression for charge density according to formulae (22)-(24) undergoes iteration with Poisson equation solution. Afterwards, the current is calculated via the Buttiker-Landauer relation (1). 6. Stages of simulation The program operates as follows. 1. Classical ballistic simulation via self-consistent solution of the Poisson equation with Fermi-Dirac distribution function to obtain a selfconsistent potential. 2. Solution of the Schroedinger equation with the foregoing self-consistent potential to obtain the transmission coefficients and new (quantum) electron density inside the channel. 3. Solution of Poisson equation corrected by new electron density inside the channel to obtain a self-consistent potential. Iterations with stage 2 until the required accuracy is attained. 4. Calculation of current according to Buttiker-Landauer formula. 7. Results of simulation Up to date we have carried out only preliminary, all-quantum calculations. Geometrical parameters of the structure are: gate length 10nm, spacer length 5nm, silicon body thickness 2nm, channel width 5nm, effective gate oxide thickness 1.5nm. The source/drain doping is 1020cm-3. The simulation region involves a 5nm contact length, which turned out to be sufficient to make a rigorous description of the self-consistent potential barrier. The potential flattens by the boundaries and this is taken as an indication that a sufficient portion of the contact is included in the simulation area. The calculated quantum transmission coefficients for different valleys and in the absence of random impurities in the channel, are demonstrated in Fig. 6a and 6b. A sharp transition from T=0 to T≈1 appears when the longitudinal energy surmounts the barrier height. Evidently, this resembles very much, classical behaviour.

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Transmission

1 0,8 0,6 0,4 0,2 0 0

0,1

0,2

0,3

0,4

0,5

Energy, eV

(a)

Transmission

1,2 1 0,8 0,6 0,4 0,2 0 0

0,1

0,2

0,3

0,4

0,5

Energy, eV

(b) Figure 6. (a) Transmission coefficient vs. longitudinal energy of an electron in [100] and [010] valleys. No impurities in the channel. (b) Transmission coefficient vs. longitudinal energy of an electron in [001] valleys. No impurities in a channel.

The calculated quantum transmission coefficients for 4 and 10 random impurities in the channel are depicted in Fig. 7-8, respectively. It can be readily seen that the interference peaks are much more pronounced for an electron in [100] and [010] valleys than in [001] valley. This is a result of the much smaller mass and thus much larger wave length. It should be noted that electrons of [100] valleys make the largest contribution to the current as they have the lowest energy of transversal quantization due to a large mass mt=0.98m0 along the z-axis. Only electrons with energy inside a short range about several kT around the barrier top contribute to current. At room temperature kT=0.026eV. The above curves show that most of the electrons coming from contacts really possess a transmission coefficient close to zero. Indeed, they could be considered as classical. This supports our proposal for accelerating the all-quantum simulation program.

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337

Transmission

1,2 1 0,8 0,6 0,4 0,2 0 0

0,1

0,2

0,3

0,4

0,5

Energy, eV

(a)

Transmission

1,2 1 0,8 0,6 0,4 0,2 0 0

0,1

0,2

0,3

0,4

0,5

Energy, eV

(b) Figure 7. (a)Transmission coefficient vs. longitudinal energy of an electron in [100] and [010] valleys. 4 random impurities in a channel. (b) Transmission coefficient vs. longitudinal energy of an electron in [001] valleys. 4 random impurities in a channel.

The present calculations are merely demonstrations of program effectiveness. Indeed, the doping in the channel is too high, of the order of 1019cm-3. In the near future we intend to account for more realistic distributions of impurities in the channel. 8. Pitfalls of Buttiker-Landauer formalism In spite of the clarity of the Buttiker-Landauer formula (1), actually, it contains hidden quite limiting assumptions. First of all, we assume that contact reservoirs supply only pure states into the channel and they sustain their coherence during transmission through the channel. There are several reasons to make this assumption questionnable: 1. mixed states are injected from contacts instead of pure ones; 2. entangled states are injected from contacts; 3. electron-electron scattering inside the channel is considerable.

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Transmission

1,2 1 0,8 0,6 0,4 0,2 0 0

0,1

0,2

0,3

0,4

0,5

Energy, eV

(a)

Transmission

1,2 1 0,8 0,6 0,4 0,2 0 0

0,1

0,2

0,3

0,4

0,5

Energy, eV

(b) Figure 8. (a) Transmission coefficient vs. longitudinal energy of an electron in [100] and [010] valleys. 10 random impurities in a channel. (b) Transmission coefficient vs. longitudinal energy of an electron in [001] valleys. 10 random impurities in a channel.

We can consider the likely effect on the current if we take those circumstances into account. The mixed state means that a single electron occupies simultaneously, several eigen-states in the channel. Interference between these states will cause the current to vary in space and time. However, after an averaging over time and keeping in mind the random nature of the phases of states in the mixture, one comes again to the initial formula of Eqn.1 for the current. The same considerations occur when we deal with entangled states whereby the overall state of several electrons is not separable into a product of individual states. The formulism of Eqn.1 survives again. As for the electron-electron scattering, it is commonly omitted in classical Monte Carlo simulation. This is substantiated by the fact that this kind of scattering, at least, does not influence significantly the mobility due to the momentum conservation law. Such is not the case if we regard interference in quantum simulation. Interference requires coherence in the channel and electron-electron scattering breaks such coherence. The decoherence time has a reciprocal relationship with the

ALL QUANTUM SIMULATION OF ULTRATHIN SOI MOSFETS

339

electron-electron scattering rate which is for the typical bulk density n ~ 1018cm-3 equal to ~1013s-1. It leads to the decoherence length about 10nm for the thermal velocity 107cm/s. These estimations readily show that electron-electron scattering could substantially smooth down the sharpness of interference peculiarities on the I-V curve, obtained in a single-particle model. 9. Conclusion A procedure for all-quantum 3D simulation of a nanometer scale silicon-oninsulator MOSFETs is proposed. The procedure is based on the BüttikerLandauer approach and realized via a self-consistent solution of the Schrödinger and Poisson equations. Stabilization of the numerical solution of the Schrödinger equation is achieved by a wave-guide mode approach. Most of the particles (waves) moving from a contact are reflected by the self-consistent barrier and returned to the contact. Therefore, they are in equilibrium with the contact reservoir. Those particles could be easily put into consideration via Fermi-Dirac statistics and Poisson’s equation to estimate the self-consistent electric field. Herewith, no dynamic equations need to be solved. The numerical solution of dynamic equations (Schrödinger equation in this case) is only required for particles which surmount the barrier and contribute to the current. As a result, this method constitutes a fast and efficient simulation algorithm. ACHNOWLEDGEMENTS

The authors extend much gratitude to K.A.Valiev for fruitful discussions. The research was supported by NIX Computer Company ([email protected]), grant #F793/8-05, and Russian Basic Research Foundation, grants #06-0789151-а and #06-01-00097-а.

References 1.

2. 3.

Haensch W., Nowak E. J., Dennard R. H., Solomon P. M., Bryant A., Dokumaci O. H., Kumar A., Wang X., Jonson J. B., and Fischetti M. V. 2006. Silicon CMOS devices beyond scaling. IBM J. Res. & Dev. 50: 339-361A. Sidorov A. A., V’yurkov V. V., Orlikovsky A.A. 2004. Monte Carlo Simulation of Nanoscale SOI MOSFETs. Russian Microelectronics 33: 195-205. V’yurkov V. V., Orlikovsky A. A., and Sidorov A. A. 2003. Computer Simulation of a nanoscale ballistic SOI MOSFET with a sub-10-nm Si layer. Russian Microelectronics 32: 224-232.

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7. 8.

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ALL QUANTUM SIMULATION OF ULTRATHIN SOI MOSFETS Ernst T., Munteanu D. et al. 1999. Ultimately thin SOI MOSFETs: Special characteristics and mechanism. in: Proc. IEEE Int. SOI Conf., Rohnert Park (California, USA), oct. 1999. Popov V. P., Antonova I. V., Stas V. F. et al. 2000. Properties of extremely thin silicon layer in silicon-on-insulator structure. J. Mater. Sci. Eng. B73: 82-86. Uchida K. and Takagi S. 2003. Carrier scattering induced by thickness fluctuation of silicon-on-insulator film in ultrathin-body metal-oxide-semiconductor field-effect transistors. Appl. Phys. Lett. 82: 2916-2918. Ananiev S. D., V’yurkov V. V., and Lukichev V. F. 2006. Surface scattering in SOI field-effect transistor. in: Proc. SPIE, 6260:0O-1-8. Shifren L., Ringhofer C., and Ferry D. K. 2003. A Wigner function-based quantum ensemble Monte Carlo study of a resonant tunneling diode. IEEE Trans. El. Devices 50: 769. Bordone P., Pascoli M., Brunetti R., Bertoni A., and Jacoboni C. 1998. Quantum transport of electrons in open nanostructures with the Wigner-function formalism. Phys. Rev. B. 59: 3060. Mamaluy D., Sabathil M., and Vogl P. 2003. Efficient method for calculation of ballistic quantum transport. J. Appl. Phys. 93: 4628. Lake R., Klimeck G., Bowen R. C., and Javanovic D. 1997. Single and multiband modeling of quantum electron transport through layered semiconductor devices. J. Appl. Phys. 81: 7845. Hake A. and Khondker A. N. 2000. Quantum transport in mesoscopic devices: Current conduction in quantum wire structures. J. Appl. Phys. 87: 2553. Fischetti M. V. 1998. Master-equation approach to the study of electronic transport in small semiconductor devices. Phys. Rev. B 59: 4901. Venugopal R., Paulsson M., Goasguen S., Datta S., and Lundstrom M. S. 2003. A simple quantum mechanical treatment of scattering in nanoscale transistors. J. Appl. Phys. 93: 5613. Jimenez D., Saenz J.J., Iniquez B. et al. 2003. Unified compact model for the ballistic quantum wire and quantum well metal-oxide-semiconductor field effect transistor. J. Appl. Phys. 94: 1061. Landauer R. 1985. Transport as a Consequence of the Incident Carrier flux, in Localization, Interaction, and Transport Phenomena, G.Bergmann and Y. Buynseraede, Eds., Springer-Verlag, Heidelberg, P. 38. Buttiker M. 1988. Symmetry of electrical conduction. IBM J. Res. Dev. 32: 317. Gilbert M. J. and Ferry D. K. 2004. Efficient quantum three-dimensional modeling of fully depleted ballistic silicon-on-insulator metal-oxide-semiconductor field-effecttransistors. J. Appl. Phys. 95: 7954-7960. Venugopal R., Goasguen S., Datta S., and Lundstrom M.S. 2004. Quantum mechanical analysis of channel access geometry and series resistance in nanoscale transistors. J. Appl. Phys. 95: 292. Kane E. O. 1969. Tunneling Phenomena in Solids, edited by E. Burstein and S. Lundqvist (Plenum, New York) p. 1. Schulman J. N. and Chang Y. C. 1983. Reduced Hamiltonian method for solving the tight-binding model of interfaces. Phys. Rev. B. 27: 2346.

RESONANT TUNNELING DEVICES ON SOI BASIS BOGDAN MAJKUSIAK* Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw, Poland *

To whom the correspondence should be adressed: [email protected]

Abstract. The paper reviews achievements and perspectives of building silicon-base resonant tunneling devices in respect to the material and architecture issues, with especial emphasis on the SOI technology.

Keywords: nanoelectronics; silicon-on-insulator; resonant tunneling.

1. Introduction Resonant tunneling (RT) means tunneling through a quantum system containing at least two potential barriers and a quantum well between them. The probability of tunneling exhibits sharp peaks for energies corresponding to eigen-states of the inner quantum well, reaching unity if the barriers are symmetrical. In the case of a superlattice of identical barriers separated by identical quantum wells, the resonant levels create the resonant transport energy minibands. Current-voltage dependence of the resonant tunneling diode (RTD) can exhibit multiple current peaks followed by ranges of the negative differential resistance (NDR). The NDR ranges begin at peak voltages (Vp), when subsequent resonant energy levels in the quantum well drop below the bottom of the conduction band in the emitter, becoming unable to transfer carriers from the emitter to the collector electrode. The peak current density (Jp) and the peak-to-valley current ratio (PVCR) are the main figures-ofmerit of a RTD. If the potential of the quantum well is controlled directly by a galvanic contact or affected by the electric field of an additional gate electrode, the double barrier system can be exploited as the resonant tunneling transistor (RTT). Since the first theoretical prediction1 and especially the first roomtemperature observation of the NDR effect2 in the double barrier quantum

341 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 341-356. © 2007 Springer.

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system, resonant tunneling structures have become well known and widely investigated but mainly in III/V semiconductors. Attempts to build silicon nanoelectronics have resulted in a search for the resonant tunneling effect in silicon-based structures. Currently, the silicon-based resonant tunneling devices are considered to be the most promising candidates to replace MOSFETs in the beyond-CMOS era3. One of the obvious reasons for the search for new alternative silicon devices arises because scaling of the channel length in conventional field-effect transistors cannot proceed infinitely due to the ballistic transport and direct source-to-drain tunneling4. On the other hand, such conditions are desirable for tunneling as an alternative to the drift-diffusion transport principle. Because of their inherent high speed and multi-stability, the resonant tunneling devices are attractive for very high frequency, low power and multi-valued logic circuits and can be incorporated in more compound quantum functional devices and circuits. The one-transistor static memory cell5 is a good example of the increased functionality offered by the resonant tunneling device. It consists of two tunnel diodes connected in series and a transfer field effect transistor. Potential of the connection point stays in one of two stable states and switching between them is forced by the potential of the bit line, transferred by the channel of the turned-on transistor controlled from the word line. Although most concepts of the silicon resonant tunneling devices can be realized in the conventional bulk MOS technology, the ultra-thin, double gate silicon-on-insulator technology (DG SOI), owing to its manufacture possibilities, is well-suited to play the role of a technological platform for silicon nanoelectronics. Its most important feature is that the silicon thickness, which can define the length of the RTD quantum well, is controlled not by lithography but by the growth and thinning processes, which offer greater control and sensitivity than lithography resolution. Also, very good uniformity of the layer thickness can be achieved. Additionally, the thick buried oxide gives an excellent isolation of the realized structure. However, at the current state of knowledge and experience, the main task in relation to the resonant tunneling effect, is its feasibility for incorporation into the silicon technology and to silicon-on-insulator technology in particular. 2. Structural and physical requirements In order to evaluate the feasibility for silicon based resonant tunneling devices, it is appropriate to consider structural and physical requirements which must be fulfilled by a double barrier system to result in a distinct NDR effect and to be applicable in the silicon CMOS process.

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Taking into consideration the manufacture requirements to transfer resonant tunneling devices to the main-stream technology, the fabrication process of the double barrier structure must be compatible with the silicon CMOS process and the structure must have two independently biased gate electrodes. The first requirement corresponds mainly to materials issues since the silicon based double barrier structure can exploit some exotic insulators. The second condition is not trivial given that the majority of current DG SOI technologies have the gates shorted together. The most important design parameter of a RTD structure is the base length. It determines the phase shift of the wave function in its transit through the base, which must be a multiple of 2π for the eigen-energies of the quantum well and the resonant tunneling levels. If the base length is too long and resonant levels lie too densely, a drop of the resonant tunneling current through one resonant level is covered by a practically unchanged current flowing through higher resonant levels and the NDR effect may be invisible. The base length must be shorter or at least comparable to the carrier mean free path for scattering. In the opposite case, when carriers lose quantum coherence in scattering events, the double barrier system represents two tunnel junctions separated by a classical diffusive transport region and no interference effect of the wave functions should be expected. The base thickness of the RTD must be uniform since the non-uniformity results in the resonant current ‘washout’ and reduction of the peak-to-valley current ratio. The conduction band discontinuity at the base/barrier interface cannot be too small if multiple tunneling probability peaks, and in consequence multiple resonant current peaks are required. Barrier height and the effective mass of carriers in the barrier affect also resonant energies since they determine the wave function shift at inner reflections from the barriers. Barrier thickness does not affect position of the resonant energies but influences sharpness of the resonant peak of the tunneling probability and hence the magitude of the tunnel current. 3. Silicon based double barrier material systems In general, taking into consideration the energy band diagram of a double barrier system, two kinds of RT structures can be distinguished: a) intraband or b) interband. The intraband resonant tunneling (Fig. 1a) takes place when electrons or holes tunnel between energy bands of the same kind in all three conductive regions of the quantum system. In the interband resonant tunneling, electrons tunnel between the conduction and valence bands at least in one

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Figure 1. Resonant tunneling structures based on: a) electron intraband RT, b) interband RT, c) junction interband RT.

barrier region. The barrier can be created as an additional layer of material of the appropriate band offset, as shown in Figs. 1a and 1b, or can be electrostatically induced or formed as a junction transition region, as shown in Fig. 1c for the junction interband tunneling. The choice of the barrier material system is a key issue for developing the silicon-based RTDs due not only to requirements of physical parameters but also the need for compatibility with the conventional CMOS technology. The Si/SiO2 system would be the most natural and desirable but also other materials have been investigated. Different attempts have been undertaken to realize resonant tunneling structures under the requirement that the system is at least grown or deposited on a silicon substrate. In general, three approaches can be distinguished: 1) the material of the barrier layer is different than SiO2, 2) the RTD is based on the Si/SiGe heterostructure, 3) the RTD is based on the Si/SiO2 heterostructure. Given that the III/V semiconductors are established as a powerful technology for fabrication of resonant tunneling devices, it could be that a good route is to deposit them onto a silicon substrate. Such an approach has been successfully applied6 to fabricate an RT diode with AlAs barriers and In(Ga)As quantum well with electrodes grown on a silicon substrate, covered before by the InP quasi-substrate and the low temperature InAlAs buffer layer. A clear NDR effect with PVCR of 2 at room temperature was observed. One of the earliest attempts to observe the resonant tunneling effect in a structure grown on a silicon substrate was presented in7, where silicon nitride played the role of barrier layer and an amorphous silicon layer as a quantum well. No NDR effect was observed at 77 K, but current bumps at voltages corresponding to calculated resonant energies, confirmed a contribution due to resonant tunneling. Successful observation of the NDR effect at room temperature was reported for a transistor structure with a triple barrier resonant tunneling system8, where calcium fluoride was used as a barrier layer. This material has a fluorite lattice structure well-matched to the silicon lattice. The band offset at the Si/CaF2 interface is equal to 2.9 eV, nearly the same as for the Si/SiO2 system. The metallic CoSi2 layer was deposited as the quantum well region. High PVCR with a clear effect of the third electrode was observed.

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The successful use of CaF2 as a barrier layer has encouraged other attempts to fabricate resonant tunneling structures with this material. In9, amorphous silicon was deposited as a quantum well layer. The NDR effect with PVCR of 3.1 at room temperature was observed but only with the use of the pulsing measurement technique, probably due to large scattering and trapping in the amorphous silicon. The most successful result using CaF2 as a barrier layer was reported in10. The 0.9 nm thick crystalline CaF2 layer was grown on a silicon substrate and the crystalline 3.7nm–thick CdF2 was deposited as the quantum well layer. The observed record PVCR of the order 105 at room temperature, confirmed CaF2/CdF2 as a very promising material system for fabrication of resonant tunneling devices on silicon substrates. Aluminum oxide has been also investigated as a barrier layer in the RT diode on a silicon substrate11. The obtained PVCR was equal to 26 at room temperature. Another idea to fabricate silicon based resonant tunneling devices relies on the use of Si/SiGe heterostructures. Many papers on different layer combinations have been published. In general, two main concepts are exploited: intraband resonant tunneling and interband resonant tunneling. Depending on the technology and stress/relaxation engineering, resonant tunneling of holes12,13 and electrons14,15,16,17,18 with high PVCRs has been reported. In19, a triple-barrier electron intraband resonant tunneling diode with PVCR of 7.6 at room temperature was described. The first interband resonant tunneling diode was presented by Rommel20. In general, the idea of operation of such a diode and the origin of the NDR effect is the same as in the well-known Esaki diode. It relies on tunneling of electrons from the conduction band of a highly doped n-type side of the junction to the valence band of highly doped p-type side of the junction. The delta-doping layers on both sides of the junction help to fulfill the energy band overlapping required for such a tunneling. However, a very important change is introduced if an additional SiGe layer is placed between the delta-doped planes. Due to the upward shift of the valence band edge, intermediate resonant states for tunneling are created that filter energy levels that aid transfer electrons and the tunneling probability is enhanced due to the resonant tunneling regime. Structures of this type (e.g., 21,22,23 ) have been realized with different sequences and parameters of the sandwich layers, resulting in high PVCR factors and in a very wide range of the peak current. Also, examples of successful monolithic integration with Si CMOS process to fabricate quantum functional and multi-valued logic circuits have been reported (e.g.,24,25,26) confirming that this technology can be considered to be mature for commercial applications.

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However for the silicon technology, silicon dioxide is the most natural and well recognized insulator material, thus it would be most desirable to fabricate the resonant tunneling devices basing on the Si/SiO2 material system. Compared to Si/SiGe, the Si/SiO2 system offers much higher conduction band discontinuity. The silicon dioxide is also an excellent insulator. The fundamental limit for the SiO2 thickness to confine electrons in the Si quantum well is evaluated to about 0.5nm27 as a result of the probability washout. The practical problem results from the fact that the ultrathin crystalline silicon layer must be grown on a SiO2 layer, which is amorphous. The first attempts to observe resonant effects in a Si/SiO2 multilayer structure obtained by recrystallization of the deposited amorphous silicon has been done my Tsybeskov28. Although no NDR effect was observed, the step-like characteristics at temperature 4.2 K were interpreted as a result of hole tunneling. A similar approach to realize nanocrystalline silicon superlattices was applied to fabricate RT based memory devices29. Another idea to fabricate the Si/SiO2 based resonant tunneling structures is to produce silicon micro- or nano-crystallites embedded in SiO2 (e.g.,30,31,32,33). Different processing techniques have been used and resonant tunneling has been proposed as an explanation for current jumps observed on current-voltage characteristics. In general, it must be remembered that due to the dependence on crystallite dimensions, the current-voltage characteristic can be affected by resonant tunneling and also by Coulomb blockade. Resonant tunneling has been also observed through boron B+ states in a δ layer34 and Na+ ions embedded in the SiO2 layer35. An interesting way of fabricating an assembly of silicon nanodots between conducting electrodes patterned from the silicon-on-insulator layer was proposed in36. Owing to a good contrast between the hydrophobic surface of silicon and hydrophilic surface of silicon dioxide, the dispersion solution containing silicon nanodots has a tendency to settle between the source and drain nano-electrodes made of silicon-on-insulator layer. The dispersion solution was deposited with the use of a capillary but other deposition techniques could be developed. If the growth of a crystalline silicon layer on SiO2 presents so many problems, it seems natural to use the silicon-on-insulator layer as a quantum plane of the resonant tunneling diode. In37,38,39,40 resonant tunneling diodes were fabricated on the bonded SOI substrate with a buried oxide of thickness in the range of a few nanometers. The silicon layer was thinned to the same thickness range and thermally oxidized to obtain the second ultrathin SiO2 layer. The n+ substrate served as the emitter while the aluminum electrode was used as a collector. The measured current-voltage characteristics exhibited the peak-to-valley current ratio of 1.8 at temperature 15 K, which was the first observation of the NDR effect in the

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SiO2/crystalline silicon/SiO2 resonant tunneling system. Although such SOI devices using the silicon substrate as an active electrode cannot be integrated in a circuit, the obtained result is very promising for the development of SOI based resonant tunneling devices. 4. Device architectures Two architecture configurations of resonant tunneling devices, shown schematically in Fig. 2, can be defined due to the dependence on the direction of tunneling in reference to the crystal substrate surface: vertical and lateral. The vertical configuration is natural for RT structures utilizing the base region obtained in the semiconductor growth or deposition processes, with a very good control of thickness. The area of the active tunneling region is defined by the lateral dimensions of the gate electrode and can be large, which is desirable. A galvanic contact to the base region can potentially lead to the RTT structure, but due to the extremely thin semiconductor layer

Figure 2. Configurations of the resonant tunneling structures: a) vertical (potentially with a galvanic contact to the base), b) lateral (potentially with a double gate control).

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and resultant large base resistance, the RT current control by the base potential or current can be difficult. As an example, the vertical RTD configuration can be easily achieved with the use of the PAGODA separate double gate SOI architecture 41. The lateral RT structure can be realized provided the lithography resolution allows the fabrication of semiconductor quantum wells in the sub-10nm range, where ballistic transport dominates the source-to-drain current, defining the ultimate limit for the classically operating field-effecttransistor. If such patterning control of the lateral dimensions is achieved, ordinary planar FETs but also FinFETs can be exploited to build the RTT structure42,43. Figure 3 shows a single gate SOI adaptation of this concept, where the source/drain regions play the role of emitter/collector electrodes and are separated from the semiconductor body region by ultrathin barrier layers. In this architecture, the gate electrode(s) can effectively control the potential of the ultrathin base, influencing the position of the resonant levels and the output current. Theoretically, resonant tunneling in SiO2/Si based structures in the lateral architecture may be also obtained with the use of Schottky barriers at the source and drain junctions. Another possibility for the RTT utilizing the MOSFET structure is that the potential barriers are induced in the base region by a vertical electrostatic effect, if the sourcedrain channel is not completely overlapped by the gate electrode. Lateral structures with negative differential conductance (NDC) or transconductance (NDT) effects have been obtained utilizing the interband tunneling between the source/drain regions and the gate-induced body region at the surface in the field-induced interband tunneling-effect transistor (FIBTET)44. In this SOI compatible device45,46 (Fig. 4 shows the npn version) with the lateral energy band diagram schematically shown in Fig. 4b, the NDC effect results from Esaki tunneling in the emitter junction

Figure 3. Concept of the lateral SOI RTT in the planar single gate SOI technology.

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Figure 4. The schematic structure (a) and the energy band diagram (b) of the field-induced interband tunneling-effect transistor.

surface region, but if the surface base length is shorter than 10 nm, the resonant tunneling regime can additionally affect the PVCR. 5. Theoretical simulation Theoretical simulation of resonant tunneling has had a long history but the first papers on the SiO2/Si/SiO2 structures47,48 and influence of the main design parameters has been considered quite recently49. Key issues for theoretical modeling of RTDs are the description of the scattering effect and definition of the condition determining the steady state for the floating base regime of operation. In general, the electrostatic problem requires selfconsistent solution of the set of equations consisting of Poison’s equation, two Schrödinger’s equations for electrons with the longitudinal ml = 0.916m0 and the transverse mt = 0.190 m0 effective mass and at least two Schrödinger’s equations for holes with heavy mhh = 0.537m0 and light mlh = 0.153m0 effective mass. The tunneling probability can be calculated basing on the scattering matrix based model50: Prt =

k C / m xC t E t B tC k E / m xE (1 − rE ' rB )(1 − rB ' rC ) − rE ' t B t B ' rC

2

(1)

where t, t’, r, and r’ are elements of the scattering matrices for the regions in Fig. 5, binding the forward (a) and back (b) going components of the wave functions in the emitter, base, and collector regions. The elements of the scattering matrices are calculated with the use of the transfer matrix method for a given distribution of the electrostatic potential in the structure.

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Figure 5. Scattering matrices defined for the emitter, base, and collector regions.

If scattering is taken into account, the transition coefficients of the base matrix tB and tB’ are multiplied by (1–Psc)1/2, where Psc is the probability of scattering during one sequential transition of the electron wave function through the base: ⎛ tT ⎞ ⎟ Psc = 1 − exp⎜⎜ − ⎟ τ r ⎠ ⎝

(2)

where tT is the semi-classical transit time through the base and τr is the scattering time constant obtained50 from perturbation theory and the Fermi golden rule for energy levels in the semiconductor well. Then, the scattering probability is calculated as: (3)

PS = 1 − Prt − Rrt

where Rrt is the probability of reflection of an electron hitting the double barrier system from the emitter side: R rt = rE + t E t E '

rB + rC (t B t B '−rB rB ') (1 − rE ' rB )(1 − rB ' rC ) − rE ' t B t B ' rC

2

(4)

Figure 6 shows energy distributions of the tunneling probability without scattering (Prt0) and with scattering included (PrtS) as well as the probability of scattering PS calculated for the (n+)polySi/SiO2/ (i)Si/SiO2/(n+)polySi system with the 1nm/3nm/1nm thickness sequence and at the collectoremitter voltage VCE = 0.5V. Since the electron effective mass in silicon has two values, two ladders of the resonant levels are present. Scattering strongly reduces the resonant tunneling probability peaks, but it has also a resonant character, exhibiting probability peaks for the resonant energy levels.

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PROBABILITY

1 10

-2

10

-4

10

-6

10

-8

10

-10

10

-12

-0.2

PS Prt0

mt PrtS

ECE

0

0.2

ml VCE = 0.5V

0.4 0.6 E - EFE [eV]

0.8

1

Figure 6. Energy distributions of the resonant tunneling probability Prt (with and without scattering) and scattering probability PS calculated50 for the polySi/SiO2/Si/SiO2/polySi structure (1nm/3nm/1nm) at VCE = 0.5 V.

The resonant tunneling current density Jrt and the scattering currents supplying noncoherent electrons to the base from the emitter SE and the collector SC can be calculated basing on the Tsu-Esaki formula1: J rt = q ∫ Prt (E x )[ N E (E x ) − N C (E x )]dE x ,

(5)

S E ,C = q ∫ PS (E x )N E ,C (E x ) dE x ,

(6)

where NE and NC are the “supply” functions in the emitter and the collector region, respectively, e.g: NE =

4πm E h

3

⎡ ⎛ E − Ex k B T ln ⎢1 + exp⎜⎜ FE ⎝ k BT ⎣⎢

⎞⎤ ⎟⎟⎥ ⎠⎦⎥

(7)

Figure 7 shows the energy distributions of the resonant tunneling current with and without scattering included and of the scattering currents. In turn, Figure 8 shows the voltage dependence of the total current density calculated for the considered structure with and without scattering.

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2

ELECTRON CURRENT [A/cm eV]

10

5

10

1

10

-3

10

Jrt

-7

10

-11

10

-15

VCE = 0.5V

Jrt0

SE

JrtS

SeC ECE

-0.2

0

0.2

0.4

0.6

0.8

1

E - EFE [eV] Figure 7. Energy distributions of the resonant tunneling current without (Jrt0) and with (JrtS) scattering included and of scattering currents supplying electrons from the emitter SE and the collector SC. 3

without IeRT 0 scattering IC with scattering

2

ELECTRON CURRENT [A/cm ]

3x10

2x10

10

T = 300 K

3

3

0 0

0.5 1 VOLTAGE VCE [V]

1.5

Figure 8. Voltage dependence of the tunneling current without and with scattering included for the polySi/SiO2/Si/SiO2/polySi structure (1nm/3nm/1nm).

RESONANT TUNNELING DEVICES ON SOI BASIS

353

6. Conclusions The Si/SiGe intraband and interband RT structures are mature for applications both in SOI and bulk Si technology, offering high peak-tovalley current ratios and peak current density in a wide range. Resonant tunneling in the Si/SiO2 based double barrier system has been also observed but much effort must be devoted to develop deposition of ultrathin (<10nm) and uniform crystalline Si layers on amorphous SiO2. Perhaps the lateral recrystallization process will help to achieve this task. The planar separate double gate SOI processes (e.g., PAGODA) are the most promising of todays technologies to fabricate Si/SiO2 based resonant tunneling devices. The field-induced interband tunneling-effect transistor offers the NDR effect even today but reduction of the base length below 10 nm should result in its operation in the resonant tunneling regime. The lateral resonant tunneling double gate SOI devices will be easy to realize when lithography resolution is in the sub-10nm range, which is a very demanding condition. Then, SOI transistors with additional oxide barriers between the source/drain regions and the semiconductor body can be exploited as gate controlled resonant tunneling transistors. ACKNOWLEDGMENTS

The paper has been prepared and presented with a support of the 6FP IP PULLNANO project (contract 026828).

References 1. 2.

3. 4. 5. 6.

R. Tsu and L. Esaki, Appl. Phys. Lett. Tunneling in a finite superlattice, 22, 562-564 (1973). T. C. L. G. Sollner, W. D. Goodhue, P. E. Tannenwald, C. D. Parker, and D. D. Peck, Resonant tunneling through quantum wells at frequencies up to 2.5 THz, Appl. Phys. Lett. 43, 588-590 (1983). International Technology Roadmap for Semiconductors 2005 Edition. F. G. Pikus, K. K. Likharev, Nanoscale field-effect transistors: An ultimate size analysis, Appl. Phys. Lett. 71, 3661-3663 (1997). J. P. A. van der Wagt, A. C. Seabaugh, and E. A. Beam, III, RTD/HFET low standby power SRAM gain cell, IEEE Electron Device Lett. 19, 7-9 (1998). W. Prost, V. Khorenko, A. C. Mofor, A. Bakin, E. Khorenko, S. Ehrich, H.–H. Wehmann, A. Schlachetzki, and F –J. Tegude, High-speed InP-based resonant tunneling diode on silicon substrate, Proceedings of ESSDERC, Grenoble, France, 257-260 (2005).

354 7.

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9.

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14. 15.

16. 17.

18. 19.

20.

21.

22.

RESONANT TUNNELING DEVICES ON SOI BASIS S. Miyazaki, Yohji Ihara, and M. Hirose, Resonant tunneling through amorphous silicon – silicon nitride double-barrier structures, Phys. Rev. Lett. 59 (1), 125-127 (1987). T. Suemasu, Y. Kohno, W. Saitoh, M. Watanabe, and M. Asada, Theoretical and measured characteristics of metal(CoSi2)-insulator (CaF2) resonant tunneling transistors and the influence of parasitic elements, IEEE Trans. Electron Dev. 42, 2203-2209 (1995). M. Tsutsui, M. Watanabe, and M. Asada, Resonant tunneling diodes in Si/CaF2 heterostructures grown by molecular beam epitaxy, Jpn. J. Appl. Phys. 38, L920-L922 (1999). M. Watanabe, T. Funayama, T. Teraji, N. Sakamaki, CaF2/CdF2 double-barrier resonant tunneling diode with high room temperature peak-to-valley ratio, Jpn. J. Appl. Phys. 39 L716-L719 (2000). H. K. Mosammat, M. Shahjahan, R. Ito, K. Sawada, M. Ishida, Current-voltage characteristics of γ-Al2O3/epi-Si resonant tunneling diodes, Jpn. J. Appl. Phys. 44, 4795-4798 (2005). H. C. Liu, D. Landheer, M. Buchanan, D.C. Houghton, Resonant tunneling in Si/Si1xGex double-barrier structures, Appl. Phys. Lett. 52, 1809-1811 (1988). O. G. Schmidt, U. Denker, K. Eberl, O. Kienzle, F. Ernst, R. J. Haug, Resonant tunneling diodes made up of stacked self-assembled Ge/Si islands, Appl. Phys. Lett. 77, 4341-4343 (2000). K. Ismail, B. S. Meyerson, P. J. Wang, Electron resonant tunneling in Si/SiGe double barrier diodes, Appl. Phys. Lett. 59, 973-975 (1991). Ž. Matutinović-Krstelj C. W. Liu, X. Xiao, and J. C. Sturm, Symmetric Si/Si1-xGex electron resonant tunneling diodes with an anomalous temperature behavior, Appl. Phys. Lett. 62 (6), 603-605 (1993). D. J. Paul, P. See, I.V. Zozoulenko, K.-F. Berggre, B. Kabius, B. Holländer, S. Mantl, Si/SiGe electron resonant tunneling diodes, Appl. Phys. Lett. 77, 1653-1655 (2000). P. See, D. J. Paul, B. Holländer, S. Mantl, I. V. Zozoulenko, K.-F. Berggren, High performance Si/Si1-xGex resonant tunneling diodes, IEEE Electron Device Lett. 22, 182184 (2001). P. See, D. J. Paul, The scaled performance of Si/Si1-xGex resonant tunneling diodes, IEEE Electron Device Lett. 22, 582-584 (2001). Y. Suda, H. Koyama, Electron resonant tunneling with a high peak-to-valley ratio at room temperature in Si1-xGex/Si triple barrier diodes, Appl. Phys. Lett. 79, 2273-2275 (2001). S. L. Rommel, T. E. Dillon, M. W. Dashiell, H. Feng, J. Kolodzey, P. R. Berger, P. E. Thomson, K. D. Hobart, R. Lake, A. C. Seabaugh, G. Klimeck, D. K. Blanks, Room temperature operation of epitaxially grown Si/Si0.5Ge0.5/Si resonant interband tunneling diodes, Appl. Phys. Lett. 73, 2191-2193 (1998). S. L. Rommel, T. E. Dillon, P. R. Berger, P. E. Thompson, K. D. Hobart, R. Lake, A. C. Seabaugh, Epitaxially grown Si resonant interband tunnel diodes exhibiting high current densisties, IEEE Electron Device Lett. 20, 329-331 (1999). R. Duschl, K. Eberl, Physics and applications of Si/SiGe/Si resonant interband tunneling diodes, Thin Solid Films, 380, 151-153 (2000).

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23. N. Jin, S.-Y. Chung, A. T. Rice, P. R. Berger, R. Yu, P. E. Thompson, R. Lake, 151 kA/cm2 peak current densities in Si/SiGe resonant interband tunneling diodes for highpower mixed-signal applications, Appl. Phys. Lett. 83, 3308-3310 (2003). 24. U. Auer, W. Prost, M. Agethen, F.-J. Tegude, R. Duschl, K. Eberl, “Low-voltage MOBILE logic module based on Si/SiGe interband tunneling diodes”, IEEE Electron Device Lett. 22, 215-217 (2000). 25. S. Sudirgo, R. P. Nandgaonkar, B. Curanovic, J. L. Hebding, R. L. Saxer, S. S. Islam, K. D. Hirschman, S. L. Rommel, S. K. Kurinec, P. E. Thompson, N. Jin, and P. R. Berger, Monolithically integrated Si/SiGe resonant interband tunnel diode / CMOS demonstrating low voltage MOBILE operation, Solid-State Electron. 48, 1907-1910 (2004). 26. N. Jin, S.-Y. Chung, R. M. Heyns, P. R. Berger, R. Yu, P. E. Thompson, S. L. Rommel, Tri-state logic using vertically integrated Si resonant interband tunneling diodes with double NDR, IEEE Electron Device Lett. 25, 646-648 (2004). 27. B. Majkusiak, J. Walczak, Theoretical limit for the SiO2 thickness in silicon MOS devices, Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsch Environment, ed. D. Flandre et al., Kluwer Academic Press, pp. 309-319 (2005). 28. L. Tsybeskov, G. F. Grom, R. Krishnan, L. Montes, P. M. Fauchet, D. Kovalev, J. Diener, V. Timoshenko, F. Koch, J. P. McCaffrey, J.-M. Baribeau, G. I. Sproule, D. J. Lockwood, Y. M. Niquet, C. Delerue, and G. Allan, Resonant tunneling in partially disordered silicon nanostructures, Europhysics Lett. 55, 552-558 (2001). 29. L. Montès, G. F. Grom, R. Krishan, P. M. Fauchet, L. Thybeskov, B. E. White Jr., A memory device utilizing resonant tunneling in nanocrystalline silicon superlattices, Mat. Res. Soc. Symp. Proc. 638, F2.3.1-F.2.3.6. (2001). 30. O. Ye, R. Tsu, E. H. Nicollian, Resonant tunneling via microscystalline-silicon quantum confinement, Phys. Rev. B, 44, 1806-1811 (1991). 31. D. W. Boeringer, R. Tsu, Avalanche amplification of multiple resonant tunneling through parallel silicon microcrystallites, Phys. Rev. B, 51, 13337-13343 (1995). 32. P. Normand, D. Tsoukalas, E. Kapetanakis, J. A. Van Den Berg, D. G. Armour, J. Stoemenos, Silicon nanocrystal formation in thin thermal-oxide films by very-low energy Si+ ion implantation, Microelectronic Engineering, 36, 79-82 (1997). 33. H. Mizuta, S. Oda, Bottom-up approach to silicon nanoelectronics, Proceedings of ENS'05, Paris, France, 14-16 Dec. 2005. 34. J. Caro, I. D. Vink, G. D. J. Smit, S. Rogge, T. M. Klapwijk, R. Loo, M. Caymax, Direct obervation by resonant tunneling of the B+ level in a δ-doped silicon barrier, Phys. Rev. B, 69, 125324-1-5 (2004). 35. R. H. Koch, A. Hartstein, Evidence for resonant tunneling of electrons via sodium ions in silicon dioxide, Phys. Rev. Lett. 54, 1848-1851 (1985). 36. A. Tanaka, G. Yamahata, Y. Tsuchiya, K. Usumi, H. Mizuta, and S. Oda, 5th IEEE Conference on Nanotechnology, 2005. 37. H. Namatsu, S. Horiguchi, and Y. Takahashi, M. Nagase, K. Kurihara, Fabrication of SiO2/Si/SiO2 double barrier diodes using two-dimensional Si structures, Jpn. J. Appl. Phys. 46, 3669 (1997). 38. Y. Ishikawa, T. Ishihara, M. Iwasaki, M. Tabe, Negative differential conductance due to resonant tunneling through SiO2/single-crystalline-Si double barrier structure, Electronics Letters 37, 1200-1201 (2001).

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39. H. Ikeda, M. Iwasaki, Y. Ishikawa, M. Tabe, Effect of structural imperfection on resonant tunneling in SiO2/Si diodes, Microprocesses and Nanotechnology Conference 2002, Digest of Papers, 60-61. 40. H. Ikeda, M. Iwasaki, Y. Ishikawa, M. Tabe, Resonant tunneling characteristics in SiO2/Si double-barrier structures in a wide range of applied voltage, Appl. Phys. Lett. 38 (7), 1456-1458 (2003). 41. K. W. Guarini et al. Triple-self-aligned, planar double-gate MOSFETs: devices and circuits, IEDM Tech. Dig. 425-427 (2001). 42. N. Matsuo, J. Yamauchi, Y. Kitagawa, H. Hamada, T. Miura, T. Miyoshi, Extension of physical limit of conventional metal-oxide-semiconductor transistor by double barriers formed at the channel edges, Jpn. J. Appl. Phys. 39, 3850-3853 (2000). 43. N. Matsuo, H. Kihara, Y. Takami, Application of advanced metal-oxide-semiconductor transistor in next generation, silicon resonant tunneling MOS transistor, to new logic circuit, Solid-State Electron. 47, 1969-1972 (2003). 44. K. R. Kim, D. H. Kim, S.-K. Sung, J. D. Lee, and B.-G. Park, Negative-differential transconductance characteristics at room temperature in 30-nm square-channel SOI nMOSFETs with a degenerately doped body, IEEE Electron Device Lett. 23, 612-614 (2002). 45. K. R. Kim, D. H. Kim, K,-W. Song, G. Baek, H. H. Kim, J. I. Huh, J. D. Lee, B.-G. Park, Silicon-based field-induced band-to-band tunneling effect transistor, IEEE Electron Device Lett. 25, 439-441 (2004). 46. S.-H. Song, K. R. Kim, S. Kang, J. H. Kim, J. I. Huh, K. C. Kang, K.-W. Song, J. D. Lee, B.-G. Park, Analytical modeling of field-induced interband tunneling-effect transistors and its application, IEEE Trans. Nanotechnology, 5, 192-199 (2006). 47. B. Majkusiak, Theoretical modeling of the double gate MOS resonant tunneling diode, 4th European Workshop on Ultimate Integration of Silicon ULIS, Udine, Italy, March 2003, Proceedings 147-150. 48. C.-H. Choi, Z. Yu, R. W. Dutton, Resonant gate tunneling current in double-gate SOI: A simulation study, IEEE Trans. Electron Dev. 50, 2579-2581 (2003). 49. B. Majkusiak, J. Walczak, Silicon Resonant Tunneling Devices – Theoretical Study, Nanoelectronics Days 2005, Jülich, Germany, Feb. 2005, Abstract Book, 83-84. 50. B. Majkusiak, Modeling the inelastic scattering effect on the resonant tunneling current, J. Computational Electronics, in print.

MOBILITY MODELING IN SOI FETS FOR DIFFERENT SUBSTRATE ORIENTATIONS AND STRAIN CONDITIONS VIKTOR SVERDLOV*, ENZO UNGERSBOECK, HANS KOSINA Institute for Microelectronics, TU Wien, Gusshaussstrasse 2729/E-360, A-1040 Wien, Austria * Viktor Sverdlov, Institute for Microelectronics, TU Wien, Gusshausstrasse 27-29/E-360, A-1040 Wien, Austria

Abstract. Conduction band modification due to shear stress is investigated. Mobility in single- and double-gate SOI FETs is modeled for silicon thin body orientation (001) and (110) under general stress conditions. Decrease of conductivity mass induced by uniaxial [110] tensile stress leads to mobility enhancement in the stress direction in ultra-thin body SOI MOSFETs.

Keywords: mobility modeling, Monte Carlo simulations, SOI FET, stress engineering, hybrid orientation

1. Introduction Mobility in ultra-thin body (UTB) FETs in double-gate (DG) and singlegate (SG) configuration has recently been the subject of intensive experimental1,2 and theoretical3,4 studies. Mobility in DG devices is expected to be enhanced compared to the mobility in SG FETs, due to volume inversion5. Recent experiments2 have confirmed that the DG mobility is indeed higher than the SG mobility in (110) UTB FETs over the whole range of inversion charge concentrations. Contrary to predictions of the volume inversion hypothesis5 however, the mobility in (100) UTB DG FETs is lower than the SG mobility at high carrier concentrations1,2. In order to resolve the apparent controversy, an accurate mobility modeling in UTB FETs is required for different substrate orientations, both in DG and SG structures.

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Additional process steps to induce uniaxial strain along the MOSFET channel have recently become routinely used by the semiconductor industry. Surprisingly, stress along [110] has received little attention within the research community. Only recently a systematic experimental study of the mobility modification due to stress in [110] was reported6. It was demonstrated that the electron mobility data under [110] stress condition is consistent with the conductivity mass being a function of the stress value. Since stress engineering is becoming an established technique to enhance performance of modern MOSFETs, it is important to include appropriate models into modern simulation tools. 2. Uniaxial stress and conduction band structure The [110] stress produces off-diagonal elements ε xy in the strain tensor, which lift the degeneracy between the two lowest conduction bands at the X points along the [001] axis in the Brillouin zone7. As a result, the conduction band minimum moves closer to the X point, and shifts down in energy with respect to the four remaining degenerate valleys. Uniaxial stress also modifies longitudinal and transversal effective masses in the [001] valleys. Results of simulations of the transversal mass dependences

Figure 1. Transversal mass changes in valleys along the [001] axis as a function of the shear component of the strain tensor due to uniaxial [110] tensile stress. Results of the empirical pseudopotential method (symbols) are compared to Eq. (1) (dashed lines). Closed squares describe the conductivity mass reduction in the [110] tensile stress direction

MOBILITY MODELING IN SOI FETs

359

on tensile stress in [110] direction using the empirical pseudopotential method8 are shown in Fig. 1, together with analytical expressions

mt (η ) / mt = [1 ± η mt / M ] , | η |≤ 1 ;

(1a)

mt (η ) / mt = [1 ± mt / M ] , | η |≥ 1 ,

(1b)

−1

−1

where η = 2 Dε xy / ∆ , ∆ is the conduction band splitting at the minimum in unstrained Si, and D is the shear deformation potential, and M = m0/4.4 is a parameter. The sign “+” corresponds to the mass decrease along the [110] stress direction, while the sign “-” – in [-110] direction. 3. Method We have used a subband Monte Carlo algorithm to compute the electron mobility in thin silicon films. The algorithm includes degeneracy effects9, which are of major importance in UTB FETs, especially at high effective fields. We included electron-phonon and surface roughness scattering. The surface roughness is assumed uncorrelated and equal at opposite UTB film interfaces. 4. Results Figure 2 shows the mobility calculated in a thick silicon film for (100) and (110) substrate orientations. For a 20 nm thick film the mobility in SG mode coincides with the DG mobility, plotted as function of the concentration per channel. Mobility is isotropic for (100) substrate orientation, whereas for (110) a clear anisotropy is displayed. Results of simulations are in good agreement with the experimental data1,2 also shown in Fig. 2. We apply uniaxial strain of 0.1 GPa and 1.0 GPa along [110] direction to a thick (001) oriented Si film. Figure 3 demonstrates that the in-plane mobility enhancement is maximal along the strain direction. In the in-plane direction orthogonal to the strain, the mobility enhancement is less pronounced and may change sign depending on carrier concentration. The enhancement is clearly anisotropic. Similar anisotropic mobility enhancement under [110] uniaxial stress was recently observed experimentally10. This anisotropy cannot be explained by the higher subband depopulation due to strain since the ground subband is isotropic, which would inevitably result in isotropic mobility. Therefore, the anisotropic mobility enhancement is due to conductivity mass anisotropy produced by [110] strain as illustrated in Fig. 1.

360

MOBILITY MODELING IN SOI FETs

Figure 2. Simulated mobility for a 20 nm thick Si body compared to measurements1,2 (symbols), for (110) and (110) substrate orientation

Figure 3. Channel mobility enhancement in 20 nm thick (100) Si film for two values of uniaxial stress along [110]

Mobility dependencies on charge concentration for (110) substrate are shown in Fig. 4. Mobility, which is anisotropic, is only shown in <001> direction, for different silicon thicknesses. Due to volume inversion5 the mobility in DG operation is higher for all NS than the SG mobility, in good agreement with experimental data2. Finally, we study the influence of strain

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361

on UTB FET mobility. Results of mobility calculations for [110] uniaxial stress are shown in Fig. 5 for two (001) oriented Si body thicknesses. Due to the change of the effective masses (Fig. 1) induced by strain a substantial

Figure 4. Mobility for (110) substrate in <001> direction, for different silicon body thicknesses. Mobility in DG operation is higher for all NS, in qualitative agreement with recent experiments2

Figure 5. Mobility for [110] uniaxial stress in (001) UTB Si films. Substantial mobility modify

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MOBILITY MODELING IN SOI FETs

in-plane mobility modulation is observed even at 2.4 nm thick Si film. Uniaxial stress is a promising technique for mobility engineering in UTB FETs. 5. Conclusion Effective mass dependences on the strength of uniaxial [110] stress in the valleys along the [001] direction are analyzed both theoretically and computationally using the empirical pseudopotential method. Mobility in single- and double-gate SOI FETs is modeled for different Si thin body orientation under general stress conditions. Good agreement with recent experiment is found for ultra-thin body (110) orientated FETs. It is shown that uniaxial [110] tensile stress reduces the conductivity mass and leads to mobility enhancement in the stress direction in ultra-thin body SOIFETs. ACKNOWLEDGEMENTS

This work was supported in part by the Austrian Science Fund FWF, project P17285-N02.

References 1. 2. 3.

K. Uchida, J. Koga, and S. Takagi, in: IEDM Techn. Dig. (2003), pp. 805-808. G. Tsutsui et al., in: IEDM Techn. Dig. (2005), pp. 747-750. F. Gamiz et al., Electron mobility in double gate silicon on insulator transistor: symmetric gate versus asymmetric gate configuration, J. Appl. Phys. 94(9), 5732-5741 (2003). 4. D. Esseni et al., Physically based modeling of low-filed electron mobility in ulrathin single- and double-gate SOI n-MOSFETs, IEEE Trans. Electron Devices, 50(12), 24452455 (2003). 5. F. Balestra et al., Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance, IEEE Electron Device Lett., 8(9), 410412 (1987). 6. K. Uchida et al., in: IEDM Techn. Dig. (2005), pp. 135-138. 7. J.C. Hensel, H. Hasegawa, and M. Nakayama, Cyclotron resonance in uniaxially stressed silicon. II. Nature of the covalent bond Phys.Rev., 138, A225-A238 (1965). 8. M. Rieger and P. Vogl, Electronic-band parameters in strained Si1-xGex alloys on Si1yGey substrates, Phys.Rev., B48, 14275-14287 (1993). 9. S. Smirnov et al., Monte Carlo modeling of small signal response including the Pauli exclusion principle, J.Appl.Phys., 94(9), 5791-5799 (2003). 10. H. Irie et al., in: IEDM Techn, Dig. (2004), pp. 225-228.

THREE-DIMENSIONAL (3-D) ANALYTICAL MODELING OF THE THRESHOLD VOLTAGE, DIBL AND SUBTHRESHOLD SWING OF CYLINDRICAL GATE ALL AROUND MOSFETS H.A. EL HAMID1*, B. IÑIGUEZ1, JAUME ROIG2 Departament d’Enginyeria Electrònica, Elèctrica i Automàtica, Universitat Rovira i Virgili, Tarragona, Spain. 2 LAAS / CNRS, 7 avenue du Colonel Roche, 31077 Toulouse Cedex 4, France

1

* Presenting author. Tel: +34977558521. Fax:+34977559605. E-mail: [email protected].

Abstract. We present 3-D analytical, scalable models for the threshold voltage roll-off, the subthreshold swing and the DIBL of undoped cylindrical Gate All Around (GAA) MOSFETs. The models are based on an analytical solution of the 3-D Poisson equation. Device geometry dependences are inherent to the models. Excellent agreement has been obtained with 3-D numerical simulations and experimental results.

Keywords: Gate All Around MOSFET, short-channel effects, 3-D modeling, scalability

1. Introduction The Gate All Around (GAA) MOSFET is considered one the most promising devices for downscaling below 50nm [1-3]. By surrounding the channel completely, the gate increases its electrostatic control of the channel and short-channel effects can be drastically reduced. However, even in GAA MOSFET devices, Short Channel Effects (SCE) such as the threshold voltage roll-off, the drain induced barrier lowering (DIBL) and the subthreshold swing degradation, cannot be neglected for channel lengths below 100nm. Compact and accurate models of the threshold voltage (including DIBL) and the subthreshold swing are needed in order to facilitate the use of these devices in nanoscale integrated circuits. A three-dimensional analysis is

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364 ANALYTICAL MODELING OF SCE IN CYLINDRICAL MOSFETS

necessary to derive threshold voltage and subthreshold swing models that properly account for the channel length dependence. A few 2-D models of the threshold voltage for doped [4] and undoped [5] GAA MOSFETs have been presented; however, all of them neglect the effect of the mobile charge density, which can be important in the near-threshold regime and in particular for undoped devices. In this paper, we present a 3-D model for the threshold voltage, and subthreshold swing of a cylindrical GAA MOSFET including the effect of the mobile charge density. The dependences of channel length, thickness and drain-source voltage are accounted for. We observe a quite good agreement with the results obtained from 3-D numerical simulations with DESSIS-ISE for different channel lengths/thickness and from low to high drain-source voltage values. 2. Derivation of the electrostatic potential model Figure 1 shows the cross section of the undoped cylindrical GAA-MOSFET considered in this work. The channel electrostatics for undoped devices is governed by the Poisson equation with only the mobile charge term included:

∇ 2φ (r , x) =

q

ε Si

n.

(1)

The electron density is given by n = ni e (φ −φ F ) / VT , where ni is intrinsic electron density in silicon, VT is the thermal voltage, and φ F is the quasiFermi level referred to the Fermi level in the source, satisfying the boundary conditions: φ F (0, r ) = 0 , φ F ( L, r ) = V DS . The boundary conditions for φ are given by: φ (0, r ) = Vbi , φ (0, r ) = Vbi and Cox (VGS − φMS − φ ( x, r0 )) = ε Si

∂φ ( x, r ) , ∂r r = r0

(2)

where VGS is the gate voltage, φMS is the gate work function referenced to intrinsic silicon, ro is the device radius, and Vbi is the built-in voltage. In subthreshold, the quasi-Fermi potential can be considered to have its value at the source end in most of the channel [3]. Therefore, in the 2-D Poisson’s equation we can use the expression of the electron density with φF = 0 , n = ni eφ ( x ,r ) /VT .

ANALYTICAL MODELING OF SCE IN CYLINDRICAL MOSFETS 365 gate insulator

Drain

x

Source Source

(a)

r Surrounding gate

Vgs Surrounding gate tox ro

r

(b)

Source n+

φ(x,r)

Drain n+

x

L

r=ro, x=L

r=ro, x=0

Surrounding gate

Vds

tox

Vgs

Figure 1. Cylindrical GAA-MOSFET considered in this work, a) 3-D device structure, and b) Cross section.

The potential can be written as the sum of two terms: φo(r), which is the solution of the 1D Poisson’s equation in the radial direction, and φ1(x,r), which is the solution of the residual 2D differential equation :

φ ( x, r ) = φ0 (r ) + φ1 ( x, r ) .

(3)

Analytical expressions are obtained for both φ0 (r ) , and φ1 ( x, r ) under the assumption that φ1 ( x, r ) VT is small), and therefore, for the electrostatic potential. 3. Threshold voltage model Having determined the electrostatic potential distribution, we can now obtain an analytical expression for the location of the channel at which the potential reaches its minimum value, xmin , and also the minimum potential. In undoped devices the threshold voltage, VTH , is defined as the gate voltage necessary to reach a certain value of the mobile charge sheet density, QTH [6]. It has been found numerically (using 3-D simulations) to be ~ 1012cm-2. The mobile charge sheet density, Qinv is obtained by integrating its spatial density throughout the entire channel diameter at the channel location where the potential is minimum,

366 ANALYTICAL MODELING OF SCE IN CYLINDRICAL MOSFETS r0

⎡

r⎤ r0 ⎦

φ ⎢ xmin , ⎥ VT

Qinv = 2 ∫ ni e

⎣

dr .

(4)

0

After some mathematical manipulations, we obtain: ⎛ ⎞ ⎛ Q ⎞ VTH = φ + ⎜V ln ⎜ TH ⎟ − S ⎟ ⎛⎜1 − S ⎞⎟ , gs ⎠ ms ⎜ T ⎜ 2n ⋅ r0 ⎟ ds ⎟ ⎝ ⎝ i ⎠ ⎝ ⎠

(5)

where Sds and Sgs are analytical functions of the applied bias. As observed in Fig. 2 and Fig. 3, very good agreement with the 3-D simulations has been obtained for the threshold voltage roll-off and the DIBL coefficient, respectively.

Figure 2. Threshold Voltage roll-off vs. channel length. Cylindrical GAA MOSFET with different channel radius, tox=1.5nm, VDS=10mV.

Figure 3. Drain Induced Barrier Lowering coefficient vs. channel length, for different channel radius, tox=2nm.

ANALYTICAL MODELING OF SCE IN CYLINDRICAL MOSFETS 367

4. Subthreshold swing model The subthreshold swing, S, can be expressed as: S=

⎡ r0 ∂VGS ∂φ = ⎢ ∫ n m ( r ) min dr ∂ log I D ⎢ r = 0 ∂VGS ⎣

−1

⎤ ∫ n m ( r )dr ⎥ VT ln(10) ⎥⎦ r =0 r0

(6)

where nm (r ) = ni ⋅ eφmin / VT . The integrals in (6) can be approximated by their values at 0.5r0. After some mathematical manipulations, we obtain: S = VT (1 − S gs ) ⋅ ln(10) .

(7)

A good agreement is observed between our model (7) and 3-D simulation results for different channel lengths (Fig. 4) down to 30 nm.

Figure 4. Subthreshold swing for GAA MOSFET with tox=2nm, Vds=10mV.

5. Conclusion In this paper, 2-D scalable models are presented for the threshold voltage, including the DIBL effect, and the subthreshold swing for GAA MOSFETs. Solving the 2-D Poisson equation, a potential profile is obtained analytically. From the value of the minimum of this potential we have derived our expressions for the threshold voltage and subthreshold swing. Good agreement has been observed with numerical 3-D simulations for a good range of channel lengths, diameters, and drain-source voltage values.

368 ANALYTICAL MODELING OF SCE IN CYLINDRICAL MOSFETS

References 1.

2.

3.

4.

5.

6.

C. H. Wann, K. Noda, T. Tanaka, M. Yoshida and C. Hu, “A comparative study of advanced MOSFET concepts,” IEEE Trans. Electron Devices, vol. 43, no. 10, pp. 1742-1753, Oct. 1996. S.–H. Oh, D. Monroe and J. M. Hergenrother, “Analytic description of short-channel effects in fully-depleted Double-Gate and Cylindrical, Surrounding-Gate MOSFETs”, IEEE Electron Device Letters, vol. 21, no. 9, pp. 445–447, September. 2000. B. Iñíguez, D. Jiménez, J. Roig, and H. A. Hamid “Explicit Continuous Model for Long-Channel Undoped Surrounding Gate MOSFETs,” IEEE Trans. on Electron Devices, vol. 52, no. 8, pp. 1868-1872, August 2005. Kranti A, Haldar S, Gupta RS Analytical model for threshold voltage and I-V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET Microelectronic Engineering 56 (3-4): 241-259 August 2001. H. Lu and Y. Taur, “Physics-based, non charge-sheet compact modeling of DoubleGate MOSFET”, Proc. Of the Workshop on Compact Modeling (WCM), Anaheim, CA (USA), May 2005. Q. Chen, B. Agrawal and J. D. Meindl, “A Comprehensive Analytical Subthreshold Swing Model for Double-Gate MOSFETs,” IEEE Trans. on Electron Devices, vol. 49, no. 6, pp. 1086-1090, June 2002.

AUTHORS INDEX

Lysenko V..................................... 251 Majkusiak B. ................................. 341 Mitrovic I.Z............................. 33, 171 Mollenhauer T................................. 89 Mubarek, El, H.A.W............... 73, 171 Nazarov A. ............................ 199, 251 Novikov P.L.................................. 113 Olbrechts B. .................................... 89 Orlikovsky A................................. 323 Pailloncy G.................................... 221 Passi V. .......................................... 89 Patruno P. ...................................... 159 Perera A.H..................................... 239 Popov V........................................... 59 Raskin J.-P. ............................. 89, 221 Reckinger N. ................................. 251 Roig J. ........................................ 363 Rudenko T..................................... 199 Sampedro C................................... 303 Samsudin K................................... 259 Schrüfer K. .................................... 159 Schulz T. ....................................... 159 Semenikhin I. ................................ 323 Stepina N.P.................................... 113 Sverdlov V. ................................... 357 Tang X. ........................................ 251 Tyschenko I..................................... 59 Ungersboeck E.............................. 357 Voelskow M.................................... 59 Vyurkov V. ................................... 323 Wahlbrink T. ................................... 89 Xiong W................................ 159, 165 Yakimov A.I. ................................ 113 Zaouia S. ....................................... 239 Zhang J. ........................................ 171

Asenov A. ......................................259 Ashburn P. ...............................73, 171 Balestra F...........................................3 Bayot V. .........................................251 Bolten J. ...........................................89 Buiu O. ...................................33, 171 Cherkov A. ......................................59 Cleavelin C.R. .......................159, 165 Colinge C.A...................................165 Colinge J.-P. ................. 129, 159, 165 Collaert N. .....................................199 Cristoloveanu S. ............................239 Davey W.M. ....................................33 Dvurechenskii A.V........................113 Flandre D. ..............................199, 221 Gámiz F. ........................................303 Godoy A. .......................................303 Gottlob H.D.B. ................................19 Hall S. ...................................33, 171 Hamid, El, H. A.............................363 Hiramoto T. .....................................97 Iñiguez B........................................363 Jurczak M. .....................................199 Khomyakov A. ..............................323 Kilchytska V..........................199, 221 Kirienko V.V. ................................113 Knoch J. .........................................143 Kosina H. .......................................357 Kurz H. .....................................19, 89 Lederer D.......................................221 Lemme M.C...............................19, 89 Levacq D........................................221 Lu Y. ...........................................33 Lukichev V. ...................................323 Lukyanchikova N. .........................181 Lüth H. .........................................143

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