RF and Microwave Microelectronics Packaging

Ken Kuang · Franklin Kim · Sean S. Cahill Editors

RF and Microwave Microelectronics Packaging

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Editors Ken Kuang Torrey Hills Technologies, LLC 6370 Lusk Blvd, F-111 San Diego CA 92121 USA [email protected]

Franklin Kim Kyocera America, Inc. 8611 Balboa Avenue San Diego CA 92123 USA [email protected]

Sean S. Cahill BridgeWave Communications Inc. 3350 Thomas Road Santa Clara CA 95054 USA [email protected]

ISBN 978-1-4419-0983-1 e-ISBN 978-1-4419-0984-8 DOI 10.1007/978-1-4419-0984-8 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2009939146 © Springer Science+Business Media, LLC 2010 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)

Preface

This book is an outgrowth of the first IMAPS (International Microelectronics and Packaging Society) Advanced Technology Workshop on RF/Microwave Packaging, held September 16–18, 2008 in San Diego, California. Wireless technologies have undergone tremendous growth in the last decade and the interest in packaging for high-frequency applications has grown as well. Over 30 invited speakers gave presentations on select advanced topics in RF, microwave, millimeter-wave and broadband packaging. The motivation behind this conference, however, goes beyond the obvious areas of utility. When referring to fundamental engineering limits to very high speed electronics, packaging and interconnect constraints figure significantly. Ever increasing data rates are transforming digital technologies into what are essentially RF systems. The once arcane tools of the RF discipline are becoming increasingly applicable to electronic systems in general, motivating many new considerations. RF systems, despite their small device count, have traditionally been voracious, inefficient consumers of power, creating significant challenges for packaging engineers to deal with heat dissipation. Most digital devices have been much more frugal, but speed and high levels of integration turn these devices into significant heat sources as well. In light of these evolutionary trends, a sampling of the workshop participants were asked to submit chapters on these fascinating areas of development for the work at hand. Given the diversity of voices at this workshop, and the highly interdisciplinary nature of the topics discussed, this work ranges broadly. Authors include academics, students, large industrial concerns and small entrepreneurial ventures covering a variety of areas such as performance fundamentals, design considerations, novel structures, manufacturing methods, and advanced materials. Although some of the information included here may be of particular use to those studied in a specific discipline, an effort has been made to convey large portions of the information in a way accessible to an audience with general knowledge of electronic packaging. Chapter 1 introduces the topic with a look at the fundamentals underlying design and performance trade-offs and the additional complexities encountered at microwave and millimeter wave frequencies. In these regimes, even simple interconnects like wire bonds must be considered as complex circuit elements.

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Chapter 2 introduces a new interconnect approach that allows low-cost highvolume packaging philosophies to be translated into the high-frequency domain. This development will have implications for digital electronic packaging as well. Chapter 3 shows a possible path for making millimeter wave passive components with a high-volume production approach. This innovation may enable much more pervasive penetration of millimeter wave systems into consumer and other cost sensitive applications. Chapter 4 gives some pointers on how low cost is achieved through chip-onboard integration and packaging for millimeter wave electronics and then discusses the particular problems of millimeter-wave circuit performance. Chapter 5 presents the design and development of thin-film liquid crystal polymer (LCP) surface mount packages for X, K, and Ka-band applications. Constructed using multi-layer LCP films, the packages are surface mounted on a printed circuit board (PCB). Packages include a typical low pass feedthrough design, as well as a new bandpass feedthrough design. Chapter 6 reviews the design options and the materials available to make portable products and discusses ways to meet packaging density and performance needs. The material discussion focuses on types of organic materials used in portable products and techniques to make PWBs thinner, lighter and cost effective. Chapter 7 shows how advances in ceramic materials and processing are permitting the creation of increasingly complex multi-layer structures. Going beyond simple routing structures, these ceramics become device elements, and critical packaging for micro-electro-mechanical RF systems. Chapter 8 discusses Laminated Waveguides, characterizing them numerically, and addressing issues in material and process tradeoffs arising when considering interconnects on a common substrate at mm-wave frequencies with regards to insertion loss and isolation between interconnects. Numerical simulations illustrate the trade-offs using laminated waveguide or common stripline in the same material set. Chapter 9 shows the latest developments in both simulation and fabrication of LTCC for RF/MW packaging applications. It reviews current LTCC fabrication methods and discusses the trend for RF/MW System in Package modules, high bandwidth design and integrated antenna. Chapter 10 discusses advances in thermally dissipative composite materials. The discussion covers constituents such as carbon nanotubes, diamond composites, and puts some new spin on well-known materials such as aluminum nitride and beryllium oxide. Chapter 11 reviews the heat sink material fabrication, application and development for RF/MW packaging. The discussion covers the traditional, second and third generations of heat sink materials. Chapter 12 reviews the latest development of AlN 3D MCM technology for RF/MW packaging. The discussion covers the AlN HTCC process, matching with various tungsten pastes, impact of firing profiles and other practical design and manufacturing issues. We, the editors, give profuse thanks to all of the contributing authors, not just for making the effort to inform all of us, but for jumping numerous administrative

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hurdles at their various institutions to bring these advances to print. We also would like to thank Mr. Nick Zhou for his help in formatting the draft chapters and in converting all figures to grey scale photos. Lastly we would like to thank Steve Elliot and Andrew Leigh from Springer for their consistent support during the long journey to edit this book. Our involvement with these knowledgeable and informative folks has made the undertaking a great pleasure. It is our sincere hope that the information conveyed here will illuminate the efforts of subsequent investigators, and inspire technological advances that will have a positive impact for our world.

Contents

1 Fundamentals of Packaging at Microwave and Millimeter-Wave Frequencies . . . . . . . . . . . . . Rick Sturdivant 1.1 Wavelength and Frequency . . . . . . . . . . . . . . 1.2 Lumped Elements . . . . . . . . . . . . . . . . . . 1.3 Transmission Lines . . . . . . . . . . . . . . . . . . 1.3.1 Dispersion . . . . . . . . . . . . . . . . . . 1.3.2 Dispersion Effects in High Speed Systems . 1.3.3 Transmission Line Distributed Effects . . . 1.3.4 Transmission Line Coupling and Cross Talk 1.4 Package Fabrication Methods . . . . . . . . . . . . 1.4.1 Co-fired Ceramics . . . . . . . . . . . . . . 1.4.2 Thick Film and Thin Film Ceramics . . . . 1.4.3 Organic Substrates . . . . . . . . . . . . . 1.5 Interconnects . . . . . . . . . . . . . . . . . . . . . 1.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . .

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3 Polymeric Microelectromechanical Millimeter Wave Systems . . . Yiin-Kuen Fuh, Firas Sammoura, Yingqi Jiang and Liwei Lin 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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2 Low-Cost High-Bandwidth Millimeter Wave Leadframe Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . Eric A. Sanjuan and Sean S. Cahill 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . 2.2 MicroCoax Approach . . . . . . . . . . . . . . . . . 2.2.1 Packaging Approaches . . . . . . . . . . . 2.2.2 Limitations to the Approach . . . . . . . . 2.3 MicroCoax/Leadframe Approach . . . . . . . . . . 2.3.1 Package I/O Structure Considerations . . . 2.3.2 Modelling the Signal Path . . . . . . . . . . 2.3.3 Performance . . . . . . . . . . . . . . . . . 2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . .

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Polymeric Millimeter Wave Systems using Micromachining Technologies . . . . . . . . . . . . . . . . . . 3.3 Fabrication Examples of mm-Wave Components . . . . . . . . 3.3.1 Polymeric Waveguides . . . . . . . . . . . . . . . . . 3.3.2 Waveguide-Based Iris Filters . . . . . . . . . . . . . . 3.3.3 Waveguide-Based Tunable Filters and Phase Shifters . 3.3.4 Waveguide-Fed Horn Antennas . . . . . . . . . . . . . 3.3.5 W-Band Waveguide Feeding Network of a 2×2 Horn Antenna Array . . . . . . . . . . . . . . . . . . 3.4 Fundamental Characterizations of Polymer Metallization Process 3.4.1 Surface Roughness . . . . . . . . . . . . . . . . . . . 3.4.2 Characterization of In-channel Electroplating Thickness 3.4.3 Geometry Effects . . . . . . . . . . . . . . . . . . . . 3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Millimeter-Wave Chip-on-Board Integration and Packaging . . . . Edward B. Stoneham 4.1 Motivation for a Chip-on-Board Approach for Millimeter-Wave Product Manufacturing . . . . . . . . . . . . 4.1.1 The Drive for Low Cost . . . . . . . . . . . . . . . . . 4.1.2 Low-Cost Manufacturing Processes . . . . . . . . . . 4.1.3 Problems Specific to Millimeter-Wave Electronics . . . 4.2 A Chip-on-Board Solution . . . . . . . . . . . . . . . . . . . . 4.2.1 The Surface-Mount Panel . . . . . . . . . . . . . . . . 4.2.2 Attaching the Bare Chips . . . . . . . . . . . . . . . . 4.2.3 Wire Bond Interconnects . . . . . . . . . . . . . . . . 4.2.4 Eliminating Wire Bonds in the RF Path . . . . . . . . . 4.2.5 Cover Lamination . . . . . . . . . . . . . . . . . . . . 4.2.6 Segregation . . . . . . . . . . . . . . . . . . . . . . . 4.2.7 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Application Examples . . . . . . . . . . . . . . . . . . . . . . 4.3.1 A 60-GHz Transceiver . . . . . . . . . . . . . . . . . 4.3.2 Miniaturized 60-GHz Transmitter and Receiver Modules 4.3.3 76-GHz Automotive Radar Module Package . . . . . . 4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Liquid Crystal Polymer for RF and Millimeter-Wave Multi-Layer Hermetic Packages and Modules . . . . . . . Mark P. McGrath, Kunia Aihara, Morgan J. Chen, Cheng Chen, and Anh-Vu Pham 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 5.2 Design and Fabrication of the Thin-Film LCP Package 5.3 Lid Construction and Lamination . . . . . . . . . . . 5.4 Results and Model of Lowpass Feedthrough . . . . . .

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Hermeticity and Leak Rate Measurement . . . . . . . . Reliability of LCP Surface Mount Packages . . . . . . . 5.6.1 Non-operating Temperature Step Stressing . . . 5.6.2 Non-operating Thermal Shock Testing . . . . . 5.6.3 Operating Humidity Exposure Testing . . . . . 5.6.4 Reliability Testing Summary . . . . . . . . . . 5.7 Bandpass Feedthrough . . . . . . . . . . . . . . . . . . 5.7.1 Bandpass Feedthrough Design and Fabrication . 5.7.2 Bandpass Feedthrough Results and Discussion . 5.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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7 Ceramic Systems in Package for RF and Microwave . . . . . . . . Thomas Bartnitzek, William Gautier, Guangwen Qu, Shi Cheng, and Afshin Ziaei 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 RF-PLATFORM . . . . . . . . . . . . . . . . . . . . . . . . .

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6 RF/Microwave Substrate Packaging Roadmap for Portable Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mumtaz Bora 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Substrate Materials for Portable Products . . . . . . . . 6.3 RF Substrate Materials Thermal and Electrical Properties 6.3.1 Standard FR-4 . . . . . . . . . . . . . . . . . . 6.3.2 High TG FR-4 . . . . . . . . . . . . . . . . . . 6.3.3 Polyimide . . . . . . . . . . . . . . . . . . . . 6.4 Cyanate Ester Blend (BT- Bismaleamide Triazine) . . . 6.5 PTFE Based Laminates . . . . . . . . . . . . . . . . . . 6.5.1 PTFE Resin Coated on Conventional Glass . . 6.5.2 PTFE Film Impregnated with Cyanate Ester or Epoxy Resin . . . . . . . . . . . . . . . . . . . 6.5.3 PTFE Mixed with Low Dk Ceramic . . . . . . 6.6 Materials Summary . . . . . . . . . . . . . . . . . . . . 6.7 Substrate Critical Properties . . . . . . . . . . . . . . . 6.7.1 Dielectric Constant (Dk) . . . . . . . . . . . . 6.7.2 Dissipation Factor/Dielectric Loss: (tan δ) . . . 6.7.3 Glass Transition Temperature (Tg) . . . . . . . 6.7.4 Glass Decomposition Temperature; Td . . . . . 6.7.5 Moisture Absorption . . . . . . . . . . . . . . 6.7.6 Coefficient of Thermal Expansion . . . . . . . 6.8 Materials Summary . . . . . . . . . . . . . . . . . . . . 6.9 Portable Products Technology Roadmap . . . . . . . . . 6.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 Summary . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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7.2.1 7.2.2 7.2.3 7.2.4 7.2.5

LTCC for Systems in Package . . . . . . . . . . . . . Design of Ceramic Packages . . . . . . . . . . . . . . Why Multi-Project Wafers Made of LTCC? . . . . . . Hermetic Capping of MEMS with Ceramic Lids . . . . LTCC Packages for Advanced RF and Microwave Applications . . . . . . . . . . . . . . . . 7.3 Three Examples . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 4 by 4 Patch Antenna Array for Operation at 35 GHz . 7.3.2 LTCC for 77–81 GHz Automotive Radar Systems-in-Package . . . . . . . . . . . . . . . . . . . 7.3.3 24 GHz Switched Beam Steering Array Antenna Based on RF MEMS Switch Matrix . . . . . . 7.4 RF-MEMS for Radar and Telecom Applications . . . . . . . . 7.4.1 Research Activities and Trends on RF-MEMS Switches References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Low-Temperature Cofired-Ceramic Laminate Waveguides for mmWave Applications . . . . . . . . . . . . . . . . . . Jerry Aguirre 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 8.2 The Laminated Waveguide . . . . . . . . . . . . . . . 8.3 Transitions to a LWG . . . . . . . . . . . . . . . . . . 8.4 Rectangular Waveguide Theory . . . . . . . . . . . . 8.5 LTCC Process . . . . . . . . . . . . . . . . . . . . . 8.6 Insertion Loss in an LTCC Laminated Waveguides . . 8.7 U- band . . . . . . . . . . . . . . . . . . . . . . . . . 8.8 V-band . . . . . . . . . . . . . . . . . . . . . . . . . 8.9 E-band . . . . . . . . . . . . . . . . . . . . . . . . . 8.10 W-band . . . . . . . . . . . . . . . . . . . . . . . . . 8.11 F-band . . . . . . . . . . . . . . . . . . . . . . . . . 8.12 LWG-to-LWG Coupling . . . . . . . . . . . . . . . . 8.13 LWG vs. Stripline . . . . . . . . . . . . . . . . . . . 8.14 Summary . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 LTCC Substrates for RF/MW Application Jian Yang and ZiliangWang 9.1 Introduction . . . . . . . . . . . . . . 9.2 LTCC Fabrication Process . . . . . . 9.3 Current Status and Trend . . . . . . . References . . . . . . . . . . . . . . . . . . 10

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High Thermal Dissipation Ceramics and Composite Materials for Microelectronic Packaging . . . . . . . . . . . . . . . Juan L. Sepulveda and Lee J. Vandermark 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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10.2

Ceramics and Carbon Based Materials . . . . . . . . . . . . 10.2.1 Common Packaging Ceramics . . . . . . . . . . . 10.2.2 LTCC . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 High Performance Packaging Ceramics (BeO AlN) 10.3 Direct Bond Copper (DBC) Packaging . . . . . . . . . . . . 10.4 RF/MW Brazed Packages . . . . . . . . . . . . . . . . . . 10.5 Thin-Film Packaging . . . . . . . . . . . . . . . . . . . . . 10.6 Thick-Film Packaging . . . . . . . . . . . . . . . . . . . . 10.7 Carbon Nanotubes (CNT) . . . . . . . . . . . . . . . . . . 10.8 Composites . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8.1 Metal Matrix Composites . . . . . . . . . . . . . . 10.8.2 Cu/cBN Composites . . . . . . . . . . . . . . . . 10.8.3 Cu/SiC Composites . . . . . . . . . . . . . . . . . 10.8.4 Al/Diamond Composites . . . . . . . . . . . . . . 10.9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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High Performance Microelectronics Packaging Heat Sink Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jiang Guosheng, Ken Kuang, and Danny Zhu 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Refractory Metal Based Microelectronics Packaging Materials 11.2.1 Development, Manufacturing and Application of Copper Tungsten . . . . . . . . . . . . . . . . . . 11.2.2 Development, Manufacturing and Application of Copper Molybdenum (MoCu) . . . . . . . . . . . 11.2.3 Development, Manufacturing and Application of Copper-Molybdenum-Copper Laminates and Copper-Copper/Molybdenum-Copper Laminates 11.3 Aluminum Based Heat Sink Materials . . . . . . . . . . . . . 11.3.1 AlSiC Heat Sink Materials . . . . . . . . . . . . . . 11.4 New Development for Microelectronics Packaging Heat Sink Materials . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technology Research on AlN 3D MCM . . . . . . . . . . . Zhang Hao, Cui Song, and Liu Junyong 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 12.2 Experiment . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 Co-fired Spacer Rod and 2D MCM Substrate 12.2.2 Vertical Interconnected by BGA Solder Ball . 12.2.3 AlN 3D MCM Package . . . . . . . . . . . . 12.2.4 Technological Method . . . . . . . . . . . . 12.3 Result and Discussion . . . . . . . . . . . . . . . . . 12.3.1 General Technological Scheme . . . . . . . . 12.3.2 Layout and Interconnect Design . . . . . . .

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12.4

Matching Optimization Research on W paste and AlN Ceramics 12.4.1 Technological Improvement Experiment of AlN 2D MCM Substrate . . . . . . . . . . . . . . . . 12.4.2 The Making of Spacer Rod . . . . . . . . . . . . . . . 12.4.3 Package Technology . . . . . . . . . . . . . . . . . . 12.4.4 Vertical Interconnected Technology Research . . . . . 12.5 Result of Experiment . . . . . . . . . . . . . . . . . . . . . . . 12.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Contributors

Jerry Aguirre Kyocera America, Inc., San Diego, CA 92123, USA Kunia Aihara Microwave Microsystems Laboratory, University of California, Davis, CA 95616, USA Thomas Bartnitzek VIA electronic GmbH, Robert-Friese-Straße 3, DE-07629 Hermsdorf Mutaz Bora Peregrine Semiconductors, Inc., San Diego, CA 92121, USA Sean S. Cahill BridgeWave Communications, Inc., Santa Clara, CA 95054, USA Cheng Chen Microwave Microsystems Laboratory, University of California, Davis, CA 95616, USA Morgan J. Chen Microwave Microsystems Laboratory, University of California, Davis, CA 95616, USA Shi Cheng University of Upsala, Sweden Yiin-Kuen Fuh Department of Mechanical Engineering, University of California, Berkeley, CA 94720, USA William Gautier EADS Innovative works, Germany Jiang Guosheng Changsha Saneway Electronic Materials Co., Ltd, Central South University, Changsha, Hunan, China 410012 Zhang Hao East China Research Institute of Microelectronics, Hefei, Anhui, China 230022 Yingqi Jiang Department of Mechanical Engineering, University of California, Berkeley, CA 94720, USA Liu Junyong East China Research Institute of Microelectronics, Hefei, Anhui, China 230022 Ken Kuang Torrey Hills Technologies, LLC, San Diego, CA 92121, USA

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Contributors

Liwei Lin Department of Mechanical Engineering, University of California, Berkeley, CA 94720, USA Mark P. McGrath Microwave Microsystems Laboratory, University of California, Davis, CA 95616, USA Anh-Vu Pham Microwave Microsystems Laboratory, University of California, Davis, CA 95616, USA Guangwen Qu University of Uppsala, Sweden Firas Sammoura Department of Mechanical Engineering, University of California, Berkeley, CA 94720, USA Eric A. Sanjuan BridgeWave Communications, Inc., Santa Clara, CA 95054, USA Juan L. Sepulveda Materials and Electrochemical Research, Tucson, AZ 85706, USA Cui Song East China Research Institute of Microelectronics, Hefei, Anhui, China 230022 Edward B. Stoneham Stoneham Innovations, Los Altos, CA 94024, USA; Endwave Corporation, San Jose, CA 95134, USA Rick Sturdivant Microwave Packaging Technology, Inc., Brea, CA 92821, USA Lee J. Vandermark Brush Ceramic Products, Tucson, AZ 85706, USA Ziliang Wang Nanjing Electronics Devices Institute, Nanjing, Jiangsu, China 210016 Jian Yang Nanjing Electronics Devices Institute, Nanjing, Jiangsu, China 210016 Danny Zhu Jiangsu Dingqi Sci. & Tech. Co. Ltd., Yixing, Jiangsu, China 214200 Afshin Ziaei THALES TRT, France

Chapter 1

Fundamentals of Packaging at Microwave and Millimeter-Wave Frequencies Rick Sturdivant

Abstract The thirst for higher data rates and greater bandwidth has resulted in increased interest in millimeter-wave systems as a means for local and wider area information transport. At the same time there is a real need for lower cost and more compact systems. These requirements have led to the development of a highly integrated millimeter-wave System In Package (SIP), which operates beyond 40 GHz. This solution uses low cost ceramic packaging as well as optimized interconnects and transitions to allow for wide-band electrical performance. This paper will present details on the functionality, electrical performance and packaging used to realize this solution. Packaging at microwave and millimeter-wave frequencies has the same challenges as packaging at lower frequencies except that there are several additional complexities. An example is distributed effects. This is an issue at high frequencies because circuit features and components can have dimensions that are an appreciable fraction of a wavelength. This causes circuit elements to have electrical characteristics that change as frequency increases. For instance, a wire bond is a simple connection point at low frequencies. However, at microwave frequencies a wire bond performs more like an inductor and at millimeter-wave frequencies it can perform more like a resonator or antenna. Distributed effect concerns dominate the design procedure for packaging at high frequencies. The requirement to treat metal traces as transmission lines and interconnecting vias as signal transitions adds another layer of complexity. For instance, features as minute as a bend in a signal trace will degrade performance if not carefully designed. A via carrying a signal from one layer to the next can create a signal transition which can limit electrical bandwidth. Often times, extreme effort is required to accurately model and predict the performance of interconnects and transitions. The use of three dimensional numerical simulation tools such as the finite element or finite difference method is common.

R. Sturdivant (B) Microwave Packaging Technology, Inc., Brea, CA 92821, USA e-mail: [email protected] K. Kuang et al. (eds.), RF and Microwave Microelectronics Packaging, C Springer Science+Business Media, LLC 2010 DOI 10.1007/978-1-4419-0984-8_1, 

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Another layer of complexity is coupling and radiation. Adjacent metal traces, traces next to integrated circuits and traces between layers can couple energy. This can be a useful effect and circuits such as directional couplers and baluns can be created using coupling. However, coupling is often the hidden enemy of the designer of microwave and millimeter-wave packaging. Coupling and radiation effects can be difficult to model and often only reveal themselves during electrical test. Even during electrical testing, it can be a challenge to precisely determine the location and cure for a coupling or radiation problem. Such effects can lead to resonances or amplifier oscillation. Material selection is an important part of the packaging process at high frequencies. One of the reasons is material selection will affect the line impedance and insertion loss of transmission lines. In addition to the material itself, the thickness of dielectric layers and metals layers will affect the design of the transmission line. Also, the materials must be selected to minimize interaction with integrated circuits as in the case of a glob top or under-fill application. Another major concern when packaging at high frequencies is the thermal power density that is often associated with high frequency components. This is especially an issue for RF power amplifiers, which can have power densities of hundreds or thousands of watts per square centimeter. Often these requirements work against each other. For instance, the requirement to design for distributed effects and the need to provide thermal paths for high power devices are usually in conflict. The designer of high power packaging often spends a large amount of effort balancing these, often conflicting, requirements. “Normal” Packaging Issues: • • • •

Choose compatible materials for reliability Die attach method and interconnect method Metal system, CTE matching Sealing and die encapsulation Additional Packaging Issues for Microwave and Millimeter-wave Frequencies:

• Design of the metal pattern and dielectric thickness to maintain required line impedance. • Short interconnect lengths to minimize reflections. • Careful material selection to minimize effect on electromagnetic fields in integrated circuits • Coupling between traces and package resonance • Active devices often have high power dissipation Radio frequency (RF) ranges are typically described by bands of operation. Table 1.1 shows the frequency spectrum and the name or letter designation for each band. Use of these designations is common among professionals developing products and technology for high frequency applications.

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Table 1.1 Frequency bands and their names and letter designations. IEEE Std 521-2002 (original standard adopted in 1984) Band

Frequency range

HF band VHF band UHF band L Band S band C band X band Ku band K band Ka band V Band W band mm band

3–30 MHz 30–300 MHz 300–1000 MHz 1–2 GHz 2–4 GHz 4–8 GHz 8–12 GHz 12–18 GHz 18–27 GHz 27–40 GHz 40–75 GHz 75–110 GHz 110–300 GHz

1.1 Wavelength and Frequency Distributed effects become important when circuit element’s physical features are an appreciable portion of a wavelength. Consider for example a 10 mm package operating at 10 MHz. At that frequency, the free space wavelength is about 30 m which is 3000 times larger than the package. However, at 10 GHz, the free space wavelength is about 30 mm which is only 3 times larger than the package. Therefore, the features of the package can have a significant effect on the electrical performance of the package. Equation 1.1 shows the relationship of wavelength, frequency and material dielectric constant. It is important to note that for materials with larger dielectric constant, the wavelength is smaller which means that distributed effects become more important. This means that higher dielectric constant materials will be more sensitive, in general, to circuit features and will have more coupling. v λ= √ f εr

(1.1)

Where: λ = wavelength, v = free space velocity = 299,792,458 m/sec, εr = dielectric constant of the material (unity for free space).

1.2 Lumped Elements The issue with lumped elements is that above a certain frequency, lumped elements no longer perform electrically like lumped elements. The frequency at which a particular inductor, capacitor or resistor begins to deviate from the ideal or desired

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Fig. 1.1 A comparison of measured data for a lumped inductor, an ideal inductor and electromagnetic simulations of an embedded spiral inductor. Simulations performed using Microwave Office© from Applied Wave Research [1]

frequency response depends upon the type of lumped element, manufacturing technique and manufacturer. As a result, at microwave and millimeter-wave frequencies, lumped elements are often integrated or “embedded” as part of the packaging. The performance benefit of integration is that the lumped elements can be designed to perform to higher frequencies. Also, integration usually leads to smaller size and, often, lower cost. Figure 1.1 compares an ideal lumped element inductor with measured data for an inductor and electromagnetic simulation results for an embedded spiral inductor. Notice how the ideal lumped inductor insertion loss (S21) increases smoothly as a function of frequency. This is exactly what you would expect from a series inductive element. However, the measured data for the lumped inductor shows that the insertion loss begins to deviate from ideal at about 0.5 GHz. Observe from the graph how the behavior of the lumped inductor not only deviates from the ideal inductor slope, it also has a resonance at about 1.8 GHz. This type of response means that the lumped inductor is not very useful above about 0.5 GHz. The figure also shows the electromagnetic simulation results for an embedded spiral inductor. It follows the ideal inductor performance to about 1 GHz or about double the frequency of the lumped element. Though the example is for an inductor, most capacitors and resistors embedded elements perform over a wider frequency range than their lumped equivalent value components. Embedded lumped elements can be realized using most of the available fabrication technologies available including low temperature co-fired ceramic, high temperature co-fired ceramic, thick-film, thin-film and laminates.

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Fig. 1.2 Spiral inductor model used in the electromagnetic simulations

Figure 1.2 shows the model used in the electromagnetic simulations of the embedded inductor. The spiral inductor is formed by the metal pattern on the dielectric substrate. The bandwidth of the spiral inductor is limited by the stray capacitance to ground plane and capacitance between the windings.

1.3 Transmission Lines A transmission line is a metal conductor that transports electrical signals. An ideal transmission line is shown in Fig. 1.3. The transmission line is connected between a generator and a load and transfers energy between them.

Fig. 1.3 Transmission line with line impedance Zo and phase constant γ connected between a source with impedance ZS and load with impedance ZL

A transmission line can be described electrically by its characteristic impedance, Zo , and its propagation constant. The transmission line physical dimensions,

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substrate material, and substrate dimensions determine these parameters. The propagation constant has a loss term and a phase constant term. Equation 1.2 shows the relationship: γ = α + jβ

(1.2)

Where: α = attenuation constant = αc + αd , αc = loss due conductors, αd = loss due to dielectric, β = phase constant. The loss due to conductors is often calculated using the incremental inductance rule [2]. However, most modern transmission line analysis programs will predict conductor loss. The loss is due to the finite conductivity of the metals used in the transmission line. The finite conductivity causes a portion of the RF energy to be converted into heat. Another layer of complexity is that the conductor loss is dependent upon the skin depth. It is a measure of the distance the RF current penetrates into the conductor. At low frequencies, the current can be considered to be uniformly distributed within a conductor. However, at high frequencies, the RF current is confined to the surface of the metal. This increases the current density, which increases the conversion of RF energy into heat, and therefore increases insertion loss. The relationship for skin depth is given in Equation (1.3). δ=√

1 π μσ f

(1.3)

Where: μ = permeability of the metal = μo μr , σ = conductivity of the metal, f = frequency. The dielectric loss depends upon the material characteristics of the dielectric material surrounding or supporting the transmission line metal. The parameter of interest is loss tangent. Loss tangent is the ratio (or angle) in the complex plane of the lossy portion of the electric field and the lossless reactive portion. The relationship is: ∇ × H = jωε E + (ωε  + σ )E 

The designer rarely has access to the fundamental parameters tan δ = ωε + σ in ωε the equation above. However, many manufacturers will supply loss tangent. It can be used to calculate the insertion loss due to dissipation in the dielectric. Equation (1.4) shows the relationship for the dielectric loss. This equation assumes TEM wave propagation. αd =

π tan δ λ

(1.4)

Where: λ = wavelength, tan δ = loss tangent (often given in material datasheets). Table 1.2 shows a few of the more typical transmission lines along with their benefits, drawbacks and typical use. One of the most common transmission lines is microstrip. It is particularly useful in planar circuit applications.

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Fundamentals of Packaging at Microwave and Millimeter-Wave Frequencies Table 1.2 Benefits, drawbacks and uses for typical transmission lines Transmission Line Type

Benefits Drawbacks 1. Good 1. Difficult access to the isolation due to the external signal line ground shield. due to ground 2. Low shield. dispersion. 2. Physically 3. Wide band. large

Typical Uses 1. TV and cable signal. 2. Lab testing. 3. Instrumentation.

1. Physically 1. Low small. isolation. 2. Low cost 2. Higher and ease of dispersion. manufacturing. 3. Higher 3. Large industry order mode propagation base of is MMW compatible circuits and frequencies. components. 4. Easy access to signal line.

1. Printed circuit boards. 2. Micr owave hybrids. 3. Antennas 4. Passive circuits and components. 5. MMICs

Stripline

1. Low cost 1. Difficult and ease of access to manufacturing. signal line. 2. No dispersion. 2. Higher order mode 3. Physically propagation. small. 4. Low radiation and can be low coupling.

1. Buried signals in PWB and ceramic packages. 2. Signal distribution. 3. Couplers and other components. 1. Printed circuit boards. 2. Microwave hybrids. 3. Antennas 4. MMICs

Coplanar Waveguide With Ground

1. Small size 1. Prone to 2. Low cost higher order and ease of propagation manufacturing. modes and 3. Large industry resonances. base of Requires compatible careful via circuits and placement. components. 4. Easy access to signal line.

Coax

Microstrip

5. Lower dispersion

Coplanar Waveguide

1. Physically 1. Requires 1. Antennas. small. connection of 2. Suspended 2. Low cost grounds at substrate and ease of discontinuities. circuits and manufacturing. components. 3. Easy access 3. MMICs. to signal line. 4. Low dispersion.

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Coax should be familiar to most as the transmission line used to connect to a television or cable box. Fig. 1.4 shows an example of coax. It has a center conductor surrounded by a dielectric. A metal ground shield surrounds the dielectric. Plastic usually encloses the assembly though some industrial and lab grade coaxial line does not. The ground shield provides excellent isolation that is important for most systems where coaxial cabling is being used to connect between subsystems or modules. Coax can be very wide band and has very low dispersion. Fig. 1.4 Coaxial transmission line

Microstrip can be fabricated using many different types of technology. Typically it is etched onto printed circuit boards. However, it can also be fabricated by etching thin film or by printing thick film on ceramics. Also, microstrip is often used in Monolithic Microwave Integrated Circuits (MMICs). Stripline is used for passive components such as couplers and power dividers. It is also used as a buried transmission line in multiplayer circuits. Stripline provides excellent shielding with proper via placement and very broad bandwidths. However it is difficult to connect components to the signal line since it is buried in the dielectric. Traditionally, stripline was fabricated by a sandwich of soft circuit boards. Coplanar Waveguide (CPW) can be used with or without a bottom side ground plane. CPW is often used in planar circuits. In these instances, a ground plane is usually required to provide isolation from other circuits in buried layers. When a ground plane is used, the circuit is said to be Conductor Backed Coplanar Waveguide (CBCPW) or Coplanar Waveguide With Ground (CPWG). Both terms are used to describe the same transmission line. If a bottom ground is used, vias must connect the topside ground to the bottom ground. This is to reduce the effect of the zero cut off transverse radiation mode and the patch resonance that can be set up by the top side ground planes.

1.3.1 Dispersion In transmission lines, dispersion occurs when the propagation constant is not linear with frequency. The effect can be devastating for some signals. For instance,

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Fig. 1.5 Simulation results of a microstrip line on 0.25 and 0.75 mm alumina and a coaxial line showing the dispersion effect of the inhomogeneous microstrip transmission line. Electromagnetic simulations conducted using EM Sight Simulator from Applied Wave Research [3]

dispersion can result in increased bit error rates in wide band, high data rate telecommunications systems. Figure 1.5 shows the group delay simulation results from an electromagnetic analysis of a 50  transmission line on 0.25 and 0.75 mm thick alumina (er = 9.9) and coaxial line. Group delay is the change in phase constant as a function of radian frequency (dφ/dω). It can be used to show dispersion. For a non-dispersive transmission line such as coax, the group delay is flat as a function of frequency. This means that for coax, the phase is linear with frequency and the transmission line does not show dispersion. Microstrip line, on the other hand, does show dispersion. For the 0.75 mm thick substrate, the group delay begins to diverge from ideal flat group delay at about 3 GHz. The ripple in the group delay is due to the transmission line being slightly off from 50 . The absolute change in group delay from zero to 30 GHz is about 26 pS for microstrip on 0.75 mm thick alumina, but is only about 9.8 pS for the 0.25 mm thick alumina substrate. Since the propagation constant in a dispersive transmission lines is not linear, the energy propagates at a different group velocity as frequency changes. This means that if a wide band signal is injected onto a dispersive transmission line, some of the energy will arrive at a different time relative to other energy at a different frequency. This results in pulse distortion in wide band systems. However, for most narrow band systems, dispersion can be ignored. Dispersion occurs because a transmission line is not homogeneous. An example of a homogeneous line is coax. The dielectric material that the wave experiences

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is continuous. Another example is stripline, since it has a homogenous dielectric. Microstrip uses two dielectrics (air and the dielectric under the strip) and is therefore not homogeneous. In other words, the air above the microstrip line causes the dispersion. If the dielectric were continuous with no air above, the transmission line, ideally, would not have dispersion.

1.3.2 Dispersion Effects in High Speed Systems Dispersion is important because it affects signal integrity, which is an important consideration in the design of most high-speed systems. This is especially true for telecom and datacom systems, which may be operating at many gigabits per second. Fig. 1.6 shows the effects of dispersion on eye quality of a 10 Gb/s signal by comparing a 12.7 mm (0.500 ) length of coaxial line and microstrip line. It can be seen that the coaxial line has essentially no effect on eye quality. The microstrip line has overshoot and the eye closes early. In addition, the rise and fall times have been reduced. To be fair, most designers would not choose a 0.75 mm thick alumina substrate for a 10 Gb/s application. However, the results demonstrate that dispersion can have a significant effect on eye performance. Consider the case of the 0.25 mm thick alumina substrate. It has significantly less dispersion and as can be seen in Fig. 1.7, the eye performance is commensurately improved. The improvement is due to use of a thinner substrate. A thinner substrate has less dispersion which is the same as saying that its phase is more linear (flatter group delay). It has been shown that transmission line dispersion can have a negative effect on eye quality. A few general design considerations are given for reducing dispersion in microstrip as a guide to the designer: Substrate Thickness Effects: The substrate thickness, h, affects dispersion. A thicker substrate causes more dispersion. From a simple consideration, this seems to follow from the fact that the inhomogeneity of the transmission line is increased with more dielectric. A more rigorous approach is to compare the substrate thickness to the wavelength in the material. As the ratio of substrate thickness to wavelength in the material is reduced, the dispersion is also reduced. Therefore as frequency is increased, the substrate thickness should be decreased to maintain a required level of linear phase (flat group delay response). Substrate Dielectric Constant Effects: The substrate dielectric constant also affects dispersion and eye quality. For a given substrate thickness, a lower dielectric constant has less effect on eye performance. Again, this makes sense from the consideration of the inhomogeneous transmission line. The lower the dielectric constant, the closer it is to air, which is the homogeneous (no dispersion) case. Also, a lower dielectric constant reduces the ratio of substrate thickness to wavelength. Transmission Line Length: The effect of a dispersive transmission line can be reduced if the lengths of dispersive lines are minimized. This may seem to be

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Fig. 1.6 The effect of dispersion on eye quality for a 10 Gb/s signal can be seen by comparing 12.7 mm (0.500 ) length of (a) coaxial transmission line and (b) 0.75 mm thick alumina

obvious. However, the effect of long, dispersive transmission lines is often missed by circuit and board designers. √ hf εr h ≤ 0.05 = λ vo

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Fig. 1.7 The effect of dispersion on eye quality for a 10 Gb/s for a 0.25 mm thick alumina substrate

A fairly conservative design goal is to have the substrate thickness less than 5% of a wavelength in the material. The equation below gives the relationship: h=

0.05vo √ f εr

This equation leads to the relationship for choosing the substrate thickness: Where: λ = wavelength in the dielectric material, νo = velocity (free space), f = frequency, h = substrate height. For example, consider a 10 Gb/s signal. As a general rule, the transmission lines should perform well to a frequency that is at least twice the frequency for a RZ (Return to Zero) signal. For 10 Gb/s, this translates into a transmission line bandwidth of not less than 20 GHz. For high purity alumina (er = 9.9), the substrate thickness using the above equation is 0.25 mm. The equation is fairly conservative and it is possible to achieve successful products with a ratio of h/λ as high as 0.15 or 0.2. However, the challenge will be to reduce line lengths.

1.3.3 Transmission Line Distributed Effects Another level of complexity in the design and development of microwave and millimeter-wave packaging is distributed effects. They are caused by the fact that

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the circuit dimensions are an appreciable portion of a wavelength. Because of distributed effects, the metal traces must be treated as transmission lines. Also, small features or discontinuities in the signal traces can have a significant effect on circuit performance. Consider a microstrip transmission line with a simple bend. A bend is a very common circuit feature. Fig. 1.8 shows the bend realized three different ways. The first is square which may be first choice for making a bend in a metal trace. The second is mitered which has half of the metal removed from the signal line. Lastly, there is the optimum miter which has additional metal removed from the bend. Other realizations are possible such as a smooth curve, but are not being considered in this analysis.

Fig. 1.8 Three methods to realize a bend in a microstrip line

The circuits were analyzed using electromagnetic simulation from 0 to 30 GHz. The model for the optimum mitered bend is shown in Fig. 1.9 for the case of 0.25 mm thick alumina (εr = 9.9). The results are shown in Fig. 1.10. The curve shows insertion loss which is a measure of the amount of energy that is lost due to reflections of energy, absorption or radiation. The results show that the square bend has more insertion loss than the mitered bends. The optimum mitered bend has the best performance. Many other discontinuities can exist in a package at microwave and millimeterwave frequencies. Because of distributed effects significant care must be taken when designing so that the impact on electrical performance can be miminized.

1.3.4 Transmission Line Coupling and Cross Talk At microwave and millimeter-wave frequencies coupling can occur between metal traces, devices and integrated circuits. The coupling can be significant and extreme steps are often taken to mitigate its effects. Fig. 1.11 shows a pair of coupled microstrip lines. Energy in one line will coupled to the other line across the gap (S) between the lines. In general the coupling between the lines is:

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Fig. 1.9 Model used in the electromagnetic analysis of the bend. Electromagnetic simulations conducted using EM Sight Simulator from Applied Wave Research [3]

Fig. 1.10 Insertion loss for the square bend, mitered bend and optimum mitered bend

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Fig. 1.11 Coupled microstrip lines

(1) Proportional to frequency at low frequency (below the point where the length of the lines is a quarter wave long). (2) A function of frequency at high frequencies and exhibits a resonant behavior. (3) Proportional to the dielectric constant. (4) Decreased as the substrate thickness is decreased.

1.4 Package Fabrication Methods Packages and substrates can be fabricated using several commercially available technologies. The fabrication methods can be broken into described and organized many different ways. We have divided the methods into three groups using the base material: (1) Co-Fired Ceramics (2) Thick and Thin Film Ceramics (3) Organic Materials The focus of this section will be upon the electrical characteristics as well as the general benefits and drawbacks of each technology.

1.4.1 Co-fired Ceramics Co-fired ceramics are fabricated with “green” tape layers, which are fired at high temperatures. The result is a homogeneous ceramic with three-dimensional metal features formed by metal traces and filled vias that were part of each layer prior to firing. Fig. 1.12 shows a typical co-fired ceramic process flow. At the start of the process, raw materials are received such as alumina, quartz, glass and binders. The materials are prepared into a slurry, then cast into “green” tape. After the tape has dried, it is punched with vias and the vias are filled with metal. Metallization layers are then added using a printing method. Next, the packages may be singulated or may remain in an array where they are stacked and sintered (or fired) at high

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Fig. 1.12 Typical process flow for co-fired ceramics. (Courtesy of Adtech Ceramics)

temperatures. Finally, the parts are plated and brazed if required. There are many variations on this basic process depending upon the material and the package design. However, the basic processing concept is similar for co-fired ceramics. Some typical co-fired ceramics are High Temperature Co-fired Ceramic (HTCC) alumina and aluminum nitride. HTCC alumina has been used extensively for integrated circuit and multichip module packaging for a variety of applications including microprocessors, military radar modules and high speed telecom modules. The benefits are hermeticity, good metal adhesion, good thermal conductivity (20–25 W/mK), excellent compatibility with brazed metal, high strength, relatively low cost and good electrical performance at microwave frequencies. The main draw back to HTCC ceramic at microwave and millimeter-wave frequencies is that refractory metals such as Molybdenum (Mo) or Tungsten (W) must be used for the internal metal features. The resistive losses in Mo and W are higher than gold metallization by a factor of about 2.5.

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A major benefit of HTCC aluminum nitride is its thermal conductivity, which can be as high as 120–180 W/mK in cofired packages. The thermal conductivity is about 5–7 times higher than HTCC alumina, which can be a significant benefit for some applications such as high power transmit receive modules for military radar. The firing temperature of HTCC ceramics is typically 1200–1800◦ C. Alumina HTCC fires at the lower range and aluminum nitride fires at the higher range. Though aluminum nitride can react with moisture, measurements have shown that such a reaction does not appreciably affect the propagation of microwave signals [3]. Figure 1.13 shows a package realized in HTCC alumina along with its measured electrical performance. The performance shows that it is possible to achieve low insertion loss performance to about 25 GHz. The photo shows the measured insertion loss and return loss.

a

b

Fig. 1.13 HTCC alumina QFN style package with measured electrical performance (Courtesy of Microwave Packaging Technology, Inc., Brea, CA)

Another co-fired ceramic is Low Temperature Co-fired Ceramic (LTCC). The benefits of LTCC are that it has good electrical properties at microwave and millimeter-wave frequencies, uses noble metals such as gold and silver for conductors, can have integrated resistors, can use high dielectric constant layers to realize capacitors and can be made to be hermetic. The drawbacks are that the thermal conductivity of the ceramic is low, at about 2 W/mK, and the material strength and metal adhesion are much less than alumina HTCC. The thermal conductivity can be improved by using arrays of thermal vias. However, the improvement usually results in an effective thermal conductivity of only 10–15 W/mK. Some methods have been used to improve on this such as heat up thermal paths. One of the benefits of HTCC and LTCC is the ability to realize buried components and circuits. For instance, it is possible to realize buried transmission lines such as stripline, power dividers, filters and couplers. This advantage is used extensively to realize compact highly integrated packages and modules.

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Table 1.3 Material characteristics of some common dielectrics used at microwave frequencies Material

Dielectric constant

Loss tangent

Alumina (HTCC, 92%) LTCC (Ferro A6) LTCC (Dupont 951) Aluminum Nitride (HTCC)

9.2 5.9 7.9 5.8

0.003 0.0012 0.0045 0.005

Some typical HTCC and LTCC ceramic materials and electrical properties are shown in Table 1.3. There are many different suppliers and varieties of LTCC. Two of the more common types are shown. The fact that LTCC is available in a variety of dielectric constants is interesting and sometimes useful for design flexibility.

1.4.2 Thick Film and Thin Film Ceramics Thick film and thin film ceramics differ from HTCC and LTCC in that the fabrication starts with a base substrate ceramic that is already fired. Although multiple layers can be fabricated using thick film or thin film, the resulting package or substrate is a mix of materials. Also, the multiple layers are typically used to realize signal cross-overs. Each thick film supplier has it own process for fabrication. However, a generic description of the thick film process is helpful. Thick film is fabricated by starting with a ceramic base material. The base ceramic is already fired and can be alumina, aluminum nitride or beryllia (BeO). The substrate is laser machined to produce via holes, ceramic outline features and scribe lines. Next, screenprinting is used to add metal features. The metal uses a chemistry that allows for good adhesion to ceramics. The substrate is then fired. Next, other layers such as resistors, dielectrics or additional metal layers are printed and fired. Each additional layer requires its own firing. Finally, the substrates receive a resistor trim and singulation. The resulting metal layers are typically on the order of 7–15 μm thick. Minimum line width and gap is typically 75–120 μm depending upon the manufacturer and metal thickness. The line tolerances are typically ±25 μm, though ±10–15 μm can be achieved. Variations on thick film exist, such as etched thick film, plated copper thick film, ultra fine line thick film. Etched thick film is a process that uses a thin layer of printed conductor processed using thin film methods. The resulting lines can have a width and gap of 25–50 μm. Also the line tolerances can be ±5–10 μm. Figure 1.14 shows a surface mountable package that uses thick film processing. The package has a brazed kovar ring with allows attachment of a lid for a hermetic package. The package can be solder attached to a motherboard.

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Fig. 1.14 Hermetic surface mount package fabricated using thick film methods (photo courtesy of Remtec Inc., Norwood, MA)

Thin film is fabricated by depositing conductor material and etching with a photolithography method. The resulting metal traces can have excellent microwave and millimeter wave performance. Line widths and gaps can be a small as 10 μm with tolerances of 2.5 μm. Dielectric layers can be created using Silicon Nitride or polyimide to realize capacitor and metal crossovers.

1.4.3 Organic Substrates Organic substrates include a host of materials. Our focus will be upon high frequency laminates. One of the benefits of these materials is that they are available in a variety of dielectric constants from 2.2–10 or higher. They are fabricated using printed wiring board (PWB) methods. Extensive research has been invested in developing high performance laminates with excellent microwave and millimeter-wave performance. The laminate substrates can be used to create multi-layer structures. For instance, they can be used for surface transmission lines or buried components. Fig. 1.15 shows an image of a microstrip line with a transition to a buried stripline and the resulting measured performance. The benefits of laminates include the ability to use low cost PWB fabrication methods, ability to realize buried transmission lines, use of high conductivity copper metallization, low cost and compatibility with other laminates to realize mixed material solutions.

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Fig. 1.15 Measured return loss of a microstrip to buried stripline transition realized in RO4003 substrate material (Courtesy of Microwave Packaging Technology, Inc., Brea, CA)

1.5 Interconnects Interconnects are an important consideration for packaging at microwave and millimeter-wave frequencies. For instance, wire bonds are used to connect from integrated circuits to packages and substrates. At low frequencies they perform as an ideal connection. However, as frequency increases, wire bonds begin to perform like series inductors and can behave as antennas at certain frequencies. To analyze the electrical performance of wire bonds, a model was created using High Frequency Structure Simulator (HFSS) from Ansoft Corporation. An image of the model and return loss for 1–3 wires is shown in Fig. 1.16. HFSS is a finite element simulator that will solve the electromagnetic fields and generate scattering parameters. The results predict electrical performance. An interesting result of the wire bond analysis is that the benefit of more than 2 wires is minimal. This is due to the fact that the additional wire bonds add mutual inductance. Therefore, there is benefit for a double wire bond, but a third or more wire bonds have nearly no benefit. The bandwidth of wire bonds can be extended by providing additional capacitance at the wire bond pad to “match out” the inductor. This technique is very useful to millimeter-wave frequencies, but usually results in a narrow band match. A wire bond can be modeled as a series inductor. A model that is valid to 40 GHz is shown in Fig. 1.17. The model is basically a series inductor with shunt capacitors.

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Fig. 1.16 Model of a wire bond between substrates using HFSS (Ansoft Corporation [4])

The capacitors arise from bond pad capacitance and any capacitance of the wire bond to ground.

Fig. 1.17 Wire bond equivalent circuit

Flip chips offer an alternative to wire bonds for IC interconnects. They can provide very low inductance interconnects to 100 GHz. The connection between the integrated circuit and the motherboard is made using a bump. The bump can be solder or metallic using gold pads. One method of interconnection is to use metal bumps plated up on the IC with solder used to connect to the motherboard. The bandwidth of flip chip interconnects is dictated by the size of the bump. The smaller bumps have wider bandwidth and lower inductance. One issue is that the IC must be designed to perform with a flip chip interconnect. One method is to use coplanar waveguide as the integrated circuit transmission line. A simplified flip chip connection is shown in Fig. 1.18. For applications to 100 GHz, the bump diameter must be very small on the order of 30 μm.

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Fig. 1.18 Flip chip interconnect

There are many other methods to achieve integrated circuit connection. One is to use embedded integrated circuits. Fig. 1.19 shows an example of this method. It has been used for transmit/receive modules for phased arrays and in some millimeterwave applications.

Fig. 1.19 Embedded integrate circuit method for realizing interconnects

1.6 Conclusions One of the most important issues in packaging at microwave and millimeter-wave frequencies is distributed effects. It impacts nearly every consideration in the design process. A good summary of the process and required steps for packaging at microwave and millimeter-wave has been developed. Mechanical Design: Critical issues are Coefficient of Thermal Expansion (CTE) interactions, structural and weight requirements, processing temps, ramp up, system attachment, mounting, materials and their behaviors, expected lifetime and cost. Simulation can be performed using 3D finite element and finite difference simulators. Packaging Electrical Design: The goal is to manage specific impedances, isolation requirements, interactions, propagation and interferences while meeting requirements. One should use 2D and 3D Electromagnetic (EM) solvers extensively.

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Simulation may be done through circuit simulation, 2.5D method of moments and 3D finite element or finite difference. Worst case modeling and Monte Carlo analysis for specification compliance modeling and interfacing with manufacturing is recommended. Design Verification, Materials and Reliability Tests: It is important to know material properties prior to modeling either through one or more databases or through material testing. It is also important to have validation of simulation data so that model can be relied on for future. Reliability testing follows for specific systems. Fully Automated Production: Currently, in most advanced facilities, CAD, CAM and CIM are all integrated in a smooth transition to manufacturing and provide transparent, accessible mgt/eng/mfg databases open to decision making [5].

References 1. EM Sight Simulator from Applied Wave Research, www.appwave.com. 2. R.L. Sturdivant, “Transmission line conductor loss and the incremental inductance rule,” Microwave Journal, September 1995. 3. R. Sturdivant and T. Theisen, “Heat dissipating transmission lines,” Applied Microwave and Wireless, vol. 7, pp. 57–63, Spring 1995. 4. Ansoft Corporation. www.ansoft.com. 5. J.S. Pavio, IEEE MTT-S Workshop, 2006.

Chapter 2

Low-Cost High-Bandwidth Millimeter Wave Leadframe Packages Eric A. Sanjuan and Sean S. Cahill

Abstract As integrated circuit speeds and bandwidth needs increase, low-cost packaging and interconnect technology continue to be challenges. Solutions to these problems are driven by consumers’ desire for increasing bandwidth (e.g., portable communications applications) and manufacturers’ desire to drive down system cost (e.g., taking advantage of volume manufacturing processes). This work describes a low-cost plastic QFN package possible of meeting these needs. This package has low-loss, high-bandwidth and is based around microCoax interconnect technology. Since this package structure is broadband, it allows for a variety of chipsets to be assembled using the same process sequence and I/O configuration, thereby eliminating costly overhead. With less than 0.5 dB insertion-loss and >15 dB return-loss per RF interconnect at 50 GHz, a 5×5 mm microCoax QFN package allows existing bare-die only applications to enter the world of high-speed PCB assembly, significantly driving down the cost of high-frequency RF subsystems. Process technology, I/O performance, active device performance, PCB board material selection and test protocol will all be discussed.

2.1 Introduction Electronic devices and components are operating at ever increasing speeds and over increasing frequency ranges. For this reason, electronic device packages can become a source of performance degradation, often leading high-frequency system designers to dispense with a package altogether. Such “bare die” approaches frequently give inconsistent performance as the devices are subjected to environmental stresses to a greater degree than packaged devices. Commonly available high-frequency packages, often constructed from metal and ceramic laminates, address some of the

E.A. Sanjuan (B) BridgeWave Communications, Inc., Santa Clara, CA 95054, USA

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concerns imparted by standard package approaches in that they bring controlledimpedance planar waveguide structures such as microstrip and coplanar waveguide (CPW) interconnects very close to the device. Device and waveguide are then connected by a short wire bond, ribbon bond, or flip-chip bump. While this provides a performance improvement, bonds and bumps still do not comprise waveguide structures, and therefore create signal mismatch at each occurrence. Solitary bonds and bumps are inductors at high frequencies, and so a matching network structure is typically constructed on the device, package, or printed circuit board (PCB) in order to cancel the effect of the inductance. This solution then results in frequency range or bandwidth limitations for the device-package-PCB system. A further drawback of this approach is that the typical high-frequency package is much more expensive than its common low-frequency counterpart, in large part because of the RF tune/test/rework yield impacts associated with conventional assembly technologies at these higher frequencies. An alternative approach is needed.

2.2 MicroCoax Approach MicroCoax, an approach based on wire bonding, is similar in structure to common 50  coax cable. MicroCoax allows signals to flow over large frequency ranges from 0 to 115+ GHz, with significant impedance matching and very little cross-talk. The main differences between microCoax and common coax cable relates to coax sizes, connection, and fabrication techniques. The following formula may be used to estimate the impedance, Z0 , of a coaxial transmission line:   138 b (2.1) Z0 : = √ · log εr a Where a is the diameter of the bond wire, b is the outside diameter of the dielectric, and εr is relative permittivity of the coaxial dielectric. A typical microCoax is about 70 μ in diameter, or about the width of a single human hair. To turn a wirebond into a microCoax, the process is relatively simple. First, chips to be packaged are die-attached. Then, the chip is wirebonded using a conventional wire bonder. Next, the chip and wire bonds are coated with a plastic layer forming the coaxial dielectric that is very uniform and of precise thickness. Metal coating on the outside of a coax is tied to ground through small holes, which are made using standard laser trimming equipment, in precise locations on the package. The metal may be selectively patterned (so that ground metal is not on the chip surface) through an additional process step. This ground on the outside of the microCoax creates an impedance-controlled structure, shields from noise, and prevents signal leakage (Figure 2.1). Unlike bare wires or flip-chip bumps, coax cables are matched in impedance to the devices that they connect and thus do not exhibit limited bandwidth behavior of lumped structures. This advantageous behavior is depicted in Figure 2.2, which shows measured insertion and return loss performances of microCoax through-line

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Fig. 2.1 Standard coax structure compared to wirebond-based microCoax

Fig. 2.2 Performance of 2.2 mm long microCoax

structures connected to CPW I/Os for probing purposes. Note that the insertion loss is less than 0.7 dB at any point from 0 to 115 GHz. The return loss is never worse than 15 dB, and typically better than 20 dB across this same band. Example test structures are shown in Figure 2.3.

Fig. 2.3 MicroCoax test structures (L to R): Dielectric-coated wirebonds; 2 Views of CPW probing structures after outer metal shield is in place. Note the circular vias to establish ground

Key to the performance of microCoax is how well the formation process can produce interconnects of the desired impedance. High-frequency devices have mostly standardized on input and output impedances of 50 , so the process to-date has focused on this target value. Equation 2.1 shows that for a given dielectric constant, once the center conductor diameter is fixed, the characteristic impedance is purely a function of the dielectric diameter. Wire bond diameter batch-to-batch variation is about ±3%, and is primarily due to variation from die-to-die in the wire-drawing tooling. Process variation accounts for less than 1% tolerance of the final diameter.

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With these assumptions in mind and utilizing the materials set under discussion, variation in wire diameter produces about 2.2% variation in final impedance value. Presuming that target thickness of deposited dielectric is controlled to the same level, one can assume deviation from target impedance of about ±3%. In terms of return loss, the impact is less than –30 dB, and therefore negligible. Other sources of variation, such as deposition uniformity, must also be considered. The process for creating the dielectric coating utilizes vacuum-condensation, and is thus extremely uniform. Variations can occur if diffusion of reactant species is somehow limited, thus it is useful to consider how such variations might impact performance. One can model this problem as a simple conductor positional offset within the coax structure. An example of this approach is shown in Figure 2.4.

Fig. 2.4 Offset conductor impedance model and cross-section of offset conductor

Table 2.1 shows that offset has a very weak impact on impedance, as the core has to be offset by 40% of the dielectric thickness before the impedance changes by 10%. A 10% offset leads to impedance changes of about 0.3 . Thus, process induced offset is not a major concern.

Table 2.1 Impedance as a function of offset % Offset

Impedance

0 10 20 30 40 50

50.05 49.75 48.86 47.30 45.00 41.75

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2.2.1 Packaging Approaches Once the power of microCoax as an interconnect technology was realized, packaging approaches were developed around it. This led to the possibility of making extreme-performance packaging for high-end applications on a chip scale. The highest performing package I/O structure for marriage with a microCoax interconnect would seem to be something of the same form factor, namely a coaxial feedthrough. Such a package is shown in Figure 2.5.

Fig. 2.5 Coaxial Feedthough package with microCoax interconnects with test die (left) and with port-to-port through lines of various lengths (right)

The process sequence for creating such a package, as earlier described, is shown in Figure 2.6 and comprises the steps of: (1) forming dielectric “donuts”, (2) build-up of metallic package with feedthrough. This approach allows for creation of hermetic packages when combined with a glass or ceramic “donut” for the dielectric, as metal + glass/ceramic constructions have excellent gas impermeability.

Fig. 2.6 Process sequence for coax feedthrough package and dielectric “donut” example

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Package assembly steps (Figure 2.7) include: (1) die attach and wire bond, (2) coat with conformal dielectric, (3) laser via formation, (4) selective metallization. Lidding would comprise the final step of the assembly. A formed-metal cavity lid, with a soldered or brazed seal, creates a fully hermetic assembly. If hermeticity is not a requirement, other lid materials can be used, and even overmolding may be applied. Existing semiconductor backend equipment can be used to execute every step of the assembly.

Fig. 2.7 MicroCoax creation on coax feedthough package

Figures 2.8 and 2.9 show an 18–31 GHz LNA interconnected with microCoax. Note that ground metal appears only in the areas near the I/O regions. The performance of this device is shown in Figure 2.10. The solid S21 line in the figure shows the essentially lossless performance vs. compensated probe data (dots) from the manufacturer. Performance over the band of interest is excellent. Slightly early roll-off is due to the lack of 0.2 nH inductance from a bare wirebond expected at each port. Excellent return loss characteristics demonstrate the minimal impact of the package implementation on the overall performance. This further implies that the inductance-compensating structures of the MMICs may be eliminated through

Fig. 2.8 MicroCoax-interconnected MMIC (left to right): UMS CHA2069 with patterned ground; I/O area prior to via formation (note center conductor); I/O after via/patterned ground formation

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Fig. 2.9 X-ray micrograph of packaged UMS CHA2069. Coaxial structure of interconnects is visible, as are ground vias within the MMIC chip

Fig. 2.10 MicroCoax interconnected MMIC performance

the use of microCoax, further improving bandwidth. This, in turn, would allow reduction of chip size, saving costly real estate, and lowering chip cost. The coaxial feed-through structure of the package described so far has some unique assembly requirements. To use the coaxial feed-through in combination with PCB routing structures requires the ability to create a transition from the coaxial structure of the package to the planar waveguide structure, either coplanar or microstrip, that will propagate signals around the board. The assembly technology is not too different than that commonly used for ball-grid array (BGA) or other higher I/O count surface-mount packages. Figure 2.11 is an x-ray micrograph of a

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Fig. 2.11 Package attach to PCB. Small circular vias scattered about the attach area are thermal vias in the PCB

typical microCoax package board attach. What is meaningful to note in this micrograph is that there are no voids in the die attach area underneath the package, and that all center conductors are contiguous (dark grey areas) with board leads.

2.2.2 Limitations to the Approach The coaxial package, combined with microCoax interconnects, provides many desirable characteristics. These significant advantages, however, can also be an Achilles heel when cost-sensitivity begins to dominate package considerations. The use of coaxial feed-throughs, in this glass/metal surface-mount package, is unique in the assembly industry. The hermetic performance of this geometry is ideal for demanding military and space-born applications. Such an attribute is neither necessary nor cost-effective for most consumer applications. We must therefore ask ourselves, is another less-costly, high-volume friendly approach possible?

2.3 MicroCoax/Leadframe Approach With the foregoing discussion in mind, the ideal package would have the following attributes: • Low-cost of package and assembly – Standard package outline – Surface mount – suitable for pick and place • Controlled impedance from PCB to die interface

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Integral shielding to minimize cross-talk Good thermal dissipation Multi-chip and passives possible Internal routing possible

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A standard JEDEC 95 Quad Flat No-lead (QFN) package of the open-cavity variety (depicted in Figure 2.12) has several desirable attributes (ie. 1, 4, and 5), while having some performance limitations. With careful design, QFN packages are used up to 10–20 GHz frequencies. The main limitation of QFNs has been the bare wirebond interconnections, as they are not waveguides.

Fig. 2.12 Standard open cavity QFN packages

2.3.1 Package I/O Structure Considerations In order to achieve good signal propagation characteristics from the PCB, into the package, through the interconnect, and to the chip, the entire signal path must be considered as a waveguide. Different waveguide geometries are possible. Substrate waveguides are typically one of three common varieties: microstrip, stripline, and coplanar waveguide (CPW). The devices are waveguides because they have both signal and ground leads held in a specific geometric arrangement that allows for controlled impedance. The CPW configuration in particular is implemented through the arrangement of three leads in a ground-signal-ground (GSG) arrangement on single plane. The width of the signal lead, and the gaps between the signal and ground leads, and the dielectric constant of the substrate material are key determinants of the impedance of the CPW configuration. The stripline has a similar GSG configuration, but the arrangement is layered in stacked planes rather than on a single plane, rendering it more complex for attachment to a PCB. Leadframe-style packages lend themselves to consideration as quasi-CPW or quasi-stripline waveguides. Three adjacent leads on the leadframe may be configured in a GSG arrangement, thus a waveguide-like structure is achieved. A

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standard QFN package may range in lateral dimension from 3.0 to 12.0 mm in increments of 0.5 mm. Typical terminals range in width from 0.15 to 0.5 mm, range in pitch from 0.4 to 1.27 mm, and have a thickness from seating plane to upper terminal surface of 0.2 mm and overall height of 0.3–1.0 mm. Given this range of dimensions, a wide range of impedances may be realized, crudely estimated as variable from 30 to 120 ’s with a typical plastic material of dielectric constant value ranging from 3.5 to 4.0. As previously discussed, impedance of 50  is typical for the I/O’s of devices operating in the 10’s of GHz such as millimeter-wave integrated circuits (MMICs). The typical desired impedance for device packages, utilizing a GSG structure, is thus achievable within the allowed dimensional ranges of industry standard QFN packages. Matching the impedances between two structures is not a sufficient condition for efficient energy transfer in waveguides, however. In a CPW, energy is distributed primarily in the two gaps between the signal lead, and the ground electrodes adjacent to it. This shaping of the electromagnetic energy is known as the mode shape. Similarly, in a coaxial waveguide in its lowest order mode, the energy fills the entire space between the center conductor and the outer ground shield. The fundamental modes in the respective waveguides are very different in shape, thus coupling from one waveguide structure to another can cause reflections that are detrimental to performance. For this reason, it is important to blend the energy distribution shapes as smoothly as possible from one waveguide type to another. This blend region is known as a transition. The previously discussed JEDEC Design Guides do not limit dimensions and spacings internal to the package, but only define the external elements. Complex three-dimensional (3-D) shapes created with dissimilar front and back photolithographic patterns allow for sculpting of signal lead and ground lead shapes such as may be useful for creating mode transforming structures that transform from CPW, with its planar GSG configuration, to a coaxial bond wire, with its concentric signal-insulator-ground structure. Thus, two-sided forming can create 3-D mode transforming shapes in the metallic leadframe.

2.3.2 Modelling the Signal Path The transforming structures are typically not simple geometric blends of one shape into another. This is because both spacings and shapes control reactive impedance. Analytical and numerical analysis tools are brought to bear to optimize the overall performance of the transition region. Both frequency-domain and time-domain approaches are useful for this purpose. Frequency domain analysis allows one to assess performance at any given frequency over the entire frequency band of interest. Time domain analysis allows one to identify trouble spots in the transmission path, which can cause energy reflections. Localizing the sources of mismatch permits optimization of the geometries of leads and adjacent spaces for improved performance.

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Fig. 2.13 (a) Package I/O structure – solid model. (b) Package I/O structure – EM simulation

Numerical approaches (e.g., CST Microwave Studio) can be used to simulate the expected performance of different design variants, as can be seen in Figure 2.13. The high frequency input ports of the package have several parameters that can be varied in order to optimize performance. Because of the lithographic process used to define the shapes in the leadframe, parameters of concern are easily divided into an external and an internal layer. Each of the parameters has some influence on performance, but some are much more significant in their effect than others. Figures 2.14 and 2.15 show the results of frequency domain models. The effect of varying the “side gap” (Figure 2.14) is quite significant. Figure 2.15 shows the effect of varying the “front gap”, which is relatively small. Parameters also have interactive effects, which can be quite challenging to adequately characterize. For this reason, it is helpful to create parameterized electromagnetic models, which can automatically vary parameters, and optimize for the best performance. Such optimization criteria include minimizing S21 (insertion loss) and S11 (return loss), while maximizing

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Fig. 2.14 Parametric model – return loss: Large impact of varying the side gap

Fig. 2.15 Parametric model – return loss: Small impact of varying the front gap

bandwidth for frequency domain models and minimizing the effects of dimensional variation and tolerance on performance. Time domain models such as time domain reflectometry (TDR) are similarly useful for optimization. The models are useful for probing discontinuities in the signal propagation path. The greater the reflected signal, the worse is the impedance mismatch at a given propagation distance into the path. Thus, the actual location of impedance mismatch can be established. With this tool, one would optimize for best impedance match and least reflected energy. Figures 2.16 and 2.17 show the impact with variation of different parameters on the instantaneous impedance as a wave travels from the simulated PCB, through the package leads, and into the coaxial bond wire to the chip and out through a reciprocal path (note the relative symmetry of the waveforms). The effect of the chip is ignored for the purpose of these models. An ideal characteristic for this simulation is a constant 50  impedance for the entire signal propagation time.

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Fig. 2.16 Parametric model – time domain: Impedance estimate as a function of a signal line width parameter

Fig. 2.17 Parametric model – time domain: Impedance estimate as a function of a signal line shape parameter

Thus, modeling allows one to optimize the design of quasi-CPW inputs of the package for performance criteria such as impedance and signal integrity. The present-day leadframe and transfer molding fabrication methods, as well as assembly technologies, place some limits on the achievable geometries in such a package. It is anticipated that fabrication technology improvements will permit consequent improvements in achievable designs and package performance with time.

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Figure 2.18 shows the simulated performance of a package input port, leading to a 50  termination internal to the package in order to simulate attachment to a MMIC. At 80 GHz, insertion loss is predicted to be about 0.6 dB, and return loss to be 18 dB. This is quite acceptable, as most MMICs of interest have broadband return loss characteristics of 10–15 dB.

Fig. 2.18 Optimized package model – 0 to 80 GHz

2.3.3 Performance In order to evaluate performance characteristics for actual microCoax enhanced packages, port-to-port thrus were constructed. The package has the general outline of the standard QFN (Figure 2.12), but contains geometric enhancements internal to the package that vastly improve the high frequency performance when used in combination with microCoax. The resulting device is depicted in Figure 2.19.

Fig. 2.19 MicroCoax enhanced QFN package (left to right): A bare package with enhanced ports; the same package with coaxial through-line; close-up of port/through-line structure

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This testing configuration is really an “acid-test” of performance, because the longest interconnect is constructed (>4 mm long), maximizing insertion loss, and the back-to-back connections essentially double the return loss. Testing of the through-line structures can be performed with a vector network analyzer (e.g., Agilent 8510C VNA) and appropriate fixturing (e.g., Anritsu 3680 V-band Universal Test Fixture). Figure 2.20 shows data collected from a

Fig. 2.20 Fixture based test of back-to-back through-line. Lower return loss line shows predicted performance of single I/O connecting to a perfect 50  termination internal to the package

Fig. 2.21 Un-mounted package vs. PCB-mounted package performance. Both parts were placed in test fixture so that performance could be directly compared

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package as shown in Figure 2.19. In this particular case, SOLT-based coaxial calibration was used, so the losses of the test fixture are embedded in the data. There are methods to de-embed the test fixture effects from the data, such as TRL and its variants, but these approaches generally have bandwidth limitations. Since we are looking to assess performance over the entire band from near-DC to 50 GHz, coaxial calibration up to the test fixture gives us a reasonable measure of system performance over the entire band. In the instance where a specific band of interest is desired, a TRL method may be preferred. Most important in the test device evaluation is the entire utilized path. In other words, a package must ultimately be attached to a PCB, and the performance on the PCB, ideally, would be no worse than the bare package itself. Figure 2.21 shows that this goal has been achieved. The on-board performance (bold lines) is generally better at all frequencies than the un-mounted performance (thin lines) for both the insertion loss and return loss characteristics. This is because the interconnectpackage-PCB system was modeled and designed to optimize mounted performance. The PCB test board is fabricated from Rogers 5880 and was approximately 1 cm in length. The connectors of the Anritsu 3680 are representative of typical v-band edge connector performance. The impact of the package on performance of MMICs is the ultimate test of utility. One of the important features of this package is its substantial bandwidth. The CHA2069 (available from United Monolithic Semiconductor) is an 18–31 GHz Low Noise Amplifier (LNA) with nice performance characteristics. A device with this significant bandwidth will challenge most packaging approaches, as they are usually optimized to operate over a limited band. Figure 2.22 compares the “bare die”

Fig. 2.22 Comparison of bare die and microCoax-enabled QFN (mQFN) package performance. Note low impact on insertion loss and slightly early roll-off due to lack of parasitic inductance

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and microCoax-enhanced QFN (mQFN) approaches for this MMIC LNA. The reference plane for evaluating the bare die is at the probe pads on the die surface, and neglects any interconnect losses. The LNA with mQFN packaging is mounted on a PCB and placed in the previously described Anritsu 3680 test fixture. The reference plane for evaluating the LNA is external to the test fixture for reasons previously discussed. This creates an effective path difference of approximately 18mm between bare die and PCB implementation reference planes. There are several things to note in the performance comparison. First, the mQFN package has little impact on insertion loss through the gain region, exhibiting performance approaching the bare die itself. This is especially noteworthy given the presence of connector, PCB, and transition losses. Second, the leading edge of the respective S21 graphs overlay one another perfectly. The trailing edge shows slightly early roll-off of the mQFN part. This is due to the fact that most MMICs are designed to compensate for 0.2–0.4 nH of series inductance arising from the wirebond interconnects through the use of additional capacitance at the I/Os. Because the mQFN interconnects are true coaxial waveguides, there is no lumped inductance to compensate. This leads one to propose that mQFN style packaging might allow for elimination of the capacitive compensation structures, and permit some shrinkage of the die. This, in turn, would have cost benefits accruing from higher die count per wafer.

Fig. 2.23 Comparison of QDG vs. mQFN package performance. Note the improved gain flatness and superior return loss characteristic

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As previously discussed, existing package offerings for MMICs do not typically have the wide band performance of mQFN. A packaged CHA2069 is commercially available in a 4mm QFN. This offering carries the designation QDG. Figure 2.23 compares published data for the QDG package vs. the mQFN. There are several important performance aspects that should be noted. First, note that the gain flatness over the 13–32 GHz band is significantly better for the mQFN that for the QDG, ±3 dB vs. ±0.6 dB, or 5× better flatness. Secondly, the input return loss (S11) is better for the mQFN at nearly all frequencies, with as much as 12 dB improvement at some instances. Again, the QDG package data assumes a reference plane immediately external to package and excludes connectors or board transmission lines (approx. 6.2 mm path), while the mQFN data includes all connector, PCB, and transition (approx. 20 mm path) losses.

2.4 Conclusion High performance microCoax interconnects have been successfully applied to multiple package configurations, including high-volume compatible QFN outlines. Since these package structures are broadband, they allow for assembly of a variety of chipsets using identical process sequences and I/O configurations, vastly reducing overhead associated with multiple unique solutions. Costly measures such as custom substrates, wire bond trajectory adjustments, and trimming procedures can be eliminated. With less than 0.5 dB insertion-loss and >15 dB return-loss per RF interconnect form DC – 50 GHz, a 5×5 mm microCoax QFN package allows existing bare-die only applications to enter the world of high-speed PCB assembly, significantly driving down the cost of high-frequency RF subsystems. This material is based, in part, upon work supported by the National Science Foundation under Grant No. 0620136.

Chapter 3

Polymeric Microelectromechanical Millimeter Wave Systems Yiin-Kuen Fuh, Firas Sammoura, Yingqi Jiang and Liwei Lin

Abstract Polymeric millimeter-wave components and systems based on micro molding technologies have been demonstrated, including waveguides, iris filters, tunable filters, phase shifters, waveguide-fed horn antennas and waveguide-based feeding networks. Fundamental issues in polymer metallization process such as conformal and uniform deposition as well as mass transfer and current density effects on the novel in-channel electroplating encapsulation, surface morphology and roughness on mm-wave attenuation will be discussed in detail. We believe this new class of polymeric millimeter-wave systems has potential applications in replacing the expensive metallic counterparts (a few thousand dollars for each waveguide) in current millimeter-wave systems.

3.1 Introduction Millimeter-wave systems are the key to remote detection/communication with the possibility to provide various sensing functionalities for all-weather applications. For example, extremely high data-rate short–range communication systems are among the emerging applications for the 60 GHz spectrum [1–3]. The 60-GHz band offers ample, license-free bandwidth. In the US, the range from 57 to 64 GHz Industrial Scientific, and Medical (ISM) band is available, while in Japan, 59–66 GHz is also available [4]. With seven gigahertz of bandwidth, many high data rate applications have been investigated based on silicon germanium (SiGe) technology such as wireless personal area networks (PAN), wireless high definition multimedia interface and point-to-point 60 GHz links [1–5]. In addition to the aforementioned 60-GHz band, there are other interesting and potentially high-volume millimeter-wave bands. For example, the licensed E-band is for point-to-point communications, useful for telecommunications backhauls or point-to-point local-area

Y-K. Fuh (B) Department of Mechanical Engineering, University of California, Berkeley, CA 94720, USA e-mail: [email protected]

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networks. Another major interest is the vehicular radar, which the 76–77 GHz band is allocated for forward-looking as well as rear short-range vehicular radars [6, 7]. Such radars are also called “adaptive cruise control” or “collision avoidance” radars, and would provide drivers useful warnings about obstacles in their path and therefore, would be an evolutionary step towards intelligent traffic systems. Also of interest is the 94-GHz band. It could be used for imaging or wireless communications. The wavelength at 94 GHz provides excellent resolution for imaging applications as many materials, clothes included, are transparent to 94 GHz. This provides an opportunity for possible security applications, such as airport screening to detect weapons, explosives and chemical or biological materials [8–10]. Other possible applications in the 94 GHz range include vision goggles that can assist firefighters to see through smoke, mobile radars that can enhance driving safety in foggy/rainy weather, and satellite uplink/downlink communication systems. One futuristic application, for example, is a millimeter-wave enhanced “smart goggle” worn by homeland security personnel at airports and public places to detect concealed weapons without going through X-ray detection. The camera operates by detecting heat naturally emitted by the human body in mm-waves, generating images of the heat silhouette to expose objects that block or attenuate heat. The motivation of this work came from the cost and size impact of typical millimeter-wave systems, where individual metallic components such as waveguides, antennas, and couplers are fabricated individually and assembled manually such that the manufacturing cost is high. We propose and successfully developed a low-cost, integrated front-end manufacturing process utilizing the existing millimeter-wave device concepts with new approaches from micromachining processes such as polymer molding and electroplating to build light-weight, low-cost, portable millimeter-wave systems for applications including mobile radars, and satellite uplink/downlink systems. This paper is organized as follows. In Section 3.1 we briefly discuss the development and applications of mm-wave radar systems. An overview of polymeric mm-wave systems using micromachining technologies is given in Section 3.2 and various demonstrated polymeric mm-wave components are discussed in Section 3.3. We will explore some of the fundamental issues relevant to the polymeric MEMS architectures in Section 3.4 and followed by conclusion in Section 3.5.

3.2 Polymeric Millimeter Wave Systems using Micromachining Technologies The proposed integrated manufacturing is to use micro molding techniques and electroplating processes to fabricate three-dimensional structures combining antenna, splitter, waveguides and other passive mechanical components in a batch process fashion. The dramatic difference in architecture as compared to the traditional system is the batch process to reduce the manufacturing cost. In order to make a versatile front-end manufacturing process, we propose to build plastic manufacturing

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modules, including plastic molding, embossing, mechanical polishing, assembly and bonding processes as shown in Fig. 3.1. This process eliminates current manualassembly requirement of bulky mechanical reflectors, and phase-shifters/amplifiers in single-mode millimeter-wave waveguides to reduce cost, size and operation power. The key advantage of this process as compared with other processes, such as stereo-lithography or EFAB [11] is that this approach is better suited for millimeter-wave systems, such as antennas, waveguides, and coaxial transmission lines. First, these components are relatively big three-dimensional structures (up to mm range) and it will take a considerably longer processing time for the competitive thin-layer processes to construct these structures. Second, multiple alignment steps are expected by using thin-layer based processes such that the sidewalls of waveguides are expected to be rough. A “three-thick-layer” architecture for the three-dimensional antenna array can be fabricated based on the process modules as illustrated in Figure 3.1. The proposed thick-layer manufacturing process is versatile and can be applied for devices beyond this work. For example, the two fabrication examples in Figure 3.1 of circular coaxial and rectangular waveguides use “twothick-layer” structures. Another example of a three-thick-layer architecture for the three-dimensional antenna array can be fabricated based on the same process modules as illustrated in Figure 3.2 where the horn-shape antenna is to be fabricated as part of the integrated system.

Fig. 3.1 Cross-sectional views of various process modules for the three-dimensional, plastic-metal manufacturing process for integrated millimeter-wave systems, including (a) molding or embossing of plastic substrates, (b) electroplating of metals, (c) mechanical surface polishing, (d) new polymer filling, polishing, metal lift-off or patterning and (e) assembly and bonding for integration. Two millimeter-wave components are shown, including a 3-D coaxial transmission line and a rectangular waveguide

Figure 3.3 illustrates a further embodiment of a schematic 4×4 mm-wave radar system using the rectangular waveguide and waveguide-based components in the feeding networks. For W-band systems, the dimension of a waveguide is 2.54×1.27 mm2 and the fabrication process is typically done by precision machining on a metallic block followed by brazing a metallic cover to enclose the waveguide. In the new polymeric molding process as illustrated in Figure 3.3, an

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Fig. 3.2 Fabrication example of the proposed process modules. The horn-shape antenna is to be fabricated as part of the integrated system (a). The second layer substrate is molded to have the desired rectangular waveguide shape and bonded with the first layer. An electroplating process is conducted and followed by a mechanical polishing process to clean the metal on the surface as shown in (b). The third layer is first molded to have the desired shape as illustrated and the back of the layer is deposited and patterned with a layer of metal to provide the top surface of the waveguide structure. It is then bonded with the system and a reshape mold is applied to define the horn antenna in (c). The system is completed by final electroplating and polishing process in (d)

Fig. 3.3 A 4×4 beam-former horn array illustrating the architecture of the 3D mm-wave radar system. (a) Top view showing the main components of the system include, horn array antennas. (b) Sectional view showing waveguides, couplers, T-junctions, and resonant cavities

aluminum mold insert is fabricated by mechanical machining processes and is used to shape a polymeric substrate in the molding process to form an open waveguide at a temperature above the glass transition point of the chosen polymer. The polymeric replica is then detached and a metallic seed layer, such as 200 Å/6000 Å Cr /Pt is sputtered for the electroplating step. A second substrate is sputtered with the same

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seed layer and is clamped on top of the first substrate to cover the open waveguide structure. The clamped combination is then immersed into a gold electroplating bath to deposit an 8 μm-thick gold layer. The selective electroplating process also metallically seals the waveguides. Fabrication processes of polymeric MEMS mm-wave systems can be classified into low and high aspect ratio operations according to structural geometries of various components. For low aspect ratio components such as waveguides and waveguide-based iris filters, the process is illustrated in Figure 3.4a–c where micro molding, selective electroplating and assembly processes are routinely used. For high aspect ratio structures such as waveguide-fed horn antennas, a self-aligned 3D hot embossing molding process is conducted, followed by 2-step selective sputtering (front and back side of polymer substrate) and in-channel electroplating as shown

Fig. 3.4 Fabrication process of typical polymeric MEMS mm-wave components. Low-aspectratio components such as waveguide and waveguide-based Iris filters, polymeric waveguides are illustrated in (a)–(c). In process (a), polymer substrate is molded to create the waveguide shape. (b) Selective electroplating to deposit metallic seed layer. (c) A second polymer substrate is assembled by means of selective electroplating and bonding process. High-aspect-ratio structures such as waveguide-fed horn antenna are fabricated in steps (d)–(f). (d) Font-side and back-side views of a polymeric substrate fabricated by means of self-aligned 3D hot embossing process using both front-side and back-side mold inserts. (e) Selective seed layer deposition in the front and back side. (f) A second polymer substrate is assembled by means of selective electroplating and bonding process

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in Figure 3.4d–f. There are two key technology challenges which require careful investigation. First, the plastic-to-plastic bonding process in which the bonding strength and integrity is of great importance. This critical metal bonding process is accomplished by the approach of selective electroplating and bonding process developed previously [12]. Fundamental issues about the polymer metallization process such as conformal and uniform deposition of seed layers as well as mass transfer and current density during the in-channel electroplating process are addressed in Section 3.4.

3.3 Fabrication Examples of mm-Wave Components 3.3.1 Polymeric Waveguides Rectangular waveguides and waveguide-based systems are commonly employed for millimeter-wave systems because of their low loss and high power-carrying capabilities compared to microstrip structures. Currently, rectangular waveguides are fabricated using conventional machining techniques in metal and later assembled/mounted to construct a complete millimeter-wave system. High frequency systems demand small feature sizes such that micromachining technologies are natural alternatives. Previously, Tai et al. have demonstrated a silicon-based rectangular waveguide using bulk micromachining processes of a (1 0 0)-silicon wafer with an insertion loss of 0.04 dB/λ for a frequency range of 75–110 GHz [13]. LeDuc et al. integrated superconductor-insulator-superconductor (SIS) tunnel junctions mounted on a nitride membrane with a bulk micromachined rectangular waveguide using wet etching of a (1 0 0)-silicon wafer. The waveguide was tested for a frequency range of 170–260 GHz and a 0.8 dB per wavelength insertion loss was measured [14]. Davies et al. have fabricated a reduced-height, air filled, surface-micromachined Wband rectangular waveguide. The waveguide performance was poor due to height limitation and the measured insertion loss was 0.2 dB/λ [15]. Katehi et al. demonstrated a diamond-shape waveguide in W-band using wet etching of a (1 0 0)-silicon wafer and the mismatch between the WR-10 ports of the network analyzer and the diamond waveguide caused an insertion loss of 0.135 dB/λ [16]. We present a polymeric, hot-embossed, W-Band waveguide. In contrast to the previous works, three distinctive achievements have been accomplished: (1) plastic waveguides using batch embossing technologies [17, 18], (2) metallic coating and sealing by selective electroplating and bonding, and (3) integrating a precision hot-embossed flange using press fitting/instant glue bonding with subsequent planarization. Figure 3.5 shows two SEM micrographs of an overview of the fabricated waveguide. From the preliminary observation, the metallic surface is smooth and electroplated sealing is good with no observable leak. The scattering parameters s11 (return loss) and s12 (insertion loss) of the waveguide are measured from 75 to 110 GHz and a two-piece flange connection port has been fabricated as an adaptor connecting the waveguide to the Agilent PNA 5250 network analyzer. Figure 3.6a

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Fig. 3.5 SEM pictures of the fabricated waveguide. (a) The lower left corner of the waveguide and (b) close up view of the upper left corner showing the good sealing between the 2 wafers

shows measured prototype device s11 and s12 values of –14 dB and –1.5 dB at 95 GHz, respectively and 71% of the signal is successfully transmitted as compared to commercial all-metal waveguides at 85%. Figure 3.6b is the photo of the fabricated waveguide that is 2.54 cm in length and Fig. 3.6c is the close-up tilted view of the waveguide showing both the input and the output ports. Detail information regarding design, fabrication and characterization of proposed 95 GHz polymeric mm-wave rectangular waveguide can be found in reference [19, 20].

3.3.2 Waveguide-Based Iris Filters Micromachined three-dimensional (3D) processes have been demonstrated to make coaxial transmission lines to construct high frequency components, including filters [21]. For example, Chen et al. have demonstrated a compact, low-loss Ka-band filter using coaxial line architecture but the fabrication process requires forty-one layers [22]. Asao et al. have shown a metal-plated plastic waveguide filter using injection molding for Ka-band applications [23]. Chi et al. have reported a planar inter-digitated bandpass filter operating at 20 GHz using silicon-based micromachining processes [24]. Robertson et al. have presented a membrane supported W-band bandpass filter using a 5-element, coupled microstrip line in shielded cavity [25]. Jiang et al. have made Ka-band filter using an SU-8 UV lithography and assembly process [26]. In addition, Lee et al. have fabricated perfluorocyclobutane (PFCB) optical waveguides of 41×47 μm2 cross-section using a PDMS molding process [27]. These works show examples of innovative processes and materials to make various filters. Here, we present a different class of micromachined filters based on hollow waveguides with a cost-effective hot embossing molding and electroplating process. Based on the developed polymeric waveguide approach, 5-cavity iris filters are designed using Chebyshev synthesis method by constructing resonant cavities inside

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Fig. 3.6 (a) Scattering parameters measured using Agilent Network analyzer PNA5250. At 95 GHz, the return loss parameter, s11 , is –14 dB and the insertion loss parameter, s12 , is –1.5 dB. At 92.5 GHz, s21 is –0.7 dB (85% transmission) (b) optical photo of fabricated waveguide with polymeric flange and (c) close-up view of metalized cross-section

the polymeric hollow waveguide with a coated metal layer [28, 29]. Integrated plastic flanges have also been fabricated and connected to these filters by press fitting as the matching connectors between the filters and network analyzer during the experimental characterization processes. Figure 3.7a is the Iris filter measurement results. This filter shows a bandwidth of 3.05 GHz centered at 96.77 GHz while simulation predicts a bandwidth of 3.5 GHz centered at 96.63 GHz. Minimum insertion loss is –1.22 dB and a return loss better than 9.3 dB over the entire pass band. Figure 3.7b is the optical photo of fabricated filter and 3.7(c) is the Scanning Electron Microscope (SEM) picture showing the iris section with thickness of 500 μm.

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Fig. 3.7 (a) Iris filter measurement results. This filter shows a bandwidth of 3.05 GHz centered at 96.77 GHz while simulation predicts a bandwidth of 3.5 GHz centered at 96.63 GHz. Minimum insertion loss is –1.22 dB and a return loss better than 9.3 dB over the entire pass band. (b) Optical photo of fabricated filter. (c) SEM picture showing the iris section

3.3.3 Waveguide-Based Tunable Filters and Phase Shifters Tunable filters and phase shifters can play a key role in millimeter-wave systems, especially in multi-channel communication and electronically scanned radar systems. The state-of-art tunable filters at high frequency have been based on solid-state varactors [30]. However, there are major disadvantages of this approach, such as high losses, unacceptable signal-to-noise (SNR) ratio, and rendered linearity. Over the past decade, radio frequency micro-electro-mechanical systems (RF MEMS) provided an alternative way of building tunable filters for multi-band receivers. For example, MEMS varactors have been employed by Liu et al. in order to realize a transmission line with voltage-variable electrical length. Tunable filters with 3.8%

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tuning range at 20 GHz and a minimum insertion loss of 3.6 dB were demonstrated [31]. Entesari et al. presented wide-band tunable filters using a digital capacitor bank for 6.5∼10 GHz and 12∼18 GHz ranges with an insertion loss varying between 5.5 and 9 dB [32, 33]. A reconfigurable low-pass filter was reported by Lee et al. using multiple MEMS contact switches. The values of the inductors and capacitors were changed independently while the filter cutoff frequency dropped from 53 to 20 GHz [34]. Robertson et al. presented a micromachined W-band bandpass filter at 94.7 GHz without tuning capability [35]. Uher et al. described a magnetically tunable E-plane large-gap finline filter where the waveguide sections are symmetrically loaded with ferrite slabs. A midband tuning from about 14.1 to 15.7 GHz was achieved [36]. Almost all the tunable filters reported in the literature are discrete type and most of them suffer from high insertion loss. On the other hand, phase shifters are important elements in testing and measurement systems and they play a key role in phased array antennas where the antenna beam is steered electronically in space. There are various techniques to build phase shifters such as using ferrite materials where a change in the bias field of the ferrite induces time delay on the wave. Other approaches include the use of solid state devices such as microwave diodes and FET [37]. Ferrite phase shifters consume low power; while diode-based phase shifters provide the advantages of small size, integrability with planar circuitry, and high speeds. FET-based phase shifters have low-power consumption, but introduce a lot of signal losses. Zuo et al. demonstrated a ferrite phase shifter with a differential phase shift of 90◦ /KOe.mm at a frequency of 20 GHz and an insertion loss of 0.75 dB/mm [38]. Moreover, Shan et al. reported a 90◦ nonreciprocal phase shifter at 12 GHz using an H-plane ferrite-slab loaded into a rectangular waveguide [39]. Glance described a 14-GHz 4-bit p-i-n microstrip phase shifter with an insertion loss of 1.4 dB with a switching time of 1 nsec and a switching power of 15 mW [40]. Phase shifters based on MEMS technologies offer low-loss and low-power consumption alternative to the solid-state phase shifters, and are implemented as MEMS switches that replace the solid-state switches. Hung et al. have developed a 2-bit wide band distributed MEMS transmission lone phase shifter with discrete phase shifts of 0◦, 89.3◦, 180.1◦, and 272◦ at 81 GHz with an average insertion loss of 2.2 dB [41]. In addition, Lakshminarayanan and Weller presented an electronically tunable thru-reflect-line (TRL) using a 4-bit time delay MEMS phase shifter built on a coplanar waveguide (CPW) sections. A phase shift of 90◦ /mm was reported at 50 GHz [42]. In the previous section, a micromachined W-band iris filter with 3.5% bandwidth at 95 GHz using polymer hot-embossing technologies has been demonstrated. This section presents tunable W-band iris filters and phase shifters using deformable membrane for microwave tunable filter operating at 95 GHz [43–45]. Figure 3.8a shows the schematic diagram of a 2-cavity iris filter with two deformable, circular membranes on the top surface of each cavity. In the figure, “a” and “b” are the width and height of the rectangular waveguide, respectively; rm is the radius of the diaphragm; R is the length of the resonant cavity; d1 , d2 , d3 , are iris gaps and t is the iris thickness. In the prototype design, the deformable diaphragm is controlled by an external pump and this could be further improved by using built-in MEMS actuators. Figure 3.8b is a transmission line model for the tunable filter where the

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Fig. 3.8 (a) Schematic diagram of the W-band tunable filter. Equivalent circuit of a 2-cavity iris filter where the metal layers are modeled as inductive shunts between transmission lines of variable electrical length 1 and 2 respectively in (b); (c) transmission line equivalent circuit with negative-length sections forming impedance inverters; (d) equivalent circuit using inverters and λ/2 resonators

inductive metal planes are modeled as parallel inductive shunts of impedance, X, and the resonant cavities are modeled as transmission lines of electrical length 1 and 2 respectively. In this 2-cavity design, 1 equals 2 and X1 equals X3 due to symmetry (d1 = d3 ). The deflection of membrane changes the electrical lengths of the transmission lines and the center frequency of the filter can be tuned accordingly. The change in the electrical length of the transmission lines adjusts the time delay of the propagating waves and this property can by used as a continuous phase shifter. The tunable filter scattering parameters s11 (return loss) and s21 (insertion loss) were measured from 75 to 110 GHz using Anritsu ME7808B network analyzer. The membrane deflection is first characterized under a probe station. When vacuum is applied, the deflection of the membrane is about +150 μm. When a pressure of 0.25 atm is applied, membrane deflection of –50 μm is expected. These deflection data were gathered under the microscope using the focusing/defocusing method and the accuracy can be as good as10 μm. The experimental insertion loss data in Figure 3.9a shows an insertion loss of 2.36 dB, 2.37 dB, and 2.4 dB when the membrane deflections are +150, 0 and –50 μm, respectively. The return loss shown in Figure 3.9b is always better than 15 dB and the center frequency drops from 96.59 to 94.79 GHz and to 94.00 GHz. Therefore, the tuning range is 2.76% of the center frequency and Table 3.1 summarizes the tunable filter performance. The simulated data at zero deflection shows a bandwidth of 4.2 GHz centered at 94.38 GHz, while the measured data shows a bandwidth of 4.05 GHz centered at 94.79 GHz. The extra insertion loss is attributed to the gap between the devices under test (DUT) and the network analyzer adaptors as observed previously from a time domain plot [20]. The tunable filter can be configured as a phase shifter and Figure 3.10 shows the measured phase from 75 to 110 GHz. Without membrane deflections, both cavities

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Fig. 3.9 Measured (a) insertion loss and (b) return loss of the tunable two-pole filter which the operating between 94 and 96.6 GHz

Table 3.1 Filter performance due to membrane deflection Deflection [μm]

−50

0

+150

fc1 [GHz] fc2 [GHz] fc [GHz] I. L. [dB] BW [GHz] % BW

92.00 96.05 94.00 2.4 4.05 4.31

92.79 96.84 94.79 2.37 4.05 4.27

94.48 98.75 96.59 2.36 4.27 4.42

Fig. 3.10 Measured phase shift using the tunable two-pole tunable iris filter

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resonate at the center frequency, f01 , and as the membrane deflects, the center frequency changes while waves within the pass band experience a phase shift. Table 3.2 summarizes the measured phase data as well as the insertion loss at 95 GHz. A total phase shift of 110◦ at 95 GHz was achieved upon deforming the membrane from –50 to 150 μm and this comes with an additional 1.11 dB insertion loss. These data agree qualitatively well with the simulated results using HFSS. A total phase shift of 97.17◦ is predicted using HFSS for membrane deflections between –50 and +150 μm while a total phase shift of 110◦ is measured. Table 3.2 Measured phase shifter characteristics Deflection [μm]

I.L. [dB]

φ [deg]

φ [deg]

−50 0 150

2.9 2.37 3.48

130 164 240

0 34 110

3.3.4 Waveguide-Fed Horn Antennas Conventional horn antennas and waveguides are made of 3D metallic materials [46]. Recently, micromachining technologies have been proposed to construct three-dimensional wireless components and systems massively and in parallel. For example, silicon micromachined antennas have been demonstrated by using anisotropic silicon etching to construct 3D horn flare angles by combining two wafers having V-shape grooves [47], by using silicon nitride membranes on top of open pyramidal cavities made by silicon wet etching process [48], or by using several layers of micromachined silicon to construct an octagonal horn antenna [49]. The flare angles of these antennas are limited by the crystalline orientation of silicon due to the anisotropic silicon etching processes. The LIGA process, on the other hand, has also been used to make a tapered slot antenna [50]. However, it is well known that the LIGA process is not suitable to make true 3D structures. A layer-by-layer electrochemical fabrication (EFAB) process has been used to build a miniature rectangular coaxial transmission line for Ka band applications but a total of 41 layer processes is required [51]. Electroforming, on the other hand, has been used to demonstrate a single corrugated horn antenna in W-band [52]. However, the stripping step from mandrel prohibits its application to make 3D-integrated structures such as combination of the horn antenna and waveguide network. Furthermore, the electroforming process results in heavier products as compared with polymer-based structures [53]. Here we demonstrate a simple, selfaligned plastic micro hot embossing technique with an internally coated metallic layer to construct millimeter-wave components [54, 55]. A horn antenna fed by a 90-degree E-plane bend and connecting rectangular waveguide has been chosen as the demonstration example.

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Figure 3.11a illustrates the diagram of a single waveguide-fed pyramidal horn antenna to be built. An analytical approach provides fast turn-around time for the first level evaluation of the antenna system such as the influence of dimensional variation on antenna gains as well as the possibility to analyze an array of antennas by superposition. A pyramidal horn is flared in both the E and H planes and the radiation characteristics are basically a combination of the E- and H- plane. The design of the pyramidal horn uses the optimum gain method by specifying the dimensions of the waveguide and the desired antenna gain. In order to physically realize and design a pyramidal horn antenna, the following parameters are calculated according to [56–58]: height of the pyramidal horn (L3 ); length (a) and width (b) of the horn antenna at its base in the E and H-plane; the flared length (a1 ) and width (b1 ) of the horn antenna at its distal end as illustrated in Fig. 3.11a. (a)

(b)

Fig. 3.11 A single 3D horn antenna with design dimensions (a) and design graphs based on the analytical results given by horn antenna theory (b)

Figure 3.11b shows the analytical results of antenna gain with respect to the dimensions of the pyramidal horn based on WR-10 waveguide. For a desired gain of 17 dB at 76.5 GHz, dimensions a1 , b1 , and L1 are calculated as 12.73, 9.8, and 9.53 mm respectively. It is noted that higher gain will require larger dimensions and L1 becomes the dominating dimension when the desired gain is larger than 19 dB. A waveguide-fed horn antenna which consists of E-plane bend and direct waveguide connection to a horn antenna has been demonstrated as an alternative way for the integration of antenna and waveguide systems, which is potentially very useful for the integrated polymeric fabrication process. The return loss, s11, of the waveguide-fed horn antenna is measured and compared with simulation result using HFSS as shown in Figure 3.12a. The return loss, s11 at 95 GHz is measured to be −17.5 dB and the measured return loss of better than –10 dB demonstrates broadband attributes with bandwidth of 25.2 GHz (26.5%) between 76.5 and 101.7 GHz. It is noted that the measured return loss is better than the simulated return loss by about 3 dB. A second simulation is conducted to include the effect of the extra 1 mm-wide gold layer. From the simulation results, an average of 2 dB lower return loss is observed as compared to the model without the extra gold layer. Figure 3.12b

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Fig. 3.12 Scattering parameters for the waveguide-fed horn antenna. (a) Simulated and measured return loss. (b) Simulation and measured radiation patterns of the antenna for the co-polarized E and H-planes. The inset in (c) shows the optical photo of fabricated horn antenna

shows the simulated (based on the fabricated dimensions) and measured radiation patterns of the antenna between –90◦ and +90◦ for both co-polarized E and H-plane, respectively. The radiation patterns in both planes agree relatively well between simulation and measurement results between –50◦ and +50◦ , indicating the effectiveness of design methodology and fabrication process. The measured 3 dB beam-widths of the E- and H-plane patterns are 26◦ and 23◦ respectively. At 95 GHz, the directivity based on measured 3 dB beam-width is calculated at 17.33 dB as compared with simulation results at 17.02 dB.

3.3.5 W-Band Waveguide Feeding Network of a 2×2 Horn Antenna Array In order to demonstrate the capability of integration with other millimeter-wave components, a 2×2 horn antenna array feeding network has been designed and optimized using HFSS simulations. The components such as resonant cavities, T-junction with power splitters, horn antennas, E-plane bend and feeding waveguide networks, are achieved by using a single shot hot embossing process. The microwave power is designed to distribute equally to four antennas by power splitters as shown in Figure 3.13 and the three T-junctions and related power splitters were designed to match the incoming waves and minimize reflections. The 3D, high-aspect-ratio micro hot embossing process is used to fabricate this polymeric 2×2 antenna array. The process starts with the fabrication of an upper mold insert piece by mechanical machining process to construct the horn pattern and another lower mold insert piece to construct the WR-10 rectangular waveguide networks. The polymer 3D horn antenna array fabricated with the self-aligned 3D fabrication process is illustrated in Figure 3.14 in which 3D CAD model and fabricated R COC polyprototypes are presented. The mold is heated to 320◦ F for the Topas mer and a pressure of 22.64 KPsi is applied. At the end of the molding process, a thin layer of polymer residue of about 30 μm in thickness is found between the

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Fig. 3.13 Simulated electric field pattern at 76.5 GHz. (left) Power are designed to distribute equally for the four antennas by power splitters. (right) The three T-junction splitters are designed to match the incoming waves and minimize reflection losses

Fig. 3.14 (a) CAD model of the 2×2 horn antenna array feeding network. (b) Digital pictures of fabricated waveguide-fed 2×2 horn antenna array with top and bottom views

top and bottom mold inserts at the pyramidal horn and the waveguide intersection region, although both mold inserts are “contacted” in the molding process. This thin residual layer is removed using a razor blade. Afterwards, a 200 Å/6000 Å of Cr/Pd is sputtered as the seed layer for the electroplating process. An aluminum substrate with a seed layer made of 200 Å/6000 Å of Cr/Pd is added at the bottom. A polymer flange adaptor is designed to connect the waveguide to the spectrum analyzer and it is separately fabricated using the same hot embossing process and is fitted at the waveguide end [20]. Super glue (Loctite quicktite) is used to fix the adaptor with the waveguide-fed antenna. The external surface of the flange facing the spectrum analyzer is planarized afterwards using a lapping process with silicon carbide paper of very fine, 600-grid mesh. Finally, a selective electroplating and sealing process is conducted to deposit an 8 μm-thick gold layer on the internal surface of the antenna and to seal the waveguides. During the sputtering and deposition process, Kapton tapes are applied manually as the masking material to cover areas that do not need the metallic coverage. As a result, excess electroplated gold layer is deposited around the edge of the top surface of the horn antenna. Four screws are used to fasten the polymer antenna and cover plate before the electroplating process to ensure the in-channel sealing of waveguides.

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Comparison of simulated and measured return loss with respect to frequency for the 2×2 horn antenna array feeding network is performed and the simulated results are in good agreement with measurement between 75 and 76 GHz as shown in Figure 3.15. The measured reflection loss is better than 13.5 dB within the 5 GHz bandwidth from 75 to 80 GHz and the frequency shift is believed to come from the inaccuracy of assembly and fabrication processes.

Fig. 3.15 Simulated and measured return loss versus frequency of the 2×2 horn antenna array feeding network. The simulated results are in good agreement with measurement between 75 and 76 GHz and the measured reflection loss is greater than 13.5 dB within the 5 GHz bandwidth from 75 to 80 GHz

3.4 Fundamental Characterizations of Polymer Metallization Process 3.4.1 Surface Roughness Attenuation of commercially available rectangular waveguides was experimentally determined in various reports for the millimeter-wave transmission bands (25–200 GHz) and excess attenuation was found as a result of surface roughness [60]. We have used surface profiler to scan areas of 1×1 mm on both horn and waveguide regions of our fabricated samples and found that the root mean square (RMS) surface roughness is measured as 0.515∼1.34 μm, peak-to-peak roughness is 3.83∼9.36 μm. Figure 3.16 represents two measured cases (best and worse roughness). SEM pictures are taken on intersection areas of waveguide and horn as shown in Figure 3.17. For further investigation of surface roughness and the impact on attenuation, HFSS simulation was conducted. Previously, molded polymer waveguides were reported to have surface roughness RMS as 1.7 μm [59, 60]. Simulation results in Figure 3.18 show that at 76.5 GHz, the attenuation constant can be reduced by 18% if RMS roughness is reduced by half from 1.7 to 0.85 μm. However, this effect is not linear. For example, doubling the RMS from 1.7 to 3.4 μm,

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Fig. 3.16 Surface roughness measurement using surface profiler. (a) A good example of surface roughness with RMS of 0.515 μm and peak-to-peak roughness of 3.83 μm. (b) A worst case example with RMS of 1.34 μm and peak-to-peak roughness 9.36 μm

Fig. 3.17 SEM photos of gold-electroplated surface on the waveguide-fed horn antenna array

Fig. 3.18 Surface roughness and its impact on attenuation is simulated using HFSS. At 76.5 GHz, attenuation constant, which is the logarithmic reduction rate of change in amplitude and intensity of a signal, is reduced 18% when surface roughness is reduced by half. (1 Np/m=8.686 dB/m)

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the attenuation is increased only 7%. The typical surface roughness for commercial metallic waveguides WR12 was reported as 0.73∼0.82 μm using copper and 0.31∼0.57 μm using silver [60]. Our experimental characterizations have shown that these mm-wave components/systems could have similar surface roughness as the state-of-art metallic structures such that surface roughness will not be a problem for polymer-based mm-wave systems.

3.4.2 Characterization of In-channel Electroplating Thickness In the polymeric mm-wave system fabrication process, a selective in-channel electroplating and sealing step is conducted to deposit a metallic layer. Several engineering challenges are discussed here such as (1), electroplating kinetics inside the micro-channel due to the long distance & protrusions of these microchannels, and (2) non-uniformity on the electroplated metallic films arising from mass transfer and local current density variations. The characterization experiment is conducted and Figure 3.19a illustrates the schematics of electroplating characterization experiment. Results of deposited thickness versus distance along micro-channel are shown in 3.19b. In this experiment, a 2000 Å Cr seed layer is first sputtered on polymeric substrate and followed by electroplating with current density of 4∼5 mA/cm2 . The results show at the entrance the deposited metal layer is about 3.9 μm after the four-hour electroplating process. At the distal end of about 22 mm away, the thickness of the film decreases to 4.3 m.

Fig. 3.19 In-channel electroplating experiment (a) schematic of electroplating characterization. (b) Deposited thickness versus distance along the micro-channel

Finite element simulation is used to investigate and explain the experimental results with emphasis on mass transfer effects based on 2D incompressible NavierStokes equations. The waveguide with height of 1.27 mm and length of 30 mm is

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performed to characterize the flow of electrolyte as shown in Figure 3.20. As electrolyte flows into closed-end micro-channel, the velocity and pressure decreases and eventually becomes stagnant. The mass transfer of electrolyte solution is found to be of great importance and therefore, avoidance of close-channel stagnant flow with suitable openings on both ends of the microchannel is required for more uniform thin-film thickness.

Fig. 3.20 Flow simulation of mass transfer in a closed channel of 1.27 mm in height and 30 mm in length

The electroplating current density is a key factor on the thin-film thickness and Faraday’s law is used to provide some explanations [61]. Where m is the mass of deposited material, α is the current efficiency, I is the total current, t is the duration of the deposition, n is the charge of the deposited ions, F is Faraday’s constant, h and A are the thickness and area of the deposit thin film, ρ is the density of the deposit thin film, M is the molar mass and i is the current density. The deposition rate (thickness over time) is directly proportional to the current density and time as shown. However, results in Figure 3.19b does not reflect this analysis as the experiments were conducted in “closed” channel while the above equations are based on open fields with endless supplies of electrolyte. Future analytical model should be established based on the special characteristics of the “in-channel” deposition conditions.

3.4.3 Geometry Effects One particular issue we have observed is the residual polymer remaining at the neck of the horn antenna where the top and bottom mold inserts are in contact during the molding process. There are possible residuals of polymer left even after efforts of using blades to remove them. Figure 3.21a shows the FEM simulation region and grids assuming a 20 μm-wide polymer residue is left in the connection region of horn antenna and waveguide. The simulated electric field (arrow), electric potential (contour line) and current density distribution (color) are shown in (b) and (c), respectively. One can clearly identify four high peaks with two highest peaks at the

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Fig. 3.21 Effects of residue polymers. (a) FEM grids and the 20 μm-wide residue polymer at the transition region between horn antenna and waveguide. (b) Simulated electric field (arrow), electric potential (contour line) and current density (color) distribution. (c) 3D current density plot indicates four peaks with two highest peaks at residue polymer regions and two smaller peaks at the open entrance of horn antenna

polymer residue region and two smaller peaks at the entrance of horn antenna and will result in non-uniform deposition rate according to Faraday’s law. This effect is further investigated by implementing the ALE (Arbitrary Lagrangian-Eulerian) technique using moving boundaries in the simulation for the non-uniform deposition process [62]. The FEM setup and grids are shown in Figure 3.22a where a flat anode is assumed and the cathode is on the surface of the channel-shape structure. The simulated electric field (arrow), potential (contour line) and current density distribution (color) are shown in Figure 3.21b. Uniform electric

Fig. 3.22 Electroplating simulation on the effect of sharp corner during the electroplating process. (a) Simulation setup and grids. (b) Simulated electric field (arrow), potential (contour line) and current density distribution (color). (c & d) A close-up view in the waveguide transition region. (e–h) Deposited thickness after 10, 30, 50 and 100 min, respectively

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field and current density can be observed away from corners whereas the closeup views of sharp corners in Figure 3.21c–d indicate a order-of-magnitude higher current density. Figure 3.22e–h simulates the deposition results as time progresses and the ALE deformed mesh plots can be used to estimate the deposition thickness. Figure 3.22e indicates that after 10-min electroplating process, the deposited thickness at the corner is approximately 2 times larger than the other areas. The predicted spikes actually grow faster as illustrated in Fig. 3.22f–h. This is due to the fact that electric field follows the Coulomb’s law and is inversely proportional to the square of distance. As the spikes grow bigger, the distance between the anode and cathode is reduced. The simulation is in good agreement with experimental observations where gold spikes can be found around the sharp corners. Therefore, it is very important to control and characterize the geometrical irregularities such as sharp corners during the electroplating process to assure uniform deposition of the metallic thin film layer. There are several approaches to alleviate the non-uniform deposition due to the geometrical effects. First, a careful cleaning and polymer-removing processes should be adopted to reduce polymer residues. For example, sonification in conjunction with acetone/IPA solution is found effective experimentally. Second, a two-step electroplating process is employed. The process starts with electroplating on an “open” channel for about 3 μm-thick gold layer. The top plate is applied and the selective deposition and sealing process is followed for another 5–7 μm thick gold layer. This process reduces the non-uniformity problem due to the difficulty of mass transfer in “closed channels.” Figure 3.23a shows the SEM picture with severe gold spikes in the perimeter due to residue polymer. The modified process shows significant improvement on surface quality in Figure 3.22b and c. Some polymer residues are folded on the sidewall and may be due to polymer flow during the hot embossing process.

Fig. 3.23 SEM photos for the electroplating results. (a) Severe gold spikes can be seen in the horn and waveguide intersection perimeters due to residue polymer. (b) SEM photo and (c) close-up view showing improved surface quality by adopting the proposed process modifications including sonification and two-step electroplating. The scale bar is 20 μm

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3.5 Conclusion In this work, we propose and successfully developed low-cost and integrated manufacturing processes for millimeter-wave front-end sensing systems/components, including the fabrication process to make low-aspect-ratio structures such as waveguide and waveguide-based Iris filters and high-aspect-ratio structures such as waveguide-fed horn antenna using polymeric substrates. In contrast to the previous works in conventional mm-wave systems using mechanical machining processes or emerging RF-MEMS silicon systems using micromachining technologies, several distinctive achievements have been accomplished: (1) polymeric substrates with batch embossing/micro molding technologies, (2) metallic coating and sealing by selective electroplating and bonding, and (3) component integration by a one-shot molding process. Furthermore, the proposed fabrication process can be further advanced toward a full millimeter-wave system with built-in microstructures such as micro Iris structures for filters, micro membrane structures as tunable filters or phase shifters, and integrated networks as the frontend systems for antennas. We believe this technology provides the capability for low-cost manufacturing and the feasibility of integration with other micro electromagnetic-wave components, such as antennas, transmission lines, and phase-shifters as integrated millimeterwave systems. Possible applications include mobile radars that can enhance driving safety in foggy/rainy weather or battle field, and satellite uplink/downlink communication systems. Any system that resembles the “smart goggle” concept for millimeter-wave, lightweight, low-cost sensors could benefit from this integrated manufacturing and miniaturized system architecture.

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Chapter 4

Millimeter-Wave Chip-on-Board Integration and Packaging Edward B. Stoneham

Abstract A form of chip-on-board integration and packaging is being applied to millimeter-wave electronics to bring it into the low-cost, high-volume arena. This chapter gives some pointers on how low cost is achieved and then discusses the particular problems of millimeter-wave circuit performance. These problems have to do with interconnect lengths, encapsulant effects, shielding effectiveness, and cavity resonances. Also discussed are issues with thermal expansion mismatch and environmental control. What then follows is a description of the low-cost chip-on-board method for millimeter-wave integration and the means by which it overcomes the various millimeter-wave-specific problems. This solution combines existing surface-mount PC board technology with the highly-automated die attachment and wire bonding operations used in the plastic packaging industry and places bare millimeter-wave chips in environmentally protected air cavities. Examples of millimeter-wave products utilizing this technology are described, and some price points are given.

4.1 Motivation for a Chip-on-Board Approach for Millimeter-Wave Product Manufacturing 4.1.1 The Drive for Low Cost The history of electronics has been one of upward movement in frequency. At each stage of progress from audio to AM broadcast to short wave to VHF, UHF, microwave, and now millimeter-wave the trend has been to start with high-priced products for specialized applications and then to develop the means to bring prices E.B. Stoneham (B) Stoneham Innovations, Los Altos, CA 94024, USA; Endwave Corporation, San Jose, CA 95134, USA email: [email protected]; [email protected]

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down to the consumer level. Microwave electronics has reached the consumer level with Wi-Fi at 2.4 and 5.8 GHz and with radar at 24 GHz. The second decade of the twenty-first century will likewise see millimeter-wave electronics reaching consumer markets at affordable prices. Though millimeter-wave frequencies range technically from 30 to 300 GHz, the part of the spectrum that is seeing the most immediate applications is the portion between 30 and 100 GHz. This range includes a couple of bands in use for scanning and imaging, a wide band about 60 GHz that has been allocated for license-free use, a pair of easily-licensed bands from 71 to 76 GHz and 81 to 86 GHz for high speed data links, a 76–77 GHz band being adopted for automotive radar use, and a 92–95 GHz band that has been allocated in the U. S. for license-free use. The main entry points for high-volume consumer product introduction are the licensefree 60-GHz and 76–77 GHz bands. These are the frequencies for which low-cost integration and packaging is most needed.

4.1.2 Low-Cost Manufacturing Processes Achieving low cost requires attention to the cost of labor and capital, the cost of materials, and the scalability. Success on any two of these fronts is not sufficient without success on the third. 4.1.2.1 Minimizing Labor and Capital Cost per Unit In modern electronics labor has been minimized through the introduction of highlyautomated massively parallel processing. Figure 4.1 illustrates three of the most prominent low-cost manufacturing technologies. In all three technologies many units are connected together in two-dimensional arrays so that an entire array of units can be processed together through each step of the manufacturing process. The cost of each manufacturing step, which is primarily labor and capital depreciation, can be spread over the many units in the array. In some cases, such as in the lamination of circuit boards or chemical etching of semiconductor wafers, the arrays can be stacked in a third dimension to spread the cost over an even larger number of units. Automation enters into the processing of semiconductor wafers through the use of capital-intensive machinery that can do cassette-to-cassette transfer and batch processing of lots of typically 25 wafers at a time. In the circuit board industry there is automation in the fast numerically-controlled drilling and routing equipment and in the screen printing equipment, and the automation reaches particularly high levels in the surface-mount placement operations that transfer parts to the boards at high speed prior to solder reflow. Most impressive, though, is the automation achieved in plastic packaging lines in which semiconductor chips can be picked and placed and wire bonded at over 10,000 units per hour on a single manufacturing line.

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Fig. 4.1 Examples of prominent manufacturing technologies employing highly-automated, massively parallel processing. Upper-left–semiconductor chip processing on wafers. Upper-right– circuit board processing on laminated panels followed by surface-mount assembly. Bottom–chip packaging on leadframes

While processing of arrays of units in parallel and use of highly-automated manufacturing capabilities must be embraced to reduce cost, there are also many labor-intensive and capital-intensive operations that have to be avoided in order to prevent additions to cost. They include, for example, RF testing, hand tuning, hermeticity testing, and reworking of defective units. DC testing is much less expensive than RF testing, since DC testing is faster and requires less expensive equipment, and DC testing can in many cases be used in place of RF testing to screen parts and to prevent further processing of defective units. Hand tuning is prohibitive, when every second of labor is a significant addition to cost. Hermeticity testing, which includes bubble testing and helium fine leak testing, is too time consuming for low-cost manufacturing. Meanwhile, on a low-cost manufacturing line reworking of defective units typically costs more in labor and reliability than the material saved is worth. It is important that manufacturing yields be high enough to justify the abandonment of these expensive remedial operations. Among the types of manufacturing capabilities that are common in the electronics industry some are more expensive than others. Sheet metal operations such as rolling, stamping, and forming are generally less expensive than solid metal operations such as die casting and extruding, and the latter are usually less expensive than numerically-controlled machining. In the patterning of films screen printing, ink-jet printing, plating, and etching are much less expensive than vacuum deposition and photolithography. In the application of adhesives such as conductive or nonconductive epoxies screen printing, spray coating, and roller coating are less expensive than automatic dispensing.

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4.1.2.2 Minimizing Materials Cost In the choice of materials for low-cost manufacturing there are some generalizations to be considered. At the low end of the cost range are molded plastics and organic or composite laminates. The latter include circuit board materials such as FR4, the workhorse of the PC board industry. Unfortunately, the dielectric loss tangent of FR4 (typically 0.02) is so high that the dielectric losses at millimeterwave frequencies are prohibitive. More expensive materials, termed “RF laminates,” become preferable as materials choices. Such materials include polytetrafluoroethylene (more commonly known by the Dupont trademark TeflonTM ), liquid crystal polymer (LCP), polyimide, and various other low-loss organic polymers with fillers such as fiberglass or ceramic powders. The RF laminates should be used sparingly to keep costs down and may be included as just one or two layers on a stack of FR4 layers in a multilayer PC board. Progressing toward the higher end of the materials price range are bulk metals, ceramics, glasses, metal composites, semiconductors, and exotic dielectrics such as sapphire and diamond. Bulk metals are generally more expensive than sheet metals such as the copper or aluminum cladding used on PC boards, but they may be needed in some cases for heat sinking. Ceramics are frequently used in thinfilm circuits, in semiconductor packages, and in co-fired ceramic laminates. In fact, low-temperature co-fired ceramic (LTCC) technology is the primary contender with organic composite PC board technology and has advantages for some purposes. Table 4.1 compares the two technologies. LTCC can be favorable for some applications in which small size is important, but its cost per function is typically twice the cost of an implementation in PC board technology. Near the top of the cost range, semiconductor materials have potential applications in the form of microelectromechanical systems (MEMS). The high cost of MEMS, however, makes this technology a candidate only for very small parts and for parts with functions not achievable by other technologies. Table 4.1 Comparison between LTCC technology and PCB technology Technology

LTCC

PCB

Dominant panel size Maximum process temperature Hermetic? Need hydrogen getter? Relative module size Relative module cost

4 ×4 850–950◦ C Yes Yes for GaAs chips 1.0 ∼2

18 ×24 200–250◦ C No No 1.4 1

4.1.2.3 Achieving Scalability The “chicken and egg” syndrome applies to millimeter-wave technology as much as to most other emerging technologies. The move from low volume to high volume cannot be made in one jump. The manufacturing processes have to be proven before the large investments required for scaling up can be made with acceptable risk. The

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development follows more of a chicken-and-egg spiral as depicted in Fig. 4.2. To the extent possible the technology should be scalable from low volume to high volume. Each process can be proved out in the market at low volumes and then scaled to higher volumes. The alternative would be the case in which one has to jump to a different technology for high volume than that which is affordable at low volume, and such a jump may have to wait a long time because of the risk.

Fig. 4.2 The chicken-and-egg spiral. Development of high-volume manufacturing occurs most reliably when the same basic technology can be scaled up from low volume to high volume

4.1.3 Problems Specific to Millimeter-Wave Electronics There are a number of problems that materialize when frequencies reach the millimeter-wave range and wavelengths are comparable to the sizes of the smallest electrical components. The integration and packaging technology has to evolve to deal effectively with all of the problems. 4.1.3.1 The Problem of Distances At low frequencies the impedance at point A on a node is no different from the impedance at point B several inches away so long as there is a good conductor connecting the two points. At millimeter-wave frequencies a constant impedance is maintained over distances greater than a fraction of a wavelength only if the conductor is a transmission line impedance-matched at both ends. If there are mismatches, impedances change significantly over distances as small as a tenth of a wavelength, which ranges from 1 mm at 30 GHz with an air dielectric down to 0.1 mm at 95 GHz for microstrip on gallium arsenide (GaAs). For example, a bond wire connecting two MMICs (microwave monolithic integrated circuits) has a characteristic impedance as an air dielectric transmission

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line of roughly 180 . If, as is customary, each MMIC has an impedance of 50  at its pads, there is a large impedance mismatch between the bond wire “transmission line” and the MMIC termination at each end. A typical bond wire length of 0.44 mm (17 mils), which is an eighth of a wavelength in the upper E band, would transform the 50- impedance at one MMIC to a complex impedance at the point where the other MMIC is connected, and only about 68% of the power available from one MMIC would be transferred to the other MMIC, amounting to a loss of 1.7 dB. Matching networks can be used to overcome the mismatch caused by bond wires, but the matching is effective only over limited bandwidths. Figure 4.3 shows the profile of a typical minimum-length bond wire connection, a matching network

a

b

c

Fig. 4.3 Bond wire tuning example. (a) Profile of a bond wire interconnect of minimal manufacturable length with bond-to-bond distance D = 275 ± 55 μm, height H = 150 ± 75 μm, and conductive epoxy squeeze-up distance S = 50 ± 50 μm. (b) Plan view of a microstrip matching ciruit designed to compensate for the bond wire impedance discontinuity at 50 GHz. (c) Graph of the reflection coefficient in dB versus frequency for the tuned interconnection

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designed to compensate for the bond wire’s effects at 50 GHz, and a plot of reflection coefficient or return loss versus frequency for the combination. The 10-dB-returnloss bandwidth is only 24%. Moreover, the return loss at the design frequency is sensitive to changes in the bond wire parameters. Figure 4.4 shows how much the return loss at different design frequencies can be impacted by the variations in each of the bond wire profile parameters shown in Fig. 4.3a. In the worst case with all of the profile parameters at their extremes the return loss can be as low as 10 dB at 60 GHz.

Fig. 4.4 Return loss at the worst extreme in deviation from nominal of each bond wire interconnect parameter D, H, and S defined in Fig. 4.3a and in the worst-case combination of deviations of the three parameters. At each design frequency the bond-wire compensation network is adjusted to give infinite return loss at the nominal values of D, H, and S

Reflections due to mismatches can interfere constructively with each other. For example, if two impedance discontinuities with return losses of 10 dB produce reflections that are in phase, the return loss of the combination can be as low as 5 dB. Figure 4.5 plots the worst-case return losses that can result from two discontinuities whose reflections are in phase. Combinations of two or more discontinuities permeate the electronics in most cases. For instance, an MMIC may have a typical return loss of unspecified phase of 10 dB, and the interconnection (bond wire, flipchip, or otherwise) may have a return loss of 12 dB. The combined return loss can be as poor as 5.5 dB. When impedance discontinuities are separated by distances comparable to a wavelength or more, they give rise to ripple. Figure 4.6 shows the ripple in gain over frequency for two discontinuities each with 5 dB return loss and placed 1 cm apart at the ends of a transmission line with an effective dielectric constant of 4. The gain ripple is severe. This is what the ripple looks like when two packaged MMICs with input and output return losses degraded to 5 dB by bond wires and

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Fig. 4.5 Return loss resulting from the in-phase combination of reflections from two discontinuities, where RL1 and RL2 are the return losses of the individual discontinuities

package discontinuitites are cascaded with each other. Such ripple leads to problems in millimeter-wave systems such as a reduction in the maximum data rates and maximum ranges of wireless links. The minima in the ripples are spaced at a frequency interval of f, where f is the frequency at which the spacing between the discontinuities is one-half wavelength. The greater the spacing, the more gain slope is introduced within a frequency band. A third problem with distances is absorptive loss. Dielectric loss in dB per unit distance on a transmission line is proportional to frequency, and this loss can become significant (0.3 dB or more) at millimeter-wave frequencies if the dielectric loss tangent is greater than 0.01 for a distance of a wavelength or more or greater than 0.001 for a distance of 10 wavelengths or more. Often more important, though, is conductor loss. As wavelength decreases, the distance between signal and ground conductors must decrease proportionately to prevent coupling of power to modes other than the desired transmission mode. The widths of the conductors must decrease proportionately to maintain a practical characteristic impedance. Meanwhile, the skin-effect resistance of the conductors increases in proportion to the square root of frequency. The result is a loss in dB per unit length that increases as the 3/2 power of frequency. Attenuation of 0.2 to 1 dB/cm of length is common in the best of millimeter-wave systems. Choice of good conductors and low dielectric constants is imperative for minimizing conductive loss, and distances once again must be minimized. 4.1.3.2 The Problem with Encapsulants As mentioned above, dielectrics produce more loss at millimeter-wave frequencies than they do at lower frequencies. They also cause an increase in capacitance

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a

b

Fig. 4.6 Insertion gain degradation caused by reflections between two discontinuities with identical return loss. (a) Gain degradation in dB as a function of frequency for the case of discontinuities with 5 dB return loss each spaced 1 cm apart and connected with a transmission line with effective dielectric constant 4. (b) Maximum insertion loss (or peak-to-peak ripple in gain) versus return loss of the two discontinuities

between conductors in their vicinity. Since the admittance of a capacitor is proportional to frequency, any increase in capacitance is particularly disadvantageous at millimeter-wave frequencies. Encapsulation, which is the usual practice for low-cost plastic packaging, works fine at low frequencies, and it is being employed in MMIC packaging up to 30 GHz. Above 30 GHz, however, the detuning of the MMIC circuitry due to the added

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capacitances often requires special design of the MMICs to compensate for the encapsulation. Also, effective distances in wavelengths increase due to the capacitive effect of the encapsulant, exacerbating the problem of distance. The overall result in well-designed circuitry is ∼1 dB of gain loss per stage and ∼1 dB saturated power reduction–less at 30 GHz and more at 100 GHz. Encapsulation should be avoided at millimeter-wave frequencies if such can be done without a major cost increase or a decrease in reliability. 4.1.3.3 The Problem of Shielding Smaller wavelengths can leak through smaller holes. Any holes or feedthroughs in the shielding around a millimeter-wave circuit must be small enough to act as a waveguide below cutoff or to minimize evanescent fields. A maximum width dimension of under one-third of a wavelength (taking account of the dielectric constant of any material within the hole) is usually small enough for holes in the form of tunnels of length greater than a wavelength. For holes with little or no length the maximum width must be smaller still. Also, any structure comparable to a wavelength in size tends to become an antenna and radiates significant amounts of power that can be picked up by other parts of the system. Figure 4.7 illustrates a situation in which a conductive via in a circuit board acts as an antenna radiating power into the space between ground planes. This space acts like a waveguide filled with dielectric. Any other via acts as an antenna that can pick the signal up. Steps have to be taken to prevent this stray coupling.

Fig. 4.7 Cross-section of a circuit board illustrating the coupling between two well-separated circuits. The conductive via on the left, which carries DC or AC from the top conductor layer to the third conductive layer, may be excited by millimeter-wave signals on the top of the board. The via acts as an antenna or a waveguide probe, launching millimeter-wave power into the parallelplate waveguide between ground planes. Travelling with minor loss, even past occasional groundconnecting conductive vias, the millimeter-wave signal reaches another circuit via, which like a probe or antenna picks up the signal and carries it to supposedly isolated circuitry on top of the board

4.1.3.4 The Problem of Cavity Resonances Any enclosure with dimensions larger than a half-wavelength in each of two orthogonal directions has the potential for supporting resonant modes known as cavity modes. In a well-shielded enclosure, if there is nothing that is effective at absorbing RF power, the cavity modes can be high-Q resonances that couple one portion of

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a circuit to another over a narrow frequency range. The amount of gain that can be allowed in a millimeter-wave amplifier chain within the enclosure may be severely limited due to gain slope, “suck-outs,” or outright oscillations caused by the coupling. Handling more than 30 dB of gain in an amplifier or requiring better than 30 dB of isolation in a filter can be difficult. At lower frequencies it is common practice to keep cavity dimensions below a half-wavelength, to use mode bars to alter cavity resonance frequencies, or to use ferrite absorbing material to reduce the Q of the resonances. At millimeter-wave frequencies, however, these options are often not sufficient. Table 4.2 shows the half-wavelengths at 30 and 80 GHz in cavities loaded with three different dielectrics. The half-wavelengths are comparable to the size of an MMIC chip. It appears not to be practical to reduce cavity sizes to such small dimensions. Cavities are usually multiple half-wavelengths in size, and mode bars cannot be counted on to keep all resonant modes out of the pass band. Ferrite absorbers, which typically also have high dielectric constants (∼17), are less absorptive at millimeter-wave frequencies and are not sufficient for dampening cavity modes. Other solutions are necessary at millimeter-wave frequencies. Table 4.2 Half-wavelengths at millimeter-wave frequencies in three common dielectric media Dielectric

λ/2 @ 30 GHz (mm)

λ/2 @ 80 GHz (mm)

Air Epoxy Alumina

5.0 2.5 1.6

1.9 0.9 0.6

4.1.3.5 The Problem of Thermal Expansion Mismatch In low-cost semiconductor electronics there is always the need to make a transition between the world of semiconductors and the world of copper or aluminum. In the world of semiconductors the thermal expansion coefficient ranges from about 4 ppm/◦ C (for silicon) to about 6 ppm/◦ C (for gallium arsenide). In the world of copper and most PC board materials like FR4 the thermal expansion coefficient is about 16 ppm/◦ C, and for aluminum it is about 25 ppm/◦ C. Transitioning between the lowexpansion-coefficient world of semiconductors to the high-expansion-coefficient world of surface-mount circuit boards requires the imposition somewhere of an expansion joint–one that is capable of conducting heat with low thermal resistance. This transition is usually made with solder (as in ball-grid arrays or solder-attached flip chips), with conductive elastomers (such as z-axis conductive elastomers), or with conductive epoxies (such as those used for die attachment). As a rough rule of thumb the transition material has to have a thickness of at least 5 μm for each millimeter of maximum lateral extent in order to guarantee that the joint will not fracture due to thermal cycling over the lifetime of the product. If the transition is made over a large area, the transition material may be so thick and so variable in lateral extent that millimeter-wave connections to and from the semiconductor world

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would suffer in return loss or bandwidth. For example, if the transition is made between a 5-cm-by-5-cm LTCC package (which is thermally matched to the semiconductors) to a PC board with conductive epoxy, the conductive epoxy must be at least 0.25 mm thick and may squeeze out as much as a millimeter from the edge of the package. This situation makes it difficult to accomplish any kind of repeatable millimeter-wave connection between the LTCC package and the PC board. Moreover, transition materials like thermally-conductive epoxy are expensive, and the use of thick layers over wide areas adds significantly to the cost of the assembly. For these reasons in millimeter-wave electronics it is generally preferable to make the thermal expansion transition at the chip level rather than at the package level or higher. 4.1.3.6 The Problem of Environmental Control As mentioned in Section 4.1.3.2, it is desirable to avoid the use of encapsulants over millimeter-wave circuitry. The millimeter-wave circuitry should, therefore, be situated in an air cavity, and climate control within the cavity becomes important. Any moisture intrusion or condensation on unencapsulated semiconductor devices results in electrolytic corrosion and etching of metal traces and semiconductor materials leading to device failure. Also, moisture condensation on unencapsulated passive circuitry on PC boards, ceramic circuits, integrated passive devices (IPDs), etc., results in electrolytic metal migration or corrosion. In the case of indium phosphide (InP) and GaAs field effect transistors there is an additional problem due to what is known as “hydrogen poisoning” [1, 2]. A buildup of hydrogen beyond a concentration of a few parts per million within the cavity results in gradual drifts in the characteristics of these devices leading to potential failure over a period of years. Hydrogen is emitted from various materials within a package, including metals (especially plated metals) and organics, and its concentration builds up over time unless it can somehow leak out of the cavity or unless a hydrogen getter is included in the package. Hydrogen getters are expensive and costly to install.

4.2 A Chip-on-Board Solution The problems specific to millimeter-wave electronics demand a packaging and integration solution that is different from the low-cost solutions of lower-frequency electronics. Rather than packaging each semiconductor or passive circuit separately and interconnecting the packages by surface-mount technology, it is preferable, due to the problem of distances, to interconnect all of the RF chips in a subsystem as bare die within a single enclosure. Due to the problem of encapsulants it is preferable to make the single enclosure an air cavity. Due to the problem of shielding, the cavity should be surrounded by metal with only a few small holes to allow connections to pass through to the outside. Due to the problem of cavity effects, the shielding cavity should be equipped with means for dampening resonances or attenuating

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waveguide propagation. To cope with the problem of thermal expansion mismatch, each semiconductor or IPD chip should be attached with a shear-compliant medium to a copper-matched substrate. To economically address the problem of environmental control, the cavity should be non-hermetic and should be provided with means for preventing liquid intrusion while allowing hydrogen to exit the cavity. To achieve low cost and scalability the manufacturing process should allow the processing of multiple units on a single panel and should utilize the automation that has been developed for low-frequency electronics. Altogether, these requirements lead to a chip-on-board solution. Figure 4.8 gives a schematic overview of the process, and the sections that follow describe the process step-by-step.

4.2.1 The Surface-Mount Panel The assembled surface-mount panel is generally a multi-layer PC board panel of conventional technology. It can be a full-sized panel, such as the 18-inch by 24-inch

a

b

Fig. 4.8 Manufacturing steps for chip-on-board assembly of millimeter-wave subsystems. (a) Attachment of bare die to a multi-up preassembled surface-mount panel. (b) Wire bonding or ribbon bonding as necessary. (c) Lamination of cover. (d) Segregation of panel into individual units. (e) Electrical testing

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c

d

e

Fig. 4.8 (continued)

standard of the PC board industry, or it can be a smaller panel, but it should be large enough to have many units arrayed across its area. Figure 4.8 shows a panel with four units on it, but panels with larger numbers of units on them are desirable for achieving lower cost per unit. The number of conductor layers in the PC board should be at least four, but there should be only as many as necessary to provide one or more ground planes and to handle all of the interconnections required in a reasonable space. If the ground planes are required to conduct heat away from the integrated circuits, they may have to be thicker than the half-ounce standard. The dielectric layers will usually consist of FR4 material. However, if frequencies greater than one or two GHz must be routed on the PC board with low loss, the top core and prepreg layers may have to consist of a more expensive material with a dielectric loss tangent lower than that of FR4 material.

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Automatic routers are used in PC board manufacturing facilities to separate individual units from a panel. This equipment can be used to rout channels along unit boundaries to allow the edges of the units to be metalized. Portions of the edges (particularly at the corners of the units) are left unrouted so that the units continue to be held together on the panel as a web. Routing of metalized waveguide holes or structures for antennas is accomplished in the same step. Surface-mount parts such as regulators, bypass capacitors, phase-lock-loop (PLL) chips, connectors, etc., can be mounted on the top surface, the bottom surface, or both. Having parts mounted on the surface opposite the surface on which chip-on-board components will be placed can help to save space. The surface-mount assembly can be accomplished at low cost on highly-automated pick-and-place lines with in-line solder reflow and cleaning facilities.

4.2.2 Attaching the Bare Chips If the assembled surface-mount panels are sized properly, they can be put through the same kind of highly-automated assembly equipment that is used for plastic packaging on leadframes. The first step at this stage is to dispense conductive epoxy at all die attachment sites. The die are then picked from tape frames or containers and placed on the attachment sites. Afterwards, the panels are run through a curing oven to harden the epoxy. These steps can all be conducted on automated in-line assembly equipment of the type that can process up to 10,000 die per hour. In addition to attaching semiconductor die it may be necessary in the same step to attach bypass capacitors, ceramic circuits such as filters, and components such as waveguide launches that are made of ceramic, glass, or RF laminates. Existing in-line automated die attachment equipment can be configured to handle these components as well as the semiconductor chips.

4.2.3 Wire Bond Interconnects After die attachment and cure the panels can proceed in the same in-line automated system to an automatic ball bonding module capable of bonding up to 10 wires/s. Clusters of chips spaced as close as 0.006 inches (0.152 mm) apart can be wire bonded to make short RF connections between them. DC and low-frequency connections to traces on the circuit board can be made with wire bonds going directly from chips to the top metal on the board if the finish on the metal is suitable for wire bonding, or the wires from the chips can be bonded to plated metal tabs that, like the chips, are die attached to the board. Finishes suitable for gold wire bonding directly to the board include thick (> 1 μm) bondable soft gold, electroless nickel/immersion palladium/immersion gold (ENIPIG), and electroless nickel/electroless palladium/immersion gold (ENEPIG). The latter two are also suitable for surface-mount soldering, but the

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bondable soft gold is not. Thick gold tends to dissolve in the solder and form intermetallic phases upon solidification, and the intermetallics can cause the solder joints to fail under thermal cycling. Bondable soft gold, if used, has to be applied with a selective process so that it is deposited only where wires are to be bonded.

4.2.4 Eliminating Wire Bonds in the RF Path As was pointed out previously, wire bonds of even the shortest practical length can produce significant impedance discontinuities leading to lowered or varying insertion losses. Subsystems can be manufactured with wire bonding, providing distances are minimized, if some cost in insertion loss (typically 0.5–2.0 dB/interconnect) can be accepted. However, there are ways to improve upon or eliminate wire bonding. The simplest is to replace wire bonding with low-profile ribbon bonding. Automated equipment for ribbon bonding exists, but it is slower than ball bonding equipment. Ribbon bonding is less developed, and with ribbon bonding there is a need for rotation as well as translation of the bonding tool. However, in exchange for the extra cost the loss at each interconnect can be improved by ∼0.2–0.5 dB. More advanced approaches make use of flip-chip technology, which can reduce interconnect losses to under 0.1 dB. One such approach involves the flip attachment of semiconductor chips to passive integrated circuit substrates that are matched in thermal expansion coefficient to the chips. The passive substrate has all of the resistors, capacitors, inductors, and transmission lines that an MMIC has, but the material is much less expensive, since it utilizes none of the expensive semiconductor processes such as molecular beam epitaxy, electron beam lithography, or UV stepper lithography that are required for semiconductor devices. The passive substrate can integrate an entire RF subsystem, including in some cases the antenna or waveguide launch. As a result, there are no bond wires or ribbons in the RF path, and all connections to the passive integrated circuit are low-frequency or DC connections. An example of perhaps the most advanced technology of this type is the MLMSTM (MultiLithic MicroSystemTM , a trademark of Endwave Corporation) flipchip technology [3–5]. Depicted in Fig. 4.9, an MLMSTM substrate includes bumps

Fig. 4.9 Cross-sectional drawing of an MLMSTM flip-chip circuit. The pads on the flip chip are thermocompression bonded to gold bumps on the integrated passive substrate

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for thermocompression attachment of the flip chips plus low-inductance, highthermal-conductivity ground vias that double as heat sinks. The substrate dielectric, which has a thickness of 100 μm and a relative dielectric constant of about 4, sustains microstrip circuitry with low losses up to 100 GHz. Flip attachment of the semiconductor chips is achieved with automated pick-and-place equipment, and the completed MLMSTM subsystem can be epoxy attached to a PC board just like any other bare chip. Another flip-chip approach involves the flip attachment of chips directly to the PC board. The IBM C4 (Controlled Collapse Chip Connection) process is an example of a flip-chip process suitable for millimeter-wave interconnection. Solder balls are fabricated on the chip. When the chip is placed with the solder balls against the pads on the PC board and the assembly is heated, the solder reflows to make the electrical connections. The surface tension in the solder controls the height and position of the chip. There are a few drawbacks to the direct-flip-attachment approach. This type of attachment usually puts RF signals on the PC board, and the top layer of the board has to be a more expensive low-loss RF material. To ensure the mechanical reliability of the solder joints under thermal cycling, it is usually necessary to apply an underfill, and this dielectric influences the tuning and loss to some degree, as discussed in Section 4.1.3.2. Finally, solder ball connections are not highly thermally conductive, and, if the heat dissipation in a chip is high, a means must be provided for sinking heat out of the back of the chip. With direct flip attachment the process flow shown in Fig 4.8 has to be altered. The chip attachment may precede the surface mount assembly step if the solder balls have a high melting temperature, or the chip attachment may occur concurrently with the surface-mount assembly if the solder ball melting temperature is compatible with that of the surface-mount solder. If all bare chips are flip attached, the wire bonding step can be eliminated. Interestingly, in high-volume manufacturing all costs other than the cost of gold come down, and the cost of gold wire bonds or ribbon bonds becomes significant. Being able to eliminate gold wire bonding and ribbon bonding eliminates this gold cost. Other than using flip-chip technology, a move to aluminum or copper for wire or ribbon bonding may eliminate the cost of gold.

4.2.5 Cover Lamination Once the chip interconnections have been completed, the chip-on-board circuitry has to be protected against mechanical damage, electromagnetic interference, and the elements. The protection is accomplished with a cover that is laminated onto the PC board. The cover is itself a PC board that is metalized for shielding. It could also be made of metalized molded plastic. In either case the cover, like the PC board, can be applied as a webbed array covering an entire multi-unit PC board panel. The cost of the lamination operation is thus spread over many units.

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The adhesive for the lamination is usually a B-stage conductive epoxy applied to the cover panel prior to assembly. The metalized outer surface of the cover, the conductive adhesive, and the top metal ground plane on the PC board together form a Gaussian shield around the RF subcircuit. The only holes in this shield are (1) the conducting vias that carry DC and low-frequency signals between the RF subcircuit and the inner conductor layers of the PC board, (2) the waveguide holes or antenna holes that channel RF signals in and out of the cavity, (3) the unmetalized web joints, and (4) the breather holes for selectively permeable membranes. All of these types of “holes” are holes in the cladding or plated metal only, for the dielectric and membranes still completely seal the cavity to make it water-tight. The unmetalized web joints are the points typically located at the corners of the cover on each unit at which the covers for adjacent units in the panel array are joined to keep the panel together during processing and assembly. When these joints are cut through later to separate the units, the cut planes remain unmetalized. These unmetalized “holes” in the shielding can allow electromagnetic radiation into and out of the circuit cavity unless precautions are taken. One of these precautions would be to make the webs, and hence the “holes,” small enough to minimize electromagnetic leakage. Another would be to paint over the exposed dielectric at the unmetalized cut planes with conductive paint. There are also methods subject to patent protection in which waveguide-below-cutoff and artificial bandgap structures are employed. The so-called “breather hole” typically consists of a metalized via in either the cover or the PC board. Air can pass through this via, but a membrane is placed over the via to seal it off. The membrane is adhered to the metalized surface surrounding the via. The purpose of the membrane is to allow the selective passage of certain gases, such as hydrogen, out of the circuit cavity while preventing the ingress of water or other liquids. The conductive vias carrying DC and low-frequency signals into and out of the circuit cavity can be either blind vias or “thru” vias (vias that go through all layers of the board). If they are thru vias, they are either filled or blanked off to keep the circuit cavity leak-tight. The cover is the preferred home of another feature–the absorber. As explained in Section 4.1.3.4, it is frequently necessary to dampen resonances within the circuit cavity. Since magnetic materials such as ferrites are not sufficiently effective as absorbers at millimeter-wave frequencies, other lossy materials such as highdissipation-factor dielectrics and resistive materials are required. To be effective, these materials require a minimum amount of thickness approaching a quarter wavelength. Resistive foams covering the roof of a cavity can be effective. If the cover is made of a lossy dielectric material like FR4, just leaving the cavity unmetalized on the inside can help to dampen resonances. There are also a couple of highlyeffective absorption techniques involving inexpensive thin resistive layers that are subject to patents by QinetiQ Ltd and by Endwave Corporation. With proper design a wide-band amplification gain of greater than 45 dB over the length of two MMICs can be sustained stably within a single circuit cavity.

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4.2.6 Segregation Once the cover has been applied the units are well protected against moisture, dust, and mechanical damage, but they are still connected together in a panel array and have to be separated. There are several ways in which this separation can be achieved. For instance, the common methods for segregating individual boards from a PC board panel can be applied. The most standard procedure is to rout out gaps between the units with an automatic router. A less expensive procedure is to simply snap the units apart, assuming that the connections between them are either tenuous enough already or have been weakened by drill perforation or scoring. Some manufacturers have been introducing automated sawing techniques that produce a kerf much narrower than the cuts produced by routers but which require that the cuts be along straight lines. Less common methods of cutting are also being introduced, including water-jet cutting and laser cutting, both of which can produce narrow kerfs with arbitrary shapes.

4.2.7 Testing Final testing of the units can take place either before or after segregation. Fig. 4.8e depicts a rather unsophisticated method of testing individual units after segregation. Having to fixture each unit and apply power through a hand-inserted connector is relatively expensive in terms of labor. For volume production a more suitable means of testing is the use of an automated handler to press units one at a time against a test socket for testing. With proper module design the same techniques and equipment can be used for this procedure as are used in the plastic packaging industry for high-speed testing of packaged semiconductor chips. Unlike the testing of packaged semiconductor devices, though, the testing of the millimeter-wave modules requires the use either of waveguide openings in the test socket or of antennas hovering over the socket to inject and receive millimeter-wave signals. In some cases it may be preferable to test the units while they are still in panel form before they are segregated from the array. Automatic positioning equipment can be utilized to place each unit in the panel in relation to a set of spring-loaded probes, pogo pins, or other contacts for making the necessary DC and low-frequency connections and a set of antennas or waveguide openings for injecting or receiving the millimeter-wave signals. Alternatively, spring contacts and/or millimeter-wave electromagnetic couplings can be made simultaneously to all units on the panel to enable testing with higher throughput.

4.3 Application Examples At the time of this writing the application of these low-cost mass production techniques to millimeter-wave electronics is just beginning. In early 2009 the highest

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manufacturing volume for a millimeter-wave product is in the tens to hundreds of thousands of units per year, and low-volume manufacturing techniques are still being applied. There are, nevertheless, some examples of products and price points that show what can be achieved.

4.3.1 A 60-GHz Transceiver Perhaps the first product on the market to be manufactured with the techniques described is the EW600-series 60-GHz transceiver developed by Endwave Corporation. The transceiver, shown in Fig. 4.10, is the size of a name card. It includes separate synthesized sources for the receiver and the transmitter that produce local oscillator signals with phase noise equal to that of the best carrier-class telecommunications backhaul transceivers on the market. The transceiver employs a GaAs MMIC chipset to achieve a noise figure under 6 dB, a linear output power of 13 dBm and a saturated output power of 15 dBm.

Fig. 4.10 A 60-GHz transceiver with built-in antennas and two synthesized sources

The transceiver is based on a 6-layer PC board made entirely of FR4. All of the surface-mount components are attached to this board. Also attached to the PC board are the chip-on-board components. These components occupy an area of about

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75 mm2 for the receiver and 90 mm2 for the transmitter, both small fractions of the overall 3600-square-millimeter area of the card. The chip-on-board components are interconnected with gold ribbon bonds. In the version shown in the figure the cover has two antennas built in. To handle the millimeter-wave signals to and from the antennas the cover is manufactured as a four-layer PC board made of a laminate material with low dielectric loss at millimeter-wave frequencies. Another version of the transceiver does not have builtin antennas but instead has waveguide ports on the PC board side. It utilizes a cover made entirely of low-cost two-layer FR4 material. In both versions the cover incorporates resistive absorbers and provides complete shielding. The transceiver dissipates up to 5 W of power. Heat is removed by conduction through the copper ground planes in the PC board carrying heat from the semiconductor devices to the mounting holes at the two ends of the board. In the version with waveguide ports the heat can be sunk either through waveguide flanges to which the unit is attached or through the mounting holes at the ends of the board. Estimates have been given of the pricing (including profit margin) of this transceiver at an annual volume of one million units per year. The component of the price attributable to the packaging, but not including the semiconductor chips, the surface-mount components, and the connectors, is $10 U. S. per transceiver for the version with waveguide ports and $30 U. S. for the version with built-in antennas. The price including all components is estimated to be under $300 U. S. per unit.

4.3.2 Miniaturized 60-GHz Transmitter and Receiver Modules Cost estimates have been made for high-volume production of 60-GHz transmitter and receiver modules manufactured with chip-on-board laminate technology. Each module, measuring 20 mm by 15 mm by 5 mm, includes two 10-dB-gain antennas, two or three coaxial connectors, and surface-mount circuitry for bias stabilization and for protection against electrical overstress on all inputs and outputs. The DC and switching voltages are diplexed onto the coaxial cable conductors along with the reference oscillator signal and the I and Q quadrature baseband input/output signals. A single silicon chip in each module integrates the millimeter-wave amplifiers, the mixer, the switches, the local oscillator and the PLL circuitry. In volumes of 5 million modules per year the price (including profit margin) for each module excluding the silicon millimeter-wave chip comes to $5 U. S. per module.

4.3.3 76-GHz Automotive Radar Module Package Size is an important factor in the determination of packaging cost, since materials and labor costs are reduced when the number of units per panel is increased. However, there are situations in which the size of a unit is necessarily large. A long-range 76-GHz automotive radar sensor with a built-in phased-array antenna is

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an example. A certain amount of antenna area is necessary, by the laws of physics, to produce the narrow beamwidth required to achieve the desired range and resolution. In this case the packaging technology must achieve low cost not through miniaturization but by virtue of its use of inexpensive materials. For example, the cost of co-fired ceramic technology relative to laminate technology increases from about 2:1 to about 3:1 when the potential miniaturization advantage of co-fired ceramic is not applicable. An estimate of the packaging component of the price (including profit margin) of a 76-GHz radar module manufactured with flip-chip-on-board technology comes to about $20 U. S. per unit at an annual volume of one million units. The size of such a unit is about 95 mm by 80 mm by 11 mm, and the packaging includes the antenna array and some bulk metal that is required for heat sinking and mechanical stability. There appears to be no other technology currently available that can achieve such a low cost.

4.4 Summary The special requirements of millimeter-wave electronics demand a packaging approach that is different from the approaches used for lower-frequency electronics. The problem of distances, the problem with encapsulants, and the high cost of gain compel the use of bare chips in air cavities. The combination of highlyautomated laminate PC board technology with the high-speed die attachment and wire-bonding technologies of the plastic packaging industry leads to a low-cost solution for millimeter-wave packaging. The highly-automated massively parallel processing of which this technology is capable allows it to be scaled to high volumes at which the packaging costs are estimated to be lower than those of other technologies to date.

References 1. Blanchard R, del Alamo J (2006) Stress-related hydrogen degradation of 0.1-μm InP HEMTs and GaAs PHEMTs. IEEE Trans Electron Devices, vol. 53, pp. 1289–1293 2. Chao P, DeOrio W et al. (1997) Ti-gate metal induced PHEMT degradation in hydrogen. IEEE Electron Device Letters, vol. 18, pp. 441–443 3. Stoneham E (2006) High-precision flip-chip process yields e-band harmonic mixers with potential sub-10-dB conversion loss. Proceedings of the 36th European Microwave Conference Manchester UK:506–509 4. Stoneham E (2006) A high-performance 34 to 40 GHz frequency quadrupler fabricated with flip-chip technology. Proceedings of the 36th European Microwave Conference Manchester UK:1618–1620 5. Zeeb D (2006) A high-performance 14.4 to 19.7 GHz power detector fabricated with flipchip technology. Proceedings of the 36th European Microwave Conference Manchester UK: 1621–1624

Chapter 5

Liquid Crystal Polymer for RF and Millimeter-Wave Multi-Layer Hermetic Packages and Modules Mark P. McGrath, Kunia Aihara, Morgan J. Chen, Cheng Chen, and Anh-Vu Pham

Abstract In this chapter, we present the design and development of thin-film liquid crystal polymer (LCP) surface mount packages for X, K, and Ka-band applications. The packages are constructed using multi-layer LCP films and are surface mounted on a printed circuit board (PCB). Packages include a typical low pass feedthrough design, as well as a new bandpass feedthrough design. Our experimental results demonstrate that the low pass package feedthrough transition including a PCB launch and bond wires achieve a return loss of better than 20 dB and an insertion loss of less than 0.4 dB around Ka-band. We achieve more than 45 dB measured port-to-port isolation of the package across Ka-band. The leak rate of LCP cavities has been found to be 3.6×10–8 atm-cc/s. Experiments show exceptional reliability results for several reliability tests including temperature cycling and prolonged exposure to humidity of packaged amplifiers. Finally, we demonstrate that our bandpass package feedthrough transition including bond wires achieve a 13 dB or higher return loss and less than 0.5 dB insertion loss across K-band. The package transition offers 0.2 dB insertion loss and > 15 dB return loss across X-band, and operates well across 8–27 GHz.

5.1 Introduction Packaging is becoming increasingly important as higher performance and reliability are sought in conjunction with reducing cost and weight of components. Moisture, air contaminants, and chemical processes caused by the packaging material itself can seriously degrade the lifetime of components. In general, moisture readily promotes corrosion and cracking effects. In cavity packages, excellent sealing against moisture is critical for maintaining moisture sensitivity levels (MSL) that prevent popcorning during component solder reflow processes. MEMS devices, such as M.P. McGrath (B) Microwave Microsystems Laboratory, University of California , Davis, CA 95616, USA e-mail: [email protected]

K. Kuang et al. (eds.), RF and Microwave Microelectronics Packaging, C Springer Science+Business Media, LLC 2010 DOI 10.1007/978-1-4419-0984-8_5, 

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switches, incorporate micrometer sized moving parts, which are extremely sensitive to any contamination that increases static friction, or stiction. Temperature sensors and satellite systems require long lifetime, and, thus, require hermetic packaging. Gas permeation effects of packaging materials, sealants and vias is becoming ever more important as one also seeks to satisfy cost, weight and size requirements for high performance electronics. The objective of this chapter is to illustrate the need for a light weight, hermetic, and low cost packaging platform and to illustrate how LCP meets this need. Emerging microwave and millimeter wave applications require effective and low-cost approaches to high-frequency electronic packaging to fulfill industry demands. Organic surface mount packages are becoming an attractive solution for millimeter-wave frequency applications [1–5]. Highly automated assembly processes for surface mount packages offer low cost production [6]. Millimeter wave organic surface mount packages reported to date are non-hermetic [1–3]. The quest for hermetic organic surface mount packages has led to the investigation of LCP for packaging [4, 5, 7–10]. LCP has permeation close to glass and can be used to construct potentially hermetic cavities. Researchers have presented surface mount packages using thin-film LCP at millimeter wave frequencies [4, 5]. However, the characteristics of a complete package feedthrough transition, lid sealing techniques and hermeticity have not been reported. One LCP packaging platform is quad flat no-lead (QFN) packages molded with LCP alloy [11, 12]. LCP QFN packages are formed by injection molding LCP alloy around a conventional lead frame [11, 12]. However, these packages do not have well-matched, low loss transitions required for millimeter wave frequencies due to large lead frame feature sizes, poor tolerance, and limited design flexibility. Another drawback of this LCP QFN package is the use of epoxy to seal a lid [11]. The epoxy forms a path for moisture to penetrate into the package. Ultrasonic and laser welding techniques can be a possible solution for hermetic sealing [13]. In ultrasonic welding, a lid interface to the base must be narrow to accumulate enough ultrasonic energy to melt LCP. Laser welding is challenging on LCP due to low IR transmission rates of 1–2% [14]. Molding small feature sizes on LCP present challenges, and the barrier can be insufficient for protection against moisture. In this chapter, we present the design and development of surface mount hermetic packages to include a lowpass feedthrough, sealing processes, hermetic evaluation, reliability testing, and a new bandpass feedthrough. We report a new package feedthrough that incorporates pad capacitance to compensate for bond wire inductance and a PCB launch transition (Fig. 5.3). The newly designed feedthrough provides a matched transition from PCB launch pads through a grounded CPW below the package, a vertical via to bond wires. We demonstrate that the package feedthrough transition, which includes a PCB signal launch and bond wires, achieve a measured return loss of better than 20 dB and an insertion loss of less than 0.4 dB around Ka-band. In addition, we have developed a process to seal a package cavity in an LCP enclosure without using any adhesive material, and demonstrated a packaged amplifier that has negligible degradation at Ka-band. Hermetic evaluation of LCP cavities have shown measured fine leak rates of ∼1.3×10–8 atm-cc/s,

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which is less than the 5×10–8 atm-cc/s specification required by the MIL-STD-883 Method 1014 [15]. Rather than using the term quasi-hermetic, we refer hermeticity as passing a fine leak rate of less than 5×10–8 atm-cc/s. Humidity exposure, thermal shock, mechanical shock, and thermal stress testing have been performed for the lowpass coupled packages. The design and results of the new bandpass feedthrough including PCB launch and bondwires will also be discussed. Section 5.2 elaborates on design and fabrication processes of thin-film LCP packages. Performance sensitivity to physical variation of copper trace and solder thickness is investigated. Section 5.3 introduces LCP lid construction and lamination of a lid onto a package base. Section 5.4 presents RF performance of the lowpass package feedthroughs. Section 5.5 presents hermetic characterization on surface mount packages fully formed with LCP. Section 5.6 presents results of various reliability tests. Finally, Section 5.7 presents design and results of bandpass feed-throughs.

5.2 Design and Fabrication of the Thin-Film LCP Package Figures 5.1 and 5.2 demonstrate thin-film LCP packages developed at the University of California, Davis [16, 17]. Electrical signals enter the package through underside metal traces and traverse up through a plated via to the top of the package base (Figs. 5.1 and 5.2). A cavity is formed by laser ablating through LCP and the cavity bottom consists of package base backside copper. MMICs are mounted directly on the copper base inside the cavity for thermal dissipation. Die attachment and wire bonding will be followed by a lid lamination that hermetically seals the cavity. We have designed a vertical feedthrough transition for thin-film LCP surface mount packages using full-wave finite element method analysis (Ansoft High Frequency Structure Simulator, HFSS [18]), and quasi-static approaches (Ansoft

Fig. 5.1 Diagram of the top side of the multi-layer thin-film LCP package

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Fig. 5.2 Diagram of the bottom side of the multi-layer thin-film LCP package

Fig. 5.3 Ka-band thin-film LCP package feedthrough transition design structures on HFSS

Q3D Parasitic Extractor). We used a 254 μm (10 mils) thick LCP multi-layer substrate and a 254 μm (10 mils) diameter via process are used for mechanical drilling compatibility. The dielectric constant and loss tangent of the LCP films are 2.9 and 0.0025, respectively. Figure 5.3 shows a package feedthrough transition model in HFSS. Once the initial design is optimized, we started investigating the electrical performance sensitivity to package ground copper and solder thicknesses. Figure 5.4 illustrates copper and solder thickness parameters. Figure 5.5 shows the electrical sensitivity of the package feedthrough to the total thickness of ground copper and solder. The total ground copper thickness varies from 64, 83, 98 to 118 μm while

Fig. 5.4 Cross section of the package showing the package ground copper and solder thicknesses

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Fig. 5.5 S-parameters of the package feedthrough with varied metal thickness at package and PCB interface

the solder layer is 30 μm thick in simulations. As can be seen, the thickness of the ground metal does not have dramatic effects on the insertion loss electrical performance. For mechanical support, the copper ground thickness can be chosen up to 72 μm. Figure 5.6 shows simulated electrical performance of the feedthrough with changes in bond wire length. While the bond wire length varies from 180 to 380 μm, insertion and return losses are maintained to within 0.03 and 18 dB, respectively. Package bases were fabricated on multi-layer LCP films using a printed circuit board process. Five layers of LCP films with thickness of 25.4 μm (1 mil), 50.8 μm (2 mils), 101.6 μm (4 mils), 50.8 and 25.4 μm were laminated to produce a 254 μm (10 mils) thick substrate. First, a high temperature (315◦ C) LCP film is sandwiched between two outer lower temperature (280◦ C) LCP layers, and the 3-layer structure is laminated. Two additional high temperature LCP films are laminated above and below this 3-layer structure to form a 5-layer board. The bottom ground is 36 μm thick to provide mechanical support. Top metal traces are 9 μm thick. Once the multi-layer LCP package base was fabricated, laser ablation was used to create a cavity [19], as can be seen in Figs. 5.1 and 5.7. In production, LCP films can be made with holes using low cost machining or punching techniques (Nippon Steel Chemicals, “private communication”).

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Fig. 5.6 Simulated S-parameters of the package feedthrough with varied bond wire length

Fig. 5.7 Thin-film LCP surface mount package mounted on a printed circuit board

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5.3 Lid Construction and Lamination We have developed a process to laminate a LCP lid directly onto a package base without adhesive materials. Since LCP adheres to itself, MMICs will be enclosed in a moisture-resistant cavity. A lid can be formed by multi-layer lamination and molding. The multi-layer laminated lid consists of 20 layers of 101.6 μm (4mil) thick LCP. The molded lid is a molded 2 mm (80 mil) thick structure. A milling machine drills a cavity into the lid. Figure 5.8 demonstrates the prototypes of a molded lid used in this paper. We used molded lid because of its low cost and repeatability in manufacturing, and uniformity of lid to package interface surface and cavity.

Fig. 5.8 (a) Top view and (b) bottom view of the all LCP lid

Figure 5.9 shows the schematic diagram of the lamination process. Lids and outer layers of package base are composed with high melting temperature LCP (315– 350◦ C). A low melting temperature LCP film (260◦ C) is used at the interface of the package lid and substrate. A metal tube applies heat and pressure only to the edges of the lid. The temperature applied at the interface layer is roughly 280◦ C for thirty minutes. The lid edges are locally heated to a melting temperature of ∼260◦ C for making adhesion and sealing. Thermal simulations using Ansoft ePhysics (Fig. 5.10) show that the temperature is less than 160◦ C inside the package and maintains the integrity of solder and interconnect structures.

Fig. 5.9 Cross section of the LCP lid lamination process onto the package base

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Fig. 5.10 Cross section of the lid at the edge and temperature distribution of simulated lamination

5.4 Results and Model of Lowpass Feedthrough LCP surface mount packages were mounted onto a 508 μm (20 mils) thick Rogers RO4350B printed circuit board using solder. In order to characterize a package feedthrough, a 50  coplanar waveguide to microstrip adapter [20, 21] is mounted in the cavity, approximately 200 μm from the LCP cavity wall, to provide connection from 3 bond wires to a micro-probe. The adapter is a 50  line fabricated on 127 μm (5 mils) thick alumina substrate (εr = 9.6) with a ground-signal-ground probe pattern at one end [20]. The adapter and cavity wall are intentionally spaced 200 μm apart for bond wires to match our design length. This construction will establish a complete package transition from bond wires through a vertical via to a printed circuit board. The input of the package was probed directly on the printed circuit board. The package feedthrough transition was measured using a Cascade Microtech probe station, Agilent’s Performance Network Analyzer 8364B (PNA) and 150 μm pitch coplanar waveguide probes. The network analyzer was calibrated using a Line-Reflect-Line technique up to 50 GHz. Measurement of the feedthrough includes a small grounded CPW signal launch on PCB, a solder joint between the PCB pad and package, a vertical via transition, a short microstrip line with pad extension on package substrate, three bond wires and a ceramic adapter (Fig. 5.7). A comparison of simulated, measured and lumped-modeled results of the LCP thin-film package feedthrough transition is provided in Fig. 5.11. The thickness of the copper ground and solder used in HFSS simulation is 30 μm and 36 μm, respectively. We optimized the feedthrough design for Ka-band operation but include measurements from 0 to 40 GHz for completeness. We have achieved a measured return loss of better than 20 dB and a measured insertion loss of 0.4 dB around

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Fig. 5.11 Measured, design and modeled feedthrough data

Ka-band. HFSS simulation predicted lower insertion loss and better return loss than measurement at the lower half of the Ka-band. This is due to uneven solder thickness used to mount a package to PCB. Recall from the HFSS simulation in Fig. 5.6 that thicker solder degrades electrical performance at Ka-band. In addition, the length of bond wires was not exactly the same as that used in the simulation. Bond wire compensation pads were designed to compensate a specific length of bond wire inductance. Hence, the variation of wire length can cause some mismatches. Overall, experimental results demonstrate that a well-matched package feedthrough can be designed to enable surface mount packages for millimeter wave frequencies. Figure 5.12 shows an equivalent circuit model of a package feedthrough transition with corresponding values shown in Table 5.1. Initially, a simple lumped

Fig. 5.12 Lumped circuit model of package feedthrough transition

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Value

Element

Value

L1 R 1 ,R 2 ,R 3 C1 L2 C2

0.26 nH 0.008  0.0653 pF 0.172 nH 0.115 pF

L3 C3 C4 C5 –

0.059 nH 0.078 pF 0.007 pF 0.049 pF –

element model is generated using Q3D Extractor. Then, the circuit is modified using Advanced Design System (ADS) [22] software to correlate the modeled S-parameters to measurement. Resistors R1 and R3 in Fig. 5.11 represent the microstrip line conductor losses on top and at the bottom of the package base. L1 and L3 model the inductance of the microstrip lines. C1 and C4 are capacitances between the microstrip lines and grounds. R2 and L2 model the conductor loss and inductance of the via, respectively. C2 and C3 represent capacitances of via pads. The circuit also includes a PCB launch, bond wires and a CPW to microstrip adapter, all modeled using ADS built-in components. The modeled and measured S-parameters are well correlated. To investigate isolation, a package was constructed without and amplifier, where each package feedthrough is terminated with a 50  SMT resistor (Fig. 5.13). The measurement is taken using the same package cavity dimensions as the one that

Fig. 5.13 Demonstration of 50  terminated feedthrough for isolation measurement

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will be used to package an amplifier in the next section. Micro-probes are placed at RF input and RF output on the printed circuit board to measure isolation. The experimental result shows that isolation is better than 45 dB for 2 ports separated by 2 mm.

5.5 Hermeticity and Leak Rate Measurement LCP package parts have been subjected to gross and fine leak testing performed by Six Sigma Services [23]. The package cavity volume under test is ∼0.3 cm3 . Leak tests are performed on three LCP package parts using Mil-Std-883, Method 1014 [24]. Gross leak testing first involves a517.1 newton/m2 (75 PSIA) perfluorocarbon fluid bomb for 125 min. Parts are then submerged into a second perfluorocarbon bath, heated to above boiling of the first perfluorocarbon fluid, and inspected for bubbles. Fine leak testing requires the same 517.1 newton/m2 helium bomb for 125 min. A mass spectrometer is then used to measure helium leaking from a cavity to determine leak rates. Equipment is calibrated daily to be accurate to 2×10–8 atm-cc/s helium. Since LCP is a thermal plastic material, surface absorption occurs. In other words, during helium bomb, helium will be absorbed onto the surface of the LCP packages. When a mass spectrometer measures the helium leaking from a cavity, it also includes any adsorbed helium coming off the package surface. This increases the fine leak rate reading since more helium is measured by the mass spectrometer. In order to evaluate artificially high leak rates, a solid LCP block is also tested as a control. The solid block is intended to identify a virtual leak rate of helium desorbing from the surface of LCP. Leak rate results are shown below in Table 5.2. The results of the LCP packages are compared against the solid LCP block, which does not have a cavity that can be affected by leaks. A further comparison is made between leak rates conducted immediately and after a 3 h dwell. Dwell time is the period defined between the end of helium bomb and the beginning of mass spectrometer measurements. The gross leak results indicate that the packages are free from large leaks. For a dwell time of a few minutes, the cavity LCP packages are found to have average fine leak rates of 3.07 ± 0.2×10–7 atm-cc/s helium. For comparison, the solid LCP block is found to have 3.2 ± 0.2×10–7 atm-cc/s helium. The results indicate that the fine leak rates of 3.07 ± 0.2×10–7 atm-cc/s and 3.2 ± 0.2×10–7 are measured from the helium desorbing from the LCP surface rather than from helium leaking from the cavity. The measured difference between solid and cavity block leak rates is 1.3 ± 0.4×10–8 atm-cc/s, which reflects the portion of leak rate coming from the cavity. In fact, the virtual leak rate of the solid block reaches an acceptable leak rate after a 3 h dwell time as shown in Table 5.2. At this time, all the cavity packages surpass the mil-std requirements. Optical leak rate testing has also been performed to substantiate these claims. Optical leak tests are performed through measuring lid deflections under dynamically applied pressure. Hence, this optical fine leak rate analysis does not encounter

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the solubility or the surface absorption issue. Through optical leak rate testing, leak rates have been measured to better than 3.6×10–8 atm-cc/s, the mil-std requirements. Table 5.2 Leak rate test results after immediate removeal from bombing and after several hour dwell Part #

Measured immediate leak rate (atm cc/s helium)

Measured leak rate after 3 h dwell (atm cc/s helium)

Gross leak (P or F)

Solid block Package 1 Package 2 Package 3

3.2×10–7 3×10–7 3×10–7 3.2×10–7

5.0×10–8 3.6×10–8 3.6×10–8 4.0×10–8

P P P P

5.6 Reliability of LCP Surface Mount Packages In addition to electrical design, measurement and modeling of LCP package feedthroughs, dependability of package protection from external environment must also be evaluated. This section investigates the long-term reliability of LCP surface mount packages by exposing them to various environmental tests following JEDEC [25], military standard 883F [24] and other industry standards [26], and shows outcome of each test that was carried out. These tests were designed to accelerate different types of real life environmental conditions that include temperature, humidity and pressure/force. The test results can be used to predict a package’s long term reliability in a relatively short amount of time compared to an actual life time of a package. The assembled packages are surface mounted onto a PC board and connectorized. A test board used for single packages before and after is assembled is shown in Fig. 5.14. Hittite’s HMC564 [27] amplifier is used for the single chip package.

Fig. 5.14 Reliability test board for single chip package

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The bias circuit requires two 100 pF capacitors, installed inside a package cavity and a 0.1 μF capacitor mounted on a test board. Frequency of operation is in C and X bands. End launch SMA connectors are mounted onto package test boards. Silver loaded epoxy was used to mount all components for high temperature curing. Each reliability test requires a pre and post test data measurement for comparison. The amplifier gain was measured before and after each test from 6 to 10 GHz and gain difference was evaluated. TRL calibration [20] was used to calibrate out the RF cable that connects the PNA to the test board.

5.6.1 Non-operating Temperature Step Stressing Temperature difference between day and night varies greatly as distance increases from the coast to inland of a continent. At such location, a package may have to endure severe daily cycle of temperature from cold to hot to cold. In order to predict long term reliability in this environment, a non-operating temperature step stressing test, or temperature cycle test, is carried out. Temperature cycle test determines the ability of packages to resist extremely low and extremely high temperatures, as well as their ability to withstand cyclical exposures to these temperature extremes. The test consists of subjecting the packages to a specified low temperature, then subjecting the same units to a specified high temperature for 100 cycles. The test was carried out following the military standard 883F method 2010.8 test condition C [24]. The test involves placing the part in a temperature chamber, reducing the temperature to –65◦ C, keeping the part at that temperature for 10 min, increasing the temperature to 150◦ C with in 5 min, keeping the part at that temperature for 10 min, and repeating the process 99 times. The parts were then tested for performance degradation. Figure 5.15 shows the difference in gain measured before and after non-operating temperature step stressing test. As can be seen, all five tested parts have measured gain less than 1 dB of drop after test compared to initial data and passed the test.

5.6.2 Non-operating Thermal Shock Testing Non-operating thermal shock test is performed to evaluate the resistance of a package to sudden changes in temperature (greater than 400◦ C/min). The test parts undergo a specified number of cycles, which start at ambient temperature. The parts are then exposed to an extremely low temperature and within a short period of time, exposed to an extremely high temperature, before going back to an extremely low temperature again. Non-operating thermal shock involves submersing the parts in liquid nitrogen for a minute, then immediately transferring the part to a 300◦ C and kept there for a minute. The part is then immediately submersed in liquid nitrogen and the steps are repeated five times. The part is then evaluated for performance degradation. Figure 5.16 shows the difference in gain measured before and after

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Fig. 5.15 Non-operating temperature step stressing test results

Fig. 5.16 Non-operating thermal shock test results

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non-operating thermal shock test. Five parts were tested. As can be seen, all tested parts have measured gain drop of less than 1 dB after test compared to initial data, and passed.

5.6.3 Operating Humidity Exposure Testing In reliability testing, one of the most severe conditions is known to be the operating humidity exposure test, where test samples go through an environment with 85◦ C and 85% relative humidity for more than 1000 h, while packaged components are biased. The condition accelerates metal corrosion and dendrite formation on chip metal when moisture enters package cavity. Performance degrades when chip metal corrodes or dendrites forms and short circuits a packaged chip. Operating humidity exposure test involves applying bias to the parts and setting the environment to 85◦ C and 85% relative humidity. The current of parts is monitored continuously while the parts are measured on the 24th, 96th, and 500th hour to ensure that parts are still functioning. The parts are then evaluated at the 1000th hour for performance degradation. Figure 5.17 shows the difference in gain measured from test units before and after operating humidity exposure test for the single chip packages. Five parts were tested. As can be seen, all parts have measured gain drop of less than 1 dB after test compared to initial data.

Fig. 5.17 Operating humidity exposure test results

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5.6.4 Reliability Testing Summary In addition to the test shown above, several other tests were also performed in analyzing the reliability of the packages including: Non-operating high temperature storage following the military standard 883F method 1008.2 test condition F, non-operating moisture resistance following military standard 883F method 1004.7, and non-operating mechanical shock follows Mil-Std-883F Method 2002.4 Test Condition C and Mil-Std-883F Method 2011.7 Test Condition F [24]. The results of all of these tests for single package amplifiers are shown in Table 5.3. Table 5.3 Reliability test summary Test type

Results

Operating humidity exposure Non-operating temperature step stressing Non-operating high-temperature storage Non-operating moisture resistance Non-operating thermal shock Non-operating mechanical shock

5/5 Passed 5/5 Passed 5/5 Passed 5/5 Passed 5/5 Passed 5/5 Passed

5.7 Bandpass Feedthrough As a further improvement on the reliability of the packages, we have also developed bandpass feedthroughs to eliminate the need for vias to couple the RF signal out of the package [28]. This structure offers several advantages over the typical low pass feedthrough including: improving the hermeticity of the package, removing sources or virtual leaks, easier fabrication, and eliminating the need for DC blocking capacitors on the MMIC that was developed as a compromise between the Low Pass and Bandpass Feedthroughs. Many of the advantages are retained.

5.7.1 Bandpass Feedthrough Design and Fabrication Figure 5.18 demonstrates the diagram of the LCP band-pass feedthrough package. Electrical signals enter the package through the bottom metal trace and continue to the bottom trace of the broadside coupler through a plated via. The signal is then coupled to the top trace of the broadside coupler to bond wires. Laser ablation is used to drill a cavity to the backside copper of the package. MMICs are mounted directly on the copper base or copper-molybdenum for thermal dissipation. The die attachment and wire bonding are followed by lid lamination to hermetically seal the cavity. The band-pass feedthrough was designed for a package with a 304.8 μm (12 mil) multilayer LCP substrate. A 25.4 μm (1 mil) thick LCP is used to provide

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Fig. 5.18 Schematic diagram of a bandpass feedthrough surface mount package

tight coupling via a quarter wave broadside coupled line. The bottom trace of the broadside coupler is connected to a printed circuit board using a via. The broadside coupled lines are first designed as an ideal component in ADS. The even and odd mode impedances are chosen for the required bandwidths and in band return loss. LINPAR [29] software is then used to determine the even and odd mode impedances of the asymmetric section. The K-band design (18–27 GHz) was initially designed using a straight coupled line section as shown in Fig. 5.19. The total length of the feedthrough is 3 mm.

Fig. 5.19 (a) 3D image of the surface mount package and (b) close up of band one structure, including coupled lines, 6-mil via, and coplanar-to-microstrip transition

We used three parallel wires in simulation to reduce the inductance of the bond wires. In addition, the bond pad at the edge of top metal trace of the broadside coupled line extends to compensate the residual parasitic inductance. The length of extension is designed so that the total capacitance of the pad and the bond wire inductance form a 50  transition. The whole band-pass feedthrough from PCB probe launch to bond wires is optimized using HFSS. The bond wire pad is bent at the edge to reduce usage area, as well as reducing coupling to adjacent feedthroughs in a larger package with more than one RF input on each side of the package.

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The broadside coupling structure was designed using a straight coupled line section and adjusting the even and odd mode impedances for the desired bandwidth and return loss. We designed the top and bottom metal traces to be 405 μm wide. The broadside coupled lines are separated by a 25.4-μm thick layer of LCP and are 2.4 mm long. The even and odd mode impedances of the structure are determined by both the width of the lines, the distance between the two coupled lines, and the substrate thickness. The case of symmetric coupled lines suggests bandwidth increases with increasing even mode impedance and decreasing odd mode impedance. Insertion loss at the center frequency is minimized by setting the difference between the two mode impedances to 100  [30]. The widest bandwidth section with minimum in-band insertion loss is found to have an even mode impedance on the order of 100  and minimum odd mode impedance. Figure 5.20 shows the effect of changing the odd mode impedance via changing the coupling distance for the broadside coupled lines. The design is optimized for the 25 μm case, and the bandwidth is inversely proportional to the odd mode impedance. For comparison, the 5 μm case, having inherently lower odd mode impedance, could potentially be optimized for broader bandwidth. However, the fabrication process is limited to 25 μm. The final design is a quarter wavelengths long at 23 GHz and has effective even and odd mode impedances of 111 and 6 , respectively.

Fig. 5.20 Effect of changing coupling distance on bandwidth: (a) return loss and (b) Insertion loss with respect to the LCP coupling film thickness, t

A 152.4 μm (6 mil) via is used with a 304.8 μm (12 mil) pad to provide the electrical connection from the bottom broadside coupled line to the bottom of the package. A coplanar to microstrip transition is included on the underside of the package so it can easily be incorporated into planar circuits. Sensitivity analyses show that the package transition RF performance is relatively insensitive to expected package manufacturing variations. The package bases were fabricated on multi-layer LCP films using a printed circuit board process. Seven layers of LCP films with thickness of 25.4 μm (1 mil), 25.4 μm, 101.6 μm (4 mils), 25.4 μm, 50.8 μm (2 mils), 25.4 and 50.8 μm were laminated on top of each other to produce a total of 101.6 μm (12-mil) thick substrate. 25.4 μm thick Kuraray low temperature LCP bond films were inserted in

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between the four high temp Nippon steel LCP films. Initially, the bottom 6 layers were laminated to produce a 279.4 μm (11 mils) thick substrate. At this stage the top LCP layer is the low temperature LCP bond film. Vias are drilled and plated. Finally, a 25.4 μm high temperature LCP, to separate the coupled lines, is laminated on top to complete the package base. The bottom ground has a thickness of 36 μm to provide mechanical support. The top metal traces have a thickness of ∼9 μm. Once the multi-layer LCP structure of the package base was fabricated, laser ablation was used to create a cavity (Figs. 5.18 and 5.19a). In production, LCP films can be made with holes using low cost machining or punching techniques.

5.7.2 Bandpass Feedthrough Results and Discussion The bandpass package feedthroughs were mounted onto a 254 μm (10-mil) thick Rogers RO4350B printed circuit board using solder. A 50  coplanar waveguide to microstrip adapter was used to provide the pads for probing and bond wires to the package feedthrough (Fig. 5.21). The input of the package was probed directly on a printed circuit board. The package feedthrough transitions were measured using a Cascade Microtech probe station and Agilent’s Performance Network Analyzer 8364B (PNA). The structures were probed with both 250 and 350 μm pitch coplanar waveguide probes. The PNA was calibrated using a Through-Reflect-Line technique up to 40 GHz. The measurement of the feedthrough includes a launch on the PCB board into the package, a vertical via transition through the multi-layer LCP films, a short microstrip line on LCP, three bond wires and a ceramic adapter. Figures 5.22 and 5.23 show the measured results of the LCP thin-film bandpass package feedthrough transition. We have achieved return loss of 13 dB or higher in K-band (18–27 GHz) and insertion loss less than 0.5 dB in K-band. Across X-band, the package transition achieves 0.2 dB insertion loss and greater than 15 dB return loss with a linear phase response.

Fig. 5.21 Feedthrough structures with J Micro adaptors

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Fig. 5.22 Measured and HFSS Model return loss for feedthrough

Fig. 5.23 Measured Insertion loss on both a large scale (left) to show DC blocking and small scale (right) to show in band insertion loss

Simulations were performed with the actual copper thicknesses of the PCB board and the solder paste used for mounting. The simulations match quite well for the lower end of the band, while the deviate at the upper end. The PCB transition and J Micro adaptors were not included in the model and are a possible cause of the deviation. The coupling effect of two adjacent feedthroughs was also examined for multiple RF input and output applications. Feedthroughs were fabricated side by side with 500 μm spacing between bond pads of. Two different structures were used. The first structure has its bond pads bent for compactness, and thus the coupled sections are closer together. The second has the bond pads unbent, and thus a larger distance between the coupled sections. The coupled lines had the unused connections terminated in 50 . The worst case coupling was 25 dB for the structure with the bent

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Fig. 5.24 Coupling of two adjacent feedthroughs terminated in 50 

bond pads, while the structure with straight bond pads had a worst case coupling of 30 dB (Fig. 5.24). Isolation was measured with two 50  resistors terminated at each port. The 2 ports are separated by a distance of 1.5 mm. The measured isolation was less than 40 dB in K-band and less than 30 dB up to 37 GHz (Fig. 5.25).

Fig. 5.25 Measured isolation data for the two opposite ports

5.8 Conclusion LCP Packages have been presented with high performance in the electrical characteristics, while performing excellent in leak rate and reliability tests. A process for

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lid lamination has been developed that prevents the packaged MMICs from being exposed to high temperatures and provides hermeticity that meets the military standards. Packaged amplifiers have been subjected to a variety of tests demonstrating the long term reliability of the package platform. A new bandpass feedthrough has also been developed that provides inherent DC blocking, filtering, and provides a further improvement in hermicity by eliminating the via as path for contaminants into the package. In summary, we have developed a hermetic organic packaging platform capable of electrical performance into the millimeter range and reliability on the order of the most stringent specifications. Acknowledgments The authors wish to acknowledge the support of Endwave Corporation, REMEC Defense and Space, UC Discovery Grant, and Tom Dalrymple of the Air Force Research Laboratory.

References 1. Nicholson, D.: Low return loss DC to 60 GHz SMT Packages with Performance Verification by Precision 50 ohm load. Proceedings of 35th European Microwave Conference Paris, France. October 2005. 2. Fujii, K., Morkner, H.: A 6-30 GHz Image-rejection Distributed Resistive MMIC Mixer in a Low Cost Surface Mount Package. IEEE MTT-S International Microwave Symposium Digest, Long Beach, CA. June 2005, 37–40. 3. Fujii, K., Morkner, H.: Two Novel Broadband MMIC Amplifiers in SMT Package for 1 to 40 GHz Low Cost Applications. 35th European Microwave Conference, Paris, France. October 2005. 4. Aboush, Z., Benedikt, J., Priday, J., Tasker, R. J.: DC-50 GHz Low Loss Thermally Enhanced Low Cost LCP Package Process Utilizing Micro Via Technology. IEEE MTT-S International Microwave Symposium Digest, San Francisco, CA. June 2006, 961–964. 5. Kanno, H., Ogura, H., Takahashi, K.: Surface-Mountable Liquid Crystal Polymer Package with Vertical Via Transition Compensating Wire Inductance up to v-band. IEEE MTT-S International Microwave Symposium Digest, Philadelphia, PA. June 2003, 1159–1162. 6. Kitazawa, K., Koriyama, S., Minamiue, H., Fujii, H.: 77-GHz-band surface mountable ceramic packages. IEEE Trans. Microwave Theory Tech. 48 (9), 1488–1491, 2000 7. Palazzari, V., Thompson, D., Papageorgiou, N., Pinel, S., Lee, J. H., Sarkar, S., Pratap, R., DeJean, G., Bairavasubramanian, R., Li, R. L., Tentzeris, M., Laskar, J., Papapolymerou, J., Roselli, L.: Multi-Band RF and mm-Wave Design Solutions for Integrated RF Functions in Liquid Crystal Polymer System-on-Package Technology. Proceedings of 54th Electronic Components and Technology Conference, Las Vegas, NV. June 2004, 1658–1663. 8. Thompson, D., Kingsley, N., Wang, G., Papapolymerou, J., Tentzeris, M. M.: RF Characteristics of Thin Film Liquid Crystal Polymer (LCP) Packages for RF MEMS and MMIC Integration. IEEE MTT-S International Microwave Symposium Digest, Long Beach, CA. June 2005, 857–860. 9. Chen, M., Pham, A-V., Kapusta, C., Iannotti, J., Kornrumpf, W., Evers, N. Maciel, J., Design and development of a hermetic package using LCP for RF/Microwave MEMS switches, IEEE Trans. Microwave Theory Tech. 54 (11), 4009–4015, November 2006. 10. Chen, M. J., Pham, A.,Evers, N. A., Kapusta, C., Iannotti, J., Kornrumpf, W., Maciel, J., Karabudak, N.: Development of Multilayer Organic Modules for Hermetic Packaging of RF MEMS Circuits. IEEE MTT-S International Microwave Symposium Digest, San Francisco, CA. June 2006, 271–274.

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11. Ross, R. J.: LCP Injection Molded Packages – Keys to JEDEC 1 Performance. Proceedings of 54th Electronic Components and Technology Conference, Las Vegas, NV. June 2004, 1807–1811. 12. Aihara, K., Chen, A., Pham, A., Roman, J. W.: Development of Molded Liquid Crystal Polymer Surface Mount Packages for Millimeter Wave Applications. Proceedings of 14th Electrical Performance on Electronic Packaging, Austin, TX. October 2005, 167–170. 13. [Online.] Available: http://www.qlpkg.com 14. Leaversuch, R.: Laser Welding Comes of Age. Plastics Technology. http://www.ptonline.com/ articles/200202fa2.html (2002). Accessed 15 February 2009. 15. [Online.] Available: http://www.dscc.dla.mil/programs /MilSpec /List Docs.asp?BasicDoc= MIL-STD-883 16. Aihara, K., Pham, A.: Development of Thin-Film Liquid Crystal Polymer Surface Mount Packages for Ka-band Applications. IEEE MTT-S International Microwave Symposium Digest, San Francisco, CA. June 2006, 956–959. 17. Aihara, K., Chen, M. J., Pham, A.: Development of thin-film liquid-crystal-polymer surfacemount packages for Ka-band applications. IEEE Trans. Microwave Theory Tech. 56 (9), 2111–2117, 2008 18. High Frequency Structure Simulator www.ansoft.com 19. Li, M., Hix, K., Dosser, L., Hartke, K., Blackshire, J.: Micromachining of Liquid Crystal Polymer Film With Frequency Converted Diode-Pumped Nd:YVO4 laser. Proceedings of SPIE, 4977, 2003, 207–218. 20. Pham, A., Laskar, J., Schappacher, J.: Development of On-Wafer Microstrip Characterization Techniques. Proceedings of 47th IEEE ARFTG Conference Digest, June 1996, 85–94. 21. Fraser, A., Schappacher, J.: Test adapter substrates ease the task of measuring PHEMT FETs. Microwave Journal. 38, 120–122, 1995 22. Agilent Advanced Design Sys’tem (ADS) 23. [Online.] Available: http://www.sixsigmaservices.com/hermeticity.asp 24. HYPERTEXT:http://www.dscc.dla.mil/Downloads/MilSpec/Docs/MIL-STD-883/std883 .pdf 25. HYPERTEXT:http://www.jedec.org/ 26. HYPERTEXT: http://www.endwave.com 27. HYPERTEXT: http://www.hittite.com/HMC564 28. McGrath, M., Aihara, K., Pham, A. V., Nelson, S.: Development of LCP Surface Mount Package with a Bandpass Feedthrough at K-band. IEEE MTT-S International Microwave Symposium Digest, Atlanta, GA, June 2008, 93–96. 29. Djordjevic, A., Bazdar, M., Sarkar, T. Harrington, R., LINPAR for Windows – Matrix Parameters for Multiconductor Transmission Lines – Software and User’s Manual, Version 2.0, Artech House Publishers, 1999. 30. Kajfez, D., Vidula, B. S.: Design equations for symmetric DC blocks. IEEE Trans. Microwave Theory Tech. 28 (9), 974–981, 1980

Chapter 6

RF/Microwave Substrate Packaging Roadmap for Portable Devices Mumtaz Bora

Abstract The RF/Microwave substrates play a key role in the design and performance of RF products. The use of high speed devices, including RF circuits for wireless, broadband and portable applications drives the need for improved electrical performance. The low loss dielectrics will play a significant role in RF isolation and performance as signal communication speeds shift from 1–5 to 5–10 for future applications. The understanding of substrate material properties, PWB design and substrate selection play an important role in product reliability. The PWB industry is responding with many new material sets and processes such as high Tg and low loss dielectric, microvia boards, thinner dielectrics and Flex/RigidFlex substrates. The users face the challenges of selection of appropriate materials with low moisture absorption and good dimensional stability and meeting the cost target. Additionally, as new environmental regulations like ROHS, WEEE and REACH take effect, the necessary cost and performance tradeoffs have to be made to stay competitive in the global market. This chapter discusses the material properties of various substrates and options to meet packaging density and performance needs as the industry migrates to thinner, lighter and cost effective portable products to meet the demands of wireless, broadband and high reliability applications.

6.1 Introduction The trends of increased functionality and reduced size of portable wireless products, such as handsets and PDAs are demanding increased routing densities for printed circuit boards. The handheld wireless product market place demands products that are small, thin, low-cost and lightweight and improved user interfaces. In addition, the M. Bora (B) Peregrine Semiconductors, Inc., San Diego, CA 92121, USA e-mail: [email protected]

K. Kuang et al. (eds.), RF and Microwave Microelectronics Packaging, C Springer Science+Business Media, LLC 2010 DOI 10.1007/978-1-4419-0984-8_6, 

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convergence of handheld wireless phones with palmtop computers and Internet appliances is accelerating the need for functional circuits designed with smallest, low-cost technology. The key element of success for portable products is the design of the printed circuit board as meeting RF margins and design specs is heavily dependent on PWB design and material set , # of layers, type and size of vias, trace width , type of laminates etc. This chapter reviews the design options and the materials available to make portable products and discusses ways to meet packaging density and performance needs. The material discussion focuses on types of organic materials used in portable products and techniques to make PWBs thinner lighter and cost effective. The chapter also reviews the portable product roadmap using HDI (High Density Interconnect) and Anylayer via technologies such as ALIVHTM and B2it etc.

6.2 Substrate Materials for Portable Products Many substrate materials are used to fabricate PC boards. The most common being epoxy glass typically known as FR-4 (Flame Retardant 4) in industry. The specialty materials discussed here are used in high performance PWB. These include R ), epoxy cyanate ester blends (BT- Bismaleamide Triazine), polyimide (Kapton R (PTFE). The elecCyanate ester, PPO Blends, polyphenylene oxide and Teflon trical, mechanical and RF properties of the substrate are critical for overall system performance (Table 6.1) Table 6.1 Typical values of multi layer PWB material properties [3] Material

Dk-1 GHz

Tan δ,1 GHz

Tg ◦ C

Td ◦ C

Moisture %

Mid/Hi TgFR-4 Polyimide Cyanate Ester BT PTFE-glass PTFEmat-CE PTFE Ceramic

4.43 4.06 3.65 2.94 2.60 2.79 2.79

0.018 0.006 0.006 0.011 0.001 0.003 0.003

145–178◦ C > 250 > 200 181 – – –

310–345◦ C > 300 > 300 295 > 300 > 300 > 300

1–1.5 1.0 – 0.6 – – 0.4

6.3 RF Substrate Materials Thermal and Electrical Properties 6.3.1 Standard FR-4 FR-4 is a highly crosslinked brominated epoxy resin reinforced with woven glass cloth. Most FR-4 materials meet the UL- V0 classification of flame retardancy.

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Most FR-4 materials are either made of difunctional or tetrafunctional resin systems resulting in either a Tg of 120◦ C for difunctional epoxy resins and a Tg of 140◦ C or above for tetrafuntional epoxy resins. These materials were acceptable for eutectic tin lead reflow. Standard FR-4 made of epoxy resin and woven glass has a Dk in the range of 4.4 and tan δ of 0.02. [1]

6.3.2 High TG FR-4 With the advent of lead free, the industry has switched to laminates with Tg of 150◦ C or above using a tetrafunctional epoxy. Laser drillable prepreg is commonly used in the outer layers of high density microvia boards to ease the drilling and plating of vias. Higher glass transition (170◦ C) or above materials are also available, but do cost 10% more and are widely used for high temp. reflow. It is important to understand moisture absorption in the High Tg materials as this can become an issue during assembly and field life. High Tg laminate has a Dk in the range of 4.4 and tan δ of 0.02. Figure 6.1 shows a multilayer PWB in HDI (high Density Interconnect) – Build up construction and Fig. 6.2 shows a multilayer PWB in Anylayer ALIVHTM construction. [1, 2]

Fig. 6.1 High Tg- HDI board

Fig. 6.2 High Tg Anylayer board (ALIVH)TM (courtesy of Panasonic Corp.)

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6.3.3 Polyimide R Polyimide (Kapton ) substrate material has the best thermal stability as it has a Tg in excess of 250◦ C, a high thermal degradation temperature and CTE lower than epoxy-glass. The combination of high TG and low CTE makes it an excellent candidate for applications where package, assembly or system must survive fatigue life for PTH and multiple thermal cycles over a wide temperature range. A combination of polyimide and epoxy glass board fabrication known as Rigid Flex has found an excellent application in cell phones, camera modules, video cameras and other portable products. Polyimide flex cables have contributed a lot of space saving in cell phone designs for anchoring LCDs on the main board, both, static and dynamic flex applications have been used in portable products and survived dynamic shock tests. Polyimide substrates do cost more than epoxy glass, so cost vs. design advantage has to weigh carefully. Additionally, moisture absorption and uptake can be an issue so proper baking drying, packaging and handling practices have to be followed. Polyimide has a Dk value of 4.06 at I GHz and tan δ of .006 at 1 GHz, so it is slightly lower than epoxy glass. Figure 6.3 shows some of the Rigid Flex applications in portable products. [3]

a

b

Fig. 6.3 Rigid flex applications in portable products

6.4 Cyanate Ester Blend (BT- Bismaleamide Triazine) BT resin is a blend of cyanate ester resin with epoxy glass and a small amount of polyimide. This resin blend is coated on glass cloth to produce a laminate. BT laminates have a Tg of 180◦ C and a high degradation temperature. The moisture uptake and processibility of BT laminate is much closer to epoxy glass than to polyimide. BT laminate is less expensive than polyimide, but it is more expensive than FR-4, so cost/design tradeoff have to be made.

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The tan δ and Dk value of BT resin is much lower than epoxy. BT has a Dk of 2.94 and a tan δ of 0.01. This improvement is useful in some applications such as substrate materials for BGAs, but it is inadequate for many high performance applications. [3]

6.5 PTFE Based Laminates R The PTFE resin system is commonly known under the trade name Teflon PTFE provides the best electrical performance as the Dk of PTFE is close to 2.0 and the tan δ is less than .001.PTFE has a combination of excellent electrical and thermal properties. It is a thermal plastic that can operate at temperatures above 300◦ C without softening, oxidation or other form of degradation. It is naturally fire retardant so it does not need bromine addition to achieve the UL rating -V0. It has very low moisture absorption. PTFE laminates are much more expensive (100×) than FR-4 so proper justification is needed for use of PTFE. Several laminate systems are available with PTFE resins. [3]

6.5.1 PTFE Resin Coated on Conventional Glass The construction of this laminate is similar to standard FR-4, but it is not very usable in multilayer board constructions. The higher CTE of PTFE coupled with in plane strength of glass cloth leads to a very high Z axis expansion that can easily fracture a PTH during soldering. This material can be used for applications such as antennas and RF microstrip cables where circuit is placed on one side of the substrate and ground plan eon the other, Plated holes are not needed and a very low Dk is not critical. [3]

6.5.2 PTFE Film Impregnated with Cyanate Ester or Epoxy Resin PTFE film can be impregnated with low Dk resin like cyanate ester and formed into a PWB substrate without any glass reinforcement. This composite formed is at least as good as a glass reinforced PTFE and can be fabricated into a multi layer board with mixture of PTFE and epoxy layers. The major application for this material is in supercomputer design that has high speed circuits requiring enhanced electrical properties. [3]

6.5.3 PTFE Mixed with Low Dk Ceramic PTFE mixed with 60% ceramic by weight makes a composite with low CTE, low tan δ and low Dk and a very close match to the CTE of FR-4.This allows the fabrication of an unbalanced hybrid structure without excessive warp. The cost of the

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composite is 4–5× times FR-4 cost, which makes it less expensive than the other PTFE options. The only drawback is the needs for plasma dry etch to ensure hole wall wetting. [3]

6.6 Materials Summary Substrate material properties play an important role in PCB performance. The use of high speed devices, including RF circuits for wireless applications drives the need for improved electrical performance. The growth of broadband wireless industry is expected to shift Signal communication speeds from 1–5 to 5–10 Gbps depending on applications. The portable products industry is responding with high Tg laminates, microvia boards, thinner dielectric layers and low Dk materials to meet these demands. The major challenge faced by designers is selection of appropriate materials and meeting the cost targets. The other challenges faced are availability of materials with low moisture absorption, good dimensional stability, low warpage and low cost. PCB suppliers are already looking at material and design factors that affect signal integrity, including epoxy and hardener, resin chemistry, laminate ply up construction, resin content, glass cloth fabric weaves, copper foil surface and moisture pick up. This is essential because of all the material options, it is evident that the higher Tg laminates ( multifunctional epoxies) are likely to be the lowest cost option and main drivers for substrates for high volume manufacturing

6.7 Substrate Critical Properties The six critical properties of substrates are 1. 2. 3. 4. 5. 6.

Dielectric Constant (Dk) Dissipation Factor (Dielectric Loss) – tan δ Glass Transition Temperature Tg Degradation temp. Tk Moisture Absorption Coefficient of Thermal Expansion (CTE)

6.7.1 Dielectric Constant (Dk) The impedance and transmission speed are both affected by Dk. The characteristic impedance must be matched throughout the high speed circuit. The current industry spec is for impedance is 50  ± 10%, but as we migrate to GHz speed boards, this spec may need to be tightened to 50  ± 7% and eventually to 5%.

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Thinner PWBs allow for better PTH and microvia reliability and minimize crosstalk; this makes low Dk materials more desirable. Transmission speed is critical because signal transit time affects device timing. At 1 GHz PCB materials have a Dk of 4.4 and the transmission speed is reduced to 6 in/ns compared to air Dk =1 and speed 12 in/ns. With low Dk materials, transmission speed is increased to 8 in/ns.

6.7.2 Dissipation Factor/Dielectric Loss: (tan δ) The energy loss per wavelength from the transmitted signal isproportional to tan δ. For standard epoxy glass materials, tan δ is 0.02 which results in serious loss at frequencies above 1 GHz. For circuits operating at 1 GHz or higher, a material such as PTFE with tan δ of 0.001 is preferred.

6.7.3 Glass Transition Temperature (Tg) The thermal properties of an epoxy glass laminates are characterized by glass transition temperature Tg and glass decomposition temperature Td. The Tg of a resin is the temperature at which the resin reversibly changes from a glassy state to a rubbery state. Tg affects the thermal fatigue life of a PTH and also impacts solder joint reliability. When the industry migrated to lead free reflow, there was a switch to mid Tg (150◦ C) – Td 310◦ C and High Tg 170◦ C – Td 340◦ C materials to maintain thermal stability of the laminate thru high temp. reflow (245–260◦ C). The earlier tin lead eutectic solder process used laminates of 140◦ C Tg for a peak reflow temp. ranging from 225 to 240◦ C.

6.7.4 Glass Decomposition Temperature; Td The Td is the decomposition temperature of a laminate where the epoxy begins to degrade irreversibly. Td is generally much higher than Tg. One measure of degradation is the length of time at 260◦ C before a rapid exothermic takes place and material expands due to delaminating. The migration of the surface mount assembly industry to lead free reflow has resulted in the revision of IPC 4101_Specification for Base Material for Rigid and Multilayer Boards to Revision B. This includes several new tests for laminates including Td, Time to delamination at T260, T288, T300 and Z axis expansion. These tests are critical in conducting the qualification of laminates and PWBs for lead free reflow. [1]

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6.7.5 Moisture Absorption Moisture absorption is detrimental to the performance of a PWB. It raises the Dk, expands the board and causes barrel cracking and delaminating during reflow. Even a small increase in Dk value can cause drift in the impedance values and affect circuit performance. Proper, storage handling and packaging of PWB is essential for success in reflow and test.

6.7.6 Coefficient of Thermal Expansion The CTE for FR-4 is 14–20 PPM/C is higher than that of ceramic or silicon ∼∼3–5 PPM/C. The resulting thermal expansion mismatch between the PWB and assembled devices can lead to solder joint fatigue failures when the system undergoes multiple heat cycles during power up and power down. In cases where the device package is incompatible with the FR-4 substrate, a higher Tg epoxy glass with filler material can be used. Proper processing of drilled holes should be ensured if using substrate materials with fillers. Other options are FR4 material with quartz R Both of these materials are expensive and difficult to or Aramid fibers (Kevlar) process.

6.8 Materials Summary Substrate material properties play an important role in PCB performance. The use of high speed devices, including RF circuits for wireless applications drives the need for improved electrical performance. The growth of broadband wireless industry is expected to shift Signal communication speeds from 1—5 to 5—10 Gbps depending on applications. The portable products industry is responding with high Tg laminates, microvia boards, thinner dielectric layers and low Dk materials to meet these demands. The major challenge faced by designers is selection of appropriate materials and meeting the cost targets. The other challenges faced are availability of materials with low moisture absorption, good dimensional stability, low warpage and low cost. PCB suppliers are already looking at material and design factors that affect signal integrity, including epoxy and hardener, resin chemistry, laminate ply up construction, resin content, glass cloth fabric weaves, copper foil surface and moisture pick up. This is essential because from all the material options, it is evident that the higher TG laminates (multifunctional epoxies) are likely to be the lowest cost option and main drivers for RF substrates for high volume manufacturing.

6.9 Portable Products Technology Roadmap Portable products such as Handsets and PDA are currently operating in the 800– 1900 MHz range for CDMA products and 850–1900 MHz range for GSM products. As the technology goes to higher frequency ranges such as1700–2100 MHz for

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AWS, 1900–2100 MHz for WCDMA and 2 5–3.5 GHz for WiMax, more demand is coming on the PWB substrate to withstand these higher frequencies and meet performance margins. Newer ways to improve PWB performance are being addressed to meet these demands. Historically, the industry has met this challenge through high density interconnect technology and increased silicon integration and component miniaturization. Microvia high density interconnect (HDI) also known as build up technology, is one method for constructing circuit boards with high routing density demands For HDI board, vias can be formed using unreinforced dielectric such as Resin Coated Foil (RCF), using processing techniques such as laser drilling or photoimaging. The vias are then metallized using electroless copper/electrolytic plating. The advantage of the HDI construction is the ability to create smaller vias (6 mils) and via pad sizes. This enables higher routing density, lower metal count, reduced board area and increased functionality as compared to conventional plated thru hole boards. HDI improves the wiring density by using build up microvia in the outer layers. However there is still dead space where components cannot be mounted and lines cannot be wired, because of staggered via whole structure. On the other hand, ALIVH-GTM (Any Layer Interstitial via Hole) needs no through hole. This is because any two layers are electrically connected by IVH (Interstitial Via Hole). The IVH can be placed in any position. Since there is no through hole that disturbs interconnections between components, the dead space becomes reduced and the wiring capability is improved greatly. The technology uses copper filled epoxy paste for via formation instead of plated copper vias. [4] The fabrication processes for conductive paste/ink filled PWBs consist of 1. Formation of microvia in individual prepreg layers using laser drill or photo via formation. 2. Filling via holes with conductive paste/oink materials. 3. 3/ Lamination of copper foil on the prepreg with filled microvia. 4. Circuitization of copper foil by photolithography 5. Testing of individual layers 6. Lamination of tested individual layers 7. Circuitization of outer layers by photolithography The conductive paste/ink materials used for via filling must have corrosion resistance, electrical conductance, and low shrinkage after processing high strength, good adhesion to PCB material and low cost. B2it (Buried Bump Interconnect) is another Anylayer via technology using conductive silver paste bumps on copper foil. The conical bumps can pierce through dielectric prepreg to establish interconnections between conducting layers. The B2it structure is intended to provide high density interconnections in the vertical dimension. The use of piercing technology enables the interconnection of bumps to the prepreg followed by lamination of the next layer of copper foil. This technology was patented by Toshiba [5]. This technology eliminates drilling and plating of microvia making the manufacturing process simpler and more environmentally friendly.

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Fig. 6.4 HDI board

Figures 6.4 and 6.5 show the structure of an HDI (High Density Interconnect) board with plated microvias and Anylayer Board with conductive paste microvias in each layer. The migration to lead free reflow is bringing many challenges for the PCB industry. High Tg laminates, stability of materials thru 2× reflows, rework, moisture sensitivity etc. This requires careful evaluation of new laminate materials, balancing component layout and optimization of reflow profiles to minimize damage to PWBs. This is critical for thin PWBs (> 0.1 mm) boards used in cell phones and other portable products that use build up microvia technologies Assembly should be subjected to temperature humidity testing typically 85◦ C/85% RH and temperature cycling from –40 to +125◦ C or other combination per IPC 9701A [6]. For portable products, a dynamic shock test such as drop test is required to assess the mechanical integrity of the assembly and to ensure that there are no solder joint crack or pad cratering in the laminate. Additionally, microvia to capture pad interface should be intact after shock test. The advent of lead free reflow resulted in addition of two new reliability tests for PWB reliability. CAF test – Conductive Anodic Filament Resistance Test (Electromechanical Migration Testing), IPC Test Method 2.6.25 and IST Interconnect stress test IPC test method 2.6.26 for DC current Induced Thermal Cycling test.

6

RF/Microwave Substrate Packaging Roadmap for Portable Devices

Fig. 6.5 Anylayer board (ALIVH, B2it)

Fig. 6.6 HDI board – thermal shock

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Fig. 6.7 ALIVH board – thermal shock

Figures 6.6 and 6.7 show an HDI board and Anylayer board after thermal shock test showing microvia, laminate structure and solder joints are intact.

6.10 Summary Portable products technology roadmap is migrating towards miniaturization of PWBs and transition to thin form factor PWB (< 0.8 mm thickness), fine line /fine spacing, tighter component spacing and use of fine pitch packages (0.5 mm or less) and lower cost targets. The growth of 2.5, 3G handsets, PDAs wireless PDAs and notebook PCs is fueling the growth of fine pitch electronics. The assessment of portable products currently used in the industry indicates the following: Power requirements with longer battery life, talk and standby time. Integration of RF, impedance , interconnection and other functions for wireless. Lightweight plastics and materials with better dielectric constant properties. Integrated stack-ups to reduce layer counts, thickness including stacked chips and flip chip. High definition displays with character and voice recognition. Greater processing power and memory.

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The portables PWB technology factors are summarized in the table below (Table 6.2)

Table 6.2 Portable product roadmap [2, 5] Technology factor

2009

2010

2011

Materials Board area cm2 PWB thickness Stack up # of layers Line width/space-microns Microvia Diam/Pad (um) Min. Hole Diam (um) Microvia quantity Solder mask registration Laser Microvia aspect ratio Drilled hole -mechanical

FR-4/RigidFlex 10 0.8 mm 2-4-2 10/8 100/100, 75/75 100/250 200 4000 75 0.9/1 6:1

FR4/Flex/RigidFlex 10 0.75 mm 2-2-2 8/6 65/65 75/150 150 5000 50 1.0:1 8:1

FR4/Flex/Low Dk 8 0.55 mm 2-2-2 6/4 50/50 50/110 100 6000 40 1.2/1 9:1

It is important to understand that there is a difference in the RF roadmap and portables roadmap as the technology requirements for both are different. The RF/microwave require larger PWB sizes and special laminate materials to handle impedance control and low DK/Df properties. The PWBs have fiber optic input and need active heat removal technology. The assembly requires large array packages with some ceramic packaging requirements. The assemblies require additional shielding at both; the board level and the equipment level .They also require High I/O and High speed connectors (Table 6.3)

Table 6.3 RF product roadmap [2, 4, 5] Technology factor

2009

2010

2011

Materials Board area cm2 PWB thickness-mm Stack up # of Layers Line width/space-microns Microvia Diam/Pad (μm) Min. Hole Diam (μm) Microvia quantity Solder mask registration Laser microvia aspect ratio Drilled hole –mechanical

Low DK/PTFE 1000 2.5 mm 16 10/8 100/100, 75/75 100/250 200 4000 75 0.9/1 6:1

Low Dk 1110 2.5 mm 18 8/6 75/75 75/150 150 5000 50 1.0:1 8:1

Low Dk 1200 2.5 mm 20 6/4 70/90 50/110 100 6000 40 1.2/1 9:1

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6.11 Summary The RF/Microwave roadmap for portable wireless products is expanding in many product applications. The PWB design and selection of materials plays a key role in the success of product performance. During product development phase it is important to understand the RF characteristics of the laminate material. If multiple suppliers are used, RF characterization should be done using each supplier. It is recommended to stay consistent with the material set when technology is transferred from prototype to production as RF characteristics can change and affect performance margins of the product. The environmental roadmap should be considered in material selection. As new environmental regulations take effect for RoHS (Restriction of Hazardous substances), WEEE (Waste Electrical and Electronic Equipment) and REACH (Registration, Evaluation and Authorization of Chemicals), Halogen Free etc, the necessary cost and product requirement tradeoffs have to be made to stay competitive and meet the environmental protocols of the global market.

References 1. IPC 4101 B- Specification for base materials for rigid and multilayer boards 2. Microvias for low cost, high density interconnects – John H. Lau, S.W. Ricky Lee-ISBN-0-07136327-0 3. Printed circuits handbook – Clyde f. Coombs Jr. 4th Edition-ISBN-0-07-012754-9 4. Advanced ALIVH substrate with fine design rules for high density packaging. Ishimaru, Yukihiro et al. 1999 5. New B2it method for highdensity printed circuit boards. Circuit Mounting Society Journal, 1998 6. IPC 9701A- Performance test methods and qualification requirements for surface mount solder attachments

Chapter 7

Ceramic Systems in Package for RF and Microwave Thomas Bartnitzek, William Gautier, Guangwen Qu, Shi Cheng, and Afshin Ziaei

7.1 Introduction Ceramic multilayers are known as very universal PCB s and packages with advanced properties, 3-dimensional functionalities, good RF performance and integration of passives. Since LTCC as a highly reliable ceramic interconnection technology enables an increased circuit density and an advanced versatility of functions, it acts as the carrier for the electrical wiring and packaging, contains buried components and structures, waveguides and antenna functions and is last but not least the package for the system with the opportunity of hermetic encapsulation. Advanced RF suitable materials with very low losses enable the entering of frequency ranges and loss sensitive applications which have not been addressable by ceramic techniques until a couple of years ago. The current leading edge in electronics demands more functionality in electronic devices; packaging solutions must be smaller, lighter, more complex, operate at higher frequencies and accommodate more components per unit area. This fact is not only a challenge to RF and microwave designers, but also to packaging engineers and electronic materials suppliers. Circuit design, packaging, material and system development have to work together simultaneously to meet these challenges.

7.2 RF-PLATFORM This article will refer to the cooperation in a network, which is an organization combining these points from the customer request up to the complete system. The network RF-PLATFORM is a project consortium of an European Integrated project T. Bartnitzek (B) VIA electronic GmbH, Robert-Friese-Straße 3, DE-07629 Hermsdorf e-mail: [email protected]

K. Kuang et al. (eds.), RF and Microwave Microelectronics Packaging, C Springer Science+Business Media, LLC 2010 DOI 10.1007/978-1-4419-0984-8_7, 

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combining a wide field of R&D competences with a consolidated service action. All partners in the consortium investigate different technologies, develop applications and perform multi project wafer production runs consisting of numerous structures in their technologies. This cooperation has been helpful to establish a strong technological knowledge base as well as manufacturing competencies. One of the main technological challenges in RF-Platform is the development of systems-in-package for a couple of applications in combination with RF-MEMS switches, packaged in and with ceramic multilayers. There are five sections describing the special ceramic technology, followed by three systems as applications and a final section about the specific RF-MEMS.

7.2.1 LTCC for Systems in Package The development of more complex devices generates a constant pressure to reduce both size and part count in RF and microwave circuits, mobile handsets and other devices beeing constrained to get more lightweight, more miniaturized and less expensive. The high potential of integration and combination of functional properties makes low temperature co-fired ceramic (LTCC) the core technology of module integration. Many active and passive components can be integrated and assembled into a multilayer subsystem with 10–15 or even more layers. They may contain integrated passives such as capacitors, inductors and impedance controlled transmission lines, baluns, filter elements as well as additional surface mounted devices. But not only the fact that passives may be integrated instead of assembling is important. The option to integrate many components currently assembled on the surfaces saves solder connections, wiring length and enables improvement of the characteristics [1]. In particular the field of RF and microwave requires lowering of parasitics, which can be achieved by shorter wiring, less vias going up the stack to the SMD and down again into the circuit. Furthermore the option to place the components directly on the path of the wave (e.g. let-in a sheet resistor as a load flush at the end of a buried stripline without impedance mismatch) brings advantages for increasing the performance and functionality of the system. As a matter of course the opportunity to create windows and cavities (also stepped ones), frames, membranes with the multilayer material by the lamination of differently tooled single sheets is attractive. This enables advanced chip assemblies either by short and flat wire loops or using top-down techniques, even lowered to a buried stripline structure [2]. Other advantages of LTCC are the good thermal resistance compared to organic base materials (e.g. Teflon and FR4), the excellent thermal shock resistance and the good matching of the thermal coefficient of expansion (TCE) with silicon, GaAs, SiGe and quartz as base material for integrated passive devices (IPD). This enables numerous assembly opportunities including flip chip and micro-ball-bumping based chip-scale-packaging (CSP) techniques.

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7.2.2 Design of Ceramic Packages The development of LTCC circuits can be significantly accelerated with the help of electromagnetic analyses. Additionally, in some cases EM analyses are the only way to identify parasitic couplings between different circuit groups already in an early stage of a design. An efficient design flow even for complex circuits can be obtained when an appropriate electromagnetic analysis method is used. It is known that high frequency applications do not leave too much space for creative design or technological comfort. The layouts are driven by extremely harsh requirements, applications need special materials for the complete setup, beginning with carriers, chips and packaging, RF waveguides and components, even lids, connectors and adhesives have to be chosen very carefully to avoid unwanted loss, interactions or reduction of performance. Although LTCC is used significantly for high-performance, high-density packaging, low loss LTCC has not yet realized its potential as a material for high-volume manufacturing requirements of emerging microwave designs. One factor holding low loss LTCC back from reaching this potential is the lack of design infrastructure. Silicon and gallium arsenide technologies have well-developed libraries of component models in various EDA packages for designers to use. The reason that low loss LTCC does not yet have this level of design infrastructure is that for simple, low frequency, low component density applications, these models are unnecessary. Coupling between signal lines, effects of quarter-wave resonance effects, and dielectric loss were generally minor considerations that could largely be ignored. For modern microwave designs, however, these factors cannot be ignored [3]. The supplier of the investigated LTCC material DuPont 943 Green TapeTM provided a design kit to overcome these drawbacks a few years ago [4]. Additional features, especially for frequencies above 38 GHz, have been simulated, calculated and designed by the microwave engineers in the consortium. Qualified feedback from test vehicles leads to a substantial knowledge base. So far it shall be mentioned, that the design according to design rules and recommendations would help to have best possible results and high RF performance at the end. The design of the structures has to fulfill many requirements, because the wave character of signals in the two-digit GHz frequency range is the dominant component of the conductive mechanism.

7.2.3 Why Multi-Project Wafers Made of LTCC? The field of RF and microwave is both delicate and mainly not a mass market and that is why the number of independent suppliers acting on the open market is low. Most of the very advanced materials are not comparably published, as there is a complicated knowledge base in the market and little information available, based on applications. Material suppliers manufacture some specific products for key customers, which are not merchandized to others. Available publications are

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often presenting results, minus information about materials and technology, leaving out process or technological details. So far the access to advanced technologies is complicated for potential users, companies, developers or institutes. Additionally they are not in the focus of sales activities and will suffer from high NRE and development cost for a single application. Typically R&D people especially in SME’s, as well as researchers, developers in different technologies of RF and microwave business often do have at least one of the following problems: • • • • • •

they have to deal with new requirements are not equivalently equipped to cover many technologies have not enough experience in the design of a system or subsystem possible suppliers do not gladly offer very small numbers of samples if they do, NRE and small volume cost for one-time jobs are very high they need support in design, simulation, measurements.

The main intention was to characterize this market, to generate an adequate network of specialists to provide these services, beginning with knowledge, followed by R&D capabilities up to manufacturing, assembly and test. In that sense, the processing as Multi-Project-Runs helps to split the cost per partner attractively. With a low volume test vehicle or prototype this is a cost efficient option for interested customers to enter the available runs of different technologies.

7.2.4 Hermetic Capping of MEMS with Ceramic Lids As a first technology VIA developed a hermetically sealable lid made of LTCC with vertical feedthroughs and a sealing frame for wafer level packaging on top of the Si-MEMS surface. This enables an SMT like handling of a single or an array of MEMS switches without their own packaging. The movable part of the switching bridge on MEMS switches needs to be protected against moisture, dust and sticky media like flux residue. The principle of these caps is to combine a sealing step with the electrical connection of the chip with the outside world. This permits one to overcome a typical difficulty with the capping of MEMS: through holes in silicon to connect the MEMS to the rear are not available for all technologies, would have to be performed hermetically and could not cover all expected frequency ranges with a high quality. Figure 7.1 shows the opportunities of this capping principle with the illustration of the circular solder connection and the electrical bumps. The interface between chip and ceramic multilayer lid consists of a ringlike outer bonding which represents the sealing frame. Furthermore the contacts inside (light grey) are electrical pads. The demonstrator modules being manufactured within the project have been produced with a standard LTCC, processed in pressure assisted

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Fig. 7.1 Cross section of a MEMS chip with soldered hermetic cap

sintering. Top and bottom surface metallizations are performed in thinfilm technology to enable both wirebonding and soldering. The solder rings, as well as the connections, have been applied with stencil printing of a class 5 gold-tin solder paste on the LTCC. After reflowing and flux removal the cap can be flip-chipped to the MEMS counterpart. The MPW for LTCC caps consisted of 6 different structures, where single caps had a size up to 13×6 mm and could be soldered on the silicon chips. (see Fig. 7.2a and b) A continuing development is still ongoing using LTCC with improved TCE matching to allow the bonding of larger groups of lids and in the future as a real wafer-level process. Therefore it is neccessary to achieve a mismatch in TCE preferably below 0.3 ppm/K, taking into account, that the coefficient is not linear over temperature neither with silicon nor with LTCC.

7.2.5 LTCC Packages for Advanced RF and Microwave Applications The following sections will show some applications in more detail. They are parts of the MPW runs and demonstrate some remarkable opportunities how to use the advantages of a high performance and low loss LTCC, concretely DuPont 943. LTCC allows integration of features that have useful functions beyond a standard PCB. Due to the layer structure of ceramic (see Fig. 7.3) material with an excellent HF performance one can intergrate chip pockets for flip chip (1) or low-loop wiring (2), resistors in inner layers as loads integratable in RF lines (3) and radiating/antenna structures (4). These are just a few of the integrable features: many varieties of special line routing as striplines, CPW, hollow feeds, which are not hollow, but filled with ceramic, have walls made of stacked vias and top / bottom of

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a

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Fig. 7.2 Singularized LTCC caps and soldered cap on MEMS-MPW (photo a: Dr. Janes, FhG ISIT)

wide conductors (5). Furthermore spiral inductors, capacitor plates with the same or higher k material, are also available. The challenge of manufacturing high quality LTCC for RF applications is the combination of highly dense structures, small vias, catchpads and clearances around them, high demand for extreme alignment accuracies in the stack, thin lines directly besides huge solid and meshed GND and very small resistors. This is a complicated situation for the manufacturer. Through the use of very special tools and technologies the results became quite acceptable. After sintering the lateral shrinkage

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Fig. 7.3 Schematic cross section and total view of the MPW II layout

tolerances could be reduced to less than ± 0.1% with a substrate warpage below 50 μm over a length of 100 mm [5].

7.3 Three Examples 7.3.1 4 by 4 Patch Antenna Array for Operation at 35 GHz William Gautier The antenna demonstrated in the coming section is an antenna array designed for spaceborne communication at 35 GHz. The antenna is intended to be electrically steered in the H-plane and assumes a fixed broadside pattern in the E-plane. In order to facilitate the integration of the antenna in the complete RF front-end, a ceramic tape has been favorably preferred to an organic soft-substrate for the realization of the antenna. The antenna is made out of a low-loss 6-layer LTCC. DuPont 943 substrate ( r = 7.4, tan δ = 0.0015), which could be the six top layers of a 3D fully integrated millimeter-wave LTCC module containing the different electronic components of the transceiver. The main beam of the antenna may be electrically steered by means of RF-MEMS phase shifters processed on silicon and integrated in a hybrid fashion onto the ceramic substrate of the antenna. The work presented below has been motivated by the will to learn about the gain that LTCC technology could bring for the next generation of millimeter-wave phased array antennas, where higher integration density, lower fabrication costs and better efficiency is expected. The following paragraphs will present the different features of the antenna manufactured in LTCC technology. The two first sections will describe successively the design of the Ka-band antenna array and the related measurements necessary to assess the design and the fabrication of the antenna. Finally, the last section will introduce a novel LTCC-based hybrid integration and packaging concept for the RFMEMS phase shifters. The proposed concept is intended for implementation within the frame of the already mentioned project.

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7.3.1.1 Design of the Fixed Beam Antenna The fixed beam antenna is a four-by-four microstrip antenna array. The antenna array is designed with four sub-arrays connected in parallel by a 1-to-4 corporate feed network. The feed network distributes the RF-power to four feeding microstrip lines, where each microstrip line feeds one of the four sub-arrays. The radiating patches are realized on top of the top LTCC layer. The feed network, corporate feed network plus feeding microstrip lines, is processed five layers below the patches, i.e. one 110 μm-thick LTCC layer above the back-side of the antenna. Three LTCC layers below the patches, a metal plane serving as ground plane for both the radiating elements and the buried microstrip feed network is realized. Each one of the four sub-arrays is designed with four patches connected in series by one of the four buried feeding microstrip lines. The patches are connected to their respective feeding line according to the aperture coupling principle through coupling slots patterned in the common ground plane. A cross- sectional view of the multi-layer ceramic setup containing the various features described above is given in Fig. 7.4. The last patches of the sub-arrays are placed one-quarter of guided wavelength away from the open-circuited end of the buried feeding microstrip lines, at a maximum of the magnetic field. Further, since the radiation pattern to achieve in the E-plane is broadside, all four patches of a sub-array have to be fed in phase. This is done by placing them one guided wavelength away from one another. Finally, the coupling slots are centered on the symmetry axis of the feeding microstrip lines, which have themselves the same symmetry axes as the microstrip antennas. In order to minimize the side lobe level of the pattern radiated in the E-plane, an aperture distribution is implemented among the four patches of each sub-array. Since all patches are in series, the same current feeds them all, thus the amount of energy radiated by a patch is proportional to the length of the coupling slot placed below it. For this reason, the sub-arrays of the antenna are designed with 600 μm-long coupling slots for the two patches close to the center of the sub-array and with 525 μm-long coupling slots for the first and last patches. All coupling slots are H-shaped and are 100 μm-wide. The corporate feed network connecting the four sub-arrays is designed

Fig. 7.4 Cross-sectional view of the antenna array on 6-layer DuPont 943 substrate

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using asymmetrical T-junction power dividers allowing for the implementation of an aperture distribution in the H-plane of the aperture. A top view of the complete fixed beam antenna array showing the different elements of the antenna is depicted in Fig. 7.5.

Fig. 7.5 Transparent sketch of the fixed beam antenna array on DuPont 943

In order to prevent a possible de-lamination of the ceramic tape off the Au-paste used to process the ground plane, metal-free areas have been patterned in that same ground plane. These metal-free areas allow for ceramic-to-ceramic contact regions. They are placed 800 μm (approx. one-quarter wavelength) away from the radiating patches, where the electromagnetic field is negligible and where they do not influence the RF-behavior of the antenna. The antenna has been manufactured by Via Electronic GmbH (Germany), whose design rules for both DuPont 951 and 943 LTCC green tapes are summarized in [6]. The RF-interface is achieved with a mini-SMP connector manufactured by Rosenberger Hochfrequenztechnik GmbH & Co. KG (Germany). The connector designed for operation up to 40 GHz is directly soldered on a connector footprint patterned on the backside of the antenna. The footprint is connected to the buried microstrip line and to the ground plane using vias processed in LTCC. A photograph of the antenna is given in Fig. 7.6. 7.3.1.2 Characterisation and Measurements The antenna has been measured in the anechoic chamber at the University of Ulm for its far field radiation pattern at 35 GHz. The H- and E-plane far field radiation characteristics of the fixed beam antenna array are plotted in Fig. 7.7 and Fig. 7.8,

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Fig. 7.6 Photograph of the Ka-band fixed beam antenna array on DuPont 943; front view (left) and back view (right)

Fig. 7.7 H-plane far field pattern of the fixed beam antenna array on DuPont 943 at 35 GHz

respectively. The measured and simulated return loss of the antenna is plotted in Fig. 7.9. Figures 7.7, 7.8, and 7.9 show good agreement between measurements and simulations. The –3 dB beamwidth is 26◦ and 37◦ in the H- and E-planes, respectively. The side lobe level is –13 dB in the H-plane and –16.8 dB in the E-plane. In the H-plane, the antenna is strictly symmetric and the slight 3◦ off-axis angle observed between simulation and measurement is believed to be due to an inaccuracy in

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Fig. 7.8 E-plane far field pattern of the fixed beam antenna array on DuPont 943 at 35 GHz

Fig. 7.9 Return loss of the fixed beam antenna on DuPont 943

the positioning of the antenna. This inaccuracy is similar to the one observed in the E-plane (4.5◦ ). The gain of the antenna has been measured at 13.4 dBi. Using the directivity of the antenna determined experimentally at 15.27 dBi, this value of the antenna gain corresponds to a radiation efficiency of 65%. Since the antenna is intended for integration on top of a 3D highly integrated LTCC front-end, it is important to assess its behavior over a temperature range, in which the complete module is susceptible to operate. The temperature range, limited by the measurement setup, is chosen between room temperature and approximately 130◦ C. The matching properties of the antenna, matching frequency and return loss,

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Fig. 7.10 Evolution of the matching frequency and return loss of the fixed beam antenna over temperature

extracted from the measurement of the return loss over temperature are summarized in Fig. 7.10. A first conclusion that can be drawn from the experiment is that the matching frequency of the antenna decreases as the temperature of the LTCC substrate increases. This drift of the matching frequency was expected and it is explained by the geometrical extension of the structures, patches and coupling slots, when the antenna is warmed up. However, the extension, quantified by the TCE (Thermal Coefficient of Extension) of the LTCC material (6 ppm/◦ C for the DuPont 943 tape), is not enough to explain the measured shift of about 0.47% over almost 100◦ C. Another phenomenon that contributes to the shift observed for the matching frequency is a change in the dielectric constant of the ceramic substrate. The evolution of the dielectric constant of the DuPont 943 material has been investigated over temperature with two different kinds of weakly coupled microwave resonators (triplate and cavity resonator) and has been measured at 96 ppm/K as the temperature increases within the above-mentioned temperature range. The increased dielectric constant occurring at high temperature results logically in a down shift of the matching frequency of the antenna. On the other hand, the plot of the return loss over temperature shows that the S11 -parameter decreases as the temperature of the DUT goes up (from –22.2 dB at 30.7◦ to –15.25 dB at 134.8◦ ). This degradation of the return loss of the antenna is due to the same mechanisms, geometrical extension and temperaturedependence of the dielectric constant, as the ones explaining the down shift of its matching frequency. 7.3.1.3 Hybrid Integration Concept for RF-MEMS Phase Shifters on Silicon In order to form a one-dimensional electrically steerable antenna, the fixed beam antenna on ceramic substrate is intended to be equipped with RF-MEMS phase

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shifters. The four phase shifters are envisioned for integration between the corporate feed network and the four antenna sub-arrays, enabling hence a beam steering in the H-plane of the aperture. The RF-MEMS technology available for the fabrication of the phase shifters is developed and processed by the Fraunhofer Institute for Silicon Technology (Germany). The phase shifters are realized in coplanar topology on 500 μmthick high-resistivity silicon wafer. In the foreseen integration concept, the silicon chips are mounted onto the LTCC substrate using flip-chip and the RF- and DC-connections are realized with Au stud-bumps that are approximately 25–30 μmhigh. The concept avoids the use of RF bond-wires for the connection of the coplanar lines on the chips and the feed network in LTCC. Stud-bumps are generally preferred to RF-bond wires for millimeter wave applications because at high frequencies, even a modest length of RF-bond wire is inductive and damages the return loss of the entire antenna. This can be overcome by placing several bond wires in parallel to reduce the inductance of the transition or by designing matching networks close to the bond wires. However, the design of wide band matching networks is a challenging task and the implementation of such networks will, in some cases, reduce the bandwidth of the antenna. In return, the use of bond wires allows for a larger mechanical freedom useful when the TCE of the materials is different as it is the case here: TCE of silicon = 3 ppm/◦ C and TCE of LTCC DuPont 943 = 6 ppm/◦ C. Bond-wires accept variations in the relative dimensions of the two connected devices, whilst stubbumps record internal stress when compensating for their different extension. This stress may lead stud-bumps to crack after a couple of warming-up and cooling-down cycles, which is of course critical for the reliability of the connections. Because of that the material used for the stud-bumps has to be chosen carefully depending on the TCE of the substrates and the dimensions of the devices to connect. Another constraint dealing with the choice of the material to use for the stud-bumps is the melting temperature. Depending on their technology, MEMS structures are generally sensitive to temperatures above 100–120◦ C when they are applied to the device over more than a given time. Because of that, the material chosen to sold the MEMS chips must have a low-enough melting temperature and the flip-chip process must be executed within a maximal duration. In order to prevent the coplanar-MEMS-bridges from touching the LTCC substrate when they are in the up-state, one-LTCC-layer-deep cavities are manufactured in LTCC, below the phase shifters. Further, the phase shifters are packaged using a 800 μm-high LTCC frame placed on top of the LTCC antenna board and on top of which a glass lid is fixed. In order to keep the temperature of the device at an acceptable level for the RF-MEMS chips whilst fixing the lid and the frame, a glue curable at high temperature cannot be used and a UV-curable glue is preferred. This packaging principle prevents the RF-MEMS phase shifters from being altered by dust and humidity but it is not hermetic and does not allow for a sawing of the chips since it is realized after the integration of the chips onto the LTCC substrate. However a major advantage of the packaging concept introduced here is that it covers all the four phase shifters with only one frame and one lid and thus takes care of the DC- and

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Fig. 7.11 Hybrid integration of the RF-MEMS phase shifters onto the ceramic antenna substrate

RF-bond wires between the silicon chips and the LTCC board. A drawing indicating the various features of the presented hybrid integration and packaging concept is depicted in Fig. 7.11. In this section a compact and planar antenna array on LTCC substrate intended for up-link spaceborne communication has been demonstrated. Further, an hybrid integration concept for silicon RF-MEMS phase shifters onto the ceramic substrate of the antenna has been presented. The successful implementation of low-loss ceramic tape as dielectric for the millimeter-wave antenna underlined the capability of modern processing techniques of LTCC to manufacture structures that are accurate enough for the design of high frequency structures up to the millimeter-wave range. On the other hand, the non-stop optimization of low-temperature ceramic materials makes possible the realization of microwave devices having honorable efficiency whilst enabling un-precedent integration densities, possibly 3D, for the complete RF front-end. In a near future, it is expected that ceramic tapes will contribute significantly to size reduction and the performance improvement mandatory for the next generation of millimeter-wave transceivers as it has already shown at lower frequency up to 10 GHz, where its benefit is already proven.

7.3.2 LTCC for 77–81 GHz Automotive Radar Systems-in-Package Guangwen Qu Unlike in e.g. the United States of America, where a 3 GHz segment at 24 GHz is provided for high-resolution pseudo-random bit sequence (PRBS) automotive radar sensors, the use of this spectral band is highly restricted in Europe (no more than

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7% of the total fleet is to be equipped with such sensors, and installation is only allowed before 2013). Work is therefore intensifying to implement solutions in the 77–81 GHz range, which is globally allocated to short range vehicular RADAR applications. GaAs and SiGe are two popular semiconductor technologies to be used in frond-end IC designs at this frequency. In general, GaAs based amplifiers demonstrate better noise performance and power handling capability, while SiGe technology is superior in low phase noise signal generation, and allows higher on-chip complexity. System-on-package (SoP) integration using multilayer low-temperature co-fired ceramic (LTCC) technology enables the combination of these two technologies together with high-Q passive devices in one compact package. An example RF transmitter combining SiGe and GaAs ICs on a LTCC substrate was designed using DuPont 943 material. The block diagram and the layout can be seen in Fig. 7.12.

Fig. 7.12 Block diagram of the example RF transmitter intended for automotive radar application

The system consists of a differential SiGe VCO connected to the LTCC substrate using bond wires, microstrip matching networks and a rat-race BALUN realized on the LTCC substrate, and two single-ended GaAs power amplifier flip-chipped onto the same substrate (Fig. 7.13). One of the amplifiers is being used as a driver. The VCO is realized with the SG25H1 Si/SiGe BiCMOS process from IHP GmbH. With 0.25 μm minimum feature size, the bipolar process features an fT = 180 GHz and a maximum frequency of oscillation fmax = 220 GHz [7]. The simplified circuit diagram is shown in Fig. 7.14. The VCO utilizes a negative resistance type oscillator core, based on the topology presented in [8]. Capacitive loading in the emitter was used to generate a negative resistance looking into the base. The base inductor completes the resonance circuit. The GaAs power amplifier utilizes the PH15 process from United Monolithic Semiconductors GmbH. It is a 0.15 μm gate length pseudomorphic high electron mobility transistor (0.15 μm P-HEMT) process which features a typical drain source break down voltage of 5.5 V. This circuit diagram is shown in Fig. 7.15. A threestage common emitter topology is used for the design. The first two stages are optimized for gain, while the last stage is optimized for output power. Radial stubs

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Fig. 7.13 Layout of the RF transmitter system-in-package (top view)

Fig. 7.14 Simplified schematic of the SiGe VCO

are used in each stage for in-band RF bypass. The series resistor-capacitor networks are used to ensure low frequency and general out-of-band stability. For RF system operating at millimeter wave frequency, interconnects between different elements have a large impact on the overall performance of the whole subsystem. While use of wire bonding is still widespread, flip chip interconnect is believed to have smaller parasitics [9]. The SiGe VCO has a buffer amplifier, therefore, it is not very sensitive to parasitic loading. Wire bonding is used here for

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Fig. 7.15 Simplified schematic of the GaAs power amplifier

interconnecting it to the LTCC carrier substrate. The GaAs ICs are flip-chipped on to LTCC substrate because here the loss introduced by wirebonding would be too high. On the other hand, the relatively low dissipated power can still be handled in flip-chip configuration. The special abilities of LTCC were leveraged to improve system performance: • The SiGe VCO is sunken into a four-layer cavity in LTCC to minimize the length of bond wires and thus associated parasitics, • Under the GaAs power amplifiers one-layer cavities are introduced to reduce capacitive loading of MMIC transmission lines by the LTCC substrate, • A printed sheet resistor is used to improve the performance of BALUN. The total substrate size is about 10.5×11.5 mm2

7.3.3 24 GHz Switched Beam Steering Array Antenna Based on RF MEMS Switch Matrix Shi Cheng A switched beam steering array antenna at 24 GHz based on conventional solid-state switches has been recently implemented where such switches represent a large part of the losses [10]. Compared to p-i-n or field-effect transistor (FET) diode switches, RF MEMS switches offer highly attractive merits, e.g. near-zero power consumption, very high isolation, low insertion loss, high linearity, and low cost [11]. Hence, this technology enables significant improvement on the performance of reconfigurable antenna systems at millimeter-wave frequencies. Using RF MEMS switches, antenna systems with a variety of reconfigurability in terms of resonance frequency, impedance bandwidth, polarization, and radiation patterns, can be realized. In this section, a beam steering array antenna concept based on RF MEMS switches is presented. The proposed concept consists of a single-pole-six-through (SPST) router (beam steering switch matrix) using RF MEMS switches (from

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Fig. 7.16 Schematic of the 24 GHz switched beam steering array antenna concept

Fraunhofer ISIT) and two traveling wave array antennas on LTCC (from VIA), cf. Fig. 7.16. In order to simplify the design procedure, the switched beam array antenna were divided into two parts and analyzed separately.

7.3.3.1 RF MEMS Switch Network The SPST router using RF MEMS switches from Fraunhofer ISIT have been designed and characterized. Figure 7.17 displays the photograph of the fabricated SPST router. Simulations were performed using Agilent ADS simulator and equivalent circuit models. Measurements on port impedance of the SPST router have been carried out to verify the numerical results. Figure 7.18 describes how the SPST router is used for steering the antenna beam. By applying control voltages on switches S2 , S4 , S5 and S6 , they are switched to the down-state. The RF input from port 1 is directed to port 2 and one of the traveling wave array antennas is fed from the left end. The other end of the antenna is connected to port 3 and terminated by a 50  load at port 4. In this case, an antenna beam tilt towards the left-hand side can be achieved, whereas an antenna

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Fig. 7.17 Photograph of the SPST router (beam steering switch matrix) fabricated by Fraunhofer ISIT

Fig. 7.18 Schematic of the SPST router when S1 , S3 , S7 and S8 are in the up-state, S2 , S4 , S5 and S6 are in the down-state

beam pointing to the right-hand side can be attained while the antenna fed in the opposite way. Simulated and measured reflection and transmission coefficients of the SPST router are demonstrated in Figs. 7.19–7.21. According to the experimental results, the SPST router exhibits an impedance bandwidth of approximately 24% and an insertion loss of 1.9 dB at 24 GHz. The performance is much better than those of commercial semiconductor switches in terms of isolation and losses at this frequency range.

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Fig. 7.19 Simulated and measured S11 of the SPST router (S1 , S3 , S7 , S8 : up-state; S2 , S4 , S5 , S6 : down-state)

Fig. 7.20 Simulated and measured S21 of the SPST router (S1 , S3 , S7 , S8 : up-state; S2 , S4 , S5 , S6 : down-state)

7.3.3.2 Travelling Wave Antennas The traveling wave array antennas on LTCC (from VIA) have been analyzed numerically and experimentally. Photographs of the fabricated 8- and 11-element array antenna samples are shown in Fig. 7.22.

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Fig. 7.21 Simulated and measured S22 of the SPST router (S1 , S3 , S7 , S8 : up-state; S2 , S4 , S5 , S6 : down-state)

Full-wave simulations were performed using Ansoft HFSS. For verification, port impedance and radiation characteristics were characterized. Figures 7.23–7.24 present the simulated and measured reflection and transmission coefficients of the two antennas. Good agreements between the numerical and experimental results were achieved. Both antennas feature broad impedance bandwidth at 24 GHz. Experiments on the antenna radiation patterns were carried out, in which the antenna was fed by a RF probe at one end and terminated by a 50  load at the other end. Simulated and measured radiation patterns of the 8- and 11-elment traveling wave array antennas are displayed in Figs. 7.25–7.28. By combining the beams of the two antennas, an overall coverage of ± 38◦ in E-plane can be achieved with an average gain of 10 dBi at 24 GHz. While in the H-plane, either antenna exhibits broad beam coverage. Ripples can be found in the measured radiation patterns as a result of reflections from the probe holder.

7.3.3.3 Heterogeneous Integration Using LTCC As shown in the measurements, both the RF MEMS based beam switching matrix and traveling wave array antennas feature good RF performance. Hence, the identical designs would be applied to the final 24 GHz switched beam steering array antenna module with minor adaption for the packaging. A schematic of the packaging concept is depicted in Fig. 7.29 where the SPST router chip is flip-chip bonded to the LTCC part using thermal compression bonding. The RF MEMS chip is sealed by a LTCC frame and then a glass lid. The connections for the control voltages of

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a

b

Fig. 7.22 Photographs of the 8-(left) and 11-(right) element travelling wave array antennas on LTCC

the RF MEMS switches are distributed on the top metal layer of LTCC and isolated from the array antennas at the bottom metal layer by a large ground plane. The LTCC part of the 24 GHz switched beam steering array antenna has been fabricated, cf. Fig. 7.30. The final test on the complete beam steering array antenna integrated with RF MEMS switch matrix will be carried out in the near future.

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Fig. 7.23 Simulated and measured S11 and S21 of the 8-element travelling wave array antenna

Fig. 7.24 Simulated and measured S11 and S21 of the 11-element travelling wave array antenna

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Fig. 7.25 Simulated and measured E-plane radiation patterns of the 8-element travelling wave array antenna at 24 GHz

Fig. 7.26 Simulated and measured H-plane radiation patterns of the 8-element travelling wave array antenna at 24 GHz

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Fig. 7.27 Simulated and measured E-plane radiation patterns of the 11-element travelling wave array antenna at 24 GHz

Fig. 7.28 Simulated and measured H-plane radiation patterns of the 11-element travelling wave array antenna at 24 GHz

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Fig. 7.29 Schematic of the packaged 24 GHz switched beam steering array antenna

Fig. 7.30 Photograph of the LTCC chip for 24 GHz switched beam steering array antenna

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7.4 RF-MEMS for Radar and Telecom Applications Afshin Ziaei The development of multifunction systems in airborne, ground and naval systems implies higher bit rates and dynamic ranges. However, these systems will still have to face the same critical issues in terms of volume. Using MEMS in radar and telecom systems would allow a step forward in miniaturization thanks to their high potentialities of integration, allowing a higher density of elements and therefore a higher capacity of the overall systems. This section starts with a presentation of the Radar and telecom applications aimed at Thales in which RF-MEMS will have a crucial role to play, as well as the benefit earned thanks to these components. Then, the actual design and fabrication activities and the research routes followed at Thales to improve in particular the power handling of the RF-MEMS and their integration into systems are reviewed. Finally, a focus is made on RF-MEMS components developed for 35-GHz applications in the framework of the FP6 project RF-PLATFORM. Antennas for radar applications are heading towards multi-beam techniques, which combine reconfigurability and simultaneous operations ability. RF-MEMS technology and devices offer new possibilities for improved performances and miniaturization for radar Transmitter/Receiver (T/R) modules. Functions like RF switching and phase shifting can be realized with RF-MEMS components and systems. They can be inserted in the radar front end in replacement of the antenna matching circuit and the circulators. They also provide new solutions for phase shifters in reflectors array antennas, tunable delay of a beam forming network, etc. In telecommunication networks, RF switches are key parts for realising the following sub-functions: • Transmit/receive switching, band switching (handset phones. . .); • Phase shifters in electronic beam steering antennas (satellite antennas, airborne radar, car antennas tracking satellites such as INMARSAT ones); • Switching matrix to provide redundancy capabilities for critical functions (satellite antennas); • Tunable filtering (VCO, . . .) Today, MEMS technology introduction in the field of microwave presents a considerable interest for circuit designers, because it allows the realisation of switches with electrostatic command. They offer a good alternative to other types of switches currently used as can be seen from Table 7.1. Although switching time is higher for RF-MEMS switches (∼1 μs), which slightly restrains application fields, they display improved characteristics compared to conventional switches:

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PIN diode

GaAs FET

RF MEMS

Loss (1–100 GHz)(dB) Isolation (1–10 GHz) Isolation (10–40 GHz) Power consumption (mW) Voltage (V) Current (mA) Switching time Serial resistance () Typical size (mm2 )

0.3–1.2 High Medium 5–100 3–5 3–20 1–100 ns 2–4 0.2

0.4–2.5 Medium Low 0.05–0.1 3–5 0 1–100 ns 4–6 0.2

0.05–0.2 Very high Very high 0.05–0.1 10–80 0 1–300 μs 0.5–2 0.2

• Cost and size are similar to those based on PIN diodes or FET. • Insertion losses are very low compared to diodes or FET devices, and compete with ferrite. • Current consumption is negligible For low cost antennas, the trend in network architecture is to introduce RF switches between radiating elements and power amplifiers, leading to a class of RFswitches which have to support RF electrical power ranging from 1 to 10 W. T/R switches for handsets also support between 1 and 2 W RF power, leading to significant RF currents when compared to the MEMS microscopic size, which could damage the device. Another application lies in wireless communication systems for the next generation market (3G, UMTS and further). In cell phones MEMS devices may replace a lot of components. Low power switches currently developed in various European and US projects are very attractive, even if they are not yet commercially available and, all the more, are not integrated into any system. But they still collide with technological obstacles when submitted to significant RF power (>30 dBm), leading to dramatic reliability failures. For high power switches (> 30 dBm), thermal and electrical impacts lead to specific design and packaging for performance and reliability purposes.

7.4.1 Research Activities and Trends on RF-MEMS Switches 7.4.1.1 High Performance RF-MEMS Switches on Silicon Using High-k Dielectric Material The core competence of Thales Research and Technology in the field of RF-MEMS is to design and fabricate switches to be further implemented in their systems and equipment. Surface micromachining technologies are used to fabricate series or shunt, capacitive or ohmic switches, typically on Silicon substrates (see Figs. 7.31

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Fig. 7.31 Series MEMS switch on Silicon substrate

Fig. 7.32 SEM pictures of capacitive shunt switch

and 7.32), but also on glass substrates for low cost applications and GaN based buffers for high power applications. The design and fabrication process are optimized to maximize the RF performances from 1 to 40 GHz, according to the aimed application. For instance, the use of a high dielectric constant material such as PZT ( > 150) to maintain an 0.2 μm thick capacitive layer has allowed realisation of a high capacitance ratio (Cr = 400) capacitive shunt switch with very high isolation in down-state (< –30 dB from 5 to 37 GHz) and a very low insertion loss (> –0.3 dB), as presented in Figs. 7.33 and 7.34.

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Fig. 7.33 Isolation of a PZT-based shunt switch in down-state

Fig. 7.34 Insertion loss of a PZT-based shunt switch in up- state

The switching time of this RF-MEMS switch has been measured to 4 μs for an actuation voltage of 30 V. The life-time of a similar PZT-based shunt component has been measured to 1010 cycles on a cold switching test bench under 37 dBm of input power in X-band. 7.4.1.2 Integration of RF-MEMS in Functional Devices Once the design and fabrication processes of elementary switches are optimized for aimed applications, they are integrated in functional devices such as SPDT or SP8T (for switched arrays of capacitances or filters). Figs. 7.35 and 7.36 shows a 0-level packaged SP8T with a glued glass cap. The insertion loss on each port of this SP8T

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Fig. 7.35 SPDT made of 2 series MEMS switches for S-band applications

Fig. 7.36 SP8T using 14 shunt MEMS switches for X-Band applications

at 10 GHz decreases from –0,4 to –0,8 dB and the isolation increases from –50 to –40 dB after the addition of the packaging. SPDT based on series RF-MEMS switches have been specifically designed for their integration into LTCC 3-bit phase shifters in S-Band active phased array antenna (Fig. 7.37). The low insertion losses and the good power handling (2 W) of these components have allowed their insertion on each of the active channels of the antenna. Multilayer ceramic materials are well known and frequently used for applications where packaging, heat dissipation aspects, RF behaviour and high integration are requested. In the LTCC substrate used here the combination of all these demands was the real challenge. The most innovative topic was to find out how it would be possible to integrate the capacitive and inductive structures for the R-L-C networks of several 3-bit-shifters on a small module with minimal

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a

b

c

Fig. 7.37 LTCC 3-bit phase shifters for S-band phased array antenna

size and integrated MEMS switch chips. Their dice are placed in cavities to wire them wave-guide-friendly on top and with good heat distribution opportunities on bottom. 7.4.1.3 Monothically Integrated GaN-Based RF-MEMS Switches for High Power Handling The aimed operational conditions for the Radar applications require more and more power handling with high integration in order to achieve compact and powerful T/R modules using GaN technologies at high frequencies (typically X-Band). That’s why Thales puts actually lots of efforts on the realisation of monothically integrated T/R module in which RF-MEMS switches are built on the same GaN substrate as MMICs such as High Power Amplifiers. This activty is under investigation. The fabrication processes have been adapted to be compatible with the the anisotropic etching of GaN, AlGaN based materials. Vertical profile, smooth surface quality, low roughness, reproducibility and homogeneity are crucial criteria for the successful growth of a high quality GaN based MEMS (see Figs. 7.38 and 7.39).

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Fig. 7.38 Mesa etching of GaN, AlGaN layers on HR Silicon substrates

Fig. 7.39 Capacitive shunt MEMS switch grown on GaN/AlGaN epilayers, after the release of the membrane, which is one of the most critical steps of MEMS growth

In the monolithic integration of the MEMS with high power active components such as HEMT, strong constraints have to be taken into account. On one hand, the release of the membrane must be the last step because it can be easily damaged once released. On the other hand, the high temperature annealing (900◦ C) necessary for the deposition of drain and source electrodes of the transistor are incompatible with the MEMS process. Consequently, preliminary passivation of the HEMT structure is required before the MEMS fabrication.

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7.4.1.4 35-GHz RF-MEMS Switches in the Framework of RF-PLATFORM Thales’ role in the RF-PLATEFORM project was the design, the realisation and the characterization of a 35 GHz RF-MEMS Switch in order to obtain a low-cost active antenna module for communication links at 35 GHz. The aim for such a switch was to have isolation greater than 15 dB and insertion losses lower than 0.3 dB. The design of the switches have been made on a high resistivity Silicon substrate with a SiO2 top layer for greater RF performances at high frequencies. The RF-MEMS Switches have been designed for both the series and the shunt types, where the switching principle is shown in Fig. 7.40.

Fig. 7.40 Shunt type switch and Series type switch

The goals have been reached for the design of the shunt and series type switches as their simulated performances are slightly better than the initial aim. So far the power handling of these switch has been limited to power up to 2 W due to the high frequency of work of these devices. Thus the next aim for these devices will be to have a greater power handling and reach powers up to 5 W at 35 GHz so they can be used in high speed high data-rate communication devices, antenna and radars. They are arranged to be assembled in ceramic multifunctional packages in order to achieve the required system solution as already shown on other parts. Acknowledgments I would like to thank all colleaques in VIA electronic and the partners of the international project team RF-PLATFORM for the excellent cooperation. A special thank to the European Commission for the support of the project work in the 6th framework program, project number 027468 RF-Platform. List of Abbreviations (in the order of appearance) LTCC RF PCB NRE CPW RF-MEMS

Low Temperature Co-fired Ceramics Radio Frequency(ies) Printed circuit board Non-recurring engineering Coplanar waveguide Radio Frequency-Micro ElectroMechanical System

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Ka TCE DUT DC UV W PZT

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Kurz above (from german) =27 to 40 GHz Thermal Coefficient of Expansion Device Under Test Direct Curent Ultra Violet Watt Lead Zirconate Titanate

References 1. Y. Imanaka, “Multilayered low temperature cofired ceramics ((LTCC) technology”, Springer 2005, ISBN 0-387-23130–7 2. C. Block et al., “LTCC technology for system-in-package solutions”, SiRF 2006, pp. 236 ff. 3. G. E. Oliver, “Designing with LTCC”, Advanced packaging 04/2007 4. DuPontTM 943 Design Kit, Design tools for the DuPontTM 943 low loss green tape material system, DuPont microcircuit materials 2004 5. T. Bartnitzek et al., “Ceramic systems-in-package for RF and microwave”, Proceedings of IMAPS ATW RF&Microwave, San Diego, September 16–18 2008 6. VIA electronic, Design rules, www.via-electronic.de, 2008 7. B. Heinemann, H. Ruecker, R. Barth et al. (2002). Novel collector design for high-speed SiGe:C HBTs. IEEE IEDM Tech Dig. Doi: 10.1109/IEDM.2002.1175953. 8. Hao li, Rein, H.-M., Suttorp, T., Bock, J. (2004). “Fully integrated SiGe VCOs with powerful output buffer for 77-GHz automotive Radar systems and applications around 100 GHz,” IEEE J. Solid-State Cir. Doi: 10.1109/JSSC.2004.833552. 9. Krems, Th., Haydl, W., Massler, H.,Ruediger, J (1996). “Millimeter-wave performance of chip interconnections using wire bonding and flip chip,” IEEE Intern. Microw. Symposium MTT-S. Doi: 10.1109/MWSYM.1996.508504. 10. P. Hallbjörner, M. Bergstrom, M. Boman, P., Lindberg, E. Öjefors, and A. Rydberg, “Millimetre-wave switched beam antenna using multiple travelling-wave patch arrays,” IEE Proc.-Microw. Antennas Propag., vol. 152, no. 6, pp. 551–555, December 2005. 11. G. M. Rebeiz, RF MEMS: Theory, design and technology. New York: Wiley, 2003. 12. Y.S. Bang et al., “Fabrication and characterization of RF MEMS package based on LTCC lid structure and AuSn eutectic bonding, Eurosensors, Lyon FR, June 2007 13. M. Reppel, Electromagnetic analysis of LTCC high frequency devices, Microwave Engineering Europe, July 2003, pp. 25–30 14. http://www.crc.gc.ca/en/html/crc/home/mediazone/eye_on_tech/2008/issue8/finland (VTTCRC)

Chapter 8

Low-Temperature Cofired-Ceramic Laminate Waveguides for mmWave Applications Jerry Aguirre

Abstract A critical component in mm-wave applications is the electromagnetic interconnect between devices. At mm-wave frequencies it is necessary to consider reducing the losses arising from that of using conventional transmission lines such as stripline and microstrip. An interconnect that offers comparatively lower loss connections at mm-wave frequencies is the laminate waveguide (LWG) constructed in low-temperature cofired ceramic (LTCC) technology. The LWG has superior loss characteristics as compared to stripline. The LWG, which propagates a dominant TE10 wave mode, approximates a dielectrically filled rectangular waveguide where the top and bottom walls are pattern printing and the sidewalls of the waveguide are tightly spaced via fences.

8.1 Introduction There are many applications operating in the mmWave (millimeter-wave) bands such as targeting and tracking radars, radiometers, automotive long-range radars, and more recently in the emerging 60 GHz wireless applications [1]. A critical component to consider in these mmWave applications is the electromagnetic interconnect between devices sharing a common substrate. A particular challenge in designing these mmWave interconnects is minimizing the insertion loss and reducing, or eliminating altogether, the electromagnetic interference (EMI) arising from unintended radiation from the interconnects. Higher losses in the interconnects between components can lead to higher noise floors in the system and hence lower overall system performance. At high frequencies, typical feature sizes become comparable to a significant fraction of a wavelength. The electrical dimension of these structures can lead to unintended radiation and potentially have a severe impact

J. Aguirre (B) Kyocera America, Inc., San Diego, CA 92123, USA e-mail: [email protected]

K. Kuang et al. (eds.), RF and Microwave Microelectronics Packaging, C Springer Science+Business Media, LLC 2010 DOI 10.1007/978-1-4419-0984-8_8, 

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on the operation of the device, or nearby electronic systems. These electromagnetic compatibility (EMC) issues can render a system inoperable or in violation of FCC regulations in certain environments. At mmWave frequencies it is thus necessary to consider a transmission structure that minimizes the insertion losses and is electromagnetically shielded from the surrounding structures. An interconnect that offers low-insertion-loss connections at mmWave frequencies is the laminate waveguide (LWG) [2], also referred to as a “substrate integrated waveguide” (SIW) [3, 4]. In addition to having desirable low-loss characteristics, the LWG also has excellent electromagnetic shielding properties because of its embedded structure. In this chapter we discuss laminated waveguides (LWGs) constructed from low-temperature co-fired ceramic (LTCC). The LTCC material technology has several attractive qualities. It has stable electrical and mechanical properties over temperature as compared to organic substrates, and the higher dielectric constant of many of the LTCCs naturally lends them to the miniaturization of passive microwave components and sub-components. One particular component utilizing the LWG is the feed network and radiating elements of antenna arrays [5–11]. The extreme pattern printing and via placement accuracy (in LTCC volume production), critical for coupling and phase considerations, removes any potential post-manufacture tuning. In addition, LTCC is an order of magnitude lower in weight than air-filled rectangular waveguide systems, which has an important impact on gimbaled systems for mechanically scanned arrays. The first part of this chapter provides a brief description of the LWG. After this description, a short review of electromagnetic wave propagation in a rectangular waveguide (RWG) is provided as background for the LWG. Depending on the details of the LWG structure, the dominant propagation mode, TE10, in an LWG is the same as that of the RWG propagation [4]. The essential waveguide theory is presented; however there are other comprehensive sources available on the fundamental analysis of rectangular waveguide structures [11, 12]. In the subsequent sections of this chapter, the LWG will be investigated and characterized numerically. The full-wave electromagnetic field solver, CST MWSTM is used to determine the insertion loss and isolation of LWGs constructed with various pitches. These results are also compare to results computed for the stripline transmission line. The goal of this chapter is to help the practicing engineer address the issues in material and process tradeoffs arising when considering interconnects on a common substrate at mmWave frequencies with regards to insertion loss and isolation between interconnects. Several numerical simulations are provided to weigh and tradeoff the benefits between using an LTCC laminated waveguide or the commonly used stripline in the same material set.

8.2 The Laminated Waveguide The LWG is essentially an approximation to the dielectrically loaded RWG as can be seen in Fig. 8.1. The LWG approximates the dielectrically filled waveguide by the fabrication of via fences for the conductive side walls and solid printed planes

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Fig. 8.1 A single LTCC laminated waveguide

for the top and bottom walls. The electromagnetic energy is guided between the via fences and top and bottom ground planes. The via size and pitch in the via fences must be sufficiently small, as compared to a guide wavelength, to meet the stringent requirements for insertion loss and isolation for devices in mmWave applications. Also, to prevent parallel plate mode excitation at transitions from LWG-to-LWG, the vias are connected by ground strips [3]. Without loss of generality, for the numerical simulations in this chapter we will only consider Ferro A6MTM in our case studies. The reason for this is that this material is well characterized up to 94 GHz, and has been found to have a stable dielectric constant and loss tangent across the mmWave bands. In this chapter the insertion loss of an LWG is characterized for dominant mode propagation in the U, V, E, W, and F bands. The insertion losses of the LWG are significantly lower as compared to stripline losses. For the LWG, the near-end and far-end isolation between two parallel LWGs is presented for typical and advanced manufacturing capabilities.

8.3 Transitions to a LWG Coupling energy to the LWG is of course a critical element in the utilization of an LWG for any application. There are several methods for coupling energy to an LWG that are dictated by the performance desired and the space and volume requirements of the system design parameters. A straightforward approach for coupling energy to an LWG is directly connecting an RWG to a slot opening in a ground plane of the LWG [10, 13]. Figure 8.2a illustrates this transition-type from air-filled metallic waveguide to an LWG. The top metallization of the LWG has a slot opening over which an air filled waveguide interfaces. Through optimization and interior matching circuits, the energy from the RWG is coupled and guided along the LWG as shown in the simulation in Fig. 8.2b. The LWG can also be excited by a via probe which is in turn connected to a coaxial cable [8] as illustrated in Fig. 8.3a. Instead of a coaxial interface to the via probe,

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a

b

Fig. 8.2 (a) A RWG-to-LWG transition with matching circuits, (b) Field simulation of energy coupling from RWG to LWG

a

b

Fig. 8.3 (a) Coaxial feed to LWG concept, (b) coplanar waveguide to LWG concept

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a microstrip or coplanar waveguide launch can be connected to the via exciting the LWG [14] as illustrated in Fig. 8.3b. Optimization of the probe location and specific geometry values are found through full-wave solver optimization techniques specific to the bandwidth and application.

8.4 Rectangular Waveguide Theory A rectangular waveguide is essentially a hollow, or dielectrically filled pipe having a rectangular cross section as shown in Fig. 8.4.

a

b

Fig. 8.4 (a) Rectangular waveguide and (b) cross section

Energy propagation through a waveguide is described by Maxwell’s equations. Faraday’s Law and Ampere’s Law are written in point form assuming a sinusoidal steady state variation in the frequency domain as below. = −jωμ H ∇ ×E = jωε E ∇ ×H

(8.1)

These equations illustrate how the electric field, E, is coupled with the magnetic field, H. Consider the rectangular waveguide geometry shown in Fig. 8.4b. The top and bottom walls are located at y=0, and y=b. The side walls are located x=0, and x=a. We assume that the energy propagates in the negative z-direction, which in this figure is into the paper. The fields are time varying as exp(-iωt) and the electromagnetic field at one point differs from another point by a phase difference hence we can write the general form of the electric fields and magnetic fields as the e(x,y,z)∗exp(-iβt) and h(x,y,z) exp(-iβt), where β is the propagation constant. For the purposes of the background for this chapter we will only consider the lowest order mode in the RWG and the LWG. It is well known that the lowest order mode in a rectangular waveguide is transverse electromagnetic (TE) with the electric field in the direction of propagation being equal to zero. From 1 we can derive the following

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Hx =

−jβ ∂Hz kc2 ∂x

Hy =

−jβ ∂Hz kc2 ∂y

Ex =

−jωμ ∂Hz kc2 ∂y

Ey =

−jωμ ∂Hz kc2 ∂x

(8.2)

To solve for the electric and magnetic fields in Equation 2, the two-dimensional wave equation for Hz must be solved first ∇t2 Hz (x, y) + kc2 Hz (x, y) = 0

(8.3)

where kc is referred to as the cutoff wave number. It is a straightforward approach to apply the method of separation of variables to solve the wave equation (3)and use the relations in Equation 2 to find Ex =

−jωμ ky (A cos kx x + B sin kx x)( − C cos ky y + D sin ky y) kc2

Ex =

−jωμ kx ( − A cos kx x + B sin kx x)( − C cos ky y + D sin ky y) kc2

(8.4)

where kc2 = kx2 +ky2 . To solve for the constants in (4), we must examine the boundary conditions of the electric field inside the waveguide. For this discussion we will assume that the waveguide is a perfectly conducting electric material. Thus from basic electromagnetic theory we know that the tangential electric field components at the waveguide walls must be zero. Or, Ex (x, y) = 0 at y = 0, b Ey (x, y) = 0 at x = 0, a

(8.5)

It follows that the solution for Hz is Hz (x, y, z) = Cmn cos

mπx nπ y −jβz cos e a b

and the solution for the transverse field components are

(8.6)

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jωμnπ mπ x nπ y −jβz Cmn cos sin e a b kc2 b jωμmπ mπ x nπ y −jβz Cmn sin Ey = cos e 2 a b kc a jβmπ mπ x nπ y −jβz Hx = 2 Cmn sin cos e a b kc a

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Ex =

Hy =

jβnπ C cos mπx a kc2 b mn

(8.7)

sin nπb y e−jβz

where the propagation constant is    mπ 2  nπ 2 2 2 − β = k − kc = k2 − a b

(8.8)

It can be seen from Equation 7 that the magnitude of the electric field distribution is sinusoidal as illustrated by Fig. 8.5 Fig. 8.5 The sinusoidal distribution of the magnitude of the electric field inside a rectangular waveguide

Figure 8.6 is a full-wave electromagnetic visualization of the electric and magnetic field of a wave propagating down a rectangular waveguide for the lowest order mode, TE10 . From Equation 7 and 8 we note that k > kc

(8.9)

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Fig. 8.6 The electric and magnetic fields inside a rectangular waveguide

for propagating modes. Up to the cutoff frequency, no energy can propagate in the RWG. It can thus be stated that the RWG is a high pass filter, which can be intuitively confirmed by taking an unloaded waveguide and noting that one can observe light propagate from one end of the waveguide to the other end. For the lowest order mode, the cutoff frequency is determined by the longest dimension of the cross section of the waveguide fc10 =

1 √ 2a με

(8.10)

To illustrate the cutoff frequency characteristic, Fig. 8.7 shows a full-wave simulation of an RWG operating in the U-band (40–60 GHz) range. The cutoff frequency for this band is 31.4 GHz, below which there is theoretically no propagation. In Fig. 8.7, the insertion loss and return loss are generated for a dielectrically loaded waveguide, filled with Ferro A6m. The dielectric constant of A6M is nominally 6, and the loss tangent is nominally .002 in this band. The walls are assigned to have the finite conductivity of copper. The behavior of the S-parameters closely follows that predicted by theory. The insertion loss is large up until very close to cutoff after

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Fig. 8.7 The insertion and return loss, in dB, for a rectangular waveguide designed for U-band operation

which it approaches near 0 dB. The return loss at cutoff is large, diminishing as the waveguide operates in the frequencies for which it was designed. Below cutoff, the return loss is shown to be very small; however it would be expected to be close to 0 dB, representing a large reflection. Thus care must be taken in interpretation of numerical results for an RWG operating below cutoff. In the numerical handling of the excitation of an RWG below cutoff there is no forward or reflected wave so the definitions of characteristic impedance, reflection coefficient, transmission coefficient, and wave motion can become undefined. In the mmWave bands, the RWGs are designed to operate starting at approximately 25% above the cutoff frequency to almost twice the cutoff frequency. The wavelength in the guide is the electrical dimension that must be kept in mind when designing resonant features, or computing equal phase distances in the RWG and LWG . The guide wavelength is given by λ λg =   2 1 − λ 2a

(8.11)

This wavelength is plotted in Fig. 8.8 function of frequency normalized by the cutoff frequency. For mmWave bands, the guide wavelength varies from about 1.2

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Fig. 8.8 Guide wavelength plotted as a function of frequency normalized by cutoff frequency

times the free space wavelength at the maximum operating frequency to almost 1.6 times the free space wavelength at the minimum operating frequency.

8.5 LTCC Process In this section we briefly touch upon the LTCC process in general terms. The process details are numerous, but essentially the basics are captured in the steps illustrated in Fig. 8.9. The first step is the tape casting of the LTCC. In this stage, the material is soft and compliant making it relatively easy to cut. After tape cutting, vias and cavities are punched into the tape. The vias are filled with conductive material. Depending on the process, the conductive material can be silver, gold, or copper. The use of these high conductivity metals is one of the key attractive characteristics of the LTCC technology for use in microwave and high frequency applications. After the via fill step, patterns for trace routing are screen printed on each layer, which is subsequently stacked with other layers. The stacked layers are heated and pressed together under tremendous force – this is the laminating step. After lamination, the tape is diced and fired in an oven at around 850◦ C. During the firing process organic binders in the ceramic are burned out and the LTCC substrate becomes hard. Depending on the process, the substrate becomes available for assembly with devices, surface mount components and metals such as lids and connectors.

8.6 Insertion Loss in an LTCC Laminated Waveguides An important consideration in using LWGs is the insertion loss. The insertion loss mechanisms in the LWG arise from dielectric loss, conductor loss, and leakage loss.

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Fig. 8.9 LTCC fabrication process (courtesy of Kyocera Corporation)

The leakage loss arises from the imperfect side walls of the waveguide. Consider Fig. 8.10a, which shows two parallel LWGs sharing a common via fence wall. The simulation in Fig. 8.10b shows graphically the energy in LWG 1 and LWG 2 when port 1 is excited with a TE10 wave above the cutoff frequency of the LWG. As can be seen, the majority of the energy, as visualized by the countour lines, travels from port 1 to port 2. However, some energy is leaking into the adjacent LWG2. Of course this is undesirable, but also, ultimately unpreventable. This is, of course, as we have understood regarding a multilayer ceramic process, because we cannot support a solid wall in a substrate, and thus must approximate the side walls of a rectangular waveguide by a via fence. What can be controlled to some extent is the level of leakage depending on how tight the via pitch of the via fence can be manufactured. The amount of energy coupled into this waveguide is determined by the via pitch of this via fence. Therefore, one of the first questions that might arise when considering the use of an LWG is “what should the via size and pitch of my via fence be so that the LWG is a good approximation to the solid-walled RWG?”. As is usually the case in engineering decisions, the answer is that it depends on many factors. These factors can range from production issues such as alignment challenges, costs (gold

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a

b

Fig. 8.10 (a) Two parallel LWGs sharing a common via fence wall, (b) electric field contour lines in two parallel

is a filler conductor material for many LTCCs), frequency band of interest, to overall system requirements. A key determining question to answer in LWG applications is “what can be manufactured in volume production?”. Thus the insertion loss must be viewed in the context and terms of manufacturing capability and the band of interest. Based on previous work [10, 15] the author is aware that a 3 mil via on a 6 mil pitch represents the state-of-the-art. Therefore, this will be our baseline for characterizing the LWG via pitch tradeoffs. In Table 8.1, we show the typical standard, minimum, and state-of-the-art processing capabilities for vias in LTCC. Achieving the state-of-the-art via processes is a difficult manufacturing challenge. However, such capability is critical for mmWave component electrical performance. Table 8.1 Via fence design guidelines Via feature

Standard

Minimum

State of the art

Via diameter (in) Via pitch (in)

0.006 0.014

0.004 0.010

0.003 0.006

The simulations data plots in this section will provide for a quantitative tradeoff study and analysis between insertion loss and via pitch. To determine the needed processing, we examine the insertion loss as a function of via pitch. For the laminate waveguide, the curves in this section are specific for the following mmWave

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waveguide bands: U, V, E, W, and F. These bands span the frequency range from 40 to 140 GHz. As previously mentioned the material is Ferro A6M. The dimensions of the LWG are chosen to propagate the dominant mode along the channel defined by the two via walls. Table 8.2 summarizes the cross sectional dimensions of the LWG in each mmWave band. Table 8.2 LWG dimensional summary for mmWave bands Band

Fmin(GHz)

Fmax (GHz)

Fcutoff (GHz)

LWGWidth Scaled height (mil) (mil)

Discrete height (LTCC)

U V E W F

40 50 60 75 90

60 75 90 110 140

31.36 39.86 48.35 59.01 73.84

76.89 60.48 49.86 40.79 32.65

37.00 29.60 25.90 22.20 18.50

38.44 30.24 26.33 22.53 18.77

The scaled height is derived from the standard RWG dimensions for each band. However, in LTCC the tape thickness is processed in discrete thicknesses. The thinnest tape thickness for A6M is 3.7 mils. Thus this dimension of the LWG is chosen as close to the scaled height as this value allows. The width of the LWG is the spacing of the vias between the two sidewalls of an LWG. For the simulations, the permittivity of A6M is nominally εr =6.2, with a loss tangent nominally at tanδ=.002. The gold paste used in A6M is nominally 3 mOhms/square. The via design rules are chosen to be state of the art: 3 mils in diameter and the minimum pitch is 6 mils. If the laminated waveguide concept proves feasible, the appropriate via pitch used in approximating a side wall, can be chosen accordingly. The curves capture a point of diminishing returns as one continues to tighten the via pitch. Table 8.3 summarizes the 3 mil diameter via pitches considered for each mmWave band. Table 8.3 Fence via pitch options constrained by design guidelines Via pitch∗(mil) Band

λg (mil) @ Fmax

U V E W F

94 76 63 52 41

λg /6 15.70 12.64 10.58 8.65 6.75

λg /7 13.46 10.84 9.07 7.42 5.79

λg /8 11.77 9.48 7.93 6.49

λg /10

λg /12

λg /14

λg /16

9.42 7.58 6.35

7.85 6.32

6.73

5.89

8.7 U- band The U-band in waveguides is defined by convention as the mmWave frequencies from 40 to 60 GHz. The dimensions of the LWG are listed in Table 8.3. Figure

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8.11a shows the return loss for port 1 in Fig. 8.10. The via pitches considered vary from 1/6th to 1/16th of a guide wavelength at the highest frequency for the band (60 GHz). As can be noted, the return loss improves marginally for decreased via pitch, and is even quite good at the coarsest via pitch. In Fig. 8.11b, which shows the insertion loss, the impact of via pitch becomes easier to discern. The coarsest via pitch indicates significant loss, up to 2 additional dBs, compared to the tightest via pitch considered.

8.8 V-band The V-band in waveguides is defined by convention as the mmWave frequencies from 50 to 75 GHz. The dimensions of the LWG are listed in Table 8.3. Figure 8.12a shows the return loss for port 1 in Fig. 8.10. The via pitches considered vary from 1/6th to 1/12th of a guide wavelength at the highest frequency for the band (75 GHz). As noted before for the U-band case, the return loss improves marginally for decreased via pitch, and is fairly good at the coarsest via pitch. In Fig. 8.12b, the impact of via pitch on S21 is easier to discern and seen to be significant. The coarsest via pitch indicates significant loss, up to 1.5 additional dBs, compared to the tightest via pitch considered.

8.9 E-band The E-band in waveguides is defined by convention as the mmWave frequencies from 60 to 90 GHz. The dimensions of the LWG are listed in Table 8.3. Figure 8.13a shows the return loss for port 1 in Fig. 8.10. The via pitches considered vary from 1/6th to 1/10th of a guide wavelength at the highest frequency for the band (90 GHz). Again, as can be noted, the return loss improves marginally for decreased via pitch. In Fig. 8.13b, the coarsest via pitch indicates significant loss, up to 1 additional dB, compared to the tightest via pitch considered.

8.10 W-band The W-band in waveguides is defined by convention as the mmWave frequencies from 75 to 110 GHz. The dimensions of the LWG are listed in Table 8.3. Figure 8.14a shows the return loss for port 1 in Fig. 8.10. The via pitches considered vary from 1/6th to 1/8th of a guide wavelength at the highest frequency for the band (60 GHz). The W-band LWG also exhibits a marginal improvement in return loss marginally for decreased via pitch, and is even quite good at the coarsest via pitch.

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Fig. 8.11 U-band LWG (a) return loss and (b) insertion loss, dB/in, for 7 manufactureable via pitches for side-wall via fence

In Fig. 8.14b, the impact of via pitch on insertion loss is seen to be small for the considered via pitches. The coarsest via pitch indicates loss of less than an additional couple tenths of a dB/in compared to the tightest via pitch considered.

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Fig. 8.12 V-band LWG (a) return loss and (b) insertion loss, dB/in, for 5 manufactureable via pitches for side-wall via fence

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Fig. 8.13 E-band (a) return loss and (b) insertion loss, dB/in, for 4 manufactureable via pitches for side-wall via fence

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Fig. 8.14 W-band (a) return loss and (b) insertion loss, dB/in, for 3 manufactureable via pitches for side-wall via fence

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Fig. 8.15 F-band (a) return loss, and (b) insertion loss, dB/in, for two manufactureable via pitches

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8.11 F-band The F-band in waveguides is defined by convention as the mmWave frequencies from 90 to 140 GHz. The dimensions of the LWG are listed in Table 8.3. Figure 8.15a shows the return loss for port 1 in Fig. 8.10. The via pitches considered vary from 1/6th to 1/7th of a guide wavelength at the highest frequency for the band (140 GHz). As can be noted, the return loss for the F-band LWG case does not exhibit the expected improvement in return loss with decreased via pitch. However, as shown in Fig. 8.15b, the insertion loss is marginally reduced for a tighter via pitch as expected. At this frequency, the tightest via pitch, which from Table 8.3 is borderline manufactureable, introduces no significant improvement over the coarsest via pitch, which is just within the manufacturing guidelines for via pitch in A6M.

8.12 LWG-to-LWG Coupling To determine the via pitch for a desired isolation value between two parallel LWGs sharing a common via fence wall, as shown in Fig. 8.10, requires a specification of the coupling length. For the near end coupling (Port 1 to Port 3), the coupling length has minimal impact on the overall maximum value of coupled energy. This is shown by simulation in Fig. 8.16a for two parallel LWGS in W-band constructed with the tightest via pitch and having coupling lengths of 2, 4, 6, 8 and 10 guide wavelengths at the maximum frequency (110 GHz). The minimum and maximum peaks differ, but overall it can be said that the near-end coupling is near –50 dB. In Fig. 8.16b, as would be expected from fundamental microwave and signal integrity concepts, the far-end coupling has a strong dependence on the shared coupling length of the adjacent parallel LWGs. As can be seen the far-end coupling degrades from a –40 dB isolation for a coupling length of 2 guide wavelengths to less than –30 dB of isolation for a coupling length of 10 guide wavelengths.

8.13 LWG vs. Stripline As we mentioned in the beginning of this chapter, one of the primary reasons for selecting a LWG for interconnects at mmWave frequencies was the stated low insertion-loss properties. In addition to this property, good EMI and EMC characteristics are also desired. In this section we compare the LWG with the common alternative transmission line in LTCC substrates, the stripline. Although the microstrip can be designed for mmWave frequencies, since it is a surface trace, it has poor shielding properties. It is difficult to maintain isolation between adjacent microstrips, and discontinuities that naturally arise from routing of this transmission line will inevitably lead to unintended radiation with the associated EMI and EMC issues mentioned previously. Thus in many applications, the microstrip is not the

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a

b

Fig. 8.16 Comparison of cross-coupling between two parallel LWGs at W-band: (a) near-end coupling, (b) far-end coupling

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Fig. 8.17 Stripline structure with substrate thickness H, signal trace width W, and thickness, t

first transmission line of choice. The stripline, on the other hand, is a single transmission line sandwiched between two ground planes as illustrated in Fig. 8.17. The ground planes are normally connected with ground vias to establish a good common reference plane for the signal trace. Its buried structure addresses the EMC and EMI issues common in modern day electronic environments. This buried configuration has the advantage in that the stripline is completely shielded by ground and thus emits no radiation. As is well known, the stripline can be described by a characteristic impedance. This impedance is defined as the ratio of voltage to current at any point on the line for the case where the stripline has matched loading conditions. This condition is where the load, and the source impedance are the same as the characteristic impedance of the stripline. For the presented numerical simulations, it will be assumed that the striplines are designed to have a characteristic impedance of 50  which is nominal in microwave circuits. There are various methods for determining the characteristic impedance of the triplate. Typically one can find closed form equations for the characteristic impedance [16]. It is beyond the scope of this chapter to discuss the transmission line theory associated with stripline transmission lines; however the characteristic impedance for a lossless stripline is given by the following equation: Zo =

Rs 3 a bβkη



(8.12)

There are also numerous freeware and commercial impedance calculators that can be easily used to determine the characteristic impedance of a stripline. These impedance calculators, to varying degrees of accuracy, also compute the insertion loss of the transmission line as well. For our purposes we will compute the insertion loss for the stripline with CST MWS, which is the same full-wave solver used to compute the loss for the LWG. In Fig. 8.18 we compare the insertion loss for the LWG with the tightest manufacturable via pitch for the via-fence walls for the U, V, E, W, and F bands to striplines of varying heights, H. These heights are discrete based on the tape thickness of the A6M LTCC material. For the stripline losses the simulations are computed from DC to stripline cutoff frequency. This cutoff frequency is defined as the frequency at which the thickness of the stripline substrate equals a quarter wavelength. Above this frequency, the stripline structure becomes susceptible to generating propagating parallel plate modes, leading to significant leakage losses. As can be noted the LWG

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Fig. 8.18 LWG vs. stripline insertion loss comparison for A6M LTCC material

insertion loss is superior to that of the stripline at all waveguide bands and stripline substrate heights. However, a more complete comparison would include the different dispersion characteristics of the LWG and stripline. There is significantly less dispersion in the stripline as compared to the LWG, which could have important ramifications for certain applications.

8.14 Summary The LWG offers a high performance option for mmWave interconnects on LTCC substrates. Standard rectangular waveguide propagation theory forms the basis for understanding the LWG propagation characteristics. Full-wave simulations quantify the required via pitch for the via fences forming the side walls of the LWG for the U, V, E, W, and F bands with regards to manufacturing capabilities. The near-end and far-end cross-coupling can require tighter via pitches, depending on the system requirements. For parallel LWGs sharing a common side wall, the near end coupling is nearly independent of the coupling length, while for the far-end coupling, there is a strong dependence on the common wall coupling length. As compared to the

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stripline option, the LWG has superior insertion loss performance as well as having the common characteristic with the stripline of being a non-radiating waveguide system. While the stripline can propagate electromagnetic waves from DC to mmWave bands, the insertion loss for the stripline can be prohibitive for many systems. Acknowledgments The author gratefully acknowledges Dr. Billy C. Brock of Sandia National Labs, Ms. Iris Labadie of Kyocera America Inc., and Mr. Ed Graddy of Ferro Inc. for critically reviewing this chapter.

References 1. D. Liu, U. Pfeiffer, J. Grzyb, and B. Gaucher, eds. “Advanced Millimeter-Wave Technologies”, John Wiley & Sons. 2. H. Uchimura, T. Takenoshita, and M. Fujii, “Development of a Laminated Waveguide,” IEEE Transactions on Microwave Theory and Techniques, vol. 46, no. 12, pp. 2438–2443, December 1998. 3. F. Xu, and K. Wu, “Guided-Wave and Leakage Characteristics of Substrate Integrated Waveguide,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 1, pp. 66–73, January 2005. 4. D. Stephens, P.R. Young, and I.D. Robertson, “Millimeter-Wave Substrate Integrated Waveguides and Filters in Photoimageable Thick-Film Technology,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 12, pp. 3832–3838, December 2005. 5. H. Uchimura, and T. Takenoshita, “A Ceramic Planar 77 GHz Antenna Array,” 1999 IEEE MTT-S International Microwave Symposium Digest, vol. 2, pp. 453–456, June 13–19, 1999. 6. H. Uchimura, N. Shino, and K. Miyazato, “Novel Circular Polarized Antenna Array Substrates for 60 GHz-band,” IEEE MTT-S International Microwave Symposium Digest, 2005, pp. 1875–1878, June 12–17, 2005. 7. Y. Huang, K. Wu, D. Fang, and M. Ehlert, “An Integrated LTCC Millimeter-Wave Planar Array Antenna With Low-Loss Feeding Network,” IEEE Transactions on Antennas and Propagation, vol. 53, no. 3, pp. 1232–1234, March 2005. 8. M. Clenet, J. Litzenberger, D. Lee, S. Thirakoune, G.A. Morin, and Y. Antar, “Laminated Waveguide as Radiating Element for Array Applications,” IEEE Transactions on Antennas and Propagation, vol. 54, no. 5, pp. 1481–1487, May 2006. 9. J. Hirokawa, and M. Ando, “Single-Layer Feed Waveguide Consisting of Posts for Plane TEM Wave Excitation in Parallel Plates,” IEEE Transactions on Antennas and Propagation, vol. 46, no. 5, pp. 625–630, May 1998. 10. J. Aguirre, H. Pao, H. Lin, P. Garland, D. O’Neill, and K. Horton, “An LTCC 94 GHz Antenna Array” IEEE Antennas and Propagation Symposium, San Diego, 2008 11. S. Park, Y. Okajima, J. Hirokawa, and M. Ando, “A Slotted Post-Wall Waveguide Array With Interdigital Structure for 45◦ Linear and Dual Polarization,” IEEE Transactions on Antennas and Propagation, vol. 53, no. 9, pp. 2865–2871, September 2005. 12. S. Ramo, J.R. Whinnery, and T. Van Duzer. “Fields and Waves in Communication Electronics”, John Wiley and Sons. 13. Y. Huang, and K. Wu, “A Broadband Integrated LTCC Laminated Waveguide to Metallic Waveguide Transition,” IEEE MTT-S International Microwave Symposium Digest, 2003, pp. 2237–2240, 8–13 June, 2003. 14. Y. Huang, K. Wu, and M. Ehlert, “An IntegratedLTCC Laminated Waveguide-to-Microstrip Line T-Junction,” IEEE Microwave and Wireless Components Letters, vol. 13, no. 8, pp. 338– 339, August 2003. 15. P. Garland, J. Aguirre, H. Pao, H. Lin, D. O’Neill, and K. Horton, “Manufacturing Challenges for a W-band Laminated Waveguide Phased Array” IEEE Antennas and Propagation Symposium, San Diego, 2008. 16. D.M. Pozar, “Microwave Engineering”, Addisen-Wesley.

Chapter 9

LTCC Substrates for RF/MW Application Jian Yang and ZiliangWang

Abstract Low temperature co-fired ceramic (LTCC) is a very promising and continually evolving substrate technology, which has been widely used in wireless communications, automotive, military and space, medical and several other industries. Especially, it enables manufacturing components and modules with high performance up to millimeter-wave region. In our chapter, we will review LTCC fabrication processes, characteristics all of main commercially available LTCC material systems and LTCC current status and trend.

9.1 Introduction Low temperature co-fired ceramic (LTCC) is a very promising and continually evolving substrate technology, which has been widely used in wireless communications, automotive, military and space, medical and several other industries. Especially, it enables manufacturing components and modules with high performance up to millimeter-wave region. Firstly we should address the terminology: millimeter-waves are normally considered to include wavelengths from 10 to 1 mm – that is frequencies 30–300 GHz with the sub-millimeter band continuing to 1 THz. The term “low Terahertz” is increasingly being used in certain literature to represent systems down to 0.1 THz, that is 100 GHz, and so overlaps the interests of this Focus Area [1]. Typical LTCC application examples are “Point-to-Multipoint Transceiver in LTCC for 26 GHz”, “60 GHz LTCC SiP Transmitter for Wireless Terminal Applications” and “24 GHz RADAR Module for Automotive and Industrial Applications”[2–5]. All of these microwave or mm-wave modules and sub-systems have usually composed of highly-integrated monolithic millimeter-wave integrated circuits (MMICs) or even discrete transistors, and sub-unit thin-film ceramic/organic J. Yang (B) Nanjing Electronics Devices Institute , Nanjing, Jiangsu, China 210016 e-mail: [email protected]

K. Kuang et al. (eds.), RF and Microwave Microelectronics Packaging, C Springer Science+Business Media, LLC 2010 DOI 10.1007/978-1-4419-0984-8_9, 

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substrates and thick-film hybrids for power supply, biasing and clock signals, and so on. Thanks to improvements of materials, design and process capability in LTCC technology during the past ten year, various state-of-the-art packaging concepts and required functional units have been tested and found their respective structures or interfaces on LTCC substrate, making it a mature and versatile platform to build a system in package (SiP). Here, SiP can be consider as a full functional system or sub-system package, which contains one or more IC chips together with other discrete or integrated optical/electrical/ micromechanical components. Illustration of typical RF/MW LTCC-SiP test coupons are presentedin Fig. 9.1. There are various other multilayered substrate manufacturing technologies, including high temperature co-fired ceramic (HTCC), deposited MCM (MCMD), advanced multilayer thick-film and laminated MCM (MCM-L), and even Liquid Crystal Polymer (LCP) which is attracting more and more attention [6, 7]. They are all candidate interconnection and packaging solutions for implementing RF and MW sub-system. However, LTCC has distinct comprehensive benefits of high packaging density by integrating passive components, low dielectric and conductor losses, reliability and stability. The following schematic drawing of Fig. 9.2 can show us some aspects of these LTCC’s enabling features, such as

Fig. 9.2 (a) Section view of the 60 GHz LTCC SiP Tx Module mentioned above; (b) possibility to integrate various passive structures, hermetic sealing, thermal management etc. in LTCC substrates [8]

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transmission line transitions (CPW-to-SL, CPW-to-CPW), either Wire-bonding or Flip-Chip approach to connect Chip to substrate, embedded resistors, capacitors and coils, hermetic sealing for harsh environment applications, thermal vias to help heat dissipating and so on. A further understanding of LTCC process will be more helpful to find the secret of LTCC’s benefits or distinct advantages over other substrate technologies in RF/MW applications.

9.2 LTCC Fabrication Process In general, LTCC fabrication process (LTCC Process) is to build a multilayered substrate by making metallization and functional structures on several single layered dielectric glass/ceramic sheets (so-called green tapes) and laminate them together and sintering in a 850–900◦ C temperature. DT microcircuits Corp. (www.dtmicrocircuits.com) provided an easy-coming flow diagram in their “Design Guidelines” as shown in Fig. 9.3 [9]. More detailed LTCC fabrication process and technical status and advancements can be obtained from thorough studying on “Design Guides” provided by LTCC material manufacturers, such as Dupont, Ferro and Hereaus (well-known three, D.F.H), and LTCC foundries which are spread all over the world are available for technical support[10–14]. For quick reference, Reinhard Kulke gave us a good description of LTCC process, as well as material electronic properties comparison between LTCC and several other substrate materials, and examples of Worldwide foundry services that listed in a table [15]. In most LTCC foundries, the first step of LTCC substrate manufacturing is green tape blanking as depicted by Fig. 9.3, as green tape in rolls is bought

Fig. 9.3 LTCC process flow diagram

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from D.F.H. However, the complete process should contain green tape preparing procedure before blanking, that is mixing and casting. In mixing, raw materials composed of organic binders and inorganic recrystallized glass and ceramic powder, and other solid or liquid additives were mixed and then ball-milled for more than 48 h or even longer to get LTCC slurry . The sufficient ball-milling ensures to get slurry a good particle distribution and certain viscosity. Then the slurry is cast under “doctor blade” to obtain certain tape thickness. During it was transferred on the belt, the slurry was heated and organic composition in liquid ran out or turned to solid. At the other end of the caster, the slurry dried to become green tape and was collected around a roller, which can be easily separated by automatic tape separating cutter to the required size. The technology of manufacturing qualified green tape suitable for RF/Microwave application and for volume production requires that the green tape material has a stable electrical and mechanical performance and that a series of paste physically and chemically matching with the tape need to be developed. It is so knowledge complicated and know-how inside that can be mastered by only a few companies. Some Japanese companies like Hitachi and Murata have their own material systems and facility to manufacture their own products for automotive, communication and other industries. They do not provide LTCC green tape or paste for others. Commercially available LTCC tapes for high-frequency applications can be bought from D.F.H. Ferro A6-S/A6-M is told to be the most suitable system for millimeter-wave application by material properties comparison, benchmark test and utilization in real module making [16–18]. Table 9.1 is part of these material data collected from the three company’s product sheets. Table 9.1 Basic characteristics of LTCC material systems

Dielectric constant Tan δ (> 1 GHz) Green thickness (μm) Fired thickness (μm) Insulation resistance (/cm) Breakdown voltage (V/μm) Color Thermal conductivity (W/mK) CTE (ppm/K 25–300◦ C) Fired density (g/cmˆ3) Flexural strength (MPa) Shrinkage: Z–axis (%) X–Y axis (%)

DuPont 951-AX

Heraeus CT2000

Ferro A6-S

7.8 0.0055 254 205 > 10ˆ12 > 1000/25 Blue 3 5.8 3.1 320 (15±0.5) (12.7±0.2)

9.1 0.0027 99 77 > 10ˆ13 > 1000/25 White N.A. 8.5 3.05 240 14 11.5

5.9 0.001 127 99 > 10ˆ14 > 5000/93 White 2 W/mK 7 2.5 > 210 27 (15.5±0.2)

The second step of via punching can be done with laser or mechanical method. In comparison, laser punch has advantages of more accurate position, better quality via shape and smaller tape distortion, while mechanical method is more efficient by capable of punching multi vias simultaneously with high speed multi-head CNC

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punch machine. Since manufacturing tolerance becomes quite sensitive to electronic performance of ultimate products in millimeter-wave region, more attention should be paid on via position accuracy. Besides of build-in machine precision, tape distortion that result from laser heat effect or mechanically stretching should be considered, especially with wafer process as large as 8 by 8 , which has bigger accumulated error than smaller wafer processes. In the third and fourth step, punched vias was filled and then routing pattern was screen printed. Via filling and screen printing is so similar in procedures that they can be done on the same machine. The main difference is that the former use a 2–3 mil thick stainless steel or brass stencil and contact working mode to press paste into vias, while the latter use a screen of nylon and stainless steel and non-contact mode to transfer design pattern onto the green tape. Figure 9.4 is the schematic chart of via-filling and screen-printing process.

(a) via filling

(b) screen printing

Fig. 9.4 Via filling and screen printing schematic chart [19]

In screen-printing process, screen is covered with an emulsion mask at which the conductor pattern is left open, therefore when the paste was pressed through the screen by rubber squeegee, the pattern was moved to the substrate. To get a good pattern, both paste and screen property and printer settings need to be properly controlled. Conductor paste is formed by mixing small particle size metal powder with solvents and glass binders. By regulating the viscosity the pattern resolution and thickness can be improved, besides the emulsion thickness of screen also have effect on pattern thickness. A so-called trampoline screen is widely adopted. It is formed by a stainless steel mesh together with a polymer mesh to prolong the life of screen while simultaneously ensure a stable pattern size. The illustration of the trampoline screen is presented in Fig. 9.4 [17]. The minimum line width and spacing was well effected by the screen mesh, wire diameter and opening (Fig. 9.5). In traditional screen printing process, by using a low cost 325 mesh screen, 150– 200 μm line widths and spacing can be made in high volume production. By using

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Fig. 9.5 Trampoline screen: (a) a sketch and (b) a realized (500 mesh, 18 μm wire diameter and 32 μm opening)

more advanced screen and printing process, a minimum 50 μm line width and spacing have been reported. In order for increasing system integration and implementing system at a higher frequency to millimeter-wave region, fine line metallization method is the key to success. Therefore, photo-imaging and etching technologies were utilized to achieve a minimum 25 μm line width and spaces, as depicted in Figs. 9.3, 9.6 [19]. The photo-imaging technique uses photosensitive thick-film paste materials and feature sizes of 25 μm and even smaller can be achieved on the top surface. However, photo-imaging for the inside layers is only possible for the DuPont 951 LTCC materials system. For other LTCC material system, such as Ferro A6-S, only post-fire photo-patternable pastes are available. Etching can also be used as conductor patterning of the outer conductor of LTCC substrates. First, metallization is placed on the surface. Secondly, metallization is

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Fig. 9.6 Fine line process: (a) Printed broadband rat-race mixer with 50 μm lines; (b) Integrated lange coupler with 23 μm line width and 25 μm gap

covered with photoresist and dried in the oven. Thirdly, a mask on which the conductor patterns are formed is placed on the photoresist and metallization. Then the mask is exposed by ultraviolet light and photoresist is etched away from the unexposed parts. Finally, the photoresist is removed. However, etching can only be used on the outer surfaces of the substrate and post-firing of metallization is required [17]. For some RF/MW modules, cavities are needed to leave room for bonding chip. Therefore, cavities are punched on needed single layers after screen printed patterns are heated and dry. After each single layer has been properly processed, they will be stacked and laminated to a green substrate. Stack and lamination is by far the second key procedure of LTCC substrate fabrication. All the single via-filled and printed green tap need to be stacked together. The machined via position, screen-printed conductor and stacking alignment error is typically about 5–10 μm and sometimes over 20 μm error are possible on as large a tape as 8 square for error accumulating. To insure good interconnections between layers, a minimum alignment error must be controlled. A widely adopted stacking system was depicted in Fig. 9.7, which usually contains an alignment table with tooling rods, and automatic vision alignment sub-system and vacuum pick -up for tape transferring [4]. Stacked green tapes will be laminated under supplier recommended lamination conditions, taking Ferro A6M as an example, which is a pressure of 3000 p.s.i., a temperature of 70◦ C and a lamination time of 5–10 min. Lamination is critical in achieving consistent green density, and hence consistent shrinkage, hermeticity and electrical performance [10]. Since lamination was carried out under such a high pressure, cavities are susceptible to deforming and even clasping. Rubber inserts are needed to maintain cavity stable in geometry. The selection of a right specification of rubber is a hard nut to crack. After Lamination, the green substrates are cut to proper size and are co-fired or sintered to “ceramic” substrates and then separated to the final size. Resistors on top of fired substrates can be laser trimmed to the design value with error ±1%

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Fig. 9.7 Stacking system

in production. If needed, etched conductors can be post-fired on the top after the common process.

9.3 Current Status and Trend To realize a successful RF/MW SiP module based on LTCC substrate technology, a design library based on mature process validation is prerequisite. It will contain a series of RF circuit functional units, e.g. filters, mixter, balun, sub-systems as antenna module, power amplifier module and front-end module, that has been successfully realized on LTCC, as well as various transmission structures and their transitions and effective interconnections on the three package level such as wirebonding of chip to LTCC substrates and BGA connection between chip or PCB motherboard to LTCC substrates. Recent research interests were covered these topics above and advancement were made just during the procedure of tackling challenges to realize these building blocks working in tens of GHz. In this section we will chose 60 GHz Data link system as a typical example and center point to spread our topics to various implement of RF/MW functions units on LTCC, since rising demand for low-cost, small-size and high-speed wireless communications devices has driven wider interest and development in integrated solutions for 60 GHz radios. The target applications are home video streaming, high speed wireless LAN, Personal Area Network (PAN), point-to-point link and so on. In fact, point-to-point wireless systems operating at 60 GHz have been used for many years for satellite-to-satellite communications. This is because of high oxygen absorption at 60 GHz (10∼15 db/km). This absorption attenuates 60 GHz signals over distance, so that signals cannot travel far beyond their intended recipient. For this reason, 60 GHz is an excellent choice for covert communications. Another consequence of oxygen absorption is that radiation from one particular 60 GHz radio link is quickly reduced to a level that will not interfere with other 60 GHz links operating in the same geographic vicinity. This reduction enables higher “frequency

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reuse”- the ability for more 60 GHz links to operate in the same geographic area than links with longer ranges [20]. From cellular phones to space qualified applications, filter is always one of the fundamental passive components that has been attracting wide interest of implementing it on LTCC substrate based packages. It is well known that microwave filters can be realized with only lumped elements such as inductors, capacitors, and resistors or only distributed elements such as waveguide sections, coaxial lines microstrip lines, and strip-lines, or mixed lumped/distributed elements, arranged in a particular configuration. Isabel Ferrer and Jan Svedin designed a coupled lines bandpass filter for use as an image rejection filter together with a 60 GHz WLAN chipset [21]. In a 2 by 2 test panel manufactured using 3.7 mil thick layers of Ferro A6S, internal Ag conductors and external Au conductors by Thales Microelectronics, a number of test circuits, filters together with resonators and patch antennas, for mm-wave applications from 30 to 110 GHz in both microstrip and stripline structure were realized. Figure 9.8 is the photo of LTCC test panel. The author’s objective was to evaluate the use of LTCC as an alternative to more expensive thin-film techniques to achieve a low line loss and the required resolution. The high resolution is made possible by use of a highly optimized screen-printing process to reach a minimum line width/gap of 2 mil and a minimum via of 4 mil. The Layout of 60 GHz Coupled lines bandpass filter, simulated and measured filter performance showed that the insertion loss is about 4 dB, which is a bit higher than simulated and the center frequency is 61 GHz, which is 1.3% higher than the design frequency. However this is considered to be in adequate agreement with the simulations considering the tolerances for relative permittivity, dimensions and shrinkage etc. Furthermore, for use as an image rejection filter for transmission of 60 GHz signals and rejection of an image at 55 GHz the achieved suppression of approximately 20 db is more than the required specification of 15 db. In designing the filter, the electromagnetic effects caused by the top conductor recess were taken into account by the author using direct full-wave simulation (Ansoft HFSS) but also by a circuit simulation methodology based on the use of effective permittivity and substrate height parameters. The transition from microstrip to CPW required for the RF pads was designed using HFSS which yield a first resonance at approximately 120 GHz. Compared to stripline/microstripline or lumped element type filters, on-package integrated cavity filters are a very attractive option for three-dimensional (3D) RF front-end modules up to the mm-wave frequency range because of their relatively high quality factor (Q). A low-loss, fully integrated 3-pole band pass filter employing a slot excitation with an open stub has been implemented by Jong-Hoon Lee and Stephane Pinel for 60 GHz WLAN narrowband (∼1 GHz) applications [22]. The 3D overview and side view are illustrated in Fig. 9.8. It exhibited an insertion loss of 2.14 dB at a center frequency of 58.7 GHz, a return loss ≥16.39 dB, over the passband and a 3 dB fractional bandwidth about 1.38% (∼0.9 GHz). It was fabricated in an LTCC 044 SiO2 –B2 O3 glass by Asahi Glass Co. The relative permittivity of the substrate is 5.4 and its loss tangent is 0.0015 at 35 GHz. The

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Fig. 9.8 LTCC 3-pole cavity band pass filter employing slot excitation with an open stub (a) 3-D overview (b) side view of the proposed filter

dielectric layer thickness per layer is 100 μm, and the metal thickness is 9 μm. The resistivity of metal (silver trace) is determined to be 2.7×10-8 ·m. The top view of the microstrip feedlines and CPW probe pads utilized to excite the embedded cavity resonator is shown in Fig. 9.9 The proposed cavity resonators are based on the theory of rectangular cavity resonators and all designs are optimized with the aid of a FEM-based full-wave simulator (HFSS).The cavity resonator is built utilizing conducting planes at horizontal walls and via fences as side walls as shown in Fig. 9.10. The size (d in Fig. 9.10) and spacing (p in Fig. 9.10) of via posts are properly chosen to prevent electromagnetic field leakage and to achieve stop-band characteristics at the desired resonant frequency, and the minimum size of vias (d (via diameter) = 130 μm in Fig. 9.10) allowed by the LTCC design rules was used, since it has been proven that smaller via sizes result in overall size reduction of the cavity.

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Based on the slot excitation employed for the feeding structure cavity-based 3D filters, Jong Hoon Lee, et al. developed a probe excitation counterpart [23] to get a relatively wide bandwidth performance (1.8%). Its low loss performance is verified through an insertion loss lower than 0.95 dB over the 3 dB pass band. Cavity resonators employing probe excitation for the feeding structure was shown in Fig. 9.11. Plus in Reference [23] an aperture-coupled patch antenna integrated with a soft surface and an underlying stacked cavity below the antenna substrate has been demonstrated on a novel LTCC composite multilayer technology with variable layer dielectric constant as a potential enhanced-performance antenna topology with a higher gain (–7.6 dB) and a significantly lower backside radiation (at least 5.1 dB) as compared to the use of soft surface only. The 3D view of the patch antenna with the soft surface and sacked cavity was shown in Fig. 9.12. On-package integrating antenna is another attractive option for LTCC sustrated technology. Among various antenna topology, microstrip and slot antennas are good candidates for LTCC design, for easy fabrication, broad bandwidth and easy integration. Kwon Kim and Stephan pinel developed a Linear taped slot antenna for mm-wave applications [24], which is consisted by 3 major parts, radiation, feeding structure, and air-cavity as shown in Fig. 9.13. The radiation part is located in 2nd layer and its shape is linear type slot. The feeding structure is a microstrip to slotline transition and no additional matching circuit is required. An air cavity is located on the bottom layers of the LTCC board and the physical size is 5×2.5 mm. The characteristics of proposed antenna are investigated by using numerical tool, HFSS and experiments. Fig. 9.14 displays the return loss performance of the antenna from 35 to 85 GHz. It can be seen that the S11 bandwidth of this antenna is 32 GHz (43–75 GHz) for VSWR 2:1. The 2D XY cut (Azimuth plane) patterns (Fig. 9.15) demonstrate that this antenna has a satisfactory end-fire pattern property throughout the whole frequency range of operation. Additionally, the gain of this antenna ranges from 4.9 dB at the edges (45 and 75 GHz) to 6.9 dB around the center frequency

Fig. 9.9 The photograph of the fabricated input/output microstrip feedlines with an open stub and CPW probe pads utilized to excite the embedded the cavity resonator

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Fig. 9.10 Cavity resonators utilizing via fences as side walls

of 60 GHz. From simulation and measurement results, it is found that the proposed antenna has a broad bandwidth (> 30 GHz) and efficient end-fire radiation pattern. To enhance the antenna gain, i.e. to focus the radiation more into a specific direction, the electrical size of the antenna has to be enlarged. Another way is to place two or more antennas with similar characteristics in an array, where antennas are in a particular geometrical formation. Antti Lammine and Jussi Saily [25]developed a planar antenna arrays consisting of 4 or 16 elements using reactive T-junction or Wilkinson power divider feed networks, in which microstripline fed aperture coupled patch (ACMPA) is used as antenna element, as shown in Fig. 9.16. It is observed from the results that maximum gain of 15.3 dB and bandwidth of 8% are achievable with a basic patch antenna element design. From the above examples, integrating passive components on LTCC substrate based package showed us a very attractive option for RF/MW applications to mmwave frequency range in terms of both miniaturization and reduction of the number of components and assembly cost. In Japan, a 60 GHz-band broadband wireless transceivers with a data rate as high as 1.5 Gbps, as well as commercial products for wireless Gigabit Ethernet links and a 1.485 Gbps HDSDI (High Definition Serial Data Interface) wireless transmission system for uncompressed HDTV has been developed, utilizing the low-cost multi-chip-module concept based on the LTCC substrate technology [26]. As depicted by a cross sectional structure of the transceiver in Fig. 9.17. As the current miniaturization and integration trends are focusing a reduction in the size and weight of the modules, interconnection sizes must scale down accordingly to accommodate the increasing number of I/Os. The role of interconnection technologies classified as chip-to-substrate, transition inside substrate, and substrate to motherboard will be more emphasized as the operation frequencies move to

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Fig. 9.11 LTCC cavity resonator employing probe excitation: (a) top view of feeding structure; (b) side view of the proposed resonator

the region of tens of GHz. Electrical design and implementation of low-loss and wideband package transitions were well discussed in Reference [27]. Main aspects of LTCC technology trend are targeting a more precise manufacturing tolerance control to which electrical performance is sensitive to mm-W region, such as methods to realize fine line wiring, e.g. gravel-offset-printing process [28] and combination of thick and thin film technology [29], small diameter via forming and filling, and so on. For high power applications, related process development for thermal management enhancement has been covered, e.g. by integrating micro-fluid channel [30]. Since LTCC process has been identified as enabling technology in realizing mmwave wireless systems for low cost, light weight, compact, high performance, highly functional. It is expected that there will be an increasing number of applications appears in our lives.

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Fig. 9.12 (a) The 3D overview; (b) top view; (c) cross-section view of a patch antenna with the soft surface and sacked cavity

References 1. J. Mosig (EPFL, CH), P. Ingvarson (Saab Space, S), P. Balling (ASC, DK), et al. “Innovative Antennas for Emerging Terrestrial & Space-Based Applications”, Summary Report Cost Action 284 Activities and Results, December 2006 2. R. Kulke, G. Mollenbeck, W. Simon, et al.“Point-to-Multipoint Transceiver in LTCC for 26 GHz”, IMAPS-Nordic, Stockholm, 2002 3. Young Chul Lee (ICU, Korea),“A Very Compact 60 GHz LTCC SiP Transmitter for Wireless Terminal Applications” [ppt], IEEE 2004 CSICS 4. R. Kulke, “LTCC @ IMST”, Nov-08, IMST Gmbh

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Fig. 9.13 Simulation schematic and fabricated antenna (a) Antenna configuration and slot antenna layout; (b) Fabricated Antenna

Fig. 9.14 Return loss of proposed antenna

5. Lai Ruizong, “Automotive Radar System” (ppt), USI 6. K. Aihara, A. Pham, D. Zeeb, et al.“Development of Multi-Layer Liquid Crystal Polymer Ka-band Receiver Modules”, (Searched by Google) 7. Dane Thompson, “Characterization and Design of Liquid Crystal Polymer (LCP) Based Multilayer RF Components and Packages [D]”, School of Electrical and Computer Engineering, Georgia Institute of Technology, May 2006.

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Fig. 9.15 Radiation pattern and the gain (XY cut: Azimuth plane)

Fig. 9.16 Schematics of the antenna element, power dividers and a planar antenna array of 16 elements

8. Selmic. “Selmic Technology Presentation”, 15 December 2005, www.selmic.com 9. DT, “LTCC Design Guidelines Chapter2-Technologies”, www.dtmicrocircuits.com 10. Ferro, “LTCC A6 System for Wireless Solutions. Materials, Specifications and Guidelines”, www.ferro.com 11. Heraeus-Circuit Materials Division, “Design Guidelines for LTCC HERATAPE CT2000 Materials System”, www.heraeus.com 12. VTT. Design Guidelines Low Temperature Co-fired Ceramic Modules, www.vtt.com 13. Scrantom, Inc. Low Temperature Co-fired Ceramic Design Guidelines (Revision: I), Sep.02, 2004 14. IMST, Low Temperature Cofired Ceramic, An Introduction and Overview. www.ltcc.de 15. Reinhard Kulke, Matthias Rittweger, Peter Uhlig, Carsten Gunner,“LTCC-Multilayer Ceramic for Wireless and Sensor Applications”, www.ltcc.de 16. R. Kulke, W. Simson, C. Gunner, etc. “RF-Benchmark up to 40 GHz for various LTCC Low Loss Tapes”, IMAPS-Nordic, Stockholm, 2002

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Fig. 9.17 Transceiver module cross sectional structure

17. Antti Lamminen,“Design of Millimetre-Wave Antennas on Low Temperature Co-fired Ceramic Substrates [Master’s thesis]”, Department of Electronical and Communication Engineering, Helsinki University of Technology, January 11, 2006. 18. Murata Manufacturing Corp, “Low Temperature Co-fired Cermic (LTCC) Multi-layer Module Boards, murata’s LTCC Technolgy”, [brochure,n20e.pdf,2008.3.26] 19. Jens Muller, Dieter Schwanke, Thomas Haas, “Design Capabilities and Microwave Performance of Thin Film on LTCC”, (Searched by Google) 20. Chandni Singh, Deepak Bhatia, Madhur Mehta, et al., “1 Gbps Wireless Data link System at 60 GHz” 21. Isabel Ferrer, Jan Svedin, “A 60 GHz Image Rejection Filter Manufactured Using a High Resolution LTCC Screen Printing Process” Microwave Conference, 2003. 33rd European 22. Jong-Hoon Lee, Stephane Pinel, John Papapolymerou, et al, “Low Loss LTCC Cavtity Filters Using System-On-Package Technology at 60 GHz”, 23. J.-H. Lee, G. DeJean, S. Sarkar, et al., “Advanced 3-D LTCC System-on-Package (SOP) Architectures for Highly Integrated Millimeter-Wave Wireless Systems”. 24. Kwon Kim, Stephan pinel, et al.,“ Linear Tapered Slot Antenna on LTCC Substrates for Millimeter-Wave Applications”, 25. Antti Lamminen, Jussi Saily,“60 GHz Microstrip Patch Antennas and Arrays on Low Temperature Co-fired Ceramic (LTCC) Substrates”[PPT], http://www.vtt.fi 26. Keiichi OHATA, Kenichi MARUHASHI, Masaharu ITO, et al., “Millimeter-Wave Broadband Transceivers”. NEC Journal of Advanced Technology, vol.2, no.3. 27. Tero Kangasvieri, Surface-Mountable LTCC-SIP Module Approach for Reliable RF and Millimetre-Wave Packaging [PhD Thesis].Acta Univ.Oul.C308,2008(A04) 28. M. Lahti, V. Lantto, “Realization of RF Band-Pass Filter in An LTCC Module Structure”, IMAPS Europe, 2000 29. Jens Muller, Dieter Schwanke, “Design Capabilities and Microwave Performance of Thin Film on LTCC”, 30. Kimmo keranen, “Photonic Module Integration Based on Silicon, Ceramic and Plastic Technologies [Thesis]”. Espoo 2008, VTT Publications 692

Chapter 10

High Thermal Dissipation Ceramics and Composite Materials for Microelectronic Packaging Juan L. Sepulveda and Lee J. Vandermark

Abstract Upcoming microwave device power requirements are increasing from 1–2 W to 100 W, in some cases resulting in waste heat flux higher than 3–5 kW/cm2 under the hot die. As operating frequency climbs from microwave to millimeter wave, the required power also increases and the device efficiency falls. Recently, the incorporation of IGBT’s built on SiC substrates packaged on Al/Diamond/Graphite heat sinks have allowed power levels reaching 50 kW used for 3-phase motor inverters. Traditionally, high thermal conductivity (TC) electrical insulator ceramics have been used to package bi-polar devices, while electrically conductive metal matrix composites (MMCs) have been used to package grounded dies such as LDMOS FETs or GaAs FETs. The TC of traditional oxide ceramics has been expanded to 325 W/mK with the introduction of advanced beryllia formulations. Diamond or cubic boron nitride (cBN) will allow attainment of TC levels as high as 1200–1300 W/mK. When these materials are integrated into advanced MMCs, the thermal performance is improved to levels approaching 500– 600 W/mK. Other carbon based compounds like single-wall carbon nanotubes have been reported with TCs reaching 3000 W/mK although no practical applications have yet been reported. MMCs such as aluminium/diamond, copper/diamond, and copper/cubic boron nitride, have been reported at 500–1000 W/mK. Traditional ceramics are compared to high performance advanced ceramics such as diamond, cubic boron nitride, carbon fiber, and carbon nano tubes. Upcoming advanced MMCs such as copper/diamond, aluminium/diamond, copper/cubic boron nitride, silicon carbide/diamond, aluminium/silicon carbide, copper/silicon carbide, and beryllium/beryllia are compared to traditional existing metallic alloys. Experimental data gathered during the last three years while developing some of these lowweight, high thermal dissipation MMCs is presented. Details of the technologies, applications, and cost considerations are provided. Packaging applications for

J.L. Sepulveda (B) Materials and Electrochemical Research, Tucson, AZ, 85706, USA e-mail: [email protected]

K. Kuang et al. (eds.), RF and Microwave Microelectronics Packaging, C Springer Science+Business Media, LLC 2010 DOI 10.1007/978-1-4419-0984-8_10, 

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both microelectronics and optoelectronics using these new materials, which are designed based on point-to-point discrete functionality to better utilize material properties and reduce cost, are included. Discussion also includes associated necessary technologies such as metallization, plating, brazing, net shaping, and machining.

10.1 Introduction The demand for increasing miniaturization of circuits and increasing circuit speed are demanding ever-increasing thermal dissipation requirements. Upcoming microwave device power requirements are increasing from 1–2 W to 100 W, in some cases resulting in waste heat flux higher than 3–5 kW/cm2 under the hot die. As the operating frequency increases from microwave to millimeter wave, the required power also increases and the device efficiency falls. It is necessary to provide a high thermally conductive package to be able to dissipate all waste energy. It is convenient to place the relative thermal performance of packaging materials in terms that reflect the thermal dissipation that might be expected in a real packaging application. The universally applied parameter to indicate thermal performance of a material is its thermal conductivity (TC). The example shown in Table 10.1 is indicative of the effect of TC on thermal dissipation, assuming the majority of the heat is dissipated through conduction to a heat sink and disregarding the contributions of convection and radiation. This assumption is appropriate when applied to a simple model for the cooling of a hot die mounted on such a heat sink. The thermal dissipations per unit area (heat fluxes) for different substrate packaging materials using the same geometry and the same boundary conditions were estimated and compared in Table 10.1. Using the classical conduction heat transfer equation under steady state conditions [Q = T/(x/kA) = T/θ where Q is heat transfer, T is temperature gradient between heat source and heat sink, x is the length of the thermal path, k is the thermal conductivity (TC), A is the cross sectional area, and θ is the thermal resistance] the heat flux Q/A is directly related to the TC of the material and a good comparative estimate can be made. The advantages of higher TC materials become very apparent. It can be concluded the higher TC materials are optimum to be used as heat sinks, heat spreaders, highly dissipating cores, and inserts for highly demanding packaging applications. The baseline conditions for Table 10.1 were taken from experimental data obtained in previous research [1]. A FET and a diode operated at power densities of 1031 and 1333 W/m2 respectively mounted on 160 W/mK Cu/W was normal operation for these devices and judged representative baseline for heat flux for this material. The heat fluxes for other materials were calculated proportionally to their respective TC’s. Packaging platforms built out of these materials, following the point-to-point design concept [2, 3], will be very appropriate for transferring high heat flux to the heat sink keeping the temperature of the hot components below the desired design

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Table 10.1 Heat flux for different packaging materials using the same geometry and under same operating conditions. (Temp. range: Ambient–400◦ C) Material

CTE (ppm/K)

TC (W/mK)

Relative∗ heat flux

Heat flux (W/cm2 )

R Kovar R Invar Alumina R Silvar-K R Silvar Al/SiC Cu/SiC AlN Cu/W Cu/W Cu/Mo R AlBeMet R E-60 Material BeO R GlidCop Cu–Cu/W FGM Cu–Cu/SiC FGM Cu Cu/diamond Al/diamond Cu/cBN Diamond

5.3 5.5 7.1 7.0 6.5 8.5 8.3 4.3 7.0 8.0 7.2 13.9 6.1 7.1 21.2 7.0 8.3 17.8 8.2 8.0 7.8 3.5

17 15 20 110 153 160 180 180 160 (BL) 200 150 210 230 285 355 320 400 400 600 500 600 1200

0.106 0.094 0.125 0.688 0.956 1.000 1.125 1.125 1.000 (BL) 1.250 0.938 1.313 1.438 1.781 2.219 2.000 2.500 2.500 3.750 3.125 3.750 7.500

110 97 129 709 986 1031 1160 1160 1031 (BL) 1289 967 1354 1483 1836 2288 2062 2578 2578 3866 3222 3866 7733

∗ Based

on relative TC

BL = baseline value

limits and with an appropriate thermal expansion match to ensure device reliability during thermal cycling. Heat dissipation density levels in excess of 7000 W/cm2 can be attained around the die bonding area (hot spot) while other materials are used in less demanding areas of the device. The heat sink material is the most important element to attain good heat dissipation and good heat spreading when in intimate contact with the active semiconductor die. The current trends in packaging are miniaturization, high performance, and lower cost. Material properties are better utilized and cost is reduced when using point-to-point discrete functionality. These packaging solutions are applicable to both microelectronics and optoelectronics where complex designs may integrate microwave and light signals in a single module [7, 8]. New technologies for plating, metallization, brazing, and machining are needed before the new material attributes can be commercially used for packaging. These new technologies will also play a very important role in the utilization of these upcoming materials for microelectronic packaging. The most commonly used composite materials for microelectronic packaging include metal matrix composites (MMCs), ceramic matrix composites (CMCs), carbon matrix composites, and carbon/carbon composites.

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10.2 Ceramics and Carbon Based Materials Ceramic materials have been used extensively for packaging microelectronic and optoelectronic devices. Properties are summarized in Table 10.2. Their heat transfer ability is characterized by phonon transmission requiring simple hexagonal crystallographic structures like those found in BeO, AlN, cBN, and diamond. In all these materials, high TC is associated with very clean structures that result in minimum phonon scattering at grain boundaries, maximizing the mean free path for the phonon transport. TEM micrographs for both BeO and AlN are shown in Figure 10.1 and Figure 10.2 respectively. Notice the absence of second phase in the microstructure of BeO, resulting in TC values around 325 W/mK, while in the case of AlN the second phase is concentrated around the triple points providing clean grain boundaries. Very high TC values are obtained for diamond and cBN, which derives from their cubic clean structure.

10.2.1 Common Packaging Ceramics Alumina ceramics have been extensively used for microelectronic packaging for more than 60 years. They provide appropriate thermal conductivity for many less demanding applications and present a very attractive price. Its high dielectric properties couple with high strength, high stability in air environments, and high resistance to corrosion and abrasion make it a prime candidate for microelectronic packaging. Several grades of varying purity are available. As the purity increases so does the thermal conductivity. Two different grades, very commonly used for microelectronic packaging, are included Table 10.2. Figure 10.3 shows the reduction of alumina thermal conductivity for increasing temperature. Alumina ceramics are typically available as net shape dry pressed parts or tape cast substrates that can be shaped by green punching or by using laser cutting after sintering. Precise dimensional control tolerance is attained for thick and thin film substrates with through-hole designs requiring small diameter holes when fabricating hybrid integrated subassemblies and resistor networks. Highly smooth alumina substrates fabricated by ceramic tape casting processing or by post sintering polishing allow for the deposition of high reliability thin film circuits. Several metalizing systems have been developed for thick film and thin film application. Throughout the years these metallization strategies have been well established and proved to be highly reliable and reproducible. They represent the standard against which newer metallized substrate materials are compared.

10.2.2 LTCC Low temperature co-fired ceramics (LTCC) are a low cost, high performance solution for ceramic packaging. LTCC is generally used as a substrate or packaging

BeO

2.85 6.3 285 1.046 33.7 345 6.7 10.6 0.0001 > 1015 1–24 4×4 in. 0.01

Property

Density (g/cc) CTE (ppm/◦ C) TC (W/mK) Specific heat (J/gK) Flex. Stren. (ksi) Modulus (GPa) Dielectric Const @ 1 MHz Dielectric Stren. (kV/mm) Loss tangent @1 MHz Vol. Resist. (-cm) Surf. Fin. (μ-in) Size Cap. Min. thickness (in)

3.28 4.3 180 0.75 27 350 10 15 0.0005 > 1013 5–32 4×4 in. 0.01

AlN 3.75 7.1 21 – 40 380 9.4 15 0.0001 > 1014 0.5–30 5×7 in. 0.01

Al2 O3 96% 3.8 7.1 25.1 – 47 390 10.2 15 0.0001 > 1014 0.5–30 5×7 in. 0.01

Al2 O3 99.5%

Table 10.2 Properties of ceramic and carbon based packaging materials

3.10 4.5 180 – 21.3 218 – – – – – – –

SiC

(continued)

2.0 max. – 1500 – – 1060 – – – 41×10–6 – – –

Graphite

10 High Thermal Dissipation Ceramics and Composite Materials 211

Diamond

3.52 1–2 1100–1800 – – – – – – – – – –

Property

Density (g/cc) CTE (ppm/◦ C) TC (W/mK) Specific heat (j/gK) Flex. Stren. (ksi) Modulus (Gpa) Dielectric Const.@1 MHz Dielectric Stren. (kV/mm) Loss tangent @1 MHz Vol. Resist. (-cm) Surf. Fin. (μ-in) Size Cap. Min. thickness (in)

3.52 3.70 1400 – – – – – – – – – –

cBN 2.0 max. – 20–1200 – – 200–700 – – – 10–4 – 7000 nm  –

Carbon fiber

Table 10.2 (continued)

0.94 max. – 3000 – – 1200–1700 – – – 3×10–8 – 1–5 nm  –

Single wall (SWNT)

Nanotubes

0.77 max. – 1500–3000 – – 1000–2000 – – – 3–10×10–8 – 2.5–6.2 nm –

Double wall (DWNT)

2.10 max. – 1500 – – 1000–3700 – – – 10–7 – 13–50 nm –

Multi wall (MWNT)

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Fig. 10.1 BeO microstructure

material. LTCC makes use of low melting point glass ceramic formulation combined with another common oxide ceramic as reinforcement to green formed as ceramic tape which typically sinters around 850◦ C. Typically the glass ceramic could contain glass frit, boron oxide, calcium boro-silicate, or a mix thereof, and the reinforcement could contain alumina, zirconia, titania, mullite, calcia, barium titanate, silica powder or a mix thereof. Most of them sinter at temperatures lower than 1000◦ C as compared to high temperature co-fired ceramic (HTCC). Several LTCC tape grades and suppliers are available in the U.S. By green-forming, green-metallizing and laminating the different layers under perfect registration, high performance, low loss, multi-layer circuits are produced for RF and microwave circuitry. Operating frequencies range from MHz to several GHz. Resistors, capacitors, inductors, and active components can be buried in the multi-layer structure to produce hybrid integrated circuits. This way, the number of required discrete components is minimized. Several metallization inks are available to build the interconnected muti-layer structure as desired. The metalized green structure is co-fired in air using conductor interconnects such as silver, copper, or

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Fig. 10.2 AlN microstructure

Fig. 10.3 Thermal conductivity of BeO compared to other packaging materials

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gold while the embedded passive elements help in miniaturizing the final module. Multiple firings are possible. Additional resistors can be printed on the surface of the fired structure for additional design flexibility.

10.2.3 High Performance Packaging Ceramics (BeO AlN) Beryllia ceramics have been successfully used during the last forty years to produce reliable packaging solutions for a wide range of commercial microelectronic packaging applications. Ceramic properties have been well defined and consistently controlled throughout production of many millions of circuits to insure high performance operation and product reliability. Many metallization options such as thin-film deposition (TiW, Au, TaN, NiCr), refractory (Mo–Mn), conventional thick-film (Au, Ag, Cu), etched thick film, direct bond copper, and additive copper metallization systems are available for packaging applications. After more than 40 years of production and after many millions of parts sold world wide, BeO packaging technology is mature and proven. Key BeO performance attributes are its high thermal conductivity, good electrical insulation, and high dielectric strength. Its CTE is a proven match for semiconductor materials such as GaAs or silicon, other ceramics such as alumina, and other metal matrix composites such as Cu/W, Cu/Mo, Al/SiC, and Be/BeO. Its dielectric constant, loss tangent and loss index are all low, which makes BeO the material of choice for high frequency applications. Health and safety concerns about the use and handling of BeO ceramics are often misunderstood. Manufacturers of competing materials tend to play on both real and perceived health and safety concerns of beryllia. The real concerns are mostly associated with the manufacturing of beryllia by the primary producers. Contrary to the deceptive message of manufacturers of competing materials, handling of beryllia ceramic in its solid form, the only form in which it is used for microwave and RF packaging applications, poses no special health risk. Beryllia ceramics are in widespread use around the world. The use of beryllia ceramic is legal in all countries. The demand for high thermal conductivity substrates to produce high power modules, RF/microwave packages, high performance MCMs and BGAs, and other devices such as diode lasers has been continuously increasing as the designed performance on these devices increases and miniaturization is applied whenever possible. Standard beryllia substrates exhibit superior thermal management performance with a consistent high thermal conductivity of 280–290 W/mK coupled with high electrical resistivity (4.5×1015 ohm-cm). Beryllia substrates as large as 12.7×17.8 cm (5×7 in.) and beryllia parts of almost any shape have been produced during the last thirty years using 99.9% pure beryllia powder [1, 2]. Applications include the production of devices using Mo/Mn or W refractory metallization systems, Cu, Ag/Pd, Au, and other thick-film metallization [3, 4], and TiW, Au, TaN, NiCr, and other thin-film metallization schemes [5, 6]. Beryllia substrates have also been used to produce beryllia-copper layered

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circuitry using direct bond copper technology [7]. These layered substrates make use of the very good electrical and thermal conductivity properties of metallic copper films and the good insulating properties and thermal conductivity of the beryllia [8]. In a more recent application, beryllia substrates have been used in combination with aluminium silicon carbide to manufacture high power IGBT for electric vehicle power management systems [9]. Beryllium-beryllia composite substrates are being used to produce high end packages for satellite based telecommunications where high thermal performance, dimensional stability, light weight, and good vibration properties are required. The thermal conductivity, k, of beryllium oxide is affected by temperature. The thermal conductivity of beryllia ceramics is compared to other commonly used electronic ceramics in Figure 10.3. Beryllia ceramics thermal conductivity is only inferior to diamond and cubic boron nitride, but at a fraction of their cost and commercially available worldwide. Beryllia offers about 30% better thermal dissipation properties than AlN in the 25–300◦ C temperature range which is common for most electronic device applications. It also provides superior performance compared to aluminium nitride or alumina at very low temperatures (0–200◦ C). This behavior is very well fitted for cryogenic and space applications. Most importantly, the thermal performance of beryllia substrates has been steadily maintained since its introduction to the market, independent of the producer or production facility. The coefficient of thermal expansion (CTE) of BeO is a good match for Al2 O3 , GaAs, Si, and MMCs such as Cu/W, Cu/Mo, Al/SiC, and Be/BeO. Values of the CTE for different temperature ranges are provided in Table 10.3. The dielectric constant of beryllia is relatively low, (6.7 ± 0.1), compared to alumina or aluminium nitride ceramics, with a low loss tangent (10–4 ). Most importantly, Figure 10.4 shows that the dielectric constant has varied very little throughout the years. This has

Fig. 10.4 BeO dielectric constant at 10 GHz. MIL-I-10 testing

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been accomplished by maintaining the purity of the ceramic and keeping accurate control of the production processes. Beryllia parts are very stable in oxygen/moisture containing environments since it is an oxide ceramic. Therefore, ceramic to metal joints and metallization coatings in general, are very strong and reliable, making beryllia ceramic a prime choice for hi-rel military and high performance applications [10]. Other mechanical properties for beryllia ceramics are provided in Table 10.3. The trend in electronics towards higher performance, lower cost and more compact systems is driving the industry toward packaging solutions with superior thermal management properties. These properties require the best thermal performing material and technologies for better device efficiencies and life. Superior performing thermal management packaging systems prove to be the most reliable components in the field. If a device (such as a power amplifier in a base station system) does not meet the specification for thermal dissipation, then the device electrical linearity is diminished. It is estimated that 90–95% of all base station electronics’ field failures are due to thermal issues. So, by lowering the junction temperature, the life of the device is extended. It has been shown that if the junction temperature is lowered by 20–30%, the power efficiency can increase by as much as 50%. Without good package thermal dissipation properties, the device can electrically degrade at an accelerated rate and lead to costly field replacements. Due R Table 10.3 Beryllia substrates properties Thermalox 995

Property

Units

Value

Thermal conductivity Fired density Color Flatness Surface finish

W/mK g/cc

Grain size Young’s modulus Shear modulus Poisson’s ratio Flexural strength Tensile strength Compressive strength Hardness Dielectric constant Dissipation factor Loss index Resistivity @500◦ C @1000◦ C CTE @100◦ C 500◦ C 1000◦ C 1500◦ C

m Psi Psi

280–290 2.85–2.87 white 0.003 < 7 tape 12–30 pressed 12–20 50·106 20·106 0.26 33,700 22,000 225,000 1240 6.64 0.0001 0.0012 7.9·109 1.3·108 6.27 7.98 9.39 10.30

“/ ” μ-inch

Psi Psi Psi Knoop 1 MHz 1 MHz 1 MHz ohm-cm ohm-cm ppm/◦ C ppm/◦ C ppm/◦ C ppm/◦ C

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to increased thermal dissipation requirements in the next generation of microwave package design calling for higher RF power dissipation, BeO packaging becomes a very attractive and feasible solution. Its attractive low dielectric constant and low loss index coupled with the availability of large volume, low cost, thin substrates enables the development of packaging solutions for very high frequency applications at an attractive cost. The current trend for integration results in power modules that operate at higher power levels and at higher frequencies. BeO provides a proven cost effective solution for these applications. Another characteristic of these applications is that the need for higher frequencies will require higher electrical current near bond interfaces, which will require less resistive interface layers. The ability to dissipate power and accomplish frequency is mandatory. Beryllia provides the ability of lowering the area and miniaturization of the device, dissipating the same power, lowering the capacitance, allowing for higher frequency. An ideal solution is found in small leadless BeO packages. For these applications, BeO provides an advantage over AlN. AlN at high frequencies will not be able to provide the expected electrical or thermal performance that can be obtained from BeO. Although less thermally conductive than diamond, beryllia ceramics are more advantageous since they are easily machined or formed to final shape, lower in cost, produced through large volume processes, and available worldwide. Metallization technologies available for BeO are well proven. Beryllia ceramics, for the past twenty years, have a proven record of excellent thermal properties, robust metallization adhesion characteristics with high temperature brazing processing, excellent solderability, and are priced competitively for the market.

10.3 Direct Bond Copper (DBC) Packaging Layered substrates that make use of the very good electrical and thermal conductivity properties of metallic copper films and the good dielectric and thermal conductivity properties of a ceramic substrate provide an excellent platform to build RF/microwave packages and high power modules. The thermal properties of two or three layered systems produced by directly bonding copper to alumina, beryllia, or aluminium nitride have been determined. Table 10.4 provides thermal conductivity values determined by the laser flash pulse diffusivity technique. It can be concluded that bonding copper to these ceramics improves their thermal performance substantially. At temperatures higher than ambient, the effect of using DBC copper films improves the thermal performance of the ceramic. As was shown in Figure 10.3, the thermal conductivity of the copper does not decrease with increasing temperature as does for most common ceramics. DBC substrates, manufactured by bonding highly conductive copper foils directly to beryllia, provide a robust technology for manufacturing high power packages. DBC provides an extremely strong, hermetic bond that can be plated or soldered. High thermal and electrical conductivities are obtained by using copper films. DBC technology is also applied to alumina, tungsten copper or

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Table 10.4 Thermal conductivity, DBC substrates Substrate (in) 0.01–0.025 0.01–0.025–0.01 0.01–0.025–0.01 0.008–0.01–0.008 0.01–0.01–0.01 0.008–0.025–0.008 0.01–0.025–0.01

Laser Flash TC Layers Cu–BeO Cu–BeO–Cu Cu–AlN–Cu Cu–Al2 O3 –Cu Cu–Al2 O3 –Cu Cu–Al2 O3 –Cu Cu–Al2 O3 –Cu

(W/mK) 336 312 174 43 57 29 33

copper-moly-copper substrates. DBC substrates are offered full face metallized, etched to conform with circuit design, or with discrete copper pads placed according to specifications for large volume applications. Applications include motor controller, power management systems for electric vehicle, telecommunication, and packaging in general. The use of direct bond copper on beryllia ceramic has allowed developing high performance integrated RF and microwave packages for bi-polar applications R ). The common foundation for these products is the proven direct bond (CuPack copper process that General Electric developed and implemented in the 1970’s. After developing strong material technology and manufacturing strengths for high R packages have significant product performance volume production, CuPack advantages while lowering end-user package cost. R packages are good to house both bipolar and FET Beryllia based CuPack (Field Effect Transistor) device designs that use silicon or gallium arsenide (GaAs) R designs are excellent vehicles for newer silicon semiconductor materials. CuPack LDMOS FET (Laterally Diffused Metal Oxide Semiconductor FET) devices and GaAs devices such as MES FET (Metal Semiconductor FET), HBT (Heterojunction Bipolar Transistor), and HEMT (High Energy Mobility Transistor) devices operating at frequencies greater than 1 GHz. Bipolar packages, such as the RF046 or RF103, shown in Figure 10.5, are constructed with pure copper leads bonded to the

R Fig. 10.5 CuPack bi-polar BeO packages

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topside of beryllia ceramic. The bottom side of the package has the option of a full copper back pad. Device performance is to 3 GHz with power dissipation to 30 watts R packages are commonly used in amplifiers and power modules that RF. CuPack are primarily used in wireless handsets, cellular/PCS base stations, cable modems, HDTV amps, TV broadcast stations, and active antennas. DBC integrally bonded packages offer several advantages. Excellent thermal performance is attained since the direct bond copper process uses an oxide bonding mechanism that does not create an added resistance layer such as those found in conventional brazed packages. In addition, the package construction utilizes highly R packages are capable of conductive copper bearing materials. As a result, CuPack dissipating from milli-watts of RF power to several hundred watts. Superior electrical performance is gained through the use of pure copper conductors that have high electrical conductivity. Package performance is excellent through 8 GHz with less than 1 dB insertion loss. Fewer and simpler processing steps utilized in the direct copper bonding process permit a low package cost. As a result of these sigR packages are nificant performance advantages, and being cost effective, CuPack fast becoming the preferred option for RF applications.

10.4 RF/MW Brazed Packages Discrete transistor packaging utilizing enhanced thermal ceramic materials has been in the industry over the past couple of decades. These silicon power transistor packages can be designed for high voltage and high current usage. With these thermal and electrical packaging characteristics, they are used for high power, high efficiency applications, at frequencies exceeding 30 GHz. Silicon small microwave transistor packages are widely used for amplifiers for their high gain and low noise properties [11]. The development of Monolithic Microwave Integrated Circuits (MMIC), which combines FET transistors, microwave circuits and resistors into a single GaAs device, strives to miniaturize, lighten and produce high reliability, low cost microwave equipment and are supported with the same basic material and package technologies requiring high thermal, electrically isolating heat spreaders as do basic high power transistors. AlN ceramic heat spreaders are available in multiple forms for these packages, depending on the application needed. A pressed form of AlN could substitute for beryllia in some RF and MW applications. Although AlN has been rumored to be the material of choice in replacing beryllia due to its assumed toxicity, there is still some drop-off in thermal performance experienced by this change, which ultimately sacrifices device performance and reliability. Consequently, AlN has found a small, reluctant market. High power, SO-8, BeO packages for RF and microwave applications are built using conventional Ni and Au plating combined with refractory metallization and brazing processes. Excellent thermal properties and solderability at competitive pricing levels are obtained by using a proven and robust metallization and brazing process.

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10.5 Thin-Film Packaging Production of high performance microwave devices using thin film metal deposition requires thin, large area substrates with a highly smooth “as fired” surface. This type of surface, which is annealed and free of microcracks, is found in beryllia substrates produced by tape casting. These substrates exhibit camber of less than 0.003 in./in. They are as large as 4×4 in, with a maximum thickness of 0.060 in. and with a surface finish of less than 7 μin. center-line average. The use of high purity beryllia powder ensures a consistent high thermal conductivity (290 W/mK) and superior performance when compared to other common substrates such as aluminium nitride or alumina. Improved yields are derived from the smoothness of the surface. Thin film metallization systems that have been successfully used in industrial applications include: TaN, TiW, NiCr, Cr, Ti, Pd, Ni, Au, and Cu. These can be combined with thick film coatings such as Au, Cu, AgPd, and Ru. Using RF diode sputtering on beryllia tape substrates and subsequent subtractive pattern processes, circuitry with less than 2.5 μm absolute tolerances with about the same degree of difficulty found in similar processes with high quality “as fired alumina” are produced. Resistors fabricated with TaN show less flaws and hot spots than resistors fabricated on polished materials. Reduction of these flaws and hot spots results in higher power handling capability. The improved surface finish and flatness specifications of the beryllia tape substrates are well suited for the typical microwave metallization schemes and downstream fabrication processes [5].

10.6 Thick-Film Packaging Characteristics of beryllium oxide that make it an excellent RF package material are its high thermal conductivity, k, and intermediate coefficient of thermal expansion, CTE, that matches gallium arsenide and silicon. This is especially important as frequencies increase because with higher frequencies, the dominant semi-conductor material is gallium arsenide (GaAs) which is more prone to hot spots than silicon, and it’s k is also significantly worse. As frequencies increase, the efficiencies of power amplifiers decreases, which also exacerbates the thermal problem. The intermediate CTE and high k of beryllia make it the ideal material to rigidly attach power devices using solder. Materials with lower CTEs have increased risk that hard-soldered devices will crack and fail at the time of mounting or during power cycling. This risk increases as device size grows. Ideally the CTE of the ceramic should be slightly higher than the semi-conductor. Beryllia and alumina both satisfy this criterion. The dielectric constant and the dissipation factor are also important properties to consider. Transmission lines and passive structures are critical components of RF modules. For many applications, lower dielectric constants are preferred

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because transmission line losses are reduced. Provided the dissipation factor is low, transmission line losses are reduced because the lower dielectric constant leads to increased conductor width. Conductor losses are proportional to conductor width, therefore wider is better. Dielectric losses are also reduced with decreasing dielectric constant. Dielectric losses are important in both transmission lines and other coupled passive structures. A secondary benefit of the lower dielectric constant is that resulting conductor geometries are greater, and are therefore more producible. An additional significant benefit with decreasing dielectric constant is that the cut-off frequency for a given substrate thickness increases with lowering dielectric constant for microstrip circuits. The cut-off frequency is the frequency above which it is not practical to use the material. A BeO substrate of a given thickness could be used at frequencies approximately 20% higher than an alumina substrate of the same thickness. Thin substrates are difficult to work with and expensive, so the higher cut-off frequency of BeO allows a thicker, more manageable material to be used. Electrical properties of BeO indicate it to be a good package material for both microwave and millimeter wave products. Thick-film lithographically etched gold metallized substrates manufactured on beryllia ceramic substrates, are well suited for high-reliability, high-density, microwave circuits. Capable of operating at frequencies beyond 44 GHz, these substrates find their application in communications and direct broadcast satellites, cellular, PCS and paging base stations, satellite up and downlinks, advanced avionics, and global positioning systems. Lines and spaces down to 0.001 in. are routinely patterned on substrates as large as 4.0×4.0 in. Most precious metal, dielectric, and resistor inks, developed by DuPont and the other major thick film ink manufacturers, for use on alumina substrates, work equally well on beryllia as they are both metal oxide ceramics. This is a major advantage over aluminium nitrite (AlN) and other more expensive alternative substrates where ink compatibility has often been a serious problem. This also allows the thick film circuit manufactures to get the economies of scale of the smaller ink inventories. Thick-film technology has also been used to manufacture MCM-Cs and BGAs using metallized transfer tape laminated over a beryllia substrate base. MCM-Cs as large as 4×2 in. making use of 18,000 vias to interconnect 10 layers of gold circuitry printed on 9 layers of low temperature cofired ceramic transfer tape and one beryllia tape substrate which acts as a highly thermally conductive base have been developed [12]. About 100 thermal vias 0.020 in., in diameter, stacked down directly to the beryllia are used to transfer heat dissipated by the hottest components. High resolution thick film gold lines, 0.002 in. wide with 0.002 in. spacing, are screen printed on the transfer tape and the beryllia substrate for interconnections. The use of commercially available beryllia substrates coupled with low temperature transfer tape technology allows the production of high performance state of the art MCM-C’s at a relatively low cost when compared to cofired hot pressed MCM-C’s produced with AlN ceramic. Ball grid arrays have also been produced using the same technology.

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10.7 Carbon Nanotubes (CNT) CNTs are among the strongest structures theoretically possible and with an axial TC approaching 3000 W/mK and conduct heat exceptionally well along their axes. Tubes are highly resistant to degradation from heat and chemicals. Many tubes show “ballistic transport” of electrons. CNTs, and DWNT in particular (Figure 10.6), are the world’s most efficient producers of field emission electrons. Various research efforts have concentrated in making composites using CNT as reinforcement. However, the enhanced thermal transmission properties of CNT have not improved the thermal transmission properties of the composite yet. CNT properties are summarized in Table 10.5 [4].

Fig. 10.6 Carbon nanotubes

10.8 Composites Several advanced MMCs formulations are under development seeking increased thermal conductivity and lower density.

10.8.1 Metal Matrix Composites As shown in Table 10.6, diamond, cubic boron nitride, and other ceramics are being used with a variety of metal matrices resulting in very high TC. Silicon carbide reinforced aluminium metal matrix composites (Al/SiC) used in combination with DBC beryllia substrates has been successfully incorporated in the design of high current IGBT module baseplates [9]. The Al/SiC MMC combines the high heat dissipation capability and low density of aluminium alloys with a low coefficient of thermal expansion matched to that of the beryllia substrates. The result is reduced thermal stresses at the substrate-to-baseplate solder joint compared to modules using metallic baseplates. These type of modules have been adopted for use in power inverters for electric vehicle applications. Experiments simulating actual power cycling requirements for electric vehicle applications designed to measure the long term reliability of the solder joint between the Al/SiC baseplate and the DBC beryllia substrate showed no deterioration after 2000 thermal cycles with no evidence of bond failure. In contrast, when

0.94max 1–5 1–30 1000–5000 1200–1700

300–1500 3000

0.03 20–40

g/cc nm μ – GPa

GPa W/mK

μ∗cm %

Density Diameter Length l/d Elastic modulus Tensile strength Thermal Conductivity Resistivity Strain to failure

Single wall (SWNT)

Unit

Property

Value per nanotube type

0.03–0.1 20–40

0.77max 2.5–6.2 2–50 500–12,000 1000–2000 Estimated 300–2000 1500–3000

Double wall (DWNT)

0.1 20–40

300–600 1500

2.0max 13–50 10–500 2000–20,000 100–3700

Multi wall (MWNT)

Table 10.5 Carbon nanotube properties [4]

100 2

2–7 20–1200

2.0max 7000 – – 200–700

Carbon fiber

Alternative fillers

41 –

– 1500

2.0max – – – 1060

Graphite

10 2.5

0.4 20–70

8 – – – 200

Steel

224 J.L. Sepulveda and L.J. Vandermark

Dens. (g/cc) CTE (ppm/◦ C) TC (W/mK) Specific heat (j/gK) Tens. Strength (ksi) Modulus (GPa) Surf. Fin. (μ-in) Size Cap.(in) Min. Thick.(in) Elec. Cond. % IACS

Property

16.9 5.63 130 .160 59 306 25 2×2 0.01

27

42

10%Cu/90%W

16.2 7.1 200 0.171 73.5 274 25 1×1 0.01

15%Cu/ 85%W

23

9.6 7.2 145 0.300 – 283 25 1×1 0.01

15%Cu/ 85%Mo

–

3.01 6.7 170 – – 220 – – –

30%Al/ 70%SiC

–

2.95 8.5 160 – – 195 – – –

45%Al/55%SiC

Table 10.6 Properties of metal matrix composite packaging materials

35

8.77 6.5 153 0.36 – 110.3 – – –

R Silvar 39%Ag/ 61%Invar

18.5

8.8 7 110 – – 125 – – –

R SilvarK 39%Ag/ 61%Invar

(continued)

6.7

2.52 6.1 230 1.26 39 330 25–125 11×11 0.018

E60 60% BeO 40% Be

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E40 40% BeO 60% Be

2.30 7.5 220 1.41 42 317 25–125 11×11 0.018 14.74

Property

Dens. (g/cc) CTE (ppm/◦ C) TC (W/mK) Specific heat(j/gK) Tens. strength (ksi) Modulus (GPa) Surf. Finish (μ-in) Size Cap.(in) Min. Thick.(in) Elec. Cond. % IACS

2.06 8.7 210 1.584 58 303 25–125 11×11 0.018 25.2

E20 20% BeO 80% Be 5.2 7–9 200–250 – – – – – – –

Cu/SiC 4–6 6.5–9.0 400–500 – – – – – – –

Cu/cBN

Table 10.6 (continued)

5.9 5.8 600–1200 – – – – – – –

Cu/diamond

3.10 7.50 650 0.73 50.7 200 50–60 – – 18.74

Al/diamond

3.30 1.8 600 – – – – – – –

SiC/diamond

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copper baseplates were used, deterioration was observed initially at 250 cycles, with failure of approximately 40% of the joint area following 1000 cycles. The improved CTE match between the BeO substrate (6.3 ppm/◦ K) and the Al/SiC baseplate (7.3 ppm/◦ K) resulted in a dramatic improvement in thermal cycling life, as compared to copper baseplates (18 ppm/◦ K). High performance beryllium metal matrix composites with beryllia as reinforcement have been developed during the last four years. These composites are available worldwide as E Materials. By changing the proportion of Be to BeO, it is possible to tailor its thermal, physical and mechanical properties. E Materials are ideally suited for electronic packaging applications that require CTEs matched to ceramic chip carriers while providing high thermal conductivity and low weight. Three different grades are offered containing 20, 40, or 60% by volume beryllia reinforcement. Properties are summarized in Table 10.6. E Materials have 35% higher thermal conductivity than Al/SiC (65% SiC), are 75% lighter than Kovar, with 5× lower amplitude than Al/SiC, and a CTE to match GaAs, BeO, Al2 O3 , and AlN. They can be Ni, Au, Cu, Sn or Cd plated. They provide a good match for AuSn and AuGe brazing/soldering temperatures, conventional ring frame materials like Kovar, and Alloy 46 or 48, that are used in hermetic packaging applications. E Materials are also very well suited for applications that will have to withstand high levels of vibration. The high elastic modulus combined with the low specific gravity of E Materials, provide a very high specific stiffness which reduces the transmission of vibration to the package improving solder fatigue life of the solder joints. The E60 material has shown to have 1/5th the displacement (amplitude) of the 35/65% by volume Al/SiC. For equal vibration frequency, E40 would require 1/3 of the section thickness of Cu–Mo–Cu or Cu-Invar-Cu while still improving the thermal heat transfer. This would reduce the weight of the system by 30%. Recently a novel approach has been developed to apply MCMs to power modules [13]. For example, a base consisting of E Material composite is used in combination with ceramic or polymer substrate (spacer) provided with direct bond copper traces on both sides. This substrate contains cavities for the power devices, power vias, as well as low power interconnects and embedded passives for the control and protection circuits. Two high power conductors can be established in the same equivalent space of a conventional single layer power module. The spacers can be fabricated from advanced multilayer printed wiring board or multilayer tape ceramics.

10.8.2 Cu/cBN Composites A typical Cu/cBN heat sink will exhibit TC of 400–500 W/mK, CTE of 6.5– 9 ppm/◦ K, low density of 4–6 g/cc, and a melting point of 1085◦ C [5]. They are produced using a P/M, pressureless sintering, infiltration process, in a H environment at temperatures that can reach ∼1200◦ C. After sintering to close-to-net shape, parts can be machined using conventional surface grinding or wire/sink EDM. Electroless Ni plating followed by electrolytic Au plating have been developed for these composites. Brazing of metallized ceramic components using CuSil has

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also been accomplished. Cu/cBN composites offer an attractive cost/performance ratio. The feasibility of this technology has been demonstrated but it is still under development. Large scale industrial scale has not been reached yet.

10.8.3 Cu/SiC Composites Cu/SiC heat sinks exhibit an intermediate TC of 180–250 W/mK, CTE of 7–9 ppm/◦ K, low density of 5–5.2 g/cc, and a melting point of 1085◦ C. However, using a pure Cu FGM core raises the effective TC to 391 W/mK [6]. They are produced using a P/M, pressureless sintering infiltration process in a H environment at temperatures that can reach ∼1200◦ C. After sintering to close-to-net shape, parts can be machined using conventional surface grinding or wire/sink EDM. Electroless Ni plating followed by electrolytic Au plating has been developed for these composites. Brazing of metallized ceramic components using CuSil has also been accomplished. Cu/SiC composites offer an attractive low cost derived from the low cost precursor materials used. A 62.5% reduction in weight has been accomplished for RF-701 flanges produced out of Cu/SiC as compared to standard 15/85 Cu/W. The feasibility of this technology has been demonstrated but it is still under development. Industrial scale applications have not been reached yet.

10.8.4 Al/Diamond Composites Al/diamond composites exhibit a high TC of 500–550 W/mK, CTE of 7.5 ppm/◦ K, very low density of 3.1 g/cc, and a melting point of 650◦ C [4]. They are produced using high pressure squeeze casting using temperature conditions slightly over the melting point of Al. After sintering to close-to-net shape, parts can be machined using conventional surface grinding or wire/sink EDM. Ni and Au plating have been demonstrated for these composites. The use of synthetic diamond at about $140/lb has reduced the cost structure of these composites. Secondary machining and surface preparation constitute the main cost component for these heat sinks. EDM’ing of through holes and other dimensional features to ±0.001 in. has been demonstrated. Surface finish is rough, about 400 μin. Precision flatness would require the use of an Al “skin”. The feasibility of this technology has been demonstrated. Several parts have been produced in limited quantities. An example is shown in Figure 10.7. Industrial scale has not been reached. These composites provide attractive cost/performance ratio indicator. Other composites using diamond as reinforcement and Cu, Co, Ag, Mg, and Si as the matrix have also been produced exhibiting high TC, low density, and low CTE. Properties are shown in Table 10.7 [4]. The use of SiC as matrix for diamond composites is also an attractive formulation. Al/Diamond/Graphite composites have also been developed to package silicon carbide (SiC) based power switching devices to enable the next generation high torque electric motor drives to operate at 200–300◦ C without the need for active cooling.

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Fig. 10.7 Aluminium/diamond small footprint packaging flanges for optoelectronics Table 10.7 High performance diamond composites [4] Matrix

Reinforcement

Al Al Al

Graphite flake Diamond particle Diamond & SiC part. Diamond particle Diamond particle Diamond particle Diamond particle Diamond particle Diamond particle – – –

Cu Co Ag Mg Si SiC Diamond HOPG Graphite

Inplane TC TC (W/mK)

Through TC (W/mK)

CTE ppm/◦ K

Density g/cc

400–600 550–600 575

80–110 550–600 575

4.5–5.0 7.0–7.5 5.5

2.3 3.1 –

600–1200 >600 400 to >600 550 525 600 1100–1800 1300–1700 150–500

600–1200 >600 400 to >600 550 525 600 1100–1800 10–25 6–10

5.8 3.0 5.8 8.0 4.5 1.8 1–2 –1.0 –

5.9 4.1 5.8 – – 3.3 3.5 2.3 –

The integrated high thermal conductivity Al/Diamond/Graphite base plates house high performance IGBT’s. DBC ceramic substrates may be used to carry the power switching devices and can be integrated into the Al/Diamond base plate thereby eliminating the low reliability solder interface used in commercial power modules. These substrates can be directly integrated with a passively cooled heat sink and enable at least 5× reduction of thermal resistance from heat sink to the device junction. A low thermal resistance packaging/die attachment technique based on Transient Liquid Phase (TLP) bonding and capable of withstanding high temperatures is used allowed by the use of SiC devices, achieves significant reduction of the temperature gradient between the junction and the ambient. The TLP approach achieves 10× reduction in thermal resistance compared to soldered attachments and improved reliability due to increased resistance to formation of voids under thermal and power cycling condition. The final package solution allows the manufacturing of power modules within custom enclosures without requiring active cooling. These packages are intended for 3-phase motor inverters. Robust power modules consisting of Silicon IGBT power switching devices that allow maximum junction temperature rise to 175◦ C, and SiC Schottky diodes capable of operating at high junction temperatures up to 300◦ C are used. The SiC Schottky diode section of

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the power module is cooled via natural convection only while the Silicon IGBT can be passively cooled or air-cooled depending on the application. The passively cooled hybrid power module allows substantially larger output power delivered to the motor, as compared to the current state of the art power modules. This is due to reduced thermal resistance and reduced losses in the Si IGBT and SiC diodes due to elimination of reverse recovery losses. Several hybrid power modules can be paralleled to achieve higher output power. This advanced packaging technology will allow for hybrid power module consisting of SiC Schottky diodes, and silicon (Si) IGBTs. The power module layout will be designed such that the SiC power switching devices can be drop-in replacements (with minor modifications in the gate drive circuitry) for the Si IGBTs. These are becoming more available recently. SiC based power switching devices such as MOSFETs and IGBTs with high current ratings are currently in the research and development stage and are not widely commercially available. The technology to fabricate high current SiC Schottky diodes, however, is quite mature and diodes with current ratings greater than 20A are commercially available. SiC Schottky diodes do not exhibit reverse recovery behavior observed in Si PiN diodes. Reverse recovery loss contributes to 60–70% of the power loss in a switching device during turn-on. Hence, replacing just the Si PiN diodes by SiC Schottky diodes significantly reduces the power loss in the switching devices resulting in a substantial improvement in efficiency. Reduced power loss in the switching devices also results in reduced junction temperature rise, simplified cooling, higher power density and reliability. The switching loss in the IGBTs can be reduced by 2× by elimination of diode reverse recovery. These inverter modules will be used in a modular design to produce 50–100 kW motor drives. An illustration of these packages is provided in Figure 10.8.

Fig. 10.8 Graphite/diamond squeezed cast infiltrated packages. Diamond aluminium hot spot area shown on top

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10.9 Conclusions BeO packaging technology for microwave and power RF applications is well established and still provides highly reliable solutions after almost forty years. It will continue to provide the level of performance and reliability that users have become used to. With the development of new improved formulations, to provide improved ceramic properties, large volume, low cost processes, or as reinforcement material for metal matrix composites, the future of BeO for microwave packaging thermal material is assured. Beryllia ceramic has been the material of choice for high performance applications that need a ceramic electrical insulator that at the same time provide good thermal dissipation. The stability of beryllium oxide ceramic components in reducing and oxidizing environments makes it the prime candidate for long life, high-reliability commercial and defense applications. As a thermal management ceramic, BeO outperforms AlN for high RF packaging applications. Although less conductive than diamond, BeO presents an advantage over diamond since it is easily machined to final shape, at lower cost. The consistency of beryllia ceramics performance has been insured throughout the years by using high purity powders. Predictable ceramic properties and reliable associated metallization technologies make BeO a proven technology ready for the challenges to be found well into this millennium.

References 1. D. E. Jech, and J. L. Sepulveda, “Advances in Beryllia Ceramic Sintering,” Sintering 1995, PennState, University Park, PA, September 24–27, 1995 2. J. L. Sepulveda, D. E. Jech, and G. P. Ferguson, “Using SPC for the Dry-Pressing of Beryllia Parts,” American Ceramic Society Bulletin, vol. 73, no.1, January 1994 3. A. London, S. J. Corbett, H. Berentsen, and R. A. Stella, “Thick Film Material Requirements for Power Hybrids on Beryllia,” in Proceedings of 1984 ISHM National Symposium, Dallas, September 1984 4. E. Foley, and G. Rees, “Preliminary Investigation of Potential Beryllium Exposure While Laser Trimming Resistors on Beryllia Substrates,” in Proceedings of 1980 ISHM International Microelectronics Symposium, New York, October 1980 5. J. L. Sepulveda, C. W. Albin, E. Lewis, and D. D. Moody, “High Performance Thin Film Devices on Metallized Beryllia Tape Substrates,” in Proceedings, 25th ISHM International Symposium on Microelectronics, San Francisco, October 1992 6. “Thin Film Hybrids,” Hybrid Circuit Technology, p. 42, January 1992 7. J. F. Dickson, “Direct Bond Copper Technology, Materials, Methods, and Applications,” International Journal of Hybrid Microelectronics, vol. 5, no. 2, pp. 103–109, November 1982 8. J. L. Sepulveda, and T. D. Sims, “High Thermal Conductivity Layered Substrates,” ISHM Advanced Technology Workshop on Thermal Management, Aspen, Colorado, April 21–23, 1995 9. D. R. White, S. D. Keck, and T. G. Nakanishi, “New SiC/Al Baseplates for High Performance Power Modules,” Proceedings, PCIM Europe, 1996. 29th International. Power Conversion Conference, Nürnberg, Germany, pp. 341–346 10. P. Barnwell, and S. Fuchs, “A Detailed Evaluation of Alternative High Power Substrates for Thick Film Circuits,” Proceedings, 1994 ISHM International Symposium on Microelectronics, Boston, MA

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11. R. Sigliano, and J. Danaher, “Thermal Performance Heats Up Power RF Transistor Packaging Design,” Advanced Packaging, May/June 1997 12. P. Danner, and J. L. Sepulveda, “High Performance Ceramic Modules and Packages,” Proceedings, 1995 International Conference on Multichip Modules, Denver, Colorado, April 1995 13. A. Lostetter, J. Webster, R. Hoagland, F. D. Barlow, and A. Elshabini-Riad, “High Density Power Modules: A Packaging Strategy,” Proceedings, 1997 International Symposium on Microelectronics, IMAPS, October 14–16, Philadelphia, PA, pp. 102–107 14. P. Danner, and J. L. Sepulveda, “High Performance Ceramic Modules and Packages,” Proceedings, 1995 International Conference on Multichip Modules, Denver, Colorado, April 1995 15. A. Lostetter, J. Webster, R. Hoagland, F. D. Barlow, and A. Elshabini-Riad, “High Density Power Modules: A Packaging Strategy,” Proceedings, 1997 International Symposium on Microelectronics, IMAPS, October 14–16, Philadelphia, PA, pp. 102–107 16. J. L. Sepulveda, and D. E. Jech, “Functionally Graded Copper/Tungsten Metal Composites”, PM 2000, Kyoto, Japan, November 2000 17. J. L. Sepulveda, and L. Valenzuela, “Integrated Subassemblies Improve Optoelectronic Package Performance”, Optical Manufacturing, May 2002 18. J. L. Sepulveda, J. A. Karker, K. H. Dalal, N. Adams, and C. Mead, U.S. Patent Application No. 20030002825., “Carrier Sub-Assembly With Inserts And Method For Making The Same”, January 2, 2003 19. R. O. Loutfy, MER Corporation, Tucson, AZ. www.mercorp.com 20. J. L. Sepulveda, NSF DMI-0319026, P.O.: T. James Rudd, January 15, 2004 21. J. L. Sepulveda, NASA SBIR Contract No. NNC04CA62C, COTR: Salvatore M. Oriti, July 19, 2004 22. C. M. Steddom, J. L. Sepulveda, and J.A. Karker. “RF and Optical Circuits with Thick-Film Technology Offer Improved Performance”, IMAPS ATW Cer. Appl. for Micr. and Phot. Pack., Providence, RI, May 2–3, 2002 23. C. M. Steddom, J. Occhipinti, M. Roffe, J. L. Sepulveda, and J. A. Karker, U.S. Patent Application No. 20040080917, “Integrated Microwave Package and the Process for Making the Same”

Chapter 11

High Performance Microelectronics Packaging Heat Sink Materials Jiang Guosheng, Ken Kuang, and Danny Zhu

Abstract Ever since the birth of the first semiconductor transistor in 1947, there was a need for microelectronics packaging. The purpose of microelectronics packaging is to interconnect all active and passive components alike, and at the same time to protect the electronic devices from potential harms from environment like moisture, dust and gas etc. and from other mechanical shocks. During operation, semiconductor chips also generate a lot of heat. It is important to manage this waste heat, hence the term of thermal management. One of the key enablers of effective thermal management is high performance heat sink materials. In this chapter, we will review the main characteristics, manufacturing process and the latest development in both copper and aluminum based heat sink materials. Then we will discuss the latest development for other heat sink materials.

11.1 Introduction Ever since the birth of the 1st semiconductor transistor in 1947, there was a need for microelectronics packaging. The purpose of microelectronics packaging is to interconnect all active and passive components alike, and at the same time to protect the electronic devices from potential harms from environment like moisture, dust and gas etc. and from other mechanical shocks. For the last 60 years, microelectronics packaging has been steadily moving to smaller form, lighter weight, lower cost, more functionalities, higher reliability and

J. Guosheng (B) Changsha Saneway Electronic Materials Co., Ltd, Central South University, Changsha, Hunan, China 410012 e-mail: [email protected]

K. Kuang et al. (eds.), RF and Microwave Microelectronics Packaging, C Springer Science+Business Media, LLC 2010 DOI 10.1007/978-1-4419-0984-8_11, 

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higher powers etc. Consequently the unit area heat dissipation is getting higher and higher. It is estimated that, using CPU for computer work stations as an example, the power dissipation is currently at 40 W/cm2 and can reach 125 W/cm2 in the future. For MPU, the heat dissipation requirement reached about 150 W/cm2 . The excess heat, if not dissipated properly, increases the chip junction temperature and renders the chip less reliable. Statistically for every 18◦ C increase in chip junction temperature, the reliability of IC chips is reduced by 2–3 times. There are many ways to reduce the IC chip operating temperature, like cryogenic storage, active cooling water pipe and cooling fans etc. Basically these methods all focus on taking away waste heat from the outside packages. It is also very important to improve the thermal conductivity of the materials coming to close contact with chips so that the heat can be effectively conducted to the outer packages for eventual removal. Microelectronics packaging can be generally divided to three levels (1) device and carrier; (2) mother board or interconnect board; and (3) enclosure. In some circuits, levels 1 and 2 may be combined, as in passive integrated boards or some multilevel circuits. The ultimate goal of all levels is to ensure signal integrity and impedance matching with a minimum of reflection and distortion, low thermal resistance, good electrical isolation and protection of the component elements. For each level of packaging, there are different requirement for microelectronics packaging materials. For level 1 packaging, packaging materials generally require high thermal conductivity, low coefficient of thermal expansion (CTE) matching that of IC’s and high hermeticity etc. For level 2 packaging, the requirements of packaging materials are high heat dissipation, matching CTE and good mechanical strength. For level 3 packaging, the packaging materials are preferred to be lighter weight, good mechanical strength and good heat dissipation Fig. 1. There are many potential choices for microelectronics packaging materials. Usually the desired material characteristics are: 1. Good thermal conductivity which is important to conduct the heat away from the IC’s 2. Good hermeticity which is important to protect the immediate environment that the IC is in 3. Proper CTE to match that of IC’s (Si, GaAs) and other packaging materials like alumina, BeO and AlN ceramic etc. 4. Good mechanical strength to provide good mechanical protection to the IC’s 5. Good machinability so that they can be formed to desired shapes. 6. Other specific requirements, like for aerospace and portable applications, low weight is desired.

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Fig. 1 Different levels of packaging

In addition, the manufacturing cost is another key factor. Traditional packaging material focused on the raw material forms. Table 1 lists some properties of traditional microelectronics packaging materials. Above traditional packaging materials were widely used, each with its pros and cons. For example, both Invar and Kovar have very good CTE, but their relatively high electrical resistivity and low thermal conductivity limit their use in low power applications. Tungsten and molybdenum have the CTE very similar to that of silicon. In addition, their thermal conductivity is far better than that of Kovar and they were used quite often as base plates. Copper and aluminum have excellent thermal conductivity and good machinability. Due to their high CTE’s, they are used only limitedly in low power parts. The new generation of heat sink materials is based on what was learned from traditional materials. There are basically two main categories, copper based and aluminum based.

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Materials

Thermal conductivity (W/m·k)

CTE (10–6 /k)

Silicon GaAs GaN

150 55 130

Al2 O3 AlN BeO Al Cu W Mo SiC Invar Kovar Epoxy

20 270 210 230 400 174 140 270 11 17 1.7

4.1 5.8 5.59, a-plane 3.17, c-plane 6.7 5.8 8.0 23 17 4.5 5.0 5.0 0.4 5.9 5.4

Density (g/cm3 ) 2.3 5.32 6.15 3.9 3.29 2.86 2.7 8.9 19.3 10.2 3.21 8.04 8.3 1.2

In copper based, there are copper tungsten, copper molybdenum and copper/molybdenum/copper and copper/molybdenum-copper/copper laminates etc. Aluminum based includes AlSi, Al-graphite and AlSiC etc.

11.2 Refractory Metal Based Microelectronics Packaging Materials 11.2.1 Development, Manufacturing and Application of Copper Tungsten 11.2.1.1 Characteristics of Copper Tungsten Tungsten has very high melting point, high density and low CTE. Copper is a good electrical and thermal conductor. The combination of both tungsten and copper (i.e. copper tungsten composite) enjoys the low CTE of tungsten and high thermal conductivity of copper. At the same time, the CTE and electrical conductivity can be adjusted by varying copper tungsten ratio. Copper tungsten is widely used as electrodes and as heat sinks for microelectronics packaging. Copper tungsten’s CTE can be tailored to match the CTE’s from ceramics, semiconductor chips and other metals. For microelectronics packaging applications, WCu has some unique requirements for CTE, thermal conductivity and hermeticity. Consequently, the manufacturing process has some unique challenges: 1. material to meet CTE, thermal conductivity and hermeticity specifications 2. material to meet all dimensional requirements 3. material to meet surface finish requirements (like Ni and / or Au plating).

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11.2.1.2 WCu Manufacturing Process and Technical Properties There are many grades of WCu materials currently being used as heat sinks. Their typical technical properties are shown in Table 2. Figure 2 shows some typical WCu heat sink parts. The most common fabrication method is powder metallurgy (PM). More specifically, there are four different manufacturing techniques: 1. 2. 3. 4.

High temperature liquid phase sintering Reactive sintering Infiltration Metal injection molding

High Temperature Liquid Phase Sintering Due to the fact that the melting points of copper and tungsten are so different, it is possible to use high temperature liquid phase sintering to prepare the composite material. The advantage is its simple and mature process. The basic process Table 2 Typical properties of heat sink grade WCu Properties Name

Density g/cm3

CTE 10–6 /K TC W/m.K Young’s Modulus GPa Hardness HV10

W90Cu W88Cu W85Cu W80Cu

17.0 16.9 16.3 15.6

6.5 6.8 7.0 8.0

Fig. 2 Typical WCu heat sinks

190 ∼ 200 190 ∼ 200 200 ∼ 210 210 ∼ 220

330 320 310 280

300 290 280 260

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steps include powder mixing, dry press and sintering. The disadvantages are its high sintering temperature, long sintering cycle and relatively low sintered body density (typically at 90–95% theoretical density). In order to achieve usable materials for heat sinks, the high temperature liquid phase sintered WCu materials are very often further processed using forging and hot pressing etc. The additional post sintering process limits the use of high temperature liquid phase sintering to fabricate WCu heat sinks. A.K. Bhalla reportedly achieved good results using explosive compaction. It was also found out that copper particle size played an important role in high temperature liquid phase sintering. The smaller copper particle sizes, the higher sintered density.

Reactive Sintering Reactive sintering is commonly used to sinter tungsten powders. Similar methods are adopted to fabricate WCu composites. The typical sintering aids are Pd, Ni, Co and Fe etc. The addition of sintering aids reduces sintering temperature and time, and increases sintered density significantly. Among the sintering aids for WCu composites, Co and Fe are the best. Using W90Cu (90% W) as an example, when Co content is 0.35% and the sintering is done at 1300◦ C for 1 h, the resultant sintered composite has 99% theoretical density, hardness of 300 HV and flexural strength of 300 MPa. Ni and Pd are not as good as Co and Fe due to the fact both Ni and Pd can form alloys with Cu. The reason is that Ni and Pd are infinitely soluble in molten copper, while Co and Fe are only partially soluble. During the sintering process, Co and Fe will form intermetallic compound to promote the densification of tungsten. Unfortunately the very addition of sintering aids reduces the electrical conductivity and thermal conductivity significantly. They are rarely used in manufacturing WCu heat sinks materials.

Infiltration Infiltration starts with preparation of a dry pressed tungsten green body and them infiltrate with molten copper. Its mechanism is the capillary force to fill the microcavities inside the green body, provided that the molten metal wets the green body skeleton (Fig. 3). The advantages of infiltration are high density, excellent electrical conductivity and thermal conductivity. The disadvantages are multiple machining steps after infiltration that can lead to higher cost and lower yield. Due to the good performance of obtained materials, infiltration method is the dominant way to manufacture WCu heat sinks. One of the key processes to make good WCu heat sink materials is to prepare a evenly distributed, good cooper wetting and high purity tungsten skeleton. Tungsten powders are relatively hard to form a green body, micro cracks and delaminations are common defects. There are four ways to prepare tungsten skeletons:

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shows a typical microstructure of WCu parts fabricated by dry press and infiltration. 3. Mechanical alloying (MA): Mechanical Alloying (MA) is a solid-state powder processing technique involving repeated cold welding, fracturing, and rewelding of powder particles in a high-energy ball mill. Originally developed to produce oxide-dispersion strengthened (ODS) nickel- and iron-base superalloys for applications in the aerospace industry, MA has now been shown to be capable of synthesizing a variety of equilibrium and non-equilibrium alloy phases starting from blended elemental or prealloyed powders. Typically MA is done in reducing atmosphere. The drawback is the Fe impurities introduced during the ball mill stage which affects the thermal and electrical performance of resultant WCu material. Figures 5, 6 and 7 show the micrographs of MA Cu–W powder, XRD and WCu composite

Fig. 5 SEM pictures of Cu–W powders after different ball milling time a. 10 h, b. 40 h, c. 60 h (courtesy of Saneway Electronics Materials Co. Ltd)

Fig. 6 XRD results for Cu–W powder after different ball milling time a. 10 h, b. 60 h (courtesy of Saneway Electronics Materials Co. Ltd)

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Fig. 7 WCu composite prepared by MA after different ball milling time a. 10 h, b. 40 h, c. 60 h (courtesy of Saneway Electronics Materials Co. Ltd)

4. Extrusion 5. Injection molding

11.2.2 Development, Manufacturing and Application of Copper Molybdenum (MoCu) 11.2.2.1 Comparison Between MoCu and WCu Packaging Materials MoCu composite material was developed in 1960’s. It has good electrical conductivity, good thermal conductivity, good corrosion resistance, good machinability and adjustable CTE. It is widely used as heat sinks in microelectronics packaging, vacuum electrical contactor, aerospace and mining industries. Density Similar to tungsten, molybdenum is a refractory metal with very high melting point. At the same time, it has low CTE and high thermal conductivity making it a good material for heat sinks. Among heat sink materials, molybdenum’s CTE is one of the closest to that of Silicon, molybdenum is widely used as a carrier (tabs) for die attach. Since Mo is a lot lighter than tungsten, it is desired in many weight sensitive applications like aerospace and portable electronics. In additional, MoCu composite is easier to machine. Table 3 show the density comparison between WCu and MoCu. Table 3 Density of W–Cu and Mo–Cu Mo–Cu ρ(g.cm–3 ) W–Cu ρ(g.cm–3 )

Mo–15Cu 10.0 W–10Cu 17.3

Mo–20Cu 9.9 W–15Cu 16.42

Mo–30Cu 9.8 W–20Cu 15.66

Mo–40Cu 9.66 W–30Cu 14.31

Mo–50Cu 9.54 W–40Cu 13.17

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As shown in Table 3, with the same copper content, MoCu is about 50–75% lighter than that of WCu. Once again this property is desired in weight sensitive applications. Coefficient of Thermal Expansion (CTE) CTE changes with the temperature. Figure 8 shows the CTE comparison among 95% alumina, W–15Cu and W–15Mo. From 100 to 800◦ C, the CTE of Mo–15Cu matches that of 95% alumina very well (and better than that of W–15Cu). This translates to reduced interface residual stress and improved component reliability.

Fig. 8 CTE comparison of W–15Cu and Mo–15Cu

Specific Heat Specific heat is another important property for heat sink materials. High specific heat is desired since the heat sink material with higher Cp can absorb more heat itself and reacts better with the peak and valley of the waste heat. Since Cp is not sensitive to the microstructures, WCu and MoCu’s Cp over the temperature range from 100 to 700◦ C were estimated using the theory of combination and summarized in Fig. 9. When the heat sink mass and area are fixed, MoCu’s higher Cp allows it better heat dissipation. Copper Wettability Figure 10 shows the wetting angles θ of molten copper on tungsten and molybdenum plates. Overall molten copper wets tungsten better than molybdenum. Similar to tungsten, molybdenum does not alloy with copper easily. To sinter Mo and Cu, some sintering aids like Ni, Co, Fe and Pd etc. can be used. Among these sintering aids, Ni works the best and helps lower copper’s wetting angles on molybdenum and promotes densification.

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Fig. 9 Specific heat comparison between WCu and MoCu

Fig. 10 WCu and MoCu wetting angles

11.2.2.2 MoCu Manufacturing Process and Technical Properties For electronics packaging applications, the main compositions of MoCu composites are Mo–15Cu, Mo–20Cu, Mo–30Cu, Mo–40Cu and Mo–50Cu etc, Their properties are shown in Table 4. Table 4 Properties of Mo–Cu composites Item

Density g/cm3

CTE 10–6 /K

TC W/m.K

Young’s Modulus GPa

Mo85Cu Mo80Cu Mo70Cu Mo60Cu Mo50Cu

10.0 9.9 9.8 9.66 9.54

7.0 7.8 9.1 10.3 11.5

150 170 185 200 230

274 – – – –

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Molybdenum’s melting point of 2610◦ C is higher than copper’s boiling point 2595◦ C. Copper is not soluble in molybdenum. Most MoCu composites are fabricated using powder metallurgy and the process is very similar to that of WCu. Generally, there are three manufacturing methods: 1. High temperature liquid phase sintering: The basic high temperature liquid phase sintering process is very similar to that of WCu. The precursor materials can be either pure copper and molybdenum powders, or can be a mixture of pure and oxide copper and molybdenum powders. The basic process flow is the same as that of WCu, basically consists of powder mixing, dry press and sintering. This process works best for the high molybdenum content composites since it is difficult to do by infiltration. For high molybdenum content composites, it is very common to use ultra fine molybdenum and copper powders as precursor materials and mechanical surface activation to promote the sintering densification. The drawback is that molybdenum grains tend to have excessive growth. The structure of resultant MoCu composite is not as homogeneous as that of infiltration. 2. Infiltration: As in the case of WCu, most of MoCu heat sink materials are being fabricated by infiltration. This process starts with dry pressing molybdenum powders to a green body and pre-sintered in reducing atmosphere to obtain a porous molybdenum body. Then molten copper infiltrates the micropores of molybdenum skeleton to form a MoCu composite. The copper content is determined by the volume of interstices within the molybdenum skeleton. Since the copper density is very close to that of molybdenum, the volume of interstice is limited and consequently the copper content is limited to about 30% or less by weight. For lower copper content composite (like 85% Mo–15% Cu), the best way to fabricate is still by high temperature liquid phase sintering. 3. Mechanical alloying (MA): MoCu composites fabricated by mechanical alloying exhibit higher electrical conductivity, higher thermal conductivity and higher hardness. During mechanical alloying process, metal particles undergo extensive stress, strain and dislocation to form some nanoscale grain boundaries. The system has a lot higher residual energy, up to 10 kJ/mol or more. After mechanical alloying, the powders are highly activated. The longer the ball milling time, the smaller the metal particles and the larger the specific surface area. At the same, there are many surface and grain boundary defects. The powders are at mesotable state and very easily densified during sintering.

11.2.3 Development, Manufacturing and Application of Copper-Molybdenum-Copper Laminates and Copper-Copper/Molybdenum-Copper Laminates 11.2.3.1 Material Characteristics Copper/molybdenum/copper (CMC) or copper/molybdenum-copper/copper are laminates with low CTE material (Mo or MoCu) sandwiched by thin copper

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sheets. Typical structure has three layers. There are reports that some 4 or 5 layers were fabricated. Typical fabrication methods are hot rolling lamination, explosive lamination, and plating lamination. New developments on laser cladding and ultrasonic welding were reported too. These types of laminates enjoy good thermal conductivity and low CTE. In addition, unlike WCu and MoCu composites, there is no porosity issue. Relatively speaking, the manufacturing cost of these laminates is lower than that of WCu and MoCu. Furthermore, these laminates can be fabricated in large format (like 24 ×24 ). From metallurgical point of view, Cu and Mo are so different. Again the melting point of Mo is higher than the boiling point of Cu. Cu has very low solubility in Mo. In addition, Mo and Cu sheet metals have different mechanical properties. The recrystallization temperature for Mo is >1200◦ C, while copper recrystallizes in temperature <400◦ C. There are two types of Cu and Mo laminates: Copper/Molybdenum/Copper (CMC) and Copper/Pressed copper molybdenum/Copper (CPC). Typical properties of CMC and CPC are shown in Table 5 and 6. Table 5 Typical properties for CMC Thermal conductivity W/m.K Cu/Mo/Cu ratio

Density g/cm3

CTE×10–6 /K

In plane

Thru plane

13:74:13 1:4:1 1:3:1 1:2:1 1:1:1

9.88 9.75 9.66 9.54 9.32

5.6 6.0 6.8 7.8 8.8

200 220 244 260 305

170 180 190 200 220

Table 6 Typical properties for CPC Thermal conductivity W/m.K Cu/MoCu/Cu ratio

Density g/cm3

Young’s Modulus GPa

CTE×10–6 /K

In Plane

Thru Plane

1:4:1

9.5

195

7.0–9.0

280

180

11.2.3.2 Manufacturing Process Flow and Typical Properties Hot Rolling Lamination Hot rolling lamination uses huge rolling machine pressure, aided by heat, to apply tremendous shear force onto the laminating materials. The surface oxide layers are broken down by the shear force, undergo plastic deformation and form an atomic

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level intermetallic bond. In the hot rolling lamination process to make Cu/Mo/Cu and Cu/MoCu/Cu laminates, 4 key factors are important to control the obtained laminate quality. They are material surface condition before lamination, 1st rolling thickness deformation, rolling temperature and annealing temperature. Hot rolling lamination is a relatively mature manufacturing method with low volume manufacturing cost. However the initial capital investment is high. Due to the fact that Cu and Mo are mutually insoluble, the bonding mechanism at Mo and Cu interface is microscopic level mechanical bonding (Fig. 11).

Fig. 11 SEM micrographs for Cu/Mo interface in CMC laminates

Explosive Forming Explosive forming is a metalworking technique in which an explosive charge is used instead of a punch or press. It can be used on materials for which a press setup would be prohibitively large or require an unreasonably high pressure, and is generally much cheaper than building a large enough and sufficiently high-pressure press; on the other hand, it is unavoidably a batch process, producing one product at a time and with a long setup time. There are various approaches; one is to place metal plate over a die, with the intervening space evacuated by a vacuum pump, place the whole assembly underwater and detonate a charge at an appropriate height above the plate. For complicated shapes, a segmented die can be used to produce in a single operation a shape that would require many manufacturing steps, or to be manufactured in parts and welded together with concomitant loss of strength at the welds. There is often some degree of work hardening from the explosive-forming process, particularly in mild steel. Tooling can be made out of fiberglass for short-run applications, out of concrete for large parts at medium pressures, or out of ductile iron for high-pressure

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work; ideally the tooling should have higher yield strength than the material that is being formed, which is a problem since the technique is usually only considered for material which is itself very hard to work. Explosive forming was used in the 1960’s for aerospace applications, such as the chine plates of the SR-71 reconnaissance plane and various Soviet rocket parts; it continued to be developed in Russia, and the organizing committees of such events as EPNM tend to contain many members from the former Soviet Union. It proved particularly useful for making high-strength corrugated parts which would otherwise have to be milled out of ingots much larger than the finished product.

Laser Cladding Laser cladding is a method of depositing material by which a powdered or wire feedstock material is melted and consolidated by use of a laser in order to coat part of a substrate or fabricate a near-net shape part. The powder used in laser cladding is normally of a metallic nature, and is injected into the system by either coaxial or lateral nozzles. The interaction of the metallic powder stream and the laser causes melting to occur, and is known as the melt pool. This is deposited onto a substrate; moving the substrate allows the melt pool to solidify and thus produces a track of solid metal. This is the most common technique, however some processes involve moving the laser/nozzle assembly over a stationary substrate to produce solidified tracks. The motion of the substrate is guided by a CAD system which interpolates solid objects into a set of tracks, thus producing the desired part at the end of the trajectory (Fig. 12).

Fig. 12 Schematic diagram of laser cladding (courtesy wikipedia.org)

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11.3 Aluminum Based Heat Sink Materials 11.3.1 AlSiC Heat Sink Materials 11.3.1.1 History and Characteristics A metal matrix composite (MMC) is composite material with at least two constituent parts, one being a metal. The other material may be a different metal or another material, such as a ceramic. MMCs are made by dispersing a reinforcing material into a metal matrix. For microelectronics packaging applications, we are interested in particle reinforced metal matrix composite materials. They normally use SiC, AlN, BeO, Al2 O3 and Si etc. low CTE particles to disperse in a metal matrix like aluminum. For packaging heat sink materials, only AlSiC, Al–Si and Al-Graphite are being used commercially and will be discussed in details here. 11.3.1.2 Aluminum Matrix Composite Materials Aluminum and aluminum alloys like Aluminum-Silicon, (Eutectic, Hypo and Hyper), Aluminum-copper, Aluminum-silicon-copper, Aluminum-magnesium, Aluminum-Silicon-Magnesium, Aluminum-Silicon Magnesium-Copper form the base material for the composites. They are available in the open market covered by IS, BS and ASTM specifications. Properties of the composite can be made to suit the required specifications by the proper selection of the base alloy and the percentage of reinforcing particles to be added. AlSiC AlSiC is a metal matrix composite composed of silicon carbide particles and an aluminum alloy. As shown in Fig. 13 this gray scale micrograph the silicon carbide particles (dark grey) are surrounded by a continuous aluminum matrix (off-white). Typically AlSiC composites are isotropic and do not have an aluminum skin which can often result in non-isotropic behavior, i.e. bi-metalic deformation. There are three main challenges to fabricate AlSiC materials. 1. Aluminum does not wet SiC: Molten aluminum does not wet SiC. During the manufacturing process, it is very important to modify the surface of SiC to make sure Al–SiC interface forms a strong bond. 2. AlSiC is hard to machine: SiC is a very hard material and is often used as a grinding media. To machine AlSiC to various heat sink shapes is very hard. EDM, waterjet and diamond grinding are commonly used. 3. Plating: Since SiC is not electrically conductive, it is not possible to use conventional electrical plating method to deposit any Ni or Au plating. AlSiC material is typically electrolessly plated first. The adhesion layer between SiC and metal is critical to prevent any separation (like delamination and blisters).

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Fig. 13 SEM micrographs of AlSiC (courtesy of Thermal Transfer Composites, LLC)

A leader in developing AlSiC for thermal management application is Thermal Transfer Composites, LLC based in New Castle, Delaware. Many of the manufacturing process figures and product photos are quoted with their permission. AlSiC based composite alloy manufacturing methods are: 1. Casting molten a mixture and SiC and Al (as shown in Fig. 14)

Fig. 14 AlSiC casting process (courtesy of Thermal Transfer Composite LLC)

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Fig. 15 AlSiC pressureless infiltration process (courtesy of Thermal Transfer Composite LLC)

2. Infiltration of Al in voids or pores of a SiC porous body. This infiltration can be done either pressureless (Fig. 15 shows the pressureless infiltration process). 3. Liquid phase sintering – The composite material is obtained by compacting a mixture of SiC powder in the shape of particles, of 10–70 wt%, and Al powder, for example, and sintering the compact in a non-oxidizing atmosphere containing 99 vol% of nitrogen, with oxygen concentration of at most 200 ppm and dew point of not higher than –20◦ C., at a temperature of 600–750◦ C. 4. Hot Isostatic Pressing – a compact of AlSiC based mixed powder having 10–70 wt% of SiC in the shape of particles, for example, is subjected to atmospheric pressure sintering in a temperature range of not lower than 600◦ C. and not higher than the melting temperature of Al in a non-oxidizing atmosphere containing at least 99% of nitrogen gas, and thereafter the compact is sealed in a metal container and subjected to HIP at a temperature of not lower than 700◦ C., whereby an aluminum-silicon carbide based composite material which is uniform and having thermal conductivity of at least 200 W/mK is obtained. Table 7 lists the properties of typical AlSiC materials (Fig. 16).

X 3.2 Aluminum Silicon Materials Hypereutectic aluminum silicon alloys containing from about 16 to 19% by weight of silicon possess good wear resistant properties achieved by the precipitated primary silicon crystals. The conventional aluminum silicon alloy usually contains a substantial amount of copper, generally in the range of 4.0–5.0%. Because of the high proportion of copper, the alloy has a relatively wide solidification temperature range in the neighborhood of about 120◦ C–150◦ F. Which severely detracts from the

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Table 7 Typical AlSiC material properties Property data

AlSiC-1

AlSiC-2

AlSiC-3

AlSiC-4

AlSiC-5

AlSiC-6

Al wt% SiC wt% Thermal conductivity (W/mK) at 25◦ C CTE (ppm/ K) Density (g/cm2 ) Young’s Modulus (GPa) Poisson’s ratio Flexural strength, 4 pt bend (MPa) Specific heat at 25◦ C, (J/gK) Electrical resistivity (μ.cm)

63 37 180

55 45 165

45 55 180

42 58 185

40 60 192

22 78 255

10.9 2.9 188 – –

7.2 2.94 235 0.23 330

6.4 2.98 255 0.24 300

7 3 240 0.23 330

6.9 3.01 262 0.25 517

4.8 3.1 342 0.23 225

0.81 20.7

0.74 30–50

0.74 30–50

0.74 30–50

0.74 30–50

0.71 20–25

castability of the alloy. The copper also reduces the corrosion resistance of the alloy in salt water environments and thus prevents its use for marine engines. Hypereutectic aluminum silicon alloys have been deemed significant for use by the casting industry as well as the automotive industry. This principally results from the potential that such alloys hold for providing good wear resistance along with the conventional advantages derived from aluminum castings. Furthermore, it is well recognized that the casting characteristics of hypereutectic alloys are very good.

a

Fig. 16 Pictures of AlSi parts a. AlSiC IGBT base plates; b. AlSiC liquid cooled components; c. AlSiC air cooled components; d. AlSiC packages (photos courtesy of Thermal Transfer Composites, LLC)

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b

c

Fig. 16 (continued)

A leader in developing AlSi materials is Sandvik Materials Technology. Table 8 list the typical properties of its Osprey CE AlSi materials (Fig. 17). Table 8 Properties of typical AlSi materials Composition

Al-27%Si

Al-42%Si

Al-50%Si

Al-60%Si

Al-70%Si

CTE at 25◦ C (ppm/K) Thermal conductivity (W/m.K) Specific heat (J/gK) Young’s Modulus (GPa) Density (g/cm3 )

15.3 177.4 0.85 91.8 2.6

12.2 160 0.82 101.9 2.55

11.4 149 0.79 121.4 2.51

9.1 129.4 0.78 123.5 2.46

7.2 120 0.78 129.2 2.42

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Fig. 16 (continued)

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X 3.3 Aluminum Graphite Materials Conventional low CTE materials like CuW, CuMo, AlSiC, Mo, and Kovar have reached physical and economic limitations and can no longer offer breakthroughs in cost and performance. Thus, innovative material solutions are sought to keep pace with emerging electronic cooling requirements. As a result, advancements in graphite fiber technology are spawning new ways to design and manufacture enhanced cooling solutions for electronics – especially airborne or handheld applications where low mass is critical. Aluminum and its alloys are extensively used in a large number of industrial applications due to their excellent combination of properties, e.g. high strength to weight ratio, good corrosion resistance, better thermal conductivity, easy to deform etc. Because of high strength to weight ratio, automobile and aircraft components are generally manufactured out of aluminum alloys in order to make the moving vehicle lighter, which results in saving in fuel consumption. However, the use of aluminum alloys as an antifriction material has been limited because of unfavourable wear. They tend to seize when run under boundary lubrication condition. To circumvent the above limitation i.e. to improve wear resistance, it has been proposed to disperse graphite particles in aluminum matrices. This will not only increase wear resistance, but will also ameliorate damping capacity and machinability of the base alloy. The basic problem associated with the production of aluminum-graphite composite is that the graphite particle is not wetted by the aluminum melt. Hence, for the successful entry of the graphite particles into the aluminum melt, either wettability should be induced or sufficient energy must be supplied to allow these particles to overcome the energy barrier at the gas-liquid interface. Initial attempts of producing aluminum-graphite composites have been restricted to the use of coated graphite particles either by nickel or by copper. Coating on graphite particles increases the surface energy and hence reduces the energy for complete immersion of a single graphite particle into the melt. High performance graphite fibers with axial conductivities of two to three times that of copper are being used to reinforce Al, Cu and Mg alloys in order to enhance thermal conductivity and to restrain the CTE to specified values. In the continuous spool form, high modulus, pitch based graphite fibers are expensive – on the order of $1200/lb – and require weaving to produce a functional preform architecture that could be metal or resin infiltrated that would result in the desired properties. In the woven form, the geometry and overall design capability of components is limited – mainly to niche based, high value added applications. The aluminum alloys typically used are clean modified in the crucible versions of A356 (7%Si and higher), depending upon the application. In all alloy systems, the highest conductivity values are measured from pure metals. Si is the principal precipitant in A356 type alloys and has a low solubility in Al at operating temperatures. Fortunately, Si has almost as high a conductivity as Al. Hence Al–Si alloys suffer less conductivity degradation from extensive alloying than any other system. Since Si inhibits the aluminum carbide formation by competing for carbon, the fiber

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to matrix bond is enhanced through Si to carbon bonding at the interface during contact with molten Al during the casting process. (A) Section polished parallel to the device mounting surface (in-plane or “x–y” section) (B) Section polished normal to the device mounting surface (through-plane, or “z” section) A leader in developing aluminum graphite materials is Metal Matrix Cast Composites, LLC. Figures 18 and 19 show the microstructure of graphite reinforced aluminum and some typical aluminum/graphite composite heat sinks (Table 9).

a

b

Fig. 18 SEM microstructure of milled graphite fiber reinforced aluminum (pictures courtesy of Metal Matrix Cast Composites, LLC)

a

b

Fig. 19 Picture of some aluminum and copper graphite composite heat sinks. a. Ka-band TR module housings for Boeing SpacewayTM phased-array antenna; b. Copper graphite composite IGBT base plates (pictures courtesy of Metal Matrix Cast Composites, LLC)

Table 9 Typical properties of aluminum graphite composites Composition

Al-70% graphite

Al-40% graphite

Thermal conductivity (W/mK) CTE (ppm/K) Density (g/cm3 )

200 7.5 2.46

230 4 2.4

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11.4 New Development for Microelectronics Packaging Heat Sink Materials While writing this section, we studied many papers, patents and websites. One paper summarized the latest development of packaging heat sink materials well was by Dr. Carl Zweben, Advanced Thermal Materials Consultant, Devon, Pa., and was published in Power Electronics Technology, page 40–47, February 2006. With his permission, we will quote a lot of his writings in this chapter. In this paper, Dr. Zweben classified the thermal management materials to three generations (Tables 10, 11 and 12). Table 10 Properties of the first generation of heat sink materials (table courtesy of Dr. Carl Zweben, Advanced Thermal Materials Consultant)

Reinforcement

Matrix

Thermal conductivity (W/m-K)

– – – – – – – – Copper Copper – – E-glass fibers

Aluminum Copper Invar Kovar Cu/Invar/Cu Cu/Mo/Cu Cu/Mo–Cu/Cu Titanium Tungsten Molybdenum Sn63/Pb37 Epoxy Epoxy

218 400 11 17 164 182 245–280 7.2 157–190 184–197 50 1.7 0.16–0.26

CTE (ppm/K)

Density (g/cm3)

Specific thermal conductivity (W/m-K)

23 17 1.3 5.9 8.4 6 6–10 9.5 5.7–8.3 7.0–7.1 25 54 11–20

2.7 8.9 8.1 8.3 8.4 9.9 9.4 4.4 15–17 9.9–10.0 8.4 1.2 2.1

81 45 1.4 2 20 18 26–30 1.6 9–13 18–20 6 1.4 0.1

Table 11 Properties of the second generation of heat sink materials (table courtesy of Dr. Carl Zweben, Advanced Thermal Materials Consultant)

Reinforcement

Matrix

Inplane thermal conductivity (W/m-K)

Natural graphite Continuous carbon fibers Discontinuous carbon fibers SiC particles Continuous carbon fibers Carbon foam

Epoxy Polymer

370 330

Copper

300

Copper SiC Copper

Throughthickness thermal Inplane conductivity CTE (W/m-K) (ppm/K) 6.5 10

Specific inplane thermal Density conductivity (g/cm3) (W/m-K)

–2.4 –1

1.94 1.8

190 183

200

6.5–9.5

6.8

44

320 370

320 38

7–10.9 2.5

6.6 2.2

48 170

350

350

7.4

5.7

61

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Table 12 Properties of the third generation of heat sink materials (table courtesy of Dr. Carl Zweben, Advanced Thermal Materials Consultant)

Reinforcement –

Matrix

CVD diamond – HOPG – Natural graphite Continuous carbon Copper fibers Continuous carbon Carbon fibers Graphite flake Aluminum Diamond particles Aluminum Diamond and SiC Aluminum particles Diamond particles Copper Diamond particles Cobalt Diamond particles Silver Diamond particles Magnesium Diamond particles Silicon Diamond particles SiC

Inplane thermal conductivity (W/m-K)

Throughthickness thermal Inplane conductivity CTE (W/m-K) (ppm/K)

Specific inplane thermal Density conductivity (g/cm3) (W/m-K)

1100–1800

1100–1800

1–2

3.52

310–510

1300–1700 150–500

10–25 6–10

–1 –

2.3 –

565–740 –

400–420

200

0.5–16

5.3–8.2 49–79

400

40

–1

1.9

210

400–600 550–600 575

80–110 550–600 575

4.5–5.0 7.0–7.5 5.5

2.3 3.1 –

174–260 177–194 –

600–1200 >600 400 to >600 550 525 600

600–1200 >600 400 to >600 550 525 600

5.8 3 5.8 8 4.5 1.8

5.9 4.12 5.8 – – 3.3

102–203 >145 69 to >103 – – 182

Figure 20, which plots thermal conductivity as a function of CTE, compares traditional and advanced thermal materials. Ideal materials have high thermal conductivities and CTEs that match those of semiconductors and ceramics like Si, GaAs, alumina, aluminum nitride and low-temperature cofired ceramics (LTCCs). As the Fig. 20 shows, by combining matrices of metals, ceramics and carbon with thermally conductive reinforcements like special carbon fibers, SiC particles and diamond particles, it is possible to create new materials with high thermal conductivities and a wide range of CTEs. Thermal stresses and warpage in electronic components arise primarily from different CTEs. The increasing use of lead-free solders, which have much higher processing temperatures than lead-tin types, exacerbates the problem. Note that even when liquid cooling is used, thermal stresses caused by CTE mismatches are still important. Semiconductors and ceramics have CTEs in the range of 2–7 ppm/K. The CTEs of copper, aluminum and glass fiber-reinforced polymer PC boards are much higher. Decades-old traditional low-CTE materials like copper/tungsten (Cu/W), copper/molybdenum (Cu/Mo), copper-Invar-copper (Cu/I/Cu) and copper-molybdenum-copper (Cu/Mo/Cu) have high densities and thermal conductivities that are little or no better than that of aluminum (Table 10). We call these first-generation thermal management materials. Table 10 also shows an improved first-generation material, a laminate consisting of Cu–Mo bonded to

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Fig. 20 When selecting thermal materials, the ideal solutions have high thermal conductivity and closely matched CTEs. (figure courtesy of Dr. Carl Zweben, Advanced Thermal Materials Consultant)

outer copper layers (Cu/Cu–Mo/Cu). When both weight and thermal conductivity are important, a useful figure of merit is specific thermal conductivity (thermal conductivity divided by density or, in this case, specific gravity, which is dimensionless), as introduced by Dr. Zwben and K.A. Schmidt many years ago. All of the tables in this article include this property, which can provide a good estimate of potential weight reduction (higher is better). When aluminum and copper are used for heat dissipation, significant design compromises are typically required, which can significantly reduce cooling efficiency. For example, to minimize thermal stresses, it is common to use compliant polymeric thermal interface materials (TIMs) to attach high-In response to the welldocumented needs previously described, an increasing number of high-performance advanced materials that offer significant improvements have been and are continuing to be developed. Advantages include thermal conductivities up to more than four times that of copper, CTEs that are tailorable from –2 to +60 ppm/K and a wide range of electrical resistivities. They also have extremely high strengths and rigidity, low densities, and low-cost, net-shape fabrication processes. Demonstrated payoffs include the following: improved and simplified thermal design, elimination of heat pipes, fans and pumped fluid loops, heat dissipation through pc boards, weight savings up to 90%, size reductions up to 65%, reduced cooling power, reduced thermal stresses, direct attach with hard solders, increased reliability, improved performance, increased pc board natural frequency, increased manufacturing yield, and part and system cost reductions. These materials are being used in a rapidly increasing number of commercial, aerospace and defense applications. High-performance thermal materials, which are at various stages of

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development, fall into five main categories: monolithic carbonaceous materials, metal matrix composites (MMCs), carbon/carbon composites (CCCs), ceramic matrix composites (CMCs) and polymer matrix composites (PMCs). A composite material is two or more materials bonded together. They are nothing new in electronic packaging. For example, E-glass fiber-reinforced polymer (E-glass/polymer) pc boards are PMCs. Cu–W and Cu–Mo are MMCs, rather than alloys. The numerous ceramic particle-reinforced and metal particle-reinforced polymers used for TIMs, underfills, encapsulants and electrically conductive adhesives are all PMCs. The first second-generation thermal management material, silicon carbide particle reinforced aluminum, commonly called AlSiC in the packaging industry, is an MMC that was first used in microelectronic and optoelectronic packaging by Dr. Zweben and his colleagues at GE in the early 1980’s. AlSiC has been used for some time in high-volume commercial and aerospace microelectronics and optoelectronic packaging applications, demonstrating the potential of advanced thermal management materials. At present, we are in the early stage of the third generation of packaging materials. Several of the new highperformance materials discussed in this article are being used in production applications, including servers, notebook computers, plasma displays, aircraft and spacecraft electronics, and optoelectronic systems. Considering that these materials were only commercialized in the last few years, this is remarkable progress. Materials presented include monolithic metals, highly oriented pyrolytic graphite (HOPG) and a number of composites. The composites include carbon fiber-reinforced carbon (C/C), carbon fiber-reinforced epoxy (C/Ep), carbon fiber-reinforced copper (C/Cu), silicon carbide particle reinforced copper (SiC/Cu) and traditional Cu–W. HOPG, also called thermal pyrolytic graphite and annealed pyrolytic graphite by various manufacturers, and diamond particle reinforced metals and ceramics have the highest thermal conductivities. Tables 11 and 12 present properties of several dozen selected second-generation and third-generation high-performance materials, respectively. Table 12 includes diamond made by chemical vapor deposition (CVD) for reference. For anisotropic materials, inplane isotropic and through-thickness thermal conductivity (k) values are presented. The absolute and specific thermal conductivities of the advanced materials in Table 11 and especially in Table 12 are significantly higher than those of the traditional materials in Table 10. Figure 21 shows the synthesis process for thermal pyrolytic graphite and Fig. 22 shows some typical thermal pyrolytic graphite products. Figure 22a shows a TPG design for a 60 W total Heat Dissipation module. The results showed significant improvement in heat removal and cooling of the heat sources and significant temperature reductions utilizing TPG material over aluminum in a heat spreader for a 6U CPCI module that is conduction cooled. This was designed for rugged airborne and ground applications.

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Fig. 21 Synthesis process for thermal pyrolytic graphite. (photo courtesy of Dr. Xiang Liu, Momentive Performance Materials)

a

b

Fig. 22 Picture of some parts made by Thermal Pyrolytic Graphite (photo courtesy of Dr. Xiang Liu, Momentive Performance Materials) a. Conduction cooled 6U CPCI Format module; b. TPG material to improve standard heat sink performance

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Association. Tula Polytechnic Institute. Translated from Poroshkovaya Metallurgiya, No. 8(284), pp. 20–25, Aug. 1986. Original article submitted Nov. 19, 1985 Kinetics of Densification and Growth of Refractory Phase Grains in the Liquid-Phase Sintering of Very Finely Divided Tungsten-Copper Materials: N.K. Prokushev and V.P. Smirnov. Institute of Materials Science, Academy of Sciences of the Ukrainian SSR. Translated from Poroshkovaya Metallurgiya, No. 9(285), pp. 30–37, Sep. 1986. Original article submitted Jan. 28, 1986 Kinetics of the Change of Density Distribution in Hot One-Sided Pressing of a Viscous Porous Body: L.M. Buchatskii, A.M. Stolin and S.I. Khudyaev. Department of the Institute of Chemical Physics, Academy of Sciences of the USSR, Chernogolovka. Translated from Poroshkovaya Metallurgiya, No. 9(285), pp. 37–42, Sep. 1986. Original article submitted Jan. 28, 1986 Theory and Technology of Sintering, Thermal, and Chemicothermal Treatment Processes. Structural Inhomogeneity and Localization of Densification in the Liquid-Phase Sintering of Tungsten-Copper Powder Mixtures: V.V. Skorokhod, V.V. Panichkina and N.K. Prokushev. Institute of Materials Science, Academy of Sciences of the Ukrainian SSR. Translated from Poroshkovaya Metallurgiya, No. 8 (284), pp. 14–19, Aug. 1986. Original article submitted Nov. 13, 1985 Theory and Technology of Sintering, Thermal, and Chemicothermal Treatment Processes: Sintering of Tungsten-Copper Composites of Various Origins: V.V. Skorokhod, Yu.M. Solonin, N.I. Filippov and A.N. Roshchin. Institute of Materials Science, Academy of Sciences of the Ukrainian SSR. Translated from Poroshkovaya Metallurgiya, No. 9(249), pp. 9–13, Sep. 1983. Original article submitted Jun. 30, 1982 Theory and Technology of Sintering, Thermal, and Chemicothermal Treatment Processes: LiquidPhase Sintering of Very Fine Tungsten-Copper Powder Mixtures: V.V. Panichkina, M.M. Sirotyuk and V.V. Skorokhod. Institute of Materials Science, Academy of Sciences of the Ukrainian SSR. Translated from Poroshkovaya Metallurgiya, No. 6(234), pp. 27–31, Jun. 1982. Original article submitted Jul. 31, 1981 High Density Tungsten-Copper Liquid Phase Sintered Composites from Coreduced Oxide Powders: K.V. Sebastian and G.S. Tendolkar. The International Journal of Powder Metallurgy & Powder Technology, vol. 15, No. 1, pp. 45–53, 1979 Activated Sintering of Tungsten-Copper Contact Materials: I.H. Moon and J.S. Lee. Powder Metallurgy, No. 1, pp. 5–7, 1979 Factors Affecting Tungsten-Copper and Tungsten-Silver Electrical Contact Materials: N.C. Kothari. Powder Metallurgy, International, vol. 14, No. 1, pp. 139–143, 1982 Chemically Activated Liquid Phase Sintering of Tungsten-Copper: J.L. Johnson and R.M. German. The International Journal of Powder Metallurgy, vol. 30, No. 1, pp. 91–102, 1994 Sintering in the Presence of Liquid Phase: W.J. Huppmann. The Forth International Conference on Sintering and Related Phenomena. University of Notre Dame, Notre, Dame, Indiana, U.S.A., May 26–27, 1975 Enhanced Sintering Through Second Phase Additions: R.M. German and B.H. Rabin. Powder Metallurgy, vol. 28, pp. 7–12, 1985 A Comparison of Thin Flim, Thick Film, and Co-Fired High Density Ceramic Multilayer with the Combined Technology: T&T HDCM (Thin Flim and Thick Film High Density Ceramic Module): Dr. M. Terasawa, S. Minami and J. Rubin. Kyocera Coporation, The International Journal for Hybrid Microelectronics, vol. 6, No. 1, Oct. 1983 Power Electronics Technology: C. Zweben, Ph.D., pp. 40–47, 2006 Preparation and Properties of Mo–Cu and W Cu Alloys: Xia Yang and Song Yueqing. Chinese Journal Rare Metal, vol. 32, No. 2, pp. 240–244, 2008 Influence of High Power Ball Mill Technology on Structure oc Tungsten-Copper Composites: Luo Han, Luan Daocheng, Wang Zhengyun etc. Powder Metallurgy Industry, vol. 17, No. 2, pp. 30–33, 2007 Advances in Research on Aluminum Silicon Carbide Electronic Packaging Composites and Components: Xiong Degan, Cheng Hui and Liu Xicong. Materials Review, 2006, vol. 20, No 3, pp. 111–115

Chapter 12

Technology Research on AlN 3D MCM Zhang Hao, Cui Song, and Liu Junyong

Abstract 3D MCM technology, a kind of advanced MCM, which develops on 2D MCM technology, It can provide higher density, smaller size and more functions. In order to improve the heat-sinking capability and reliability, the material of AlN with high thermal conductivity, thermal expansion coefficient matched with Si can be used as co-fired multilayer substrate. In this research, the advantages of two kinds of materials are combined as to fabricate the module of AlN 3D MCM. Keywords AlN · RF/MW Packages · 3D MCM · High temperature co-fired

12.1 Introduction Evolving from 2D MCM, 3D MCM introduces the IC chip 3D integration technology as well as multilayer interconnected technology of hi-density chip, of which the unique excellence is characterized by higher assembly density and capability, more system functions and I/O, lower power consuming and cost, and smaller size. As an important part of electronics devices, the packaging is responsible for the circuit support, protection, I/O connection, heat dissipation and shielding. The new development of electronics devices are placing more new demands on the packages and on the development of packaging materials. AlN has high thermal conductivity (7–10 times of that of Al2O3) and at the same time, it is not toxic (like BeO). At the same time, AlN’s CTE matches that of silicon. Therefore AlN is widely used hybrid IC, microwave components like X-band TR Modules and RF Power Amplifiers etc. and opto-electronics like high density LED as both packages and substrates. Currently many companies are working on developing AlN 3D packages. They are NEC, Toshiba, Tokuyama, Hughes, Natel Engineering, Honeywell and CMC. It was reported that NEC’s AlN multilayer PGA with thermal conductivity greater Z. Hao (B) East China Research Institute of Microelectronics, Hefei, Anhui, China 230022 e-mail: [email protected]

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Fig. 12.1 Sample AlN packages

than 220 W/mK was used in high power (> 40 W) emitter-coupled logic, or ECL chips. NEC’s AlN was successfully used in 30 GHz milimeter wave TR modules. This 35×35 mm HTCC package includes all necessary functions of for 28/31 GHz

Fig. 12.2 AlN based RF/MW packages, LDMOS packages, MW power amplifiers, power hybrid and AlN PGA/BGA packages by CMC Interconnect

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milimeter wave TR modules with design life of 10+ years (Fig. 12.1a). Toshiba reported a 5-layer HTCC AlN package with 70 W/mK thermal conductivity, 300 I/Os, conductor line width of 100 μm and spacing of 215 μm. The package foot print is only 48.2×48.2×2.4 mm and heat dissipation is 10 W. Compared with the original Al2O3 package it replaced, it reduced the packagesize by 75%(Fig. 12.1b). CMC Interconnect also developed a lot of AlN based RF/MW packages, LDMOS packages, MW power amplifiers, power hybrid and AlN PGA/BGA packages (Fig. 12.2).

12.2 Experiment The research adopts the high temperature co-fired method of ceramic material and W metal to fabricate multilayer substrate, on which related chips and parts are installed. Meanwhile, several 2D MCMs (≥ 4) are stacked and interconnected by clapboard holing metallization and circumjacent interconnection to fabricate stacked AlN 3D MCM. The whole process comprises of the following several aspects.

12.2.1 Co-fired Spacer Rod and 2D MCM Substrate 3D MCM structure not only needs to stack and interconnect various 2D MCM substrates, but to separate them with spacer rod and BGA solder ball, which demands high flatness of 2D MCM substrates and spacer rod, and shrinkage consistency. In practice, secure the symmetry of wire pattern in design; stack together spacer rod and substrates for the immediate success in molding; improve co-fired conductor paste; optimize sintering parameter.

12.2.2 Vertical Interconnected by BGA Solder Ball Package, assembly and vertical interconnected require a proper temperature grads and technological sequence. 3D MCM vertical connection is to be acquired by selecting hi-temperature solder ball and low-temperature solder, screening separation solder balls twice to remain the same size, utilizing the automatic contraposition effect of Pb/Sn solder and metal, using contraposition clamp for vertical interconnection.

12.2.3 AlN 3D MCM Package Kovar frame and AlN ceramic soldering are introduced to package and parallel seam welding technology is adopted to seal.

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12.2.4 Technological Method The fabrication of AlN 3D MCM substrate mainly consists of the fabrication of 2D multilayer substrate and the package of 3D MCM. The process flow of technology is schematically shown in Fig.12.3 and Fig. 12.4 below. AlN powder

Sinter Additives

Casting Additives

Mixing W powder

Slurry

Additives

Casting Mixing Green Sheet Grinding Blanking Adding Organic Vehicle Form Vias Grinding Fill Vias W paste Printing conductor Punch Cavity

Laminate

Fire

Burnout

AlN co-fired multilayer substrate

Fig. 12.3 Process flow of AlN co-fired multi-layer substrate fabrication

multilayer substrate

plating

vertical interconnection test

package

segmentatio test test

solder ball

wire bonding

chip assembly

AlN 3D MCM substrate

Fig. 12.4 AlN 3D MCM substrate assembly process flow

12.3 Result and Discussion 12.3.1 General Technological Scheme 3D MCM enjoys two forms of side interconnection and circumference interconnection. This paper focuses on the stacked form of four 2D MCM substrates to fabricate 3D MCM substrate. Circumference interconnect is taken between 2D MCMs and BGA is introduced in I/O of the whole module. This technology metalizes multilayer substrate by screen printing. Likewise, prepare a piece of clapboard slighly thicker than a chip, on which holes paralel to the marginal ones of the substrates are formed. Then, substrate and clapboard are

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stacked and co-fired together with high temperature. Afterwards, the substrate is stacked and interconnected with another one by BGA solder ball or anisotropy conductor film Fig. 12.5.

Fig. 12.5 AlN 3D MCM substrate structure

Circuit on each substrate is connected with the lower one by circumference hole or spacer rod and ultimately out from the back side of the bottom board (motherboard). At the same time, design a metal-sealed frame 2 mm wide in the outter rim of circumference hole in a motherboard surface. After plating, we weld metal lid and its frame, and then fabricate the four pieces of 2D substrate, interconnect vertically, and solder the coverboard with parallel soldering method. Thus, the whole 3D MCM substrate is sealed. The general structure is schematically shown in the Fig. 12.3.

12.3.2 Layout and Interconnect Design 12.3.2.1 2D MCM Layout Design Four pieces of the whole 3D module and the three pieces on the 2D multilayer substrate are designed identically. The motherboard is also designed identically with the others except the metal-sealed frame on the cover (see Fig. 12.6). Layout of 2D MCM is designed to be 5 layers. The top layer is the assembly one and the three layers below for layout. The fifth floor is the plating one. 132 vertical holes are evenly distributed on four sides on each floor to transmit signals from the original place to the relevant two floors above and below. The outter metalized cube is plating soldering plate and will be cut away along the metal layout frame after plated. 12.3.2.2 3D MCM Interconnected Design 3D MCM vertical interconnection is led out from one side, that is, in one direction to each 2D substrate. In assembly, the second substrate is turned 90◦ C to form a

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Fig. 12.6 Motherboard

vertical angle with the first spacer rod. Repeatedly, 3D module with 4 pieces of 2D substrate is fully utilized in four directions. During the testing, the performance of one piece of 2D substrate may be tested on each side of I/Os.

12.4 Matching Optimization Research on W paste and AlN Ceramics 3D MCM substrate requires more strictly the flatness and conductor electricity resistance of 2D multi-layer substrate, so it is necessary to have the optimization research on the matching of W paste and AlN tape. By analyzing the matching mechanism of the material with some relevant experience, we put into W different proportions of Y2 O3 CaO AlN Al2 O3 . Under 1800◦ C, the materials sinter in the same heat preservation time and temperature ascending speed. Sheet resistance to metallization, adhesion strength to tape and substrate flatness are analyzed to observe its performance and partial results are shown in Table 12.1. Table 12.1 The matching between AlN tape and various W paste Sheet Adhesion No. W (5%) AlN (%) Y2 O3 (%) CaO (%) Al2 O3 (%) resistence strength Flatness 1 2 3 4 5 6 7 8 9 10

100 97 95 90 80 95 90 85 95 88

3 5 10 20

3

2.5 5 7.5 1 3

2.5 5 7.5 1 3

3 3

Low Low Low Lower High Low Low Lower Low Lower

How Hower Higher High High High High High High High

Camber Camber Flight camber Flat Flat Flight camber Flat Flat Slight camber Flat

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We may conclude from the Table 12.1 that the more additives and sheet resistance and adhesion strength increase, the better the flatness becomes. Apparently, high sheet resistance is the last result we prefer to expect. Considering the three aspects above, we may see that W paste of No. 7,8,10 have secured fairly good experimental results and the total amount of sintering catalyst is under control within 10∼15% on average.

12.4.1 Technological Improvement Experiment of AlN 2D MCM Substrate The desigan and technological implementation of 3D MCM is a rather complicated process and a minor failure in each step may lead to the total collapse of the process. In this case, we are particularly strict in the selection of 2D substrate. The subsequent technological amelioration in sintering betters the contraposition precision and substrate flatness. Sintering has great impact on AlN co-fired substrate capability. Sintering temperature, temperature ascending speed and temperature descending speed, temperature preservation time and sintering condition are all influential to the substrate capability. AlN tape shrinks from 1300◦ C, and pure tape between 1600◦ C∼2000◦ C, W sintering temperature is no low either. Once sintering temperature is too high, on one hand, the shrinking rates of AlN and W sintering will mismatch and the subsequent stress will camber substrate, on the other hand, W will have chemical reaction with N2 C in high temperature and such compounds as WN2 WC generated increase sheet resistance. Now, we put some CaO(2%) Y2 O3 (2%) into AlN powder to decline sintering temperature. However, once the temperature is too low and W and AlN fail to sinter to a certain extent, they will not achieve the expected density. At the moment, AlN tape is characterized as darkish in color, lower in thermal conductivity and thermal insulation electricity resistance, small in shrinkage rate and density. As for W, it is inclined to becoming dark after metallization, shelling powder and falling off. Thanks to the experiment, we ultimately secure the optimal sintering temperature and resolve the above-mentioned problem. Temperature ascending speed will also affect the substrate flatness and compactness. Once the temperature ascends too fast, crystal particle will grow faster and the subsequent prompt shrinkage is detrimental to the purification of AlN tape thereby to cause substrate camber and thermal conductivity decline. Reversely, W and AlN will shrink too fast, and thermal stress will show its form apparently to camber substrate. Table 12.2 indicates the impact of different temperature ascending speed on multilayer substrate flatness. Hereby, we select temperature ascending speed 35/min. In temperature descending, we take the measure of gradual reduction of thermal electrical current. Table 12.3 demonstrates the variety between W paste, AlN tape density and the change of heat preservation time. According to the figure, W density will no longer change after around 2 h heat preservation, while AlN tape density comes to stabilize

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Table 12.2 Impact of temperature ascending speed on substrate flatness speed of temperature ascendance Speed of temperature ascendance(/min)

Number of qualified (pieces)

Number of unqualified (pieces)

Finished product rate (%)

Flatness

3 5 10

18 16 4

2 4 16

90 80 20

Fairly good Good Serious camber

Table 12.3 Variety between W paste, AlN tape density and the change of heat preservation time Time of heat preservation

0.5 h

1h

2h

3h

4h

W AlN

18.97 3.02

19.01 3.1

19.04 3.22

19.04 3.23

19.04 3.25

after around 4 h increase. Longer heat preservation time is beneficial to AlN tape purification and thermal conductivity growth. However, the more time W heat preservation occupies, the more chance it will react, increase sheet resistance and decrease adhesion strengh. Taking all the cases into consideration, 4 h heat preservation is optical [4]. Under high temperature, both AlN and W are inclined to oxygenate (AlN and W start to oxygenate above 900◦ C and 340◦ C respectively in the air). Therefore, sintering must be executed under the protection of nitrogen. Inpurity of nitrogen or lowness of gas flux will cause minor oxygenation, decline of substrate thermal conductivity and increase of W conductor sheet resistance. With the experiement, highly purified nitrogen is selected to become the protecting gas, whose flux ranges from 5 to 10 litre per min. Figure 12.7 is the sintering curve of co-fired substrate from the experiement. After the applification of ameliorated experiement technology, we secure a 2D co-fired substrate below in Fig. 12.8, whose capability meets the demand for 3D MCM substrate drawing Fig. 12.9.

12.4.2 The Making of Spacer Rod Spacer rod and 2D MCM substrate are stacked to be co-fired together. During the process, adding silicon rubber or clipped green tape to the cavity will uneven interior side and jam the space. In response, we design moulds exclusively stacking the cavity and the outer frame respectively. The slight difference between the upper moulds are not affected under the isotonic pressure. To demould easily, we install a mobile spiral shell at the top of stacked upper mould in the center. Unscrew it in stacking; screw on it in taking mould.

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Fig. 12.7 Sintering curve for co-firing AlN

Fig. 12.8 Sample of 2D MCM substrate

In making spacer rod, punch vias firstly at the rim of the pattern on AlN green tape, print, punch it into a frame and stack, deglue, sinter together with 2D MCM substrate. Due to the identical technology, contraposition prcision is improved, shrinkage consistency is ensured, a vertical interconnection is reduced and module stability is secured. Figure 12.7 shows us the made spacer rod.

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Fig. 12.9 Co-fired sample of AlN and spacer rod

12.4.3 Package Technology The package in the research adopts parallel seam welding, weld together the Kovar frame and assemblied, vertically interconnected metal seal ring, parallel seam weld lid after completion. Cosidering that tube shell soldering is proceeded after the assembly and vertical interconnection, meanwhile the thermal expansion coefficiency of AlN and Kovar differs greatly under the high temperature, we introduce low temperature Pb/Sn solder to seal with reflow soldering technology thereby to reduce this stress and increase the soldering reliability. The result proves fine and seal capability meets the needed requirement.

12.4.4 Vertical Interconnected Technology Research We seek vertical interconnection by placing Pb/Sn soldering ball on soldering pad by spacer rod. Owing to the temperature grads different from other technology, we select a solder ball at 295. Lay it down properly, stick up chips and wire bond, and then interconnect vertically. Since the metal on the Pb/Sn and solder pad secures a good soakage, it enjoys a self-alignment effect, which is beneficial to vertical interconnection contraposition. The size of solder ball fails to be identical, which may cause an empty meet in the process of vertical interconnection. What makes the matter worse is that melting condition of solder balls is not identical either and it will also bring forward short circuit among them.

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Fig. 12.10 Sample of vertical interconnection

The principle of soldering ball size selection follows that the size of solder ball is slightly smaller than solder pad. At the same time, the solder balls with the identical size have difference as well, which may cause variance on the same side, inconvenient in testing and vertical interconnection. To resolve this problem, we filtrate the size of solder balls at first to ensure the elimination of the balls with too big or too same size; secondly, by modulating the technological parameter of the balls, we

Fig. 12.11 Sample of AlN 3D MCM substrate (samples of unsealed lid and sealed lid respectively are on the left and on the right)

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may achieve the identity of the melting condition of different solder balls. The result has demonstrated us the positive aspect. Vertical interconnection contraposition demands highly on precision and handiwork contraposition is hard to be guaranteed. Therefore, we design and fabricate contraposition clamp, of which both sides are closely placed against 2D substrate rim and package inner side. Clamps are taken out after the solder. All the substrates are connected. By exploring the above-mentioned key technology, we fabricate the sample of AlN 3D MCM substrate in Figs. 12.10 and 12.11.

12.5 Result of Experiment Capability index of AlN 3D MCM samples fabricated after the research is demostrated below in Table 12.4. Table 12.4 Sample capability index of AlN 3D MCM Index project

Practical index

2 DMCM substratelayers Number of stacked layers Thermal conductance of AlN substrate I/O number of 3D package Metal adhesion strength Solderability Camber Conductor sheet resistance (surface plating Ni, Au) Wire bonding strength (25 μm Au) Chip shearing strength BGA shearing strength

5 layers 4 ≥ 172.3 W/m·k 132 ≥ 20.9 N/mm2 Good 10 μm/50 mm 6.663 m/ ≥ 6.5799 gf ≥3.21 gf > 10gf

12.6 Conclusion The research reveals the manufacturing technology of AlN 3D MCM substrate by exploring the above-mentioned key parts.

References 1. S. L. Palnmquist, R. J. Jensen, W. F. Jacobsen, and R. K. Spielberger, Design and Characterization of Three-Dimensional Aluminum Nitride Multichip Modules. IEEE Multichip Module Conference 1994:177–182

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2. K.J. Lodge et al. Prototype Packages in Aluminum Nitride for High Performance Electronic Systems. IEEE 1990 (3):103–110 3. Zhang Jingguo, Yang Bangchao. Three-Dimensional Multichip Modules. Electronic Components and Materials, 1994 (4):28–30 4. Cui Song et al. The Study on the High Temperature Co-fired AlN Multilayer Substrate Technology Hybrid Microelectronics Technology, 2000 (1):26–23

Index

A Actuator, 52–53 Antenna directivity, 139–140 far-field, 137–138, 139 horn, 46, 47–48, 55–59, 60, 62–63 near-field, 145–146 patch, 135–142, 198, 200, 201, 203 phased array, 52, 89–90, 135, 159–160, 257 tapered slot, 55 travelling wave, 148–149 B Baluns, 2, 130 Bandwidth, 1, 5, 8, 12, 20, 21, 25–42, 43–44, 50, 51, 52–53, 56–57, 59, 74–75, 80, 107, 108, 141, 145, 147, 149, 169, 198, 200–201 Bonding, 26, 45, 47, 48–49, 81, 83–84, 85, 93, 106–107, 132–133, 144–145, 149–150, 192, 196, 197, 209, 218–219, 220, 229–230, 246, 270, 278 Transient Liquid Phase (TLP), 229–230 C Calibration, 40, 103 SOLT, 40 Ceramics aluminum nitride (AlN), 16, 17, 18, 259 beryllia (BeO), 18, 215–219, 220, 221, 222, 227 CuPack, 219–220 E Materials (E60, E40, E20), 227 R properties, Thermalox 995 , 217 co-fired, 4, 15–18, 72, 90, 130, 143, 166, 189, 191–192, 210–213

high temperature (HTCC), 4, 16, 191–192, 213 low temperature (LTCC), 4, 17, 72, 130, 143, 166, 189, 210–215 DupontTM 943, 137, 140 green tape, 15–16, 192, 193 metallization, 192, 215, 217, 218, 269 thick film, 15, 18–19 thin film, 15, 18–19 Chip-scale packaging (CSP), 130 Coaxial, 8, 9, 10, 11, 26, 29, 31–32, 34, 36, 38, 40, 41, 45, 49, 55, 89, 167–169, 198, 247 Coefficient of thermal expansion (CTE), 2, 22, 118, 119–120, 122, 193, 209, 211, 212, 215, 216–217, 221, 223, 225, 226, 227–228, 229, 234, 235, 236, 237, 241, 242, 243, 244–245, 248, 251, 257, 258, 259, 267 table, 217 Composite metal matrix (MMC), 209, 215, 223–227, 248, 261 table, 225–226 D Diaphragm, 52–53 Dielectric, 2, 3, 5–10, 15, 17, 18, 19, 26, 27– 30, 33, 34, 72, 73–74, 76–77, 78, 79, 82, 85, 86, 89, 94, 120–121, 122, 123, 126, 131, 140, 142, 156–158, 166–167, 172–173, 174–175, 191–192, 193, 199, 200, 211, 215, 216–217, 218, 221–222 constant, 3, 10, 15, 17, 18, 19, 27, 33, 34, 75–76, 77, 78, 79, 85, 94, 120–121, 126, 140, 166, 167, 172–173, 193, 200, 215, 216–217, 218, 221–222

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282 Direct bond copper (DBC), 215, 216, 218–220, 223–227, 229 E Electro discharge machining (EDM) sink, 227–228 wire, 227–228 Electroplating seed layer, 46–47, 48, 58, 61 selective, 47–49, 58 Embossing, hot, 47–48, 49, 52–53, 55, 57, 58, 64 F Filter bandpass, 49, 52, 198 cavity, 198 iris, 47–48, 49–51, 52–53, 54 tunable, 51–55, 155 Flip chip, 21, 22, 26–27, 79–80, 84, 85, 90, 126, 130, 133–134, 141, 143, 144–145, 149–150, 192 Free space wavelength, 3, 174 Frequency bands (table), 3 H Heat flux (table), 209 Heat sink, 208–209, 227–228, 229, 233–262 Heat transfer (equation), 208 Hermetic, 17, 18, 19, 29, 30, 32, 72, 81, 91–112, 129, 132–133, 141–142, 191, 192, 218–219, 227 High temperature co-fired ceramic (HTCC) alumina, 16, 17, 18 aluminum nitride, 16, 17, 18 QFN, 17 thermal conductivity, 16, 17, 269 I Impedance characteristic, 5–6, 27, 36, 73–74, 76, 120, 149, 173, 186 coaxial (equation), 26 match, 26, 36, 73, 234 mismatch, 36, 74, 130 Interconnects flip chip, 21, 22, 26, 144 wirebond, 33, 41 J JEDEC standard, 33

Index L Leadframe, 25–42, 71, 83 Liquid crystal polymer for rf and millimeterwave multi-layer hermetic packages and modules bandpass feedthrough, 106–111 bandpass feedthrough design and fabrication, 106–109 bandpass feedthrough results and discussion, 109–111 design and fabrication of the thin-film LCP package, 93–96 hermeticity and leak rate measurement, 101–102 lid construction and lamination, 97–98 reliability of LCP surface mount packages, 102–106 non-operating temperature step stressing, 103 non-operating thermal shock testing, 103–105 operating humidity exposure testing, 105 reliability testing summary, 106 results and model of lowpass feedthrough, 98–101 Loss insertion (S21 ), 4, 35–36, 48–49, 53 return (S11 ), 35–36, 48–49, 53, 54 LTCC, 17, 18, 72, 80, 130, 131–135, 136, 137, 139–140, 141–145, 146, 148, 149–154, 159–160, 166, 167, 174–177, 184–188, 189–205, 210–215 conductors, 17, 191–192, 195–196 Lumped elements inductor, 3–4, 198 wire bond, 26–27 M Material(s) AlGaN, 160 GaAs, 130, 143, 215, 219–220, 221, 234, 236 GaN, 160, 236 properties, packaging (table), 236 PZT, 157 SiGe, 130 Membrane, 48, 49, 52–55, 86, 130, 161 MicroCoax, 26–42 Micro-electro-mechanical systems (MEMS) polymeric, 44, 47–48 RF-MEMS, 130, 135, 140–142, 155–162

Index sealing, 91–93, 132–133 switches, 52, 132, 145–146, 150, 155, 156–162 comparison (table), 156 Micromachined, 48, 49, 52–53, 55 Micro molding, 44–45, 47–48 Microwave, 1–23, 70, 73–74, 92, 115–128, 129–162, 189, 193, 208, 215, 220, 221, 222, 267 Millimeter-wave, 1–23, 25–42, 43–65, 69–90, 91–112, 135, 141, 142, 144–145, 165, 189–191, 193, 194, 195, 208, 222 Millimeter-wave chip-on-board integration and packaging application examples, 87–90 A 60-GHz transceiver, 88–89 76-GHz automotive radar module package, 89–90 miniaturized 60-GHz transmitter and receiver modules, 89 a chip-on-board solution, 80–87 attaching the bare chips, 83 cover lamination, 85–86 eliminating wire bonds in the rf path, 84–85 segregation, 87 the surface-mount panel, 81–83 testing, 87 wire bond interconnects, 83–84 millimeter-wave product manufacturing, 69–80 the drive for low cost, 69–70 low-cost manufacturing processes, 70–73 achieving scalability, 72–73 minimizing labor and capital cost per unit, 70–71 minimizing materials cost, 72 problems specific to millimeter-wave electronics, 73–80 the problem of cavity resonances, 78–79 the problem of distances, 73–76 the problem with encapsulants, 76–78 the problem of environmental control, 80 the problem of shielding, 78 the problem of thermal expansion mismatch, 79–80 Millimeter wave integrated circuit (MMIC), 7, 8, 30–31, 34, 38, 40–41, 42, 73–74,

283 75–76, 77–78, 79, 84, 88, 93, 97, 106–107, 145, 160, 189–191, 220 Modelling Agilent ADS, 146 electric field simulation, 58, 62–64 electromagnetic, 35–36 finite difference, 1, 22, 23 finite element (FEM), 20, 23, 62–64, 199 flow simulation, 62 frequency domain, 35–36 HFSS, 110 solid, 35 time domain, 36 Mode shape, 34 Multilayer, 72, 106–107, 117, 119, 121, 129, 130, 132–133, 143, 159–160, 175, 191–192, 200, 227, 267–269, 270–271, 273 N Nanotube, carbon, 223, 224 properties (table), 224 Network analyzer, 39–40, 48–49, 50, 53, 98, 109 P Package leadframe, 25–42 quad flat no-lead (QFN), 33, 92 surface mount, 19, 31–32, 92, 93–94, 96, 98, 99, 102–106, 107 Parasitic, 40, 94, 107, 130, 131, 144–145 Phase shifter, 45, 51–55, 135, 140–142, 155, 159–160 Plastic molding, 45 Polymer, 44, 45, 46–47, 48, 52–53, 55, 57–58, 59–64, 91–112, 191–192, 194, 258, 259–260, 261 R COC, 57–58 Topas Power devices, 2, 221, 227 Power dissipation, 2, 218, 220, 234 Printed circuit board (PCB), 7, 8, 26, 31–32, 33, 36, 39, 40, 41, 42, 72, 92–93, 95, 96, 98, 99, 100, 101, 107, 108–109, 110, 115, 116, 120, 121, 122, 123, 124, 129, 133–134, 197, 254 Q Quad flat no-lead (QFN), 17, 33, 34, 38, 40, 41, 42, 92 R Radar adaptive cruise control, 44 automotive, 70, 89–90, 142–145 collision avoidance, 44

284 Radar (cont.) vehicular, 44, 143 result of experiment, 278 Ribbon bond, 26, 81, 84, 85, 89 S Stripline, 7, 8, 10, 17, 19, 20, 33–34, 130, 133–134, 166, 167, 184–187, 198, 201 Substrate ceramic, 18, 98, 135, 140–141, 142, 196, 218, 222, 229 co-fired, 143, 166, 189, 191–192, 196, 210–213, 269 high temperature (HTCC), 16, 17, 18, 191–192 low temperature (LTCC), 17, 18, 191–192 green tape, 192, 210 thick film, 18–19, 191–192, 210–213, 222 thin film, 18–19, 210–213 organic, 19–20 Substrate material beryllia (BeO), 215–216, 217, 221, 222, 223–227 boron nitride, 216, 223 copper, 81, 215–216, 218–219, 227 diamond, 229 silicon carbide (SiC), 216, 223 Surface mount device (SMD), 130 Switches series, 156–157, 159–160, 162 shunt, 156–157, 158, 162 System-in-package (SiP), 144, 189–191, 197, see also System-on-package (SoP) System-on-package (SoP), 143 T Technology research on AlN 3D MCM experiment, 269–270 AlN 3D MCM package, 269 co-fired spacer rod and 2D MCM substrate, 269 technological method, 270 vertical interconnected by BGA solder ball, 269 matching optimization research on Wpaste and AlN ceramics, 272–278 the making of spacer rod, 274–276 package technology, 276 technological improvement experiment of AlN 2D MCM substrate, 273–274

Index vertical interconnected technology research, 276–278 result and discussion, 270–272 general technological scheme, 270–271 layout and interconnect design, 271–272 2D MCM layout design, 271 3D MCM interconnected design, 271–272 Thermal coefficient of expansion (TCE), 130, 133, 140, 141, see also Coefficient of thermal expansion (CTE) Thermal conductivity (TC) table, 193, 217, 219, 224, 236, 245, 251, 252, 257, 258, 259 chart, 214, 260 Thermal dissipation, 33, 93, 106–107, 207–231 Thermal resistance, 79–80, 130, 208, 229–230, 234 Thick film, 18–19, 221–222 Thin film, 4, 8, 15, 18–19, 93–96, 221 Through holes, 123, 132, 210, 228 Time domain reflectometry (TDR), 36 Transition, 1, 19, 20, 23, 31–32, 34, 63, 79–80, 94, 98–100, 107, 121, 167–169 Transmission line benefits, 7 coaxial, 8, 9, 11, 26, 45, 49, 55 comparison (table), 7 conductor loss, 6, 222 coplanar waveguide, 7, 8, 21 grounded, 7, 8 coupling, 13–15 cross talk, 13–15 dielectric loss, 6, 75–76, 222 dispersion, 7, 8–12 distributed effects, 12–13 drawbacks, 7 loss tangent, 6, 76 microstrip, 6, 7, 8, 9, 10, 13, 19, 184–186 bend, 13 skin depth (equation), 6 stripline, 8, 17, 19, 166, 184–186 typical uses, 7 V Vector network analyzer (VNA), 39–40 Vias, 1, 8, 15–16, 27, 31, 32, 78, 85, 86, 92, 109, 116, 117, 123, 130, 133–135, 137, 167, 174, 176, 177, 186, 192, 193–194, 199, 222, 270, 275 stacked, 133–134

Index W Waveguide coplanar (CPW), 7, 8, 21, 26, 33, 52, 98, 109, 168, 169 flange, 89 microstrip, 26, 31–32 planar, 26, 31–32

285 rectangular, 45–47, 48, 49, 52–53, 55, 57–58, 59, 166, 169–174 stripline, 33–34 Wavelength, 3, 6, 10, 12, 44, 48, 73, 74, 75–76, 78–79, 86, 108, 136–137, 165–166, 173–174, 178, 184, 189 versus dielectric constant, 3, 10, 78, 79 Wirebond, 26, 27, 30–31, 33, 41, 133, 145, 197