Solid State Technology Magazine - AUGUST-SEPTEMBER 2011

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AUGUST/SEPTEMBER 2011

Scatterometry Measurement of 28nm Metal Gates Advances in Double-patterning EUV OPC Flow Optimization

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p. 14

p. 18

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D FA B R I C AT I O N E Q U I P M E N T F O R T H E I N T E G R AT E D C I R C U I T I N D U S T R Y

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Solid State Equipment Corporation SINGLE WAFER WET PROCESSING AND CLEANING

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©2010 Solid State Corporation

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A U G / S E P T 2 0 11

Vol. 54 • No. 8

CO N T E N T S The interior of KLA-Tencor’s SpectraShape tool, which includes a multi-azimuth spectroscopic ellipsometer with broadband light extending into the deep UV portion of the spectrum and a polarized, enhanced UV reflectometer.

C OV E R A R T I C L E

F E AT U R E S CDS

11 Scatterometry measurement for gate ADI and AEI CD of 28nm metal gates Measuring CD Data show that a new generation SCD tool has good sensitivity and measurement repeatability for the 28nm HKMG ADI process. Y. H. Huang, et al., United Microelectronics Corporation,Tainan Science Park, Taiwan, C. H. Lin, KLA-Tencor Corp., Milpitas, CA.

14 Double-patterning, topcoat-less RESISTS

photoresists and silicon hard masks Double-patterning, spin-on silicon hard masks, and topcoat-less resists are enabling immersion lithography

D E PA R T M E N T S World News 6 Tech News 8 ■

Is 3D packaging where it needs to be?

Mark Slezak, Brian Osborn, JSR Micro, Inc.,

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AMAT’s DRAM fab tools for denser transistors

Sunnyvale, CA.

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Samsung-Grandis spotlights MRAM potential— and uphill climb

to meet today’s advanced technology node requirements.

Web Exclusives 2

18 EUV OPC flow optimization EUV MASKS

Ad Index 23

for volume manufacturing EUV OPC flows can be optimized to meet stringent production turn-around-time and accuracy requirements of future nodes. Kevin Lucas, Jonathan Cobb, Johnny Yeap, Munhoe Do, Synopsys Inc.,

COLUMNS

Mountain View, CA, USA

Editorial 4 RESISTS

The 450mm transition: many unanswered questions

by using EUV assist layers

Peter Singer, Editor-in-Chief

Because no single method is delivering the needed

Industry forum 24

reduction in LER, combining the benefits of an assist layer material during EUV lithography and a smoothing

Leveraging collaborations to drive down the LED cost curve

process after lithography might be the dual-prong

Jeff Desroches, ATMI, Inc., Tempe, AZ USA

21 Improving line roughness

solution that is needed. Carlton Washburn, Brewer Science, Inc., Rolla, MO USA

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Solid State Technology

ONLINE Diane Lieberman, Group Publisher Ph: 603/891-9441, [email protected]

Web Exclusives

Peter Singer, Editor-in-Chief Ph: 603/891-9217, [email protected] Meredith Courtemanche, Editor, Digital Media Ph: 603/891-9176, [email protected]

ONLINE AT WWW.SOLID-STATE.COM ___________________

Robert C. Haavind, Editor-at-Large Ph: 603/891-9453, [email protected] Debra Vogler, Senior Technical Editor, Ph: 408/774-9283, [email protected]

SEMICON WEST 2011 This year’s flagship show felt a lot more optimistic all around this year, judging by observations and comments from visitors and exhibitors and even SEMI itself. And SST was busier than ever: More than two dozen video and podcast interviews with industry execs, researchers, and analysts. Half a dozen bloggers—in addition to our own editors—reporting from all areas of the show floor and conference sessions, from 3D integration to FinFETs to EUV, and high-growth markets including LEDs and solar PV. We also rounded up of dozens of new products launched at this year’s show, from front-end processes to backend testing to components in between. Everything is online at electroiq.com/semicon_west_2011.

450mm transition: Must-know changes, cost hurdles Bill Shaner from Entegris discusses key changes in the semiconductor manufacturing industry’s move from 300mm to 450mm wafers: wafer fragility and sag, increased weight, and more capital investment. And Crossing Automation’s Bob MacKnight highlights the industry’s top three cost-related hurdles when it comes to the 450mm wafer size transition—particularly how automation will mesh with new tools.

Renesas post-quake: Rebuilt and revitalized

James Montgomery, News Editor Ph: 603/891-9109, [email protected] Laura Peters, Contributing Editor Phil Garrou, Contributing Editor Rachael Caron, Marketing Manager Cindy Chamberlin, Presentation Editor Katie Noftsger, Production Manager Dan Rodd, Illustrator Debbie Bouley, Audience Development Manager Marcella Hanson, Ad Traffic Manager EDITORIAL ADVISORY BOARD John O. Borland, J.O.B. Technologies Jeffrey C. Demmin, Tessera Technologies Inc. Michael A. Fury, The Techcet Group, LLC Rajarao Jammy, SEMATECH William Kroll, Matheson Tri-Gas Ernest Levine, Albany NanoTech Lars Liebmann, IBM Corp. Dipu Pramanik, Cadence Design Systems Inc. Griff Resor, Resor Associates Linton Salmon, TI A.C. Tobey, ACT International

EDITORIAL OFFICES

Renesas’ rebuilding efforts following the March 11 disaster are the epitome of courage, teamwork, dedication, and learning from adversity—sometimes with unexpected benefits.

PennWell Corporation, Solid State Technology 98 Spit Brook Road LL-1, Nashua, NH 03062-5737; Tel: 603/891-0123; Fax: 603/891-0597; www.solid-state.com CORPORATE OFFICERS 1421 SOUTH SHERIDAN RD., TULSA, OK 74112 TEL: 918/835-3161

CEA LETI Review CEA-LETI gave SST an exclusive look at this summer’s Annual Review, with discussions on a variety of hot topics: sustaining Europe’s semiconductor industry, IDM’s top challenges, III-V/Si integration, and maskless lithography progress.

Frank T. Lauinger, Chairman Robert F. Biolchini, President and CEO Mark Wilmoth, Chief Financial Officer TECHNOLOGY GROUP

When to outsource: Ask the right questions and avoid pitfalls

Christine A. Shaw, Senior Vice President and Publishing Director Gloria Adams, Senior VP, Audience Development

Mark Danna from Owens Design shares a critical list of questions for companies considering outsourcing a project. While outsourcing can benefit mature (semiconductor) and emerging (photovoltaics) markets, the wrong decisions or strategies can destroy all of outsourcing’s proposed benefits.

Lithography CoO, and extending with complimentary e-beam David K. Lam from Multibeam addresses lithography cost-of-ownership, and how the industry does not have to “throw out” optical lithography as it proceeds to more advanced nodes—complementary e-beam lithography (CEBL) is a strong option.

2 Solid State Technology

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EDITORIAL

The 450mm transition: Many unanswered questions

T 

he move to a larger wafer size -- from 300mm to 450mm that process engineers do to keep – has been the focus of an interesting debate for the last driving things forward,” he said. five years. The largest semiconductor manufacturing Presently, although some tools have already been introcompanies in the world – Intel, TSMC and Samsung – have duced, 450mm is still at the feasibility stage. “We don’t really been strongly advocating the move, urging equipment know if we can do it or not,” Johnson said. “Once we start suppliers to start development (which has started) and putting pilot tools in, the costs start going through the roof. SEMI to create the necessary standards (which is done). This is fairly standard. Feasibility is relatively cheap. Hopefully, Equipment suppliers have been understandably slow to we can decide one way or the other whether this will be worth embrace the change, given the long time for them to see it before we start spending cubic gigabucks on R&D.” the return on their investment during the last wafer size Another unanswered question is how many technology transition (200mm to 300mm). nodes will be left by the time 450mm wafers The move to 450mm took on are in production. Intel is starting “If 450mm is really some new urgency at this year’s 22nm in production at the end of Semicon West. Applied Materials this year or early 2012. That means going to end up being announced that it would spend that they’ll be at 7nm right after a single node product, $100 million on developing the first 450mm production fab it ain’t worth it.” 450mm tools (which some say is is slated to be in operation. “We just the cost of doing feasibility studies), hear people talking, ‘We can do 32nm, companies such as EVG and KLA-Tencor we can do 22nm with some of these tools.’ So introduced new 450mm products, and several panel sessions what? When 450mm comes into production, we’re going to were devoted to the topic. be at 14nm or 10nm or below technologies. That means we Many questions remain unanswered. Although most need EUV, immersion for mix-and-match, and probably dry people seem to agree that it’s no longer a question of “if” litho all to be economically viable,” Johnson said. “The next but only “when,” there’s still a long way to go. question we have is how many nodes do we have? How long is Speaking on one of the panels was Gartner’s Bob Johnson, conventional silicon going to keep going after we pass 10nm research vice president, semiconductor manufacturing, who level, and I don’t think anybody knows the answer to that.” noted that the move is purely a cost play, with a target goal Johnson provided an interesting look at ROI considof a 30% reduction in production costs. The problem, said erations, comparing the market and thinking during the Johnson, is that there is a fundamental conflict of interest transition to 300mm in 1997, to the way it is today. “In 1997, between semiconductor and equipment manufacturers. we were convinced, looking in our rearview mirror, that “The way it looks right now is we’ve got the opportunity to the industry growth that was going on at 17% per year was spend billions of dollars on R&D that could go for other going to continue forever. We didn’t realize that we already projects, and end up cutting the market (for equipment) passed the inflection point two years earlier, and we weren’t by about 30% going forward. This is not a heck of a lot of going to realize that for another for our five years. Now we incentive to put a lot of the R&D money out there.” know that the long term growth trend in the industry is Johnson also questioned the real cost savings that have mid single digits, somewhere around 6%/year. If you look at been gained by previous wafer size transitions. “If you look the ability of the industry to generate funding for fabs and at the 30 year period from 1980 to 2010, we had 14 major everything else, it’s much less than it was back in 300mm technology node changes, each one generating, over roughly days.” We could reasonably look at about ten nodes over a two-year period, about a 50% reduction in cost. That’s the product life of 300 mm tools. Now if we look forward, 30% per year,” he said. During that time, there were three maybe 3? Maybe one? I submit if 450mm is really going to major wafer size transitions. “Each wafer transition was end up being a single node product, it ain’t worth it.” Truer ■ about the equivalent of one year’s worth of scaling. Wafer words have never been spoken. size changes really didn’t have a lot with reduction of costs. Pete Singer What happened instead was shrinks, scaling, cleverness Editor-in-Chief in making smaller cell sizes and a lot of the other things 4 Solid State Technology

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𰁌𰁁𰁓𰁅𰁒𰀠𰁍𰁁𰁒𰁋𰁉𰁎𰁇𰀠𰁓𰁙𰁓𰁔𰁅𰁍𰁓𰀠 𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰁆𰁏𰁒𰀠𰁔𰁈𰁅𰀠𰁓𰁅𰁍𰁉𰁃𰁏𰁎𰁄𰁕𰁃𰁔𰁏𰁒𰀠𰁉𰁎𰁄𰁕𰁓𰁔𰁒𰁙

𰁑𰁕𰁁𰁌𰁉𰁔𰁙 𰁓𰁐𰁅𰁅𰁄 𰁒𰁅𰁌𰁉𰁁𰁂𰁉𰁌𰁉𰁔𰁙

𰁉𰁃𰀠𰁍𰁡𰁲𰁫𰁩𰁮𰁧𰀺𰀠𰀠𰁒𰁏𰁆𰁉𰁎𲀙𰁳𰀠𰁐𰁯𰁷𰁥𰁲𰁌𰁩𰁮𰁥𰀠𰁉𰁃𰀠𰁬𰁡𰁳𰁥𰁲𰁳𰀠𰁰𰁥𰁲𰁭𰁡𰁮𰁥𰁮𰁴𰁬𰁹𰀠𰁭𰁡𰁲𰁫𰀠𰁨𰁵𰁭𰁡𰁮𰀠𰁲𰁥𰁡𰁤𰁡𰁢𰁬𰁥𰀠𰁴𰁥𰁸𰁴𰀬𰀠𰀲𰁄𰀠𰁣𰁯𰁤𰁥𰁳𰀠𰁡𰁮𰁤𰀠𰁇𰁲𰁡𰁰𰁨𰁩𰁣𰁳𰀮 𰁗𰁡𰁦𰁥𰁲𰀠𰁍𰁡𰁲𰁫𰁩𰁮𰁧𰀺𰀠𰀠𰁏𰁵𰁲𰀠𰁗𰁡𰁦𰁥𰁲𰁬𰁡𰁳𰁥𰂮𰀠𰁳𰁹𰁳𰁴𰁥𰁭𰁳𰀠𰁭𰁡𰁲𰁫𰀠𰁳𰁩𰁬𰁩𰁣𰁯𰁮𰀬𰀠𰁣𰁥𰁲𰁡𰁭𰁩𰁣𰀬𰀠𰁡𰁮𰁤𰀠𰁯𰁴𰁨𰁥𰁲𰀠𰁷𰁡𰁦𰁥𰁲𰀠𰁭𰁡𰁴𰁥𰁲𰁩𰁡𰁬𰀠𰁵𰁰𰀠𰁴𰁯𰀠𰀲𰀰𰀰𰁭𰁭𰀮 𰁗𰁡𰁦𰁥𰁲𰁬𰁡𰁳𰁥𰀠𰁌𰁅𰁄𰀺𰀠𰀠𰁆𰁯𰁲𰀠𰁴𰁲𰁡𰁮𰁳𰁰𰁡𰁲𰁥𰁮𰁴𰀬𰀠𰁳𰁥𰁭𰁩𰀭𰁴𰁲𰁡𰁮𰁳𰁰𰁡𰁲𰁥𰁮𰁴𰀠𰁡𰁮𰁤𰀠𰁯𰁰𰁡𰁱𰁵𰁥𰀠𰁉𰁉𰁉𰀭𰁉𰁖𰀠𰁷𰁡𰁦𰁥𰁲𰀠𰁉𰁄𰀠𰁭𰁡𰁲𰁫𰁩𰁮𰁧𰀮 𰁑𰁵𰁡𰁬𰁩𰁴𰁹𲀔𰁒𰁏𰁆𰁉𰁎𲀙𰁳𰀠𰀳𰀰𰀫𰀠𰁹𰁥𰁡𰁲𰁳𰀠𰁯𰁦𰀠𰁥𰁸𰁰𰁥𰁲𰁩𰁥𰁮𰁣𰁥𰀠𰁰𰁲𰁯𰁶𰁩𰁤𰁩𰁮𰁧𰀠𰁳𰁰𰁥𰁣𰁩𰁡𰁬𰁩𰁺𰁥𰁤𰀠𰁬𰁡𰁳𰁥𰁲𰀠𰁡𰁮𰁤𰀠𰁣𰁯𰁭𰁰𰁬𰁥𰁴𰁥𰀠𰁭𰁡𰁲𰁫𰁩𰁮𰁧𰀠𰁳𰁯𰁬𰁵𰁴𰁩𰁯𰁮𰁳𰀮 𰁓𰁰𰁥𰁥𰁤𲀔𰁐𰁯𰁷𰁥𰁲𰁌𰁩𰁮𰁥𰀠𰁅𰀠𰀴𰀰𰀠𰁉𰁃𰀻𰀠𰁴𰁨𰁥𰀠𰁦𰁡𰁳𰁴𰁥𰁳𰁴𰀠𰁤𰁯𰁵𰁢𰁬𰁥𰀭𰁨𰁥𰁡𰁤𰀠𰁬𰁡𰁳𰁥𰁲𰀠𰁭𰁡𰁲𰁫𰁥𰁲𰀠𰁡𰁶𰁡𰁩𰁬𰁡𰁢𰁬𰁥𰀠𰁷𰁩𰁴𰁨𰀠𰁯𰁶𰁥𰁲𰀠𰀱𰀶𰀰𰀰𰀠𰁃𰁐𰁓𰀮 𰁒𰁥𰁬𰁩𰁡𰁢𰁩𰁬𰁩𰁴𰁹𲀔𰁒𰁏𰁆𰁉𰁎𲀙𰁳𰀠𰁯𰁷𰁮𰀠𰁬𰁡𰁳𰁥𰁲𰀠𰁴𰁥𰁣𰁨𰁮𰁯𰁬𰁯𰁧𰁹𰀮𰀠𰁗𰁯𰁲𰁬𰁤𰁷𰁩𰁤𰁥𰀬𰀠𰁡𰁷𰁡𰁲𰁤𰀭𰁷𰁩𰁮𰁮𰁩𰁮𰁧𰀠𰁣𰁵𰁳𰁴𰁯𰁭𰁥𰁲𰀠𰁳𰁥𰁲𰁶𰁩𰁣𰁥𰀠𰁡𰁮𰁤𰀠𰀲𰀴𰀯𰀷𰀠𰁳𰁵𰁰𰁰𰁯𰁲𰁴𰀮

𰁗 𰁅 𰁔 𰁈 𰁉 𰁎 𰁋𰀠𰁌 𰁁 𰁓 𰁅 𰁒

𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰁗𰁗𰁗𰀮𰁒𰁏𰁆𰁉𰁎𰀮𰁃𰁏𰁍 _______________

𰁒𰁏𰁆𰁉𰁎𰀭𰁂𰁁𰁁𰁓𰁅𰁌𰀠𰁉𰁎𰁃𰀮𰀠𰀶𰀸𰀠𰁂𰁡𰁲𰁮𰁵𰁭𰀠𰁒𰁤𰀮𰀬𰀠𰁄𰁥𰁶𰁥𰁮𰁳𰀬𰀠𰁍𰁁𰀠𰀰𰀱𰀴𰀳𰀴𰀠𰀠𰀹𰀷𰀸𰀮𰀶𰀳𰀵𰀮𰀹𰀱𰀰𰀰𰀠𰁩𰁮𰁦𰁯𰁀𰁲𰁯𰁦𰁩𰁮𰀭𰁢𰁡𰁡𰁳𰁥𰁬𰀮𰁣𰁯𰁭

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WORLD NEWS ■ BUSINESS TRENDS Americas

Semi growth outlooks less rosy for 2011

Japan

Asia Pacific

Americas Japan

Europe

Asia Pacific Europe

15% Monthly change 80% Yearly change Outlooks for 2011 semiconductor growth aren’t quite as optimistic as they were just a few months ago. IC Insights 10% 60% has halved its projection to 5% (vs. 10%), with only the OSD segment (optoelectronics, sensors, and discretes) remaining 5% 40% flat. IDC also has lowered its 2011 forecast, to the floor of its previously projected 6%-8% range, and tweaked down 0% 20% its outlook for global MPUs (9.3% vs. 10.3%) after seeing -5% 0% shipments and revenues decline -4% in 2Q11. Those overall forecast adjustments are more in line with the 5.4% the -10% -20% WSTS and SIA have been predicting, even with a -2% decline J J A S O N D J F M A M J J J A S O N D J F M A M J in 2Q11 chip sales. (Back in June iSuppli slightly raised its 2010 2011 2010 2011 outlook to 7%.) WaferNews sources: SIA, WSTS *Based on a three-month moving average What’s putting a damper on 2011 outlooks? Macroeconomic headwinds, ranging from the Japanese March 11 Worldwide semiconductor sales by region, based on a 3-mo. moving average. (Source: SIA, WSTS) disaster to Middle East unrest to continued economic uncertainty in the US and Europe. GDP growth has been slowing for about a year, notes IC Insights, though 2H11 should be “moderately rating, nor similar action looming against some EU nations. IC better” thanks to Japan’s rebound and rebuild from the March 11 Insights’ end-of-July update predicted US and EU debt crises would disaster, lower gas prices, and tax breaks. “lessen” in 2H11 to help its outlook—but that was before the S&P’s Note that these forecasts, as of press time, do not include any move, which spawned a subsequent week of multi-hundred-point long-term impact from the S&P’s Aug.5 downgrade of US credit volatility in major financial markets worldwide. ■

WORLDWIDE HIGHLIGHTS Photoresist revenues will grow at about 5% for the next several years, says Techcet Group, which says consolidation is long overdue among resist suppliers, and EUV may be the last straw. Intermolecular has inked a deal with GlobalFoundries to use its combinatorial technology on R&D for semiconductor manufacturing lines covering 45nm down to 14nm. Avantor and SACHEM have developed a new selective etch chemistry that doubles as wafer cleaner. Ajit Manocha has been appointed interim CEO at GlobalFoundries; both CEO Doug Grose and COO Chia Song Hwee are stepping aside. Surging gold prices—especially given

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recent US and EU economic turmoil— are accelerating an increase in Cu wire shipments, says Techcet. A trio of companies dominates the $3.3B set-top box IC market, which is expected to flatten out over the next few years, says ABI Research. Silicon semiconductor wafer growth was nearly flat year-over-year in 2Q11 says SEMI, noting the “impressive” unbroken supply chain in the aftermath of the Japan earthquake,. Cypress Semiconductor and UMC say they have produced working silicon on 65nm SONOS flash.

AMERICAS A temporary stand-in process used in solvent cleaning being started up for

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the first time was behind a June fire at Intel’s Fab 22 facilities in Chandler, AZ. Brazil has given CEITEC the green light for the nation’s first chip fab. KLA-Tencor has joined SEMATECH’s lithography defect reduction program, housed at the U. of Albany’s College of Nanoscale Science and Engineering (CNSE), to collaborate on several areas of EUV lithography. Veeco has dropped its CIGS tool business, saying it hasn’t generated returns soon enough. Georgia Tech researchers have used zinc oxide nanowires to create a new type of piezoelectric resistive switching device, which can be used to build self-powered nanoelectromechanical systems.

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Two execs with Varian ties have new gigs: former CEO Garry Rogerson is the new CEO at Advanced Energy, while current VSEA exec Stan Yarbro is now a FSII board member.

ASIAFOCUS SMIC has appointed Tzu-Tin Chiu as its new CEO, replacing David Wang who resigned in July. Chiu most recently was president/CEO of Hua Hong NEC.

Tokyo Electron Device and Powercast have jointly developed a cell phone chip that converts RF energy to electricity.

SPTS management has completed a buyout (enterprise value ~$200M) with backing from EU private equity firm Bridgepoint.

EUROFOCUS

EV Group is adding floorspace, equipment, and recruiting 100 workers in an expansion of its Austrian headquarters.

EV Group has released a wafer bonding system for 450mm SOI wafers; Soitec will qualify the first one this fall.

Samsung has widened its lead on in the NAND flash market to 40% market share, vs. 28% for Toshiba and 13% for Hynix, says DRAMeXchange. Samsung and Hynix also are reportedly speeding development of 2Xnm DRAM modules to ramp production by year’s end. Undeterred by two unsuccessful bids over the past decade to kick-start domestic chip manufacturing, the Indian government has launched yet another bid to attract investors for domestic chip fabs. Hitachi has rolled out enterprise-class MLC SSDs built with Intel’s 25nm NAND flash technology. A Samsung study finds no link between its chip plants and cancer, though labor advocates are challenging the study’s transparency and independence. Gigaphoton says its EUV (LPP source) debris mitigation technology now achieves 93% Sn removal. Nomura has sold all its shares in semiconductor packaging substrate maker Eastern Co. to the firm’s parent company. Renesas has divested its audio processing chip business to Murata Manufacturing. Researchers in China report a “breakthrough” in densely doping indium to give coral-like SnO2 nanostructures, for use in gas sensors. Dongbu HiTek has ramped volumes of Chinese firm BYD’s CMOS image sensors.

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TECHNOLOGY NEWS Is 3D packaging where it needs to be?

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ore than a hundred attendees gathered at a Suss Eric Strid of Cascade Microtech revealed that the company MicroTec workshop at this year’s SEMICON West (“3D is producing lithographically printed probe cards by MEMS Integration: Are we there yet?”) to hear technical experts techniques capable of 6μm sq. x 20μm high probe tips on 40μm from around the globe to present updates on the status pitch for testing dense 3D IC pads. “Such technology allows of 3D IC packaging. scalability to lower cost and finer pitches,” he said, adding that Eric Beyne of IMEC addressed the technical issues of carrier these probe cards “are being sold in research quantities.” Standard systems for 3D through-silicon via (TSV) thinning and backside pad locations are required for vendor interchangeability, and processing, pointing out that right now silicon carriers are favored “standard materials specs for pads are needed in terms of materials, over glass because: (1) the glass must be CTE matched to silicon thickness and flatness,” he reported. over a large temperature range, (2) the high cost of ground to tight TTV speciDevice Adhesive on device fication, and (3) a negative effect on 1 Device plasma-based post-grinding backside Polymer adhesive 3 Carrier processes due to its low thermal conducCarrier ZoneBONDTM carrier 2 tivity. After alignment and temporary 4 Release zone bonding, Beyne recommends the use Thin device of use of in-line metrology to insure Stiction zone bonding integrity before grinding occurs. Basic Process Flow: Rama Puligadda, division manager 5 and 6 1. Coat polymer adhesive on device for advanced materials R&D for Brewer 2. Create carrier: Release zone and stiction zone Science, indicated that their Zonebond 3. Bond face to face room-temperature debonding process is 4. User processes: Thin, pattern, etc. 7 meeting all customer requirements and 5. Remove stiction zone adhesive is moving toward full commercial intro- 6. Mount device side on film frame duction. The Zonebond process basically 8 7. Separate carrier from adhesive uses a 2.5mm ring of adhesive to hold the 8. Clean adhesive from device wafer in place for grinding and backside processing. This allows for easier subsequent debonding. The thin wafers are released from the carrier at Stefan Lutter, bonder project manager for Suss MicroTec, room temperature after mounting on a film frame. discussed the company’s open platform approach, which is capable Stephen Pateras, product marketing director at Mentor of using any of the following bond/debond technologies. They see Graphics, pointed out that TSVs can be used to create test access temporary bonding trending toward the newer room-temperature paths so that all BIST resources can be accessed on any device. (RT) release processes. Pateras also concludes that all EDA players need to support Suss’ new product introduction is a HVM debonder/cleaner line common test access infrastructures since this will be required for the new RT release processes. — Dr. Phil Garrou, contributing to stack die from difference sources. editor

AMAT’s DRAM fab tools for denser transistors

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pplied Materials debuted three systems at SEMICON West for next-generation DRAM chip manufacturing: the Centura DPN HDTM system to improve the gate insulator scaling, the Endura HAR Cobalt PVD system for high-aspect-ratio (HAR) contact structures, and the Endura Versa XLR W PVD system for reduced gate stack resistance. (Also at SEMICON West, Applied decloaked a new Vantage Vulcan RTP tool for 2Xnm with backside wafer heating, and a new deposition and UV curing toolset for 22nm interconnects.)

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Key transistor technologies, borrowed from logic devices, are helping DRAM chips achieve better performance and speed, overcoming a “memory wall:” the speed of the control circuitry that transfers data between the memory cell array and external data bus. These transistors are denser and more advanced, requiring new toolsets, Applied asserts. The Applied Centura DPN HD system incorporates nitrogen atoms into the gate insulator to improve its electrical characteristics. The high-dose gate stack system for oxynitride gate scaling is said

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products, emphasized the impetus behind the HAR Cobalt PVD chamber (Fig. 2) and the need to transition from TiSi2 to cobalt. (Listen to the interview at electroiq.com/podcasts). Cobalt replaces titanium for transistor contact metallization on the Endura Cobalt system, depositing uniform films in high-aspect-ratio contact structures with 50% lower contact resistance than titanium. DRAM devices fabbed with the lower-resisitivity element can have faster switching speed and lower power consumption, he explained. Meanwhile, the Applied Endura Versa XLR W PVD system is a tungsten-based tool that is said to offer a 20% reduction in gate stack resistivity (Fig. 3). The optimized reactor design improves consumable component lifetimes as well. Together these two products (PVD Co) replace the much cheaper TiCl4 process, which has been used for many years but has shortcomings. An interesting sidenote to the introduction of these products is that using PVD instead of CVD runs counter to industry expectations. — D.V.

Provides control for on/off state

Polysilicon gate

Insulates gate electrode from channel

Oxynitride Silicon

Drain

Source Channel

Nitrogen content

Carriers

Figure 1. The gate dielectric/oxide. Decoupled plasma nitridation enables high surface nitrogen content. (Source: Applied DRAM HAR cobalt PVD High aspect ratio PVD for 2x DRAM

Aspect ratio ALPS step coverage Co → 65nm Step coverage requirement 50nm

35nm

120nm

1:1

≥7:1

≤3:1 Aspect ratio

AN EXCITING NEW CONCEPT IN PLASMA TECHNOLOGY

PLASMA-PREEN“

Figure 2. Logic-derived expertise for fast DRAM implementation.(Source: AMAT)

to increase DRAM periphery speeds, which enhance DRAM output. The HD technique builds on Applied’s decoupled plasma nitridation (DPN) technology for advanced logic and memory fab. Decoupled plasma nitridation enables high surface nitrogen content (Fig. 1). Higher nitrogen content leads to higher capacitance, thus enabling equivalent oxide thickness (EOT) scaling, explained David Chu, global products management at Applied Materials. The ot her members of the Normalized resistivity product t rio addressing 2Xnm Versa PVD DRAM scaling challenges are the Endura HAR Versa XLR PVD Cobalt PVD tool 20% reduction for periphery contacts, and the Endura Versa XLR W PVD tool for memory 1000 1250 0 250 500 750 gate electrodes. Thickness (Å) Kevin Moraes, director of product Figure 3. The Versa XLR W PVD chamber enables lower gate resistance required for 2Xnm. management for (Source: Applied Materials) metal deposition

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Manufactured from a Microwave Oven Hybrid Cleaning-Ceramic Cleaning Wire Bond Pad Cleaning Die Attach Pad Cleaning Epoxy Bleed Removal Flux Residue Removal Photo Resist Removal Surface Preparation for Welding, Soldering and Inking

Plasmatic Systems, Inc. 1327 Aaron Road North Brunswick, NJ 08902 TEL: (732)-297-9107 FAX: (732)-297-3306 Email: [email protected] www.plasmapreen.com

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TECHNOLOGY NEWS

c o ntin ue d fr o m p a g e 10

Samsung-Grandis spotlights MRAM potential—and uphill climb Korean semiconductor giant Samsung Electronics has acquired Grandis, a maker of spin-transfer torque random access memory (STT-RAM), a flavor of magnetic random-access memory (MRAM). The only details disclosed were that it closed in July, covering “the full scope” of Grandis technology, assets, and HR, and will be folded into Samsung’s memory chip R&D operations. MRAM’s promise is for its nonvolatility, power efficiency, and operation at ultrahigh speeds, for applications requiring highdensity memory or lower power consumption (e.g. smart phones). It’s also touted for its scalability, beyond 32nm or whenever current memory technologies finally lose steam. However, current memory technologies have continued to scale well enough to keep such next-gen memory technologies at bay—Intel famously said back in 2003 that NAND flash wouldn’t be able to scale past the 60nm node, and now it’s at 20nm and counting, notes Jim Handy from Objective Analysis, and Toshiba/Sandisk reportedly have a 19nm device dubbed “1X” and another called “1Y” in the works suggesting another node in the hopper. Perhaps this Samsung-Grandis deal is no more than IP positioning, “a preemptive move by Samsung to secure potential IP and technology in the MRAM arena, and not necessary representing a significant

move forward in bringing the technology to mass production,” says Michael Yang, principal analyst for memory and storage at IHS iSuppli. Note that Toshiba and Hynix recently announced their own MRAM partnership, aiming to eventually create a production JV and cross-license patents, joining forces to minimize risk and accelerate MRAM’s pace toward commercialization. Hynix CEO Oh Chul Kwon called MRAM “our next growth platform,” while Toshiba’s Kiyoshi Kobayashi pledged to “strongly promote initiatives” integrating products from MRAM to NAND to HDD. Keep in mind that Samsung already has put its bet down on phasechange memory (which it calls PRAM), and claims to be shipping actual devices. (Others touting improvements in PCM over the past few months: an IBM/industry/academia consortia, Numonyx/Micron, Samsung, and KAIST.) Buying Grandis suggests Samsung is at least covering its IP bases in next-gen memory tech—or maybe it’s even an outright change of strategic direction, Handy speculates. In the end, it all comes back to scalability. As long as memory makers continue to extend existing memory technologies’ limits—and at higher volumes and lower costs—next-gen memory technologies won’t get the hard push they need to prove manufacturing costcompetitiveness and achieve commercialization. — J.M.

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MEASURING CDs

Scatterometry measurement for gate ADI and AEI CD of 28nm metal gates E XECUTIVE OVERVIEW

enhanced ultra-violet reflectometer (eUVR). The multi-AZ and multi-channel capabilities of this new tool promised enhanced critical parameter sensitivity and reduced correlation between parameters. We planned to gather data from process of record (POR), focus-exposure matrix (FEM) and design of experiment (DOE) wafers to characterize the performance of this new SCD tool on metal gate ADI and AEI structures. We also planned to compare metal gate AEI scatterometry measurement results to transmission electron microscopy (TEM) reference measurements. This evaluation process was designed to demonstrate the ability of this new-generation scatterometer to serve as a production process monitor for complex metal gate structures at the 28nm node and beyond.

For reduced gate leakage and enhanced device performance, many IC manufacturers utilize novel metal gate technologies instead of traditional poly silicon gates. The new materials and geometries required to form metal gates mean that new parameters control the optimization of device performance [1]. Traditional gate process control has relied heavily on scatterometry for ensuring that variation in structural dimensions remain in control, as some dimensional deviations can strongly affect device performance. A new-generation scatterometry tool with multiple extensions to traditional scatterometry technology is evaluated as a production process monitor for complex metal gate structures at the 28nm device node and beyond.

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nline control and monitoring of the dimensions of the high-k metal gate (HKMG) structure are critical for device performance [2]. This paper focuses on dimensional measurement and control of a 28nm high-k metal gate for two layers: after-develop inspection (ADI) and after-etch inspection (AEI). For ADI, critical measurement parameters include side wall angle (SWA) and critical PR dimension (CD). The ADI structure is very challenging for traditional HM_HT BARC2 scatterometry measurements because the six different films under the photoresist (Fig. 1a) result in high correlation among measurement HM_recess BARC1 parameters. For the AEI process, nanometer-sized variations in the Poly_TCD high-k and metal gate recess relative to poly Si width (Fig. 1b) affect Poly_HT device performance [3]. This recess represents another challenge Poly_WA HM for traditional scatterometry tools because nanometer-sized variations are difficult to detect. To qualify for production process control Poly MG_recess of these structures, the metrology tool must not only be sensitive MG to variations in all key structural parameters, but also be precise, Si HK_recess HK non-destructive, and capable of production-worthy throughput. Critical dimension scanning electron microscopy (CD-SEM) Figure 1. a) ADI model and stack information; and b) AEI model and parametric description nearly qualifies—except that not just CD but also shape metrology for HKMG. is required. Scatterometry emerges as the only near-term option. We decided to evaluate a new-generation spectroscopic critical Experiment and results dimension (SCD) metrology tool, KLA-Tencor’s SpectraShape High-k metal gate ADI. The first study was designed to determine 8810, to determine if it had the sensitivity and precision required the sensitivity and precision of scatterometry measurement for a for measurement of critical parameters on metal gate structures. 28nm high-k metal gate ADI layer. Two wafers were used in the study. The new tool’s core technologies include a multi-azimuth (“multi- The first was exposed with a focus-exposure matrix (FEM), while AZ”) spectroscopic ellipsometer with broadband light extending the second was exposed with constant, standard (POR) lithography into the deep UV portion of the spectrum [4] and a polarized, conditions. For the same DOE conditions, there were two targets in one field: one for an NMOS structure and a second for a PMOS structure. AcuShape2 advanced modeling software was used to Y. H. Huang, C. H. Chen, K. Shen, H. H. Chen, C. C. Yu, J. H. Liao, United Microelectronics Corporation, Tainan Science Park, Tainan County 741, Taiwan, R.O.C. C. H. Lin, break the parameter correlation. The floating parameters used in KLA-Tencor Corporation, One Technology Drive, Milpitas, CA, USA the model (the measurement parameters) include the critical param-

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Measured CDs continued from page 12

SCD NMOS PR MCD Bossung curve E+1

MCD (nm)

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Figure 2. MCD as function of focus and exposure for NMOS target (top) and PMOS target (bottom).

eters photoresist height (PR_HT), middle CD (MCD) and sidewall angle (SWA); plus the heights of BARC1, BARC2, hardmask and poly. The scatterometry measurement requirements included: 1) dynamic precision <0.1nm or <0.1degree; 2) sensitivity to dose and focus on the FEM wafer; and 3) baseline wafer verification. The MCD measured by scatterometry versus focus and energy exposure for both NMOS and PMOS targets are displayed in Fig. 2. The Bossung curves for the NMOS and PMOS structure indicate that scatterometry has good sensitivity to focus and exposure variations during photolithography. The MCD and SWA of whole wafer map plots for the FEM wafer and the baseline wafer are shown in Fig. 3. The wafer maps show that MCD decreases from left to right for both NMOS and PMOS targets and the SWA is increasing from left to right. These results are consistent with the FEM DOE pattern. For the baseline wafer there is no clear pattern observed, as expected. The dynamic precision of MCD, SWA and resist height (PR_HT) was measured on the baseline wafer: ten repetitions with wafer load and unload for 11 sites. The results showed that scatterometry has excellent precision with a demonstrated 3 sigma of less than 0.1nm for MCD and resist height, and less than 0.1 degree for SWA. High-k metal gate AEI. To demonstrate the new tool’s sensitivity and precision for the HKMG AEI profile, seven DOE wafers with varying process conditions were prepared. The DOE wafer varied three critical parameters, metal gate recess (MG_recess), high-k recess (HK_recess) and poly side wall angle (SWA), and two non-critical parameters, poly Si CD and hard mask (HM) height

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Figure 3. Wafer maps of MCD and SWA for DOE wafer and baseline wafer.

(Fig. 1b). The scatterometry measurement requirements for this HKMG AEI process layer were: 1) dynamic precision <0.1nm or <0.1 degree; 2) metal gate and high-k DOE sensitivity; and 3) correlation to the TEM reference measurement. The high-k recess and metal gate recess are the most critical parameters in this application. Because the metal gate and high-k layer thickness under poly is very low, the sensitivity of the scatterometer to variations in the MG and HK recess is also very low. To improve the scatterometry measurement sensitivity and precision for the HK recess and MG recess, the multi-AZ and multi-channel approaches were used. 2D contour maps of MG recess and HK recess revealed that the variations in MG recess and HK recess across the wafer were within 1nm and followed a concentric pattern. The edge of the wafer had a higher MG recess and a lower HK recess. HK recess and MG recess data from all DOE wafers showed that the SCD tool was able to recognize the MG recess and HK recess DOE splits. Poly BCD and SWA data were also collected for all wafers on the DOE list. The results showed that the new tool is able to distinguish poly BCD and poly SWA DOE splits. The dynamic precision of critical parameters for HKMG AEI was measured on the POR wafer. As before, the 11-site measurement was performed ten times with wafer load and unload. The results showed that the tool has excellent precision for the critical parameters. The average of 3 sigma dynamic precision is less than 0.05nm for MG recess, 0.07nm for HK recess and less than 0.03 degree for SWA. Metal gate AEI: correlation to TEM. To verify in-line scatterometry measurement accuracy, a transmission electron microscope (TEM) was used as a reference. The TEM measured two sites on each wafer, at the center and at the edge, for a total of 14 TEM data points in the DOE wafer set. The scatterometry measurement values were compared with the corresponding TEM values. The MG/HK CD and MG/HK recess results are shown in

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TEM (nm)

MG CD

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y = 1.0267x – 0.4459 R2 = 0.9763

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TEM (nm) 1.6 y = 0.9761x + 0.4332 1.4 R2 = 0.9617 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -1.0 -0.5

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TEM (nm) 35

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Figure 4. MG/HK CD and MG/HK recess correlation between SCD tool and TEM reference.

Fig. 4. The R 2 correlation of metal gate CD and high-k CD is about 0.97 and the slope is around 1.05. MG recess and HK recess are the most critical and challenging parameters. The SCD correlation with TEM shows an R 2 greater than 0.96 for MG recess and 0.95 for HK recess, and a slope around 1.0 +/- 0.03. For all critical parameters the R 2 correlation was greater than 0.95 and the slope was 1.0 +/- 0.05. These TEM correlation results confirm that the new generation SCD tool can be used as an in-line monitor for the 28nm high-k metal gate etch process in production. Conclusion As semiconductor structures become increasingly complex, they require ever more sophisticated metrology for characterization and process control. A new-generation SCD tool combines multi-AZ and multi-channel optical signals, providing the metrology performance required for advanced structures in metrics such as precision and accuracy. Data presented in this paper has demonstrated that this new tool has good sensitivity and measurement repeatability for the 28nm HKMG ADI process. For AEI, this tool has the sensitivity to track DOE conditions, and the measurement results correlate very well with the reference TEM measurements. With its high sensitivity, high throughput, and nondestructive measurement capabilities, the new scatterometry dimensional metrology system has proven to be suitable as a 28nm HKMG ADI and AEI process monitor. ■

Acknowledgments The authors thank Xiafang (Michelle) Zhang, Russell Teo, Zhi-Qing (James) Xu, Sungchul Yoo, Chao-Yu (Harvey) Cheng and Jason Lin of KLA-Tencor Corporation for their contributions to this article. A more detailed version of this manuscript originally appeared in Metrology, Inspection, and Process Control for Microlithography XXV, ed. Christopher J. Raymond, Proc. of SPIE Vol. 7971, 79712O, 2011. References 1. M. Sendelbach, A. Vaid, P. Herrera, T. Dziura, X. Zhang, A. Srivatsa, “ Use of multiple azimuthal angles to enable advanced scatterometry applications,” Proc. SPIE Vol. 7638, (2010). 2. M. Sendelbach, W. Natzle, C.N. Archie, B. Banke, D. Prager, D. Engelhard, J. Ferns, et al., “Feedforward of mask open measurements on an integrated scatterometer to improve gate linewidth control,” in Metrology, Inspection, and Process Control for Microlithography XVIII, edited by Richard M. Silver, Proc. of SPIE Vol. 5375 (SPIE, Bellingham, WA 2004) pp. 686-702. 3. N. Collaert, M. Demand, I. Ferain, J. Lisoni, R. Singanamalla, P. Zimmerman, et al., “Tall triple-gate devices with TiN/HfO2 gate stack,” 2005 Symp. VLSI Tech. Dig. of Papers, paper 7A-2. 4. T. G. Dziura, B. Bunday, C. Smith, M. M. Hussain, R. Harris, X. Zhang, J. M. Price, “Measurement of high-k and metal fi lm thickness on FinFET sidewalls using scatterometry,” Proc. SPIE Vol. 6922, (2008).

Contact author Yu-Hao Huang is a senior engineer at United Microelectronics Corporation, Tainan Science Park, Tainan County 741, Taiwan, R.O.C.; ph.: 886-6-5054888 ext.11637; email [email protected]

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RESISTS

Double-patterning, topcoat-less photoresists and silicon hard masks is exposed twice, using either different or offset masks, and/or altogether different illumination conditions. Dual-tone resists. These photoresists have both positive and negative tone aspects, which are patterned based on the relative exposure dose, being cross-linked (negative tone) in high dose areas and positive tone in lower dose areas. Self-aligned spacer. This typically involves patterning a semidense pitch (1 line to 3 spaces) using a conventional ArF or ArFi (immersion) resists, followed by either chemical-vapor he semiconductor industry is relying on materials innovation deposition (CVD) or spin-on SiO2, which creates an oxide layer more and more as we begin to run into fundamental limits atop the resist pattern. The top of the resist pattern is revealed via of physics. Photolithography anxiously awaits the implemen- etch, then the photoresist removed, leaving an equal line space (1 tation of EUV, as its 13.5nm wavelength line 1 space, 1:1) relief image of light will allow lithographers to work under of oxide as the final, transmore relaxed k1 imaging. The reality, however, ferred pattern. Depending on is that there are many challenges associated the mask layout, an additional 1st litho. with EUV, such as light source reliability, lithography step (often called masks (and the ability to inspect them), photoa cut mask) is needed to trim resist sensitivity and line edge roughness. The the ends of the lines that were good news is that EUV is making strides deposited with SiO2. Litho-etch, litho-etch and the first full-field EUV tools are being (LELE). This technique is delivered now. The bad news is that it will Post develop bake perhaps the least time and be awhile before the lithography community cost effective, but easiest to relies on EUV as the workhorse solution for immediately implement. critical layer lithography. The LELE process does two complete lithography and Double-patterning 2nd litho. etch sequences for a single Double-patterning is a technique that has device layer. While lengthy served well as an interim process between and costly, it can be done now ArF immersion and EUV. Double-patterning with existing materials, tools has taken on many mantles within the lithogFigure 1. Thermal freeze double-patterning cuts down on processing steps and and mask sets. raphy community, but at its most basic, it is two provides a better overall cost of ownership over many other double patterning The primary technique for patterning steps done for one layer. There are techniques. double-patterning is: the first a variety of ways to accomplish this, such as: resist is patterned in a typical Double-patterning. This technique uses two resists and two consecutive sequences of resist patterning, lithography process, and will then have the second resist coated directly on top of it and subsequently patterned – hence, the double exposure and development. Double exposure. In this technique, the same photoresist layer patterns. However, this means that there cannot be any chemical intermixing due to solvent or chemical component miscibility Mark Slezak, Brian Osborn, JSR Micro, Inc., Sunnyvale, CA USA between the first and second resists. E XECUTIVE OVERVIEW

Double-patterning has allowed us to push the limits of 193nm imaging, and is where leading edge photolithography stands today. The blend of incredibly low k1 imaging, improvements in scanner alignment capabilities, the ability of mask houses and designers to provide extremely complicated pattern stitching, and the move toward one directional mask layouts, have all paved the road for new and exciting materials solutions in double-patterning. The integration of double-patterning has also allowed more opportunities in the ancillary area of specialty materials with technologies such as spin-on hard masks, freezing/shrinking/slimming agents, along with immersion topcoats and topcoat-less resists.

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Layer 1

24.85nm

Layer 2

54.44nm 31.95nm

50.89nm

Figure 2. This figure demonstrates the use of thermal freeze where line 1 and line 2 are 32nm features at a 64nm pitch.

Chemical freeze reagents/thermal cure resists Two compelling methods to minimize the potential for intermixing in double patterning are the use of chemical freeze reagents or thermal cure resists. Chemical freeze employs a separate material that is dispensed on the first resist pattern, cross-linking (“freezing”) the outside or entirety of the resist. A thermal cure process is where the first resist can be effectively cross-linked, or otherwise rendered solvent insoluble, with a high temperature bake after initial patterning is complete. The thermal route is more advantageous than chemical freeze within a manufacturing environment, as the introduction of an additional bake step (and subsequent cool step) is the only process change necessary for thermal cure (Fig. 1). Recent work with the thermal freeze method using JSR thermal curable first resist, and the specially designed second resist, was presented at the 2011 SPIE Advanced Lithography conference. Initial pitch split work at a targeted 64nm pitch was demonstrated, showing the capability and robustness of the designed system (Fig. 2). Work at smaller pitches and tighter CDs is ongoing.

hence process cost. There can also be tool or even infrastructure costs associated using with this process. Whereas NTD can show significant improvements in conventional resist patterning schemes, it can be more powerful in a double-patterning process. Low k1 imaging that was previously too difficult in single patterning, let alone double-patterning, can be accessed with NTD and then further sized down with doublepatterning. The combinations of techniques available for doublepatterning (thermal cure, chemical freeze, LELE, NTD, et al) make it a very attractive choice for manufacturers trying to bridge the gap between immersion and EUV.

Immersion resists and topcoat materials An immersion topcoat is an additional layer atop the photoresist that protects the scanner from possible contamination. Additionally, this topcoat is used to manage the wafer / scanner interface through the manipulation of the contact angle of the film that comes in contact with the water lens from the immersion scanner. While, topcoats are in wide use today, there can be technical and economic drawbacks. Most topcoats are somewhat acidic and this can create more dark Negative tone development Finally, negative tone development (NTD) is a relatively new loss or resist top rounding of the profile. The extra processing steps technique that is showing much promise in double-patterning. incurred by the topcoat use are not minute and must be taken into Instead of the usual tetramethylammonium hydroxide (TMAH) consideration for throughput of a process flow. Finally, the cost-ofdeveloper used in lithography, an organic solvent is used instead. ownership of topcoats must be acknowledged: they add extra cost to Photoresists that are traditionally rendered soluble in the exposed an immersion process due to use of an additional material. However, areas are instead soluble in the unexposed areas, leaving a negative these upfront costs can be balanced against the preservation of tone image of a positive tone resist. It takes some time to navigate the immersion tool integrity, overall lower defect counts, and the and conceptualize this new NTD technique with the milieu of double enabling of a higher resolution patterning process that ultimately patterning schemes, but NTD shows strength in theory and practice. yields less expensive device production. Beyond the use of topcoats is the advent of topcoat-less We have found that an NTD process can work better than positive tone develop (PTD) in certain cases, such as contact holes, due to resists (Fig. 3). Here, no topcoat is used, but the photoresist the higher aerial image contrast seen for these features. This “bright is still qualified as immersion-capable with similar or better field” application has a better aerial image than does the conven- levels of defectivity and tool protection. The solution lies in the tional contact hole, which is done on a mask area with high chrome engineering of the topcoat-less photoresist formulation, which, if coverage (“dark field”). The downside is that using solvent as done correctly creates an in situ topcoat. Topcoat-less immersion photoresists have the same set of developer automatically incurs an initial increase in materials, and

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Resists continued from page 15

RCA behavior RCA (deg)

Conventional non-topcoat photoresist

Modified non-topcoat photoresist

Total defects: ~10,000

Total defects: ~500

After SB After dev.

Figure 3. By tuning the contact angles of topcoat-less resists, material companies are able to improve the defect density seen on wafer post develop.

Non-topcoat process

Topcoat process

Water

Water

Topcoat Topcoat Resist

Non-topcoat resist

Pros: Allows conventional ArF resist chemistry use Cons: Adds an additional process

Pros: Shorter process cycle time Cons: Need to develop immersion specific resist

Figure 4. A summary of the pro’s and con’s of the use of topcoat in immersion lithography vs. the use of topcoat-less resists

requirements and properties as a photoresist that requires a topcoat but come as an added component to the resist and does not necessitate extra track processing steps to create an immersion barrier. However, while the economical cost benefits are readily apparent, technical challenges exist for topcoatless resists. Examples of these challenges come in the need to precisely engineer the receding contact angle (RCA) of topcoatless photoresist films to match the needs of advanced immersion tools sets and their scan-speed requirements of >500mm/s, while still making the film hydrophilic enough after exposure to have favorable dissolution rates in TMAH developer (Fig. 4).

is used, relies a great deal on advanced etch techniques to transfer resist, self-aligned spacer (oxide) or thermally/chemically cured resist patterns into the desired substrate. A simple bottom anti-reflective coating (BARC) does not typically offer sufficient etch resistance or selectivity for any of these processes. One solution to these issues in immersion lithography and doublepatterning is to use a hard mask directly beneath the photoresist that functions both as a pattern transfer layer and an antireflective material. Usually, a BARC layer provides reflectivity control, but it does not always have the necessary etch resistance. Ideally a siliconcontaining layer with good reflectivity control would work best and such materials have been implemented in advanced development Spin-on silicon hard masks lithography groups around the world. As numerical apertures (NA) and ultimate resolution increase, depthThe spin-on silicon anti-reflective coating (or SiARC) material of-focus decreases, often leading IDM lithography layer owners to is placed between the resist and an underlying organic planarizing reduce photoresist thickness to gain back focus depth. This leaves less layer, also called carbon underlayer, forming a tri-layer scheme for etch resistance for the pattern transfer into the underlying substrate. ArF immersion lithography processes. The optical properties for the continued on page 22 The aforementioned double-patterning, depending on which scheme

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EUV MASKS

EUV OPC flow optimization for volume manufacturing • Long-range exposure position-dependent and scan-dependent asymmetric flare effects modified by flare apertures in the scanner [6,7]; and • Shadowing effects from the interactions of mask absorber topography and the non-normal main optical exposure angle which varies across the reticle [3]. There are a number of technical challenges in adapting OPC for long-range effect correction. The radius over which flare and shadowing effects are calculated may be in the 20+mm range compared to the typical OPC kernel range of 1-2μm. Brute-force methods of incorporating these long-range effects into OPC will not be fast enough to meet the turn-around-time (TAT) requirements of mask synthesis flows. For flare, clever approximations are required to speed up the computations while achieving accuracy requirements of approximately 0.10% 1σ flare error for development applications and 0.05% 1σ flare error for production. Additional reticle scale and scanning-dependent flare and shadowing effects must also be accurately encapsulated into compact models, which can run quickly on extremely large layouts.

E XECUTIVE OVERVIEW

Extreme ultraviolet (EUV) lithography is a leading contender for patterning of the 2X node memory and 14nm logic manufacturing and will provide significant relaxation in k1 factor versus existing 193nm lithography. However, EUV does add additional difficulties to mask synthesis flows such as across-slit shadowing variation, across-reticle flare variation, new resist effects, and significant increases in file size. This article will investigate EUV-specific issues and solution options for a production mask synthesis flow, including different correction and flow automation approaches. Improved methods help enable EUV optical proximity correction (OPC) tapeout flows to achieve comparable or better metrics than existing 193nm lithography flows.

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he 14nm logic node will have features at a minimum half-pitch of approximately 24 to 28nm, and the industry’s first highvolume manufacturing (HVM) for these nodes will likely start in 2015. Several 1.35NA 193nm optical lithography options have been considered for patterning at the 14nm node, including double patterning, triple patterning, and self-aligned double patterning. Another option is to lower the light wavelength to 13.5nm with 0.32NA EUV scanners. This enables relatively high k1 lithography and may offer the resolution required for the 10nm device generation by increasing projection system numerical aperture (NA). With leading semiconductor manufacturers receiving beta EUV scanners in 2011-12, the pace of EUV integration development EUV mask synthesis full flows and issues will rapidly accelerate. Therefore, the demand for accurate and fast There are several major OPC issues that result from correction EUV OPC software to synthesize reticle patterns will substantially of significant long-range physical effects. One issue is that each increase in the near future. However, there are several flow issues chip placement is now lithographically distinct and must receive a to resolve before OPC is ready to meet integration and production unique OPC modification. For reticles with only one or a few placeneeds. This article will examine those flow issues and some state-of- ments of a very large chip, the impact on OPC is not great. However, the-art solutions [1]. for the typical case where there are many placements of a mediumsized or small chip, the impact on OPC is very large, i.e., many Introduction to EUV OPC chips will have to be OPC processed in order to define a reticle. A There are several new physical effects that need to be considered in related issue is that we can no longer assume multiple placements of EUV OPC. Several of the most important are: a single cell inside a chip design are lithographically identical. This • Long-range flare (scattered light from roughness in the lens is due to the different magnitudes of flare and shadowing effects elements), which varies in intensity across the exposure field [2-4]; across each individual chip placement. The combination of these • Long-range reflected light from the large EUV mask absorber two issues results in the requirement that OPC must produce a final regions at the edges and corners of the exposure field, which are post-OPC data file with little or no design hierarchy (i.e., flat) that in between the reticle bladed-off region and the desired exposure covers the entire exposure field of the reticle. The resulting TAT and post-OPC file size will then be much larger than is typically area [5]; handled with OPC for 193nm lithography. A flow diagram of a typical EUV mask synthesis total flow is Kevin Lucas, Jonathan Cobb, Johnny Yeap, Munhoe Do, Synopsys Inc., Mountain View, CA, USA shown in Fig. 1. This flow includes the following steps: pre-OPC

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OPC improvements for EUV Significant improvements are needed to enable EUV mask synthesis flows to meet overall TAT requirements. Improvements in TAT can be obtained by optimizing the methods used to compute new EUV physical effects. To illustrate this, several different methods were investigated for EUV flare computation across the reticle (e.g., [1,2, Input design received, pre-OPC, tiling, etc.

Reticle layout defined, flare map created

OPC with MB shadowing and MB flare

EUV reticle verification

Mask data prep and fracture

FTP to mask shop

Buried defect avoidance per mask blank

Figure 1. Typical EUV mask synthesis flow containing pre-OPC, OPC, OPC verification, MDP and EUV mask defect avoidance steps. Sample graphical examples for each flow step are shown at right. [1] Used with permission of SPIE.

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Y

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X

X

Figure 2. Example of a new mask-based shadowing compensation methodology. The different wafer contours across the reticle slit for the same input mask pattern can be clearly seen. [1] Used with permission of SPIE.

9-10]) and a method implemented that exhibited both high accuracy and speed. Accuracy was benchmarked against a rigorous lithography EUV simulator’s full-chip flare computation for different layouts. The flare error between the OPC model computed flare and the rigorous simulator was found to be lower than the production target accuracy of 0.05% 1σ for a scanner with a flare TIS of 4.5%. This method of flare calculation can enable recalculation of the flare map in just a few minutes from a density map. Increasing speed without sacrificing model accuracy is possible by optimizing long-range shadowing modeling. Figure 2 illustrates a new faster mask-based shadowing compensation methodology. This method enables fitting both the ideal shadowing bias across the reticle scan and empirically observed process and tool specific characteristics. These shadowing model speedups and accuracy enhancements also benefit the full-reticle, full-model-based OPC verification step. New EUV mask synthesis flows to improve TAT The TAT improvements described above offer significant benefits for individual components in the mask synthesis flow. However, further improvements are necessary to make up for a) the large increases in TAT flow expected due to the full flattening of reticlelevel data as input to OPC; and b) the very large data files, which take considerable time to be passed between components in the flow. Another problem with the large data files in EUV is that any steps in the flow that are not highly distributable (across many processor cores) quickly become bottlenecks and begin to dominate the overall TAT. MDP/fracture tools do not distribute linearly to many hundreds of processors, as OPC does. In addition, read-in/ out steps of tools are generally poorly distributable. Therefore, as data volumes continue to rise into multiple terabytes of data per layer [11], lower scalability steps can lead to significant flow delays. To counteract these issues, a parallelized combined OPC + MDP flow for EUV can be implemented that utilizes the massive parallelization capability of data cells/templates that have finished all OPC and cell context updating. Completely finished cells/templates can be passed in a pipeline to start MDP/fracture modification well before the full OPC job has completed. This effectively enables massive

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(biasing for device and process considerations); reticle layout creation (placement of individual chips in the reticle field); OPC (including both model-based flare and model-based shadowing compensation); full model-based OPC verification; MDP (mask data prep and fracture to create the final reticle data); FTP (to either an internal or external maskshop); and mask defect avoidance (shifting the layout pattern relative to the mask blank to avoid irreparable EUV buried mask defects from printing on a critical layout feature [8]). The TAT to meet fab cycle-time goals for the same advanced mask synthesis flow are typically 12 to 24 hours for OPC, OPC verification and MDP/ fracture steps; and less than a few hours for other steps. Because of the across-reticle effects that need to be handled in EUV, traditional OPC methods may lead to missing these TAT goals by many hours or even by several days.

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EUV Masks continued from page 19

Traditional flow

parallelization of read-in/out and MDP/ MDP FTP EUV-OPC LRC fracture steps (Fig. 3). Experimental results show sizeable I/O and I/O I/O TAT savings with such a parallel approach file operations operations 2 transfer [10]. For a large (600mm area, 16nm logic) test case running in standalone mode, MDP took approximately 16hrs. Running Time the same test case in parallel mode took exactly 1 hour − 15-hour savings in reticle data availability for mask write. In Application a moderate sized 3X node DRAM chip concurrency example running in standalone mode, MDP took 1.5 hours, but running the Parallelized flow same test case in parallel mode took only 3 minutes. As this DRAM chip would be repeated 15 times in the reticle field, the estimated TAT for a full reticle case is 22.5 hours vs. 45 minutes, achieving a savings Time savings of over 21hrs in data availability for mask Time write. TAT savings will further increase for denser 10nm node logic and 2X/1X node memory cases. Figure 3. Parallelized combined component flow for EUV. The flow utilizes massive parallelization of cells/templates of data that Unfortunately, EUV’s large post-OPC have finished all previous component processing and cell context updating. Cells/templates completely finished by the previous compoand post-fracture file sizes causes the FTP nent can be passed in a pipeline for modification by the next flow component to start well before the previous component has complettransfer between different groups within a ed the entire layout. [1] Used with permission of SPIE. company or to the mask shop to take many hours of user time. Currently, FTP of a 40nm mask set (all layers) Sooryong Lee of Samsung that is 1 terabyte (TB) post-fracture often takes 12hrs on a fast FTP Eric Hendrickx, Gian Lorusso of imec. connection to the mask shop. Thus, the FTP step alone for a single 1X node RAM single layer file of 3.3TB would take more than 36hrs. References To meet these requirements, existing MDP/fracture functionality can 1. [1] J.Cobb, et al., “Investigation of EUV tapeout flow issues, requirements and options for volume manufacturing,” Proc. of SPIE Advanced Lithogbe reused, parallelizing the FTP of huge post-fracture data files well raphy Vol. 7969-26, 2011. before fracture has completed. Results on very large fractured files 2. [2] J. Cobb, et al., “Flare compensation in EUV lithography,” Proc. of the EUV Symposium, Antwerp, 2003. show that FTP time can be reduced to less than one hour with this 3. [3] J. Yeo, “EUVL projection on Samsung’s device roadmap,” presentation parallel method. at Sematech EUV Symposium, 2009. Conclusion Several new physical effects are impacting EUV OPC and mask synthesis flows. The impact of these effects on accuracy and TAT of flows was evaluated, especially the large increase in data file sizes for EUV mask synthesis and the risk this poses for meeting strict modern mask synthesis flow TAT requirements. After review of several options for improving the TAT and accuracy of individual flow components and the entire flow, results show that EUV flows can be optimized to meet stringent production TAT and accuracy requirements of future nodes. ■ Acknowledgements The authors would like to thank the following people for their helpful work and support: Hua Song, Lin Zhang, Jim Shiely, Robert Lugg, Yan Ping, Stephen Jang, Lena Zavyalova, Lantian Wang, Kunal Taravade, Thomas Schmoeller, Uli Klostermann of Synopsys Sunghoon Jang, Junghoon Ser, Insung Kim, Young-Chang Kim,

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4. [4] I. Kim et al., “Flare mitigation strategies in extreme ultraviolet lithography,” Microelectronic Eng. Vol. 85, Issues 5-6, May-June (2008). 5. [5] E. Van Setten, et al., “EUV mask stack optimization for enhanced imaging performance,” Proc. of SPIE BACUS, vol. 7823, 2010. 6. [6] G. F. Lorusso, et al., “Extreme ultraviolet lithography at IMEC: Shadowing compensation and flare mitigation strategy,” Vac. Sci. Technol. B 25, 2127 (2007). 7. [7] M. Shiraishi, et al., “EUV mask stack optimization for enhanced imaging performance,” Presentation at MNC, 2010. 8. [8] J. Burns, et al., “EUV buried defect avoidance,” Proc. of SPIE BACUS, vol. 7823, 2010. 9. [9] S. Jang, et al., “Requirements and results of a full-field EUV OPC flow,” Proc. of SPIE Vol. 7271-46, 2009. 10. [10] L. Zavyalova, et al., “OPC flare and optical modeling requirements for EUV,” presentation at 2008 International workshop of EUV Lithography, May, 2008. 11. [11] International Technology Roadmap for Semiconductors (ITRS) roadmap for EUV masks; http://www.itrs.net

Contact author: Kevin Lucas, Corporate Applications Engineer, may be reached at Synopsys, Inc., 1301 S. Mopac Expressway, Austin, TX, 78746; ph.: 512-372-7584; email [email protected].

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RESISTS

Improving line roughness by using EUV assist layers E XECUTIVE OVERVIEW

Research has shown that some of the causes of LWR and LER are partly from the blur of the pattern connected to secondary electron emission, partly from the optical flare, partly from out-of-band radiation, and largely from the acid diffusion that occurs during the post-exposure step [3-5]. With several root causes, a multifaceted solution is needed. We have seen two logical approaches to managing roughness, either preventing it or smoothing the lines after the pattern has formed. Within these two approaches, several methods are being

EUV lithography is facing several challenges, including line roughness. The cause of line roughness is complex and several approaches to prevent or smooth lines have been explored. The individual approaches are compared and a dual approach of a material and process solution is proposed.

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s the semiconductor industry has maintained the pace set by Moore’s law, it has driven development in all areas of semiconductor manufacturing. This progress can easily be tracked when looking at lithography development Resist and HMDS Resist and HMDS over time. G-line exposure tools led to i-line scanners and 32 nm features 40 nm features then to 248nm scanners. Achievements at these wavelengths, in turn, drove research into ArF technology and then to 193nm immersion lithography. Currently, the industry is focused on advancing EUV technology. We have been developing materials for EUV lithography for the past 5 years. Through this research, many unique challenges facing EUV patterning were identified as it moves closer to production. In particular, patterning features smaller than 100nm poses an uncommon set of challenges compared to previous lithography generations. Sub-100nm technology enters the quantum realm AL412 and resist AL412 and resist 32 nm features 40 nm features in which most classical models break down. One reason for the departure from traditional models is that at these feature sizes, the sizes of the molecules that compose the materials become important, along with geometric changes such as surface area versus volume adjustments. It is not surprising then that feature sizes of less than 30nm have suffered from irregularities in feature width and line edge smoothness [1]. These irregularities are commonly referred to as line width roughness and line edge roughness, or LWR and LER, respectively. The stochastic imperfections measured as LWR and An example of smoother lines from using the E2Stack AL412 assist layer coated under the LER have a direct impact on the performance of a transistor. photoresist. The assist layer “assists” the photoresist during the lithography patterning process to produce Most material metrology is focused on LER, whereas LWR smoother lines. has a larger effect on device performance. Research into the on-off current fluctuations using 45nm devices has shown a explored, some of which are a combination of prevention and direct correlation of Ioff with LWR [2]. As feature sizes decrease, smoothing. However, industry research has focused mostly on the it is expected that the impact of line roughness on device perfor- process of minimizing roughness before it forms. This solution mance will increase. appears more attractive because it is easier to avoid or minimize a problem, and usually less costly, than to troubleshoot it after the Carlton Washburn, Brewer Science, Inc., Rolla, MO USA issue has materialized.

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One approach to minimizing roughness during the lithography step is to use non-chemically amplified photoresists. Because much of the roughness comes from acid diffusion, it was thought that eliminating the amplification would decrease the roughness. This concept has been explored with similar conclusions. By using a non-chemically amplified photoresist, the LER was reduced. However, a large increase in dose was needed to reach the target CD size [6,7]. Our approach to minimizing line roughness is to assist the photoresist during the lithography step. This method improves line roughness by using an assist layer (AL) under the photoresist. The Figure shows top-down SEM images of a process using HMDS with photoresist, and the same photoresist with 40nm of E2Stack AL412 assist layer material. A clear improvement in performance can be seen when the assist layer is used. Researchers at imec have confirmed the benefits of this assist layer using a 20nm fi lm thickness, with 3-sigma LER values in the range of 3.5 to 4nm [8]. The improvement seen by using our assist layer is apparent, but the LER must be further improved to meet the ITRS target of 2.5nm for 2012. Smoothing techniques involve ion milling, ablation, reactive ion etching, and resist reflow methods. Ion milling has shown solid improvement [9]. Resist reflow processes have also shown promise [10]. Smoothing processes, however, have still not delivered a solid solution. Because no single method is delivering the needed reduction in LER, combining the benefits of an assist layer material during lithography and a smoothing process after lithography might be the dual-prong solution that is needed. By using separate steps, additional processing conditions will present options for optimization over a single step. One way this solution could work is that the assist layer would mitigate roughness during the lithography step by improving absorbance of EUV photons and secondary electrons, while postimaging processes would burnish the lines to the needed smoothness [11]. The LER and LWR targets would then be possible, while different processing options would be available to ease integration and process tuning. ■ Acknowledgment E2Stack is a registered trademark of Brewer Science. References 1. C. Gustin, L. A. H. Leunissen, et al., ”Impact of line width roughness on the matching performances of next-generation devices,” Proc. Int Symp Dry Process, 6, pp. 177-178 (2006). 2. C. Gustin, L. A. H. Leunissen, et al., “Impact of line width roughness on the matching performances of next-generation devices,” Thin Solid Films, 516, pp. 3690–3696 (2008). 3. R. L. Brainard, J. Cobb, J, C.A. Cutler, “Current status of EUV photoresists,” Jour. of photopolymer science and tech., 16(3), pp. 401-410 (2003). 4. H. Oizumi, et al., “Patterning capability of new molecular resist in EUV lithography,” Microelectronic Eng., 84, pp. 1049–1053 (2007). 5. C.C. Higgins, et al., (2011), “Coefficient of thermal expansion (CTE) in EUV lithography: LER and adhesion improvement,” SPIE: Advances in Resist Materials and Processing Technology XXVIII, 7972 (2011). 6. R. Gronheida, et al., “Characterization of extreme ultraviolet resists with interference lithography,”Microelectronic Eng., 83, pp. 1103–1106 (2006). 7. A. Yu, et al., “Patterning of tailored polycarbonate based non-chemically amplified resists using extreme ultraviolet lithography,” Macromolecular Rapid Comm., 31, pp. 1449-1455 (2010). 8. F.V. Roey, et al., imec: internal communication, May 5, 2011. 9. C.R.M. Struck, et al., “Grazing incidence ion beams for reducing LER,” SPIE: Lithography Asia, 7140 (2008). 10. I.W. Cho, et al., “Reduction of line width and edge roughness by resist reflow process for extreme ultra-violet lightography,” SPIE: Advances in Resist Materials and Proc. Tech. XXVI, 7273 (2009). 11. D.J. Guerrero, et al. “Organic underlayers for EUV lithography,” Jour. of Photopolymer Science and Tech., 21, pp. 451-455 (2008).

Biography Carlton Washburn received his bachelor of science in physics and mechanical engineering from Illinois College and the U. of Missouri-Rolla, respectively. Carlton is a senior applications engineer at Brewer Science, 2401 Brewer Drive, Rolla, MO 66401 USA; ph.: 573-364-0300; email [email protected].

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SiARC and underlayer can be individually tuned to match a particular lithography setup, minimizing substrate reflectivity into the resist as much as possible, typically below 0.5% or lower. When considering double patterning, a tri-layer approach can yield better combinations of reflectivity control for the second resist patterning step, where the first resist pattern now impacts and contributes to the local optical environment. Where SiARCs separate themselves from BARCs is with the silicon content of their polymer. Utilizing variations of resins, such as siloxanes and silsequioxanes, the silicon content of the polymer can be >40%, which is nearly the same amount of silicon as chemical-vapor deposited (CVD) SiO2 films. Polymers with silicon content >40% results in a very hard etch mask compared to any organic spin-on BARC and enables the use of fluorocarbon etches that would not be of use with a BARC. Modern SiARC materials offer much more than reflectivity control and better etch resistance. Early SiARCs, like BARCs before them, used high temperature postapplication bakes, but are now baked in the 200-250°C range, to better complement process flows. SiARCs can even incorporate additives into their formulations to combat resist poisoning, increase resist adhesion, and reduce footing profiles – all giving a lithographer more flexibility when setting up the process. The spin-on silicon hard mask material is packaged with spin-on organic hard masks (underlayers) to make process development easier and more tolerant of different resists or process conditions (Fig. 5). It is evident that SiARCs, in combination with underlayers, are at the forefront of leading edge lithography film stack solutions because of the multitude of benefits they impart. Today’s hyper-NA immersion systems necessitate the use of very thin resist coatings, and along with complex double-patterning schemes, require a more advanced anti-reflectivity solution than single or dual layer BARCs. The new SiARC materials are satisfying these needs, encompassing the requirements of reflectivity control, planarization over topography, etch resistance and selectivity, along with resist adhesion and poisoning prevention.

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Conclusion The chemistry of lithography is changing at a rapid rate to keep up with device scaling demands. While EUV is not yet ready for high volume manufacturing, a multitude of materials-based approaches have arisen to fill the exposure tool gap. Using immersion lithography to meet today’s advanced technology node requirements can only go so far. Doublepatterning, spin-on silicon hard masks, and topcoat-less resists are taking the industry the rest of the way. In a world where lithographic tools are standing (relatively) still, materials are leading the charge to meet and beat Moore’s Law. And as always, the next generation of device requirements is already upon us, but materials development stands ready to answer the challenge. ■

Regional Sales Manager West Coast US, Western Canada Lisa Zimmerer, 190 Cecil Place, Costa Mesa, CA 92627 Tel: 949/515-0552; Fax: 949/515-0553; e-mail: [email protected]

References 1. S. J. Holmes, C. Tang, M.E. Colburn, M. Slezak, B. Osborn, N. Fender, et al., “Optimization of pitchsplit double-patterning photoresist for applications at 16nm node,” Proc. of SPIE-The International Society for Optical Engineering 2011, (Advances in Resist Technology and Processing XXVIII). 2. B. P. Osborn, K. Goto, V. Pham, M. Slezak, “Non-topcoat immersion resist advancements (poster),” LithoVision 2010 Nikon Precision Symposium, San Jose, CA, February 21st, 2010.

Biographies Mark Slezak received his bachelor degree from California Polytechnic State University San Luis Obispo in Engineering and is the Director of Lithography Technology at JSR Micro, 1280 N. Mathilda Ave., Sunnyvale, CA 94089 USA; ph.: 408-543-8800; email [email protected] Brian Osborn received his PhD and undergraduate from the University of Texas at Austin in Chemistry and is the Lithography Technology Supervisor at JSR Micro, 1280 N. Mathilda Ave., Sunnyvale, CA 94089 USA; ph.: 408-543-8800; email [email protected]

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Aug/Sept 2011, Volume54, Number 8•SolidState Technology©2011 (ISSN 0038-111X) Periodicals postage paid at Tulsa, OK 74112, & additional mailing offices. Published 10x per year by PennWell Corp., 1421 S. Sheridan Rd., Tulsa, OK 74112. Subscriptions: Domestic: one year: $258.00, two years: $413.00; one year Canada/Mexico: $360.00, two years: $573.00; one-year international airmail: $434.00, two years: $691.00; Single copy price: $15.00 in the US, and $20.00 elsewhere. Single copy rate for the special March issue that contains the Resource Guide Supplement: $139.00 in the U.S; $155.00 in Canada; $176.00 international airmail. Digital distribution: $130.00. You will continue to receive your subscription free of charge. This fee is only for air mail delivery. Address correspondence regarding subscriptions (including change of address) to: Solid State Technology, PO Box 3425, Northbrook, IL 60065-9595, [email protected], ph 847-559-7500 (8 am – 5 pm, CST). PRINTED IN THE USA. GST NO. 126813153. Publication Mail Agreement No. 40052420. POSTMASTER: Send address changes to Solid State Technology, PO Box 3425, Northbrook, IL 60065-9595. Return Undeliverable Canadian Addresses to: P.O. Box 122, Niagara Falls, ON L2E 6S4.

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I N D U S T RY F O R U M

Leveraging collaborations to drive down the LED cost curve

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Jeff Desroches, ATMI, Inc., Tempe, AZ USA

or many years, IDMs, OEMs and temperature control and many others. Similarly, materials materials suppliers in the semiconductor suppliers have their own unique set of levers that they can industry have faced the increasingly adjust to modify and optimize their materials, including difficult challenges of device scaling by stoichiometry, viscosity, reactivity and many others. If sharing knowledge with one another and the respective Venn diagrams for these levers can be combining their respective skill sets in a combined such that the collaboration exploits the advancollaborative environment. While these tages of the overlapping capabilities, optimized solutions collaborations often bring their own challenges from a can be delivered to end users. Of course, the end-user commercial and cultural standpoint, there is no doubt IDMs typically bring their own key levers, most critically that technical benefits have helped the industry continue in the area of process integration. down the performance and cost path laid out several As a strong proponent of collaborative engagements, decades ago by Gordon Moore. WellATMI often refers to delivering “process known examples of collaborative efforts efficiency” to customers. While these The most that have delivered valuable solutions activities may include reducing price over accessible to the industry abound in almost every time as scale and other factors allow, more module application, especially those of often than not they focus on joint develcost-reduction lithography, CMP, deposition and plating. opment activities with a device and/or an Consortia, such as SEMATECH, imec, etc., equipment maker to drive process improveopportunities have also proven to be effective models. ments that lead to higher yields, increased The LED industry, although decades old, throughput, and/or less non-value-added have already has only seen explosive growth over the past steps. A promising example of an opporfew years with increasing demand for display been harvested tunity for innovation through collaboration backlighting and solid-state lighting (SSL). in the LED industry is around epitaxial To support the performance and cost-reduction roadmap deposition processes. dictated by Haitz’s Law (LED’s version of Moore’s Law), it’s The U.S. Department of Energy, in a recent report on likely that the industry will need to incorporate many of the the SSL industry, highlighted MOCVD processes as a key same methodologies utilized by its more mature brethren. area for improvement. The yield and throughput of the In conversations with key market players, it is clear that MOCVD process has a significant impact on final LED while some of the best known methods of the semicon- device cost. Methodologies utilized by the semiconductor ductor industry have found their way into the LED industry, industry to improve their process efficiency, many originumerous opportunities for improvement still exist. In fact, nally driven by collaborative efforts, include improvemany industry observers have expressed that they believe ments in stoichiometric control of reactants, improved the most accessible cost-reduction opportunities have flux stability, increased material utilization, and reduced already been harvested, such as migrating to larger wafer downtime through the use of bulk material delivery. sizes, maximizing use of commodity materials, etc., and that Solving difficult technology challenges is often best, further improvements will take significantly more effort. and sometimes only, achieved through concerted efforts If we think of any collaborative effort as a group of by partners who combine their respective capabilities to somewhat overlapping sets of competencies – a Venn deliver more value than the sum of the parts. As the LED diagram if you will – then the areas of overlap should industry matures, it seems exceedingly likely that many highlight the best opportunities for collaboration to of the future breakthroughs in performance and cost will ■ realize significant technological breakthroughs. For come through collaborative engagements. example, equipment manufacturers have a set of capabilities, let’s call them “levers,” which they can utilize to adjust Jeff Desroches is Business Development Manager at and optimize hardware performance. These may include ATMI, Inc., 2151 East Broadway Road, Suite 101, Tempe, flow rates, chamber design, materials of construction, AZ 85205, 480-736-7600, [email protected]

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