Ultra High-Speed CMOS Circuits. Beyond 100 GHz

Ultra High-Speed CMOS Circuits

Sam Gharavi

•

Babak Heydari

Ultra High-Speed CMOS Circuits Beyond 100 GHz

With contributions to Chapters 6 and 7 from M.C. Frank Chang and M.H. Gharavi

123

Sam Gharavi Electrical Engineering Department University of California, Los Angeles Los Angeles, CA 90095-1594, USA [email protected]

Babak Heydari Stevens Institute of Technology Hoboken, NJ 07030, USA [email protected]

ISBN 978-1-4614-0304-3 e-ISBN 978-1-4614-0305-0 DOI 10.1007/978-1-4614-0305-0 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2011933660 © Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)

Contents

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 1.1 Future of CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 1.2 The Terahertz Gap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 1.3 Shift of Paradigm in the IC Design . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 1.4 Potential New Applications and Technologies . . .. . . . . . . . . . . . . . . . . . . . 1.5 This Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

1 1 1 2 3 4

2 mm-Wave Device Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 2.1 The Importance of Modeling in mm-Wave .. . . . . .. . . . . . . . . . . . . . . . . . . . 2.2 High Frequency Modeling Procedure . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 2.2.1 Large Signal Modeling .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 2.3 Measurement and De-embedding .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 2.3.1 RF Measurement Pads . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 2.3.2 Open-Short De-embedding . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 2.3.3 Recursive Modeling Process . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 2.4 Cascode Modeling .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

5 5 8 10 11 11 12 14 17 21

3 mm-Wave Device Optimization . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 3.1 Device Performance Metrics . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 3.2 Layout Effect on Device Performance .. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 3.2.1 Parasitic Resistance Optimizations . . . . . . .. . . . . . . . . . . . . . . . . . . . 3.2.2 Multi-Finger Layout Optimization . . . . . . .. . . . . . . . . . . . . . . . . . . . 3.3 Round-Table Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 3.4 mm-Wave Power Device Optimization .. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

23 23 26 27 29 29 32 34

4 mm-Wave CMOS Noise Analysis . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 4.2 Two Port Noise Models . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 4.3 CMOS Noise Model .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 4.4 mm-Wave Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

35 35 35 37 38 v

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Contents

4.5 Noise Sensitivity Analysis to Parasitics . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 4.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

41 44 45

5 Unilateralization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 5.1 Theory of Unilateralization . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 5.1.1 Mason Gain as a Maximum Gain. . . . . . . . .. . . . . . . . . . . . . . . . . . . . 5.2 2-Port Unilateralization Techniques . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 5.3 N-Port Unilateralization .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 5.4 Single Transistor Unilateralization.. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 5.5 Simulated Results and Implementation .. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 5.5.1 Implementation and Experimental Results . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

47 47 49 49 50 52 54 55 58

6 Terahertz CMOS Devices, Circuits and Systems . . . . .. . . . . . . . . . . . . . . . . . . . 6.1 Ultra-High Speed CMOS Devices . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 6.1.1 CMOS with Enhanced-Mobility Channel .. . . . . . . . . . . . . . . . . . . 6.1.2 Graphene High-Speed Transistors .. . . . . . .. . . . . . . . . . . . . . . . . . . . 6.2 Ultra-High Speed CMOS Circuits . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 6.2.1 Nano-Scale CMOS Transceivers in the 90–170 GHz Range . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 6.2.2 CMOS THz Oscillator Based on Linear Superposition . . . . . 6.2.3 THz CMOS Push–Push Oscillator . . . . . . .. . . . . . . . . . . . . . . . . . . . 6.2.4 300 GHz Fundamental-Tone Oscillator in CMOS . . . . . . . . . . . 6.2.5 600 GHz CMOS Passive Imager .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . 6.2.6 200 GHz CMOS Frequency Divider .. . . . .. . . . . . . . . . . . . . . . . . . . 6.3 Ultra-High Speed Systems . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 6.3.1 Ultra-High-Speed Data Communication .. . . . . . . . . . . . . . . . . . . . 6.3.2 Direct Antenna Modulation Systems . . . . .. . . . . . . . . . . . . . . . . . . . 6.4 Chapter Summary and Conclusion.. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

59 59 60 61 63 64 67 69 70 71 72 73 73 76 78 79

7 Imaging Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.1 Photons Interaction with Matter . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.2 Active and Passive Imaging . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.3 Optical Versus Non-optical Imaging .. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.3.1 Responsivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.4 Attenuation .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.5 Image Quality Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.5.1 Spatial Resolution . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.5.2 Contrast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.5.3 Penetration Depth . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.6 Passive Imaging Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.7 Imaging Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.8 Medical Imaging .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

81 81 82 83 83 84 85 85 88 88 88 90 91

Contents

vii

7.8.1 X-ray Imaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 91 7.8.2 Magnetic Resonance Imaging . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 93 7.8.3 Nuclear Imaging .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 98 7.9 Emerging New Medical Imaging Applications . .. . . . . . . . . . . . . . . . . . . . 98 7.10 Chapter Summary and Conclusions . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 103 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 103 Index . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 105

Chapter 1

Introduction

1.1 Future of CMOS Silicon technology at frequencies above 100 GHz is a newborn field with tremendous potentials. This newborn field can be thought as the intersection of a new generation of devices, circuits, systems and applications. From the device view point, the economic fuel of the IC industry, CMOS technology, is reaching a turning point due to the physical limitation of silicon in the super-scaled nodes. As a result, fundamental changes have been envisioned for the CMOS in the near term. For example, hybrid CMOS/III-V devices, CMOS-compatible hybrid photonics/electronics technologies and nano-engineered graphene-based FET are three parallel research efforts for shaping the future of the devices. We will briefly introduce these topics in Chap. 6. The ultimate goal of all these research efforts is to engineer a device that can operate in the terahertz1 band while preserving the beloved features of the CMOS for mixed-signal VLSI integration (Fig. 1.1).

1.2 The Terahertz Gap The terahertz frequency band has been traditionally inaccessible neither by photonic devices, nor by the electronic devices. Perhaps that is why this band has been called the “terahertz gap”. In simple terms, this inaccessibility has been due to the “lowpass” nature of active electronic devices (e.g. diodes and transistors) caused by the transient time and R-C parasitics and the “high-pass” nature of photonic devices due to the bandgap energy levels. The main impediment to filling the terahertz gap in an industrial scale remains the lack of a cheap, solid-state source that can deliver enough power while operating at room temperatures. There has been an exponential

1 We

refer to the 100 GHz to 10 THz range as the terahertz band in this book.

S. Gharavi and B. Heydari, Ultra High-Speed CMOS Circuits: Beyond 100 GHz, DOI 10.1007/978-1-4614-0305-0 1, © Springer Science+Business Media, LLC 2011

1

2

1 Introduction

Fig. 1.1 CMOS future

CMOS/III-V Hybrid

Graphene FET

CMOS compatible photonics

Electronics domain

Photonics domain THz gap

Fig. 1.2 THz gap

growth in the terahertz technology research over the past few years. The exponential growth of terahertz technology research has motivated the IEEE to launch a new publication called the “IEEE transaction on terahertz science and technology” in 2011 (Fig. 1.2).

1.3 Shift of Paradigm in the IC Design From the circuit design perspective, the traditional paradigm of electronic IC design is no longer applicable to the new setup. The miniature wavelength at higher frequencies and larger dimensions of chips (due to the increased complexity), have seriously challenged the old, lumped-element-based, IC design approaches. In the

1.4 Potential New Applications and Technologies

3

Fig. 1.3 Electrically large chips

d>λ

emerging circuit paradigm, interconnects and components are treated as electrically large and chips often include radiating elements. This convergence of circuits and electromagnetics opens new opportunities for implementing novel systems. One example of such novel systems is called the “Near-Filed Direct Antenna Modulation (NFDAM)” and will be covered in Chap. 6. IC design at 100 GHz and above follows no well-established and commonly-accepted method yet and individual designers have their unique methodologies. We will present some fundamental, innovative techniques such as device optimization and unilateralization in Chaps. 1–5. In addition, examples of different design methodologies from different research group will be presented in Chap. 6 (Fig. 1.3).

1.4 Potential New Applications and Technologies Several applications have been envisioned for terahertz. Many of these proposed applications are still in the feasibility verification phase in the labs. For example, terahertz band offers unique features that can be exploited in medical and nonmedical imaging and spectroscopic applications. The non-ionizing nature of the terahertz waves (as opposed to the X-ray) and their sensitivity to the water concentration make them ideal for skin analysis as we will see in Chap. 7. Also terahertz waves have been applied to the label-free genetic sequencing. On the other hand, terahertz waves easily penetrate clothing, textile and packaging materials. As such, they have been proposed for security screening and weapon detection purposes (Fig. 1.4). Also the unique “signature” of many chemicals at the terahertz band makes the terahertz waves very attractive for spectroscopic applications. From a different perspective, the increasing data rate demand for the wireless communication systems can no longer be satisfied with the current available standards. A simple extrapolation of the wireless data rates trend in the past few years will reveal a need for links as fast as 10–20 Gbps at application layer and more than 25 Gbps at the PHY layer in the upcoming few years. Such data rates cannot be achieved with the current standards (e.g. the 60 GHz) and requires a move to higher frequency bands (e.g. 300 GHz and above) with higher available unlicensed bandwidths.

4

1 Introduction

Fig. 1.4 Weapon detection with terahertz imaging

1.5 This Book This book is divided into two parts. In part I, which includes Chaps. 2, 3, 4 and 5a number of new device modeling and optimization techniques are presented. These techniques will equip the designer with the tools such as “device unilateralization” and layout optimization to get the best possible performance out of a given technology node. The mentioned techniques are generic and not limited to any specific CMOS node. In part II, which includes Chaps. 6 and 7, we will overview the state of the art in ultra-high speed integrated devices, circuits and systems. Also some fundamental concepts from imaging and medical imaging are covered in part II.

Chapter 2

mm-Wave Device Modeling

Circuit designers are mostly used to assume device models as given, instantiate their desired devices in their schematic windows, set up the simulation and run! They might perform their simulations in a number of different process corners and this is as much as they should worry about the whole notion of device modeling. mm-wave circuit design, at least for now, is an exception and both active and passive devices need extensive modeling. In this section, first reasons for this importance are discussed, then the device modeling procedure up to 100 GHz is presented and modeling results for single-transistor devices are shown. This follows by a discussion about measurement and de-embedding at these frequencies. Finally modeling of cascode devices are is included as an example of a multi-transistor structure.

2.1 The Importance of Modeling in mm-Wave Available models that circuit designers use in their daily simulations are the socalled “compact” models. Compact models are the interface between the technology and the design. A circuit designer learns about a process by experimenting with the compact model, rather than running expensive and time-consuming experiments. Several good compact models have been developed for digital, analog, and RF applications [1,6,18,20]. These models use a combination of physical and empirical methods to develop general equations, usually a large number of them, to describe the behavior of the device. Several parameters are embedded in each equation in order to capture the details of a given technology. These parameters are necessarily determined through complicated curve fitting procedures (parameter extraction) and shape the familiar model card for circuit designers. Most compact models have the advantage of describing the behavior of the device in all regions of operation at the same time. Furthermore, they provide small and large signal analysis as well as noise analysis. They also operate over a fair range of geometry, width and length of the device, over which the extracted parameters are valid. This generality S. Gharavi and B. Heydari, Ultra High-Speed CMOS Circuits: Beyond 100 GHz, DOI 10.1007/978-1-4614-0305-0 2, © Springer Science+Business Media, LLC 2011

5

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2 mm-Wave Device Modeling 1. 0 0. 9

S11

0. 8 0. 7 0. 6

S22

0. 5 0. 4 0. 3

S12

0. 2 0. 1 0. 0 0

5

10

15

20

25

30

35

40

45

50

55

60

65

Fig. 2.1 S parameters of an 80 μm common-source device, measurement versus model using available BSIM3v3 foundry model

however comes with an accuracy penalty if the model is used over a bias or geometry range outside of the extraction process. Moreover, the core equations in most compact models have been derived under quasi-static assumptions. This, together with the fact that most of available extracted parameters are also for low frequency applications, make these compact models less desirable and inaccurate for millimeter wave applications. Figure 2.1 shows the foundry modeled S parameters of a common-source device and compares it with the actual measurement of the device. There are two main reasons for this inaccuracy: First of all, as mentioned before, the fact that the parameter extraction has been done in lower frequencies makes the extrapolation to mm-wave frequencies problematic [2]. Some of device mechanisms that are not well captured at low frequencies, and naturally not modeled properly, have considerable effect on the performance of the device in higher frequencies, resulting in some inaccuracy. The substrate network including capacitances and resistances is an example of such an effect [13]. The inaccuracy due to this effect could be addressed by increasing the frequency range of parameter extraction process. The second reason for the error in modeling – which is more difficult to address – is due to the layout effect [5, 11]. The device interconnections to the outside world introduce small inductors, resistors and capacitors to the model. These small components are generally negligible at lower frequencies making the device model more or less independent of layout. These components however change and in fact dominate the performance of the device as the frequency increases and therefore should be included in the model. An accurate prediction of these parasitic requires

2.1 The Importance of Modeling in mm-Wave

7

Fig. 2.2 A sample 90 nm test chip fabricated for modeling and characterizing

a detailed full-wave electromagnetic simulation, which is difficult and lengthy. Therefore existing compact models are used as the core for a hybrid customized mm-wave model. In essence, each small finger of the transistor is modeled with the “intrinsic” transistor model and interconnects are captured by a combination of selective electromagnetic simulation and experimental techniques. Due to the importance of device modeling in this project, two round of test structures were fabricated and modeled. The micrograph of one of these chips is shown in Fig. 2.2. The test chip contains common-source, common-gate and cascode transistors with various sizes as well as different transmission lines and capacitors. The characterized devices were used in all circuits designed and fabricated in 90 nm process in Berkeley wireless research center. Given the difficulties in modeling the device, one may be tempted to work directly with measured data. In traditional microwave design the common approach is to use measured S-parameter data for a specific device and treat the transistor as a black box [9, 19]. This approach is very accurate in nature and accounts for all parasitics and distributed effects associated with the device and the layout. While this method is sufficient for small-signal circuit design applications, the accuracy of the S-parameter data hinges on reliable measurements of the device and deembedding structures. As a result, the accuracy of the method may deteriorate for very high frequencies, both due to limited accuracy of test equipment and due to de-embedding errors. Besides, since S-parameters are small-signal in nature, this method is not suitable for simulation of any non-linear circuit such as mixers or oscillators or the assessment of the dynamic range of amplifiers. Moreover, because the transistor is treated as a black-box, there is no physical insight for improving

8

2 mm-Wave Device Modeling

the device performance or layout. Due to these issues, for mm-wave application, a combination of “RF” and traditional microwave methodology is preferred even for small-signal applications.

2.2 High Frequency Modeling Procedure A typical transistor layout designed for high frequency is shown in Fig. 2.3a. The device usually is long and narrow as it is designed with a large number of short fingers to minimize the gate resistance. A connection at the gate and the drain, usually in the form of a transmission line connects the device to the outside world. These transmission lines are connected through a 45◦ taper to the transistor for a

a

Tline

Ground b

Fig. 2.3 (a) Layout of a typical high frequency MOSFET. (b) A cross-section of a MOS transistor showing various parasitics

Gate Taper

Ground

Drain Taper

Multi-finger Device Bridge

Tline

Ground

2.2 High Frequency Modeling Procedure

9

Fig. 2.4 Model of a common-source NMOS (a) S11 with and without the gate resistance. (b) S22 with and without the substrate resistance network

proper current distribution to and from the device. The cross-section of a device is also shown in Fig. 2.3b to show several parasitics that should be considered in the high frequency modeling of the transistor. At mm-wave frequencies, series resistive and inductive parasitics become more significant.While the resistive parasitics are always a part of the device, the inductive portion is usually more significant in high-frequency transistors because of the special layout onsiderations as mentioned earlier. Consequently, it is critical to properly model these parasitics, in addition to the capacitive effects that are traditionally captured by digital CMOS models. Moreover, neglecting or oversimplifying the substrate network of the device can introduce a considerable error at these frequencies. Figure 2.4 shows the error in the S11 and S22 of the device caused by ignoring the gate resistance and the substrate network in the small signal model of a typical NMOS transistor. Equivalent circuits have been an effective approach to analyze the electrical behavior of a device by representing the important components [4, 17]. As shown in Fig. 2.5a MOSFET device can be divided into two portions: intrinsic part and extrinsic part. The intrinsic part (the shaded area in Fig. 2.5) is the familiar hybrid-π model of the device, used for low frequency circuit analysis. The extrinsic part consists of parasitic resistances and inductances at the gate,drain and source as well as a proper substrate network. It is shown that a three resistor substrate network is sufficient to model the device behavior in the mm-wave frequencies [8]. Note that extrinsic parasitic capacitances between various terminals could be embedded in the internal device capacitances and be modeled as a part of the intrinsic part. For each model, the extrinsic component values and device parameters were extracted from measured data using a hybrid optimization algorithm in Agilent IC-CAP [12]. Values of the components that could minimize the measurement to model error are not unique and one could come up with several equivalent circuits of the device for the same set of measurement data. This is acceptable as long as the model is used within the measured range of frequency. However, if the component

10

2 mm-Wave Device Modeling

Fig. 2.5 Small signal high frequency equivalent circuit of a MOS transistor

values in the model are made close to their physical values,there is an additional benefit and they can be used in frequencies well beyond the maximum measured frequency. Moreover, having a physical equivalent model can help with an accurate assessment of the value of parasitics and the sensitivity of the device performance to them. These information are very useful in optimization of the device physical structure as will be discussed in Chap. 3. Because of these reasons, the initial values of the components are calculated using proper equations and based on the measured Y parameters of the device up to 20 GHz [17]. The initial value of external resistances and inductances could also be estimated by simulating the connection leads and contacts on the terminals using EM simulators. These initial values then are fed to the optimizer with reasonable tuning ranges to get an accurate physical model.

2.2.1 Large Signal Modeling Although small signal models are usually sufficient for the design of linear circuits, the design of high performance non-linear blocks such as mixers, oscillators and power amplifiers depends on capturing the nonlinear characteristics of the active devices over a wide range of voltage and current. Developing a large-signal equivalent model from the scratch is a very complicated process and many physical effects that affect the DC behavior of the device need to be considered. Fortunately, available compact models, such as BSIM3v3 or BSIM4 are specifically created to capture most of these effects. By adding proper parasitics to these foundry given compact models as shown in Fig. 2.6, both DC nonlinearities and high frequency effects could be captured simultaneously. Since external terminal resistances and the substrate network are added manually, the BSIM model should be adjusted to turn-off the internal options for these parasitics. Moreover, due to the inherent accuracy compromise in these models to

2.3 Measurement and De-embedding

11

Fig. 2.6 Large signal high frequency equivalent circuit of a MOS transistor

enable them to cover all geometries, the DC behavior of each individual device could be made more accurate and should be also fitted to the measurement by adjusting proper BSIM parameters [7].

2.3 Measurement and De-embedding In the high frequency measurement of active and passive devices, the effect of probing pads and extra leads are typically subtracted from the measurement through a de-embedding method [23]. In direct de-embedding, the measured results from test structures (such as open and short circuits) are used directly and subtracted from the measurements. In a model based approach, a suitable physical equivalent circuit topology is selected and rough values for these equivalent circuit parameters then are estimated using a combination of equation-based calculations based on low frequency data. The final fine tuning and fitting is done using an optimizer such as Agilent IC-CAP [12]. In this section we review the major de-embedding procedures and discuss the problems and advantages of the various techniques.

2.3.1 RF Measurement Pads Since most connections to the external world go through measurement pads, a good model for the pad is critical. In the model based de-embedding approach, this model

12

2 mm-Wave Device Modeling

Fig. 2.7 Layout of a common RF GSG pad

also serves as a foundation for de-embedding the effects of the pads whereas in the design of building blocks, the effects of the pads must be included in order to predict the real world performance of the device or circuit. A common RF pad arrangement is the ground-signal-ground (GSG) structure shown in Fig. 2.7. These pads mate naturally with CPW probes and have good performance in the mm-wave band. Often the signal pad is shielded from the substrate, forming a grounded CPW (G-CPW) structure at the pad. If the transmission line leads to the rest of the circuit are microstrip or G-CPW, then this is the best option to use. Otherwise, if CPW is used, the decision to ground the pad is not clear cut. A shielded pad will form a high-Q structure, since the fields are isolated from the lossy substrate, but the shield adds extra capacitance and a discontinuity in the fields from the probe to the device. In order to reduce the pad capacitance, the signal pad is reduced to the minimum allowable probing dimensions, or about 90 μm × 90 μm, for 150 μm pitch pads. For smaller pitch pads, smaller pads can be used. The RF pad is considerably smaller than the ground pads. A short 45◦ taper is used at the output of the pad in order to reduce the reflections due to discontinuities. In the example shown, a 40 μm, 50Ω transmission line connects the pad to the rest of the circuits.

2.3.2 Open-Short De-embedding A popular de-embedding approach is the so-called open de-embedding, which simply removes the effects of the pads from the measurement structure shown in Fig. 2.8a by subtracting the measured Y parameters of the pad from the measured device, as shown in Fig. 2.8b. The key assumption is that the pads are connected in parallel to the DUT, which neglects the physical nature of the pads and treats the signal entry/exit points as lumped circuit nodes. The equivalent circuit for parasitics that could be captured in the open measurement is shown in Fig. 2.9. For the DUT we can write: Ydut = Ym − Yo (2.1)

2.3 Measurement and De-embedding

a

13

b

c

Ground

P1

DUT

Ground

P2

P1

Ground

P2

Ground

Ground

P2

P1

Ground

Fig. 2.8 (a) The device under test and the measurement pads. (b) The open test structure. (c) The short test structure Fig. 2.9 The equivalent model of parasitics for the open de-embedding

Y3

Input

Output DUT

Y1

Y2

And we can write these equations for the parasitics: Y3 = −Y12,o = −Y21,o

(2.2)

Y1 = Y11,o + Y12,o

(2.3)

Y2 = Y22,o + Y21,o

(2.4)

The other assumption for in the open de-embedding is that we can indeed measure a true pad open structure by simply open circuiting the pad test structure. In reality, the open circuits have finite fringe capacitance and radiation, which invalidates the above assumptions. In practice this procedure is quite accurate up to 10 GHz for small on-chip structures. In summary, open de-embedding removes the shunt parasitics from the measured device. As the frequency increases, open de-embedding is not sufficient to de-embed all the parasitics and a more common approach is the so called open-short deembedding. In this approach, in addition to measuring the embedded structure and open pads, a short structure as shown in Fig. 2.8c is also measured. A typical DUT with parasitics can be represented by an equivalent circuit shown in Fig. 2.10. If we device the matrix Zs as   Z1 + Z3 Z3  (2.5) Zs = Z3 Z2 + Z3

14

2 mm-Wave Device Modeling

Fig. 2.10 The equivalent model of parasitics for the open-short de-embedding

Y3

Z1

Input

Z2

Output

DUT

Y1

Z3

Y2

Then we can calculate the Zs matrix from this equation: Zs = (Ys − Yo )−1

(2.6)

the same correction is applied to the measured data of interest Ym = Ym − Yo

(2.7)

and then the modified short measurement is subtracted from the measurements −1  Zm = Ym−1 − Zs = (Ym − Yo )−1 − Zs−1 − Yo

(2.8)

In practice this technique is reliable up to about 40 GHz or more, depending on the size of the test structures. By neglecting the distributed nature of the pads, we are limited to frequencies where all dimensions are negligibly small compared to the wavelength.

2.3.3 Recursive Modeling Process Evidently, the de-embedding step is a major source of inaccuracy at mm-wave frequencies. It introduces error in the data due to imperfect assumption about the de-embedding structures. For example, for open-short de-embedding, the error arises from imperfect open and short especially at higher frequencies and the distributed nature of the structure. These inaccuracies make the de-embedded result noisy, directly affecting the accuracy of the extracted model. In order to resolve this problem several high frequency de-embedding methods have been proposed [14, 15, 22]. Here as an alternative a model based de-embedding approach, dubbed the recursive modeling has been employed. A typical test structure comprises of probing pads, lead transmission lines and the device under test (DUT). In this method, probing pads are modeled in the first step. Pad models are then used to model the transmission line leads and finally the

2.3 Measurement and De-embedding

15

Fig. 2.11 Equivalent circuit of pad includes a section of transmission line

14.3 pH

43.5 fF

240 mΩ Zo = 47.3 Ω L = 40.8 µm

2.77 Ω

two models are employed to model the complete DUT. Typically all different test structures use identical probing pads and lead transmission lines making it sufficient to model them only once for all the structures. This modeling technique in principal is applicable for any structure, passive or active, as long as an equivalent circuit can capture the behavior of the structures. The circuit shown in Fig. 2.11 is used to model the pad over a broad frequency range from 40 MHz to 65 GHz. The parallel branch represents the equivalent circuit for the pad itself and the series branch models the extra lead. The 1-port S parameters measurements are performed for the pad in two configurations, the first with the output port connected to ground, and the second with the output port left open. To increase the accuracy of the modeling, the Z and Y parameters of the model are simultaneously matched with the measured parameters in both configurations. The results in Fig. 2.12 show that the model accurately captures the RF pad behavior over the frequency range of interest. The transmission line that is used as a lead from the probe to the device has to be modeled in the next step. Coplanar waveguide (CPW) transmission lines are used in all test structures. A length scalable electrical transmission-line model has been developed to capture the complex propagation constant and frequency dependent characteristic impedance. Figure 2.13 shows the modeling result for a 500 μm CPW transmission line with a 4 μm signal-to-ground gap. In the next step, the DUT is modeled. The complete model of the measured structure is made by connecting the previously modeled pad and transmission line whose models should be kept unchanged during this step and the equivalent model of the DUT that could be both small-signal or large-signal as was discussed in the previous section. The initial guesses of the equivalent circuit components are calculated and the whole model is then fitted to the raw device measurement through optimization of transistor core and external parameters. An experimental verification of this approach has been performed. All the measurements have been done using on-chip probing up to 110 GHz. Agilent IC-CAP software and the hybrid optimization method has been employed to perform model optimizations. Figure 2.14 shows the modeling result, the measured and modeled real and imaginary parts of S-parameters for an 80 μm/0.09 μm transistor up to 100 GHz. The cleanness of the measured data is an advantage of this method which helps the accuracy and speed of the modeling process. The good agreement

16

2 mm-Wave Device Modeling

a

Im(Zin) vs. Freq, pad, port grounded

Im (Zin)

15

10

5

0 0

5

10

15

20

25

30

35

40

45

50

55

60

65

55

60

65

Frequency (GHz)

b

Im(Zin) vs. Freq, pad, port open 0

Im (Zin)

-500

-1000

-1500

-2000 0

5

10

15

20

25

30

35

40

45

50

Frequency (GHz) Fig. 2.12 Measured vs. simulated ℑ(Z) parameters for the RF pad with the port (a) grounded and (b) open

S12 0.3

1.0

real

0.5

real

0.2 0.1

0.0

S11

Imag

Imag 0.0

-0.5

-0.1

-1.0 10 15 20 25 30 35 40 45 50 55 60 65

Freq(GHz)

10 15 20 25 30 35 40 45 50 55 60 65

Freq(GHz)

Fig. 2.13 Measured versus model of a 500 μm long CPW transmission line with gap spacing S = 4 μm

2.4 Cascode Modeling

17

Fig. 2.14 Measured (marker) versus simulated (lines) S-parameters of a 40 μm/90 nm transistor modeled using the recursive approach

between the model and measurement suggests that the extended lumped hybrid-pi model is valid to frequencies as high as 100 GHz. Figure 2.15 compares the result of the proposed modeling technique to the openshort de-embedding method. The difference can be best noticed by comparing Y-parameters. The de-embedded data is clearly noisy especially for frequencies in the millimeter-wave bands. For frequencies in the K and Ka bands, the two models give similar results. The discrepancy however gets significant for frequencies higher than 40 GHz showing the inaccuracy of open-short de-embedding for millimeterwave applications. The error becomes specially significant in the imaginary parts of Y11 and Y22 and the real part of Y21 . These would result in major circuit performance degradations as we approach 100 GHz. The method was also tested with measured data up to 60 GHz and the predicted data at 100 GHz were compared to the actual measurement at this frequency and found to be in a good agreement. This indicates another important advantage of this modeling method that is its ability to extend beyond the measurement frequency without introducing significant error.

2.4 Cascode Modeling Cascode devices are used extensively in mm-wave design. These devices could potentially provide higher gain compared to common-source devices and are usually unconditionally stable at these frequencies due to the isolation between

18

2 mm-Wave Device Modeling 0.10

0.018

Imag

0.010

0.08 0.06

Y11

0.006

0.04

Imag

Real

0.014

0.02

0.002

Real

-0.002

0.00 110

100

90

80

70

60

50

40

30

20

10

0

Freq(GHz) 0.001

0.000

-0.010

-0.003

Y12

-0.005

-0.015 -0.020

Real

-0.007

Imag

Real

-0.005

Imag

-0.001

-0.025

0.08

110

100

90

80

70

60

50

40

30

20

10

0

Freq(GHz)

0.000

Imag

-0.015

Y21

0.06

Real

-0.030

0.05 0.04 110

100

90

80

70

60

50

40

30

20

10

0

Freq(GHz)

-0.045

0.020

Imag

Y22

0.008

Real 0.004

0.07 0.06 0.05 0.04 0.03 0.02 0.01

Imag

Real

0.016 0.012

Imag

Real

0.07

0.00 110

100

90

80

70

60

50

40

30

20

10

0

Freq(GHz)

Fig. 2.15 Comparison of the open/short versus recursive de-embedding/modeling approach for the Y parameters of a 40 μm/90 nm

2.4 Cascode Modeling

19

a

b Vout Ld2 Rd2 Cdb1 Cgd2 Lext

Cext

Rsub1 Rsub2

M2 Cgs2 Rsub3 Cgd1 Lg1

Cdb2

Rg1 M1

Rsub4

Vin Cgs1

Cdb3

Rs1 Ls1

Fig. 2.16 Equivalent circuit of a cascode device. The transistors can be replaced with a hybrid-π model for small signal modeling

input and output [16]. To minimize the capacitance at the junction of the input and cascode device, a shared junction structure as shown in Fig. 2.16a is usually used.1 Because of using this structure, cascode devices need special treatment in 1 This

is more explained in Chap. 5.

20

2 mm-Wave Device Modeling

Fig. 2.17 Comparison of measured and modeled device S-parameters

modeling and a simple connection of the two single transistor models does not accurately predict the device high frequency behavior and specifically can introduce substantial error in the Y22 of the device [3]. An equivalent circuit of a cascode transistor is shown in Fig. 2.16b. The model is essentially similar to the common-source model that was discussed earlier. One important difference is the way the substrate network is modeled. Because of the shared junction structure, the substrates of the two devices are shared and this needs to be considered in the equivalent circuit. This substrate can be a source of feedback between the output and input [10]. The second gate of the device is also connected to a bypass capacitor to ensure a high frequency ground to avoid oscillation. Because of the sensitivity of the cascode gate to parasitics, the proper equivalent model of the capacitor should be included on the cascode gate. To test the accuracy of the model, a sample 40 μm/90 nm is measured and compared to the model using the proposed method. The close match between measured and modeled S-parameters up to 65 GHz as shown in Fig. 2.17 confirms the validity of the model as well as the modeling procedure.

References

21

References 1. The BSIM 3v3 and 4.4.0 Website, http://www-device.eecs.berkeley.edu/bsim3BSIM Website 2. Cheng Y, Hu C (1999) MOSFET Modeling and BSIM3 User’s Guide. Springer, New York 3. Choong CY et al (2003) Small-signal substrate resistance effect in RF CMOS cascode amplifier. IEEE Microwave and Wireless Components Letters, vol 13, pp 253–255 4. Dambrine G et al (1988) A new method for determining the FET small-signal equivalentcircuit. IEEE Transaction on Microwave Theory and Techniques, vol 36, pp 1151–1159 5. Doan CH, Emami S, Niknejad AA, Brodersen RW (2005) Millimeter-Wave CMOS Design. IEEE Journal of Solid-State Circuits, vol 40, pp 144–155 6. EKV model website, http://legwww.epfl.ch/ekv/EKV Website 7. Emami S, Doan CH, Niknejad AM, Brodersen RW (2004) Large-signal millimeter-wave CMOS modeling with BSIM3. IEEE RFIC Symp Dig, pp 163–166 8. Enz C (2000) MOS transistor modeling for RF design. IEEE J of Solid-State Circuits, vol 35, pp 186–201 9. Gonzalez G (1996) Microwave Transistor Amplifiers. 2nd edn. Prentice-Hall Inc 10. Heydari B, Adabi E, Bohsali M, Afshar B, Arbabian MA, Niknejad AM (2007) Internal unilateralization technique for CMOS mm-wave amplifiers. RFIC Digest of Papers, pp 463–466 11. Heydari B, Bohsali M, Adabi E, Niknejad AM, mm-Wave Devices and Circuit blocks up to 104GHz in 90nm CMOS. IEEE J of Solid State Circuits, vol 42 pp 2893–2903 12. ICCAP website, http://eesof.tm.agilent.com/products/iccap main.htmlICCAP website 13. Jia OJ et al (1998) CMOS RF modeling for GHz communication IC’s. Digest of Technical papers, VLSI symposium, pp 94–95 14. Kolding TE (2000) A four-step method for de-embedding gigahertz on-wafer CMOS measurements. IEEE Trans Electron Devices, vol 47, pp 734–740 15. Koolen MCAM et al (1991) An improved de-embedding Technique For on-wafer HighFrequency Characterization, IEEE Bipolar Circuits and Technology Meeting, pp 191–194 16. Lee TH (2003) The design of CMOS radio-frequency integrated circuits, 2nd edn. Cambridge University Press, Cambridge 17. Lovelace D et al (1994) Extracting small-signal model parameters of silicon MOSFETtransistors. Microwave Symposium Digest, vol 2, pp 865–868 18. MOS11 website, http://www.semiconductors.philips.com/Philips Models/mos models/ model11/ MOS11 Website 19. Pozar DM (2004) Microwave Engineering. 3rd edn. Wiley 20. PSP model website, http://www.nxp.com/Philips Models/mos models/psp/PSP Website 21. Tsividis Y (2003) Operation and modeling of the MOS transistor, 2nd edn. Oxford University Press, Oxford 22. Wei X et al (2007) An improved on-chip 4-port parasitics de-embedding method with application to RF CMOS. 2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, pp 24–27 23. Ytterdal T, Cheng Y, Fjeldly TA (2003) Device modeling for analog and RF CMOS circuit design, 1st edn. Wiley, New York

Chapter 3

mm-Wave Device Optimization

As was mentioned in the previous chapter, device performance in mm-Wave frequencies is deeply under the influence of layout parasitics. Apart from the urge for layout dependent models, as was pointed out before, this has another important consequence: Unlike low frequency circuit design in which the device design is absolutely in the realm of process engineers, here the circuit designer could- and should- alter the device performance by changing the device layout [1, 3]. This enables the designer to layout the device based on the performance metric which is more important in any specific application. It might be astounding in the first look how much the device layout could vary certain device parameters. fmax , for instance, which is an indicator of the speed of the transistor, have been reported for a similar process, CMOS 90 nm, from 80 GHz to up to 300 GHz mainly due to differences in layout [2, 8]. Millimeter-wave device design is essentially customizing the device layout in order to maximize certain performance metrics. Performance metrics for mmwave devices are several, ft , fmax , maximum stable gain at a given frequency, maximum unilateral gain at a given frequency and minimum noise figure are the most important ones. That which metric is to be considered as an optimization target depends on the specific application of the device. In this chapter, we first look more closely at some of the most important device performance parameters. Then few examples of device optimization including a novel “round-table” device are presented. In the end, there is a brief discussion about the optimization process for large devices used as power delivering transistors.

3.1 Device Performance Metrics There are several performance parameters for a transistor, and each defines the performance in a different way. Unity current gain frequency ( ft ), unity power gain frequency ( fmax ), maximum stable gain (MSG), and maximum unilateral gain (U) are the most popular metrics as shown on Fig. 3.1. Noise performance and linearity S. Gharavi and B. Heydari, Ultra High-Speed CMOS Circuits: Beyond 100 GHz, DOI 10.1007/978-1-4614-0305-0 3, © Springer Science+Business Media, LLC 2011

23

24

3 mm-Wave Device Optimization 1.2

50

ty F act o r( k)

45

h2

dB

30

1

as

on

25 20

G

ai

n

S ta

M

35

1.0 0.8

b ili

40

0.6

MSG

15 fmax

10

0.4 0.2

5 0 -5

ft 0.0 1

10

100 200

Freq(GHz)

Fig. 3.1 MSG, U and h21 of a sample common-source device. The ft and f max of the device is pointed at the unity values of h21 and U curve respectively

of the device are also crucial when it comes to specific circuit blocks such as low noise or power amplifiers. In order to maximize the performance of a device through layout optimization, it is crucial to consider the correct figure of merit and the criteria for optimization. The unity current gain frequency, ft , is the most popular high frequency number of a process and is basically the frequency in which the current gain of the device becomes one. It can be calculated from the h21 of the device and is equal to [9]: ft = fh21 =1 ≈ 2π

Gm Cgs + Cgd

(3.1)

In this equation Gm is the effective transconductance of the device and Cgs and Cgd are total gate to drain and gate to source capacitances of the device, including parasitic capacitances. When the layout is reasonable in a way that does not add considerable extra capacitances, ft is mostly determined by the intrinsic device characteristics and is improved by scaling and/or process optimization. Because resistive losses in the input and output do not affect this parameter, the device layout has negligible effect on ft . Although ft is the most common performance metric for a given technology node, it does not reflect the performance level of a specific device at that technology node. What actually matters more is the power gain of a device rather than its current gain [6]. A device can remain active (have power gain larger than one) in frequencies well above ft . For this reason fmax – the maximum frequency in which the device has power gain – is a more valid metric to show the limit of the activity of the transistor. The unity power gain frequency, fmax , strongly depends on parasitic losses of the

3.1 Device Performance Metrics

25

device and can be improved (or degraded) by optimizing the layout of the transistor. Depending on the layout, the fmax could vary from below ft to values considerably higher than ft . The ratio, fmax / ft is a figure of merit that shows the optimality of the layout. Depending on the assumptions, several equations have been proposed to evaluate the f max of a MOS transistor. Assuming the reasonable assumption that Rs is smaller than the total gate resistance the fmax can be written as [7]: ft fmax ≈    t 2 Rg gds + 2π ft cgd

(3.2)

In which Rtg is the total gate resistance. This equation shows the effect of Rg and Cgd on the value of fmax and indicates these are the main factors that need to be minimized to increase the f max . We will see the detail of this optimization in the next section. While ft and fmax indicate unity gain frequencies and indicate limits of the performance of the device, MSG and Mason’s Gain (U) represent the performance of the device at the frequency of interest. U, is the gain of the device under the condition that the device is unilateralized through some feedback mechanisms or some circuit techniques [5].1 More importantly, it is also a figure of merit independent of the topology in which the device is employed and is important in applications where device or circuit unilateralization techniques are used. The value of U can be calculated from this equation [5]: U=

|S21 /S12 − 1|2 2 (k|S21 /S12 | − ℜS21 /S12)

(3.3)

Where k is the stability factor and can be calculated from this equation: k=

1 − |S11|2 − |S22 |2 + Δ 2 2|S12S21 |

(3.4)

In an open loop structure, the achievable gain could be considerably lower than the Mason Gain specially in frequencies below ft /2; thus we need a different metric for open loop applications where reaching U is not an option. MSG is a good candidate to serve this goal. To better grasp a sense out of MSG, the case for the stability of the device in question should be beard in mind. Under frequencies of high gain condition, devices are generally conditionally unstable. This means that under certain source/load impedance conditions, there is a chance that the circuit starts oscillating. Considerable amount of literature is available to come up with parameters that represent an instability potential of a device. The most common measure is k parameter that is directly calculated through S parameters and ensures

1A

general condition for N-port unilateralization is presented in Chap. 5.

26

3 mm-Wave Device Optimization

and unconditional stability when is above 1. As the Fig. 3.1 suggests, the MSG curve consists of two separate regions distinguished by a kink in between. The kink happens at k = 1 and at a frequency after which the device becomes unconditionally stable. The equation for MSG is also piece-wised based on k:

Δ = S11 S22 − S12S21 |S21 | if k < 1 |S12 |  |S21 | MAG = (k − k2 − 1) |S12 |

(3.5)

MSG =

(3.6) if

k>1

(3.7)

It’s worth noting that at frequencies before the kink, the unconditional stability is ensured by adding as much loss to the input/output ports to drive k exactly equal to 1 and MSG is calculated based on this assumption. As a result, the internal gate and drain resistances of the device do not affect the MSG as long as they are less than the required add-on resistance to make the device stable. This is an important fact that helps designing especially high performance power devices as will be discussed in the next section. In the k < 1 region, the MSG of a MOS transistor is proportional to gm /cgd , the ratio of feedforward and feedback factors of the device. As a result cgd is very crucial factor in MSG optimization. The source resistance can also change the value of MSG through changing the effective gm of the device. After the frequency in which device becomes unconditionally stable, the parasitic losses at the input and output terminals increase the value of K and make the MSG drop faster. Although these metrics are in correlations with each other, changing one does not always guarantee a change in the other and ultimately the application and the topology in which the device is used determine the goal parameter. Generally Mason gain and it’s unity cross over, i.e. Fmax , are more sensitive to the layout than the maximum stable gain, especially where the device is conditionally stable, due to the loss compensation in MSG calculation.2

3.2 Layout Effect on Device Performance To determine the effect of layout on device parameters, a physical small signal model is used in order to ascertain the effect of each parasitic on the desired performance metrics of the device. The small-signal model of the device, discussed in the previous section, is not necessarily unique and different combination of lumped element values could satisfy the required matching between the measurement and the simulation result. As a result, in order to make the model physical and extendable

2 Noise

analysis and optimization is discussed in Chap. 4.

3.2 Layout Effect on Device Performance

27 ce

an

t is

es

e at

t.

R

G

is

D G

S

D Dist. Channel Resistance

Fig. 3.2 Distributed gate and channel resistance

to higher frequencies, the values of these parasitics were partly determined through 3D EM simulation (HFSS) and were set as the initial value for optimization. The developed physical small-signal model helps determine the effect of each parasitic element on the performance of the transistor. Ultimately this insight can be used to determine the optimal transistor layout. For example, the layout of a common source device has been optimized for fmax . The starting point for this procedure was a 80×1 μm/90 nm sized device with an MSG of 7.5 dB at 60 GHz and the extrapolated fmax of 143 GHz. A sensitivity analysis was performed for the developed model and the variation of maximum unilateral gain (Mason’s Gain) and MSG together with maximum frequency of operation were determined. As expected, the gate to drain capacitance and the gate resistance have the largest impact on fmax , and thus layout methods should give the first priority to their minimizing. As we noted earlier, MSG does not change with a reduction in gate and drain series resistances when the transistor is conditionally stable (k ≺ 1). The source resistance, however, changes the MSG since it changes the effective transconductance through its local feedback effect. A more detail analysis of parasitic resistances and their minimization methods are discussed in the next section.

3.2.1 Parasitic Resistance Optimizations Gate resistance is the most important resistive parasitic that needs to be minimized. A large gate resistance significantly reduces the fmax and available gain. It also affects the noise performance of the device as will be shown in Chap. 4. The gate network can be viewed as a distributed RC transmission line as is shown in Fig. 3.2. The total gate resistance can be divided into three parts [4]: Rgate = Rgpoly + RNQS + Rwire g g

(3.8)

28

3 mm-Wave Device Optimization Rvia

Gate Rsalicide Drain

Source Rldd Rc

Substrate

Fig. 3.3 Various portions of a MOSFET drain resistance

The NQS resistance is an intrinsic device parameter and is a function of the geometry and bias conditions and to optimize the gate resistance one should focus on the other two portions. The Rwire can be minimized by increasing the number of g poly

connection vias from the gate to the top metal layer. Rg Rgpoly

Rsh = Nf L f

  Wf Wext + α

can be written as [10]: (3.9)

In this equation, Rsh is the gate sheet resistance, W f is the channel width per finger, L f is the channel length, N f is the number of fingers, and Wext is the extension of the polysilicon gate over the active region that is imposed by the design rules. The factor α is related to the distributed nature of the gate resistance and is equal to 1/3 or 1/12 for single and double gate contacts respectively [6]. Equation (3.9) suggests that using more short fingers can reduce the poly gate resistance. The effect of finger width reduction becomes minor as soon as the poly gate resistance becomes a small portion of the total gate resistance in (3.8) and is not beneficial any more. Moreover, as will be seen later in this chapter, short finger width can negatively affect the performance of large power devices. The source and drain resistances have several components including the via resistance, the salicide resistance and the resistance of the LDD region as is shown in Fig. 3.3. However, the contact and the LDD sheet resistances usually dominate the total resistance. Accordingly, their values can be written as: Rd = Rd0 +

rdw Nf Wf

(3.10)

Rd = Rs0 +

rsw Nf Wf

(3.11)

3.3 Round-Table Structure

29

where rdw and rsw are the parasitic drain and source resistances with unit width and Rd0 and Rs0 represent the width independent part. Increasing the number of fingers and connection vias help to reduce Rd and Rs too although the number of fingers has to be decided based on gate resistance considerations and other issues related to large power devices as will be described later in this chapter. The value of Rs needs to be minimized as it affects the effective gm and the noise performance of the device. On the other hand, circuit performance metrics, neither fmax nor NFmin , are not much sensitive to the value of Rd and the circuit layout could be optimized in favor of other parameters if there is any trade-off.

3.2.2 Multi-Finger Layout Optimization The NMOS structure was modified based on these findings. Mainly the shape of gate and drain tapers, number of gate vias, and width of connections and gate/drain overlap regions were changed. Figure 3.4 shows a layout comparison of the structure before and after modification. The measured performance of the initial device and that of the modified device is shown in Fig. 3.5. The fmax for the improved structure is up to 178 GHz. The MSG of the device is intact however since the device is in the conditionally stable region as was expected.

3.3 Round-Table Structure As was showed in the last section the optimal multi-finger layout of an NMOS device could increase the fmax up to 20%, but increasing the performance further required further innovation. This is particularly true of the available gain in the conditionally stable frequencies. In order to improve the performance of the device even further, a new structure for the device is proposed. The idea is to reduce the parasitic losses by using a modular approach in device design and using multi-path connections between various modules. The building block is a standard 10 μm cell with double-gate contacts in order to decrease the finger resistance of the device. Since each finger of the device forms a distributed RC network, double contact reduces the resistance of each finger by a factor of four [9]. These cells are then connected in a matrix or circular fashion depending on the desired size of the final transistor. Figure 3.6 shows a W = 60 μm NMOS using a circular connection, hence the name “Round-Table”. This structure uses external double-contacts (between cells) and multi-path connections between sources and drain of the sub cells. The layout trade-offs were addressed based on the results of the predictive model discussed in the previous section. Several dimensions of these devices were fabricated in 90 nm CMOS process. Measurements were carried out up to 65 GHz and probing pads were de-embedded

30 Fig. 3.4 Initial (a) and improved (b) layout for an 80 μm/90 nm device. The improved layout includes more substrate contacts, higher density of gate and drain vias and smaller taper

3 mm-Wave Device Optimization

a

b

Fig. 3.5 The effect of layout improvement on Mason U and MSG

50 M a s o n G a in 40 M o d ifie d 30 In itia l

dB 20 MSG

10 0 -10 1

10 GHz

100

200

3.3 Round-Table Structure

31

Fig. 3.6 Layout of a round-table device

Fig. 3.7 Measured h21 , Mason’s U and MSG for a 40 μm/90 nm round-table device

from the devices. Figure 3.7 shows MSG, Mason’s gain (U) and h21 of a W = 40 μm round-table NMOS. The fmax is calculated by extrapolation of the Mason’s gain U for frequencies between 20 GHz to 50 GHz, a frequency range where the most reliable data occurs. As evident, measurements suggest significant improvement in both the speed and the desired gain of these devices as compared to regular RF transistors with the same number of fingers. Even though ft remains almost constant (100 GHz), fmax improved by almost two fold, or to about 300 GHz. This is of course the extrapolated fmax since the device introduces new high frequency poles after 100 GHz, rendering the linear approximation of the Mason curve inaccurate beyond

32 Table 3.1 Parasitic comparison between a regular layout and a round-table layout

3 mm-Wave Device Optimization

Value Rg (Ω ) Rd (Ω ) Rs (mΩ ) Cgs (fF) Cgd (fF)

Regular 4.46 3.54 627 35.7 21.3

Round table 2.23 2.42 438 57.1 17.2

100 GHz. Unlike the improvement of the regular multi-finger device presented in the previous section, the MSG of the round-table device increases even at frequencies in which the device is conditionally stable. The MSG at 60 GHz is 8.5 dB up from the value of 7.5 dB (regular NMOS) for I = 28 μA/ μm. The ratio fmax to ft , a measure of the optimality of the physical structure of the device, is close to 3, the highest reported for CMOS. The improvement of the MSG is the result of decreased source resistance and parasitic drain to gate capacitance that both act to decrease the internal series and shunt feedback gains respectively. The improvement of fmax was mostly due to reduction in the gate and drain resistances. Table 3.1 compares the result of extracted small-signal parameters of a round-table W = 40 μm device to a regular optimized multi-finger 40 μm transistor. All the resistive losses have been reduced considerably as shown in the accompanying table. The parasitic gatesource capacitance of the device is increased. This is mainly due to the increased overlap capacitance between source and gate in order to reduce the gate and source resistances. This is a good trade-off since the cgs can be tuned out by the matching network.

3.4 mm-Wave Power Device Optimization The design of a power amplifier hinges around the selection of the appropriate power device. Large devices are quite popular to deliver a large amount of current to the output load in the output stage of power amplifiers. A large power device can be realized in different ways, with a standard multi-finger layout, an array “round table” layout as described in the previous section, or as a delay equalized structure. The primary considerations for the design of the amplifier include sufficient power gain G p , stability, output power Po , and the drain efficiency η . The maximum stable power gain of a 2 μ versus 4μ finger width transistor are shown in Figs. 3.8 and 3.9. Both devices have 100 fingers and so the 400 μ device should in theory be able to deliver twice the power of the 200 μ device. The 200μ device is biased with 47 mA whereas the 400μ device is biased at 94 mA. It is interesting to note that the 400μ device is unconditionally stable as the gate resistance stabilizes the devices. The 200 μ device is only conditionally stable, but the unstable region occurs for only a small inductive range when the load is terminated in a small resistance. The larger device, though, has smaller maximal stable gain (MSG ∼ 6.8 dB versus

3.4 mm-Wave Power Device Optimization

33

Kink Frequencies 55 GHz 85 GHz

Fig. 3.8 A comparison of device power gain as a function of device layout (2 μ versus 4μ finger width)

Fig. 3.9 Load impedance contours of constant device power gain and contours of constant output power

MSG ∼ 8.4 dB). More importantly, the variation in gain is much more rapid as we move away from the optimal point, which means that process variations would lead to more variation of power gain. Utilizing a large device with small finger width, though, is problematic due to the difficulty in making the gate/drain transmission lines. This difficulty is apparent in the layout of such a device (Fig. 3.10), where the transition region introduces extra series resistance and shunt capacitance into the signal path. The measured MSG of this device is less than 5 dB, less than half of the optimal device width.

34

3 mm-Wave Device Optimization

Fig. 3.10 A W = 400μ device realized with 400 fingers

References 1. Cheon KS et al (1997) CMOS layout and bias optimization for RF IC design applications. Digest of IEEE Microwave Symposium, vol 2, pp 945–948 2. Guo JC, Lien WY, Hung MC et al (2003) Low-K/Cu CMOS logic based SoC technology for 10 Gb transceiver with 115 GHz fT, 80 GHz fMAX RF CMOS, high-Q MiM capacitor and spiral Cu inductor. VLSI Digest of Technical Papers, pp 39–40 3. Heydari B, Bohsali M, Adabi E, Niknejad AM, mm-Wave Devices and Circuit blocks up to 104GHz in 90nm CMOS. IEEE J. of Solid State Circuits, vol 42 pp 2893–2903 4. Jin X et al (1998) An effective gate resistance model for CMOS RF and noise modeling. IEDM’98 Technical Digest, pp 961–964 5. Mason SJ (1954) Power gain in feedback amplifiers. Trans IRE Professional Group on Circuit Theory, vol CT-1, no 2, pp 20–25 6. Niknejad AM (2007) Electromagnetics for high-speed analog and digital communication circuits, 1st edn. Cambridge University Press, Cambridge 7. Sze SM (1990) High speed semiconductor devices. Wiley, New York 8. Tiemeijer LF et al (2004) Record RF performance of standard 90 nm CMOS technology. IEDM Technical Digest, pp 441–444 9. Tsividis Y (2003) Operation and modeling of the MOS transistor, 2nd edn. Oxford University Press, Oxford 10. Ytterdal T, Cheng Y, Fjeldly TA (2003) Device modeling for analog and RF CMOS circuit design, 1st edn. Wiley, New York

Chapter 4

mm-Wave CMOS Noise Analysis

4.1 Introduction The range of many wireless communication systems is limited by the sensitivity of their receivers, meaning the minimum amount of signal to noise ratio that the receiver can successfully detect [8]. This sensitivity heavily depends on the noise figure of the entire receiver. However since the noise of each stage is normalized by the total gain of previous stages, as Friis equation predicts, the noise figure of the low-noise amplifier essentially dominates the entire receiver sensitivity [2]. Although several noise mechanisms such as flicker, shot-noise and generationrecombination noise can be considered for a MOS device, at high frequencies, the main source of noise that is important to linear circuits is the thermal noise [3]. Due to the direct effect of the noise figure of LNA on the performance of the entire receiver, this parameter should be accurately predicted during the design process. Moreover, in the low noise amplifier design, coming up with a simultaneous optimization of noise performance with other important circuit parameters such as gain and input match is always a challenge and needs an accurate noise model. In this chapter, first, the general noise representation methods for any two port network is overviewed, then the thermal noise model of CMOS devices is discussed. This is followed by a section about CMOS mm-wave noise model and the behavior of noise parameters versus frequency and layout parasitics. In the end, the developed model is compared with some experimental results in the 50–75 GHz frequencies.

4.2 Two Port Noise Models Two-port theory provides a means to represent a noisy two-port in terms of a noiseless two port and its corresponding two noise sources. Modeling the noise of a two port network is essentially based on a generalized Thevenin’s theorem. Just like deterministic two port parameters, the noise model can be represented in S. Gharavi and B. Heydari, Ultra High-Speed CMOS Circuits: Beyond 100 GHz, DOI 10.1007/978-1-4614-0305-0 4, © Springer Science+Business Media, LLC 2011

35

36

4 mm-Wave CMOS Noise Analysis

a

b + -

+ -

i1

noiseless network

V1

i2

noiseless network

V2

+ -

c V1

noiseless network

i1

Fig. 4.1 Equivalent two-port noise representation (a) Admittance (PRC) model; (b) Impedance model; (c) ABCD model

admittance, impedance or ABCD form as shown in Fig. 4.1. These noise sources form a correlation matrix that is Hermitian and non-negative. The PRC and ABCD representations are the most common forms and their correlation matrix are shown as following: ⎞ ⎛ i1 i∗1 i1 i∗2 ⎠ (4.1) Cyn = ⎝ ∗ ∗ i2 i1 i2 i2 ⎛ CAn = ⎝

vn v∗n vn i∗n in v∗n

⎞ ⎠

(4.2)

in i∗n

∗ . Thus, C11 , In both of these matrices, C11 and C22 are positive real and C12 = C21 C22 together with the real and imaginary parts of C12 form four noise parameters that are sufficient to fully characterize the noise behavior of a two port network. Most of the time, the ABCD matrix is needed to be calculated starting from the PRC representation from this equation:

⎛ CAn = ⎝

0B

⎞

⎛

⎠ CYn ⎝

1D

0 1

B∗

⎞ ⎠

(4.3)

D∗

In which A, B, C, and D are the ABCD matrix elements. Circuit designers are more familiar with another four parameter noise representation F = Fmin +

Rn |Ys − Yopt |2 Gs

(4.4)

in which Fmin is the minimum achievable noise figure, Rn is the noise sensitivity resistance, and Yopt is the optimal source noise admittance. Also Ys = Gs + jBs is the source admittance of the network.

4.3 CMOS Noise Model

37

To bridge between this representation and the ones mentioned earlier, one can use the ABCD representation. This form is a function of the circuit representation as follows: ⎛ ⎞ Fmin − 1 ∗ − R R Y n opt ⎟ ⎜ n 2 ⎟ CAn = ⎜ (4.5) ⎝ F −1 ⎠ min 2 − RnYopt Rn |Yopt | 2 and the four circuit parameters can be calculated by solving the corresponding four equations [12].

4.3 CMOS Noise Model The main source of transistor noise in mm-wave frequencies is thermal noise. Thermal noise is the result of the kinetic energy of particles. These thermally-excited particles in a conductor undergo a random walk Brownian motion via collisions with the lattice of the conductor. This random walk produces random electrical characteristics in the device terminals. Among the various methods proposed for MOSFET noise modeling, the Van Der Ziel model is the most widely accepted one [11].Van Der Ziel modeled the FET noise as a voltage modulated resistor, capacitively coupled to the gate as depicted in Fig. 4.2. This way, two noise sources for the channel resistance and the induced gate noise are calculated. As the source of both these noises are the channel noise, there is a strong correlation between these two sources. However due to the distributed nature of the channel that translates to infinite noise sources, the represented sources are not completely correlated. Van Der ziel model is essentially a PRC model as described earlier. The value of the two sources and their correlation can be calculated using these equations: i2d = 4kT Δ f γ gd0

(4.6)

i2g = 4kT Δ f δ gg

(4.7)

noise source

Fig. 4.2 Generation of channel and induced gate noise in MOSFET

38

4 mm-Wave CMOS Noise Analysis

ig id c  i¯2g i¯2d gg  ζ

2 ω 2Cgs gd0

(4.8)

(4.9)

where γ , δ , and ζ are bias-dependent factors; gd0 is the drain output conductance under zero drain bias; gg is the real part of the gate-to-source admittance; and c is the cross correlation coefficient. For a long channel MOSFET, γ is 2/3 when the channel is pinched off and 1 when the channel is symmetric [11]. Values of δ , ζ and c could be also calculated to 4/3, 0.2 and j0.395 respectively. Although the model is well matched with long channel transistors, substantial increase has been observed and reported in both γ and δ for short channel MOSFETs [1, 4, 10]. There have been extensive discussions on the amount of noise increase and subsequently the value that γ an δ take as well as the physical source of the origin of this excess noise. However, recently there has been a consensus that the noise parameter, γ , is substantially smaller than what initially had been assumed and its value for a saturated MOSFET is close to twice as its long channel value [5, 6, 9].

4.4 mm-Wave Noise Model The main problem with PRC and ABCD models is that the correlation between the two noise sources, makes the simulation difficult as few circuit simulator tools offer correlated noise sources. To remedy this problem, Pospieszalsky proposed a new model, as shown in Fig. 4.3, based on two uncorrelated noise sources in the source and drain sides. This model, assumes two uncorrelated noise sources, rgs and rds to model the channel noise. The temperature of these two resistors are set to Tg and Td , the only model parameters, respectively where Tg is close to the environment temperature while Td a is much higher temperature and could go up to several

Fig. 4.3 Pospieszalski model assumes two uncorrelated noise sources, rgs at Tg and rds at Td

4.4 mm-Wave Noise Model

39

thousands. In this model, the rgs noise is responsible for the correlated part of the channel noise as if the Td is set to zero, the model represents a noise process with ρc = − j. Based on the procedure described in the previous section, the noise optimal source impedance can be calculated using the Cy and ABCD matrices of the device. Ignoring the effect of C − gd for now, the Ropt and Xopt will be

Ropt



 ft 2 rds Tg (Rg + rgs ) = + (rgs + Rg )2 f Td Xopt =

1 ω Cgs

(4.10)

(4.11)

At low frequency, when f is much smaller than ft , the second term in the Ropt equation could be neglected and the equation simplifies to (Rg + rgs )rds Tg f t low f (4.12) Ropt = f Td This value could be much larger than Rg + rgs , the optimal gain resistance. This considerable difference, makes it crucial to use simultaneous noise and gain optimization techniques. As the frequency approaches the ft of the device, this approximation becomes invalid. In fact, the two terms become comparable in value for such frequencies. To get an approximate value for Ropt in this case, we need few assumptions. The value of rgs is equal to ng1m and n is a value between 3 to 5. We can also assume that Rg , by using some good layout techniques, is roughly equal to rgs . We can further assume that Td is 10 to 15 times larger than Tg and gm is roughly 10 times larger than gds , the Ropt will become √ kn = 2...2 (4.13) Ropt = kn (Rg + rgs ) In fact the optimal noise resistance is only a factor of kn larger than the optimal gain resistance. In this simple model, the imaginary part of optimal noise and gain sources are also equal. As a result the optimal noise and gain source impedances approach each other as evident on Fig. 4.4. These imply that, if the Rn is sufficiently small, minor compromise in the noise and gain performance, can result in the simultaneous noise/power match as we approach and pass the ft of the device. Even small deviation from the optimal noise source, can have a considerable noise penalty if the value of Rn is large. Calculation of Rn is more complicated and needs considering the effect of the gate to drain capacitance of the device to show the real trend. The value of Rn is equal to the value of A in the ABCD noise matrix of the device, considering both Rg and Cgd as shown in Appendix III.

40

4 mm-Wave CMOS Noise Analysis

Fig. 4.4 Optimal noise and gain impedances for a 40μ device for f = 1 to 100 GHz

Opt gain source Opt Noise source

Fig. 4.5 (a) Simulated NFmin and Rn for a 40μ common-source round-table device; (b) noise and gain circles for optimal, optimal −0.3 dB and optimal −0.5 dB at 60 GHz

Rn = rgs

2 C2 ω 2 ) gds (1 + rgs Tg Td g2m gs + 2 2 ω2 T0 (gm + CgsCgd rgs ω 2 )2 + Cgd ω 2 T0 (gm + CgsCgd rgs ω 2 )2 + Cgd (4.14)

Both these terms show a reduction with the frequency and the simulated Rn is shown in Fig. 4.5a. The implication is that the penalty to be paid as a result of a deviation from the optimal noise impedance gets smaller as the frequency approaches ft . In fact this together with the closeness of the optimal noise and gain impedances, suggest that with a compromise of about 0.5 dB in gain and noise figure, one can get a simultaneous noise and gain match as depicted in Fig. 4.5b. It is worth mentioning the importance of considering the Cgd of the device in the Rn calculation. If the Cgd is neglected, (4.14) simplifies to the more familiar equation.

Tg Td gds 2 2 2 Rn = rgs + Cgs ω 1 + rgs (4.15) T0 T0 g2m

41

6

70

5

65

4

60 Rn

NFmin

4.5 Noise Sensitivity Analysis to Parasitics

3 55

2

50

1 0 0

10

20

30

40

50

60

70

80

45 90 100

Fig. 4.6 NFmin and Rn for a 40 μ cascode device

This would imply a direct relation between Rn and frequency that could be misleading. In fact, high frequency device noise measurements for non-silicon technologies, had shown the reduction of Rn with frequency [7] and the effect is verified for CMOS as will be represented in the next section. It is expected however, that if the output and input of the device are de-coupled, as is the case for cascode devices, the Rn experiences a moderate increase with the frequency in the mm-wave region as predicted by (4.15). This prediction is verified both in simulation and measurements. The simulated Rn and Fmin for a cascode device is shown in Fig. 4.6. This increase has been observed in measurements as well [7].

4.5 Noise Sensitivity Analysis to Parasitics Determining the noise contribution of various noise sources and the sensitivity of the noise performance to their values are essential specially when it comes to optimize a device for a low noise applications. Figure 4.7a shows the contribution share of different noise sources of a round-table device based on the proposed model. The sensitivity of the noise figure to the increase in the parasitic resistances have been also shown in the Fig. 4.7b. It is clear that with a reasonable layout to keep the parasitic gate resistance low, most of the device noise comes from the drain side noise source. The parasitic gate resistance is the second large contributor and it is the main controllable noise source that shows a large sensitivity as well. This suggest that even further reduction of Rg could still significantly help in terms of noise performance of the device and should be considered for devices specifically tailored to low noise applications.1 The source resistance, although showing rather a large sensitivity, does not contribute to the overall noise figure as it is sufficiently small for the round-table device.

1 The

detail of the relationship between Rg and the device layout has been discussed in Chap. 2.

42

4 mm-Wave CMOS Noise Analysis

a

Rds Contribution Rgs Contribution Gate parasitic Resistance Drain parasitic Resistance Substrate network Source Resistance

b Gate parasitic Resistance Drain parasitic Resistance Substrate network Source Resistance

Fig. 4.7 (a) Noise contribution of various noise sources for a round-table device; (b) noise sensitivity of the device to parasitic noise sources Fig. 4.8 The substrate noise coupling to the channel gmba(f). Vns.

Ccp a(f). Vns. R* sub

Vns

The drain and substrate resistances demonstrate low noise contribution as well as low sensitivity. The noise of the drain resistance is scaled down by the gain of the device. The substrate resistance noise capacitively couples to the channel and can add to the drain current noise based on the effective gmb of the device. ¯ = 4kT i2sub 0

R∗sub g2mb 2 R2 1 + ω 2Ccp sub

(4.16)

R∗sub is the effective substrate resistance assuming a simple one resistor substrate network and Ccp is the associated coupling body to channel capacitor as depicted in Fig. 4.8. Due to the low pass nature of the filter formed by the substrate resistance and the coupling capacitor, this noise is not of a great importance in high frequency as verified by sensitivity and noise contribution analysis.

4.5 Noise Sensitivity Analysis to Parasitics Lg

Rg

43

Rgi(Tg)

Ls

Rd

Cgd Rds

gm

Cds Cdb

Cgs

Rs

Lg

Ld

Td

Rsub1

Rsub2

Rsub3

Fig. 4.9 The employed model for noise analysis

a 6 5 4 3 2

NFmin

1 0 50

55

60

65

70

75

Freq ( GHz)

b 70 60 50

Rn

40 30 20 10 0 50

55

60 65 Freq ( GHz )

70

75

Fig. 4.10 Simulated and measured (a) NFmin and (b) Rn for a 40μ common-source round-table device

44

4 mm-Wave CMOS Noise Analysis

4.6 Experimental Results For the complete noise simulation, the small signal model as shown in Fig. 4.9 has been used. The Td and Tg of the device have been set to 4,200 K and 310 K while all the parasitic resistances have the environment temperature to fit the measured data. The noise measurement is performed for the frequency range of 50 to 75 GHz although the data in the lower frequency range is very scattered and most of the reliable data occur after 60 GHz. The noise data was de-embedded using the recursive de-embedding method described in Chap. 2. Figure 4.10a, b compares the simulated and measured minimum noise figure and noise resistance for the round-table 40 μm device. The slight increase in the NFmin as well as the predicted reduction in Rn can be seen in these measurements while both values have good agreements with the model. Figure 4.11 demonstrates the measured and modeled optimal noise impedance and compares it to the measured optimal gain impedance. While the model and measurement show a good agreement, the optimal gain impedance is also very close to the corresponding noise impedance as was explained and predicted in the previous section.

a

1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0

b

50

55

60

65

70

75

50

55

60

65

70

75

200 180 160 140 120 100

Fig. 4.11 Simulated and measured optimal noise impedance and measured optimal gain impedance (a) magnitude (b) phase for a 40μ common-source round-table device

References

45

References 1. Abidi AA (1986) High-Frequency Noise Measurements on FETs with Small Dimentions. IEEE Transactions on Electron Devices, vol 33, no 11, pp 1801–1805 2. Fries HT (1944) Noise Figures of Radio Receivers. Proceedings of the Institute of Radio Engineers, vol 32, pp 412–422 3. Goo JS (2001) High Frequency Noise in CMOS Low Noise Amplifiers. PhD Thesis, Stanford University 4. Jindal RP (1986) Hot-electron effects on channel thermal noise in fine-line NMOS field-effect transistors. IEEE Transactions of Electron Devices, vol 33, pp 1395–1397 5. Jung-Suk Goo et al (2001) Physical Origin of the Excess Thermal Noise in Short Channel MOSFETs. IEEE Electron Device Letters, vol 22, no 2, pp 101–103 6. Navid R et al (2002) The physical phenomena responsible for excess noise in short-channel MOS devices. International SISPAD Conference, pp 75–78 7. Niknejad AM, Hashemi H (2008) mm-wave devices and circuits 8. Razavi B (1997) RF Microelectronics, 1st edn. Prentice Hall PTR 9. Scholten AJ et al (2003) Noise modeling for RF CMOS circuit simulation. IEEE Transactions on Electron Devices, vol 50, pp 618–632 10. Triantis DP (1996) Thermal noise modeling for short-channel MOSFETs. IEEE Transactions of Electron Devices, vol 43, pp 1950–1955 11. van der Ziel A (1986) Noise in solid state devices and circuits.Wiley, New York 12. Vandelin GD, Pavio AM, Rohde UL (2005) Microwave circuit design, using linear and nonlinear techniques, 2nd edn. Wiley, New York

Chapter 5

Unilateralization

The limited performance of transistors at high frequencies usually result in an increase in the number of gain stages which proportionally adds to the power dissipation of the system and also degradates the noise performance of the circuit. As a result, circuit techniques to improve the gain-power efficiency of devices at frequencies in the vicinity of the ft of the device are highly valued. On the other hand, it is of a theoretical value to construct a systematic method of boosting the gain of an N-port active networks and to determine the maximum possible stable gain achievable out of such a network. As the maximum stable gain is inversely proportional to the reverse feedback conductance of a network, minimizing this feedback path is a way to increase the potential gain of the network. In the extreme case, where this feedback is canceled out completely, the network becomes unilateral. At this point, the network is also very stable due to the lack of reverse feedback. As a result of these two effects, unilateralization techniques are highly valued techniques for RF and mm-wave circuit design.

5.1 Theory of Unilateralization In 1953, when transistors where only 5 years old, people had started considering them for RF applications, limited in the VHF range for old-time devices. Mason [3] started a goal to look for an invariant property of two port networks that could be used as a figure of merit for high frequency devices. The problem is defined as follow: Consider a linear two port network as shown in Fig. 5.1a (both being two port and linear are essential constraints for the problem). An invariant metric has to be indifferent to any lossless transformation to the network. Any transformation of the device can be conceptualized as an embedding network, similar to Fig. 5.1b. The 4-port embedding network has to be linear, lossless and reciprocal. Mason has shown that all conceivable transformation that satisfy the constraints in the four port network, could be realized from just three basic transformations. S. Gharavi and B. Heydari, Ultra High-Speed CMOS Circuits: Beyond 100 GHz, DOI 10.1007/978-1-4614-0305-0 5, © Springer Science+Business Media, LLC 2011

47

48

5 Unilateralization

Fig. 5.1 (a) used as an amplifier (b) embedded in a 4-port lossless reciprocal network

These transformations are Reactance Padding, Real Transformation and Inversion. In terms of impedance matrix they could be represented as follow: 1. Reactance padding 

     Z 11 Z 12 Z11 Z12 x11 x12 = +j Z 21 Z 22 Z21 Z22 x21 x22

2. Real transformation       n11 n12 Z11 Z12 n11 n12 Z 11 Z 12 = Z 21 Z 22 n21 n22 Z21 Z22 n21 n22 3. Inversion



  −1 Z 11 Z 12 Z11 Z12 = Z 21 Z 22 Z21 Z22

These three transformations could be realized with several different circuits. Now the problem reduces to finding an index in terms of the impedance matrix that remain intacts to these three transformation. The reactance padding keeps [Z − Zt ] and [Z + Z ∗ ] unchanged while the real transformation reduces this to the determinant of [Z − Zt ][Z + Z ∗ ]−1 . In the end, inversion transformation restrict only the magnitude of this matrix to be invariant. The resulting invariant term from all these three basic transformations is thus: U=

|det(Z − Z t )| det(Z + Z ∗ )

This could be written in the more familiar forms of U=

|Z12 − Z21|2 4{ℜ(Z11 )ℜ(Z22 ) − ℜ(Z12 )ℜ(Z21 )}

(5.1)

|Y12 − Y21 |2 4{ℜ(Y11 )ℜ(Y22 ) − ℜ(Y12)ℜ(Y21 )}

(5.2)

U=

At this point, the desired invariant metric is found and this in fact is the major result of Mason’s paper.

5.2 2-Port Unilateralization Techniques

49

5.1.1 Mason Gain as a Maximum Gain Other than being invariant, U implies a maximum gain under certain condition. If the original twoport network is unilateralized using a 4-port linear lossless reciprocal network, then the value of U is equal to the value of maximum stable gain of that network. A more formal proof to this statement is as follow: Writing the maximum stable gain equation in a slightly different form we have Gmax =

1 |Y21 | √ |Y12 | k + k2 − 1

(5.3)

Now Gumax = lim Gmax = Y12 →0

|Y21 |2 4ℜ(Y11 )ℜ(Y22 )

(5.4)

Setting Y12 to zero in the (5.2) gives the same result proving that Gumax is equal to U. This suggests that the stable gain of a unilateral network is bounded by mason gain. It is however crucial to remember that U is not the maximum gain unless the device is first unilateralized using an embedding network. if the device is not unilateral, the maximum stable gain could be significantly higher than U as will be demonstrated in the following sections. In fact, as we pass the unilateral frequency, on one hand, K decreases since the network becomes less stable and makes the expression in the parenthesis in (5.3) increase. This in competition with the ration of |Y21 | and |Y12 | determines the global maximum of the stable gain over the frequency. However, since the gain and stability increase coincide at the point where the device is unilateral, several circuit techniques to achieve unilateralization have been developed as will be discussed in the next section.

5.2 2-Port Unilateralization Techniques Investigating unilateralization techniques has a long history. Cheng [1] in his classic paper in 1953, presented a general scheme and some circuit implementation for unilateralization of 2-port networks all require transformers. A more commonly used technique is neutralization which can be implemented more easily and often used as a subsequent for unilateralization in moderate frequencies. Neutralization may be defined as “the process of balancing out an undesirable effect” [1]. The technique is mostly investigated for common-source/common-emitter devices. For this architecture, the dominant reverse feedback element is the Cμ of the device and neutralization goal is to cancel out the effect of this capacitor. This could be achieved by simply resonating out the capacitor, using an inductor as depicted in Fig. 5.2a. A large series capacitor is needed to dc couple the gate and the drain. More over, this technique is narrow band due to its resonance nature.

50

5 Unilateralization

Fig. 5.2 (a) Neutralization using a resonating inductor. (b) Cross coupled capacitor neutralization

A wider band neutralization could be achieved as shown in Fig. 5.2b [4]. The idea is that CN is sized in such a way that it injects a negative current equal to the magnitude of the feedback current passing through Cgd so that the total current returns to the input becomes zero. As the drain voltages of a differential pair have opposite phases, the negative current could be achieved with this architecture. For mm-wave application however, the parasitic inductance of the neutralization capacitance becomes significant and could limit the applicability of this method. It is also important to remember that neutralization is equivalent to unilateralization, only if the reverse feedback is pure imaginary. This is not the case for architectures other than common-source/base. The assumption of imaginary reverse feedback for common-source/base also breaks in frequencies close to ft as other effects become important. A general condition for unilateralization in such frequencies could be achieved by looking at the desired circuit as a multi-port network.

5.3 N-Port Unilateralization For an N-port network, the unilateralization technique translates into finding proper complex terminations for the (N-2) ports to make the remaining 2-port unilateral. Consider an N-port network as shown in Fig. 5.3. One can readily write the N dimensional admittance parameters relating input voltages and currents with designated signs shown on the picture: 1−n In = Y1−n Vn

(5.5)

This equation could be decomposed in this fashion: 1−2 3−n V1−2 + Y1−2 V3−n I1−2 = Y1−2

(5.6)

3−n 1−2 I3−n = Y3−n V3−n + Y3−n V1−2

(5.7)

5.3 N-Port Unilateralization

51

Fig. 5.3 N-port network with N-2 external complex termination 1 −m2 For which Ykm1 −k represents a (k2 − k1 + 1) × (m2 − m1 + 1)matrix with yi j 2 elements for which i and j change from k1 to k2 and m1 to m2 respectively. Now assume that ports 3 to n are terminated by a series of complex loads with i (i : 3...n). These loads introduce another set of equations: admittances equal to Yext

1−2 V1−2 I3−n = Yext V3−n + Y3−n

In which

⎤ 3 0 ··· 0 Yext ⎢ .. ⎥ 4 ⎢ 0 Yext . ⎥ ⎥ =⎢ ⎢ .. . .. . ⎥ ⎣ . . . ⎦ n 0 · · · 0 Yext

(5.8)

⎡

Yext

(5.9)

Combining (5.6)–(5.8), the parameters for the resulted twoport network will be: ¯ = Y 1−2 − Y 3−n (Y + Y 3−n )−1Y 1−2 1−2 Y1−2 1−2 1−2 ext 3−n 3−n

(5.10)

i s to make Y¯ = 0 could be found to realize Using this equation, the set of Yext 12 unilateralization. To check the applicability of this technique, two other conditions must be tested. First, to take advantage of the benefits of this method, it is desirable to realize this gain boost using passive components to form the Yext , requiring its real part to be positive at all frequencies. The unilateral network needs also to be stable. Since the Y 12 = 0, this condition translates to Re(Y 11 ) and Re(Y 22 ) be positive, putting a condition over the original Y parameters set. These will become more clear in the 3-port discussion.

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Fig. 5.4 (a) Unilateral common-source and common gate; (b) simplified small signal model for 3-port CMOS

5.4 Single Transistor Unilateralization The first natural candidate for testing the theory is a single transistor. Ignoring the body terminal for simplification, a transistor is a three terminal device which can be terminated with a proper external impedance to increase the gain as described earlier. In order to see the possibility of this method, we test it for the two widely used gain stages, the common-source and common-gate devices as shown in Fig. 5.4a. For the hybrid-pi model of transistor as depicted on Fig. 5.4b, the admittance metric is: ⎤ −gds −gm − jω c1 gm + gds + jω c1 Y3 = ⎣ −(gm + gds) gds + jω c2 gm − jω c2 ⎦ − jω c1 − jω c2 jω (c1 + c2 ) ⎡

(5.11)

Using these parameters in (5.11), the required Yext could be determined for these two structures. For the common-source structure, it can be readily seen that the unilateralization is not achievable using passive devices since the real part of Yext is negative over all frequencies:

 C1 − gm − jω C1 Yext = −gds 1 + C2

(5.12)

The common-gate is a more interesting. The required Yext for this structure is as follow: ℜ(Yext ) =

ω 2C1C2 gds

ℑ(Yext ) = −ω (C1 + C2 ) −

(5.13) gmC2 gds

(5.14)

5.4 Single Transistor Unilateralization

53

Implying that unilateralization is achievable with a passive inductive impedance. Using a series R-L circuit to realize the load, the required inductance and resistance is Lext =

Rext =

ω2



gds (C1C2 ω )2 1 +C2 )gds +gmC2

(C1 + C2 )gds + gmC2 + (C

Lext C1C2 ω 2 (C1 + C2 )gds + gmC2

(5.15)

(5.16)

Since an inductor at the gate is a classical method to build an oscillator, it’s natural to question the stability of this structure. For the unilaterized common-gate structure, the real parts of Y 11 and Y 22 are as follow

 C1 ≥0 ℜ(Y 11 ) = gm + gds 1 + C2

(5.17)

ω 2 (C1 − C2 )C1 gds ≥ 0 g2m + ω 2C12

(5.18)

ℜ(Y 22 ) =

The first condition is always met. To satisfy the stability at the output, it is needed that C1 be larger than C2 with a proper margin. With a reasonable control over external parasitics, this is almost always the case for CMOS processes hence ensures the stability of the structure. In fact, the condition for oscillation is the opposite of what we are looking for, requiring the Y12 to be equal to infinity. This translates to Yext +Y33 be equal to zero. Considering an inductor at the gate, this condition yields to the familiar frequency of oscillation:

ωosc = 

1 (c1 + c2 )Lext

(5.19)

Using (5.19) and (5.16) it can be shown that the difference between the two frequencies can be shown as follow: (ωosc ωuni )2 ωosc − ωuni = ωosc + ωuni

 (c1 c2 ωuni )2 Lext c2 β + Lext (c1 + c2 ) + c2β

(5.20)

Since this difference is always positive, it implies that the unilateralization frequency always happens first and the difference is a function of the β as well as internal capacitances of the device.

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5.5 Simulated Results and Implementation The value of the required L and R were calculated for NMOS devices of various size in the 90 nm technology. These devices were modeled up to 100 GHz to extract the required device parameters based on the method described in Chap. 2. For a sample 40 × 1 μm/90 nm, Fig. 5.5a shows the magnitude of Y12 and the stability factor. The gate network is set to make Y12 zero at 40 GHz. The stability factor is above one confirming the stability of the device as was predicted in the previous section. Figure 5.5b compares the maximum stable gain as oppose to the maximum unilateral (Mason) gain. The significant difference between the two types of the gain is apparent in frequencies far below the unilateralization frequency. At this frequency, the two gains become equal as suggested by the definition of the Mason gain. Interestingly, the stable gain goes beyond this value. As un-intuitive as it might seem at first, it actually does not contradict with the Mason theory. The theory in fact suggests that the U is the maximum unilateral gain and is invariant to the type of the external network that has been used to realize the unilateralization [2]. The gain boost resulted from this technique could be up to 7 dB at the unilateral point and up to 13 dB at the peak gain depending on the frequency of operation and the size of the device.

Fig. 5.5 (a) Simulated magnitude of Y12 and the stability factor (k) and (b) device maximum stable gain and maximum unilateral gain (Mason gain)

5.5 Simulated Results and Implementation

55

Fig. 5.6 (a) Required Lext and Rext values for unilateralization for NMOS devices of W = 20 μ , 40 μ , and 60 μ , L = 90 nm. (b) Simulated oscillation frequency vs. unilateralization frequency for W = 40 μ

Figure 5.6a shows the corresponding Lext and Rext for three sizes of an NMOS device with the same multi-finger layout structure. The needed inductance is very large at lower frequencies, but quickly drops to reasonable integrable values as the frequency increases to mm-wave region. The required inductor also decreases for larger device sizes due to larger internal capacitances. These two suggest that the method is mostly suitable for relatively large devices and frequencies beyond 5 GHz. Resistance value on the other hand, is quite steady versus frequency and is on the order of few ohms for. Figure 5.6b illustrates how the oscillation frequency changes versus unilateralization frequency for different values of external inductances and shows a significant distance between these two frequencies as predicted by (5.20). Practically, a by pass capacitance is usually used at the gate of common-gate devices to minimize the effects of biasing lines. With a value of few pFs, the self resonance frequency of such capacitors usually happen somewhere in the mm-wave region implying the existence of a series inductance of few pHs with the capacitor. An external inductance in a form of a short transmission line could be used to set a net inductive impedance based on (5.16). The line could also be designed to set the required resistance.

5.5.1 Implementation and Experimental Results Cascode devices are used extensively due to their larger gain and the input-output isolation. The gain benefit that normally associated with cascode structures is not necessarily available at mm-wave frequencies as the unilateral assumption breaks. Figure 5.7 compares the measured maximum available gain (MSG) between a normal common source device and a cascode device. As evident in the figure, the maximum available gain of the cascode device is considerably higher at high frequencies, but gets close to the value for the common source device at mm-wave frequencies. At 60 GHz for example, both devices show similar MSG of around 7.5 dB.

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Fig. 5.7 Comparison of maximum stable gain (MSG) between a common source and cascode structure using similar current

The described technique could essentially be used for cascode structures by placing the required network at the second gate of the device. To calculate the required impedance, the input device and the shared substrate network needs to be counted in the calculations. Using the small-signal model of the device as shown in Fig. 5.8, the required admittance at the second gate could be calculated as follows: ℜ(Yext ) =

  ω 2Cgd G2sub ((3Cgs +Cdb )gm2 + −3Cgs Gsub ) +CdbCgs ω 2 (2Cdb gm2 +Cgs Gsub − 2Cdb gm2 )  2    2 2 Gsub + ω 2Cdb G2sub + ω 2Cgs 

Cgd Gsub (Cdb gm2 −Cgs Gsub )  ℑ(Yext ) = ω 3Cgd −Cgs +  3 2 2 C ω2 Cdb ω +Cdb G2sub −Cgd G2sub −Cdb gd    GsubCgd 2Cdb − 3Cgd (Gsub − gm2 ) − 2 ω 2) (Cdb −Cgd )(G2sub +Cgd

(5.21)

(5.22)

The unilateralization procedure was implemented on a sample 80 μm/90 nm cascode device using an integrated 2 pF external capacitor in series with a total of 50 pH of external inductance. The 2 pF finger “MOM” capacitor was modeled and its internal inductance was used in the modeling process. Figures 5.9a and b the measured and modeled S12 of the device as well as the maximum available gain up to 65 GHz. The fall-off of the magnitude of the reverse reflection parameter, S12 after 20 GHz corresponds to the increase in the

5.5 Simulated Results and Implementation

57

Fig. 5.8 Small-signal model of a cascode structure used in hand calculations

Fig. 5.9 (a) Device S12 ; (b) device maximum stable gain

maximum available gain in the same frequency range. Both these effects are well in agreement with the modeling results. The peak gain at 50 GHz is close to 20 dB which is drastically larger than the 8 dB gain for the case of normal cascode, as shown previously in Fig. 5.7. The noise performance of the device was simulated using Pospieszalski noise model with the aid of the proposed small-signal circuit [5]. The equivalent noise parameter γ was set to 1.3 as suggested by [6]. The effect of unilateralization technique was investigated on the minimum noise figure and equivalent noise resistance (Rn ) by changing the series inductance at the second gate LC tank. The

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Fig. 5.10 Simulated device noise resistance parameter Rn minimum achievable noise figure NFmin

effect is minor as shown in Fig. 5.10a. While NFmin decreases slightly when the device goes into unilateral region, Rn increases and no clear overall benefit or disadvantage is associated with technique in terms of noise performance. However, the technique enables the designer to trade-off gain for noise optimization which results in an overall more power efficient amplifier.

References 1. Cheng CC (1955) Neutralization and unilateralization. IRE Trans Circuit Theory, vol CT-2, no 2, pp 138–145 2. Gupta MS (1992) Power gain in feedback amplifiers, a classic revisited. IEEE Trans Microw Theory Tech, vol 40, no 5, pp 864–879 3. Mason SJ (1954) Power gain in feedback amplifiers. Trans IRE Professional Group on Circuit Theory, vol CT-1, no 2, pp 20–25 4. Niknejad AM (2007) Electromagnetics for High-Speed Analog and Digital Communication Circuits, 1st edn. Cambridge press 5. Pospieszalski MW (1989) Modeling of noise parameters of MESFETs and MODFETs and theirfrequency and temperature dependence. IEEE Transactions on Microwave Theory and Techniques, vol 37, pp 1340–1350 6. Triantis DP (1996) Thermal noise modeling for short-channel MOSFETs. IEEE Transactions of Electron Devices, vol 43, pp 1950–1955

Chapter 6

Terahertz CMOS Devices, Circuits and Systems Sam Gharavi and Frank Chang Electrical Engineering Department, University of California, Los Angeles (UCLA), Los Angeles, CA, USA e-mail: [email protected]

This chapter reviews the state of the art in CMOS devices, circuits and systems operating at 100 GHz and above. Section 6.1 is devoted to the CMOS devices. CMOS geometric scaling is going to reach a point where other technologies such as the III-V, the nano-engineered Graphene, and even the photonics will merge. It is therefore important to understand the possible future paths for the CMOS technology. This topic is presented in Sect. 6.1 by means of introducing two parallel research efforts on the mobility-enhanced FETs and the nano-engineered FETs. We will then present some of the recently-published, ultra-high speed CMOS integrated circuits in Sect. 6.2. Most of the integrated circuits presented in Sect. 6.2 are stand-alone building blocks that are designed to experiment the high-frequency limits of the advanced CMOS nodes. There are also a few circuits which are designed with a specific final application in mind. Finally, in Sect. 6.3 we will review two examples of system-level efforts. Such system-level innovations open new design paradigms that can be exploited by the circuit designers.

6.1 Ultra-High Speed CMOS Devices From the device speed standpoint, at the time of writing this manuscript, the 45 nm CMOS technology with the maximum oscillation frequency of around 400 GHz has the best high-speed performance among all semiconductor technologies which are in large-volume, industrial production. It is also expected that maximum oscillation frequencies of around 600 GHz will be observed shortly in the 22 nm CMOS node [1]. Such high-speed CMOS devices will make it possible to design tuned amplifiers operating at 300 GHz and higher. Therefore CMOS is entering the Terahertz regime. Due to its very low production cost and the possibility of integration with very dense digital circuits, it is natural to think that the CMOS technology will be the mainstream technology for the numerous potential applications in the Terahertz regime.

S. Gharavi and B. Heydari, Ultra High-Speed CMOS Circuits: Beyond 100 GHz, DOI 10.1007/978-1-4614-0305-0 6, © Springer Science+Business Media, LLC 2011

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CMOS technology is the main focus of this book. Interestingly however, it has been predicted that a combination of high-mobility materials such as Germanium (Ge) and Gallium-Arsenide (Ga-As), or even nano-engineered materials such as Graphene will be merged with the super-scaled CMOS devices of 16 nm and lower channel lengths. On the other hand, an interesting research effort has started on building CMOS-compatible photonic integrated circuits [2]. As a result, what is known today as the silicon CMOS, is going to change significantly over the course of next few years. The remainder of this section is divided into two subsections. In the Sect. 6.1.1 we will present the research efforts on the mobility-enhanced FETs. Section 6.1.2 is devoted to the nano-engineered, Graphene-based FETs.

6.1.1 CMOS with Enhanced-Mobility Channel Study of the challenges associated with the scaling of CMOS in the low-nano meter era and the potential solutions to these challenges is the subject of an active and universal research effort. The Emerging Research Material (ERM) working group of the International Roadmap for Semiconductor (ITRS) reports the summary of these research efforts [3]. The ultimate goal of the mentioned research efforts is to design devices that can be used for the analog/RF applications in the terahertz band and are suitable for the VLSI digital applications at the same time. Such devices must exhibit a number of key attributes, most important of which are [4]: 1. 2. 3. 4. 5.

Low access resistance from the outside world to all device terminals High drive current density Thin wells High sheet career density High-energy and thin gate barriers

These constraints are usually quantified and summarized in the device “scaling law”. As an example, Table 6.1 summarizes the scaling law for the FET bandwidth extension by a factor γ [5]. For the CMOS technology, following the scaling laws has become very challenging. In particular, CMOS technology suffers from very poor transport of silicon. This poor transport has become the performance bottleneck in the super-scaled CMOS nodes. The undesired issues caused by the silicon channel in the super-scaled CMOS devices are usually referred to as the “short-channel effects”. These challenges motivated the device engineers to change the standard process flow of the CMOS technology. In particular, device engineers are considering use of other materials with higher electron (and hole) transports to replace silicon in the MOSFET channels of the future transistors. Examples of such materials are the III-V materials with high electron mobility and Germanium (Ge) with high hole mobility. When a new device process is designed it is of very high importance that the drain and the source of the devices remain “self-aligned” to the gate. In [4], a fully self-aligned, MOSFET process with In-Ga-As channel has been developed.

6.1 Ultra-High Speed CMOS Devices Table 6.1 MOSFET scaling law for a bandwidth extension with ratio γ [5] Parameter Gate length, source and drain contact length: Lg , Ls/d (nm) Gate width: Wg (nm) Equivalent oxide thickness: Teq = Toxide εSiO2 /εoxide (nm) Dielectric capacitance: Cox = LgWg εSiO2 /Teq (fF) Inversion thickness: Tinv = Twell /2(nm) Semiconductor capacitance: Csemi = Wg Lg εsemi /Tinv (fF) Density of state capacitance: CDOS = q2 nm∗ LgWg /2π h2 (fF) Electron density: ns (cm−2 ) Gate-channel capacitance: Cg-ch = 1/(1/Cox + 1CDOS + 1/Csemi )(fF) Transconductance: gm ≈ Cg-ch vinj /Lg (mS) Gate-source or drain fringing caps: Cgd ∝ Wg (fF) Source/drain access resistance: Rs , Rd (Ω) Source /drain contact resistivity: (Ω − μm) Drain current: Id ≈ gm (Vgs −Vth )(mA) Drain current density (mA/μm)

61

Law γ −1 γ −1 γ −1 γ −1 γ −1 γ −1 γ −1 γ1 γ −1 γ0 γ −1 γ0 γ −1 γ0 γ1

In this process, a 4.7 nmAl2 O3 gate dielectric is deposited on a 5 nm In0.53 Ga0.47 As channel. The gate is made of a blanket W/Cr/SiO2 deposition. The source and drain regions are made of 50 nm thick InAs and are fully self-aligned to the gate. The source and drain contacts have 1 − 3Ωμm2 resistance. Figures 6.1 and 6.2 show a micro-photograph of the fabricated devices in this process along with the DC drain current of a 200 nm gate length device in this process, respectively. Currently, the state of the art, mobility-enhanced FET devices are still in the research phase. Many challenges must be addressed in the lab before these new devices can replace the silicon in an industrial setting [3].

6.1.2 Graphene High-Speed Transistors Invention of Graphene (two-dimensional sheet of carbon atoms) in 2004 ignited a revolution in the science and technology [6].1 This exciting discovery grabbed the attention of the solid-state physics community very quickly. Device engineers 1 Inventors

of Graphene were awarded the Nobel Prize in physics in October 2010.

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Fig. 6.1 InGaAs FET, (a) oblique view (b) cross c IEEE sectional view [4] ( 2010)

c IEEE 2010) Fig. 6.2 Current for a 200 nm gate length III-V FET in [4] (

6.2 Ultra-High Speed CMOS Circuits

63

recognized a great potential in Graphene from solid state devices perspective. The most exciting features of Graphene from a device engineering perspective are: (1) it’s very high carrier transport, (2) it’s purely two-dimensional lattice structure. These promising attributes motivated the fabrication of the first Graphene-based FET in 2007 [7]. Shortly after that the first high-speed Graphene FET with a Gigahertz cut–off frequency was reported in 2008 [8]. The exceptional features of Graphene make it an ideal candidate for the ultra-high speed FET devices. Graphene transistors with the record cut-off frequencies of 300 GHz have been reported recently [9]. The achieved device speed in [9] is significantly higher than the silicon CMOS devices with comparable gate lengths. Due to the immaturity of Graphene FET technology, Graphene FET speeds s are far behind what Graphene can potentially offer in theory. Graphene FET is theoretically a promising alternative for silicon FET. However, many problems with the existing implementations of the Graphene FET devices must be addressed before Graphene can replace silicon in the industry. The most challenging technical issue is creating a well-controlled and high-yield band gap for Graphene. Such band gap will resolve the poor turn-off and weak drain-current saturations of the current Graphene FETs [10].

6.2 Ultra-High Speed CMOS Circuits Non-stopping device scaling has made the integrated circuit design to undergo a fundamental change of paradigm. In classical integrated circuit world, the onchip dimensions were much smaller than the on-chip wavelengths at the operation frequencies of the chips. This fact has considerably changed over the past few years; main due to two reasons (1) the increased size of the chips due to the increased complexity of the systems (2) the decreased cut-off wave-length2 of the devices due to the geometric scaling. Figure 6.3 shows these trends and the mentioned shift of paradigm [11]. There is no efficient and systematic method for designing circuits in the mentioned new paradigm yet. It is instructive however, to review the techniques exploited by different researchers. The following examples in this section (Sects. 6.2.1– 6.2.6) were chosen to familiarize the reader with a diverse set of terahertz circuit design techniques. One keystone to all these design strategies is the accurate modeling of the active and passive devices in order to predict the performance of the circuit. Modeling can be either merely simulation-based [12] or based on a combination of previous measurements and simulations [13].

2 The cut-off wavelength denoted by λ , is defined as the wavelength of the electromagnetic waves T travelling on the chip at the cut-off frequency of the device.

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6 Terahertz CMOS Devices, Circuits and Systems

Fig. 6.3 Chip size and cut-off wavelength as a function of time [11]

6.2.1 Nano-Scale CMOS Transceivers in the 90–170 GHz Range Authors in [14] have reported their CMOS transceivers operating in the 90–170 GHz range. They have also outlined their design methodology and have delved into the design issues on the architecture, circuit, and device layout levels. From the final application standpoint, due to the comparable power levels of the radios and imagers, authors of [14] believe that the same transceivers are suitable for both imaging and wireless radio applications. An attention-grabbing architecture for a passive imaging camera is proposed in [14]. The proposed camera architecture is a combination of the beamforming array architecture and the traditional switched-antenna passive imagers. The proposed architecture has a sub-array, zoom-in capability that can be turned on only if needed. In other terms, different subsets of pixels can be grouped together in a beamforming manner only if zooming is desired in a certain direction.3 In order to save power, the proposed imager can also operate in the low-resolution, low-power mode with minimum active pixels. A block diagram of this imaging architecture [14] is shown in Fig. 6.4. Working at frequencies above 100 GHz offers an enormous advantage for onchip integration of imagers. At these frequencies, the distance between the adjacent antennas4 in a phased array becomes comparable to the dimensions of the on–chip transceivers. Therefore large number of pixels can be integrated on a single standard CMOS die without any extra area overhead from the antennas.

3 We

will see in the next chapter that beamforming increases spatial resolution of an imager, by increasing its effective aperture size. 4 In a phased array antenna, the distance between adjacent antenna elements is usually set around half of the free-space wavelength at the operation frequency of the array. At 100 GHz, the freespace wavelength is about 3 mm and the antenna element spacing is therefore around 1.5 mm.

6.2 Ultra-High Speed CMOS Circuits

65

c IEEE 2009) Fig. 6.4 Passive low-power camera with zoom-in capability proposed in [14] (

In their previous publications, the same research group as in [14], had introduced a high-frequency, CMOS sizing and biasing methodology called the “constant current densities” [15]. The inspiration behind this design methodology is that there are current densities at which the high-frequency performance of the CMOS is optimum. These current densities have been shown to remain fairly constant when the CMOS devices scale down. As a result, these optimal current density rules can be applied to various advanced CMOS nodes. For example, many advanced CMOS nodes exhibit their best maximum oscillation frequency, fmax , at a current density 5 close to 0.25 mA μm . Figure 6.5 [15] shows the fmax of a few submicron CMOS nodes. As evident from this figure, the current density at which these devices show their highest fmax is fairly constant. The mentioned design strategy can be very helpful when a circuit needs to be transferred from an older technology node to a more advanced node. In particular if reliable, RF, device models are not available yet for the new technology node. Authors in [14] believe that the transistor device layout is one of the most significant factors that determine the performance of circuits operating at 100 GHz and above. As such, they have suggested that different device layouts be used for different circuit applications. The justification behind this suggestion is that different device layout parasitic elements have different impacts on the transistor RF performance. For example, often in a low-noise amplifier (LNA) the most imperative device metric is the minimum noise figure, NF min , which is most sensitive to the parasitic gate resistance. Therefore transistor layouts that minimize the gate parasitic resistance are the most favorable for the low-noise amplifiers design. However, the same layout strategies might not be optimal for a power amplifier (PA) or a tuned amplifier designs. This is why having at least five specialized layouts are highly

5 Current

densities are per unit width of the transistors.

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6 Terahertz CMOS Devices, Circuits and Systems

Fig. 6.5 Measured maximum oscillation frequency of different CMOS.technology nodes as function of current density c IEEE 2007) [15] (

recommended for the circuit design at 100 GHz and above. These specialized device layouts are: 1. 2. 3. 4. 5.

Common-source stage with grounded source Common-source stage with inductive degeneration Common-gate stage Cross-coupled pair for VCO Differential pairs

As mentioned earlier in this chapter, modeling plays a critical role in the ultra-high speed circuit design. An algorithmic modeling approach based on iterations between the electromagnetic (EM) simulations of the passive components, schematic simulations and RC-extractions of the transistors is described in [14]. By applying all these design techniques, authors in [14], have designed a set of CMOS transceivers operating in the 90–140 GHz range. As an example, Fig. 6.6 shows the block diagram and the die photograph of a 140 GHz CMOS receiver reported in [14]. The mentioned receiver is designed in the 65 nm CMOS technology and includes an on-chip dipole antenna, a LNA, a double-balanced mixer and IF amplifiers. In line with the optimal current density method described above, most of the transistors have been biased at 0.25 mA/μm which corresponds to peak fmax of the process. Lumped, spiral inductors and transformers (as opposed to transmission-line-based inductors) have been used for matching at all places. No RF process options (e.g. MIM caps) beyond the pure digital CMOS process have been exploited in this design. All decoupling capacitors were implemented as metal-on-metal (MoM) capacitors.

6.2 Ultra-High Speed CMOS Circuits

67

c IEEE 2009) Fig. 6.6 Block diagram and die photograph of a 140 GHz receiver reported in [14] (

Testing the integrated circuits operating at 100 GHz and above imposes unique challenges. The mentioned 140 GHz receiver has been no exception. Due to the lack of viable, external local oscillator (LO) signals at 140 GHz, authors in [14] have driven their circuit with an LO signal at 100 GHz for the conversion gain measurement of the receiver chain. The measurement results are shown in Fig. 6.7.

6.2.2 CMOS THz Oscillator Based on Linear Superposition [16] Authors in [16] reported a 324 GHz CMOS frequency generator. This frequency generator superimposes the phase-shifted versions of a fundamental oscillation at 81 GHz. One of the novelties of this design is in the introduction of the “linear

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6 Terahertz CMOS Devices, Circuits and Systems

c IEEE 2009) Fig. 6.7 Rx chain conversion gain for the 140 GHz receiver in [14] (

c IEEE 2008) Fig. 6.8 Linear superposition method for frequency quadrupling reported in [16] (

superposition” technique. In this technique, which is conceptually depicted in Fig. 6.8, four sinusoidal signals at a frequency f0 are phase-shifted, rectified, and added to each other. The resulting waveform will have a strong harmonic at 4 f0 . The theoretical efficiency of this superposition is about 17% [16]. One attractive property of the linear superposition method is its generality. The same method is applicable to other technologies and other frequencies.

6.2 Ultra-High Speed CMOS Circuits

69

Fig. 6.9 Schottky diode cross section and equivalent circuit model in a CMOS technology [17] c IEEE 2010) (

6.2.3 THz CMOS Push–Push Oscillator [17] Authors in [17] believe that until the CMOS technology is capable of amplification at THz, passive detectors based on the Schottky diodes offer a viable option, compatible with the CMOS fabrication. Such diodes can exhibit cut-off frequencies as high as 1 THz and can be used for frequency multiplication to generate THz signals. The cross-section and circuit model of a Schottky diode in the CMOS technology are depicted in Fig. 6.9. Also authors in [17] have demonstrated a 410 GHz CMOS, push-push VCO in the 45 nm CMOS technology. The push technique has been exploited in the design of the mentioned VCO in order to multiply the fundamental frequency. As mentioned before, one tricky part of the Terahertz integrated circuit laboratory development process is the testing and measurement. Since no commercial electronic probe can operate at frequencies above 110 GHz, measurements should rely on other innovative techniques. One of these techniques is to radiate the signals using an on-chip antenna. This technique was exploited in the measurement setup of the mentioned 410 GHz CMOS VCO in [17]. The spectrum of the radiated electromagnetic waves has then been measured using the optical infrared equipment. The schematic and die photograph of the circuit are shown in Fig. 6.10.

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c IEEE 2010) Fig. 6.10 simplified schematic and die photograph of the 410 GHz VCO in [17] (

Fig. 6.11 Oscillator c IEEE topology in [18] ( 2010)

6.2.4 300 GHz Fundamental-Tone Oscillator in CMOS None of the on-chip oscillators previously shown in this chapter were fundamental oscillators. A fundamental (first harmonic), 300 GHz, CMOS oscillator is reported in [18]. The proposed circuit topology for this oscillator is different from the conventional, cross-coupled pairs and allows the core oscillator circuit to tolerate higher device non-idealities. Due its superior circuit topology, the designed oscillator in [18] has been capable of providing a fundamental oscillation at 300 GHz while consuming only 3.5 mA from a 1 V supply in the 65 nm CMOS technology. The VCO topology is shown in Fig. 6.11. In order to simplify the measurements, a down-conversion mixer driven by an external, W-band source is also integrated with the oscillator on the same chip. A die photograph of the oscillator and the mixer is shown in Fig. 6.12.

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Fig. 6.12 Die photograph of the oscillator and mixer in c IEEE 2010) [18] (

6.2.5 600 GHz CMOS Passive Imager A focal plane, passive imaging array operating at 600 GHz is presented in [19]. The “self-mixing” phenomenon, which is caused by the signal leakage in the resistive, down-converting mixers, is exploited and embraced as an energy detection scheme in this work. The self-mixing scheme eliminates the need for a local oscillator signal. The main drawback of the self-mixing method is that it entirely loses the phase information of the signal. A block diagram and die photograph of the detector is shown in Fig. 6.13. The input signal is sensed by an on-chip, folded dipole antenna and is then applied to the self-mixing, differential pair. Additional capacitors C1 and C2 have been added to enhance the leakage and self-mixing. Transmission lines TL1 and TL2 have been used for power matching. One interesting aspect of this work is that it has been implemented in the 0.25μ CMOS technology with the maximum oscillation frequency on the order of 30 GHz (twenty times smaller than the operation frequency of the imager). This has been feasible because the imager is fully passive and the self-mixing scheme eliminates the need for the LO signal. The focal-plane, passive, imager array has been tested and proved functional. The test setup and measurement results are available in [19].

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Fig. 6.13 Block diagram and die photograph of the one pixel of the passive focal plane imager in c IEEE 2008) [19] (

6.2.6 200 GHz CMOS Frequency Divider Frequency dividers are keystones to the frequency synthesis. There is a traditional tradeoff between the division center frequency and the locking ratio of the frequency dividers. In order to relax this tradeoff, a novel frequency division scheme that can support locking ranges as wide as %20 at frequencies as high as 200 GHz has been proposed and implemented in [20]. More specifically, Authors of [20] have suggested the injection of both voltage and current signals in a time-interleaved scheme in order to increase the locking range. This novel idea has been implemented in the TSMC 65 nm CMOS technology.

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As with other ultra-high speed circuit blocks reviewed in this section, testing of this chip has imposed unique challenges. In particular, generating a 200 GHz signal with sufficient power to server as the divider input is quite challenging. Authors of [20] have devised a three-step testing technique to overcome the abovementioned challenge. A mm-wave external source has been fed to the cascade of a multiplyby-three block, a power amplifier and a multiply-by-two block to generate the 200 GHz input signal with adequate power. The figure of merit of the circuits6 in [20] outperforms that of all previously shown, similar works.

6.3 Ultra-High Speed Systems This section is devoted to the ultra-high speed system efforts. Section 6.3.1 delves into the challenges and opportunities of the terahertz, wireless, data communication systems with potential data rates of tens of Gbps. To the best of our knowledge, no illustrations of such systems have been reported in the CMOS technology yet. However, there is a huge pool of potential applications. Section 6.3.2 is devoted to the concept of near-field, direct, antenna modulation (NFDAM). NFDAM is a novel architecture that has become implementable on-chip, and also has an enormous potential for new wireless applications at frequencies above 100 GHz.

6.3.1 Ultra-High-Speed Data Communication By a simple extrapolation of the data rates of the commercial, wireless data communication systems from 1990s to today, we can expect that data rates as high as 10–20 Gbps will be needed soon. Presently, the highest data-rates for the commercial, wireless data communication systems belongs to the 60 GHz radios which can support up to 5 Gbps (in short range). Current systems therefore do not meet the required data rates of 10–20 Gbps for the future. One natural way of increasing the data rates is moving to the higher center frequencies with more accessible bandwidths. Two options for the higher frequency bands can be imagined: (1) near infrared/visible range (2) terahertz band (from 100 GHz to 10 THz). There are several factors that severely limit the achievable data rates at the infrared frequencies and above. These factors include the eye safety power limit, the poor sensitivity of detectors and receivers at the visible range, and the high ambient light noise from the natural radiations [21]. The alternative is moving to the terahertz band. For example, there is almost 50 GHz of unregulated bandwidth centered around 350 GHz [21]. This band also enjoys a relatively low

6 Figure-of-merit

for frequency dividers is defines as the center frequency times the locking range divided by the power consumption.

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Fig. 6.14 Measurement of refractive index and absorption of a sample at THz for the purpose of c IEEE 2007) channel modeling [22] (

atmospheric attenuation. A link budget analysis at this band reveals the need for highly directive antennas, with gains on the order of 30 dBi [21].7 The preferred mode of communication at terahertz is the directive, line of sight (DLOS) communication. However, if the DLOS is blocked by an object, directive, non-line of sight (DNLOS) might be exploited to close the communication link [21]. The idea behind DNLOS is to have “mirrors” that can properly reflect and redirect the blocked DLOS [21]. Due to the tight link budgets, precise modeling of the communication channel is a key to the successful design of ultra-high data rate systems. Such accurate channel modeling requires characterization and modeling of the scattering profile of different materials in indoor and outdoor scenarios. A channel modeling research effort based on the three-dimensional ray-tracing for the terahertz wireless can be found in [22]. Figure 6.14 shows an example of the measured scattering parameters in [22]. Based on the channel models and the link budget analysis, achievable data rates for a 350 GHz communication link have been simulated in [21]. Figure 6.15 shows two of such simulations for the line of sight and non-line of sight scenarios. Based on these simulations, data rates as high as 10 Gbps seems reasonably achievable.

7 Considering

that free space path loss at 300 GHz for one meter is about 80 dB, which is roughly 20 dB higher than the path loss for an average WLAN communication system working at 3 GHz, and the lower power level of sources at higher frequencies, the need for the high-gain antennas makes sense.

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Fig. 6.15 Simulated achievable data rates for a 350 GHz wireless link indoors (a) through line c of sight (b) through multiple scattering rays. Unit for data-rate numbers is Gbps [21] ( IEEE 2008)

From the hardware standpoint, one of the most challenging components in a terahertz communication system is the modulated source. We will return to the problem of Terahertz sources in the next chapter. A wireless radio operating at 300 GHz is reported in [23]. Although this radio operates at a rather low data rate of around 100 Mbps, it proves the feasibility of closing a wireless link at 300 GHz. For the future, ultra-high speed, wireless, data communication systems, utilizing the diversity is a necessity. Diversity which can be in time, frequency, or space, helps overcome severe channel conditions and increases the throughput of the system [24]. In particular, spatial diversity is more attractive at higher frequencies due to the short wavelengths and small antenna dimensions. In addition to the conventional beamforming, spatial multiplexing schemes can also be used [24]. In the spatial multiplexing, several independent data streams are transmitted through the channel. Spatial multiplexing has been mostly exploited by the wireless communication

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Fig. 6.16 NFDAM-based communication system. Antenna pattern changes by means of switchable reflectors in the vicinity of the main radiator. Received data is a function of direction [26] c IEEE 2009) (

systems working at a few gigahertzes. However, examples of mm-wave wireless communication systems utilizing the spatial multiplexing has been shown in [25].

6.3.2 Direct Antenna Modulation Systems The miniature wavelengths at 100 GHz and above make it possible to have multiple, on-chip, radiating elements. Moreover, adding the active switching devices to these radiating elements makes it possible to merge the electromagnetic boundary conditions with data transmission in a variety of ways [26]. One possible scheme for mixing the data transmission and the electromagnetic boundary conditions is through the “near-field direct antenna modulation” (NFDAM) [27]. Unlike the conventional, baseband-modulation systems in which modulation symbols sent by a transmitter are the same at all spatial directions, NFDAM makes it feasible to have direction-dependent data streams. As a result, higher security can be achieved. The idea in the NFDAM is that the binary data bits modulate the phase and amplitude of the antenna patterns. As a result, receivers located at different directions in the space will receive different modulation data from the same transmitter. Antenna patterns can be changed by altering the electromagnetic boundary conditions of the antenna through a few reflectors in the vicinity of the main radiator. These reflectors are controlled by an array of switches driven by the binary bits. Figure 6.16 shows a conceptual NFDAM system. Due to the strong dependence of the received data on the spatial direction, NFDAM systems have a very narrow “information beam-width”. Information beamwidth is defined as the range of angles at which the bit error rate (BER) of the system remains within a specific range. Figure 6.17 shows the BER of a NFDAM-based system as a function of the angular position [26].

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Fig. 6.17 Information beam-width of a NFDAM – based communication system [26]. System’s c IEEE bit error rate drops sharply as a function of deviation angle from the intended direction ( 2009)

Fig. 6.18 A sample block diagram of a NFDAM system. Main radiator antenna is a dipole and baseband data controls the reflectors by means of switches. Baseband coarse control signals A and c IEEE 2009) B are optional [26] (

Another interesting property of the NFDAM systems from the circuit’s standpoint is their relaxed bandwidth requirements for the power amplifier. Because a constant-envelop, locked carrier signal goes through the power amplifier, a highly efficient and narrowband power amplifier can be used, regardless of the system’s bandwidth. This point can be better understood by looking at the system block diagram of an NFDAM system in Fig. 6.18 [26]. NFDAM systems can also be used in a phased array configuration. While the low information beam-width of the NFDAM systems provides higher security, the reduced antenna beam-width of the phased array will lead to higher power efficiency. This concept is shown in Fig. 6.19. Fully integrated NFDAM systems have been demonstrated in [27] at the 60 GHz. A similar concept is reported at 90 GHz in [28].

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Fig. 6.19 Left: single NFDAM system right: NFDAM systems in a phased array configuration c IEEE 2009) [26] (

6.4 Chapter Summary and Conclusion In this chapter we reviewed cases of ultra-high speed CMOS devices, circuits and systems. As we discussed in Sect. 6.1, CMOS technology is about to undergo changes in order to accommodate the RF circuits working at the terahertz band, and the VLSI digital circuits. In particular, one major impediment to the performance of the super-scaled CMOS is the poor transport of silicon. This problem can be mitigated by introducing self-aligned processes that use high-mobility compounds or nano-engineered materials in their channels. At circuit level, the shift of paradigm from the traditional electronic world to the new era in which chip dimensions are comparable to (or even bigger than) the wavelength was introduced in Sect. 6.2. As we saw in Sect. 6.2, there is no systematic design flow for the terahertz CMOS circuit design. Different designers have their own methods. One keystone to the design process is the iterative electromagnetic modeling of the passive components and the active device parasitic extraction. We also saw that testing the integrated circuits at terahertz frequencies imposes unique challenges due to the lack of standard equipment at theses frequencies. We saw how testing can be done at these frequencies by introducing on-chip antennas, on-chip down-conversion of the signals or through other innovative methods. At the system level, we reviewed two research efforts. One is for the future ultra-high speed, wireless data communications and the other is the near-filed direct antenna modulation.

References

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References 1. Sankaran S, Chuying M, Eunyoung S, Dongha S, Changhua C, Ruonan H, Arenas DJ, Tanner DB, Hill S, Chih-Ming H, O, KK (2009) Towards terahertz operation of CMOS. Solid-State Circuits Conference – Digest of Technical Papers, 2009. ISSCC 2009. IEEE International, pp.202–203,203a, 8–12 Feb. 2009 2. Heinz-Wilhelm H. (2010) Terahertz technology: Towards THz integrated photonics. Nat Photon 4:503–504 3. http://www.itrs.net/Links/2009ITRS/2009Chapters 2009Tables/2009 ERM.pdf 4. Rodwell MJW, Singisetti U, Wistey M, Burek GJ, Carter A, Baraskar A, Law J, Thibeault BJ, Kim EJ, Shin B, Lee Y-J, Steiger S, Lee S, Ryu H, Tan Y, Hegde G, Wang L, Chagarov E, Gossard AC, Frensley W, Kummel A, Palmstrom C, McIntyre PC, Boykin T, Klimek G, Asbeck P (2010) III-V MOSFETs: scaling laws, scaling limits, fabrication processes, 2010 International Conference on INDIUM PHOSPHIDE & RELATED MATERIALs (IPRM), pp.1–6, May 31 2010-June 4 2010 5. Rodwell M, Frensley W, Steiger S, Chagarov E, Lee S, Ryu H, Tan Y, Hegde G, Wang L, Law J, Boykin T, Klimek G, Asbeck P, Kummel A, Schulman JN (2010) III-V FET Channel Designs for High Current Densities and Thin Inversion Layers. IEEE Device Research Conference, June 21–23, 2010, South Bend, Indiana 6. Novoselov KS et al. (2004) Electric field effect in atomically thin carbon films. Science 306:666–669 7. Lemme MC, Echtermeyer TJ, Baus M, Kurz H (2007) A graphene field-effect device. IEEE Electron Dev Lett 28:282–284 8. Meric I, Baklitskaya N, Kim P Shepard KL (2008) in Tech. Dig. IEDM 2008, paper 21.2 (IEEE, 2008) 9. Liao L, Lin Y-C, Bao M, Cheng R, Bai J, Liu Y, Yongquan Q, Wang KL, Huang Y, Duan X (2010) High-speed graphene transistors with a self-aligned nanowire gate. Nature, Sept 1, 2010 10. Schwierz F (2010) “Graphene transistors”. Nat Nanotechnology 5:487–496 (30 May 2010) doi:10.1038/nnano.2010.89 Review 11. Babakhani A, et al. (2009) “10 years of silicon millimeter waves: from oxymoron to reality”, Lee Center workshop 2009, http://leecenter.caltech.edu/workshop09/talks/hajimiri.pdf 12. Liang CK, Razavi B (2009) Systematic transistor and inductor modeling for millimeter-wave design. IEEE J Solid State Circ 44(2):450–457, Feb. 2009. doi: 10.1109/JSSC.2008.2011031 13. Doan CH, Emami S, Niknejad AM, Brodersen RW (2005) Millimeter-wave CMOS design. IEEE J Solid State Circ 40(1):144–155, Jan. 2005. doi: 10.1109/JSSC.2004.83725 14. Laskin E, Khanpour M, Nicolson ST, Tomkins A, Garcia P, Cathelin A, Belot D, Voinigescu SP (2209) Nanoscale CMOS transceiver design in the 90–170-GHz range. IEEE Trans Microw Theor Tech 57(12):3477–3490 15. Terry Y, Gordon MQ, Tang KKW, Yau KHK, Ming-Ta Y, Schvan P, Voinigescu SP (2007) Algorithmic design of CMOS LNAs and PAs for 60-GHz radio. IEEE J Solid State Circ 42(5):1044–1057 16. Daquan H, LaRocca TR, Chang M-CF, Samoska L, Fung A, Campbell RL, Andrews M (2008) Terahertz CMOS frequency generator using linear superposition technique. IEEE J Solid State Circ 43(12):2730–2738 17. Eunyoung S, Dongha S, Chuying M, Ruonan H, Sankaran S, Changhua C, Knap W, Kenneth KO (2010) Progress and challenges towards terahertz CMOS integrated circuits. IEEE J. Solid State Circ 45(8):1554–1564 18. Razavi B (2010) A 300-GHz fundamental oscillator in 65-nm CMOS technology,” 2010 IEEE Symposium on VLSI Circuits (VLSIC), pp.113–114, 16–18 June 2010. doi: 10.1109/VLSIC.2010.5560333 19. Pfeiffer UR, Ojefors E (2008) A 600-GHz CMOS focal-plane array for terahertz imaging applications, Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European, pp.110–113, 15–19 Sept. 2008

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20. Gu QJ, Heng-Yu J, Zhiwei X, Yi-Cheng W, Chang MCF, Baeyens Y, Young-Kai C (2010) 200GHz CMOS prescalers with extended dividing range via time-interleaved dual injection locking. 2010 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp.69–72, 23–25 May 2010 21. Piesiewicz R, Jacob M, Koch M, Schoebel J, Kurner T (2008) Performance analysis of future multigigabit wireless communication systems at THz frequencies with highly directive antennas in realistic indoor environments. IEEE J Sel Top Quant Electron 14(2):421–430, March-April 2008 22. Piesiewicz R, Jansen C, Mittleman D, Kleine-Ostmann T, Koch M, Kurner T (2007) Scattering analysis for the modeling of THz communication systems. IEEE Trans Antenn Propag 55(11):3002–3009, Nov. 2007 23. Jastrow C, Priebe S, Spitschan B, Hartmann J, Jacob M, Kurner T, Schrader T, KleineOstmann T (2010) Wireless digital data transmission at 300 GHz. Electron Lett 46(9):661–663, April 2010 24. Tse D, Viswanath P (2005) Fundamentals of wireless communications. Cambridge University Press, Cambridge. 25. Sheldon C, Seo M, Torkildson E, Rodwell M, Madhow U (2009) Four-channel spatial multiplexing over a millimeter-wave line-of-sight link, Microwave Symposium Digest, 2009. MTT ’09. IEEE MTT-S International, pp.389–392, 7–12 June 2009 26. Babakhani A, Rutledge D, Hajimiri A (2009) Near-field direct antenna modulation. IEEE Microw Mag 10(1):36–46, February 2009 doi: 10.1109/MMM.2008.930674 27. Babakhani A, Rutledge DB, Hajimiri A (2008) Transmitter architectures based on near-field direct antenna modulation. IEEE J Solid State Circ 43(12), Dec. 2008. 28. Arbabian A, Afshar B, Chien J-C, Kang S, Callender S, Adabi E, Dal Toso S, Pilard R, Gloria D, Niknejad AM (2010) A 90GHz-carrier 30GHz-bandwidth hybrid switching transmitter with integrated antenna. IEEE Int Solid State Circ Conf to appear in the 2010

Chapter 7

Imaging Applications Sam Gharavi and Frank Chang Electrical Engineering department, University of California, Los Angeles (UCLA), Los Angeles, CA, USA e-mail: [email protected] Mohammed H. Gharavi Tehran University of Medical Sciences, Tehran, Iran

Applications of the CMOS technology above 100 GHz are much less recognized than its applications below 100 GHz. Envisioned applications for the CMOS above 100 GHz can be divided into two main groups: (1) the imaging applications and (2) non-imaging applications. Imaging applications range from the medical imaging to remote sensing to security and concealed weapon detection. Non-imaging applications include (but are not limited to) very fast wireless or chip-to-chip communications and industrial sensors. This chapter is devoted to the imaging applications. The chapter starts by discussing the basics of imaging physics. After the general imaging introduction, we will review the medical imaging. Finally, at the end of this chapter, a few emerging imaging applications at the terahertz frequency band is outlined.

7.1 Photons Interaction with Matter Although the term “imaging” has a much broader meaning, what we mean by imaging in this chapter is only limited to the sensing of the energy waves emitted by an object in order to extract information about the object’s physical structure and/or compounding materials. Most often, the mentioned energy waves are electromagnetic waves. Electromagnetic waves interact with objects at photon level. Interaction of a photon with a material is a random event with different possible outcomes. Photon may just pass through the material or it may hit a non-uniformity (e.g. an atomic particle or cells in tissues or surface roughness) when it travels in the material. When a photon hits an atomic particle it injects energy to the atom. In other terms, the photon “excites” the atom. The electron cloud of the excited atom typically radiates back the photon’s extra energy through the emission of a second photon at a different direction (and possibly with a different wavelength) compared to the primary photon. This type of interaction which involves the deviation of the

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82 Fig. 7.1 Scattering of a photon due to collision with an atom. The secondary photon is deviated and might have a different wavelength, compared to the primary photon

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λ1

Ε

λ2 θ

primary photon from a straight trajectory is called “scattering”.1 Figure 7.1 shows a conceptual photon scattered after colliding with an atom [1]. Another possible outcome of the interaction of a photon with a martial is called the “absorption”. Absorption happens when the photon energy is transformed to heat or to other types of energy and hence the atom doesn’t radiate any secondary photon.

7.2 Active and Passive Imaging In the context of imaging, electromagnetic waves that are emitted from an object can either originate from the natural emissions of the object or can be in response to an energy wave sent from the imager. Imagers are classified as either passive or active based on this difference. Active imagers transmit their own electromagnetic energy toward the objects in a scene and sense the waves after they interact with the objects.2 Passive imagers on the other hand, rely on the electromagnetic energy that is naturally emitted from the objects. This natural radiation is sometimes called the “blackbody radiation” and is a function of the object’s temperature and the materials that object is made of. Due to the low power-level of the natural radiations, passive imaging is generally more prone to noise and therefore requires receivers with higher sensitivity. Compared to active counterparts, passive imagers can operate with lower power consumption because they do not have transmitters. Passive imagers are also completely harmless to the object or tissue that is imaged. Active imagers require a computationally-expensive post-processing step called the “inverse scattering” in order to form an image. This is while passive imagers usually do not require the inverse scattering and are hence less computationally expensive. Active imagers typically can reproduce the image of a scene regardless of the illumination conditions while passive imagers are more prone to the environmental variations such as natural and artificial illuminations of the environment [2]. 1 Several

different scattering mechanisms such as Rayleigh scattering and Thompson scattering have been defined in Physics. As an introductory text on imaging, we choose to treat all these scattering types similarly in this chapter. 2 Most imagers sense the waves that are scattered back from the object but some imaging systems such as X-ray measure the waves that pass through the objects.

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7.3 Optical Versus Non-optical Imaging When we think of imaging optical imaging is the first thing that comes to mind. Optical imaging uses electromagnetic energy in the infrared, visible and sometimes ultraviolet range. If the electromagnetic waves used for in the imaging don’t lie in the mentioned range, imaging can be called “non-optical”. Examples of non-optical imaging are X-ray, mm-wave and terahertz imaging. Figure 7.2 shows examples of images taken at the mm-wave spectrum [2].

7.3.1 Responsivity In the context of imaging, a detector is a transducer that converts the optical energy to the electrical energy. Responsivity is the conversion gain of the detector and is usually expressed as Ampere/Watts or Volts/Watts. Responsivity is a function of the photon’s wavelength, λ , and the quantum efficiency3 of the detector, η , and can be expressed as: η R = q hc (7.1) λ

In (7.1), R is the detector’s responsivity with the unit of Ampere/Watts, q is the charge of an electron and h is the Plank’s constant. As a numerical example, a 300 GHz imager with 50% quantum efficiency has responsivity equal to 402.8 Ampere/Watts.

Fig. 7.2 Passive millimeter wave imaging examples. Left: optical image of a man hiding a c IEEE 2003) weapon. Right: passive mm-wave image of the same person [2] (

3 Quantum

efficiency is defined as the average number of electron-hole pairs that are released, per each photon that is collected by the detector.

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7.4 Attenuation We previously mentioned that the photon interaction with material is a random process. The statistical distribution of the possible interactions of a photon with a host material depends on the photon’s wavelength and the atomic structure of the host material. For example, the probability that a photon scatters at some point during its travel in a host material is a function of the photon’s wavelength, the atomic structure of the host material and the thickness of the host martial slab. As an insightful and general rule, the higher the atomic number of the host material and the thicker the slab of the material the higher the likelihood of scattering [1]. One commonly used notion in all physical sciences is the notion of “attenuation”. In the context of matter and photon interaction, attenuation is the process of elimination of photons from a beam of photons as the beam travels in a host material. Both absorption and scattering of the photons contribute to the attenuation. Depending on the photon energy4 level, either absorption or scattering can be the dominant attenuating mechanism. Attenuation is usually expressed per unit of host material thickness. As an example, Fig. 7.3 shows the attenuation of the electromagnetic waves as they pass through one kilometer of the atmospheric material [2].

Fig. 7.3 Attenuation of electromagnetic beam caused by travelling 1km in atmosphere at different c IEEE 2003) wavelengths and for different weather conditions [2] ( 4 Photon

energy and wavelength are related through Planck’s equation.

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By looking closely at Fig. 7.3, we can recognize “propagation windows” at which the atmospheric attenuation exhibits a local minimum. Some of these windows are centered at λ = 8.5, 3.2, 2.1 and1.3 mm, corresponding to the frequencies of 35, 94, 140, and 220 GHz, respectively. These propagation windows are suitable for longdistance wireless communications, imaging or radar.

7.5 Image Quality Metrics Image quality is a broad concept that applies to all types of images from medical images to photographs to radar images. Quality therefore depends on the ultimate purpose of an image. For example, in the medical imaging, the more accurately an image can help diagnose an abnormality the higher its quality. Humans are very visual creatures and they can quickly assess the quality of an image by just looking at it. However, in order to quantify the image quality, we need to understand the metrics commonly used to measure the image quality. We also need to know how different physical parameters affect each image quality metric. The metrics used to describe the image quality are rather universal. The intended function of the image determines which parameter is more important. For example, to diagnose a very small tumor in a tissue, image needs to have a high “spatial resolution”. However, to distinguish two big masses made of very similar materials the image needs to exhibit a high contrast between the two materials. These concepts are briefly described here.

7.5.1 Spatial Resolution Spatial resolution (or simply resolution) is a measure of the imaging system’s ability to distinguish between two separate small objects as they get smaller and closer together.5 Spatial resolution is tightly connected to the “point spread function (PSF)” of the imaging system. If we consider an imaging system as a linear and time-invariant system whose input is the physical object and whose output is the image of the object, then the PSF is the impulse response of the system. To have a better understanding of the PSF, consider a very narrow wire as the object (input). Because this object (input) closely resembles an impulse, the image (output) of it closely resembles the imaging system’s PSF. It is needless to say that an ideal imaging system is the one whose PSF is just a point. Such a system can replicate an object perfectly. An imaging system can have “isotropic” or “non-isotropic” PSF. Isotropic PSF is rotationally symmetric while non-isotropic PSF is not. Figure 7.4 shows the point stimulus and an isotropic and a non-isotropic PSF [1].

5 Although

it is more appropriate to assign resolution to the imaging system, sometimes resolution is assigned to the image.

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Fig. 7.4 Point spread function (a) A point stimulus (b) Isotropic PSF (c) Anisotropic PSF [1] Fig. 7.5 Three different spatial resolutions defined for a 3-D imager

Resolution can be defined as the full-width-at-half-maximum (FWHM) of the PSF. For three-dimensional imagers, it is common to define three different resolutions called “axial”, “lateral “and “elevational”. The axial resolution is defined along the propagation direction of the beam in the far-field and is perpendicular to the two-dimensional image plane. The lateral and elevational resolutions are sometimes referred to as “in-plane” resolutions. Figure 7.5 shows the three spatial resolutions for a general three-dimensional imager. In pulse-based active imagers, the axial resolution is a function of the pulsewidth. As the pulse bandwidth increases, pulse-width decreases and the axial resolution becomes higher. To understand this concept, envision two identical small objects separated by a small axial distance. The received pulses, after scattering back from these two objects are identical in shape and only delayed relative to each other. The amount of delay is proportional to the axial separation of the two objects6 . As the transmitted pulses get narrower in time, the overlap between the received pulses decreases and the imager’s ability to separate the two identical objects increases. This concept is depicted in Fig. 7.6. In [3], a fully integrated pulsebased imager transmitter with pulse widths as low as 35ps is reported. Roughly speaking, in-plane resolutions of most imaging systems are fundamentally limited to their operation wavelengths. This physical limitation is imposed

be more precise, the amount of delay is given by τ = dc , where d is the axial separation of two objects and c is the speed of waves in the medium. 6 To

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Fig. 7.6 Effect of pulse-width on the axial resolution of pulse-based imagers. (Top) The imager can distinguish the scattered waves from two close objects and (bottom) the imager cannot fully distinguish between the two close objects

by the “diffraction limit”7 law [5]. For example, if an imaging system operates at 220 GHz, its in-plane resolution limit is approximately on the order of a millimeter, which is the wavelength of light at 220 GHz. Since wavelength is inversely proportional to frequency, typically imagers with higher operation frequencies exhibit higher spatial resolutions. Another factor that affects the in-plane image resolution is the size of effective aperture or antenna used for the detection. The higher the aperture size, the higher the in-plane resolution [5]. Most imagers include an array of pixels. If the antenna pattern of a group of pixels is directed toward the same direction, their aperture sizes add and as a result, higher resolution in the focus direction can be achieved.

7 Many techniques such as near-filed imaging or super-lenses have been proposed [4] to overcome the diffraction limit. However, this doesn’t change our general discussion.

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7.5.2 Contrast Contrast is the difference between the image intensities at two close regions8 . Higher contrast images are better in distinguishing different objects. Our eyes are sensitive to the contrast. We usually describe low-contrast images as “washed-out”. Figure 7.6 shows the effect of contrast on the appearance of an image. Contrast of an imaging system is highly dependent on the underlying physics of the imaging. In every imaging system, one physical parameter is mapped to the signal intensity level. For example, magnetic resonance imaging (MRI) is known for having a high soft-tissue contrast compared to the X-ray imaging [1]. We will see later that the X-ray imaging maps the attenuation of different tissues to the image intensity. MRI on the other hand, maps the magnetic spin density9 to the image intensity. Since different soft tissues exhibit very close attenuations at the X-ray frequencies, the X-ray imaging cannot provide a very high contrast between two soft tissues. On the other hand, soft tissues typically can have very different magnetic resonance parameters leading to a high contrast in the MR imaging.

7.5.3 Penetration Depth Penetration depth of an electromagnetic wave in a material is a function of the host material’s attenuation at the photon’s wavelength. Depending on the imaging application and frequency of operation, penetration depth of the electromagnetic waves in the materials may need to be taken into account. As an example, X-rays can penetrate a much deeper distance in the biological tissues when compared to the visible range light waves [1]. This is why the X-ray medical imaging systems can are used to image the internal body organs while optical imagers cannot be used for such purpose.

7.6 Passive Imaging Basics Passive imagers typically consist of a radiometer (radiation detector) and their image contrast is based on the difference between the “emissivity”, ε , of different objects. Emissivity is a measure of the amount of energy an object emits from its surface and is a unit-less number between 0 and 1. A perfect radiator or “blackbody” exhibits an emissivity equal to one. A perfect reflector such as a metal exhibits y1) formally, the contrast can be defined as I(x2, y2)−I(x1, where I(x1,y1) and I(x2,y2) are the I(x1, y1) image intensities at two different regions. 9 There are many other contrast sources available in MRI. Spin density is the most basic and the easiest to understand. 8 More

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Table 7.1 Effective emissivity of some objects at different imaging c IEEE) frequencies [2] ( Emissivity Emissivity Emissivity Surface at 44 GHz at 94 GHz at 140 GHz Bare metal 0.01 0.04 0.06 Dry asphalt 0.89 0.91 0.94 Dry concrete 0.86 0.91 0.95 Smooth water 0.47 0.59 0.66 Rough dirt 1.00 1.00 1.00

emssivities close to zero. The amount of emissions from an object at the thermal equilibrium state, is a function of the product of is emissivity, ε , and its absolute temperature, T0 , and is called “surface brightness temperature”, TS , and is given by TS = ε To

(7.2)

Typical numerical values of the emissivity of a few materials at the imaging frequencies are shown in Table 7.1 [2]. In addition to the intrinsic emissivity of the objects in a scene, the way the scene is illuminated plays a significant role in the passive imaging. For example, a perfect metal has emissivity of zero but can act as a mirror and send the emissions from other objects toward the imager. To capture this effect, the product of the object’s reflectivity, ρ , and the radiometric temperature of the illuminations sources, Tilumm , should be added to the surface brightness temperature in (7.2). The result is called the “effective surface brightness”, TSeff , which is given by [2]: TSeff = ε To + ρ Tillum

(7.3)

As suggested by Table 7.1, the amount of inherent emissions from an object depends on the frequency too. As a result, an “emission spectrum” can be defined for any object. A typical emission spectrum is shown in Fig. 7.7 [2]. Almost all objects emit much more power in the infrared range compared to the mm-wave and terahertz range. However, infrared detectors usually exhibit very poor noise characteristics compared to the terahertz and mm-wave detectors [2]. The lower noise of the mmwave and terahertz detectors makes their overall performance comparable with (or even better than) the infrared imagers despite the lower available emitted power. Also mm-wave and THz imagers are less sensitive to the weather conditions compared to the visible or infrared imagers [2]. As can be seen in Fig. 7.7, infrared radiations are almost completely blocked by the fog.

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Fig. 7.7 Three images of one scene with different contrasts. Image on the right has the most and image on the left has the least contrast

7.7 Imaging Arrays Imagers are typically formed by several pixels (i.e. detectors and receivers) in an array configuration. The signals picked up by these pixels are then combined to form an image. Imaging arrays can be divided into two main classes: (a) the “focal plane arrays” (b) the “scanning arrays”. In focal plan arrays, a two-dimensional (2-D) array of detectors is located at the focal plane of a lens and the desired field-of-view is imaged in a single shot. Different detectors capture different parts of the field of view in a focal plan array. Focal plane imaging arrays are more common in the infrared frequency band. However, they can be applied to other frequency bands. In chapter 1, an example of a focal plane imaging array working at 600 GHz was presented. In the scanning arrays, image of the field of view is taken line by line. The main beam of the antenna array is steered either mechanically or electronically. Scanning arrays typically need fewer number of pixels compared to the focal plane arrays. This benefit is at the expense of having a higher image acquisition delay. Similar to the radio receivers, imagers can also benefit from the multiple-antenna techniques. Examples of such multiple antenna techniques are the beamforming and the spatial multiplexing. Depending on the communication channel, link budget and the data throughput, using one of these multiple-antenna techniques is more advantageous. For example, when the channel has a strong and dominant lineof-sight mode, beamforming works the best. Whereas, for the highly scattering channels with weak line-of-sight modes, the spatial multiplexing works better. In the beamforming receiver arrays, the signals received by the different pixels are assumed to be the delayed replicas of each other. This assumption is only accurate for the channels with low to moderate multiple scattering. When there

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is sever multiple scattering, the signals received from different pixels become highly uncorrelated. Beamforming arrays can improve the signal to noise ratio (SNR). One intuitive explanation to such SNR improvement is that the signals received by different pixels are highly correlated, while the noises are uncorrelated. The SNR of the combined signals is therefore higher than the individual signals. As mentioned earlier, arrays also increase the in-plane spatial resolution of the imager by increasing the effective antenna aperture.

7.8 Medical Imaging As mentioned previously, optical imaging of the biological samples is limited to shallow tissues due to the very high attenuation of waves in the biological tissues at the optical frequency range. The electromagnetic spectrum outside the visible range is widely used for deeper medical imaging. Examples are in the X-rays (including mammography and computed tomography), magnetic resonance imaging (MRI), and nuclear medicine. This section is designed to give a reader with no medical imaging background, a very brief review of the X-ray, MRI, and nuclear imaging. The recently emerged medical imaging at the mm-wave and terahertz frequencies will then be discussed in Sect. 7.10. Different imaging modalities have different strengths and weaknesses. For example, there is a well-known, universal tradeoff between the penetration depth and the resolution of different imaging modalities. Figure 7.8 shows this tradeoff for a number of imaging modalities. In this figure, the resolution and penetration depth of the following medical imaging modalities have been shown: (1) non-optical modalities including MRI, CT and ultrasound (2) optical modalities including: optical coherence tomography (OCT), and confocal microscopy.

7.8.1 X-ray Imaging As described before, a photon beam experiences some attenuation as it travels through a piece of material. The amount of attenuation is mainly a function of three parameters: (1) the wavelength of the photon (2) the atomic structure of the material (3) the thickness of the material [1]. For a given material, a parameter called the “mass attenuation coefficient”, μ , is defined at every photon wavelength.10 The attenuation, A, of a photon beam due to travelling in a piece of material with mass attenuation coefficient μ is given by A = eμ x ,

(7.4)

in which x is the travel distance.

10 It is common to define mass attenuation coefficient of materials at different photon energy levels. Photon energy level, E, and wavelength, λ , are connected though E = hc λ where h is Planck constant and c is the speed of light.

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c IEEE 2003) Fig. 7.8 Typical emissivity spectrum of ground and space objects [2] ( Table 7.2 Mass attenuation coefficient of a few materials at the 50-keV photon [1]

Material Hydrogen Fat Water Compact bone

μ @ 50 Kev (cm−1 ) 0.00028 0.193 0.214 0.573

Table 7.2 shows the mass attenuation coefficients of some materials at a typical X-ray photon energy level of 50 KeV [1]. X-ray imagers have a transmitter (called the X-ray tube) which emits an X-ray beam toward the objects. The beam then travels through the objects and exits from the other side. The attenuation of the photon beam compared the original photon beam is measured at the other side of the object by means of an X-ray detector [1]. X-ray imaging is therefore an active imaging system according to our classification in Sect. 7.2. The diffraction limit law predicts a maximum resolution on the nanometer range for the X-ray systems. Practical medical X-ray systems however, cannot achieve resolutions better than a few hundred microns. This means that the X-ray medical imaging systems are not diffraction-limited. One major restriction to using the X-ray for in vivo imaging is the “ionizing” nature of the X-rays. In simple terms, this means that the X-ray photons have enough energy to detach the electrons from their host atoms and consequently ionize the atoms. Excessive exposure to ionization radiation increases the chances of cancer and other chronic diseases [1]. In the United States there are strict legal regulations that limit the total amount of X-ray dose, a human can be exposed to. Figure 7.9 shows an X-ray image of a human body. As described before, the attenuation is mapped to the gray-scale image intensity. Lighter areas in the

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Fig. 7.9 Tradeoff between resolution and penetration depth for several imaging modalities: (1) MRI (2) CT (3) ultrasound (4) conventional OCT, (5) ultra-high resolution OCT 6) confocal microscopy

image correspond to more attenuation. For example, bones exhibit relatively high attenuation at X-ray (refer to Table 7.2), therefore they appear relatively lighter in the image. A single X-ray image provides one projection of the object through a single line. Computed Tomography (CT) is an extension to this single projection and can be thought as the 3-D version of the X-ray. The mathematics of CT was first introduced by Radon in 1917. Radon proved that a complete image of an unknown object can be reproduced if one had infinite number of projections through the object. This theorem is the main idea behind “tomographic11 imaging”. Computed tomography starts with of a series of X-ray projections of the object taken from different angles. After these projections are taken, the image of the unknown object is reconstructed through an algorithm called the “backprojection” [1]. Figure 7.10 shows a CT image of a human head. For in-depth understanding of X-ray and CT imaging reader is referred to [1]

7.8.2 Magnetic Resonance Imaging Magnetic Resonance (MR) imaging is a powerful and noninvasive imaging modality with no ionizing hazard. The most common applications for MR imaging includes studies of the central nervous system (CNS) and musculoskeletal (MSK) system. Besides its huge clinical significance, MR imaging is a very active field of research.

11 The

word tomography consists of –tomo (slice) and –graphy (image).

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Fig. 7.10 X-ray image of human body

New techniques and applications for the MR are introduced every day. One of the unique advantages of the MR imaging is the extreme flexibility. MR offers a wide range of physical parameters to image and many control knobs to tailor the image to a specific application. Also MR imaging can be done in almost any desired cross section of an object. In depth understanding of how MR imaging works requires a whole book. Nevertheless it is instructive to have a very basic understanding of the MR operation. MR imaging is based on the “nuclear magnetic resonance” (NMR) phenomenon, briefly explained in the following paragraphs. Atoms with odd number of protons (and/or odd number of neutrons) possess magnetic angular momentum.12 Magnetic angular momentum is also referred to as “nuclear spins” (or simply spins). In the biological samples, hydrogen atom is the most abundant and by far the most frequently used atom spin for MR. The MR imaging is based on the interaction of spins with external applied magnetic fields. There are three different magnetic fields involved in the MR imaging: (1) a huge, constant magnetic field, B0 , produced by a magnet in the MR scanner (2) a radiofrequency (RF) magnetic field, B1 , produced by the RF coils (3) the linear gradient fields, G, produced by the gradient coils. We will explain the interactions of these three fields with the spins in the following paragraphs.

12 One

intuitive description of angular magnetic moment is a charge which is spinning.

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In the absence of an external magnetic field, the spins of most atoms are dispersed randomly and hence their net macroscopic magnetic moment is zero. When an external magnetic field, B0 , is applied, two interesting phenomena occur: (1) the spins lean to align themselves to the external magnetic field and produce a net magnetization (2) the spins exhibit a so-called “resonance”13 by rotating around the axis of the main field at an angular frequency called the “Larmor frequency”. This angular frequency, ω , is proportional to the applied magnetic field and is given by the following equation:

ω = γ B0

(7.5)

In (7.5), γ is the “gyromagnetic ratio” of the atom. A classical, numerical example is for the hydrogen atoms in an external magnetic field with the strength of 1Tesla. In this case the angular frequency of the spins is roughly 42.6 MHz. We can conclude that the gyromagnetic ratio of hydrogen is around 42.6 MHz/T. If the frequency of a RF, magnetic field, B1 , is tuned to the Larmor frequency of the spins, it can “excite” the spins “on-resonance”. One intuitive explanation is that B1 acts similar to a torque that rotates the spins by a an angel determined by the strength and duration of B1 . After the RF pulse is turned off, spins have a tendency to go back to their equilibrium state (i.e. rotating around the main field at the Larmor frequency). Before the spins completely return to their equilibrium, they induce an electromotive force (EMF) by the Faraday’s induction law in a receiving coil that records the MR signal. The generated signal is called the “free induction decay” (FID). MR imaging includes recording of an array of FID signals and then reconstructing the image based on a mapping between the recorded FID signals and the spins of the object under study. An object can be thought as a collection of thousands of tiny oscillators inducing RF signals. The purpose of the MR imaging is then to establish a mapping between the FID signals and the spatial distribution of the tiny oscillators [6]. A very central part of the MR imaging is the “spatial localization”. The FID signals received at the receiving coils are the net superposition of many tiny oscillators in the excited region. In order to construct an image, it is important to determine the contribution of different parts of the region in the overall recorded FID signal. In the MR imaging, the spatial localization is achieved by applying the linear gradient fields in addition to the main field. To get an intuitive idea of how this works, consider the following example. Imagine the main magnetic field is applied in the z direction in the x-y-z Cartesian space. If a small linear x-gradient field Gx is applied in addition to the main field, the total magnetic fields of different points in the space become slightly different depending on their position as given by: B(x, y, z) = z∧ [B0 + xGx ]

13 This

is why this imaging modality is called magnetic resonance.

(7.6)

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As a result, the angular frequency of spins at different locations becomes a function of the spin position as given by:

ω (x, y, x) = γ (B0 + xGx )

(7.7)

Different spins therefore contribute to the overall FID at different frequencies and are separable by means of a Fourier decomposition of the FID signal. In other terms, there is a linear mapping between the frequency components of the FID and the position of the source spin. The diffraction limit law predicts a maximum resolution on the order of a few tens of centimeters for MR imaging. MR imaging however, can achieve spatial resolutions on the order of a few millimeters! This apparent contradiction can be explained through the spatial localization. The RF field consists of a superposition of many closely- spaced tiny sources. Despite the coarse wavelength of the RF wave, location of these tiny sources can be resolved because their spatial positions are encoded by their frequencies. This is while in the derivations of the diffraction limit law, no spatial localization is assumed. A MR image of a human brain is shown in Fig. 7.11. It is useful to compare Figs. 7.10 and 7.11. Unlike CT, MR can differentiate between the fine soft tissue structures of the brain. This soft tissue contrast is a huge advantage for the MR imaging. One of the main disadvantages of MR imaging is the relatively long acquisition time. We only touched upon some basic concepts in the MR imaging in this section. Interested readers are encouraged to refer to [1] and [6] for more information. Recently, there has been an interest in scaling down the physical dimensions of the MR imaging systems for point-of-care diagnosis. Such scaling imposes several challenges to the design of the MR imaging hardware. In particular scaling the magnet and the associated electronic transceiver is challenging. The main challenge with smaller magnets is that their magnetic field is not uniform. As a result, the spatial localization that ideally should be a linear mapping between the resonance frequency of dipoles and their spatial locations becomes a nonlinear, coordinate-dependent mapping. This problem can be overcome by using sophisticated electronic transceivers and robust communication schemes. In [7] the capabilities of integrated circuits are exploited to demonstrate a CMOS transceiver designed for a small MR system. The block diagram of the system is depicted in Fig. 7.12. The scanner designed in [7] is based on the “Spectral Scanning MRI” (SSMRI) method. SSMRI method is capable of working in inhomogeneous magnetic fields. Readers are referred to [7] for more details.

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Fig. 7.11 Head CT image

Fig. 7.12 MR image of a human brain

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c IEEE 2009) Fig. 7.13 Scaled down Spectral Scanning MRI (SSMRI) transceiver in [7] (

7.8.3 Nuclear Imaging Nuclear imaging belongs to the category of “functional imaging”. Functional imaging provides information about the physiological state of the body organs in addition to anatomical information. A radioactive isotope is given to the patient in nuclear imaging. After the isotope distributes in the patient’s body, it starts emitting X-rays and gamma-rays. Then a detector senses the emissions of the isotope after they pass through the body. For example, thallium tends to concentrate in the healthy heart tissues, but does not concentrate in infracted or ischemic areas of the heart. Thallium is therefore used for the functional imaging of heart. Similar to X-ray and CT, nuclear imaging can be either line projections or tomographic. The tomographic version of the nuclear imaging is called “Single Photon Emission Computed Tomography” (SPECT). In SPECT, a gamma camera collects the emissions from the patient’s body at many different angles. Figure 7.13 shows a myocardial stress test utilizing thallium.

7.9 Emerging New Medical Imaging Applications New medical imaging techniques are introduced on regular basis. These new techniques usually fall into one of the two main categories: 1. Imaging applications that combine two previously-existing modalities to take advantage of the strengths of both modalities. Many possible combinations can be imagined. For example, MR and OCT are combined in [8].

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2. Imaging applications that exploit unexplored frequency bands and novel physical phenomena to provide cheap and portable medical imagers for both soldiers and civilians. In battlegrounds such imagers can prove very useful for fast assessment of the soldier’s wounds and burns. For civilians they can prove useful in the early detection of cancer or for monitoring chronic conditions like diabetes. One example in this category is the terahertz medical imaging. Today’s fast CMOS devices are potentially suitable for implementation of some of these imaging applications. One can exploit the unprecedented speed, low manufacturing cost and high computational capabilities of the CMOS to make cheap and portable imagers in high production volumes. Several new directions have been opened recently in the medical imaging field. The topic that we cover here is the sub-millimeter wave and terahertz (T-ray) imaging for medical applications. This direction has been selected due to its extremely high potential and feasibility of implementation in the high speed CMOS. T-ray covers the electromagnetic spectrum from 100 GHz to around 10 THz. Medical applications of the electromagnetic waves below 100 GHz (e.g. microwave) and above 10 THz (e.g. infrared, or X-ray) have been far more investigated than in the 100 GHz–10 THz range. Traditionally, this has been due to the lack of affordable, efficient and practical sources and detectors at terahertz frequencies. The absence of practical, solid-state sources and detectors in the THz/mm-wave frequency range is why this frequency band is sometimes referred to as “THz gap” [9]. This gap is surrounded by the electronic devices domain covering from DC to around 100 GHz and the photonics device domain working above 10 THz. Electronic devices such as transistors are limited by the transit time and parasitic RC delays. As a result, these devices have a low-pass nature and their output power drops as frequency increases. Currently, the highest frequency at which most of these devices can operate is less than a terahertz. On the other hand, conventional photonic devices such as bipolar laser diodes have a high-pass nature because their minimum photon energy should be higher than a certain level (e.g. the band gap). Typical operation frequencies are higher than 10 THz. As a result, the terahertz range is not reachable by typical electronic or photonic devices. This concept is depicted in Fig. 7.14. Recent advances in the solid-state technology have narrowed the terahertz gap from electronics end and from the photonics end. From the photonics end, the evolution of new devices such as the terahertz, quantum, cascade lasers [10] and the terahertz metamaterials [11] have pushed the photonics domain to the terahertz range. From the electronics side even the digital CMOS technology has started to be operable in the terahertz range. Along with applications in remote sensing and security monitoring, the possible medical applications of the terahertz waves are being explored by the researchers. Theoretically speaking, T-rays can offer unique imaging capabilities. Their penetration depth in the biological tissues is much higher than that of the infrared waves and their spatial resolution is much finer than that of the microwaves. Also, they do not have the undesired ionizing effects of X-rays. Some other unique characteristics of

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Fig. 7.14 A nuclear functional image of the heart using Thallium. Areas of low blood flow contain less diffused Thallium and appear as cold spots.

Electronics domain

Photonics domain THz gap

Fig. 7.15 THz gap is accessible neither by electronics nor by photonics devices

the T-rays have been demonstrated in practice. For example, T-rays have shown to have a very high sensitivity to the amount of water (H2 O) in a tissue [12]. This is due to two reasons (1) the attenuation of electromagnetic waves in H2 O is very high at the mm-wave/THz band (2) H2O has a very high dielectric constant at terahertz [12]. In the medical fields, T-rays have been investigated for dermatology applications [12] and DNA detection [13]. In dermatology, the high sensitivity of T-rays to water concentration has been exploited to measure the skin burn levels for assessing the wounds and detecting the skin cancer [12]. Authors of [12] have reported the terahertz skin burn assessment which is depicted in Fig. 7.15. As can be seen in this figure, the burned skin appears darker in the images due to its lower water concentration and hence lower reflection coefficient at terahertz. Terahertz can also penetrate clothing and textile. For example in the same Fig. 7.15, burned skin is still detectable under layers of gauze.

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Fig. 7.16 THz used for skin imaging in [12]. Lighter areas means more reflection. (a) Normal skin. (b) Burned skin. (c) Burned skin under 5 layers of gauze. (d) Burned skin under 10 layers of c OSA 2008) gauze (

In the DNA detection, T-rays have been used as a means of label-free probing of the binding state of the DNA [13]. Advances in the THz sources and detectors contributed to making the terahertz frequency band reachable. There are two main groups of terahertz sources: (1) electronics-based sources (2) photonics-based sources. Currently the electronicsbased terahertz sources are mostly the traditional MMICs based on backward wave oscillators, Gunn diodes and super lattice devices. The electronic sources cover only the lower range of the mm-wave/ THz frequencies from 100 GHz to 0.5 THz and their output power is relatively limited. Photonics devices cover the upper end of the terahertz range from 1 THz to 10 THz. Figure 7.16 depicts the output power level of typical solid-state electronic and photonic devices as a function of frequency [15]. Owing to the non-stopping scaling of the CMOS technology, the silicon-based terahertz sources have become a reality. Unfortunately however, none of the terahertz signal-sources which have been demonstrated in the CMOS technology has enough output power-level for the medical applications yet. At the time of writing

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c IEEE 2008) Fig. 7.17 Photonics and electronics sources at THz [14] (

this manuscript, a 300 GHz CMOS with power generator/radiator with EIRP14 = −1 dBm has the highest achieved radiated power by CMOS at the terahertz band [16]. Currently, photonics-based terahertz sources such as the terahertz, quantum cascade laser (QCL) are still dominant in the medical applications due to their higher power levels. QCL working at terahertz needs to be cooled down to temperatures much less than the room temperature. This cooling requirement is the major disadvantage of QCL. There are many technical issues that should be addressed in order for medical THz technology to make the transition from the academia to the industry. Two of these technical issues are the low resolution and the low acquisition speed of the terahertz imaging as described below [9]. If conventional imaging techniques are used, the diffraction limit for the mmwave/THz is roughly on the order of 3 μm to 3 mm. Such resolution may not be adequate for some applications. A remedy to this issue is using the techniques that can reach beyond the diffraction limit. For example, the near-field imaging and metamaterials super lenses [17] can be used. One problem with the near-filed imaging is that it limits the imager-to-object-distance to less than a wavelength (3 μm to 3 mm in this case). Such small distances can be restrictive especially for in vivo imaging. THz sources are currently expensive. This usually means only one source is available and should be scanned mechanically to image the whole field of view. As a result, the scanning times are usually very long. This problem can be mitigated if more affordable solid-state sources are in an array configuration with electronic beamsteering. 14 EIRP stands for Effective Isotropic Radiated Power, captures both the output power and directivity of the antenna.

References

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Before finishing this chapter, it is worthwhile to refer to the interesting research on the CMOS–compatible photonic devices [18]. Silicon has interesting optical properties, which make it suitable as a host medium for building devices that can guide, route, direct and manipulate the light. On the other hand, due to the huge commercial momentum of the CMOS technology, CMOS-compatibility is a great advantage for new device technologies. CMOS-compatible photonics integration is an effort to fabricate the photonics components and CMOS circuits on the same die. CMOS-compatible photonic devices are more compact and exhibit higher performance. Also, CMOS-compatible integration reduces the fabrication cost for high-volume production. An interesting example of photonic integrated devices working in the terahertz regime can be found in [19].

7.10 Chapter Summary and Conclusions Imaging is a promising application for the ultra-high speed CMOS technology. Due to the interdisciplinary nature of the imaging, it is instructive for to have a basic understating of the imaging terminology and concepts. This chapter was written with this goal in mind. Sections 7.1–7.9 were designed to provide a reader with a basic understanding of the imaging physics. Section 7.10 introduced the terahertz medical imaging, as a new topic which has recently been opened in the medical imaging field. As we saw in Sect. 7.10, due to the inaccessibility of the terahertz band by the electronics or photonics devices, this frequency band used to be a gap. Recent advances in the electronic and photonic devices have made this band to be reachable. As we saw in Sect. 7.10, terahertz band offers unique features for medical imaging. As an example, the sensitivity of THz electromagnetic waves to the water concentration in a tissue offers an opportunity for dermatology and cancer detection applications [20].

References 1. Bushberg JT (2001) The essential physics of medical imaging 2. Yujiri L, Shoucri M, Moffa P (2003) Passive millimeter wave imaging. IEEE Microw Mag 4(3):39–50 3. Arbabian A, Afshar B, Chien J-C, Kang S, Callender S, Adabi E, Dal Toso S, Pilard R, Gloria D, Niknejad AM (2010) “A 90 GHz-Carrier 30 GHz-Bandwidth Hybrid Switching Transmitter with Integrated Antenna,” IEEE International Solid-State Circuits Conference (ISSCC). 4. Zhang X, Liu Z (2008) Nature Mater 7:435 [CAS] 5. Born M, Wolf E (1997) Principles of optics. Cambridge University Press, Cambridge. ISBN 0521639212 6. Nishimura DG (2010) Principles of magnetic resonance imaging 7. Hassibi A, Babakhani A, Hajimiri A (2009) A spectral-scanning nuclear magnetic resonance imaging (MRI) transceiver. IEEE J Solid State Circ 44(6):1805–1813. doi: 10.1109/JSSC.2009.2020456

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8. Gulsen G, Birgul O, Unlu M, Shafiiha R, Nalcioglu O (2006) Combined diffuse optical tomography (DOT) and MRI system for cancer imaging in small animals. Technol Canc Res Treat 5(4):351–363 9. Humphreys K, Loughran JP, Gradziel M, Lanigan W, Ward T, Murphy JA, O’Sullivan C (2004) Medical applications of terahertz imaging: a review of current technology and potential applications in biomedical engineering, Engineering in Medicine and Biology Society, 2004. IEMBS ‘04. 26th Annual International Conference of the IEEE, vol.1, pp.1302–1305, 1–5 Sept. 2004 10. Kohler R et al. (2002) Terahertz semiconductor-heterostructure laser. Nature 417:156–159 11. Ferguson B, Zhang X-C (2002) Materials for terahertz science and technology. Nat Mater 1(1):26–33 12. Taylor ZD, Singh RS, Culjat MO, Suen JY, Grundfest WS, Lee H, Brown ER (2008) Reflective terahertz imaging of porcine skin burns. Optics Lett 33(11):1258–60 13. Nagel M, Haring Bolivar P, Brucherseifer M, Kurz H (2002) Integrated THz technology for label-free genetic diagnostics. Appl Phys Lett 80:154–156 14. Huang D, LaRocca TR, Chang M-CF, Samoska L, Fung A, Campbell RL, Andrews M (2008) Terahertz CMOS frequency generator using linear superposition technique. IEEE J Solid State Circ 43(12):2730–2738 15. Tonouchi M (2007) Cutting-edge Terahertz technology. Nat Photon 1:97–105 16. Sengupta K, Hajimiri A (2011) “Distributed active radiation for THz signal generation” to appear in the IEEE International Solid-State Circuits Conference (ISSCC) 17. Zhang X, Liu Z (2008) Nat Mater 7:435 [CAS]. 18. Izhaky N, Morse MT, Koehl S, Cohen O, Rubin D, Barkai A, Sarid G, Cohen R, Paniccia MJ (2006) Development of CMOS-compatible integrated silicon photonics devices. IEEE J Sel Top Quant Electron 12(6):1688–1698 19. H¨ubers H-W (2010) Terahertz technology: Towards THz integrated photonics. Nat Photon 4:503–504 20. Hashemi H, Krishnaswamy H (2009) Challenges and opportunities in ultra wideband antenna array transceivers for imaging, IEEE International Conference on Ultra Wideband, Vancouver, Canada, September 2009

Index

A Absorption, 72, 80, 82 Attenuation, 72, 82–83, 86, 89–91, 98 Axial, lateral, elevational resolutions, 84

B Band gap, 61, 97 Bit error rate (BER), 74, 75 Blackbody radiation, 80, 86

C Capacitance, 12, 13, 19, 27, 32, 33, 39, 48, 53, 59 Cascode, 5, 7, 17–20, 40, 41, 53–55 CMOS, 1, 2, 4, 9, 23, 29, 32, 35–44, 50, 51, 57–76, 79, 94, 97, 99–101 Common-gate, 7, 50, 51, 53, 64 Common-source, 6, 7, 9, 17, 20, 24, 40, 43, 44, 47, 48, 50, 64 Computed tomography, 89, 91, 96 Concealed weapon detection, 79 Confocal microscopy, 89, 91 Constant current densities, 63 Constant-envelop, 75 Contrast, 83, 86, 88, 94 Cross-coupled, 64, 68

D Decoupling capacitors, 64 Directive, line of sight (DLOS) communication, 72 Directive, non-line of sight (DNLOS), 72 Diversity, 73

E Effective isotropic radiated power (EIRP), 100 Effective surface brightness, 87 Emerging research material (ERM), 58 Emission spectrum, 87 Emissivity, 86, 87, 90 EM simulation, 10, 27, 64 ERM. See Emerging research material Extraction, 5, 6, 76

F f max , 23–27, 29, 31, 32, 63, 64 Focal plane, 69, 70, 88 Free induction decay (FID), 93, 94 Frequency dividers, 70–71 Full-width-at-half-maximum (FWHM), 84 Functional imaging, 96 Fundamental oscillation, 65, 68

G Gallium-Arsenide (Ga-As), 58 Geometric scaling, 57, 61 Germanium (Ge), 58 Graphene, 1, 57–61

I III-V, 1, 57, 58, 60 Imaging applications, 79–101 Imaging passive/active–imaging optical vs. non-optical, 62, 69, 80, 81, 86–87 Inductance, 48, 51, 53–55 Information beam-width, 74, 75 In-plane resolutions, 84

S. Gharavi and B. Heydari, Ultra High-Speed CMOS Circuits: Beyond 100 GHz, DOI 10.1007/978-1-4614-0305-0, © Springer Science+Business Media, LLC 2011

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Interaction of a photon with a material, 79 International Roadmap for Semiconductor (ITRS), 58 Inverse scattering, 80 Isotropic/non-isotropic PSF, 83, 84

L Large-signal model, 10–11 Larmor frequency, 93 Linear superposition, 65–67 Local oscillator (LO), 65, 69 Locking ranges, 70 Low-noise amplifier (LNA), 63

M MAG, 26 Magnetic resonance imaging (MRI), 86, 89, 91–96 Mammography, 89 Mason’s unilateral gain, 27, 52 Mass attenuation coefficient, 89, 90 Metal-on-metal (MoM) capacitors, 54, 64 Minimum noise figure, 23, 42, 55, 63 Modeling, 4–20, 35, 36, 54, 55, 61, 64, 72, 76 MRI. See Magnetic resonance imaging

N Near-field, direct, antenna modulation (NFDAM), 3, 71, 74–76 Noise parameters, 35 Nuclear magnetic resonance (NMR), 92 Nuclear spins, 92

O Optical coherence tomography (OCT), 89, 91, 96

P PA. See Power amplifier Parasitic, 6, 9, 24, 26, 27, 29, 32, 41, 42, 48, 63, 76, 97 Penetration depth, 86, 89, 91, 97 Phased array, 62, 75, 76 Point spread function (PSF), 83, 84 Power amplifier (PA), 10, 24, 32, 63, 71, 75 Primary photon, 79, 80 Propagation windows, 83 PSF. See Point spread function

Index R Ray-tracing, 72 Remote sensing, 79, 97 Responsivity, 81

S Scaling law, 58, 59 Scanning arrays, 88 Scattering, 72, 73, 80, 82, 84, 88, 89 Schottky diodes, 67 Secondary photon, 80 Self-aligned, 58, 59, 76 Self-mixing, 69 Short-channel effects, 58 Single photon emission computed tomography (SPECT), 96 Spatial localization, 93, 94 Spatial multiplexing, 73, 74, 88 Spatial resolution, 62, 83–85, 89, 94, 97 Spectral scanning magnetic resonance imaging (SSMRI), 94, 96 Substrate, 6, 9, 10, 12, 20, 28, 30, 41, 42, 54 Substrate loss, 24, 26, 29 Substrate network, 6, 9, 10, 20, 41, 42, 54 Substrate resistivity, 9, 41, 42 Surface brightness temperature, 87

T Terahertz (THz), 1–4, 57–76, 79, 81, 87, 89, 97–101 Thz gap, 2, 97, 98 Tomographic imaging, 91, 96 Transistor layout, 8, 27, 63 Transistors, 1, 5, 7–9, 19, 23, 31, 37, 45, 58, 59, 61, 63, 64, 97 Transmission line, 7, 8, 11, 12, 14–16, 27, 33, 53, 64, 69

U Unilateral, 45, 47–49, 52, 53, 56 Unilateral gain, 23, 27 Unilateralization, 3, 4, 25, 45–56

W W-band, 68

X X-ray imaging, 86, 89–91