Fabrication of SiGe HBT BiCMOS technology

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Cressler/Fabrication of SiGe HBT BiCMOS Technology

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Fabrication of SiGe HBT BiCMOS Technology

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Fabrication of SiGe HBT BiCMOS Technology

Edited by

John D. Cressler

Boca Raton London New York

CRC Press is an imprint of the Taylor & Francis Group, an informa business

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The material was previously published in Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits and Applications of SiGe and Si Strained-Layer Epitaxy © Taylor and Francis 2005.

CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 © 2008 by Taylor & Francis Group, LLC CRC Press is an imprint of Taylor & Francis Group, an Informa business No claim to original U.S. Government works Printed in the United States of America on acid-free paper 10 9 8 7 6 5 4 3 2 1 International Standard Book Number-13: 978-1-4200-6687-6 (Hardcover) This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish reliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use. Except as permitted under U.S. Copyright Law, no part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microfilming, and recording, or in any information storage or retrieval system, without written permission from the publishers. For permission to photocopy or use material electronically from this work, please access www.copyright.com (http:// www.copyright.com/) or contact the Copyright Clearance Center, Inc. (CCC) 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400. CCC is a not-for-profit organization that provides licenses and registration for a variety of users. For organizations that have been granted a photocopy license by the CCC, a separate system of payment has been arranged. Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation without intent to infringe. Library of Congress Cataloging-in-Publication Data Fabrication of SiGe HBT BiCMOS technology / editor, John D. Cressler. p. cm. Includes bibliographical references and index. ISBN 978-1-4200-6687-6 (alk. paper) 1. Bipolar transistors--Design and construction. 2. Metal oxide semiconductors, Complementary--Design and construction. I. Cressler, John D. TK7871.96.B55F33 2008 621.3815’28--dc22 Visit the Taylor & Francis Web site at http://www.taylorandfrancis.com and the CRC Press Web site at http://www.crcpress.com

2007030735

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For the tireless efforts Of the many dedicated scientists and engineers Who helped create this field and make it a success. I tip my hat, and offer sincere thanks from all of us Who have benefitted from your keen insights and imaginings. And . . . For Maria: My beautiful wife, best friend, and soul mate for these 25 years. For Matthew John, Christina Elizabeth, and Joanna Marie: God’s awesome creations, and our precious gifts. May your journey of discovery never end.

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He Whose Heart Has Been Set On The Love Of Learning And True Wisdom And Has Exercised This Part of Himself, That Man Must Without Fail Have Thoughts That Are Immortal And Divine, If He Lay Hold On Truth. Plato ¯Œ ı Ø Ø łı ı `ª ªØÆ Ł ŒÆØ `º ŁØ Æ, ŒÆØ Ø `Œ Ł ªØÆ , ‚Æ Ø ¢ æÆ æ ø ºº Æ ŒØ ŒłØ `ŁÆ ŒÆØ ¨, ¯ æØŁ `ºŁØÆ. Pl atvna§

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Foreword

Progress in a given field of technology is both desired and expected to follow a stable and predictable long-term trajectory. Semilog plots of technology trends spanning decades in time and orders of magnitude in value abound. Perhaps the most famous exemplar of such a technology trajectory is the trend line associated with Moore’s law, where technology density has doubled every 12 to 18 months for several decades. One must not, however, be lulled into extrapolating such predictability to other aspects of semiconductor technology, such as device performance, or even to the long-term prospects for the continuance of device density scaling itself. New physical phenomena assert themselves as one approaches the limits of a physical system, as when device layers approach atomic dimensions, and thus, no extrapolation goes on indefinitely. Technology density and performance trends, though individually constant over many years, are the result of an enormously complex interaction between a series of decisions made as to the layout of a given device, the physics behind its operation, manufacturability considerations, and its extensibility into the future. This complexity poses a fundamental challenge to the device physics and engineering community, which must delve as far forward into the future as possible to understand when physical law precludes further progress down a given technology path. The early identification of such impending technological discontinuities, thus providing time to ameliorate their consequences, is in fact vital to the health of the semiconductor industry. Recently disrupted trends in CMOS microprocessor performance, where the ‘‘value’’ of processor-operating frequency was suddenly subordinated to that of integration, demonstrate the challenges remaining in accurately assessing the behavior of future technologies. However, current challenges faced in scaling deep submicron CMOS technology are far from unique in the history of semiconductors. Bipolar junction transistor (BJT) technology, dominant in high-end computing applications during the mid-1980s, was being aggressively scaled to provide the requisite performance for future systems. By the virtue of bipolar transistors being vertical devices rather than lateral (as CMOS is), the length scale of bipolar transistors is set by the ability to control layer thicknesses rather than lateral dimensions. This allowed the definition of critical device dimensions, such as base width, to values far below the limits of optical lithography of the day. Although great strides in device performance had been made by 1985, with unity gain cutoff frequencies (fT ) in the range 20–30 GHz seemingly feasible, device scaling was approaching limits at which new physical phenomena became significant. Highly scaled silicon BJTs, having base widths below 1000 A˚, demonstrated inordinately high reverse junction leakage. This was due to the onset of band-to-band tunneling between heavily doped emitter and base regions, rendering such devices unreliable. This and other observations presaged one of the seminal technology discontinuities of the past decade, silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) technology being the direct consequence. Begun as a program to develop bipolar technology with performance capabilities well beyond those possible via the continued scaling of conventional Si BJTs, SiGe HBT technology has found a wealth of applications beyond the realm of computing. A revolution in bipolar fabrication methodology, moving vii

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Foreword

from device definition by implantation to device deposition and definition by epitaxy, accompanied by the exploitation of bandgap tailoring, took silicon-based bipolar transistor performance to levels never anticipated. It is now common to find SiGe HBTs with performance figures in excess of 300 GHz for both fT and fmax , and circuits operable at frequencies in excess of 100 GHz. A key observation is that none of this progress occurred in a vacuum, other than perhaps in the field of materials deposition. The creation of a generation of transistor technology having tenfold improved performance would of itself have produced far less ultimate value in the absence of an adequate ecosystem to enable its effective creation and utilization. This text is meant to describe the eco-system that developed around SiGe technology as context for the extraordinary achievement its commercial rollout represented. Early SiGe materials, of excellent quality in the context of fundamental physical studies, proved near useless in later device endeavors, forcing dramatic improvements in layer control and quality to then enable further development. Rapid device progress that followed drove silicon-based technology (recall that SiGe technology is still a silicon-based derivative) to unanticipated performance levels, demanding the development of new characterization and device modeling techniques. As materials work was further proven SiGe applications expanded to leverage newly available structural and chemical control. Devices employing ever more sophisticated extensions of SiGe HBT bandgap tailoring have emerged, utilizing band offsets and the tailoring thereof to create SiGe-based HEMTs, tunneling devices, mobilityenhanced CMOS, optical detectors, and more to come. Progress in these diverse areas of device design is timely, as I have already noted the now asymptotic nature of performance gains to be had from continued classical device scaling, leading to a new industry focus on innovation rather than pure scaling. Devices now emerging in SiGe are not only to be valued for their performance, but rather their variety of functionality, where, for example, optically active components open up the prospect of the seamless integration of broadband communication functionality at the chip level. Access to high-performance SiGe technology has spurred a rich diversity of exploratory and commercial circuit applications, many elaborated in this text. Communications applications have been most significantly impacted from a commercial perspective, leveraging the ability of SiGe technologies to produce extremely high-performance circuits while using back level, and thus far less costly, fabricators than alternative materials such as InP, GaAs, or in some instances advanced CMOS. These achievements did not occur without tremendous effort on the part of many workers in the field, and the chapters in this volume represent examples of such contributions. In its transition from scientific curiosity to pervasive technology, SiGe-based device work has matured greatly, and I hope you find this text illuminating as to the path that maturation followed.

Bernard S. Meyerson IBM Systems and Technology Group

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Preface

While the idea of cleverly using silicon–germanium (SiGe) and silicon (Si) strained-layer epitaxy to practice bandgap engineering of semiconductor devices in the highly manufacturable Si material system is an old one, only in the past decade has this concept become a practical reality. The final success of creating novel Si heterostructure transistors with performance far superior to their Si-only homojunction cousins, while maintaining strict compatibility with the massive economy-of-scale of conventional Si integrated circuit manufacturing, proved challenging and represents the sustained efforts of literally thousands of physicists, electrical engineers, material scientists, chemists, and technicians across the world. In the electronics domain, the fruit of that global effort is SiGe heterojunction bipolar transistor (SiGe HBT) BiCMOS technology, and strained Si/SiGe CMOS technology, both of which are at present in commercial manufacturing worldwide and are rapidly finding a number of important circuit and system applications. As with any new integrated circuit technology, the industry is still actively exploring device performance and scaling limits (at present well above 300 GHz in frequency response, and rising), new circuit applications and potential new markets, as well as a host of novel device and structural innovations. This commercial success in the electronics arena is also spawning successful forays into the optoelectronics and even nanoelectronics fields. The Si heterostructure field is both exciting and dynamic in its scope. The implications of the Si heterostructure success story contained in this book are far-ranging and will be both lasting and influential in determining the future course of the electronics and optoelectronics infrastructure, fueling the miraculous communications explosion of the twenty-first century. While several excellent books on specific aspects of the Si heterostructures field currently exist (for example, on SiGe HBTs), this is the first reference book of its kind that ‘‘brings-it-all-together,’’ effectively presenting a comprehensive perspective by providing very broad topical coverage ranging from materials, to fabrication, to devices (HBT, FET, optoelectronic, and nanostructure), to CAD, to circuits, to applications. Each chapter is written by a leading international expert, ensuring adequate depth of coverage, upto-date research results, and a comprehensive list of seminal references. A novel aspect of this book is that it also contains ‘‘snap-shot’’ views of the industrial ‘‘state-of-the-art,’’ for both devices and circuits, and is designed to provide the reader with a useful basis of comparison for the current status and future course of the global Si heterostructure industry. This book is intended for a number of different audiences and venues. It should prove to be a useful resource as: 1. A hands-on reference for practicing engineers and scientists working on various aspects of Si heterostructure integrated circuit technology (both HBT, FET, and optoelectronic), including materials, fabrication, device physics, transistor optimization, measurement, compact modeling and device simulation, circuit design, and applications 2. A hands-on research resource for graduate students in electrical and computer engineering, physics, or materials science who require information on cutting-edge integrated circuit technologies ix

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3. A textbook for use in graduate-level instruction in this field 4. A reference for technical managers and even technical support/technical sales personnel in the semiconductor industry It is assumed that the reader has some modest background in semiconductor physics and semiconductor devices (at the advanced undergraduate level), but each chapter is self-contained in its treatment. In this age of extreme activity, in which we are all seriously pressed for time and overworked, my success in getting such a large collection of rather famous people to commit their precious time to my vision for this project was immensely satisfying. I am happy to say that my authors made the process quite painless, and I am extremely grateful for their help. The list of contributors to this book actually reads like a global ‘‘who’s who’’ of the silicon heterostructure field, and is impressive by any standard. I would like to formally thank each of my colleagues for their hard work and dedication to executing my vision of producing a lasting Si heterostructure ‘‘bible.’’ In order of appearance, the ‘‘gurus’’ of our field include: David L. Harame, IBM Microelectronics, USA Jin Cai, IBM, Thomas J. Watson Research Center, USA Tak H. Ning, IBM, Thomas J. Watson Research Center, USA Joachim N. Burghartz, Delft University of Technology, The Netherlands Alvin J. Joseph, IBM Microelectronics, USA James S. Dunn, IBM Microelectronics, USA Paul H.G. Kempf, Jazz Semiconductor, USA Katsuyoshi Washio, Hitachi Ltd., Japan Thomas F. Meister, Infineon Technologies AG, Germany H. Scha¨fer, Infineon Technologies AG, Germany W. Perndl, Infineon Technologies AG, Germany J. Bo¨ck, Infineon Technologies AG, Germany Dieter Knoll, IHP, Germany Alain Chantre, ST Microelectronics, France M. Laurens, ST Microelectronics, France B. Szelag, ST Microelectronics, France H. Baudry, ST Microelectronics, France P. Chevalier, ST Microelectronics, France J. Mourier, ST Microelectronics, France G. Troillard, ST Microelectronics, France B. Martinet, ST Microelectronics, France M. Marty, ST Microelectronics, France A. Monroy, ST Microelectronics, France Badih El-Kareh, Texas Instruments, USA Scott Balster, Texas Instruments, USA P. Steinmann, Texas Instruments, USA Hiroshi Yasuda, Texas Instruments, USA Roy Colclaser, Philips Semiconductors, USA Peter Deixler, Philips Semiconductors, USA Michael Schro¨ter, University of California at San Diego, USA Ramana M. Malladi, IBM Microelectronics, USA I would also like to thank my graduate students and post-docs, past and present, for their dedication and tireless work in this fascinating field. I rest on their shoulders. They include: David Richey, Alvin Joseph, Bill Ansley, Juan Rolda´n, Stacey Salmon, Lakshmi Vempati, Jeff Babcock, Suraj Mathew, Kartik Jayanaraynan, Greg Bradford, Usha Gogineni, Gaurab Banerjee, Shiming Zhang, Krish Shivaram, Dave Sheridan, Gang Zhang, Ying Li, Zhenrong Jin, Qingqing Liang, Ram Krithivasan, Yun Luo,

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Tianbing Chen, Enhai Zhao, Yuan Lu, Chendong Zhu, Jon Comeau, Jarle Johansen, Joel Andrews, Lance Kuo, Xiangtao Li, Bhaskar Banerjee, Curtis Grens, Akil Sutton, Adnan Ahmed, Becca Haugerud, Mustayeen Nayeem, Mustansir Pratapgarhwala, Guofu Niu, Emery Chen, Jongsoo Lee, and Gnana Prakash. Finally, I am grateful to Tai Soda at Taylor & Francis for talking me into this project, and supporting me along the way. I would also like to thank the production team at Taylor & Francis for their able assistance (and patience!), especially Jessica Vakili. The many nuances of the Si heterostructure field make for some fascinating subject matter, but this is no mere academic pursuit. In the grand scheme of things, the Si heterostructure industry is already reshaping the global communications infrastructure, which is in turn dramatically reshaping the way life on planet Earth will transpire in the twenty-first century and beyond. The world would do well to pay attention. It has been immensely satisfying to see both the dream of Si/SiGe bandgap engineering, and this book, come to fruition. I hope our efforts please you. Enjoy!

John D. Cressler Editor

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Editor

John D. Cressler received a B.S. in physics from the Georgia Institute of Technology (Georgia Tech), Atlanta, Georgia, in 1984, and an M.S. and Ph.D. in applied physics from Columbia University, New York, in 1987 and 1990. From 1984 to 1992 he was on the research staff at the IBM Thomas J. Watson Research Center in Yorktown Heights, New York, working on high-speed Si and SiGe bipolar devices and technology. In 1992 he left IBM Research to join the faculty at Auburn University, Auburn, Alabama, where he served until 2002. When he left Auburn University, he was Philpott–Westpoint Stevens Distinguished Professor of Electrical and Computer Engineering and director of the Alabama Microelectronics Science and Technology Center. In 2002, Dr. Cressler joined the faculty at Georgia Tech, where he is currently Ken Byers Professor of Electrical and Computer Engineering. His research interests include SiGe devices and technology; Si-based RF/microwave/millimeter-wave mixed-signal devices and circuits; radiation effects; device-circuit interactions; noise and linearity; reliability physics; extreme environment electronics, 2-D/3-D device-level simulation; and compact circuit modeling. He has published more than 350 technical papers related to his research, and is author of the books Silicon-Germanium Heterojunction Bipolar Transistors, Artech House, 2003 (with Guofu Niu), and Reinventing Teenagers: The Gentle Art of Instilling Character in Our Young People, Xlibris, 2004 (a slightly different genre!). Dr. Cressler was Associate Editor of the IEEE Journal of Solid-State Circuits (1998–2001), Guest Editor of the IEEE Transactions on Nuclear Science (2003–2006), and Associate Editor of the IEEE Transactions on Electron Devices (2005–present). He served on the technical program committees of the IEEE International Solid-State Circuits Conference (1992–1998, 1999–2001), the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (1995–1999, 2005–present), the IEEE International Electron Devices Meeting (1996–1997), and the IEEE Nuclear and Space Radiation Effects Conference (1999–2000, 2002– 2007). He currently serves on the executive steering committee for the IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, as international program advisor for the IEEE European Workshop on Low-Temperature Electronics, on the technical program committee for the IEEE International SiGe Technology and Device Meeting, and as subcommittee chair of the 2004 Electrochemical Society Symposium of SiGe: Materials, Processing, and Devices. He was the Technical Program Chair of the 1998 IEEE International Solid-State Circuits Conference, the Conference Co-Chair of the 2004 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, and the Technical Program Chair of the 2007 IEEE Nuclear and Space Radiation Effects Conference. Dr. Cressler was appointed an IEEE Electron Device Society Distinguished Lecturer in 1994, an IEEE Nuclear and Plasma Sciences Distinguished Lecturer in 2006, and was awarded the 1994 Office of Naval Research Young Investigator Award for his SiGe research program. He received the 1996 C. Holmes xiii

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MacDonald National Outstanding Teacher Award by Eta Kappa Nu, the 1996 Auburn University Alumni Engineering Council Research Award, the 1998 Auburn University Birdsong Merit Teaching Award, the 1999 Auburn University Alumni Undergraduate Teaching Excellence Award, an IEEE Third Millennium Medal in 2000, and the 2007 Georgia Tech Outstanding Faculty Leadership in the Development of Graduate Students Award. He is an IEEE Fellow. On a more personal note, John’s hobbies include hiking, gardening, bonsai, all things Italian, collecting (and drinking!) fine wines, cooking, history, and carving walking sticks, not necessarily in that order. He considers teaching to be his vocation. John has been married to Maria, his best friend and soul-mate, for 25 years, and is the proud father of three budding scholars: Matt, Christina, and Jo-Jo. Dr. Cressler can be reached at School of Electrical and Computer Engineering, 777 Atlantic Drive, N.W., Georgia Institute of Technology, Atlanta, GA 30332-0250 U.S.A. or [email protected] http://users.ece.gatech.edu/cressler/

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Contents

1 The Big Picture ............................................................................................................................ 1-1 John D. Cressler 2 A Brief History of the Field ........................................................................................................ 2-1 John D. Cressler 3 Overview: Fabrication of SiGe HBT BiCMOS Technology ...................................................... 3-1 John D. Cressler 4 Device Structures and BiCMOS Integration ............................................................................. 4-1 David L. Harame 5 SiGe HBTs on CMOS-Compatible SOI ...................................................................................... 5-1 Jin Cai and Tak H. Ning 6 Passive Components .................................................................................................................... 6-1 Joachim N. Burghartz 7 Industry Examples at the State-of-the-Art: IBM....................................................................... 7-1 Alvin J. Joseph and James S. Dunn 8 Industry Examples at the State-of-the-Art: Jazz........................................................................ 8-1 Paul H.G. Kempf 9 Industry Examples at the State-of-the-Art: Hitachi.................................................................. 9-1 Katsuyoshi Washio 10 Industry Examples at the State-of-the-Art: Infineon .............................................................. 10-1 Thomas F. Meister, H. Scha¨fer, W. Perndl, and J. Bo¨ck 11 Industry Examples at the State-of-the-Art: IHP ..................................................................... 11-1 Dieter Knoll 12 Industry Examples at the State-of-the-Art: ST........................................................................ 12-1 Alain Chantre, M. Laurens, B. Szelag, H. Baudry, P. Chevalier, J. Mourier, G. Troillard, B. Martinet, M. Marty, and A. Monroy 13 Industry Examples at the State-of-the-Art: Texas Instruments ............................................. 13-1 Badih El-Kareh, Scott Balster, P. Steinmann, and Hiroshi Yasuda 14 Industry Examples at the State-of-the-Art: Philips................................................................. 14-1 Roy Colclaser and Peter Deixler A.1 Properties of Silicon and Germanium ................................................................................... A.1-1 John D. Cressler

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A.2

The Generalized Moll–Ross Relations .................................................................................... A.2-1 John D. Cressler A.3 Integral Charge-Control Relations ......................................................................................... A.3-1 Michael Schro¨ter A.4 Sample SiGe HBT Compact Model Parameters..................................................................... A.4-1 Ramana M. Malladi Index ....................................................................................................................................................... I-1

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1 The Big Picture 1.1 1.2

John D. Cressler Georgia Institute of Technology

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1.3 1.4 1.5

The Communications Revolution...................................... Bandgap Engineering in the Silicon Material System ................................................................... Terminology and Definitions ............................................. The Application Space ........................................................ Performance Limits and Future Directions ......................

1-1 1-3 1-4 1-5 1-9

The Communications Revolution

We are at a unique juncture in the history of humankind, a juncture that amazingly we engineers and scientists have dreamed up and essentially created on our own. This pivotal event can be aptly termed the ‘‘Communications Revolution,’’ and the twenty-first century, our century, will be the era of human history in which this revolution plays itself out. This communications revolution can be functionally defined and characterized by the pervasive acquisition, manipulation, storage, transformation, and transmission of ‘‘information’’ on a global scale. This information, or more generally, knowledge, in its infinitely varied forms and levels of complexity, is gathered from our analog sensory world, transformed in very clever ways into logical ‘‘1’’s and ‘‘0’’s for ease of manipulation, storage, and transmission, and subsequently regenerated into analog sensory output for our use and appreciation. In 2005, this planetary communication of information is occurring at a truly mind-numbing rate, estimates of which are on the order of 80 Tera-bits/sec (1012) of data transfer across the globe in 2005 solely in wired and wireless voice and data transmission, 24 hours a day, 7 days a week, and growing exponentially. The world is quite literally abuzz with information flow—communication.* It is for the birth of the Communications Revolution that we humans likely will be remembered for 1000 years hence. Given that this revolution is happening during the working careers of most of us, I find it a wonderful time to be alive, a fact of which I remind my students often. Here is my point. No matter how one slices it, at the most fundamental level, it is semiconductor devices that are powering this communications revolution. Skeptical? Imagine for a moment that one could flip a switch and instantly remove all of the integrated circuits (ICs) from planet Earth. A moment’s reflection will convince you that there is not a single field of human endeavor that would not come to a grinding halt, be it commerce, or agriculture, or education, or medicine, or entertainment. Life as we in the first world know it in 2005 would simply cease to exist. And yet, remarkably, the same result would not have been true 50 years ago; even 20 years ago. Given the fact that we humans have been on planet Earth in our present form for at least 1 million years, and within communities

* I have often joked with my students that it would be truly entertaining if the human retina was sensitive to longer wavelengths of electromagnetic radiation, such that we could ‘‘see’’ all the wireless communications signals constantly bathing the planet (say, in greens and blues!). It might change our feelings regarding our ubiquitous cell phones!

1-1

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having entrenched cultural traditions for at least 15,000 years, this is truly a remarkable fact of history. A unique juncture indeed. Okay, hold on tight. It is an easy case to make that the semiconductor silicon (Si) has single-handedly enabled this communications revolution.* I have previously extolled at length the remarkable virtues of this rather unglamorous looking silver-grey element [1], and I will not repeat that discussion here, but suffice it to say that Si represents an extremely unique material system that has, almost on its own, enabled the conception and evolving execution of this communications revolution. The most compelling attribute, by far, of Si lies in the economy-of-scale it facilitates, culminating in the modern IC fabrication facility, effectively enabling the production of gazillions of low-cost, very highly integrated, remarkably powerful ICs, each containing millions of transistors; ICs that can then be affordably placed into widgets of remarkably varied form and function.y So what does this have to do with the book you hold in your hands? To feed the emerging infrastructure required to support this communications revolution, IC designers must work tirelessly to support increasingly higher data rates, at increasingly higher carrier frequencies, all in the design space of decreasing form factor, exponentially increasing functionality, and at ever-decreasing cost. And by the way, the world is going portable and wireless, using the same old wimpy batteries. Clearly, satisfying the near-insatiable appetite of the requisite communications infrastructure is no small task. Think of it as job security! For long-term success, this quest for more powerful ICs must be conducted within the confines of conventional Si IC fabrication, so that the massive economy-of-scale of the global Si IC industry can be brought to bear. Therein lies the fundamental motivation for the field of Si heterostructures, and thus this book. Can one use clever nanoscale engineering techniques to custom-tailor the energy bandgap of fairly conventional Si-based transistors to: (a) improve their performance dramatically and thereby ease the circuit and system design constraints facing IC designers, while (b) performing this feat without throwing away all the compelling economy-of-scale virtues of Si manufacturing? The answer to this important question is a resounding ‘‘YES!’’ That said, getting there took time, vision, as well as dedication and hard work of literally thousands of scientists and engineers across the globe. In the electronics domain, the fruit of that global effort is silicon–germanium heterojunction bipolar transistor (SiGe HBT) bipolar complementary metal oxide semiconductor (BiCMOS) technology, and is in commercial manufacturing worldwide and is rapidly finding a number of important circuit and system applications. In 2004, the SiGe ICs, by themselves, are expected to generate US$1 billion in revenue globally, with perhaps US$30 billion in downstream products. This US$1 billion figure is projected to rise to US$2.09 billion by 2006 [2], representing a growth rate of roughly 42% per year, a remarkable figure by any economic standard. The biggest single market driver remains the cellular industry, but applications in optical networking, hard disk drives for storage, and automotive collisionavoidance radar systems are expected to represent future high growth areas for SiGe. And yet, in the beginning of 1987, only 18 years ago, there was no such thing as a SiGe HBT. It had not been demonstrated as a viable concept. An amazing fact. In parallel with the highly successful development of SiGe HBT technology, a wide class of ‘‘transport enhanced’’ field effect transistor topologies (e.g., strained Si CMOS) have been developed as a means to boost the performance of the CMOS side of Si IC coin, and such technologies have also recently begun *The lone exception to this bold claim lies in the generation and detection of coherent light, which requires direct bandgap III–V semiconductor devices (e.g., GaAs of InP), and without which long-haul fiber communications systems would not be viable, at least for the moment. y Consider: it has been estimated that in 2005 there are roughly 20,000,000,000,000,000,000 (2 1019) transistors on planet Earth. While this sounds like a large number, let us compare it to some other large numbers: (1) the universe is roughly 4.2 1017sec old (13.7 billion years), (2) there are about 1 1021 stars in the universe, and (3) the universe is about 4 1023 miles across (15 billion light-years)! Given the fact that all 2 1020 of these transistors have been produced since December 23, 1947 (following the invention of the point-contact transistor by Bardeen, Brattain, and Shockley), this is a truly remarkable feat of human ingenuity.

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The Big Picture

1-3

to enter the marketplace as enhancements to conventional core CMOS technologies. The commercial success enjoyed in the electronics arena has very naturally also spawned successful forays into the optoelectronics and even nanoelectronics fields, with potential for a host of important downstream applications. The Si heterostructure field is both exciting and dynamic in its scope. The implications of the Si heterostructure success story contained in this book are far-ranging and will be both lasting and influential in determining the future course of the electronics and optoelectronics infrastructure, fueling the miraculous communications explosion of our twenty-first century. The many nuances of the Si heterostructure field make for some fascinating subject matter, but this is no mere academic pursuit. As I have argued, in the grand scheme of things, the Si heterostructure industry is already reshaping the global communications infrastructure, which is in turn dramatically reshaping the way life of planet Earth will transpire in the twenty-first century and beyond. The world would do well to pay close attention.

1.2

Bandgap Engineering in the Silicon Material System

As wonderful as Si is from a fabrication viewpoint, from a device or circuit designer’s perspective, it is hardly the ideal semiconductor. The carrier mobility for both electrons and holes in Si is comparatively small compared to their III–V cousins, and the maximum velocity that these carriers can attain under high electric fields is limited to about 1 107 cm/sec under normal conditions, relatively ‘‘slow.’’ Since the speed of a transistor ultimately depends on how fast the carriers can be transported through the device under sustainable operating voltages, Si can thus be regarded as a somewhat ‘‘meager’’ semiconductor. In addition, because Si is an indirect gap semiconductor, light emission is fairly inefficient, making active optical devices such as diode lasers impractical (at least for the present). Many of the III–V compound semiconductors (e.g., GaAs or InP), on the other hand, enjoy far higher mobilities and saturation velocities, and because of their direct gap nature, generally make efficient optical generation and detection devices. In addition, III–V devices, by virtue of the way they are grown, can be compositionally altered for a specific need or application (e.g., to tune the light output of a diode laser to a specific wavelength). This atomic-level custom tailoring of a semiconductor is called bandgap engineering, and yields a large performance advantage for III–V technologies over Si [3]. Unfortunately, these benefits commonly associated with III–V semiconductors pale in comparison to the practical deficiencies associated with making highly integrated, low-cost ICs from these materials. There is no robust thermally grown oxide for GaAs or InP, for instance, and wafers are smaller with much higher defect densities, are more prone to breakage, and are poorer heat conductors (the list could go on). These deficiencies translate into generally lower levels of integration, more difficult fabrication, lower yield, and ultimately higher cost. In truth, of course, III–V materials such as GaAs and InP fill important niche markets today (e.g., GaAs metal semiconductor field effect transistor (MESFETs) and HBTs for cell phone power amplifiers, AlGaAs- or InP-based lasers, efficient long wavelength photodetectors, etc.), and will for the foreseeable future, but III–V semiconductor technologies will never become mainstream in the infrastructure of the communications revolution if Si-based technologies can do the job. While Si ICs are well suited to high-transistor-count, high-volume microprocessors and memory applications, RF, microwave, and even millimeter-wave (mm-wave) electronic circuit applications, which by definition operate at significantly higher frequencies, generally place much more restrictive performance demands on the transistor building blocks. In this regime, the poorer intrinsic speed of Si devices becomes problematic. That is, even if Si ICs are cheap, they must deliver the required device and circuit performance to produce a competitive system at a given frequency. If not, the higher-priced but faster III–V technologies will dominate (as they indeed have until very recently in the RF and microwave markets). The fundamental question then becomes simple and eminently practical: is it possible to improve the performance of Si transistors enough to be competitive with III–V devices for high-performance applications, while preserving the enormous yield, cost, and manufacturing advantages associated with conventional Si fabrication? The answer is clearly ‘‘yes,’’ and this book addresses the many nuances

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associated with using SiGe and Si-strained layer epitaxy to practice bandgap engineering in the Si material system, a process culminating in, among other things, the SiGe HBT and strained Si CMOS, as well as a variety of other interesting electronic and optoelectronic devices built from these materials. This totality can be termed the ‘‘Si heterostructures’’ field.

1.3

Terminology and Definitions

A few notes on modern usage and pronunciation in this field are in order (really!). It is technically correct to refer to silicon–germanium alloys according to their chemical composition, Si1xGex , where x is the Ge mole fraction. Following standard usage, such alloys are generally referred to as ‘‘SiGe’’ alloys. Note, however, that it is common in the material science community to also refer to such materials as ‘‘Ge:Si’’ alloys. A SiGe film that is carbon doped (e.g., less than 0.20% C) in an attempt to suppress subsequent boron out-diffusion (e.g., in HBTs) is properly referred to as a SiGe:C alloy, or simply SiGeC (pronounced ‘‘silicon germanium carbon,’’ not ‘‘silicon germanium carbide’’). This class of SiGe alloys should be viewed as optimized SiGe alloys, and are distinct from SiGe films with a much higher C content (e.g., 2% to 3% C) that might be used, for instance, to lattice-match SiGeC alloys to Si. Believe it or not, this field also has its own set of slang pronunciations. The colloquial usage of the pronunciation \’sig-ee\ to refer to ‘‘silicon–germanium’’ (begun at IBM in the late 1990s) has come into vogue (heck, it may make it to the dictionary soon!), and has even entered the mainstream IC engineers’s slang; pervasively.* In the electronics domain, it is important to be able to distinguish between the various SiGe technologies as they evolve, both for CMOS (strained Si) and bipolar (SiGe HBT). Relevant questions in this context include: Is company X’s SiGe technology more advanced than company Y’s SiGe technology? For physical as well as historical reasons, one almost universally defines CMOS technology (Si, strained Si, or SiGe), a lateral transport device, by the drawn lithographic gate length (the CMOS technology ‘‘node’’), regardless of the resultant intrinsic device performance. Thus, a ‘‘90-nm’’ CMOS node has a drawn gate length of roughly 90 nm. For bipolar devices (i.e., the SiGe HBT), however, this is not so straightforward, since it is a vertical transport device whose speed is not nearly as closely linked to lithographic dimensions. In the case of the SiGe HBT it is useful to distinguish between different technology generations according to their resultant ac performance (e.g., peak common-emitter, unity gain cutoff frequency (fT), which is (a) easily measured and unambiguously compared technology to technology, and yet is (b) a very strong function of the transistor vertical doping and Ge profile and hence nicely reflects the degree of sophistication in device structural design, overall thermal cycle, epi growth, etc.) [1]. The peak fT generally nicely reflects the ‘‘aggressiveness,’’ if you will, of the transistor scaling which has been applied to a given SiGe technology. A higher level of comparative sophistication can be attained by also invoking the maximum oscillation frequency ( fmax), a parameter which is well correlated to both intrinsic profile and device parasitics, and hence a bit higher on the ladder of device performance metrics, and thus more representative of actual large-scale circuit performance. The difficulty in this case is that fmax is far more ambiguous than fT , in the sense that it can be inferred from various gain definitions (e.g., U vs. MAG), and in practice power gain data are often far less ideal in its behavior over frequency, more sensitive to accurate deembedding, and ripe with extraction ‘‘issues.’’ We thus term a SiGe technology having a SiGe HBT with a peak fT in the range of 50 GHz as ‘‘first generation;’’ that with a peak fT in the range of 100 GHz as ‘‘second generation;’’ that with a peak fT in the range of 200 GHz as ‘‘third generation;’’ and that with a peak fT in the range of 300 GHz as ‘‘fourth generation.’’ These are loose definitions to be sure, but nonetheless useful for comparison purposes.

*I remain a stalwart holdout against this snowballing trend and stubbornly cling to the longer but far more satisfying ‘‘silicon–germanium.’’

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The Big Picture

SiGe HBT BiCMOS technology evolution by generation

CMOS gate length

90 nm

3rd

0.12 µm

0.18 µm

0.25 µm

4th

2nd

1st 50 GHz

100 GHz

200 GHz

300 GHz

SiGe HBT peak cutoff frequency FIGURE 1.1 Evolution of SiGe HBT BiCMOS technology generations, as measured by the peak cutoff frequency of the SiGe HBT, and the CMOS gate length.

A complicating factor in SiGe technology terminology results from the fact that most, if not all, commercial SiGe HBT technologies today also contain standard Si CMOS devices (i.e., SiGe HBT BiCMOS technology) to realize high levels of integration and functionality on a single die (e.g., singlechip radios complete with RF front-end, data converters, and DSP). One can then speak of a given generation of SiGe HBT BiCMOS technology as the most appropriate intersection of both the SiGe HBT peak fT and the CMOS technology node (Figure 1.1). For example, for several commercially important SiGe HBT technologies available via foundry services, we have: . . . . . .

IBM SiGe 5HP—50 GHz peak fT SiGe HBT þ 0.35 mm Si CMOS (first generation) IBM SiGe 7HP—120 GHz peak fT SiGe HBT þ 0.18 mm Si CMOS (second generation) IBM SiGe 8HP—200 GHz peak fT SiGe HBT þ 0.13 mm Si CMOS (third generation) Jazz SiGe 60—60 GHz peak fT SiGe HBT þ 0.35 mm Si CMOS (first generation) Jazz SiGe 120—150 GHz peak fT SiGe HBT þ 0.18 mm Si CMOS (second generation) IHP SiGe SGC25B—120 GHz peak fT SiGe HBT þ 0.25 mm Si CMOS (second generation)

All SiGe HBT BiCMOS technologies can thus be roughly classified in this manner. It should also be understood that multiple transistor design points typically exist in such BiCMOS technologies (multiple breakdown voltages for the SiGe HBT and multiple threshold or breakdown voltages for the CMOS), and hence the reference to a given technology generation implicitly refers to the most aggressively scaled device within that specific technology platform.

1.4

The Application Space

It goes without saying in our field of semiconductor IC technology that no matter how clever or cool a new idea appears at first glance, its long-term impact will ultimately be judged by its marketplace ‘‘legs’’ (sad, but true). That is, was the idea good for a few journal papers and an award or two, or did someone actually build something and sell some useful derivative products from it? The sad reality is that the semiconductor field (and we are by no means exceptional) is rife with examples of cool new devices that

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never made it past the pages of the IEDM digest! The ultimate test, then, is one of stamina. And sweat. Did the idea make it out of the research laboratory and into the hands of the manufacturing lines? Did it pass the qualification-checkered flag, have design kits built around it, and get delivered to real circuit designers who built ICs, fabricated them, and tested them? Ultimately, were the derivative ICs inserted into real systems—widgets—to garner leverage in this or that system metric, and hence make the products more appealing in the marketplace? Given the extremely wide scope of the semiconductor infrastructure fueling the communications revolution, and the sheer volume of widget possibilities, electronic to photonic to optoelectronic, it is useful here to briefly explore the intended application space of Si heterostructure technologies as we peer out into the future. Clearly I possess no crystal ball, but nevertheless some interesting and likely lasting themes are beginning to emerge from the fog. SiGe HBT BiCMOS is the obvious ground-breaker of the Si heterostructures application space in terms of moving the ideas of our field into viable products for the marketplace. The field is young, but the signs are very encouraging. As can be seen in Figure 1.2, there are at present count 25 þ SiGe HBT industrial fabrication facilities on line in 2005 around the world, and growing steadily. This trend points to an obvious recognition that SiGe technology will play an important role in the emerging electronics infrastructure of the twenty-first century. Indeed, as I often point out, the fact that virtually every major player in the communications electronics field either: (a) has SiGe up and running in-house, or (b) is using someone else’s SiGe fab as foundry for their designers, is a remarkable fact, and very encouraging in the grand scheme of things. As indicated above, projections put SiGe ICs at a US$2.0 billion level by 2006, small by percentage perhaps compared to the near trillion dollar global electronics market, but growing rapidly. The intended application target? That obviously depends on the company, but the simple answer is, gulp, a little bit of everything! As depicted in Figure 1.3 and Figure 1.4, the global communications landscape is exceptionally diverse, ranging from low-frequency wireless (2.4 GHz cellular) to the fastest high-speed wireline systems (10 and 40 Gbit/sec synchronous optical network (SONET)). Core CMOS technologies are increasingly being pushed into the lower frequency wireless space, but the compelling drive to higher carrier frequencies over time will increasingly favor SiGe technologies. At present, SiGe ICs are making inroads into: the cellular industry for handsets [global system for mobile communications—GSM, code division multiple access (CDMA), wideband CDMA (W-CDMA), etc.], even for power amplifiers; various wireless local area networks (WLAN) building blocks, from components to fully integrated systems ranging from 2.4 to 60 GHz and up; ultrawide band (UWB) components; global positioning systems (GPS); wireless base stations; a variety of wireline networking products, from 2.5 to 40 Gbit/sec (and higher); data converters (D/A and A/D); highspeed memories; a variety of instrumentation electronics; read-channel memory storage products; core analog functions (op amps, etc.); high-speed digital circuits of various flavors; radiation detector

Industrial fabrication facilities

25 20 15 10 5 0 1993

FIGURE 1.2

SiGe HBT BiCMOS Strained–Si CMOS

1995

1997

1999 Year

2001

2003

Number of industrial SiGe and strained Si fabrication facilities.

2005

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The Big Picture

FIGURE 1.3 The global communications landscape, broken down by the various communications standards, and spanning the range of: wireless to wireline; fixed to mobile; copper to fiber; low data rate to broadband; and local area to wide area networks. WAN is wide area network, MAN is metropolitan area network, the so-called ‘‘last mile’’ access network, LAN is local area network, and PAN is personal area network, the emerging in-home network. (Used with the permission of Kyutae Lim.) Some application bands for SiGe ICs Defense Radar

Radar Navigation

GPS

Radar Automotive Collision avoidance

Polling

Cellular / PCS / Satellite / UWB

Communications WLAN

Bands: L 1

2

S

C

3

5

ISM W

Ka

X

Ku

10

20 30

50

100

Frequency (GHz)

FIGURE 1.4

Some application frequency bands for SiGe integrated circuits.

electronics; radar systems (from 3 to 77 GHz and up); a variety space-based electronics components; and various niche extreme environment components (e.g., cryogenic (77 K) hybrid superconductor–semiconductor systems). The list is long and exceptionally varied—this is encouraging. Clearly, however, some of these components of ‘‘everything’’ are more important than others, and this will take time to shake out. The strength of the BiCMOS twist to SiGe ICs cannot be overemphasized. Having both the high-speed SiGe HBT together on-chip with aggressively scaled CMOS allows one great flexibility in system design, the depths of which is just beginning to be plumbed. While debates still rage with respect to the most cost-effective partitioning at the chip and package level (system-on-a-chip versus system-in-a-package,

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etc.), clearly increased integration is viewed as a good thing in most camps (it is just a question of how much), and SiGe HBT BiCMOS is well positioned to address such needs across a broad market sector. The envisioned high-growth areas for SiGe ICs over the new few years include: the cellular industry, optical networking, disk drives, and radar systems. In addition, potential high-payoff market areas span the emerging mm-wave space (e.g., the 60 GHz ISM band WLAN) for short range, but very high data rate (Gbit/sec) wireless systems. A SiGe 60 GHz single-chip/package transceiver (see Figure 1.5 for IBM’s vision of such a beast) could prove to be the ‘‘killer app’’ for the emerging broadband multimedia market. Laughable? No. The building blocks for such systems have already been demonstrated using third-generation SiGe technology [4], and fully integrated transceivers are under development. The rest of the potential market opportunities within the Si heterostructures field can be leveraged by successes in the SiGe IC field, both directly and indirectly. On the strained Si CMOS front, there are existent proofs now that strained Si is likely to become a mainstream component of conventional CMOS scaling at the 90-nm node and beyond (witness the early success of Intel’s 90-nm logic technology built around uniaxially strained Si CMOS; other companies are close behind). Strained Si would seem to represent yet another clever technology twist that CMOS device technologists are pulling from their bag of tricks to keep the industry on a Moore’s law growth path. This was not an obvious development (to me anyway) even a couple of years back. A wide variety of ‘‘transport enhanced’’ Si-heterostructure-based FETs have been demonstrated (SiGe-channel FETs, Si-based high electron mobility transistors (HEMTs), as well as both uniaxially and biaxially strained FETs, etc). Most of these devices, however, require complex substrate engineering that would have seemed to preclude giga-scale integration level needs for microprocessor-level integration. Apparently not so. The notion of using Si heterostructures (either

Radiation

Vision of a 60 GHz SiGe wireless transceiver Package mold

Wirebond pad

Wirebond C4-Balls

Tx/Rx flip-Antenna

Mix

Filter structure

Q-signal

90 VCO I-signal

Underfill

Su

bs

tra

te

Mix Mix Q-signal LNA

I/Q

90 VCO I-signal

PLL

Mix

I/Q

QFN-package Package pin

FIGURE 1.5 Pfeiffer.)

Vision for a single-chip SiGe mm-wave transceiver system. (Used with the permission of Ullrich

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The Big Picture

uniaxial or biaxial strain or both) to boost conventional CMOS performance appears to be an appealing path for the future, a natural merging point I suspect for SiGe strained layers found in SiGe HBT BiCMOS (which to date contains only conventional Si CMOS) and strained Si CMOS. From the optoelectronics camp, things are clearly far less evolved, but no less interesting. A number of functional optoelectronic devices have been demonstrated in research laboratories. Near-term successes in the short wavelength detector arena and light emitting diodes (LEDs) are beginning to be realized. The achievement of successful coherent light emission in the Si heterostructure system (e.g., via quantum cascade techniques perhaps) would appear to be the ‘‘killer app’’ in this arena, and research in this area is in progress. More work is needed.

1.5

Performance Limits and Future Directions

We begin with device performance limits. Just how fast will SiGe HBTs be 5 years from now? Transistorlevel performance in SiGe HBTs continues to rise at a truly dizzying pace, and each major conference seems to bear witness to a new performance record (Figure 1.6). Both first- and second-generation SiGe HBT BiCMOS technology is widely available in 2005 (who would have thought even 3 years ago that fully integrated 100þ GHz Si-based devices would be ‘‘routine’’ on 200 mm wafers?), and even at the 200 GHz (third-generation) performance level, six companies (at last count) have achieved initial technology demonstrations, including IBM (Chapter 7), Jazz (Chapter 8), IHP (Chapter 11), ST Microelectronics (Chapter 12), Hitachi (Chapter 9), and Infineon (Chapter 10). Several are now either available in manufacturing, or are very close (e.g., [5]). At press time, the most impressive new stake-inthe-ground is the report (June 2004) of the newly optimized ‘‘SiGe 9T’’ technology, which simultaneously achieves 302 GHz peak fT and 306 GHz peak fmax, a clear record for any Si-based transistor, from IBM (Figure 1.7) [6]. This level of ac performance was achieved at a BVCEO of 1.6 V, a BVCBO of 5.5 V, and a current gain of 660. Noise measurements on these devices yielded NFmin/Gassoc of 0.45 dB/14 dB and 1.4 dB/8 dB at 10 and 25 GHz, respectively. Measurements of earlier (unoptimized) fourth-generation IBM SiGe HBTs have yielded record values of 375 GHz peak fT [7] at 300 K and above 500 GHz peak fT at 85 K. Simulations suggest that THz-level (1000 GHz) intrinsic transistor performance is not a laughable proposition in SiGe HBTs (Chapter 16, see Silicon Heterostructure Devices). This fact still amazes even me, the eternal optimist of SiGe performance! I, for one, firmly believe that we will see SiGe

400 4th

Cutoff frequency (GHz)

350 300 250 3rd 200 150

2nd

100 50 0 0.1

1st

1.0 10 Collector current density (mA/mm2)

100

FIGURE 1.6 Measured cutoff frequency as a function of bias current density for four different SiGe HBT technology generations.

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400 f T + f max = 400 GHz

Peak f max (GHz)

350

600 GHz f T = f max

300 250 200 GHz

200 150 100

SiGe+SiGe: C HBT 300 K

50 0

0

50

100

150

200

250

300

350

400

Peak f T (GHz)

FIGURE 1.7 Measured maximum oscillation frequency versus cutoff frequency for a variety of generations of SiGe HBT BiCMOS technology shown in Figure 1.1.

HBTs above-500 GHz peak fT and fmax fully integrated with nanometer-scale (90 nm and below) Si CMOS (possibly strained Si CMOS) within the next 3 to 5 years. One might logically ask, particularly within the confines of the above discussion on ultimate market relevance, why one would even attempt to build 500 GHz SiGe HBTs, other than to win a best-paper award, or to trumpet that ‘‘because-it’s-there’’ Mount Everest mentality we engineers and scientists love so dearly. This said, if the future ‘‘killer app’’ turns out to be single-chip mm-wave transceiver systems with on-board DSP for broadband multimedia, radar, etc., then the ability of highly scaled, highly integrated, very high performance SiGe HBTs to dramatically enlarge the circuit/ system design space of the requisite mm-wave building blocks may well prove to be a fruitful (and marketable) path. Other interesting themes are emerging in the SiGe HBT BiCMOS technology space. One is the very recent emergence of complementary SiGe (C-SiGe) HBT processes (npn þ pnp SiGe HBTs). While very early pnp SiGe HBT prototypes were demonstrated in the early 1990s, only in the last 2 years or so have fully complementary SiGe processes been developed, the most mature of which to date is the IHP SGC25C process, which has 200 GHz npn SiGe HBTs and 80 GHz pnp SiGe HBTs (Chapter 11). Having very high-speed pnp SiGe HBTs on-board presents a fascinating array of design opportunities aimed particularly at the analog/mixed-signal circuit space. In fact, an additional emerging trend in the SiGe field, particularly for companies with historical pure analog circuit roots, is to target lower peak fT, but higher breakdown voltages, while simultaneously optimizing the device for core analog applications (e.g., op amps, line drivers, data converters, etc.), designs which might, for instance, target better noise performance, and higher current gain-Early voltage product than mainstream SiGe technologies. One might even choose to park that SiGe HBT platform on top of thick film SOI for better isolation properties (Chapter 13). Another interesting option is the migration of high-speed vertical SiGe HBTs with very thin film CMOS-compatible SOI (Chapter 5). This technology path would clearly favor the eventual integration of SiGe HBTs with strained Si CMOS, all on SOI, a seemingly natural migratory path. If one accepts the tenet that integration is a good thing from a system-level perspective, the Holy Grail in the Si heterostructure field would, in the end, appear to be the integration of SiGe HBTs for RF through mm-wave circuitry (e.g., single-chip mm-wave transceivers complete with on-chip antennae), strained Si CMOS for all DSP and memory functionality, both perhaps on SOI, Si-based light emitters, SiGe HBT modulator electronics, and detectors for such light sources, together with on-chip waveguides to steer the light, realized all on one Si wafer to produce a ‘‘Si-based optoelectronic superchip’’ [8], that could do-it-all. These diverse blocks would be optional plug-in modules around a core SiGe

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HBT þ strained Si CMOS IC technology platform, perhaps with flip-chip (or other) packaging techniques to join different sub-die to the main superchip (e.g., for a Si-based detector or laser). I know, I know. It is not obvious that even if each of these blocks could be realized, that it would make economic sense to do so for real systems. I have no quarrel with that. I think such a Si-based superchip is a useful paradigm, however, to bind together all of the clever objects we wish to ultimately build with Si heterostructures, from electronic to photonic, and maintain the vision of the one overarching constraint that guides us as we look forward—keep whatever you do compatible with high-volume manufacturing in Si fabrication facilities if you want to shape the path of the ensuing communications revolution. This Si-based superchip clearly remains a dream at present. A realizable dream? And if realizable, commercially viable? Who knows? Only time will tell. But it is fun to think about. As you peruse this book you hold in your hands, which spans the whole Si heterostructure research and development space, from materials, to devices, to circuit and system applications, I think you will be amazed at both the vision, cleverness, and smashing successes of the many scientists and engineers who make up our field. Do not count us out! We are the new architects of an oh-so-very-interesting future.

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 2. ‘‘SiGe devices market to hit $2 billion in 2006,’’ article featured on CompoundSemicoductor.net, http://compoundsemiconductor.net/articles/news/8/3/22/1. 3. F Capasso. Band-gap engineering: from physics and materials to new semiconductor devices. Science, 235:172–176, 1987. 4. S Reynolds, B Floyd, U Pfeiffer, and T Zwick. 60 GHz transciever circuits in SiGe bipolar technology. Technical Digest of the IEEE International Solid-State Circuits Conference, San Francisco, 2004, pp 442–443. 5. AJ Joseph, D Coolbaugh, D Harame, G Freeman, S Subbanna, M Doherty, J Dunn, C Dickey, D Greenberg, R Groves, M Meghelli, A Rylyakov, M Sorna, O Schreiber, D Herman, and T Tanji. 0.13 mm 210 GHz fT SiGe HBTs—expanding the horizons of SiGe BiCMOS. Technical Digest of the IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp 180–182. 6. J-S Rieh, D Greenberg, M Khater, KT Schonenberg, J-J Jeng, F Pagette, T Adam, A Chinthakindi, J Florkey, B Jagannathan, J Johnson, R Krishnasamy, D Sanderson, C Schnabel, P Smith, A Stricker, S Sweeney, K Vaed, T Yanagisawa, D Ahlgren, K Stein, and G Freeman. SiGe HBTs for millimeter-wave applications with simultaneously optimized fT and fmax. Proceedings of the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Fort Worth, 2004, pp 395–398. 7. JS Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, S-J Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. SiGe HBTs with cutoff frequency of 350 GHz. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp 771–774. 8. R Soref. Silicon-based photonic devices. Technical Digest of the IEEE International Solid-State Circuits Conference, 1995, pp 66–67.

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2 A Brief History of the Field John D. Cressler Georgia Institute of Technology

2.1 2.2 2.3

Si–SiGe Strained Layer Epitaxy.......................................... 2-1 SiGe HBTs ............................................................................ 2-3 SiGe–Strained Si FETs and Other SiGe Devices ............... 2-6

In the historical record of any field of human endeavor, being ‘‘first’’ is everything. It is often said that ‘‘hindsight is 20–20,’’ and it is tempting in many cases to ascribe this or that pivotal event as ‘‘obvious’’ or ‘‘easy’’ once the answer is known. Anyone intimately involved in a creative enterprise knows, however, that it is never easy being first, and often requires more than a little luck and maneuvering. Thus the triumphs of human creativity, the ‘‘firsts,’’ should be appropriately celebrated. Still, later chroniclers often gloss over, and then eventually ignore, important (and sometimes very interesting) twists and turns, starts and stops, of the winners as well as the second and third place finishers, who in the end may in fact have influenced the paths of the winners, sometimes dramatically. The history of our field, for instance, is replete with interesting competitive battles, unusual personalities and egos, no small amount of luck, and various other fascinating historical nuances. There is no concise history of our field available, and while the present chapter is not intended to be either exhaustive or definitive, it represents my firm conviction that the history of any field is both instructive and important for those who follow in the footsteps of the pioneers. Hopefully this brief history does not contain too many oversights or errors, and is offered as a step in the right direction for a history of pivotal events that helped shape the Si heterostructures field.

2.1

Si–SiGe Strained Layer Epitaxy

The field of Si-based heterostructures solidly rests on the shoulders of materials scientists and crystal growers, those purveyors of the semiconductor ‘‘black arts’’ associated with the deposition of pristine films of nanoscale dimensionality onto enormous Si wafers with near infinite precision. What may seem routine today was not always so. The Si heterostructure story necessarily begins with materials, and circuit designers would do well to remember that much of what they take for granted in transistor performance owes a great debt to the smelters of the crystalline world. Table 2.1 summarizes the key steps in the development of SiGe–Si strained layer epitaxy. Given that Ge was the earliest and predominant semiconductor pursued by the Bell Laboratories transistor team, with a focus on the more difficult to purify Si to come slightly later, it is perhaps not surprising that the first study of SiGe alloys, albeit unstrained bulk alloys, occurred as early as 1958 [1]. It was recognized around 1960 [2] that semiconductor epitaxy* would enable more robust and controllable transistor fabrication. Once the move to Si-based processing occurred, the field of Si epitaxy was

*The word ‘‘epitaxy’’ (or just ‘‘epi’’) is derived from the Greek word epi, meaning ‘‘upon’’ or ‘‘over.’’

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Milestones in the Development of SiGe–Si Strained Layer Epitaxy

Historical Event

Year

Ref.

First investigation of the bandgap of unstrained SiGe alloys First epitaxially grown layer to be used in a transistor First investigation of high-temperature Si epitaxy Concept of critical thickness for epitaxial strained layers Energy minimization approach for critical thickness Force-balance approach for critical thickness First growth of SiGe strained layers First growth of SiGe epitaxy by MBE First stability calculations of SiGe strained layers First measurements of energy bandgap in SiGe strained layers First growth of Si epitaxy by LRP-CVD First 2D electron gas in the SiGe system First growth of Si epitaxy by UHV/CVD First measurements of band alignments in SiGe–Si First growth of SiGe epitaxy by UHV/CVD First step-graded relaxed SiGe substrate First growth of SiGe epitaxy by LRP-CVD First growth of Si epitaxy by AP-CVD First 2D hole gas in the SiGe system First growth of SiGe epitaxy by AP-CVD First majority hole mobility measurements in SiGe First minority electron mobility measurements in SiGe First growth of lattice-matched SiGeC alloys First growth of SiGe layers with carbon doping First stability calculations to include a Si cap layer

1958 1960 1963 1963 1963 1974 1975 1984 1985 1985 1985 1985 1986 1986 1988 1988 1989 1989 1989 1991 1991 1992 1992 1994 2000

[1] [2] [3] [4] [5] [6] [7] [8] [9] [10,11] [12] [13] [14] [15] [16] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25]

launched, the first serious investigation of which was reported in 1963 [3]. Early Si epitaxy was exclusively conducted under high-temperature processing conditions, in the range of 11008C, a temperature required to obtain a chemically pure and pristine growth interface on the Si host substrate for the soon-to-be-grown crystalline Si epi. High-temperature Si epi has been routinely used in basically this same form for over 40 years now, and represents a mature fabrication technique that is still widely practiced for many types of Si devices (e.g., high-speed bipolar transistors and various power devices). Device engineers have long recognized the benefits of marrying the many virtues of Si as a host material for manufacturing electronic devices, with the bandgap engineering principles routinely practiced in the III–V system. Ultimately this requires a means by which one can perform epitaxial deposition of thin Si layers on large Si substrates, for both p- and n-type doping of arbitrary abruptness, with very high precision, across large wafers, and doping control at high dynamic range. Only a moment’s reflection is required to appreciate that this means the deposition of the Si epi must occur at very low growth temperatures, say 5008C to 6008C (not ‘‘low’’ per se, but low compared to the requisite temperatures needed for solid-state diffusion of dopants in Si). Such a low-temperature Si epi would then facilitate the effective marriage of Si and Ge, two chemically compatible elements with differing bandgaps, and enable the doping of such layers with high precision, just what is needed for device realizations. Clearly the key to Si-based bandgap engineering, Si-heterostructures, our field, is the realization of device quality, low-temperature Si epi (and hence SiGe epi), grown pseudomorphically* on large Si host substrates. Conquering this task proved to be remarkably elusive and time consuming. In the III–V semiconductor world, where very low processing temperatures are much easier to attain, and hence more common than for Si, the deposition of multiple semiconductors on top of one another proved quite feasible (e.g., GaAs on InP), as needed to practice bandgap engineering, for instance, *The word ‘‘pseudo’’ is derived from the Greek word pseude¯s, meaning ‘‘false,’’ and the word ‘‘morphic’’ is derived from the Greek word morphe¯, meaning ‘‘form.’’ Hence, pseudomorphic literally means false-form.

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resulting in complex material composites having differing lattice constants in intimate physical contact. To accommodate the differing lattice constants while maintaining the crystallinity of the underlying films, strain is necessarily induced in the composite film, and the notion of a film ‘‘critical thickness,’’ beyond which strain relaxation occurs via fundamental thermodynamic driving forces, was defined as early as 1963 [4], as were the energy minimization techniques needed for calculating such critical thicknesses [5]. Alternative ‘‘force-balance’’ techniques for addressing the so-called stability issues in strained layer epitaxy came from the III–V world in 1974, and were applied to SiGe strained layer epitaxy in 1985 [9]. Interestingly, however, research continues today on stability in complicated (e.g., compositionally graded) SiGe films, and only very recently have reasonably complete theories been offered which seem to match well with experiment [25]. The first reported growth of SiGe strained layers was in 1975 in Germany [7], but the field did not begin to seriously heat up until the early 1980s, when several teams pioneered the application of molecular beam epitaxy (MBE) to facilitate materials studies of device-quality strained SiGe on Si in 1984 [8]. Optical studies on these films resulted in encouraging findings concerning the beneficial effects of strain on the band-edge properties of SiGe [10,11], paving the way for serious contemplation of devices built from such materials. Parallel paths toward other low-temperature Si epi growth techniques centered on the ubiquitous chemical vapor deposition (CVD) approach were simultaneously pursued, culminating in the so-called limited-reaction-processing CVD (LRP-CVD) technique (Si epi in 1985 [12], and SiGe epi in 1989 [17]), the ultrahigh-vacuum CVD (UHV/CVD) technique (Si epi in 1986 [14] and SiGe epi in 1988 [16]), and various atmospheric pressure CVD (AP-CVD) techniques (e.g., Si epi in 1989 [18], and SiGe epi in 1991 [20]). These latter two techniques, in particular, survive to this day, and are widely used in the SiGe heterojunction bipolar transistor (HBT) industry. Device-quality SiGe–Si films enabled a host of important discoveries to occur, which have important bearing on device derivatives, including the demonstration of both two-dimensional electron and hole gases [13,19], and the fortuitous observation that step-graded SiGe buffer layers could be used to produce device-quality strained Si on SiGe, with its consequent conduction band offsets [16]. This latter discovery proved important in the development of SiGe–Si heterostructure-based FETs. Both majority and minority carrier mobility measurements occurred in the early 1990s [21,22], although reliable data, particularly involving minority carriers, remain sparse in the literature. Also in the early 1990s, experiments using high C content as a means to relieve strain in SiGe and potentially broaden the bandgap engineering space by lattice-matching SiGe:C materials to Si substrates (a path that has to date not borne much fruit, unfortunately), while others began studying efficacy of C-doping of SiGe, a result that ultimately culminated in the wide use today of C-doping for dopant diffusion suppression in SiGe:C HBTs [23,24]. The Si–SiGe materials field continues to evolve. Commercial single wafer (AP-CVD) and batch wafer (UHV/CVD) Si–SiGe epi growth tools compatible with 200 mm (and soon 300 mm) Si wafers exist in literally dozens of industrial fabrication facilities around the world, and SiGe growth can almost be considered routine today in the ease in which it can be integrated into CMOS-compatible fabrication processes. It was clearly of paramount importance in the ultimate success of our field that some of the ‘‘black magic’’ associated with robust SiGe film growth be removed, and this, thankfully, is the case in 2005.

2.2

SiGe HBTs

Transistor action was first demonstrated by Bardeen and Brattain in late December of 1947 using a point contact device [26]. Given all that has transpired since, culminating in the Communications Revolution, which defines our modern world (refer to the discussion in Chapter 1), this pivotal event surely ranks as one of the most significant in the course of human history—bold words, but nevertheless true. This demonstration of a solid-state device exhibiting the key property of amplification (power gain) is also unique in the historical record for the precision with which we can locate it in time—December 23,

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1947, at about 5 p.m. Not to be outdone, Shockley rapidly developed a theoretical basis for explaining how this clever object worked, and went on to demonstrate the first true bipolar junction transistor (BJT) in 1951 [27]. The first BJT was made, ironically in the present context, from Ge. The first silicon BJT was made by Teal in 1954 using grown junction techniques. The first diffused silicon BJT was demonstrated in 1956 [28], and the first epitaxially grown silicon BJT was reported in 1960, see Ref. [2]. The concept of the HBT is surprisingly an old one, dating in fact to the fundamental BJT patents filed by Shockley in 1948 [29]. Given that the first bipolar transistor was built from Ge, and III–V semiconductors were not yet on the scene, it seems clear that Shockley envisioned the combination of Si (wide bandgap emitter) and Ge (narrow bandgap base) to form a SiGe HBT. The basic formulation and operational theory of the HBT, for both the traditional wide bandgap emitter plus narrow bandgap base approach found in most III–V HBTs, as well as the drift-base (graded) approach used in SiGe HBTs today, was pioneered by Kroemer, and was largely in place by 1957 [30–32]. It is ironic that Kroemer in fact worked hard early on to realize a SiGe HBT, without success, ultimately pushing him toward the III–V material systems for his heterostructure studies, a path that proved in the end to be quite fruitful for him, since he shared the Nobel Prize in physics in 2000 for his work in (III–V) bandgap engineering for electronic and photonic applications [33]. While III–V HBT (e.g., AlGaAs–GaAs) demonstrations began appearing in the 1970s, driven largely by the needs for active microwave components in the defense industry, reducing the SiGe HBT to practical reality took 30 years after the basic theory was in place due to material growth limitations. As pointed out [34] the semiconductor device field is quite unique in the scope of human history because ‘‘science’’ (theoretical understanding) preceded the ‘‘art’’ (engineering and subsequent technological advancement). Once device-quality SiGe films were finally achieved in the mid-1980s, however, progress was quite rapid. Table 2.2 summarizes the key steps in the evolution of SiGe HBTs. The first functional SiGe HBT was demonstrated by an IBM team in December 1987 at the IEDM [35]. The pioneering result showed a SiGe HBT with functional, albeit leaky, dc characteristics; but it was a SiGe HBT, it worked (barely), and it was the first.* It is an often overlooked historical point, however, that at least four independent groups were simultaneously racing to demonstrate the first functional SiGe HBT, all using the MBE growth technique: the IBM team [35], a Japanese team [62], a Bell Laboratories team [63], and a Linko¨ping University team [64]. The IBM team is fairly credited with the victory, since it presented (and published) its results in early December of 1987 at the IEDM (it would have been submitted to the conference for review in the summer 1987) [35]. Even for the published journal articles, the IBM team was the first to submit its paper for review (on November 17, 1987) [65]. All four papers appeared in print in the spring of 1988. Other groups soon followed with more SiGe HBT demonstrations. The first SiGe HBT demonstrated using (the ultimately more manufacturable) CVD growth technique followed shortly thereafter, in 1989, first using LRP-CVD [17], and then with UHV/CVD [36]. Worldwide attention became squarely focused on SiGe technology, however, in June 1990 at the IEEE VLSI Technology Symposium with the demonstration of a non-self-aligned UHV/CVD SiGe HBT with a peak cutoff frequency of 75 GHz [37,38]. At that time, this SiGe HBT result was roughly twice the performance of state-of-the-art Si BJTs, and clearly demonstrated the future performance potential of the technology (doubling of transistor performance is a rare enough event that it does not escape significant attention!). Eyebrows were raised, and work to develop SiGe HBTs for practical circuit applications began in earnest in a large number of industrial and university laboratories around the world.y The feasibility of implementing pnp SiGe HBTs was also demonstrated in June 1990 [40]. In December 1990, the simplest digital circuit, an emitter-coupled-logic (ECL) ring oscillator, using *An interesting historical perspective of early SiGe HBT development at IBM is contained in Ref. [61]. y A variety of zero-Dt, mesa-isolated, III–V-like high-speed SiGe HBTs were reported in the early 1990s (e.g., Ref. [66]), but we focus here on fully integrated, CMOS-compatible SiGe HBT technologies, because they are inherently more manufacturable, and hence they are the only ones left standing today, for obvious reasons.

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A Brief History of the Field TABLE 2.2

Milestones in the Development of SiGe HBTs

Historical Event

Year

Ref.

First demonstration of transistor action Basic HBT concept First demonstration of a bipolar junction transistor First demonstration of a silicon bipolar transistor Drift-base HBT concept Fundamental HBT theory First epitaxial silicon transistors First SiGe HBT First ideal SiGe HBT grown by CVD First SiGe HBT grown by UHV/CVD First high-performance SiGe HBT First self-aligned SiGe HBT First SiGe HBT ECL ring oscillator First pnp SiGe HBT First operation of SiGe HBTs at cryogenic temperatures First SiGe HBT BiCMOS technology First LSI SiGe HBT integrated circuit First SiGe HBT with peak fT above 100 GHz First SiGe HBT technology in 200-mm manufacturing First SiGe HBT technology optimized for 77 K First radiation tolerance investigation of SiGe HBTs First report of low-frequency noise in SiGe HBTs First SiGe:C HBT First high-power SiGe HBTs First sub-10 psec SiGe HBT ECL circuits First high-performance SiGe:C HBT technology First SiGe HBT with peak fT above 200 GHz First SiGe HBT with peak fT above 300 GHz First complementary (npn þ pnp) SiGe HBT technology First C-SiGe technology with npn and pnp fT above 100 GHz First vertical SiGe HBT on thin film (CMOS compatible) SOI First SiGe HBT with both fT and fmax above 300 GHz

1947 1948 1951 1956 1954 1957 1960 1987 1989 1989 1990 1990 1990 1990 1990 1992 1993 1993 1994 1994 1995 1995 1996 1996 1997 1999 2001 2002 2003 2003 2003 2004

[26] [29] [27] [28] [30] [31,32] [2] [35] [17] [36] [37,38] [39] [39] [40] [41] [42] [43] [44,45] [46] [47] [48] [49] [50] [51,52] [53] [54] [55] [56] [57] [58] [59] [60]

self-aligned, fully integrated SiGe HBTs was produced [39]. The first SiGe BiCMOS technology (SiGe HBT þ Si CMOS) was reported in December 1992 [42]. Theoretical predictions of the inherent ability of SiGe HBTs to operate successfully at cryogenic temperatures (in contrast to Si BJTs) were first confirmed in 1990 [41], and SiGe HBT profiles optimized for the liquid nitrogen temperature environment (77 K) were reported in 1994 [48]. The first LSI SiGe HBT circuit (a 1.2 Gsample/sec 12-bit digital-to-analog converter—DAC) was demonstrated in December 1993 [43]. The first SiGe HBTs with frequency response greater than 100 GHz were described in December 1993 by two independent teams [44,45], and the first SiGe HBT technology entered commercial production on 200-mm wafers in December 1994 [46]. The first report of the effects of ionizing radiation on advanced SiGe HBTs was made in 1995 [48]. Due to the natural tolerance of epitaxial-base bipolar structures to conventional radiation-induced damage mechanisms without any additional radiation-hardening process changes, SiGe HBTs are potentially very important for space-based and planetary communication systems applications, spawning an important new sub-discipline for SiGe technology. The first demonstration that epitaxial SiGe strained layers do not degrade the superior low-frequency noise performance of bipolar transistors occurred in 1995, opening the way for very low-phase noise frequency sources [49]. Carbon-doping of epitaxial SiGe layers as a means to effectively suppress boron out-diffusion during fabrication has rapidly become the preferred approach for commercial SiGe technologies, particularly those above first-generation performance levels. Carbon-doping of SiGe HBTs has its own interesting

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history, dating back to the serendipitous discovery [50] in 1996 that incorporating small amounts of C into a SiGe epi layer strongly retards (by an order of magnitude) the diffusion of the boron (B) base layer during subsequent thermal cycles. Given that maintaining a thin base profile during fabrication is perhaps the most challenging aspect of building a manufacturable SiGe technology, it is somewhat surprising that it took so long for the general adoption of C-doping as a key technology element. I think it is fair to say that most SiGe practitioners at that time viewed C-doping with more than a small amount of skepticism, given that C can act as a deep trap in Si, and C contamination is generally avoided at all costs in Si epi processes, particularly for minority carrier devices such as the HBT. At the time of the discovery of C-doping of SiGe in 1996, most companies were focused on simply bringing up a SiGe process and qualifying it, relegating the potential use of C to the back burner. In fairness, most felt that C-doping was not necessary to achieve first-generation SiGe HBT performance levels. The lone visionary group to solidly embrace C-doping of SiGe HBTs at the onset was the IHP team in Germany, whose pioneering work eventually paid off and began to convince the skeptics of the merits of C-doping. The minimum required C concentration for effective out-diffusion suppression of B was empirically established to be in the vicinity of 0.1% to 0.2% C (i.e., around 1 1020 cm3). Early on, much debate ensued on the physical mechanism of how C impedes the B diffusion process, but general agreement for the most part now exists and is discussed in Chapter 11 (see SiGe and Si Strained-Layer Epitaxy for Silicon Heterostructure Devices). The first high-performance, fully integrated SiGe:C HBT technology was reported in 1999 [54]. The first ‘‘high-power’’ SiGe HBTs (S band, with multiwatt output power) were reported in 1996 using thick collector doping profiles [51,52]. The 10-psec ECL circuit performance barrier was broken in 1997 [53]. The 200-GHz peak fT performance barrier was broken in November 2001 for a nonself-aligned device [55], and for a self-aligned device in February 2002 [67]. By 2004, a total of six industrial laboratories had achieved 200 GHz performance levels. A SiGe HBT technology with a peak fT of 350 GHz (375 GHz values were reported in the IEDM presentation) was presented in December 2002 [56], and this 375 GHz fT value remains a record for room temperature operation (it is above 500 GHz at cryogenic temperatures), and an optimized version with both fT and fmax above 300 GHz was achieved in June 2004 [60]. This combined level of 300þ GHz for both fT and fmax remains a solid record for any Si-based semiconductor device. Other recent and interesting developments in the SiGe HBT field include the first report of a complementary (npn þ pnp) SiGe HBT (C-SiGe) technology in 2003 [57], rapidly followed by a C–SiGe technology with fT for both the npn and pnp SiGe HBTs above 100 GHz [58]. In addition, a novel vertical npn SiGe HBT has been implemented in thin-film (120 nm) CMOS-compatible SOI [59]. Besides further transistor performance enhancements, other logical developments to anticipate in this field include the integration of SiGe HBTs with strained-Si CMOS for a true all-Si-heterostructure technology. Not surprisingly, research and development activity involving SiGe HBTs, circuits built from these devices, and various SiGe HBT technologies, in both industry and at universities worldwide, has grown very rapidly since the first demonstration of a functional SiGe HBT in 1987, only 18 years in the past.

2.3

SiGe–Strained Si FETs and Other SiGe Devices

The basic idea of using an electric field to modify the surface properties of materials, and hence construct a ‘‘field-effect’’ device, is remarkably old (1926 and 1935), predating even the quest for a solid-state amplifier [68]. Given the sweeping dominance of CMOS technology in the grand scheme of the electronics industry today, it is ironic that the practical demonstration of the BJT preceded that of the MOSFET by 9 years. This time lag from idea to realization was largely a matter of dealing with the many perils associated with obtaining decent dielectric materials in the Si system—doubly ironic given that Si has such a huge natural advantage over all other semiconductors in this regard. Bread-and-butter notions of ionic contamination, de-ionized water, fixed oxide charge, surface state passivation, and cleanroom techniques in semiconductor fabrication had to be learned the hard way. Once device-quality SiO2

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A Brief History of the Field

was obtained in the late 1950s, and a robust gate dielectric could thus be fabricated, it was not long until the first functional MOSFET was demonstrated in 1960 [69]. The seemingly trivial (remember, however, that hindsight is 20–20!) connection of n-channel and p-channel MOSFETs to form low-power CMOS in 1963 [70] paved the way (eventually) to the high-volume, low-cost, highly integrated microprocessor, and the enormous variety of computational engines that exist today as a result. Like their cousin, the SiGe HBT, SiGe–strained Si FETs did not get off the ground until the means for accomplishing the low-temperature growth of Si epitaxy could be realized. Once that occurred in the mid-1980s the field literally exploded. Table 2.3 summarizes the milestones in the evolution of SiGe– strained Si FETs, as well as a veritable menagerie of other electronic and optoelectronic components built from SiGe–strained Si epitaxy. It was discovered as early as 1971 that direct oxidation of SiGe was a bad idea for building gate dielectrics [71]. Given that gate oxide quality, low-temperature deposited oxides, did not exist in the mid-1980s, the earliest FET demonstrations were modulation-doped, Schottky-gated, FETs, and both n-channel and p-channel SiGe MODFETs were pioneered as early as 1986 using MBE-grown material [72,73]. Before the SiGe MOSFET field got into high gear in the 1990s, a variety of other novel device demonstrations occurred, including: the first SiGe superlattice photodetector [74], the first SiGe Schottky barrier diodes (SBD) in 1988 [75], the first SiGe hole-transport resonant tunneling diode (RTD) in 1988 [76], and the first SiGe bipolar inversion channel FET (BiCFET) in 1989, a now-extinct dinosaur [77]. Meanwhile, early studies using SiGe in conventional CMOS gate stacks to minimize dopant depletion effects and tailor work functions, a fairly common practice in CMOS today, occurred in 1990 [78], and the first SiGe waveguides on Si substrates were produced in 1990 [79]. The first functional SiGe channel pMOSFET was published in 1991, and shortly thereafter, a wide variety of other approaches aimed at obtaining the best SiGe pMOSFETs (see, for instance, Refs. [93–95]). The first electron-transport RTD was demonstrated in 1991 [81], and the first LED in SiGe

TABLE 2.3

Milestones in the Development of SiGe–Strained Si FETs and Other Devices

Historical Event

Year

Ref.

Field effect device concept First Si MOSFET First Si CMOS First oxidation study of SiGe First SiGe nMODFET First SiGe pMODFET First SiGe photodetector First SiGe SBD First SiGe hole RTD First SiGe BiCFET First SiGe gate CMOS technology First SiGe waveguide First SiGe pMOSFET First SiGe electron RTD First SiGe LED First SiGe solar cell First a-SiGe phototransistor First SiGe pMOSFET on SOI First strained Si pMOSFET First strained Si nMOSFET First SiGe:C pMOSFET First SiGe pFET on SOS First submicron strained Si MOSFET First vertical SiGe pFET First strained Si CMOS technology

1926 1960 1963 1971 1986 1986 1986 1988 1988 1989 1990 1990 1991 1991 1991 1992 1993 1993 1993 1994 1996 1997 1998 1998 2002

[68] [69] [70] [71] [72] [73] [74] [75] [76] [77] [78] [79] [80] [81] [82] [83] [84] [85] [86] [87] [88] [89] [90] [91] [92]

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also in 1991 (a busy year for our field). In 1992, the first a-SiGe solar cell was discussed [83], and in 1993, the first high-gain a-SiGe phototransistor [84]. The first SiGe pMOSFETs using alternate substrate materials were demonstrated, first in SOI in 1993 [85], and then on sapphire in 1997 [88], the first SiGe:C channel pMOSFET was demonstrated in 1996 [89], and the first vertical SiGe FET was published in 1998 [92]. Because of the desire to use Si-based bandgap engineering to improve not only the p-channel MOSFET, but also the n-channel MOSFET, research in the early- to mid-1990s in the FET field began to focus on strained Si MOSFETs on relaxed SiGe layers, with its consequent improvement in both electron and hole transport properties. This work culminated in the first strained Si pMOSFET in 1993 [87], and the first stained Si nMOSFET in 1994 [88], and remains an intensely active research field today. Key to the eventual success of strained Si CMOS approaches was that significant mobility enhancement could be achieved in both nFETs and pFETs down to very short (sub-micron) gate lengths, and this was first demonstrated in 1998 [90]. Strained Si CMOS at the 90-nm node and below is rapidly becoming mainstream for most serious CMOS companies, and the first commercial 90 nm strained Si CMOS technology platform was demonstrated by Intel in 2002 [91]. At last count, there were upwards of a halfdozen companies (e.g., Texas Instruments and IBM) also rapidly pushing toward 90 nm (and below) strained Si CMOS technologies, utilizing a variety of straining techniques, and thus it would appear that strained Si CMOS will be a mainstream IC technology in the near future, joining SiGe HBT BiCMOS technology. This is clearly outstanding news for our field. The merger of SiGe HBTs with strained Si CMOS would be a near-term logical extension.

References 1. R Braunstein, AR Moore, and F Herman. Intrinsic optical absorption in germanium–silicon alloys. Physical Review B 32:1405–1408, 1958. 2. HC Theuerer, JJ Kleimack, HH Loar, and H Christensen. Epitaxial diffused transistors. Proceedings of the IRE 48:1642–1643, 1960. 3. BA Joyce and RR Bradley. Epitaxial growth of silicon from the pyrolysis of monosilane on silicon substrates. Journal of the Electrochemical Society 110:1235–1240, 1963. 4. JH van der Merwe. Crystal interfaces. Part I. Semi-infinite crystals. Journal of Applied Physics 34:117–125, 1963. 5. JH van der Merwe. Crystal interfaces. Part II. Finite overgrowths. Journal of Applied Physics 34:123–127, 1963. 6. JW Matthews and AE Blakeslee. Defects in epitaxial multilayers: I. Misfit dislocations in layers. Journal of Crystal Growth 27:118–125, 1974. 7. E Kasper, HJ Herzog, and H Kibbel. A one-dimensional SiGe superlattice grown by UHV epitaxy. Journal of Applied Physics 8:1541–1548, 1975. 8. JC Bean, TT Sheng, LC Feldman, AT Fiory, and RT Lynch. Pseudomorphic growth of GexSi1x on silicon by molecular beam epitaxy. Applied Physics Letters 44:102–104, 1984. 9. R People and JC Bean. Calculation of critical layer thickness versus lattice mismatch for GexSi1x/Si strained layer heterostructures. Applied Physics Letters 47:322–324, 1985. 10. R People. Indirect bandgap of coherently strained Si1xGex bulk alloys on h0 0 1i silicon substrates. Physical Review B 32:1405–1408, 1985. 11. DV Lang, R People, JC Bean, and AM Sergent. Measurement of the bandgap of GexSi1x/Si strainedlayer heterostructures. Applied Physics Letters 47:1333–1335, 1985. 12. JF Gibbons, CM Gronet, and KE Williams. Limited reaction processing: silicon epitaxy. Applied Physics Letters 47:721–723, 1985. 13. G Abstreiter, H Brugger, T Wolf, H Joke, and HJ Kerzog. Strain-induced two-dimensional electron gas in selectively doped Si/SixGe1x superlattices. Physical Review 54:2441–2444, 1985. 14. BS Meyerson. Low-temperature silicon epitaxy by ultrahigh vacuum/chemical vapor deposition. Applied Physics Letters 48:797–799, 1986.

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15. R People and JC Bean. Band alignments of coherently strained GexSi1x/Si heterostructures on h0 0 1i GeySi1y substrates. Applied Physics Letters 48:538–540, 1986. 16. BS Meyerson, KJ Uram, and FK LeGoues. Cooperative phenomena is silicon/germanium low temperature epitaxy. Applied Physics Letters 53:2555–2557, 1988. 17. CA King, JL Hoyt, CM Gronet, JF Gibbons, MP Scott, and J Turner. Si/Si1x/Gex heterojunction bipolar transistors produced by limited reaction processing. IEEE Electron Device Letters 10:52–54, 1989. 18. TO Sedgwick, M Berkenbilt, and TS Kuan. Low-temperature selective epitaxial growth of silicon at atmospheric pressure. Applied Physics Letters 54:2689–2691, 1989. 19. PJ Wang, FF Fang, BS Meyerson, J Mocera, and B Parker. Two-dimensional hole gas in Si/Si0.85Ge0.15 modulation doped heterostructures. Applied Physics Letters 54:2701–2703, 1989. 20. P Agnello, TO Sedgwick, MS Goorsky, J Ott, TS Kuan, and G Scilla. Selective growth of silicon– germanium alloys by atmospheric-pressure chemical vapor deposition at low temperatures. Applied Physics Letters 59:1479–1481, 1991. 21. T Manku and A Nathan. Lattice mobility of holes in strained and unstrained Si1xGex alloys. IEEE Electron Device Letters 12:704–706, 1991. 22. T Manku and A Nathan. Electron drift mobility model for devices based on unstrained and coherently strained Si1xGex grown on h0 0 1i silicon subtrate. IEEE Transactions on Electron Devices 39:2082–2089, 1992. 23. K Erbel, SS Iyer, S Zollner, JC Tsang, and FK LeGoues. Growth and strain compensation effects in the ternary Si1xyGexCy alloy system. Applied Physics Letters 60:3033–3035, 1992. 24. HJ Osten, E Bugiel, and P Zaumseil. Growth of inverse tetragonal distorted SiGe layer on Si(0 0 1) by adding small amounts of carbon. Applied Physics Letters 64:3440–3442, 1994. 25. A Fischer, H-J Osten, and H Richter. An equilibrium model for buried SiGe strained layers. SolidState Electronics 44:869–873, 2000. 26. J Bardeen and WH Brattain. The transistor, a semi-conductor triode. Physical Review 71:230–231, 1947. 27. W Shockley, M Sparks, and GK Teal. p–n junction transistors. Physical Review 83:151–162, 1951. 28. M Tanenbaum and DE Thomas. Diffused emitter and base silicon transistors. Bell System Technical Journal 35:23–34, 1956. 29. See, for instance, W Shockley. U.S. Patents 2,502,488, 2,524,035, and 2,569,347. 30. H Kroemer. Zur theorie des diffusions und des drifttransistors. Part III. Archiv der Elektrischen Ubertragungstechnik 8:499–504, 1954. 31. H Kroemer. Quasielectric and quasimagnetic fields in nonuniform semiconductors. RCA Review 18:332–342, 1957. 32. H Kroemer. Theory of a wide-gap emitter for transistors. Proceedings of the IRE 45:1535–1537, 1957. 33. B Brar, GJ Sullivan, and PM Asbeck. Herb’s bipolar transistors. IEEE Transactions on Electron Devices 48:2473–2476, 2001. 34. RM Warner. Microelectronics: Its unusual origin and personality. IEEE Transactions on Electron Devices 48:2457–2467, 2001. 35. SS Iyer, GL Patton, SL Delage, S Tiwari, and JMC Stork. Silicon–germanium base heterojunction bipolar transistors by molecular beam epitaxy. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1987, pp. 874–876. 36. GL Patton, DL Harame, JMC Stork, BS Meyerson, GJ Scilla, and E Ganin. Graded-SiGe-base, polyemitter heterojunction bipolar transistors. IEEE Electron Device Letters 10:534–536, 1989. 37. GL Patton, JH Comfort, BS Meyerson, EF Crabbe´, E de Fre´sart, JMC Stork, JY-C Sun, DL Harame, and J Burghartz. 63-75 GHz fT SiGe-base heterojunction-bipolar technology. Technical Digest IEEE Symposium on VLSI Technology, Honolulu, 1990, pp. 49–50. 38. GL Patton, JH Comfort, BS Meyerson, EF Crabbe´, GJ Scilla, E de Fre´sart, JMC Stork, JY-C Sun, DL Harame, and J Burghartz. 75 GHz fT SiGe base heterojunction bipolar transistors. IEEE Electron Device Letters 11:171–173, 1990.

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39. JH Comfort, GL Patton, JD Cressler, W Lee, EF Crabbe´, BS Meyerson, JY-C Sun, JMC Stork, P-F Lu, JN Burghartz, J Warnock, K Kenkins, K-Y Toh, M D’Agostino, and G Scilla. Profile leverage in a selfaligned epitaxial Si or SiGe-base bipolar technology. Technical Digest IEEE International Electron Devices Meeting, Washington, 1990, pp. 21–24. 40. DL Harame, JMC Stork, BS Meyerson, EF Crabbe´, GL Patton, GJ Scilla, E de Fre´sart, AA Bright, C Stanis, AC Megdanis, MP Manny, EJ Petrillo, M Dimeo, RC Mclntosh, and KK Chan. SiGe-base PNP transistors fabrication with n-type UHV/CVD LTE in a ‘‘NO DT’’ process. Technical Digest IEEE Symposium on VLSI Technology, Honolulu, 1990, pp. 47–48. 41. EF Crabbee´, GL Patton, JMC Stork, BS Meyerson, and JY-C Sun. Low temperature operation of Si and SiGe bipolar transistors. Technical Digest IEEE International Electron Devices Meeting, Washington, 1990, pp. 17–20. 42. DL Harame, EF Crabbe´, JD Cressler, JH Comfort, JY-C Sun, SR Stiffler, E Kobeda, JN Burghartz, MM Gilbert, J Malinowski, and AJ Dally. A high-performance epitaxial SiGe-base ECL BiCMOS technology. Technical Digest IEEE International Electron Devices Meeting, Washington, 1992, pp. 19–22. 43. DL Harame, JMC Stork, BS Meyerson, KY-J Hsu, J Cotte, KA Jenkins, JD Cressler, P Restle, EF Crabbe´, S Subbanna, TE Tice, BW Scharf, and JA Yasaitis. Optimization of SiGe HBT technology for high speed analog and mixed-signal applications. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 1993, pp. 71–74. 44. E Kasper, A Gruhle, and H Kibbel. High speed SiGe-HBT with very low base sheet resistivity. Techncial Digest IEEE International Electron Devices Meeting, San Francisco, 1993, pp. 79–81. 45. EF Crabbe´, BS Meyerson, JMC Stork, and DL Harame. Vertical profile optimization of very high frequency epitaxial Si- and SiGe-base bipolar transistors. Technical Digest IEEE International Electron Devices Meeting, Washington, 1993, pp. 83–86. 46. DL Harame, K Schonenberg, M Gilbert, D Nguyen-Ngoc, J Malinowski, S-J Jeng, BS Meyerson, JD Cressler, R Groves, G Berg, K Tallman, K Stein, G Hueckel, C Kermarrec, T Tice, G Fitzgibbons, K Walter, D Colavito, T Houghton, N Greco, T Kebede, B Cunningham, S Subbanna, JH Comfort, and EF Crabbe´. A 200 mm SiGe-HBT technology for wireless and mixed-signal applications. Technical Digest IEEE International Electron Devices Meeting, Washington, 1994, pp. 437–440. 47. JD Cressler, EF Crabbe´, JH Comfort, JY-C Sun, and JMC Stork. An epitaxial emitter cap SiGebase bipolar technology for liquid nitrogen temperature operation. IEEE Electron Device Letters 15:472–474, 1994. 48. JA Babcock, JD Cressler, LS Vempati, SD Clark, RC Jaeger, and DL Harame. Ionizing radiation tolerance of high performance SiGe HBTs grown by UHV/CVD. IEEE Transactions on Nuclear Science 42:1558–1566, 1995. 49. LS Vempati, JD Cressler, RC Jaeger, and DL Harame. Low-frequency noise in UHV/CVD Si- and SiGe-base bipolar transistors. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minnneapolis, 1995, pp. 129–132. 50. L Lanzerotti, A St Amour, CW Liu, JC Sturm, JK Watanabe, and ND Theodore. Si/Si1xyGexCy /Si heterojunction bipolar transistors. IEEE Electron Device Letters 17:334–337, 1996. 51. A Schu¨ppen, S Gerlach, H Dietrich, D Wandrei, U Seiler, and U Ko¨nig. 1-W SiGe power HBTs for mobile communications. IEEE Microwave and Guided Wave Letters 6:341–343, 1996. 52. PA Potyraj, KJ Petrosky, KD Hobart, FJ Kub, and PE Thompson. A 230-Watt S-band SiGe heterojunction junction bipolar transistor. IEEE Transactions on Microwave Theory and Techniques 44:2392–2397, 1996. 53. K Washio, E Ohue, K Oda, M Tanabe, H Shimamoto, and T Onai. A selective-epitaxial SiGe HBT with SMI electrodes featuring 9.3-ps ECL-Gate Delay. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 1997, pp. 795–798. 54. HJ Osten, D Knoll, B Heinemann, H Ru¨cker, and B Tillack. Carbon doped SiGe heterojunction bipolar transistors for high frequency applications. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 109–116.

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55. SJ Jeng, B Jagannathan, J-S Rieh, J Johnson, KT Schonenberg, D Greenberg, A Stricker, H Chen, M Khater, D Ahlgren, G Freeman, K Stein, and S Subbanna. A 210-GHz fT SiGe HBT with nonself-aligned structure. IEEE Electron Device Letters 22:542–544, 2001. 56. JS Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, S-J Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. SiGe HBTs with cut-off frequency of 350 GHz.Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 771–774. 57. B El-Kareh, S Balster, W Leitz, P Steinmann, H Yasuda, M Corsi, K Dawoodi, C Dirnecker, P Foglietti, A Haeusler, P Menz, M Ramin, T Scharnagl, M Schiekofer, M Schober, U Schulz, L Swanson, D Tatman, M. Waitschull, JW Weijtmans, and C Willis. A 5V complementary SiGe BiCMOS technology for high-speed precision analog circuits. Proceedings of the IEEE Bipolar/ BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 211–214. 58. B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. 59. J Cai, M Kumar, M Steigerwalt, H Ko, K Schonenberg, K Stein, H Chen, K Jenkins, Q Ouyang, P Oldiges, and T Ning. Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 215–218. 60. J-S Rieh, D Greenberg, M Khater, KT Schonenberg, J-J Jeng, F Pagette, T Adam, A Chinthakindi, J Florkey, B Jagannathan, J Johnson, R Krishnasamy, D Sanderson, C Schnabel, P Smith, A Stricker, S Sweeney, K Vaed, T Yanagisawa, D Ahlgren, K Stein, and G Freeman. SiGe HBTs for millimeterwave applications with simultaneously optimized fT and fmax. Proceedings of the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Fort Worth, 2004, pp. 395–398. 61. DL Harame and BS Meyerson. The early history of IBM’s SiGe mixed signal technology. IEEE Transactions on Electron Devices 48:2555–2567, 2001. 62. T Tatsumi, H Hirayama, and N Aizaki. Si/Ge0.3Si0.7 heterojunction bipolar transistor made with Si molecular beam epitaxy. Applied Physics Letters 52:895–897, 1988. 63. H Temkin, JC Bean, A Antreasyan, and R Leibenguth. GexSi1x strained-layer heterostructure bipolar transistors. Applied Physics Letters 52:1089–1091, 1988. 64. D-X Xu, G-D Shen, M Willander, W-X Ni, and GV Hansson. n-Si/p-Si1x /n-Si double-heterojunction bipolar transistors. Applied Physics Letters 52:2239–2241, 1988. 65. GL Patton, SS Iyer, SL Delage, S Tiwari, and JMC Stork. Silicon–germanium-base heterojunction bipolar transistors by molecular beam epitaxy. IEEE Electron Device Letters 9:165–167, 1988. 66. A Gruhle, H Kibbel, U Ko¨nig, U Erben, and E Kasper. MBE-Grown Si/SiGe HBTs with high b, fT, and fmax. IEEE Electron Device Letters 13:206–208, 1992. 67. AJ Joseph, D Coolbaugh, D Harame, G Freeman, S Subbanna, M Doherty, J Dunn, C Dickey, D Greenberg, R Groves, M Meghelli, A Rylyakov, M Sorna, O Schreiber, D Herman, and T Tanji. 0.13 mm 210 GHz fT SiGe HBTs—expanding the horizons of SiGe BiCMOS. Technical Digest IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp. 180–182. 68. H Lilienfeld Patent, 1926; O. Heil, British patent number 439,457, 1935. 69. D Khang and MM Atalla. Silicon–silicon dioxide field induced surface devices. Solid State Research Conference, Pittsburgh, 1960. 70. FM Wanlass and CT Sah. Nanowatt logic using field-effect metal-oxide-semiconductor triodes (MOSTs). IEEE International Solid-State Circuits Conference, Philadelphia, 1963, pp. 32–33. 71. P Balk. Surface properties of oxidized germanium-doped silicon. Journal of the Electrochemical Society 118:494–495, 1971. 72. H Daembkes, H-J Herzog, H Jorke, H. Kibbel, and E Kasper. The n-channel SiGe/Si modulation doped field-effect transistor. IEEE Transactions on Electron Devices 33:633–638, 1986.

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73. TP Pearsall and JC Bean. Enhancement and depletion-mode p-channel GexSi1x modulation-doped field effect transistor. IEEE Electron Device Letters 7:308–310, 1986. 74. H Temkin, TP Pearsall, JC Bean, RA Logan, and S Luryi. GexSi1x strained-layer superlattice waveguide photodetectors operating near 1.3 mm. Applied Physics Letters 48:963–965, 1986. 75. RD Thompson, KN Tu, J Angillelo, S Delage, and SS Iyer. Interfacial reaction between Ni and MBE grown SiGe alloys. Journal of the Electrochemical Society 135:3161–3163, 1988. 76. HC Liu, D Landheer, M Buchmann, and DC Houghton. Resonant tunneling diode in the Si1xGex system. Applied Physics Letters 52:1809–1811, 1988. 77. RC Taft, JD Plummer, and SS Iyer. Demonstration of a p-channel BiCFET in the GexSi1x /Si system. IEEE Electron Device Letters 10:14 –16, 1989. 78. TJ King, JR Pfriester, JD Scott, JP McVittie, and KC Saraswat. A polycrystalline SiGe gate CMOS technology. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1990, pp. 253–256. 79. RA Soref, F Namavar, and JP Lorenzo. Optical waveguiding in a single-crystal layer of germanium– silicon grown on silicon. Optics Letters 15:270–272, 1990. 80. DK Nayak, JCS Woo, JS Park, KL Wang, and KP MacWilliams. Enhancement-mode quantum-well GexSi1x PMOS. IEEE Electron Device Letters 12:154–156, 1991. 81. K Ismail, BS Meyerson, and PJ Wang. Electron resonant tunneling in Si/SiGe double barrier diodes. Applied Physics Letters 59:973–975, 1991. 82. DC Houghton, JP Noel, and NL Rowell. Electroluminescence and photoluminesence from SiGe alloys grown on (1 0 0) silicon by MBE. Materials Science and Engineering B 9:237–244, 1991. 83. DS Chen, JP Conde, V Chu, S Aljishi, JZ Liu, and S Wagner. Amorphous silicon–germanium thinfilm photodetector array. IEEE Electron Device Letters 13:5–7, 1992. 84. S-B Hwang, YK Fang, K-H Chen, C-R Liu, J-D Hwang, and M-H Chou. An a-Si:H/a-Si, Ge:H bulk barrier phototransistor with a-SiC:H barrier enhancement layer for high-gain IR optical detector. IEEE Transactions on Electron Devices 40:721–726, 1993. 85. DK Nayak, JCS Woo, GK Yabiku, KP MacWilliams, JS Park, and KL Wang. High mobility GeSi PMOS on SIMOX. IEEE Electron Device Letters 14:520–522, 1993. 86. DK Nayak, JCS Woo, JS Park, KL Wang, and KP MacWilliams. High-mobility p-channel metal-oxide semiconductor field-effect transistor on strained Si. Applied Physics Letters 62:2853–2855, 1993. 87. J Welser, JL Hoyt, and JF Gibbons. Electron mobility enhancement in strained-Si n-type metal-oxide semiconductor field-effect transistors. IEEE Electron Device Letters 15:100–102, 1994. 88. SK Ray, S John, S Oswal, and SK Banerjee. Novel SiGeC channel heterojunction pMOSFET. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1996, pp. 261–264. 89. SJ Mathew, WE Ansley, WB Dubbelday, JD Cressler, JA Ott, JO Chu, PM Mooney, KL Vavanagh, BS Meyerson, and I Lagnado. Effect of Ge profile on the frequency response of a SiGe pFET on sapphire technology. Technical Digest of the IEEE Device Research Conference, Boulder, 1997, pp. 130–131. 90. K Rim, JL Hoyt, and JF Gibbons. Transconductance enhancement in deep submicron strained-Si n-MOSFETs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1998, pp. 707–710. 91. KC Liu, SK Ray, SK Oswal, and SK Banerjee. Si1xGex /Si vertical pMOSFET fabricated by Ge ion implantation. IEEE Electron Device Letters 19:13–15, 1998. 92. S Thompson, N. Anand, M Armstrong, C Auth, B Arcot, M Alavi, P Bai, J Bielefeld, R Bigwood, J Brandenburg, M Buehler, S Cea, V Chikarmane, C Choi, R Frankovic, T Ghani, G Glass, W Han, T Hoffmann, M Hussein, P Jacob, A Jain, C Jan, S Joshi, C Kenyon, J Klaus, S Klopcic, J Luce, Z Ma, B McIntyre, K Mistry, A Murthy, P Nguyen, H Pearson, T Sandford, R Schweinfurth, R Shaheed, S Sivakumar, M Taylor, B Tufts, C Wallace, P Wang, C Weber, and M Bohr. A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 mm2 SRAM Cell. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2002, pp. 61–64.

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93. VP Kesan, S Subbanna, PJ Restle, MJ Tejwani, JM Aitken, SS Iyer, and JA Ott. High performance 0.25 mm p-MOSFETs with silicon–germanium channels for 300 K and 77 K operation. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1991, pp. 25–28, 1991. 94. S Verdonckt-Vanderbroek, E Crabbe´, BS Meyerson, DL Harame, PJ Restle, JMC Stork, AC Megdanis, CL Stanis, AA Bright, GMW Kroesen, and AC Warren. High-mobility modulation-doped, graded SiGe-channel p-MOSFETs. IEEE Electron Device Letters 12:447–449, 1991. 95. S Verdonckt-Vanderbroek, E Crabbe´, BS Meyerson, DL Harame, PJ Restle, JMC Stork, and JB Johnson. SiGe-channel heterojunction p-MOSFETs. IEEE Transactions on Electron Devices 41:90–102, 1994.

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3 Overview: Fabrication of SiGe HBT BiCMOS Technology

John D. Cressler Georgia Institute of Technology

SiGe HBT BiCMOS technology is the obvious groundbreaker of the Si heterostructures application space and numerous commercial products exist around the world. At present count there are 25 þ SiGe HBT industrial fabrication facilities on line in 2005, and growing steadily. In fact, virtually every major player in the communications electronics market either (a) has SiGe up and running in-house, or (b) is using someone else’s SiGe fab as foundry for their designers. Clearly this field is maturing rapidly. Key to this success lies in the successful integration of the SiGe HBT and Si CMOS, with no loss of performance from either device. Chapter 4, ‘‘Device Structures and BiCMOS Integration Issues,’’ by D. Harame of IBM Microelectronics, discusses the various nuances of integration of HBTs with CMOS in SiGe fabrication. A recent demonstration of integrating a vertical SiGe HBT on thin film, CMOScompatible SOI substrates has generated considerable interest and is addressed in Chapter 5, ‘‘Fabricating SiGe HBTs on CMOS-Compatible SOI,’’ by J. Cai of IBM Research. For mixed-signal circuit applications of SiGe technology, the performance of integrated passive components is often just as important for circuit designers as the transistors, and significant strides have been made in the improvement of passives (and the requisite compact models for them) in recent years, and is reviewed in Chapter 6, ‘‘Passive Components,’’ by J.N. Burghartz of Delft University. A novel aspect of this handbook is that it contains numerous ‘‘snapshot’’ views of the industrial ‘‘state-of-the-art’’ for SiGe HBT BiCMOS technology, and is designed to provide the reader with a useful basis of comparison for the current status and future course of the global industry. These technology snapshots feature all the leaders of SiGe HBT BiCMOS field, including: Chapter 7, ‘‘Industry Examples at State-of-the-Art: IBM,’’ by A. Joseph of IBM; Chapter 8, ‘‘Industry Examples at State-of-the-Art: Jazz,’’ by P. Kempf of Jazz Semiconductor; Chapter 9, ‘‘Industry Examples at State-of-the-Art: Hitachi,’’ by K. Washio of Hitachi; Chapter 10, ‘‘Industry Examples at State-of-the-Art: Infineon,’’ by T. Meister of Infineon; Chapter 11, ‘‘Industry Examples at State-of-the-Art: IHP,’’ by D. Knoll of IHP; Chapter 12, ‘‘Industry Examples at State-of-the-Art: ST Microelectronics,’’ by A. Chantre of ST Microelectronics; Chapter 13, ‘‘Industry Examples at State-of-the-Art: Texas Instruments,’’ by B. El-Kareh of Texas Instruments; and Chapter 14, ‘‘Industry Examples at State-of-the-Art: Philips,’’ by R. Colclaser of Philips. In addition to this copious material, and the numerous references contained in each chapter, a number of review articles and books detailing SiGe HBT BiCMOS technology exist, including Refs. [1–11]. 3-1

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References 1. JD Cressler, DL Harame, JH Comfort, JMC Stork, BS Meyerson, and TE Tice. Silicon–germanium heterojunction bipolar technology: the next leap in silicon? Technical Digest of the IEEE International Solid-State Circuits Conference, San Francisco, 1994, pp. 24–27. 2. JD Cressler. Re-engineering silicon: Si–Ge heterojunction bipolar technology. IEEE Spectrum 49–55, 1995. 3. DL Harame, JH Comfort, JD Cressler, EF Crabbe´, JY-C Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part I—Materials, physics, and circuits. IEEE Transactions on Electron Devices 40:455–468, 1995. 4. DL Harame, JH Comfort, JD Cressler, EF Crabbe´, JY-C Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part II—Process integration and analog applications. IEEE Transactions on Electron Devices 40:469–482, 1995. 5. DL Harame. High-performance BiCMOS process integration: trends, issues, and future directions. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1997, pp. 36–43. 6. HJ Osten, D Knoll, B Heinemann, H Rucker, and B Tillack. Carbon-doped SiGe heterojunction bipolar transistors for high-frequency applications. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1990, pp. 109–116. 7. BS Meyerson. Silicon:germanium-based mixed-signal technology for optimization of wired and wireless telecommunications. IBM Journal of Research and Development 44:391–407, 2000. 8. A Gruhle. Prospects for 200 GHz on silicon with SiGe heterojunction bipolar transistors. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 19–25. 9. DL Harame, DC Ahlgren, DD Coolbaugh, JS Dunn, G Freeman, JD Gillis, RA Groves, GN Henderson, RA Johnson, AJ Joseph, S Subbanna, AM Victor, KM Watson, CS Webster, and PJ Zampardi. Current status and future trends of SiGe BiCMOS technology. IEEE Transactions on Electron Devices 48:2575–2594, 2001. 10. R Singh, DL Harame, and MM Oprysko. Silicon Germanium: Technology, Modeling, and Design. Piscataway, NJ: IEEE Press, 2004. 11. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003.

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4 Device Structures and BiCMOS Integration 4.1 4.2

Introduction......................................................................... 4-1 Types of HBT Structures .................................................... 4-1 Bipolar Structure Process Feature Tradeoffs . Bipolar Structure Examples

4.3 4.4 4.5

BiCMOS Integration Flows ................................................ 4-9 Challenges of Integrating HBTs with Advanced CMOS (<65 nm Lithography Nodes).............................. 4-11 Advanced HBT Structures and Scaling Limits ............... 4-11

4.6

Summary ............................................................................ 4-15

David L. Harame IBM Microelectronics

4.1

THz Performance Possibilities

Introduction

SiGe heterojunction bipolar transistors now have performance that rivals the III–Vs and in many cases is superior to them. This technology has grown to be a pervasive technology found in many products, not solely because of the performance, but primarily because it is realized as a BiCMOS technology such that very highly integrated product designs are possible by leveraging a base CMOS technology, which already has existing libraries and intellectual property (IP). Additionally, passives and extensive RF– analog enablement are also added to make custom designs possible that can be merged with the highly integrated digital CMOS section. This combination of the performance of the HBT with all the large digital integration capability is based on having the HBT structure and process fully integrated into the base CMOS process such that it guarantees the compatibility of the HBT and CMOS. This will be the central theme of this section on device structures and BiCMOS integration. The structures will always be seen as within the context of a BiCMOS process. This chapter will begin with a review of the structures that are used in SiGe heterojunction bipolar transistors broadly breaking them up into different types. This will include an extensive section on transistor features, which will emphasize that what the final device looks like is a combination of the bipolar structure and the intended applications. It will then review BiCMOS integration flows followed by a section on the issues in integrating SiGe HBTs into advanced CMOS processes. The chapter will conclude by looking at the performance limits and what very advanced HBT structures might look like.

4.2

Types of HBT Structures

Bipolar transistor structures can be roughly divided into non-self-aligned and self-aligned structures. A self-aligned transistor structure implies that the extrinsic base region is self-aligned to the emitter opening during the bipolar structure’s fabrication process. Note that this is a fairly limited definition, albeit an important one, considering all of the parts of the final transistor structure. Self-alignment is accomplished by the formation of an outer or inner sidewall, which enables us to make a second broad 4-1

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division of structures. Non-self-aligned structures imply that a lithographic alignment tolerance is used for the alignment as opposed to a processing feature during the formation of the structure. Another broad classification seeks to break structures into a combined performance and cost division. This division classes structures into high performance (HP) versus cost performance (CP). The concept is that for the HP set of applications, performance is everything and time to market is critical, making the cost considerations secondary. In contrast, the CP set of applications are commodity cost-sensitive applications where cost is everything and the required peak performance levels are significantly reduced. The CP applications will typically use older lithography generations. Of course, the HP and CP division is much more ambiguously defined when it comes to particular processes, since the features in a process flow are determined by the intended application that may be a mix of requirements. Nevertheless, it is interesting to understand the features and their tradeoffs while arbitrarily assigning them a HP or a CP classification. After the features are discussed, in light of either a HP or CP element, several example NSA and SA processes will be discussed in detail.

Bipolar Structure Process Feature Tradeoffs Some examples of the more typical features and tradeoffs are listed in Table 4.1 and several of these examples will be discussed in some detail here, with others addressed throughout this chapter. Issues and limitations of the different features will be discussed in this section. Selection of the starting wafer is a tradeoff. Substrate resistivity has a large impact on microstrip lines and inductors as described in detail by Long and Copeland [1]. Silicon transitions through skin effect, to slow wave, to quasi-TEM propagation modes as the resistivity is changed from low (0.01 ohm-cm) to high (50 ohm-cm) resistivity material as shown in Figure 4.1. Inductors fabricated on higher resistivity material have higher inductor Q values because of less power dissipation in the substrate [1]. However, high-resistivity wafers may be more susceptible to processing issues (warping during high-thermal steps) and the CMOS may

TABLE 4.1

Structural Processing Features of SiGe Heterojunction Bipolar Transistors

Process Feature

High Performance

Cost Performance

Wafer Subcollector

High resistivity Nþ subcollector implant followed by n-epitaxy growth. Lowest sheet resistance Deep trench. Best isolation

Same as base CMOS Implanted subcollector without n-epitaxy. Lower cost but higher sheet resistance Junction isolation. Larger transistor layout, less isolation Same as CMOS No additional layers added to the process. Must address all etch steps to not damage the NPN region Nonselective. Structure dependent. Simpler

Transistor isolation Shallow trench NPN protection layer

Epitaxy

Extrinsic base

Same as CMOS Additional layer designed to protect the NPN region during CMOS processing and prior to epi-base. Increases process margin Selective. Structure dependent. Requires close attention to process to maintain high selectivity. Susceptible to nonuniform growth in different areas and density regions Raised extrinsic base. Less like a CMOS transistor. Requires more special steps. Higher performance

Polyemitter

In situ doped. More complex. Fewer small emitter structure issues

Contacts

Separate emitter contact. Structure dependent to make it less susceptible to height differences.

Features are categorized as a high-performance or cost-performance feature.

Implanted extrinsic base. Can be SA or NSA processes. Simplest approach but results in a deeper extrinsic base Implanted emitter. Simpler. May be susceptible to small emitter nonuniform dopant distribution issues CMOS contact. Simpler. With topography differences with CMOS less process margin

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Metal SiO2

1011 SKIN EFFECT

Si

QUASI-TEM

1010

Frequency, in Hz

Electric field distribution

Ground plane Quasi-TEM mode

Digital CMOS

tsi = 350 µm tox = 5 µm

Si bipolar and RF CMOS

tsi = 350 µm tOX = 2 µm

109

tsi = 200 µm tOX = 5 µm 108

Slow-wave

Slow-wave mode 107 10−2

Skin-effect mode

10−1

100

101

102

Silicon resistivity, in Ω-cm

103

Frequency-resistivity mode chart for parallel plate waveguide

FIGURE 4.1 Propagation modes in silicon as a function of silicon resistivity and frequency. (J.R. Long, personal communication.)

have significant deltas from the base CMOS latch-up and ESD specifications. A more conservative flow is to select the starting wafer resistivity to be compatible with the base CMOS process or just slightly higher with a typical number around 10 ohm-cm. The formation of the subcollector involves another tradeoff. For the lowest subcollector resistance, a low resistivity buried subcollector is desirable. In this process a high-dose arsenic implant is followed by a long thermal cycle in an oxidizing ambient to drive the arsenic diffusion deep into the wafer and anneal out defects, which is then followed by a thin n-epitaxy layer grown at high temperatures. A buried subcollector process can achieve sheet resistances below 10 ohm/sq. The alternative process is to simply implant the subcollector more like a well implant in CMOS. This has the advantage that it is simpler and allows the starting wafer to be fully compatible with the CMOS process as opposed to adding the n-epitaxy layer to the CMOS regions. The disadvantage is that to avoid defects, the dose and depth of the subcollector implant is significantly less than that of a buried subcollector so that the sheet resistance may be as much as ten times higher than that for a buried subcollector. Reducing sheet resistance and defect density remains a concern for CP sub-collector processes. Transistor isolation is another process feature that is a tradeoff. The best isolation is created by a deep trench (6.0 mm), which is filled with a thick oxide liner and undoped polysilicon. The transistor-totransistor breakdown voltage may easily exceed 50 V. A simpler process is to use junction isolation taking advantage of other implants in the process. The interesting aspect is that it uses no additional steps but the drawback is much reduced isolation voltages and significantly larger transistor-to-transistor spacing is required. In designs with reduced bipolar transistor count density may not be an important issue and the junction isolation may easily provide adequate isolation. The combination of a deep trench and a buried sub-collector leads to reduced collector capacitance (CSC) and collector resistance (RC) parasitics and therefore the highest fT and fMAX values. The next feature is the NPN protection layer which is a layer used in the Base-after-Gate (BaG) integration flow [2] to protect the NPN regions from CMOS processing damage (Figure 4.2). This flow will be discussed in a later section of this article but for the moment all that is needed to know is that after the gate polysilicon is etched away from the active NPN area, the SiGe base is grown over that region of silicon. In modern CMOS processes, the gate oxide continues to shrink and is now on the order of 2.0 nm in 90 nm CMOS. The polysilicon gate etch must stop on that thin layer, but with thin gate oxides the silicon is often damaged. In a CMOS process this region will become heavily doped and

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Bipolar before CMOS (base before gate)

FIGURE 4.2

page 4

Bipolar after CMOS (base after gate)

Isolation

Isolation

Bipolar

CMOS

CMOS

Bipolar

Contacts and interconnects

Contacts and interconnects

Bipolar during CMOS (base during gate) Isolation

Bipolar and CMOS

Contacts and interconnects

Three simple BiCMOS process flows.

silicides formed so that the condition of the silicon surface is not such an issue. However, in a HBT process in which the intrinsic base is grown over that region, any damage in the underlying silicon will result in defects during epi growth and subsequent poor SiGe HBT yield. This damage can be prevented by adding a dielectric layer to protect the region during the gate etch. The use of this layer is based on a decision to select a larger process margin for a noncritical additional processing step, but it will add additional steps to the process. The next process feature is the SiGe epitaxy process used to grow the base layer. The three most commonly used techniques available to grow the SiGe base layer are MBE, UHV/CVD [3,4], and APCVD or RPCVD [5,6]. MBE [7] was used initially but is no longer used in production so we will not focus on it here. The fundamental problem in SiGe epitaxy is the removal of the native oxide layer and each of these three techniques addresses this in different ways. In UHV/CVD epitaxy prior to epitaxial deposition, the wafer is exposed to a HF treatment which removes all of the native oxide and forms a hydrogen-passivated layer that is maintained throughout the epitaxial growth. In APVCVD or RPCVD, the wafer is baked at a high temperature in the presence of a hydrogen flow, which desorbs the oxide layer. Selective deposition is possible with both AP or RPCVD [6] and UHVCVD but UHVCVD is usually used as a nonselective process. A concern with AP or RPCVD selective growth is the sensitivity to local pattern (area) densities, which can affect the growth rate by as much as 50% depending on the conditions [8]. All CVD techniques are capable of in situ doping using phosphorus for n-dopants and boron for p-dopants (boron) and incorporating Ge and carbon [9]. A detailed comparison between UHV/CVD and AP or RPCVD may be found in Ref. [10]. Another interesting feature is that of raised extrinsic base versus a simpler nonraised extrinsic base. A raised extrinsic base is a processing feature that requires a separate deposition of heavily doped material either before or after the intrinsic base layer is formed. The idea was advanced early in the development of epitaxial base development [11–13], and one might also argue that it is a part of the selective epitaxial base structure, which we will go over in detail. The advantages are lower base–collector capacitance and base resistance but at a cost of more complexity than a simple planar ion-implanted extrinsic base structure. This completes the review of features and tradeoffs commonly used in bipolar structures. In the next section we will explore three bipolar structures illustrating the use of these features.

Bipolar Structure Examples This section will focus on three structural examples, which will describe the three basic classes of structures: (1) non-self-aligned epitaxial base transistor, (2) self-aligned epitaxial base transistor with an inner sidewall, and (3) self-aligned using an outside sidewall. We will then look at the impact of advanced CMOS structures and the impact on BiCMOS integration and conclude with a section on advanced bipolar structures within the context of the new CMOS processes.

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Non-Self-Aligned Bipolar Transistor Structure This structure is the simplest epitaxial base bipolar structure and usually simpler processes are most widely used. It is often referred to as a quasi-self-aligned transistor structure and is essentially the same structure that has been used widely in implanted base BiCMOS integration processes [14]. An SEM of the structure to be built through a series of cross sections is shown in Figure 4.3. The process begins with the formation of the buried layer into a CMOS compatible P substrate by patterning an arsenic implant (Figure 4.4a). The buried layer implant is followed by a high-temperature anneal in an oxidizing implant to drive the implant deep into the silicon and consume the damaged silicon layer. This is followed by the growth of a very lightly doped n-epitaxial layer, which is traditionally grown at high temperature (Figure 4.4b). The base CMOS process now begins with the formation of shallow trench by depositing a nitride layer, patterning and etching the nitride and silicon (Figure 4.4c), followed by a deposition of oxide and planarization (Figure 4.4d) and subsequent nitride strip. The shallow trench is followed by the ‘‘reachthru’’ implant, which is a high-dose implant to form a low-resistance-doped region contacting the buried layer from the surface (Figure 4.4e). Typically this is a high-dose phosphorus implant, which is able to diffuse down to the buried arsenic layer under a moderate heat cycle. This example process has a BaG integration and benefits from the formation of a protect layer. The protect dielectric layer is deposited, patterned, and etched everywhere but over the regions where high-quality single intrinsic base growth is required (Figure 4.4f). After the CMOS structural process is completed a patterning and etch step remove the bipolar protect layer from the active base region and this same step may serve as an implant block mask for a collector implant to save a masking level (Figure 4.4g). In the next step the nonselective intrinsic in situ doped SiGe(C) layer is grown (Figure 4.4h). Single crystal material is grown in the region of exposed silicon and polysilicon over any regions where dielectrics are exposed. The polysilicon growth outside the active region serves as a landing pad for the metal contacts as can be seen in the SEM micrograph in Figure 4.3. A high-quality emitter base dielectric is formed by oxidation, which is followed by the deposition of thicker dielectrics. The emitter opening is formed by a patterning and etch step (Figure 4.4i). The alignment is to the shallow trench level. Next, the emitter polysilicon is deposited, doped, capped with a dielectric layer, patterned and etched (Figure 4.4j). The alignment of the level is also to the shallow trench level, which makes the alignment second order with respect to the emitter opening. The three sigma total overlay we must allow for is given by OLTotal ¼ WC þ

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ TOL2NP þ TOL2EM þ TOL2NP-ST þ TOL2EM-ST

(4:1)

where WC is the worst case overlay of NP-EM allowed by the process, OL are overlays and TOL are tolerances of the process. The extrinsic base is then implanted using the emitter polylayer as a mask for

FIGURE 4.3

SEM micrograph of a non-self-aligned SiGe HBT.

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(a) Implant subcollector

(h) After LTE EPI and base dielectric deposition

(b) Grow n- collector epitaxial layer

(c) Define and etch shallow trench

(j) Etch NPN emitter poly and emitter films

(d) After trench planarization and pad nitride strip

(e) Implant NPN reachthrough

(k) Implant extrinsic base

(f) Pattern and etch NPN protect film

(l) Etch NPN base poly

(g) Etch base opening; implant deep pedestal

(m) After TiSix Formation

FIGURE 4.4

Fabrication sequence of a simple NSA epitaxial base transistor broken in 13 steps.

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the extrinsic base implant (Figure 4.4k). The extrinsic base layer is then patterned and etched (Figure 4.4l). A dielectric deposition and etch forms a sidewall on both the emitter polysilicon and the base polysilicon layer. CMOS implants, an RTA anneal, and Ti silicide formation complete the front end of the line process. Self-Aligned Bipolar Transistor Structure with an Inner Sidewall One of the most common implanted structures used in bipolar technology is the double polysilicon self-aligned (DPSA) implanted transistor structure [15] shown in Figure 4.5. This transistor structure has been successfully integrated into many production BiCMOS integration flows. The major drawback of the DPSA structure was the difficulty in maintaining a narrow base with an implanted base process. A suggested process improvement was to incorporate an epitaxial base in place of the implanted base process. The most straightforward way to do this was to substitute an epitaxial growth for the intrinsic base implant just prior to formation of the inner sidewall. A two-step sequence using the same basic structure as the double polysilicon structure is shown in Figure 4.6a and b [16]. This approach was successful in achieving a narrower heavily doped base than an implanted base process, but required higher thermal cycles for the preclean and growth with diffused base limiting the scalabilty of the method. With time, this general approach was significantly improved by adding a pad oxide under the extrinsic base and incorporating a selective SiGe base. The process steps are

Inner sidewalls

P+ polysilicon P+ I/I Intrinsic base

FIGURE 4.5

Double polysilicon self-aligned transistor structure.

Selectively grown epitaxial base Dielectric P+ polysilicon P+ ST (a) DPSA after epi base Inner sidewalls

Selectively grown epitaxial base

Dielectric P+ Polysilicon P+ ST Deposited + diffused intrinsic base (b) DPSA after sidewall

FIGURE 4.6

Double polysilicon with epitaxial base.

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Dielectric

Pad dielectric

P+ polysilicon Dielectric

ST (a) DPSA with Pad oxide Inner sidewalls

Pad dielectric after HF dip

Dielectric P+ polysilicon Dielectric

ST (b) After SW and HF dip Selective SiGe epitaxial base Dielectric

Voids

P+ polysilicon

ST (c) After selective SiGe epitaxial growth

FIGURE 4.7

DPSA with pad oxide and selective SiGe epitaxial base deposition.

shown in Figure 4.7a–c. Note that the pad oxide lies under the extrinsic base doped polysilicon, preventing the diffusion of the extrinsic base during the epitaxial base prebake and it restricts the area so that the base–collector capacitance is significantly reduced. A disadvantage of this structure is that the HF dip contributes some variability to the underlap under the Pþ polysilicon—therefore variability in the base resistance, and the structure has significant topography so its narrow emitter effects are a concern. The selective SiGe epitaxial growth is subject to area and local pattern density-loading effects, which can significantly change local growth rate (as much as 50% depending on the conditions) and the wafer emissivity (important for lamp-heated selective SiGe reactors) is dependent on the mask pattern. In spite of these difficulties, the structure does optimize fMAX effectively by greatly decreasing CBC. Self-Aligned Bipolar Transistor Structure with an Outer Sidewall An alternative family of structures to those with an inner sidewall, are those which form the extrinsic base by the use of an outer sidewall on a sacrificial structure (referred to as a pedestal). An advantage of these structures is that the growth and deposition are nonselective and the structures have low topography, the two properties which help with manufacturing control. A process for such a bipolar structure is shown in Figure 4.8a–g [17,18]. A key aspect of the process is the formation of a pedestal of sacrificial material on which sidewalls are formed to self align the extrinsic base to the emitter opening. The process begins after the nonselective in situ doped SiGe(C) base is grown. A series of films are deposited (Figure 4.8a) and the top two layers are patterned and etched to form a ‘‘sacrificial pedestal’’ (Figure 4.8b). A dielectric sidewall is formed on the ‘‘sacrificial pedestal’’ (Figure 4.8c) and the extrinsic base is implanted (Figure 4.8d) through the remaining films except where the ‘‘pedestal’’ and sidewall block the implant. The dielectrics are removed leaving

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only the patterned pad nitride and the polysilicon layer exposed on the surface of the wafer. Next, the polysilicon is oxidized everywhere except under the pad nitride. The oxidation of polysilicon is pinned near the LOCOS (Figure 4.8e) nitride edge due to large compressive stress during field oxidation. The mechanism is the same as that in the well-understood poly-buffered-LOCOS (PBL) approach to forming a field oxide [19]. Next, the PBL nitride pad and underlying polysilicon are stripped and the remaining dielectric etched (Figure 4.8f) followed by the deposition, doping, patterning, and etching of the emitter polysilicon (Figure 4.8g). This completes the bipolar process-specific portion of the fabrication sequence, silicidation of the extrinsic base polysilicon and collector contact and contacts using the CMOS portions of the process. An SEM of a 0.18 mm SiGe HBT fabricated with this process is shown in Figure 4.9 [20].

4.3

BiCMOS Integration Flows

The previous section gave a detailed process description of three different bipolar structures. Each of these structures can be fabricated together with CMOS in a BiCMOS process. The objective of BiCMOS process integration is to create a final process with CMOS characteristics unchanged from the original CMOS only process and bipolar performance matching the bipolar only process. BiCMOS process integration flows separate out into three cases, which are shown in Figure 4.2. The first process flow is that of base-beforegate (BbG). In this case, the bipolar is structurally formed completely before the CMOS and then covered up or protected during the CMOS processing. The disadvantage of this flow is that the thermal cycles of CMOS are much higher than the bipolar and therefore would tend to diffuse and widen the intrinsic base profile. The second technique is Base after Gate (BaG) [2]. In this approach the CMOS is completely

Dielectric

Polysilicon

Nitride

Dielectric

Nonselective SiGe epitaxial base

ST

(a) Nonselective SiGe epitaxial base and layer depositions Polysilicon

Dielectric Nitride

Patterned and etched sacrificial-emitter-pedestal

Nonselective SiGe base

ST (b) Pattern and etch a sacrificial-emitter-pedestal using the top two layers Outer sidewalls

Nonselective SiGe base

ST (c) Deposit dielectric and etch back to form an outer sidewall on the sacrificial-emitter-pedestal

FIGURE 4.8

Self-aligned SiGe epitaxial base bipolar structure using an outer sidewall to self-align the extrinsic base. (Continued)

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Extrinsic base implant

Nonselective SiGe base

P+

P+ ST

(d) Extrinsic implant using boron which is self aligned to the emitter opening by the outer sidewall Oxide Nonselective SiGe base

P+

P+ ST

(e) Oxidation of the sacrificial polysilicon layer exposed in the field area but not underneath the nitride using the LOCOS effect, i.e., the polysilicon underneath the pad nitride is not oxidized Emitter Opening Nonselective SiGe base

P+

P+ ST

(f) Uncover emitter opening by selective removal of the nitride, polysilicon, and finally bottom dielectric layer. Note P+ implant is self-aligned to the emitter opening Emitter Polysilicon N+ Nonselective SiGe base

P+

P+ ST

(g) Emitter-polysilicon deposition, doping, and patterning. Note that with lower topography there is reduced narrow emitter effects.

FIGURE 4.8

(Continued )

Collector

Base

Emitter SiGe Base

N+ subcollector

FIGURE 4.9

SEM micrograph of a 0.18 mm SiGe BiCMOS HBT.

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formed and then covered up for protection during the bipolar processing and therefore the higher thermal cycles of the CMOS are completed prior to the deposition of the intrinsic base and the formation of the bipolar structure. This is the dominant integration technique in modern BiCMOS technologies. The last integration flow is base during gate. In this approach the bipolar and CMOS layers and thermal cycles are shared [17,18]. This approach was practiced in the 0.5 mm lithographic generation [21] but as CMOS became more complex there was a need to decouple the thermal cycles.

4.4 Challenges of Integrating HBTs with Advanced CMOS (<65 nm Lithography Nodes) There are many challenges in integrating a SiGe HBT into an advanced CMOS process and this section will discuss some of these after first reviewing some key aspects about advanced CMOS processes. To improve the performance of CMOS generation to generation a selective scaling methodology is used. In selective scaling, the gate length is aggressively scaled with reduced scaling of the oxide thickness and power supply voltage [22]. However, in 65 nm and beyond even selective scaling is challenged as standby power and dynamic power become equivalent and FET performance is not dramatically increasing. The new approach requires a combination of material and structural innovation as well as a scaling algorithm. These innovations have led to the introduction of strain to increase electron and hole mobilities [23–25] and novel structures like FINFETS [26]. Both strain and structural innovations (e.g. FINFETS) have been implemented on SOI and in bulk silicon. The incorporation of one or more of these approaches in a BiCMOS process will complicate integration of the SiGe HBT and modify the SiGe HBT device performance. Two commonly used approaches to introduce strain to improve FET mobility are SiGe buffer layers and post-FET structure film depositions. Buffer layers will have a drastic effect on process integration with CMOS [27], especially if the bipolar is fabricated in these strained Si and relaxed Si1x Gex layers. Given the high defect densities that currently exist in these films, there will be a major impact on transistor yield. There are limited available publications on this interesting question so it is bound to be a major research topic in the future. Less drastic process alternatives to introduce strain is through the use of a tensile nitride deposition after the completion of the front-end processing and just prior to interconnect formation [25]. Liu has published the effects of compressive and tensile strain (0.28%) on SiGe HBT and Si BJT controls. Compressive strain showed an increase in IC and current gain (þ4%) while tensile strain showed a decrease (4% to 6%) in IC and current gain [28] although this has not been studied in depth. The effects were indeed found to be minor for DC characteristics. Additionally, FinFETs and double-gate structures introduce a novel way to fabricate CMOS devices, which may well be used in future CMOS technologies. In a BaG BiCMOS integration flow FINFET processes will probably not have an impact on the Bipolar formation as far as thermal cycles are concerned, but may introduce integration difficulties due to the extreme topography of these structures. SOI technology has also emerged as an important technology for high-speed processing and it is interesting to see the possibilities of integrating HBTs with SOI. Most approaches to integrate bipolar with the SOI have centered on creating lateral [29,30] or novel vertical bipolar structures to take advantage of the SOI technology features or more conservative approaches, which utilized thicker silicon on SOI than is available in conventional logic SOI technologies [31]. Cai successfully integrated a SiGe HBT on SOI [32] and achieved an fT and fMAX of 70 GHz at a 20 V substrate bias. At 0 substrate bias the fT and fMAX was 30 and 45 GHz, respectively. Integration of HBTs with SOI is promising but much work remains to be done.

4.5

Advanced HBT Structures and Scaling Limits

Scaling in bipolar technologies involves a combination of vertical and lateral scaling. In vertical scaling the total transit time is reduced by reducing each of the component transit times. The expression for the

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total transit time is given in Equation 4.2 to Equation 4.4. In the case of graded SiGe base HBTs, the base is scaled by shrinking the base width WB and increasing the slope of the Ge across the base, which often includes increasing the peak Ge% [33]. If all doped regions are thinned the transit times may decrease but the RC time constants will increase due to increased resistances. Therefore, innovation is required with vertical scaling to simultaneously reduce the thicknesses in the structure, area of the capacitances, and resistances

tEC

1 ¼ tEC ¼ tC þ tB þ t CSCL 2pfT 2 kT kT WB WB WCSCL þ ¼ CEB þ þ RC þ RE CCB þ g þ qIC qIC Dn VEXIT 2nSAT kT kt DE g¼ 1 [1 e g;GeðgradeÞ=kT ] DEg;GeðgradeÞ DEg;GeðgradeÞ

(4:2) (4:3) (4:4)

In the case of the in situ doped SiGe base the introduction of carbon and the retarding effects on boron diffusion from high-concentration Ge have enabled the sheet resistance of the intrinsic base layer to decrease generation to generation. Fortunately, the epitaxial technology is very advanced today and it is routine to deposit and control very thin SiGe(C) layers. To achieve a higher fT value it is apparent from Equation 4.3 that the charging current (IC) must be increased, which means that the Kirk effect must be pushed out to higher current densities. This is accomplished by increasing the collector dopant concentration, usually by an increase in the siliconimplanted collector or SIC, which increases IC and decreases both RC and WCSCL. However, increasing the SIC implant causes more lateral and vertical diffusion, which increases the base–collector capacitance (CCB). The base–collector capacitance is an important term in advanced structures and it indicates an interaction of lateral and vertical scaling that must be carefully controlled to improve the fMAX as well as fT. A schematic cross section of an idealized bipolar shown in Figure 4.10 illustrates some of the key parasitics that may be reduced by lateral scaling. To first order, lateral scaling is shrinking all the dimensions and overlaps, which will significantly improve the capacitances and resistances by minimizing

RBSP

RBSU

R BSX RBSSL

Emitter polysilicon C BENP CBEP

CCBOL

CBEA CCBI

Pedestal (SIC)

Base polysilicon Shallow trench

CCBX CCBPB

Subcollector

FIGURE 4.10

Cross section through an idealized bipolar transistor showing the key later parasitics.

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the area and distances that current must flow through resistive layers. There are cases in which the shrinking dimensions may cause increased parasitics. For instance, decreasing the trench width increases the perimeter collector to substrate capacitance. Therefore, this dimension is not scaled generation to generation. In another case, decreasing the distance between the SIC implant and the extrinsic base implant will increase the overlap and increase the overlap capacitance CCBOL (see Figure 4.10). This component can be a large part of the delay so it must be decreased. The only way to do this is by structural innovation that has resulted in raised extrinsic base structures in which the implant into the silicon is removed to greatly decease the diffusion into the SIC layer (Figure 4.11) [33].

THz Performance Possibilities Having reviewed vertical and lateral scaling let us consider what type of future structures would be required to achieve an fT of 1 THz (total transit time <160 fsec or <40 fsec for tE, tB, tC, tCSCL, respectively). An important assumption is that parasitics, which can be addressed by geometrical scaling, will not be dominant delay components because they can be reduced with clever structural innovations and lithography shrinks. Solutions to THz performance will be found by using the scaling methodology discussed above and methodically addressing each delay component. The emitter delay (tE) component given by Equation 4.5 can be addressed by aggressively scaling the emitter area, i.e., emitter width, and therefore CBE. This component will not be a dominant delay component since the emitter width can be relatively easily scaled [34,35]. Concerns exist about the high current densities but by scaling the shrinkage of the emitter width to 1/(peak fT current density) many of these concerns are mitigated [36]. The base delay (tB) component can be addressed by continuing to shrink the vertical profile using a

Overlap N+ Poly

W Stud contact

Silicide SiGe

N+

DT

STI

SIC

STI

DT

N+ Subcollector P substrate

WE Shallow junction

Raised extrinsic base

STI N+

SIC

N+ Subcollector DT P substrate

FIGURE 4.11

Selective scaling in bipolar transistors.

DT

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combination of reduced thermal cycle and increased Ge and C content. Base transit time is limited by transit across the neutral base and the ability of carriers to exit the base at the base–collector space charge region [37]. A graph of these two components versus base width shown in Figure 4.12 indicates that at a neutral base width of 80 nm the transit time is less than 40 fsec. Because of the atomic layer control that SiGe epitaxy has [38], achieving neutral base widths of 8 nm is possible. The collector delay (tC) component, given by Equation 4.7, is the most complex and will be very challenging. Assuming we can use geometry, and clever structural device design, the CBC term can be reduced by scaling the active collector–base capacitance area and using structures like the raised extrinsic base to reduce the collector– base capacitance per unit area. The most critical area is the overlap between the extrinsic base diffusion and the SIC collector implant. Typically for vertical scaling, the collector doping is increased which increases the current (IC) and pushes out the Kirk effect. This also reduces RC. Structural innovation will also have to occur to continue reducing the emitter and collector resistance. These are difficult challenges but may be possible. And finally the last term to consider is the transit time through the collector–base space charge region given by Equation 4.8. This delay component is becoming a significant impediment to vertical scaling. The high-field mobility is a material property and not easily influenced by the process. Therefore, unless there are dramatic changes with a migration to new materials constants this may prove to be the limit to performance kT CBE q IC 2 kT Wb Wb þ tB ¼ DEGe Dn nexit kT t C ¼ RE þ RC þ CBC qIC tE ¼

t CSCL ¼

tB = ∆Eg,Ge kT

2 T 2b kT − T b kT D n ∆EGe D n ∆EGe

Dn ≈ 10

>5

cm2

s−1

nexit ≈

2

(4:6) (4:7)

WCSCL 2nSAT

1−e−∆EGe /kT

1.0⫻107

(4:5)

cm

+

(4:8)

Tb nexit

kT ∆E Ge

1−e−∆EGe /kT t B ≈ kT ∆E Ge

s−1

T b2 Dn

+

300 Total

Delay Time (fsec)

250

Correction 200

Diffusion

150 100 50 0 0

50

100

150

200

250

Neutral Base Width (Angstroms)

FIGURE 4.12

Base transit delay time components as a function of neutral base width.

300

Tb nexit

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4-15

Summary

There are many interesting bipolar structures that can be classed into three groups, non-self-aligned, self-aligned using an inner sidewall technique, and self-aligned using an outer sidewall. The BaG process integration flow is the most commonly used approach since it decouples the CMOS and bipolar thermal cycles. A challenge for the future will be the integration into advanced CMOS processes, which use mobility enhancement by strain techniques. SiGe HBTs will continue to improve in performance moving closer to 1 THz peak fT values. To achieve these values substantial material modifications of the SiGe HBTs and significant structural innovation will be required.

Acknowledgment The author would like to thank all the individuals at IBM who have contributed to SiGe HBT technology to make this work possible, as well as A. Joseph, J.-S. Rieh, J. Johnson, G. Freeman, and J. Dunn, for many helpful discussions about this work.

References 1. JR Long and MA Copeland. The modeling, characterization, and design of monolithic inductors for silicon RF IC’s. IEEE J Solid-State Circ 32(3):357–369, 1997. 2. SA St. Onge, DL Harame, JS Dunn, S Subbanna, DC Ahlgren, G Freeman, B Jagannathan, J Jeng, K Schonenberg, K Stein, R Groves, D Coolbaugh, N Feilchenfeld, P Geiss, M Gordon, P Gray, D Hershberger, S Kilpatrick, and S Johns. A 0.24 mm SiGe BiCMOS mixed-signal RF production technology featuring a 47 GHz fT HBT and 0.18 mm LEFF CMOS. Proceedings of the Bipolar/ BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 117–120. 3. BS Meyerson, F Himpsel, and KJ Uram. Bistable conditions for low temperature silicon epitaxy. Appl Phys Lett 57:1034–1036, 1990. 4. BS Meyerson. Low temperature silicon epitaxy by ultra-high vacuum/chemical vapor deposition. Appl Phys Lett 48:797–799, 1986. 5. D Dutarte. RTCVD growth techniques. In The Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy, JD Cressler, Ed. New York: Marcel Dekker, 2005. 6. WB De Boer, D Terpstra, and JGM Van Berkum. Selective versus non-selective growth of Si and SiGe. Mater Sci Eng 67:46–52, 1999. 7. E Kasper. MBE growth techniques. In The Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy, JD Cressler, Ed. New York: Marcel Dekker, 2005. 8. P Magnee. SiGe:C HBT device technology: what is the big deal? Short Course Notes of the IEEE Bipolar BiCMOS Circuits and Technology Meeting, Toulouse, 2003. 9. J Osten. Carbon doping of SiGe. In The Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy, JD Cressler, Ed. New York: Marcel Dekker, 2005. 10. T Adam. UHV/CVD. In The Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy, JD Cressler, Ed. New York: Marcel Dekker, 2005. 11. DL Harame, JMC Stork, GL Patton, SS Iyer, BS Meyerson, GJ Scilla, EF Crabbe, and E Ganin. High performance Si and SiGe-base pnp transistors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1988, pp. 889–891. 12. JN Burghartz, JH Comfort, GL Patton, JD Cressler, BS Meyerson, JMC Stork, JY-C Sun, GJ Scilla, J Warnock, BJ Ginsberg, KA Jenkins, K-Y Toh, DL Harame, and S Mader. Sub-30ps ECL circuits using high-fT Si and SiGe epitaxial base SEEW transistors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1990, pp. 297–300.

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13. E Ganin, TC Chen, JMC Stork, BS Meyerson, JD Cressler, G Scilla, J Warnock, DL Harame, GL Patton, and TH Ning. Epitaxial-base double-poly self-aligned bipolar transistors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1990, pp. 603–606. 14. ED Johnson, TB Hook, JE Bertsch, Y Taur, CL Chen, HJ Shin, S Ramaswamy, A Edenfeld, and C Alcorn. A high-performance 0.5-mm BiCMOS technology with 3.3-V CMOS devices. Digest of Technical Papers VLSI Technology Symposium, Kyoto, 1990, pp. 89–90. 15. JD Warnock. Silicon bipolar device structures for digital applications: technology trends and future directions. IEEE Trans Electron Dev 42(3):382–383, 1995. 16. JN Burghartz, BJ Ginsberg, SR Mader, T-C Chen, and DL Harame. Selective epitaxial base transistor (SEBT). IEEE Electron Dev Lett 9(5):259–262, 1988. 17. DL Harame, JH Comfort, JD Cressler, EF Crabbe, JYC-Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part I—Materials, physics, and circuits. IEEE Trans Electron Dev 40:455– 468, 1995. 18. DL Harame, JH Comfort, JD Cressler, EF Crabbe, JYC-Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors: Part II—Process integration and analog applications. IEEE Trans Electron Dev 40:455–468, 1995. 19. SA Jang, C-S Han, Y-B Kim, and I-S Yeo. The role of polysilicon in the suppression of Bird’s beak in poly-buffered LOCOS. IEEE Trans Electron Dev 46(2):433–436, 1999. 20. A Joseph, D Coolbaugh, M Zierak, R Wuthrich, P Geiss, Z He, X Liu, B Orner, J Johnson, G Freeman, D Ahlgren, B Jagannathan, L Lanzerotti, V Ramachandran, J Malinowski, H Chen, J Chu, P Gray, R Johnson, J Dunn, S Subbanna, K Schonenberg, D Harame, R Groves, K Watson, D Jadus, M Meghelli, and A Rylyakov. A 0.18 mm BiCMOS technology featuring 120/100 GHz (fT/fmax) HBT and ASIC-compatible CMOS using copper interconnect. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 143–146. 21. DL Harame, EF Crabbe, JD Cressler, JH Comfort, JY-C Sun, SR Stiffler, E Kobeda, JN Burghartz, MM Gilbert, JC Malinowski, AJ Dally, S Ratanaphanyarat, MJ Saccamango, W Rausch, J Cotte, C Chu, and JMC Stork. A high performance epitaxial SiGe-base ECL BiCMOS technology. Technical Digest of the Electron Devices Meeting, San Francisco, 1992, pp. 19–22. 22. DJ Frank, RH Dennard, E Nowak, PM Solomon, Y Taur, and H-SP Wong. Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 89(3):259–288, 2001. 23. K Rim, S Koester, M Hargrove, J Chu, PM Mooney, J Ott, T Kanarsky, P Ronsheim, M Ieong, A Grill, and H-SP Wong. Strained Si NMOSFETs for high performance CMOS technology. Technical Digest of the VLSI Technology Symposium, 2001, pp. 59–60. 24. S Takagi, T Mizuno, T Tezuka, N Sugiyama, T Numata, K Usuda, Y Moriyama, S Nahaharai, J Koga, A Tanabe, N Hirashita, T Irisawa, and T Maeda. Strained—Si/SiGe—On Insultator CMOS Technology as a platform of device performance boosters, Proceedings of the 206th Electrochemical Society Meeting, SiGe: Materials, Processing, and Devices Symposium, Honolulu, 2004, pp. 61–76. 25. T Ghani, M Armstrong, C Auth, M D Giles, K Mistry, A Murthy, L Shifren, S Thompson, and M Bohr. Uniaxial-strained Silicon CMOS Devices for High Performance Logic Nanotechnology, Proceedings of the 206th Electrochemical Society Meeting, SiGe: Materials, Processing, and Devices Symposium, Honolulu, 2004, pp. 681–700. 26. EJ Nowak, I Aller, T Ludwig, K Keunwoo, RV Joshi, C-T Chuang, K Bernstein, and R Puri. Turning silicon on its edge. IEEE Circuits Dev Mag 20(1):20–31, 2004. 27. JL Hoyt, HM Nayfeh, S Eguchi, I Aberg, G Xia, T Drake, EA Fitzgerald, and DA Antoniadis. Strained Silicon MOSFET Technology. Technical Digest of the Electron Devices Meeting, Washington, 2002, pp. 23–26. 28. CW Liu, S Maikap, MH Liao, and F Yuan. BiCMOS devices under mechanical strain, Proceedings of the 206th Electrochemical Society Meeting, SiGe: Materials, Processing, and Devices Symposium, Honolulu, 2004, pp. 437–438.

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29. H Nii, T Yamada, K Inoh, T Shino, S Kawanaka, M Yoshimi, and Y Katsumata. A novel lateral bipolar transistor with 67 GHz fmax on thin-film SOI for RF analog applications. IEEE Trans Electron Dev 47(7):1536–1541, 2000. 30. GG Shahidi, DD Tang, B Davari, Y Taur, P McFarland, K Jenkins, D Danner, M Rodriguez, A Megdanis, E Petrillo, M Polcari, and TH Ning. A novel high-performance lateral bipolar on SOI. Technical Digest of the 1991 Electron Devices Meeting, San Fancisco, 1991, pp. 663–666. 31. T Arnborg and A Litwin. Analysis of new high-voltage bipolar silicon-on-insulator transistor with fully depleted collector. IEEE Trans Electron Dev 42(1):172–177, 1995. 32. J Cai, M Kumar, M Steigerwalt, H Ho, K Schonenberg, K Stein, H Chen, K Jenkins, Q Ouyang, P Oldiges, and T Ning. Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate. Proceedings of the 2003 BCTM, Toulouse, 2003, pp. 215–218. 33. G Freeman, B Jagannathan, S-J Jeng, J-S Rieh, AD Stricker, DC Ahlgren, and S Subbanna. Transistor design and application considerations for >200-GHz SiGe HBTs. IEEE Trans Electron Dev 50(3):645–655, 2003. 34. G Freeman, J-S Rieh, B Jagannathan, Y Zhijian, F Guarin, and A Joseph. Device scaling and application trends for over 200 GHz SiGe HBTs. Silicon Monolithic Integrated Circuits in RF Systems. Digest of Papers 2003 Topical Meeting on Silicon Heterostructures, 2003, pp. 6–9. 35. B Jagannathan, M Meghelli, K Chan, J-S Rieh, K Schonenberg, D Ahlgren, S Subbanna, and G Freeman. 3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay. IEEE Electron Dev Lett 24(5):324–326, 2003. 36. J-S Rieh, KM Watson, F Guarin, Y Zhijian, P-C Wang, AJ Joseph, G Freeman, and S Subbanna. Reliability of high-speed SiGe heterojunction bipolar transistors under very high forward current density. IEEE Trans Dev Mater Reliab 3(2):31–38, 2003. 37. MJW Rodwell, T Mathew, D Scott, D Mensa, Q Lee, J Guthrie, Y Betser, SC Martin, RP Smith, S Jaganathan, S Krishnan, SI Long, R Pullela, B Agarwal, U Bhattacharya, L Samoska, and M Dahlstrom. Submicron sealing of HBTs, IEEE Trans Electron Dev 48 (11): 2606–2604, 2001. 38. B Tillack, Y Yamamoto, and J Murota. Atomic Level Control of SiGe Epitaxy and Doping, Proceedings of the 206th Electrochemical Society, SiGe: Materials, Processing, and Devices Symposium, Honolulu, 2004, pp. 803–814.

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5 SiGe HBTs on CMOSCompatible SOI 5.1 5.2 5.3 5.4 5.5 5.6

Jin Cai and Tak H. Ning IBM, Thomas J. Watson Research Center

5.1

5.7

The SOI Advantage ............................................................. 5-1 Vertical Bipolar Transistors on Thin SOI.......................... 5-2 Voltage Pinning in a Fully Depleted Collector ................. 5-3 Making SiGe HBTs on Thin SOI Substrate ...................... 5-6 Characteristics of SOI SiGe HBTs...................................... 5-8 Process Optimization, Device Scaling, and Complimentary Bipolar ............................................ 5-12 Summary ............................................................................ 5-13

The SOI Advantage

Silicon-on-insulator (SOI) technology has matured over the past 15 years to become production-worthy for advanced CMOS manufacturing [1], for applications ranging from high-end servers like IBM’s PowerPC and AMD’s Opteron to ultralow-power systems like Seiko and Oki’s chips for watches. Conventional silicon VLSI processing is based on bulk silicon substrates. When CMOS transistors are built into a thin silicon film of the order of 0.1 mm on top of an insulating silicon dioxide layer, the source and drain junction capacitance is greatly reduced. As a result, SOI CMOS circuits switch faster and use less power than conventional bulk CMOS. The power-delay advantage obtained from substrate material innovation has become particularly important as conventional CMOS scaling is reaching its limit. BiCMOS is the preferred technology platform for many wireless and communication applications, which need both RF/analog functions from bipolar transistors and low-power digital functions from CMOS transistors. From a mixed-signal system perspective, SOI is attractive due to the insulating nature of the substrate, which can provide RF noise isolation between digital and RF/analog components, particularly when a thick insulator or high-resistivity substrate is used [2], or when substrate engineering is applied [3]. The reduction of substrate loss also enables fully integrated high quality-factor passive elements for communication systems [2]. The challenge for SOI BiCMOS integration arises from a fundamental device architectural difference between bipolar and CMOS. Unlike CMOS transistors where current flows in a superficial silicon layer from source to drain, in high-speed vertical bipolar transistors including all SiGe HBTs, electrons flow vertically from the emitter on the top to the collector on the bottom. In order to have low resistance access to the collector from a contact electrode on the top, a subcollector layer on the order of 1 to 2 mm thick with heavy doping is needed underneath the collector, which makes it too thick to build on thin silicon film SOI. Past approaches to SOI BiCMOS integration either used a thick silicon layer on a bonded SOI substrate to accommodate the vertical bipolar transistors, or used lateral bipolar transistors on thin silicon film SOI. In the thick SOI case, the CMOS transistors have the same source and drain junction capacitances as those on a conventional bulk substrate and thus have no power-delay advantage. Digital BiCMOS technology on 1 to 1.5 mm silicon film SOI was developed for soft-error immune 5-1

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processors [4,5]. More recently, a SiGe HBT–CMOS technology on 1 mm silicon film SOI was developed for RF and mixed-signal applications, featuring integrated high-Q inductors [2]. For such thick-silicon SOI BiCMOS, deep trenches are employed to isolate the bipolar transistors from the bulk-like CMOS devices. The lateral SOI bipolar has limited speed due to base width control and is not compatible with SiGe epitaxy. It is noteworthy that process innovations to minimize the base width and base resistance have kept improving the speed of lateral SOI bipolar transistors over the years [6–8]. With fT up to 20 GHz, it still cannot compete with vertical bipolar transistors (not to mention SiGe HBTs) in terms of performance, but it may provide a low-cost solution for mobile wireless communications due to a simpler and more CMOS-compatible manufacturing process [7]. Recently, a novel vertical bipolar transistor suitable for integration on CMOS-compatible SOI was proposed and npn transistors with SiGe base were demonstrated on 0.12 mm SOI [9–12]. The remainder of this chapter is dedicated to the concept, manufacturing process, electrical characteristics, and future prospects of this new transistor.

5.2

Vertical Bipolar Transistors on Thin SOI

High-performance vertical bipolar transistors consist of an nþ emitter region, a p-type base region, and an n-type collector region stacked atop one another. The base and emitter regions can be built on top of the SOI substrate by epitaxial growth of a silicon–germanium base layer followed by LPCVD deposition of a polysilicon emitter film, like in most SiGe HBTs. Thus the silicon film of the SOI substrate needs to accommodate only the collector part. In conventional vertical bipolar, typically a thick nþ-type subcollector region and an nþ reachthrough region are used to give a low resistance contact to the collector at the silicon surface. The subcollector is placed deep enough to leave a quasineutral region of n-collector between the subcollector and collector space–charge region (or depletion region), such that the collector–base capacitance is not increased. This conventional collector structure would require an SOI substrate with a silicon film thickness (TSi) of at least 1 mm, as illustrated in Figure 5.1a. The silicon film thickness requirement is greatly relaxed if we omit the thick nþ subcollector layer, as shown in Figure 5.1b. The lower bound of TSi is determined by the depth of the depleted collector region (WC). For a collector doping concentration (NC) of 1017 cm3 and a reverse collector–base junction bias of 2 V, WC ¼ 0.19 mm, which approaches the range of TSi for SOI CMOS devices. However, the collector current is carried laterally toward the nþ reachthrough in the thin quasineutral layer above the buried oxide, which is very resistive. The collector series resistance from the quasineutral layer is inversely proportional to NC (TSI WC) and can be more than 103 times higher than that of a heavily doped 1mm thick subcollector layer. A more radical reduction of TSi to below collector depletion thickness WC leads to a new vertical bipolar transistor, as shown in Figure 5.1c. The collector underneath the base and above the buried oxide is fully depleted. The fully depleted collector not only eliminates the resistive quasineutral layer but also results in a reduced collector–base junction capacitance (CCB) due to its serial connection with a small capacitance from the thick buried oxide layer. To minimize collector series resistance, the nþ reachthrough should be placed as close as possible to the depleted collector region. However, it is desirable to leave a narrow quasineutral region in-between such that the proximity of nþ reachthrough does not limit CCB or the breakdown voltage of the device. The new device structure in Figure 5.1c is similar to bending the vertical collector structure in Figure 5.1a by 908 such that most of the vertical collector stack including the lower part of collector depletion region, the quasineutral collector region, and the nþ subcollector region rest on the side of the upper part of collector depletion region. Under forward active mode, electrons injected from the emitter, instead of flowing vertically down toward the subcollector layer as in a typical vertical bipolar transistor, are guided by the two-dimensional electric field in the collector depletion region and make a turn toward the nþ reachthrough on the side.

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SiGe HBTs on CMOS-Compatible SOI

C

B

Reachthrough

n+

B

E

n+

n+

p

p

n TSI > 1 µm

C

E

n

Depleted n collector

TSI

Quasi-neutral n collector

n Buriedoxide oxide buried

Subcollector

n+

n

n+

Substrate of SOI

Buried buriedoxide oxide

(b)

Substrate of SOI

(a)

C

B

E

n+ Reachthrough

TSI < 0.2 µm

n+

p n

n

Depleted n collector Quasi-neutral n collector

Buriedoxide oxide buried Substrate of SOI

(c)

FIGURE 5.1 Schematics of npn bipolar transistors on SOI substrate, showing the evolution of collector design that leads to the new transistor. The three cross sections have the same base and emitter layers but different collector layers: (a) the traditional design with nþ subcollector underneath the n-collector, (b) without nþ subcollector, and (c) fully depleted n-collector.

The new device concept overcomes the TSi limit for integrating SiGe HBT with SOI CMOS. For a given TSi that is usually dictated by CMOS scaling requirement, there is an upper limit to the collector doping concentration that satisfies WC ¼ TSi. To maximize the high-frequency performance of the HBT, an NC near this limit can be used to delay the onset of base push-out, or Kirk effect.

5.3

Voltage Pinning in a Fully Depleted Collector

In this section, a simple one-dimensional theory is used to analyze the onset condition of full collector depletion, as a function of the physical structure (TSi, NC) and bias conditions (VB, VC, and VS for base, collector, and SOI substrate, respectively). The unique characteristic of collector voltage pinning and its consequence on bipolar device operation will be highlighted. For simplicity, consider part of the SiGe HBT structure, with base, collector, nþ reachthrough, and SOI substrate, as illustrated in Figure 5.2a. Due to the symmetry, along the central cut line, the electric field is vertical and the potential distribution can be solved exactly using one-dimensional Poisson’s equation. The problem is simply a p–n diode in series with a MOS capacitor. Figure 5.2b illustrates the band diagram along the cut line for the case where both the p–n diode and MOS capacitor are

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VB

VC

VC p y1

n+

n+

n

y2

TBox

Buried oxide Substrate of SOI

p+

VS

(a)

Base Collector SiO2 Substrate

Base Collector SiO2 Substrate

E

TSI

EC

TSI

TSI VS

VB EV

EMAX

VC Y y1

y2

y1

(b)

y2

(c)

FIGURE 5.2 Analysis of collector potential distributions based on depletion approximation. (a) Schematic cross section of part of an SOI bipolar transistor with symmetrically placed nþ reachthough regions; (b) energy band diagram along the central cut line; and (c) electric field distribution along the same cut line.

reverse-biased (VB < VC, VS < VC), with two distinct depletion regions of width y1 and y2, respectively (y1 þ y2 < TSi). Figure 5.2c illustrates the electric field distribution along the same cut line. The voltage in the collector quasineutral region follows VC of the nþ reachthough regions. Increase of collector 0 voltage widens both depletion regions and at certain critical voltage VC , the two depletion regions 0 merge. Increase of collector voltage beyond VC no longer influences the vertical field. The potential well 0 along the center line has a fixed depth determined by VC. This is referred to as collector voltage pinning. 0 Away from the centerline, the additional voltage VC –VC increases the lateral field. The critical collector voltage can be solved analytically using depletion approximations for both the p/n diode and the MOS capacitor. For the base–collector diode, assuming one-sided abrupt junction, depletion width y1 is described by VC VB þ VBI ¼

q NC y12 ; 2«S

(5:1)

where VBI is the diode built-in potential. For the MOS capacitor, the depletion width y2 near the buried oxide is described by VS VC fMS ¼ VOX þ VSI ¼

qNC y2 q NC y22 ; 2«S COX

(5:2)

where fMS is the work function difference between the pþ substrate of SOI and the n-collector, VOX and VSI are potentials dropped across the buried oxide and the collector depletion region (y2), respectively. 0 The critical collector voltage VC that fully depletes the collector, i.e., y1 þ y2 ¼ TSi, can be solved based on Equations 5.1 and 5.2:

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SiGe HBTs on CMOS-Compatible SOI

VC0 ¼ VB VBI þ

q q 0 NC (y10 )2 VCM ¼ VB VBI þ NC TSi2 ; 2«S 2«S

(5:3)

0

where y1 is the value of y1 at the onset of full depletion: y10

1=COX þ 1=(2CS ) (VB VS þ fMS VBI )=qNC TSi ; ¼ TSi 1=COX þ 1=CS

(5:4)

1.5

Saturated collector (VC'<0)

I. Fully depleted collector

VC (V)

1.0

VC =VS −φm

T_SI = 120 nm T_BOX = 140 nm NC = 1.5E17/cm3 VB = 0 V

2.0

s

CS ¼ «S/TSi and COX ¼ «OX/TBOX. For thick buried oxide (COX << CS) and low substrate biases (VS VB), the depletion region due to the MOS capacitor is narrow and y10 TSi. In general, when the MOS capacitor is under flatband condition and the collector is fully depleted from the p/n diode (y10 ¼ TSi), 0 . More negative substrate bias induces the critical collector voltage reaches the maximum value of VCM a depletion region near the buried oxide, which has the effect of lowering the critical collector voltage via a smaller y10 . In the other direction, under more positive substrate bias, the MOS capacitor is under surface accumulation condition, i.e., electrons accumulate near the buried oxide interface. The accumulation layer is linked to the nþ reachthrough regions and acquires the collector potential VC. This breaks the collector voltage pinning. The vertical potential drop again follows the collector voltage. The accumulation layer acts like an ultrathin subcollector, which is shown to significantly enhance the speed of the SOI SiGe HBTs in Section 5.5. We call this novel structure with depleted collector directly on accumulated back surface the accumulation-subcollector transistor. For any SOI bipolar structure, there are four distinct types of collectors depending on the bias condition: (i) fully depleted collector; (ii) partially depleted collector with depleted back surface; (iii) partially depleted collector with accumulated back surface, and (iv) depleted collector on accumulated back surface (accumulation subcollector). The bias condition that defines the collector type is shown in Figure 5.3 for an SOI bipolar device with TSi ¼ 120 nm, TBOX ¼ 140 nm, NC ¼ 1.5 1017 cm3, which is used in the experiment described in Section 5.4. VB ¼ 0 is the reference voltage. The boundary between regions I and II is described by Equation 5.3. The single point that borders all four

IV. Depletedcollector on accu. layer VC = VCM

0.5 VC

C'

=V

0.0 −0.5 −1.0

II. Partially depleted collector (depleted back surface) −4

−2

0 VS (V)

III. Partially depleted collector (accu. back surface)

2

4

FIGURE 5.3 The collector characteristic of an SOI bipolar transistor is categorized into four types depending on the collector and SOI substrate bias conditions: (1) fully depleted collector, (2) partially depleted collector with depleted back surface, (3) partially depleted collector with accumulated back surface, and (4) depleted collector on accumulated back interface, or accumulation subcollector.

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regions corresponds to the condition that y10 ¼ TSi in Equation 5.4. It is noteworthy that in the fully depleted collector region, reduced vertical potential drop due to the negative substrate bias can lead to effective forward biasing of the B–C junction (VC0 < VB) for an apparent reverse bias condition (VC > VB), as shown by the shaded area. This region gives rise to collector saturation and should be avoided in circuit applications. There is a well-known tradeoff between the speed (fT) and the breakdown voltage (BVCEO) in a traditional bipolar transistor, from the vertical scaling of the collector depletion layer [13]. The voltage swing of a high-speed device is constrained by the breakdown voltage. We can design an SOI bipolar device such that the collector voltage is pinned at a value below the BVCEO of a bulk device with the same collector doping. The SOI device is expected to have improved BVCEO as well as Early voltage VA. Avalanche multiplication and breakdown is sensitive to the maximum electric field (EMAX) near the B–C junction interface. In a bulk device, EMAX increases with collector voltage as a function of pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 0 VC VB þ VBI , whereas in the fully depleted collector device, it is pinned at (qNC/«S)y1 , independent of collector voltage. Thus avalanche effect progresses more slowly with increasing collector voltage in a fully depleted collector device than a bulk device. Avalanche breakdown is delayed to higher collector voltage in the SOI device where the lateral field becomes large enough to raise EMAX. The depletion width on the base side is determined by EMAX, which does not change with collector voltage in the fully depleted collector device. Therefore, the modulation of quasineutral base width by the collector voltage is much weaker than that of a bulk device, which results in higher VA. In an accumulation-subcollector device (region IV in Figure 5.3), the B–C junction reverse bias is dropped over TSi whereas in a bulk device the same reverse bias is dropped over a larger distance, or WC > TSi if collector-doping concentrations are the same. This means higher EMAX and somewhat degraded BVCEO and VA in an accumulation-subcollector device. The difference in the maximum field is SOI Bulk EMAX EMAX ¼

5.4

qNC WC TSi : «S TSi

(5:5)

Making SiGe HBTs on Thin SOI Substrate

Figure 5.4 shows the process flow diagrams for building npn SiGe HBTs on SOI substrate. The silicon film thickness for SOI CMOS has been scaled down from about 0.2 mm to below 0.1 mm, along with channel length scaling. The new SiGe HBT is expected to be scalable to thinner SOI substrate as will be discussed in Section 5.6. In the experiment, we used the same SOI substrate that is used for a 130 nm SOI CMOS technology [14], which has a silicon thickness of 0.12 mm and a buried oxide thickness of 0.14 mm. After shallow-trench isolation, a phosphorus implant is introduced to define the collectordoping concentration in the silicon area. It can be a blanket implant in a bipolar-only process, or a masked implant in a BiCMOS flow. Both a uniform doping profile and a low–high retrograde doping profile were exercised. Then a mask is used for a high-dose phosphorus implant that defines an nþ reachthrough region surrounding the n-type collector in the middle. The mask dimension determines the length of the n-collector, LC, which was varied in the experiment to evaluate its effect on collector resistance and breakdown behaviors. Next, a dielectric stack, followed by a heavily doped pþ polysilicon layer, is deposited over the wafer. The pþ polysilicon will provide low-resistance contact to the base and the dielectric stack is served as an insulator between the pþ polysilicon and the collector. The thickness of the insulator should be optimized as it contributes to parasitic collector–base capacitance. The parasitic CCB could dominate in a fully depleted collector device as the collector–base junction capacitance is minimized. The use of a thicker insulator reduces CCB but creates more topography later in the process that can increase the base resistance. Then a window is etched into the polysilicon and insulator to expose the silicon surface for epitaxial growth of the SiGe base layer. The window size, LB, should be minimized while providing enough room for a defect-free SiGe base region. The SiGe base layer was grown by a nonselective

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SiGe HBTs on CMOS-Compatible SOI

n Buried oxide

STI, collector implant

Substrate of SOI

n+

n+

n Buried oxide Substrate of SOI

p+ n+

n+ reachthrough implant p+ n+

n

Dielectric stack, p+ poly

Buried oxide Substrate of SOI

p+ n+

p+

p n

n+

SiGe-base

Buried oxide Substrate of SOI

n+

n+ p+ n+

Dielectric stack, emitter window

p+

p n

n+

Buried oxide

n+ poly emitter

Substrate of SOI

p+ n+

n+ p n

p+ n+

Pattern n+ emitter poly

Buried oxide Substrate of SOI

B p+ n+

E n+ p n

p+

Buried oxide Substrate of SOI

FIGURE 5.4

C

Pattern p+ base poly

n+ CoSi, and contact open

An example of process flow to make SiGe HBTs on CMOS-compatible SOI.

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Fabrication of SiGe HBT BiCMOS Technology

FIGURE 5.5

Cross-sectional SEM micrograph of a SiGe HBT on 0.12 mm silicon film SOI.

low-temperature epitaxy (LTE) process using UHV/CVD tools. During the LTE process, polysilicon is grown on the sidewalls of the dielectric window, which provides the link between the SiGe base layer and the overhanging pþ polysilicon layer. Next, a second dielectric stack is deposited which will serve as an insulator between the base and the emitter. An emitter window mask is used to etch an opening in the dielectric stack, and a layer of in situ arsenic-doped polysilicon layer is deposited that becomes the nþ emitter. Due to the two-dimensional electric field in the depleted collector region, the electrons coming down through the middle of the emitter window will have a longer lateral drift path in the depleted collector than those from the edge of the emitter window. The speed of the SOI device is expected to degrade at large emitter width. Simulation results suggest that a good rule of thumb is to keep WE < 2TSi. Two more mask levels are then used to pattern an nþ polysilicon emitter region and a pþ polysilicon base region, respectively. Cobalt silicide is formed over the pþ base and nþ collector reachthrough regions to reduce access resistance to the intrinsic base and collector of the device. Finally, contacts to the nþ emitter, pþ base, and nþ collector reachthrough are etched open. It should be noted that the deep subcollector implantation and drive-in, the n-type epitaxial silicon growth, and the deep-trench isolation process steps associated with fabrication of a conventional vertical bipolar transistor are not needed in fabricating the thin-SOI bipolar. Figure 5.5 shows an SEM micrograph of an SOI SiGe HBT, after contacts to the emitter, base, and collector are opened. The mask dimensions of emitter width, LTE window, and collector length are 0.16, 0.5, and 1.2 mm, respectively. The collector-doping profile is uniform, with NC ¼ 1.5 1017 cm3. Devices with smaller LB and LC designs and different collector-doping profiles were also fabricated.

5.5

Characteristics of SOI SiGe HBTs

In this section, the electrical characteristics of the manufactured thin-SOI SiGe HBTs will be reviewed, with a focus on the breakdown behavior in the depleted collector SOI device as well as the substrate bias effect on both the DC and AC performance. Figure 5.6 shows the Gummel plot and the output ICVCE characteristics, with substrate bias, VSE (referenced to the emitter voltage), as a parameter that is varied from 5 to 20 V. The Gummel plot shows a peak current gain of over 400. Since the base and emitter process are borrowed from a bulk SiGe technology [15], the current gain is similar to that of the bulk devices. The substrate bias has an effect at emitter–base forward biases higher than 0.9 V. The opposite movement in IB and IC is a signature of collector saturation effect where the forward biasing of collector–base junction reduces IC while contributing to more IB. A positive substrate bias suppresses this saturation effect by increasing the vertical potential drop in the collector that prevents electrons from back injection into the base. The

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SiGe HBTs on CMOS-Compatible SOI

0.01 VCB = 0 V 1⫻10−4 IC IC, IB (A)

1⫻10−6 IB 1⫻10−8

VSE= −5 V 0V 5V 20 V

1⫻10−10

1⫻10−12 0.6

0.7

0.8

0.9

(a) 1.0

1.1

VBE (V) 0.25 IB = 0.1 µA/step

IC (mA)

0.20

0.15

0.10

0.05 (b) 0.00 0

1

2

3 VCE (V)

4

5

6

FIGURE 5.6 DC characteristics of a 0.16 mm 0.8 mm SOI SiGe HBT under four substrate bias (VSE ¼ VS VE) conditions: 5 V (dash–dot), 0 (solid), 5 V (dash), and 20 V (dot). (a) Gummel plot and (b) output characteristics.

IC VCE in Figure 5.6(b) shows almost identical turn-on behaviors under zero and positive substrate biases, whereas under the negative substrate bias, it requires higher collector voltage to turn on the device, another manifestation of saturation effect. This is consistent with Figure 5.3, which predicts an 0 effectively forward biased B–C junction (VC VB < 0) when VS VB < 2 V. As expected from the voltage-pinning effect, BVCEO is the highest at 5.5 V under zero substrate bias. The reduction of BVCEO at VSE ¼ 20 V is due to the accumulation subcollector that breaks the voltage pinning and creates a vertical potential drop of VCB across TSi. In contrast, at VSE ¼ 5 V, avalanche current turns on at the same VCE as the high-positive bias case, but the rate of increase with collector voltage is slower. This can be explained by Figure 5.3. Under low-positive VSE, as VCE increases, the collector makes a transition from the one with an accumulation subcollector (region IV) to a fully depleted collector (region I). The transition decouples the collector voltage to the maximum electric field at the B–C junction interface and results in a much slower increase of avalanche current with VCE.

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Fabrication of SiGe HBT BiCMOS Technology

For the same collector design, BVCEO depends on the current gain (IC/IB) due to the bipolar effect. A more direct examination of avalanche multiplication is through the measurement of the ‘‘M 1’’ factor [16]. In this measurement, a constant forward emitter current (IE) is forced through the device while ramping up the collector voltage. The electron–hole pairs generated by impact ionization in the collector depletion region contribute to an increase in the collector current and a corresponding reduction in the base current (DIC ¼ DIB). The factor ‘‘M 1’’ is extracted as jDIBj/IE. Figure 5.7a compares the avalanche multiplication in an SOI SiGe HBT to two bulk SiGe HBTs with 90 GHz fT (open symbols) and 50 GHz fT (solid symbols), respectively. In bulk devices, avalanche multiplication has the similar exponential dependence on VCB. The 90 GHz device has an ‘‘M 1,’’ which is about 6 times higher than the 50 GHz device due to heavier collector doping concentration as a part of vertical scaling. The SOI device shows a much weaker dependence of ‘‘M 1’’ on VCB under zero substrate bias, or under positive substrate bias in the high VCB range. This corresponds to the bias conditions for a fully depleted collector. In the open-base configuration, the increase of collector current due to avalanche effect is multiplied by the current gain b of the bipolar transistor. When b(M 1) ¼ 1, the collector current is doubled from its

1

IE = 10 µA Bulk SiGe HBT

Multiplication factor −1

0.1

20V

0.01

5V

1⫻10−3 0V

1⫻10−4

−5V

1⫻10−5 0

1

(a)

2

SOI SiGe HBT 3

4

5

Collector−base reverse bias (V)

M−1 at VCB = 1.5 V (10−3)

5 4

SOI SiGe HBT (increase substrate bias)

3

NC2

2 bulk SiGe HBT (vertical scaling)

1 NC1 0 20

(b)

40

60

80

100

Cut-off frequency (GHz)

FIGURE 5.7 Comparison of measured avalanche multiplication factor (M 1) in the collector–base junction between SOI SiGe HBTs and bulk SiGe HBTs. (a) ‘‘M 1’’ as a function of reverse C–B junction bias. (b) Correlation between ‘‘M 1’’ and cutoff frequency, dashed line indicates trend from bulk SiGe HBT technologies.

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SiGe HBTs on CMOS-Compatible SOI

low VCB value, which can be used as a measure for device breakdown. The flat portion of the ‘‘M 1’’ data suggests that it is possible to significantly increase the BVCEO of a fully depleted collector device by reducing the current gain from 400 in the experimental hardware to about 100. Under positive substrate bias and in the low VCB range, which corresponds to the accumulation subcollector condition, ‘‘M 1’’ is nearly the same as the 50 GHz bulk device. Under negative substrate bias, the exponential rise of ‘‘M 1’’ suggests that the lateral field dominates avalanche multiplication in the saturated collector region where there is minimum vertical potential drop in the collector. Figure 5.7b shows that the SOI devices and the bulk devices have a different ‘‘M 1’’ versus fT tradeoff. The peak fT of the SOI devices can be improved by applying positive substrate biases without much increase of avalanche multiplication, while scaling NC in a bulk device results in a steeper penalty in ‘‘M 1,’’ or breakdown voltage. The fT and fMAX characteristics of an SOI SiGe HBT are shown in Figure 5.8, along with those of a lateral SOI bipolar device from Ref. [7]. The SiGe HBT shows a 150% to 350% improvement in peak fT, depending on the substrate bias condition. The maximum oscillation frequency, fMAX, on the other pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ hand, is less sensitive to the substrate bias. This is expected from the fMAX / fT =CCB dependence. As VSE increases, CCB increases as the collector makes a transition from a fully depleted one to the one with an accumulation subcollector. A 30% increase of fT is observed for a VSE change from 0 to 5 V, while there is minimal change in fMAX. This suggests that CCB increases by 30% due to the presence of an accumulation back surface. To understand the strong dependence of fT on VSE, it is instructive to look at the two-dimensional potential distribution in the collector depletion region. Figure 5.9 shows the simulated equipotential contours in the forward active mode with VCB ¼ 1 V and VBE ¼ 0.84 V. The potential VI is referenced to the vacuum level in the emitter. The boundaries of the collector depletion region are defined approximately by VI ¼ 4 V at the base side and VI ¼ 2.5 V at the nþ reachthrough side. At zero substrate bias (VSE ¼ 0 V) in part (a), the collector is fully depleted under the base and there is little potential drop along the vertical direction. The arrow indicates the electron drift path along the electric field direction. It is mostly lateral with a length of 0.5 mm. At 20 V substrate bias (VSE ¼ 20 V), the potential at the back interface is fixed at VI ¼ 2 V, the same potential as the nþ

80 fT

SOI substrate bias

fMAX

20 V

fT, fMAX (GHz)

60

5V Vertical SOI SiGe HBT 40 0V

20

Lateral SOI Bipolar [7] 0 1⫻10−6

1⫻10−5

1⫻10−4

1⫻10−3

Collector current/emitter length (A/µm)

FIGURE 5.8 fT and fMAX characteristics of a 0.16 mm 0.8 mm SOI SiGe HBT, with SOI substrate bias as a parameter. The characteristics of a lateral SOI bipolar transistor from Ref. [7] are plotted for comparison.

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Fabrication of SiGe HBT BiCMOS Technology VCB = 1 V, VBE = 0.84 V 1.0

1.0

0.8

0.8

−2.5

3 −2.5

C

0.4

E −3.5

−2.5 −5

−3.5

−4.5 −5

−3.5 −3

−4 −3.5

B

0.6

3 −2.5

C

0.4

−2.5

−3.4 −2.5

5 10 14.8

0.2

−4 −3.5 −3

5 10 14.8

0.2

S

S

0.0

VSE = 0 V

x (µm)

(b)

VSE = 20 V

1.0

0.9

0.8

0.7

0.6

0.4

0.3

0.2

0.1

0.0

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.0 (a)

−3

−2

−4.5 −5

−4

E −4 −5.5

0.5

y (µm)

3 −2.5

y (µm)

B

0.6

x (µm)

FIGURE 5.9 Simulated potential contours in (a) a fully depleted collector device and (b) the same device transformed to an accumulation subcollector device by a 20 V substrate bias. The arrows represent the direction of electron flow in the collector depletion region. Due to symmetry, only half of the device structure is shown.

reachthrough region. The large substrate bias attracts a majority carrier accumulation layer with an electron concentration of (VS VC VBI)/qCOX ¼ 2.7 1012 cm2. The accumulation layer serves as an ultrathin subcollector, which provides a low resistance path to the nþ reachthrough. It also helps to reduce the collector series resistance in the reachthrough region. The electron drift path becomes vertical and much shorter, on the order of the SOI film thickness, or 0.1 mm. The shortened drift path results in a transit time tBC ¼ WdBC/2vSAT reduction of about 2 psec, which accounts for 80% of the fT improvements. The remaining improvement comes from the reduction of collector series resistance from the accumulation subcollector. Similar fT improvement may be obtained at a much lower substrate bias if the buried oxide is scaled down. For future SOI-CMOS technology, the ability to use a back gate voltage to control the CMOS threshold voltage is desirable for compensating chip-to-chip process variations. This can drive the scaling of buried oxide thickness to below 20 nm. On an SOI substrate with relatively thin buried oxide, it would suffice to connect the SOI substrate of the bipolar portion to the supply voltage VCC (3 V) of the analog–RF circuits to get the benefit of an accumulation subcollector. Use of nþ substrate instead of pþ substrate would further lower the required substrate bias by about 1 V. In lieu of an accumulation subcollector, a retrograde collector-doping profile with low concentration near the base and high concentration near the buried oxide can simulate some of the accumulation-subcollector effect, albeit the doping gradient is limited by the diffusion process and is much less ideal. Experimental hardware with a retrograde collector-doping profile measured a 60 GHz fT at zero substrate bias [11]. The ECL ring oscillator operation has been demonstrated using SiGe SOI bipolar transistors, with a minimum delay time of 18 pico-second per stage for a logic swing of 300 mV [11].

5.6 Process Optimization, Device Scaling, and Complimentary Bipolar This section will highlight the opportunities for some future work on the SOI SiGe HBTs. First, there are several process development opportunities for enhancing the device speed while maintaining the benefit

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SiGe HBTs on CMOS-Compatible SOI TABLE 5.1

Lithographical and SOI Thickness Scaling of Vertical SOI Bipolar Transistors Scaling Factor

Parameters

Fully Depleted Collector

WE, LB, LC TSi NC IC/LE WdBC, lateral WdBC, vertical RCLE CCB/LE RCCCB

a b 1/b2 a/b2 a b — — —

Accumulation Subcollector

Partially Depleted Collector

a b 1/b2 a/b2 — b a a/b a2/b

a b 1/b2 a/b2 — b ab a/b a2

of high breakdown voltage, which includes: (1) self-alignment of the LTE window to the nþ reachthrough region; (2) minimizing the ‘‘facet’’ region near the edge of the epitaxial layer such that the LTE window size (LB) can be reduced for the same emitter width; and (3) self-alignment of the emitter opening to the base layer. All these steps would facilitate closer placement of the nþ reachthrough to the center of the device to reduce the lateral drift path in a fully depleted collector. A buffered region of intermediate doping concentration between the nþ reachthrough and the n-collector would also help to reduce the lateral drift path while maintaining the same collector voltage pinning under the base. For SOI-CMOS, the trend in lateral (lithography dimensions) and vertical (TSi) scaling is expected to continue. We will show that the RF performance of the SOI bipolar device will benefit from this scaling trend as well. Table 5.1 shows the effect of scaling on the collector depletion layer drift length WdBC and collector delay time RCCCB for three types of collectors: fully depleted, depleted with accumulation subcollector, and partially depleted. Independent lateral and vertical scaling factors, a(<1) and b(<1), respectively, are assumed. A good guideline is to increase the collector doping concentration (NC) by 1/b2, such that the collector depletion width is reduced by the same factor b as TSi. A fully depleted collector remains fully depleted after scaling, with a shorter lateral drift path determined by the lateral scaling factor a. For the accumulation subcollector and partially depleted collector devices, in addition to a reduction in the vertical drift path by b, the collector resistance reduction results in an RC delay time reduction of up to a factor of a2. Thus, even the partially depleted device can be an attractive option after significant reduction in RC delay time. Simulation results suggest at 100 nm emitter width, 200 GHz fT can be achieved on 55 nm SOI substrates using a collector-doping concentration of 2.4 1018 cm3. The guideline for NC scaling will be eventually limited by the base–collector band-to-band tunneling current and the collector breakdown voltage. Though the speed of SOI SiGe HBT will not be as high as the most advanced bulk SiGe HBT, it will be adequate for most of the RF and wireless applications. Compared to bulk SiGe HBTs, the SOI device features a simpler manufacturing process as deep trench isolation and epitaxial collector are not necessary and the deep subcollector is omitted. The full dielectric isolation of each transistor by the shallow-trench and the buried oxide provides a lower cost opportunity to make both vertical npn and vertical pnp bipolar transistors on the same chip, as illustrated in Figure 5.10. In bulk technologies, usually only vertical SiGe npn and lateral Si pnp transistors are available, the latter simply as two back-to-back connected p–n diodes that have very low performance. The availability of a high-performance vertical SiGe pnp transistor should provide innovation opportunities in analog circuit design for significant performance improvement and power saving.

5.7

Summary

We presented a new class of vertical SiGe HBTs that is compatible with SOI-CMOS. The unique feature of collector voltage pinning in thin silicon film was discussed in depth, which gives rise to high breakdown voltage, high early voltage, and low collector capacitance. The SOI device is promising for

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Fabrication of SiGe HBT BiCMOS Technology

pnp

npn

E

E B p+ n+ p+ C

B C n+ p+ n+ p+

p

p+

n+

n

n+

nMOS

pMOS

G

G

S n+ D D p+ S n+ p n+ p+ n p+

Buried oxide Substrate of SOI FIGURE 5.10

Illustration of an SOI complementary bipolar and CMOS technology.

a better fT-BVCEO tradeoff than that from conventional collector scaling in bulk devices. The fabricated devices show the anticipated strong dependence of DC and RF characteristics on SOI substrate bias. The relatively low speed of a fully depleted collector device can be significantly enhanced by a positive substrate bias for an accumulation-subcollector operation. The new device is expected to scale well with SOI-CMOS and can enable complementary SOI-BiCMOS with the possibility of a high-performance pnp transistor.

Acknowledgments The authors would like to thank M. Kumar, M. Steigerwalt, H. Ho, A. Ajmera, K. Stein, H. Chen, and M. Khater for process support, Q. Ouyang, P. Oldiges, J. Rieh, and K. Jenkins for simulation and characterization help, and G. Shahidi, W. Haensch, G. Freeman, and D. Ahlgren for management support.

References 1. G.G. Shahidi. SOI technology for the GHz era. IBM J. Res. Develop. 46(2–3), 121–131 (2002). 2. K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, K. Kondo, T. Hashimoto, and T. Harada. A 0.2-mm 180 GHz fMAX 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications. IEDM Tech. Digest, 741–744 (2000). 3. J.N. Burghartz, M. Bartek, B. Rajaei, P.M. Sarro, A. Polyakov, N.P. Pham, E. Boullard, and K.T. Ng. Substrate options and add-on process modules for monolithic RF silicon technology. Proc. BCTM, pp. 17–23 (2002). 4. T. Hiramoto, N. Tamba, M. Yoshida, T. Hashimoto, T. Fujiwara, K. Watanabe, M. Usami, and T. Ikeda. A 27-GHz double polysilicon bipolar technology on bonded SOI with embedded 58 mm2 CMOS cells for ECL-CMOS SRAM applications. IEDM Tech. Digest, 39–42 (1992). 5. T. Hashimoto, T. Kikuchi, K. Watanabe, N. Ohashi, T. Saito, H. Yamaguchi, S. Wada, N. Natsuaki, M. Konda, S. Konda, Y. Homma, N. Owada, and T. Ikeda. A 0.2 mm bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processors. IEDM Tech. Digest, 209–212 (1998). 6. G.G. Shahidi, D.D. Tang, B. Davari, Y. Taur, P. McFarland, K. Jenkins, D. Danner, M. Rodringuez, A. Megdanis, E. Petrillo, M. Polcari, and T.H. Ning. A novel high-performance lateral bipolar on SOI. IEDM Tech. Digest, 663–666 (1991). 7. T. Shino, S. Yoshitmi, H. Nii, S. Kawanaka, K. Inoh, T. Yamada, T. Fuse, Y. Katsumata, M. Yoshimi, S. Watanabe, and J. Matsunaga. Analysis on high-frequency characteristics of SOI lateral BJTs with self-aligned external base for 2-GHz RF applications. IEEE Trans. Electron Dev. 49(3), 414–421 (2002). 8. H. Nii, T. Yamada, K. Inoh, T. Shino, S. Kawanaka, M. Yoshomi, and Y. Katsumata. A novel lateral bipolar transistor with 67-GHz fMAX on thin-film SOI for RF analog applications. IEEE Trans. Electron Dev. 47, 1536–1541 (2000).

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SiGe HBTs on CMOS-Compatible SOI

5-15

9. J. Cai, A. Ajmera, Q. Ouyang, P. Oldiges, M. Steigerwalt, K. Stein, K. Jenkins, G. Shahidi, and T. Ning. Fully-depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI. Symp. VLSI Tech. Digest, pp. 172–174 (2002). 10. Q. Ouyang, J. Cai, P. Oldiges, and J. Johnson. A simulation study of thin SOI bipolar transistors with fully or partially depleted collector. BCTM Tech. Digest, 28–31 (2002). 11. J. Cai, M. Kumar, M. Steigerwalt, H. Ho, K. Schonenberg, K. Stein, H. Chen, K. Jenkins, Q. Ouyang, P. Oldiges, and T. Ning. Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate. Proc. BCTM, pp. 215–218 (2003). 12. L. Geppert. A better bipolar transistor for wireless ICs. IEEE Spectrum, December 2003, p. 20. 13. Y. Taur and T.H. Ning. Fundamentals of Modern VLSI Devices. Cambridge University Press, Cambridge (1998) [chapter 8]. 14. P. Smeys, V. McGahay, I. Yang, J. Adkisson, K. Beyer, O. Bula, Z. Chen, B. Chu, J. Culp, S. Das, A. Eckert, L. Hadel, M. Hargrove, J. Herman, L. Lin, R. Mann, E. Meciejewski, S. Narasimha, P. O’Neil, S. Rauch, D. Ryan, J. Toomey, L. Tsou, P. Varekamp, R. Wachnik, T. Wagner, S. Wu, C. Yu, P. Agnello, J. Connolly, C. Davis, R. Ferguson, A. Sekiguchi, L. Su, R. Goldblatt, and T.C. Chen. A high-performance 0.13 mm SOI CMOS technology with Cu interconnects and low-k BEOL dielectrics. Symp. VLSI Tech. Digest, pp.184–186 (2000). 15. G. Freeman, D. Ahlgren, D.R. Greenberg, R. Groves, F. Huang, G. Hugo, B. Jagnnathan, S.J. Jeng, J. Johnson, K. Schonenberg, K. Stein, R. Volant, and S. Sabbanna. A 0.18 mm 90 GHz fT SiGe HBT BiCMOS, ASIC-compatible, copper interconnect technology for RF and microwave applications. IEDM Tech. Digest, 569–572 (1999). 16. G. Freeman, J. Rieh, B. Jagannathan, Z. Yang, and F. Guarin. Device scaling and application trends for over 200GHz SiGe HBTs. Proc. International SiGe Technology and Device Meeting, pp. 51–52 (2003).

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6 Passive Components 6.1 6.2 6.3

Introduction......................................................................... 6-1 Resistors and Capacitors..................................................... 6-3 Inductors and Transformers............................................... 6-4 Inductors on Silicon Substrates . Integrated Transformers

6.4 6.5 6.6

Transmission Lines ............................................................ 6-10 Diodes and Switches ......................................................... 6-10 Special Passive Components............................................. 6-11

6.7

Summary ............................................................................ 6-12

Joachim N. Burghartz Delft University of Technology

6.1

Emerging Passives . Suppression of Parasitic Effects

Introduction

Passive components (e.g., resistors, capacitors, inductors, and transformers) and passive devices (e.g., varactors, Schottky diodes, and pin diodes) are integral parts of the functioning and performance of radio-frequency (RF) building blocks [1]. They are used for impedance matching and transformation, in filters, in resonators, in delay lines and baluns, and for many other purposes. In RF front-end circuits they often outnumber the active device count. Unlike in the past, bipolar/BiCMOS and CMOS technologies for communications are limited today to a large extent by the quality and cost of those passive components and devices. Modern wireless communication products increasingly contain integrated passives, i.e., passive components that are engineered by exploiting the structures and materials of the device integration process itself. This is in contrast to the hybrid RF systems that have been used in RF communications for a long time. The reason behind the trend toward integration is not only cost reduction but also the small inductance (0.5 to 10 nH) and capacitance (100 to 1 pF) values needed in the current RF circuits operating at >>1 GHz. The parasitic inductances, capacitances, and resistances of the interconnects are then becoming comparable in value to those of the passive component itself, thus generally lowering the quality of that component. Also, such interconnects with all associated parasitics have to be carefully considered in the circuit design making that task extremely difficult. Placement of passive components off chip into the package or onto the printed circuit board (PCB) as a coplanar waveguide (CPW), a microstrip, or a discrete element is no longer an option as RFs are >1 GHz. Chip integration of passives, however, raises other concerns [2]. At frequencies in the range of about 900 MHz to 2.4 GHz, the inductance and capacitance values needed are considerably large (e.g., for a 50-V impedance; see Figure 6.1), thus occupying excessive chip real estate. Since that chip area is cycled through the entire transistor fabrication process on-chip inductors and capacitors are expensive. The total area taken by the inductors can in some circuits occupy nearly 50% of the total chip area. An option, which is sometimes used at frequencies near 1 GHz, is the simulation of a large capacitance or a large inductance by active circuitry. That technique, however, has the disadvantage that it generally leads to higher power and noise. The task of integrating inductors and capacitors is simpler at elevated RF, at which comparably smaller values of inductance and capacitance are required. Figure 6.1 illustrates that near 15 GHz, however, inductance values as low as 0.5 nH are needed to represent a 50-V impedance on 6-1

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Too large size!

Too small inductance value! Too long transmission line!

2

10

1.5 l = λ/4

1

1

l (mm)

L (nH); C (pF)

wL = 50 W

0.5 1/wC = 50 W 0.1

0

10

20

30

40

50

0

f (GHz)

FIGURE 6.1 Inductance and capacitance values needed to represent a 50 V impedance. Microstrip length required for a l/4 transmission line. (From JN Burghartz, KT Ng, NP Pham, B Rejaei, and PM Sarro. Proceedings of the Device Research Conference, 2001, pp. 113–114. With permission.)

chip. Beyond about that value on-chip inductors face the same virtue as their in-package counterparts did at about 1 GHz, i.e., their inductance becomes comparable to that of the interconnects feeding signals into them. At frequencies >15 GHz one, therefore, would like to use inductors and capacitors in a distributed form, i.e., by using CPWs or microstrips, as one used to do on PCB at low RF. In contrast to the lumped passive elements, which had to be smaller than l/10, such transmission line structures need to have a physical size of at least l/4 [3]. That means that the concerns with the size of the on-chip passive components suddenly become stressed again with that migration from lumped to distributed component design. Only at frequencies >30 GHz RF circuit design based on integrated microstrips or CPWs starts to become economically feasible (Figure 6.1). In spite of the simplicity of the illustrations in Figure 6.1, it becomes obvious that the frequency range from 15 to 30 GHz requires the RF engineer’s ingenuity to be able to come up with solutions to the integration of passive components [4]. In addition to the issue of chip area, any extra process steps required for the integration of the passive components and devices have to be taken into consideration. In a SiGe fabrication process, preference will likely be given to such passive component and device structures that can be integrated by exclusively using process elements from the bipolar transistor integration process (Table 6.1). Since most silicon RF integration schemes today are BiCMOS processes, with the SiGe HBT merged into a logic CMOS

TABLE 6.1 Types of Passive Components and Devices Listed with the Device Integration Processes, in Which They Most Efficiently Can Be Realized Type of Passive Component

Bipolar

CMOS

Add-On

Resistor Capacitor Varactor Diode RF Switch Inductor Transformer Transmission line Resonator or filter

Polysilicon Interdigitated PN Junction

Implanted MOS MOS

Thin Film MIM MEMS Schottky

PN MOS-FET PIN; MEMS Spiral Shielded Spiral Spiral: stacked; bifilar; nested Microstrip; coplanar waveguide LC; SAW

MEMS; FM Core FM Core Micromachined MEMS; BAW

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6-3

process, the range of such ‘‘free’’ passive components can greatly be expanded, as Table 6.1 shows. Nevertheless, there are special passives that require additional process steps or materials. They are adopted if more economic solutions are not satisfactory to the RF circuit designer or if they are instrumental in overcoming a design bottleneck.

6.2

Resistors and Capacitors

Resistors and capacitors have been a part of silicon fabrication processes for a long time. Resistors are used in bipolar circuits for dc biasing purposes and metal–oxide–silicon (MOS) capacitors are freely available in CMOS and BiCMOS processes. Resistors can be integrated in three basic forms, i.e., as an implanted or diffused component, as a polysilicon resistor, and as a thin-film metal element (Table 6.1). In bipolar processes sheet resistances ranging from 10 to 10,000 V/sq. can be realized by exploiting either the diffused regions (buried layer, intrinsic base) or the polysilicon films (extrinsic base, emitter). In BiCMOS processes, the well and channel stopper diffusions can also be used in order to cover the sheet resistance range from 100 to 1000 V/sq. Implanted and diffused resistors, however, are not well suited for RF circuit design because the junction isolation leads to a considerably large-shunt capacitance that is bias dependent. Polysilicon resistors work better in that respect since they are separated from the silicon substrate by the field oxide, leading to a much smaller shunt capacitance. The sheet resistance of doped polysilicon, however, varies with the polygrain structure and the dopant distribution between grains and grain boundaries. This results in a typically much larger statistical variation of the sheet resistance compared to implanted or diffused resistors [5]. The best results can be achieved with metal thin-film resistors that are imbedded into the multilevel interconnect stack [6] by, however, investing an extra masks layer and additional process steps (Table 6.1). The good electrical isolation of poly and metal thinfilm resistors from the silicon substrate, however, causes that such resistors are also thermally isolated due to the poor thermal conductivity of the SiO2. A small temperature coefficient is therefore another aspect in selecting the optimum resistor structure for RF applications. Capacitors can be integrated as an interdigitated metal structure, an MOS structure, or a metal– insulator–metal (MIM) structure. The interdigitated capacitor is adopted from III-V monolithic microwave integrated circuit (MMIC) technology, where it is useful since often only one interconnect layer is available. Since this is not an issue in silicon technology and because the capacitance or area is very small in comparison to that of the MOS and the MIM capacitors, the interdigitated capacitor is not used in SiGe MMICs. MOS capacitors have the same disadvantage as the mentioned implanted or diffused resistors, i.e., a considerable portion of the RF signal flows through the silicon substrate. Also, one terminal is built in silicon causing a relatively high series resistance, thus lowering the quality of the RF capacitor. Nevertheless, MOS capacitors have the comparably highest capacitance/area so that they are used in special applications, such as for dc blocking. The most favorable RF capacitor is the MIM structure since both terminals are built in metal and the structure has good oxide isolation from the substrate. A lumped-element model of an MIM capacitor is shown in Figure 6.2. The figure-of-merit of an RF capacitor is the quality factor (Q), which is defined as the ratio of the stored and the dissipated energies, i.e., QC ¼ im(Z)/re(Z), with Z the impedance of the component. It is obvious that the Q-factor will become lower as the frequency is increased, because the impedances of the lumped capacitors drop with frequency so that an increasing fraction of the total energy applies to dissipation at the resistors (see Figure 6.2). A second concern is self-resonance. The resonance frequency (fSR) is set by the parasitic series inductance LS and (primarily) CP and should be sufficiently larger than the desired operating frequency. Apart from the types and thicknesses of metal and dielectric layers available with a particular fabrication process layout optimization is effective in optimizing for Q and fSR [7]. Figure 6.3 illustrates that a finger layout with a high aspect ratio leads to both an increased Q and a higher fSR. A multifinger layout rather than one single finger can be used to best fit the MIM capacitor into the RF circuit layout. Another issue, besides layout optimization, is the accurate compact modeling of the capacitor. Figure 6.4 shows an example of the optimum 1.3-pF MIM capacitor layout from Figure 6.3, which is well applicable up to 10 GHz. The compact model with parameters shown in the insert of

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CP

P1

LS COx

CB

P2

RS RP

RB

COx RB

CB

Sub*

FIGURE 6.2 Compact model of an integrated capacitor. (From JN Burghartz, M Soyuer, KA Jenkins, M Kies, M Dolan, KJ Stein, J Malinowski, and DL Harame. IEEE Journal of Solid-State Circuits 32:1440–1445, 1997. With permission.) 100

MIM Capacitors: Areas from 10⫻194 mm2 to 80⫻24.5 mm2

4 3

80

Finger ratio increase

Q

60 40

2 1

Quality factor

Capacitance (pF)

5

20

C 0

0 0

2

4

6

8

10

Frequency (GHz)

FIGURE 6.3 Measured capacitances and quality factors of multifinger MIM capacitors with varied finger aspect ratios. (From JN Burghartz, M Soyuer, KA Jenkins, M Kies, M Dolan, KJ Stein, J Malinowski, and DL Harame. IEEE Journal of Solid-State Circuits 32:1440–1445, 1997. With permission.)

Figure 6.4 is derived from the general MIM capacitor model in Figure 6.2 with simplifications by neglecting RP and CB.

6.3

Inductors and Transformers

Inductors on Silicon Substrates Design and Compact Modeling Inductors, in contrast to capacitors and resistors, are fairly new passive components in silicon technology. In 1990, Nguyen and Meyer [8] were the first to place a spiral coil (Figure 6.5) over a conductive, and thus lossy, silicon substrate. The Q of a spiral inductor (QL ¼ þim(Z)/re(Z)) hardly reached Q ¼ 5 in the early attempts in spite of extensive knowledge in spiral inductor design from III-V MMICs and PCB implementations. As rough guidelines, the ratio of outer (R) to inner (Ri) coil radius should be R/Ri ¼ 5 for a maximum Q value and the maximum radius should not exceed l/60 to avoid distributed effects [3]. The fact that in silicon technology the inductor coil is placed over a conductive substrate is the main cause of the difficulties to reach appropriate Qs. The primary parameter set to define a spiral inductor on silicon (without the underpath) thus includes the conductor width (W) and space (S), the number of turns (N), the coil radius (R), the metal thickness (TM) and resistivity (rM), the thickness (TOx) and permittivity («Ox) of the dielectric layer between coil and silicon, and the resistivity (rSi), permittivity («Si), and thickness (TSi) of the silicon substrate (Figure 6.5). In addition, the specifications

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6-5

Passive Components

100

10 0.04nH

MIM-Cap

0.7Ω

1.37 pF

Capacitance (pF)

6

0.026pF 15Ω

60

Sub

40

Q 4 C

2

Quality factor

80

8

20

0

0 2

0

4

6

8

10

Frequency (GHz)

FIGURE 6.4 Measured and modeled frequency dependence of capacitance and quality factor of an optimized multifinger MIM capacitor (model with parameters in inset). (From JN Burghartz, M Soyuer, KA Jenkins, M Kies, M Dolan, KJ Stein, J Malinowski, and DL Harame. IEEE Journal of Solid-State Circuits 32:1440–1445, 1997. With permission.) N rM

eOx TM R TOx

TSi

W

S

rSi, e Si

FIGURE 6.5 Cross section of a spiral inductor on silicon, defined by the width (W) and space (S) of the metal conductor, the number of turns (N), the outer radius of the coil (R), the metal resistivity (rM), the metal thickness (TM), the distance of the spiral coil from the silicon substrate (TOx), the oxide permittivity («Ox), the thickness of the silicon substrate (TSi), and the permittivity («Si) and resistivity (rSi) of the silicon. (From JN Burghartz and B Rejaei. IEEE Transactions on Electron Devices 50:718–729, 2003; JN Burghartz, M Soyuer, and KA Jenkins. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

of the underpath that connects the inner coil terminal to the outside have to be considered, though play a minor role in most designs. The limitation in Q is a result of ohmic losses and parasitic capacitances in the coil and in the substrate, as illustrated in the compact model in Figure 6.6. There, the electrical characteristics of the spiral coil are represented by LS*, RS, and CP. The dielectric isolation between coil and substrate is modeled by COx, and the substrate is described by RB and CB. The elements LE, RE, and M are used to illustrate the effect of eddy currents in the substrate, which become noticeable only for a high silicon conductivity. The resistor RSub describes the effect of a planar substrate contact on the inductor characteristics. First, we discuss the situation for RSub ! 1 (no substrate contact) and RE ! 1

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CP POut COx RSub CB

PIn

R LS*=LS−M S M

COx

LE−M RE RShield

RB

RB

CB

Sub Sub*

FIGURE 6.6 Compact model of an integrated inductor. (From JN Burghartz and B Rejaei. IEEE Transactions on Electron Devices 50:718–729, 2003; JN Burghartz, M Soyuer, and KA Jenkins. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

25

60 Qmax

sse

rate

15

los

ses

10

f(Qmax)

5

L

10 0 0

Quality factor

bst

il lo

30 20

20 Su

s

40

Co

Inductance (nH)

50

1

2 3 Frequency (GHz)

4

5

0

FIGURE 6.7 Inductance and quality factor of an integrated inductor versus frequency. (From JN Burghartz and B Rejaei. IEEE Transactions on Electron Devices 50:718–729, 2003; JN Burghartz, M Soyuer, and KA Jenkins. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

(no substrate eddy currents, i.e., M ¼ 0; LS* ¼ LS). If a low-frequency bias is applied between the inductor terminals (POut, PIn in Figure 6.6) the RF signal primarily passes through the inductance LS and the resistance RS, because the impedance vLS is small and the impedances 1/vCP and 1/vCOx are large. The quality factor increases then as Q ¼ vLS/RS, which is shown in Figure 6.7. With increasing frequency a larger fraction of the RF signal passes through the substrate since vLS becomes larger, 1/vCOx becomes smaller, and because COx >> CP (TOx << R). As a result, a maximum Q-factor (Qmax) appears at a particular frequency f (Qmax), as shown in Figure 6.7. It is obvious that the inductor design should aim for optimizing Qmax at the operating frequency, i.e., f0 ¼ f (Qmax), through tailoring coil and substrate losses. Furthermore, self-resonance should occur sufficiently above f (Qmax). This can be achieved by preventing from resonance via COx so that the much smaller CP leads to a high fSR, as achieved for the sample 10-nH inductor in Figure 6.7. The metal losses in the spiral coil can be lowered by shunting several layers of the multilevel interconnects together to arrive at an effectively thicker conductor, as first shown by Soyuer et al. [9,10]. Local thickening of the top metal layer is another economic means to reduce the coil losses [11]. Other design concepts address the skin effect that leads to an increased coil resistance at increased frequency. While the skin effect from the magnetic field caused by the current through a conductor itself cannot significantly be reduced, the skin effect from a magnetic field caused by current flow through a neighboring conductor can well be minimized. The latter effect is experienced as crowding of the current to the conductor edges. That means that at high RF a large conductor width (W) may not be as effective as a

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Passive Components

sufficient conductor spacing (S). Furthermore, eddy currents can be caused in particular in the inner metal turns so that hollow coils [12] or smaller conductor width at the inner turns [13] can result in reduced losses. The coil design also affects the interturn capacitance (CP1) and the capacitance between spiral coil and underpath (CP2), which both contribute to CP ¼ CP1 þ CP2 that affects the fSR of the inductor. The coil design discussed so far has been restricted to a spiral coil consisting of a continuous metal conductor at the same interconnect layer. By alternating between interconnect layers less current crowding [14] and a higher resonance frequency [15] can be achieved particularly for large inductances. Also, multilayer inductor structures, providing higher inductance/area figures then become feasible [16,17]. Substrate Effects and Shields The substrate resistivity can have distinct effects on the inductor characteristics, as illustrated in Figure 6.8 for a simulated 2-nH inductor, varying only the silicon resistivity. For resistivities above 10 V cm both Qmax and f (Qmax) increase steadily toward higher resistivity. This so-called ‘‘inductor mode’’ of operation relates to what we had discussed above and the sample inductor in Figure 6.7. In the range of 0.1 to 10 V cm the component operates in the ‘‘resonator mode’’ because then self-resonance occurs via the substrate, i.e., COx. With COx >> CP, fSR shows a pronounced decay, which causes that fSR >> f (Qmax) is no longer valid and the component operates as a resonator rather than an inductor. That means, however, that the design direction becomes distinctly different. Now, not an increase but a

Resonator mode regime

Eddy current regime

Inductor mode regime

x 5

L (Q max) (nH)

(a)

20

Qmax

10

f(Qmax)

0

0

6

25

5

20

4

fSR

15 L(Q max)

3

10

2

5

1 0 0.001 (b)

fSR (GHz)

Qmax

10

f (Qmax) (GHz)

30

15

0 0.1

10

1000

Silicon resistivity (Ω-cm)

FIGURE 6.8 Maximum quality factor (Qmax), frequency at Qmax (f (Qmax)), inductance (L(Qmax)), and resonant frequency (fSR) of an integrated inductor as a function of substrate resistivity with indication of the three characteristic modes of operation. (From JN Burghartz and B Rejaei. IEEE Transactions on Electron Devices 50:718–729, 2003; JN Burghartz, M Soyuer, and KA Jenkins. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

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reduction in substrate resistivity leads to a higher Qmax. The Q of the resonator namely depends on both the qualities of the lossy inductor coil (QL ¼ vLS/RS) and the lossy oxide capacitor (QC ¼ 1/vRBCOx). The QC is increased by lowering the substrate resistivity and thus RB. It can be seen from Figure 6.8 that, surprisingly, somewhat higher Qmax values can be achieved in comparison to a 10 V cm substrate resistivity, particularly if eddy currents in the substrate can be suppressed. (Note that these three modes of operation of a spiral coil structure are closely related, but not identical, to the TEM, slow wave, and eddy current modes of a microstrip as described by Hasegawa et al. [18].) While eddy currents cannot, or at least not easily, be suppressed in the low-resistivity silicon, operation in resonator mode with suppressed eddy currents can be enforced by inserting a patterned ground shield in between the spiral coil and the silicon substrate [19]. Figure 6.9 shows the Qmax and the fSR of the 2-nH inductor (from Figure 6.8) with a patterned ground and the shield resistivity as the only parameter, showing that Qmax can be raised by 50% while sacrificing fSR. The effect of a patterned ground shield can be modeled by the resistor RShield in the compact model of Figure 6.6. Inductor Optimization The optimization of inductors on silicon is extensively discussed in a review paper by Burghartz and Rejaei [20]. In Figure 6.10, the Qmax values achievable for a wide range of inductances are shown for a conventional Al metallization and substrate resistivity for thick Cu interconnects in combination with high-resistivity silicon (HRS). There is a general trend that large inductance values combine typically with considerably lower Qs than small inductances. This is a result of the larger area needed to accomplish large inductances and the consequently lower impedance of the substrate leakage path (COx, CB, RB in Figure 6.6). Another consequence is that with larger inductance values Qmax appears at a lower frequency f (Qmax). This does not appear to be an issue in RF circuit design since at higher frequencies the required inductance values are smaller and the Qs needed are larger. The last feature from Figure 6.6 to be discussed is the effect of a substrate contact. Clearly, a uniform ground potential underneath the inductor coil would provide the best possible electrical symmetry of the component, except for the small geometrical asymmetry of the coil itself [21]. In silicon technology, however, only planar substrate contacts can be used to bias the silicon substrate. It has been shown that, if such a planar substrate contact is positioned close to the coil, the inductor would become electrically

40

16 Eddy currents QMax No eddy currents

30 fSR

8

20

4

10

fSR (GHz)

12 Qmax

rSi = 10 Ω-cm

rShield 0 0.0001

0.01

1

100

0 10,000

Shield resistivity (Ω-cm)

FIGURE 6.9 Maximum quality factor (Qmax) and resonant frequency (fSR) of an integrated inductor with patterned ground shield as a function of the resistivity of the shield metal. (From JN Burghartz and B Rejaei. IEEE Transactions on Electron Devices 50:718–729, 2003; JN Burghartz, M Soyuer, and KA Jenkins. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

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Passive Components

Maximum quality factor

100 SAM

4 µm Cu+ 3 kΩ-cm Si

10

1µm Al+ 5 Ω-cm Si 1 1

10 Inductance (nH)

100

FIGURE 6.10 Maximum quality factor (Qmax) versus inductance of spiral inductors built in a conventional aluminum interconnect process or with copper metallization on a high-resistivity silicon substrate. (From JN Burghartz and B Rejaei. IEEE Transactions on Electron Devices 50:718–729, 2003; JN Burghartz, M Soyuer, and KA Jenkins. IEEE Transactions on Electron Devices 43:1559–1570, 1996. With permission.)

asymmetric. The substrate contact thus has to be considered in the circuit layout [22]. Only an RF ground plane underneath the coil can eliminate this asymmetry, provided that the ground plane is spaced away sufficiently to prevent from eddy current effects [23,24]. That sensitivity of the inductor characteristics to eddy currents in nearby metal features also prevents one from placing other circuit components inside the large spiral coil or from building the coil over other circuitry [25], except if micromachining techniques are adopted (Section 6.6). Accurate modeling of the spiral inductor structure is another important task. While the compact model in Figure 6.6 is already sufficiently accurate, it has the restriction of being nonpredictive. An extensive review of predictive inductor models [26–29] is included in Ref. [30].

Integrated Transformers Transformers have been used in RF circuits since the early days of telegraphy. Conceptually, a transformer consists of two spiral coils that are brought in close proximity to achieve mutual magnetic coupling. Figure 6.11 shows the three generic types of transformers that are conceivable, i.e., the stacked (Finlay) type, the bifilar (Shibata resp. Frlan) type, and the nested coil type [31,32]. The mutual coupling, which is a first indication of quality of a transformer, is higher for the stacked coils than that of the bifilar structure, which again is higher than that of the nested coils [32]. The strong mutual coupling, however, also results in a large parasitic capacitance between the coils, which affects the bandwidth of the transformer by making the mutual coupling of the coils partly capacitive. The maximum available gain (Gmax), as used for RF transistors [3], is a useful figure-of-merit of a transformer [32], since it is independent of the port impedances. A good transformer should obviously have both high Gmax and large bandwidth. In that respect, the stacked coils provide the best results in comparison, followed by the bifilar and the nested types [33]. Stacked coils also consume minimum chip area but require three interconnect layers instead of two needed to fabricate the other types. Obviously, if capacitive coupling between the coils has a detrimental effect on the transformer Gmax and bandwidth, substrate effects will play a considerable role and will degrade the transformer in both aspects [32]. Substrate effects are minimum for the stacked coil configuration. Interestingly, a patterned metal ground shield can provide a slightly increased Gmax and bandwidth [32]. The bifilar coil type is most suitable for the design of multifilament, balun, and symmetric transformers, as extensively discussed in a review paper by Long [31] and in a book by Niknejad and Meyer [34].

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Bifilar coils (Shibata)

Stacked coils (Finlay)

Nested coils Bifilar coils (Frlan)

FIGURE 6.11 Plan view sketches of generic transformer structures. (From JR Long. IEEE Journal of Solid-State Circuits 35:1368–1382, 2000. With permission.)

6.4

Transmission Lines

At frequencies beyond about 30 GHz inductances and capacitances have to be integrated as distributed elements (Figure 6.1). This requires the fabrication of transmission lines on a lossy silicon substrate either as a CPW or as a microstrip. Both types of lines have been used on PCB or in III–V MMICs. In silicon technology, however, CPWs suffer from considerable losses in the conductive silicon substrate and microstrips are difficult to integrate due to lack of a through-substrate via process in conventional silicon technology. During the past decade these issues have been circumvented and addressed, respectively, by building microstrips in the multilevel interconnects away from the substrate [35] and by fabricating CPWs over HRS [36]. The small vertical spacing of signal and ground planes of microstrips built in the multilevel interconnects leads to a comparably narrow required width of the signal line, thus raising ohmic losses and the overall attenuation of the line. A wider signal line for reduced losses is feasible if the ground plane is integrated into the silicon substrate. This, however, requires micromachining techniques [37] (see also Section 6.6). In that case, as for the CPWs, HRS substrates have to be used to suppress the losses in the silicon. Then, particularly for the CPW, the passivation of the silicon near the Si–SiO2 interface is crucial to be able to minimize those losses [38]. The attenuation figures achieved for transmission lines on silicon substrates are in the range of 2 to 5 dB/cm at 10 GHz, depending on the metal type and thickness and on the silicon resistivity. With the passivation the attenuation can be about tenfold improved.

6.5

Diodes and Switches

There are several types of diodes that can be applied in RF and microwave applications. Varactors are used, for example, in voltage-controlled oscillators (VCO) and can be built as pn-junction [7] and MOScapacitor type components [39]. The pn-junction varactor can directly be derived from the collector– base junction structure of the bipolar transistor. The component can be modeled by using the scheme in Figure 6.2. The challenge in integrating a varactor on a silicon substrate is to achieve a maximum capacitance/area with minimum parasitic resistances and inductances of the terminals and the internal metallization, leading to a multifinger structure as the optimum layout of the component [7]. For

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Passive Components

60

5 A= 2 ⫻ 15 ⫻ 27.75 µm2

4 Capacitance (pF)

Varactor (pn junction): 50 40

3 30

Bias increase

2

C 20

1

Quality factor

Q

10

0 0

2

4 6 Frequency (GHz)

8

0 10

FIGURE 6.12 Measured capacitances and quality factors of multifinger pn-junction MIM capacitors with varied reverse bias. (From JN Burghartz, M Soyuer, KA Jenkins, M Kies, M Dolan, KJ Stein, J Malinowski, and DL Harame. IEEE Journal of Solid-State Circuits 32:1440–1445, 1997. With permission.)

varactors used in the 900 MHz to 2.4 GHz range the multifinger design provides Qs in the range of 20 to 50 (Figure 6.12), which is quite sufficient considering the limited Qs of the inductors in the LC tank of the VCO. Diodes, more specifically p–i–n diodes, are used in RF switches, particularly the transmit– receive (T–R) switch at the antenna of the RF transceiver [40]. A p–i–n diode works as a bias-controlled resistor with excellent linearity and distortion and has also been applied in microwave circuits to amplitude modulation, attenuation, and signal leveling. In addition to their use in RF switches, they also make excellent phase shifters and limiters [3]. The integration of p–i–n diodes in silicon processes, however, is difficult since they are typically built as vertical devices by exploiting the entire wafer thickness. Therefore, as the MESFET switch in III–V technology, it is possible to consider MOSFET switches in silicon technology, but they have an inferior insertion loss and isolation and they consume more chip area compared to their III–V contenders [41]. The third type of switch device that is considered for silicon technology is the MEMS switch [42], which appears to be only a technological option in applications where the p–i–n and MOS switches cannot meet the required specifications. A third type of diode that is well integratable in silicon technology is the Schottky rectifier, which can reach cutoff frequencies well in excess of 100 GHz [3,43].

6.6

Special Passive Components

Emerging Passives With the trend toward fully monolithic RF transceivers novel materials and structures are now introduced to silicon technology. Introducing them as an addition to the core device integration process is a favorable concept for economic reasons [44]. Micromachining and MEMS can be used to greatly increase the quality of passive components [37,45,46] or to integrate large components above [46] or below the active devices into the bulk silicon substrate [37]. Micromachining can also be used to establish an RF ground plane in silicon process technology [37] (see ‘‘Substrate Effects and Shields’’). The enhancement in component quality is quite pronounced in mechanical resonators [47], mechanically variable capacitors [48], and RF MEMS switches (Section 6.5). Ferromagnetic thin films can be instrumental in reducing the size of inductors and transformers and to realize novel-integrated RF passive components [49,50]. The integration of bulk-acoustic wave filters

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[51] and tunable passives becomes possible by using ferroelectric thin films on silicon [52]. In this way, other microwave components known from the hybrid technologies may be brought to silicon technology by exploiting integratable ferromagnetic and ferroelectric thin films [49]. On-chip antenna is another passive component that may gain significance in the emerging fields of integrated microwave sensors [53], unobtrusive radio devices [54], and for intrachip [55] and chip–chip signal transmission [56].

Suppression of Parasitic Effects In addition to the desired passive components there are parasitic effects that affect the characteristics of an integrated RF circuit. RF currents through the electrically conducting silicon substrate [37], electromagnetic coupling between integrated inductors and to the package [23,25], and thermal coupling through the silicon [57] are such parasitic effects that are undesirable since they are difficult to model and are detrimental to the circuit performance. Such parasitic effects, therefore, have to be carefully considered in the circuit layout [58]. Isolation techniques available with conventional silicon process technology, however, are not sufficiently effective at RF and microwaves [59]. Novel structures to block or to ground such crosstalk signals between RF circuit elements are therefore required. Availability of an RF ground plane with a via connection to the wafer frontside is, therefore, a valuable addition to any RF silicon integration process (see also Section 6.4) [37]. In addition to the unwanted crosstalk signals to an RF ground, crosstalk can also be lowered to some extent by increasing the silicon substrate resistivity and the spacing between source and drain of the parasitic RF signals. Overly, high substrate resistivity, however, does not provide any benefit as far as the crosstalk goes, since then the substrate characteristics are fully capacitive and in TEM mode [18,60]. Then, local replacement of the silicon by a lowpermittivity material will have the effect of a virtual increase of the length of the crosstalk path. This can, for example, be achieved by etching trenches through the entire substrate [37].

6.7

Summary

In this chapter, we have given a broad overview of the passive components and devices required for RF silicon integration processes. The discussion has been restricted to passives that are integrated on the chip, but with highlighting the criteria that favor the integration of passive components over off-chip or in-package solutions. The effect of parasitics on the quality and the characteristics of passive components, as well as on the coupling between passives, have been addressed as well. Among the passive components and devices, the spiral inductor on silicon has particularly been highlighted in the discussions, because this component is still fairly new to silicon technology, it limits the performance and power consumption of RF circuits, and it consumes a considerable fraction of the costly chip area. The discussion of other passive components and devices, as well as of parasitic effects, has been kept brief but combined with an extensive reference list. All in all, it can be stated that passive components and devices are an integral, if not dominant, part of monolithic RF silicon technology.

Acknowledgments The author would like to thank his colleagues at the Laboratory of High-Frequency Technology and Components (HiTeC) at DIMES, TU Delft, and his former colleagues at IBM Research and IBM Microelectronics for the many stimulating discussions on aspects of RF silicon technology. This applies particularly to Dr. Behzad Rejaei (HiTeC), Dr. Mehmet Soyuer (IBM), and Dr. Keith Jenkins (IBM).

References 1. LE Larson. Silicon technology tradeoffs for radio-frequency/mixed-signal ‘‘systems-on-a-chip.’’ IEEE Transactions on Electron Devices 50:683–699, 2003.

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2. JN Burghartz. Silicon RF technology—The two generic approaches. Proceedings of the European Solid-State Device Research Conference (ESSDERC), 1997, pp. 143–153. 3. I Bahl and P Barthia. Microwave Solid State Circuit Design. New York, NY: John Wiley & Sons, 1988. 4. JN Burghartz, KT Ng, NP Pham, B Rejaei, and PM Sarro. Integrated RF passive components— discrete vs. distributed. Proceedings of the Device Research Conference, 2001, pp. 113–114. 5. A Schuppen, H Dietrich, S Gerlach, H Hohnemann, J Arndt, U Seller, R Gotzfried, U Erben, and H Schumacher. SiGe-technology and components for mobile communication systems. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 1996, pp. 130–133. 6. R Henderson, P Zurcher, A Duvallet, C Happ, M Petras, M Raymond, T Remmel, D Roberts, B Steimle, S Straub, T Sparks, M Tarabbia, and M Miller. Tantalum nitride thin film resistors for integration into copper metallization based RF-CMOS and BiCMOS technology platforms. Digest of Papers of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2001, pp. 71–74. 7. JN Burghartz, M Soyuer, KA Jenkins, M Kies, M Dolan, KJ Stein, J Malinowski, and DL Harame. Integrated RF components in a SiGe bipolar technology. IEEE Journal of Solid-State Circuits 32:1440–1445, 1997. 8. NM Nguyen and RG Meyer. IC-compatible inductors and LC passive filters. IEEE Journal of SolidState Circuits 25:1028–1031, 1990. 9. M Soyuer, JN Burghartz, KA Jenkins, S Ponnapalli, JF Ewen, and WE Pence. Multilevel monolithic inductors in silicon technology. Electronics Letters 31:359–360, 1995. 10. JN Burghartz, KA Jenkins, and M Soyuer. Multi-level-spiral inductors using VLSI interconnect technology. IEEE Electron Device Letters 17:428–430, 1996. 11. JN Burghartz and B Rejaei. Saddle add-on metallization for RF-IC technology. IEEE Transactions on Electron Devices 51:460–466, 2004. 12. J Crols, P Kinget, J Craninckx, and M Steyaert. An analytical model of planar inductors on lowly doped silicon substrates for high frequency analog design up to 3 GHz. Digest of Technical Papers of the Symposium on VLSI Circuits, 1996, pp. 28–29. 13. JM Lopez-Villegas, J Samitier, C Cane, and P Losantos. Improvement of the quality factor of RF integrated inductors by layout optimization. Technical Digest of the Radio Frequency Integrated Circuits (RFIC) Symposium, 1998, pp. 169–172. 14. LF Tiemeijer, D Leenaerts, N Pavlovic, and RJ Havens. Record Q spiral inductors in standard CMOS. Technical Digest of the International Electron Devices Meeting (IEDM), 2001, pp. 949–951. 15. HB Erzgra¨ber, M Pierschel, GG Fischer, T Grabolla, and A Wolff. High performance integrated spiral inductors based on a minimum AC difference voltage principle. Digest of Technical Papers of the Silicon Monolithic Integrated Circuits in RF Systems, 2000, pp. 71–74. 16. JN Burghartz, KA Jenkins, and M Soyuer. Multi-level-spiral inductors Using VLSI interconnect technology. IEEE Electron Device Letters 17:428–430, 1996. 17. RB Merrill, TW Lee, Y Hong, R Rasmussen, and LA Moberly. Optimization of high Q integrated inductors for multi-level metal CMOS. Technical Digest of the IEEE International Electron Devices Meeting, 1995, pp. 983–986. 18. H Hasegawa, F Mieko, and Y Hisayoshi. Properties of microstrip line on Si–SiO2 system. IEEE Transactions on Microwave Theory and Techniques 19:869–881, 1971. 19. CP Yue and SS Wong. On-chip spiral inductors with patterned ground shields for Si-based RF ICs. IEEE Journal of Solid-State Circuits 33:743–752, 1998. 20. JN Burghartz and B Rejaei. On the design of RF spiral inductors on silicon. IEEE Transactions on Electron Devices 50:718–729, 2003. 21. JN Burghartz, M Soyuer, and KA Jenkins. Integrated RF and microwave components in BiCMOS technology. IEEE Transactions on Electron Devices 43:1559–1570, 1996. 22. JN Burghartz, AE Ruehli, KA Jenkins, M Soyuer, and D Nguyen-Ngoc. Novel substrate contact structure for high-Q silicon-integrated spiral inductors. Technical Digest of the IEEE International Electron Devices Meeting, 1997, pp. 55–58.

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23. JN Burghartz. Progress in RF inductors on silicon-understanding substrate losses. Technical Digest of the International Electron Devices Meeting, 1998, pp. 523–526. 24. KT Ng, NP Pham, PM Sarro, B Rejaei, and JN Burghartz. Characterization of a bulk-micromachined post-process module for silicon RF technology. Digest of Papers of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2000, pp. 99–102. 25. JN Burghartz, DC Edelstein, M Soyuer, HA Ainspan, and KA Jenkins. RF circuit design aspects of spiral inductors on silicon. IEEE Journal of Solid-State Circuits 33:2028–2034, 1998. 26. JR Long and MA Copeland. Modeling of monolithic inductors and transformers for silicon RFIC design. In Microwave Symposium Digest (Technologies for Wireless Applications), 1995, pp. 129–134. 27. CP Yue, C Ryu, J Lau, TH Lee, and SS Wong. A physical model for planar spiral inductors on silicon. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1996, pp. 155–158. 28. AM Niknejad and RG Meyer. Analysis, design, and optimization of spiral inductors and transformers for Si RF Ics. IEEE Journal of Solid-State Circuits 33:1470–1481, 1998. 29. B Rejaei, JL Tauritz, and P Snoeij. A predictive model for Si-based circular spiral inductors. Digest of Papers of the Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 1998, pp. 148–154. 30. JN Burghartz. Spiral inductors on silicon—Status and trends. International Journal of RF and Microwave Computer-Aided Engineering 8:422–432, 1998. 31. JR Long. Monolithic transformers for silicon RF IC design. IEEE Journal of Solid-State Circuits 35:1368–1382, 2000. 32. KT Ng, B Rejaei, and JN Burghartz. Substrate effects in monolithic RF transformers. IEEE Transactions on Microwave Theory and Techniques 50:377–383, 2002. 33. KT Ng, B Rejaei, TR deKruiff, M Soyuer, and JN Burghartz. Analysis of generic spiral–coil RF transformers on silicon. IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2000, pp.103–107. 34. AM Niknejad and RF Meyer. Design, Simulation, and Applications of Inductors and Transformers for Si RF ICs. Dordrecht, The Netherlands: Kluwer Academic Publishers, 2000. 35. DC Laney, LE Larson, P Chan, J Malinowski, D Harame, S Subbanna, R Volant, and M Case. Microwave transformers, inductors and transmission lines implemented in an Si/SiGe HBT process. IEEE Transactions on Microwave Theory and Techniques 49:1507–1510, 2001. 36. HH Meinel. Millimeter-wave technology advances since 1985 and future trends. IEEE Transactions on Microwave Theory and Techniques 39:759–767, 1991. 37. NP Pham, PM Sarro, KT Ng, and JN Burghartz. IC-compatible two-level bulk micromachining process module for RF silicon technology. IEEE Transactions on Electron Devices 48:1756–1764, 2001. 38. B Rong, JN Burghartz, LK Nanver, B Rejaei, and M vanderZwan. Surface-passivated high-resistivity silicon substrates for RFICs. IEEE Electron Device Letters 25:176–178, 2004. 39. WMY Wong, PS Hui, C Zhiheng, S Keqiang, J Lau, and PCH Chan. A wide tuning range gated varactor. IEEE Journal of Solid-State Circuits 35:773–779, 2000. 40. RH Caverly. RF technique for determining ambipolar carrier lifetime in PIN RF switching diodes. Electronics Letters 34:2277–2278, 1998. 41. RH Caverly. Linear and nonlinear characteristics of the silicon CMOS monolithic 50-V microwave and RF control element. IEEE Journal of Solid-State Circuits 34:124–126, 1999. 42. GM Rebeiz. RF MEMS: theory, design, and technology. New York, NY: John Wiley & Sons, 2003. 43. KM Strohm, J Buechler, and E Kasper. SIMMWIC rectennas on high-resistivity silicon and CMOS compatibility. IEEE Transactions on Microwave Theory and Techniques 46:669–676, 1998. 44. JN Burghartz, M Bartek, B Rejaei, PM Sarro, A Polyakov, NP Pham, E Boullaard, and KT Ng. Substrate options and add-on process modules for monolithic RF silicon technology. Proceedings of the 2002 Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2002, pp. 17–23.

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45. KJ Herrick, JG Yook, and LPB Katehi. Microtechnology in the development of three-dimensional circuits. IEEE Transactions on Microwave Theory and Techniques 46:1832–1844, 1998. 46. JB Yoon, YS Choi, BI Kim Y Eo, and E Yoon. CMOS-compatible surface-micromachined suspendedspiral inductors for multi-GHz silicon RF Ics. Electron Device Letters, IEEE 23:591–593, 2002. 47. JR Clark, WT Hsu, and CT Nguyen. High-Q VHF micromechanical contour-mode disk resonators. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2000, pp. 493–496. 48. M Bakri-Kassem and RR Mansour. Two movable-plate nitride-loaded MEMS variable capacitor. IEEE Transactions on Microwave Theory and Techniques 52:831–837, 2004. 49. B Rejaei, M Vroubel, Y Zhuang, and JN Burghartz. Assessment of ferromagnetic integrated inductors for Si-technology. Digest of Papers of the topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2003, pp. 100–103. 50. MG Allen. MEMS technology for the fabrication of RF magnetic components. IEEE International Magnetics Conference, 2003, pp. FC-05. 51. M Ylilammi, J Ella, M Partanen, and J Kaitila. Thin film bulk acoustic wave filter. IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control 49:535–539, 2002. 52. KA Jose, H Yoon, KJ Vinoy, P Sharma, VK Varadan, and V Varadan. Low voltage tunable capacitors for RF MEM filters and antenna applications. Digest of the International Symposium on Antennas and Propagation, Vol. 3, 2001, pp. 670–673. 53. P Russer. Si and SiGe millimeter-wave integrated circuits. IEEE Transactions on Microwave Theory and Techniques 46:590–603, 1998. 54. E Aarts. Ambient intelligence: A multimedia perspective. IEEE Multimedia 11:12–19, 2004. 55. BA Floyd, H Chih-Ming Hung, KK O. Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters. IEEE Journal of Solid-State Circuits 37:543–552, 2002. 56. JJ Lin, L Gao, A Sugavanam, X Guo, R Li, JE Brewer, and KK O. Integrated antennas on silicon substrates for communication over free space. IEEE Electron Device Letters 25:196–198, 2004. 57. BM Tenbroek, MSL Lee, W Redman-White, RJT Bunyan, and MJ Uren. Impact of self-heating and thermal coupling on analog circuits in SOI CMOS. IEEE Journal of Solid-State Circuits 33:1037– 1046, 1998. 58. T Blalack, Y Leclercq, and CP Yue. On-chip RF isolation techniques. Proceedings of the Bipolar/ BiCMOS Circuits and Technology Meeting, 2002, pp. 205–211. 59. KA Joardar. A simple approach to modeling cross-talk in integrated circuits. IEEE Journal of SolidState Circuits 29:1212–1219, 1994. 60. M Pfost, HM Rein, and T Holzwarth. Modeling substrate effects in the design of high-speed Si-bipolar Ics. IEEE Journal of Solid-State Circuits 31:1493–1501, 1996.

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7 Industry Examples at the State-of-the-Art: IBM

Alvin J. Joseph and James S. Dunn IBM Microelectronics

7.1

7.1 7.2 7.3 7.4 7.5 7.6

Introduction......................................................................... 7-1 BiCMOS Process Integration ............................................. 7-1 The SiGe HBT—Key Technology Elements ...................... 7-5 Electrical Performance ........................................................ 7-6 Manufacturability .............................................................. 7-12 Summary ............................................................................ 7-16

Introduction

The general market acceptance of SiGe BiCMOS technologies can be attributed to the ability to address the product performance at a very competitive cost by integrating high-performance SiGe HBTs, with state-of-the-art CMOS, and high-quality passives. SiGe HBTs have shown to be highly reliable even under extreme stress conditions [1,2] and give superior yields compared to other compound semiconductor technologies (e.g., GaAs). It is not surprising, therefore, to see SiGe BiCMOS technologies in mass production that range in various applications, such as wireless, storage, and instrumentation [3,4]. SiGe BiCMOS technologies offer the flexibility to be optimized based on the specific market applications. For example, performance focus applications such as wired, automotive, and instrumentation require ultrahigh-performance SiGe HBTs. Integrating a simplified low-cost SiGe HBT is the focus, however, for consumer applications such as wireless and storage. Therefore, a ‘‘one size fits all’’ approach for technology optimization will not be optimal to address various market segments due to significant tradeoffs one has to make on either performance or cost. The IBM SiGe BiCMOS technology roadmap addresses these wide-ranging applications by offering two flavors of SiGe HBTs. State-of-the-art examples of IBM SiGe BiCMOS technologies at 0.13 mm CMOS node will be discussed in detail in this section. SiGe BiCMOS 8HP is a technology which features a 200/275 GHz (fT/fmax) SiGe HBT with passives and back-end-of-the-line (BEOL) metallurgy tailored for applications in the 77 GHz range. Technology optimization in this case centers around the performance of the SiGe HBT. SiGe BiCMOS 8WL technology features a 100/200 GHz (fT/fmax) SiGe HBT with 0.5 dB minimum noise figure (NFMIN) at 10 GHz with wide range of active and passive devices that support cost-sensitive consumer applications. In this case, the technology optimization focus shifts to reducing process complexity (or cost) while maintaining adequate SiGe HBT performance.

7.2

BiCMOS Process Integration

The state-of-the-art BiCMOS process integration approach falls into the category of a base-after-gate (BAG) method, where the base of the SiGe HBT is built after the bulk of the CMOS processing is completed 7-1

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BiCMOS 8HP 0.13 µm CMOS Backbone

Shallow trench

BiCMOS 8WL

Bipolar

Subcoll., Nepi, Deep Trench

0.13 µm CMOS Backbone

Shallow trench

Coll. reachthru Well I/I, Gate ox, Gate Poly dep/pattern/ etch, sidewall ox., spacer, CMOS protect layer

S/D implant, anneal, Resistor salicide block

Base window, collector pedestal, UHV/CVD SiGe base, emitter definition, raised Xbase, ISD poly emitter dep, pattern and etch, Xbase pattern and etch

Well I/I, Gate ox, Gate Poly dep/pattern/ etch, sidewall ox., spacer, CMOS protect layer

Subcollector I/I Base window, UHV/CVD SiGe base, emitter definition, raised Xbase, ISD poly emitter dep, pattern and etch, Xbase pattern and etch

S/D Implant, anneal, Resistor salicide block Custom trench

Salicide and contacts Salicide and contacts

Metal interconnect Custom analog metals

FIGURE 7.1

Bipolar

Metal interconnect

Custom analog metals

Process flow comparing both BiCMOS 8HP and BiCMOS 8WL in a 0.13 mm CMOS backbone.

[5]. This approach is chosen to minimize the thermal budget for the SiGe HBT. Figure 7.1 shows the integration flows utilized in the 0.13 mm IBM SiGe BiCMOS processes. Both 8HP and 8WL process flow use the 0.13 mm CMOS backbone with the addition of bipolar and custom BEOL analog metals. Process flows deviate between 8HP and 8WL due to the tradeoff associated with the bipolar performance. The process flow starts with the formation of the NPN subcollector and the appropriate SiGe HBT isolation scheme. For the 200 GHz fT SiGe HBT in 8HP, critical process elements include a very lowresistance buried subcollector, n-type epitaxy formation, collector reach-through, and deep-trench isolation. In contrast, the 100 GHz fT SiGe HBT in 8WL does not require such process components and can be easily replaced by an implanted subcollector. After such processing sequence, the wafer in each case essentially looks like a standard CMOS processed wafer and can be put through the exact same processing sequence without any significant perturbation to the base CMOS process flow. Both BiCMOS flows then proceed with the standard CMOS processing steps: well implants, single and dual gate oxidations, gate poly deposition or pattern or etch, sidewall oxidation, LDD and extension implants, and finishing with the spacer formation. Essentially, bulk of the CMOS processing is completed with only the source–drain implant and activation remaining. There are multiple reasons for postponing the source–drain implants till after the bipolar formation—(a) the phosphorus (n-FET) and boron (pFET) dopants utilized for advanced CMOS tend to diffuse through the gate with additional lowtemperature cycles from the bipolar processing, (b) these implants can be used for the contact regions of parasitic active or passive devices built using bipolar elements, and (c) preserve modularity with the single activation RTA that can activate the CMOS and bipolar emitter. It should be noted that while the ‘‘BAG’’ approach reduces the thermal cycle for SiGe HBTs, it shifts the process challenge to clearing bipolar films from CMOS regions as well as requiring some re-engineering of CMOS well/extension/LDD implants for parametric centering. Prior to moving into the SiGe HBT build, the CMOS regions are protected by an etch stop layer that can later be easily removed. The bipolar module is extensively the same between 8HP and 8WL, with minor differences in the collector tailor implants and SiGe base profile. Structurally, both devices look quite similar and utilize advanced concepts of raised extrinsic base [6,7] as well as fully realigned in situ doped emitter processing [8,9] (see Figure 7.2). The bipolar module begins by defining a bipolar window opening by etching through a seed polysilicon and dielectric stack. Afterwards, the nonselective epitaxial growth of the

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Industry Examples at the State-of-the-Art: IBM

In situ doped emitter

Dielectric Isolation Silicide

Raised extrinsic base Boron-Doped SiGe base Collector Reachthrough plug Trench isolation

SIC collector Subcollector

FIGURE 7.2

Cross-sectional diagram of a raised extrinsic base SiGe HBT device.

UHV/CVD SiGe base region is completed. The raised extrinsic base with heavily doped p-type is then introduced. This provides a low-resistance linkup to the intrinsic base as well as much-reduced collector–base capacitance (CCB) for the SiGe HBT. The emitter–base junction is completed by the formation of an emitter opening with inside spacers, and then depositing an in situ doped polysilicon realigned emitter. The emitter polysilicon is then patterned and etched followed by the pattern or etch of the base polysilicon. The process challenge resides in the careful choice of an etch stop CMOS protect layer and the isotropic polysilicon etch that can clear all residual bipolar films from the CMOS gate topography. The CMOS protect layer is then removed for the source–drain implant and activation RTA. In the case of 8WL, prior to salicidation, a custom trench is etched around the NPN to reduce the collector–substrate capacitance. The trench is later filled with the contact dielectric and planarized. This allows minimum perturbation to the BiCMOS flow, while providing significant performance advantage for HBTs with negligible cost addition. The process sequence then moves into cobalt salicidation, contact formation, and BEOL metallization. Figure 7.3 shows a top view SEM of a static RAM cell built in 8HP, showing a clean CMOS integration that is possible with the 0.13 mm BiCMOS integration scheme. High-quality passive elements such as precision resistor, MIMcap, inductors, along with varactor, Schottky, and PIN diodes are integrated in a modular fashion to make technology attractive for various applications. Table 7.1 shows a comparative look at the various passive elements offered in 8HP and 8WL. Multiple resistors are available that range in sheet resistance, TCR, parasitic capacitance to substrate, and tolerance. For example, low TCR (<100 ppm/8C) and tight tolerance of less than 10% (3s) are achieved by the low-value polyresistor. Optimization of devices such as MIM capacitors and varactors varies from 8HP to 8WL due to the targeted applications. For example, the 8HP varactor is optimized for a Q value of 10 at 77 GHz, while the 8WL varactor is optimized for high-tuning range as well as linearity with Q >100 at 5 GHz. High-density MIM capacitors are required in wireless application to reduce the area consumed by precision capacitors that typically range from 1 to 10 pF. A high-k dielectric MIM capacitor has been developed in 8WL that is capable of 5 f F/mm2 density with high reliability of 10 ppm failure rate at 5 V for a

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Metal-1 Contact

Polygate

FIGURE 7.3 Top view scanning electron micrograph of a static RAM built using 0.13 mm groundrules and fully compatible with foundry CMOS integrated in BiCMOS 8HP.

TABLE 7.1

Passive Devices Offered in Both 8HP and 8WL Technologies

Resistors Diffused (n-type—ohms/sq.) Poly (p-type—ohms/sq.) Metal (TaN—ohms/sq.) Capacitors Hyper-abrupt varactor (VA ¼ 0 to 3 V) MOS varactor (VG ¼ 1 to 1 V) MIMcap (fF/mm2) Decoupling (fF/mm2) Inductor AM with M1 groundplane Dual Cu with M1 groundplane Diodes Schottky barrier (Vf at 100 uA in mV) ESD protection

BiCMOS 8HP

BiCMOS 8WL

8.8, 73 340, 1700 60

73 220, 340, 1700 60

3.6:1 tuning 6:1 tuning 1 11

4:1 tuning 6:1 tuning 5 11

Q ¼ 19; L ¼ 1 nH Q ¼ 22.5; L ¼ 1 nH — Yes

350 Yes

total device area of 106 mm2 at 100 K power-on-hours (see Figure 7.4). This MIM capacitor is compatible with both Al and Cu BEOL integration as a modular element and does not require any changes to the standard BEOL processes to achieve high reliability. Due to the high frequency requirements in 8HP, the MIM capacitor is mostly limited by the minimum geometry possible as opposed to density. For example, to get 50 V impedance for applications in 60 to 80 GHz range, the MIM capacitor geometry of approximately 50 mm2 is reasonable to control if a 1.0 f F/mm2 capacitance density is utilized. The requirements for metallization also diverge due to the targeted application space for 8HP and 8WL. Clearly, the lower levels of metal wiring are required for tight-pitch CMOS integration that enables chip size reduction for system-on-chip integration trends observed in wireless applications. Analog metal above the standard CMOS wiring is needed to address several parameters such as inductor Q, transmission line, and wireability. In the case of 8HP, a standard 4-mm thick Al metal wire separated by at least 10 mm from metal-1 supports the 77 GHz transmission lines. This single metal scheme, however, is not optimal for varied wireless applications due to the cost and complexity considerations. In 8WL, therefore, multiple analog metal options are offered to address performance and cost tradeoffs. Figure 7.5 compares various options offered in 8WL relative to 8HP and base CMOS technology. Thick single and dual damascene Cu levels with tight pitch are utilized in 8WL to lower the wire and via resistance as well as to reduce the inductor footprint.

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100 K µm2 single MIM capacitor

109

100KPOH

108

Time (s) to failure

107 106 105 104 103 102

Fit 1 PPM 10 PPM 100 PPM

101 100

6

8 10 12 Stress voltage (V)

14

16 18 20

FIGURE 7.4 A state-of-the-art MIM capacitor built using high-k dielectric with density of 5.0 fF/mm2 and a lifetime of 100K POH at 9.0 V. This device is integrated into the 8WL Cu BEOL metallurgy.

0.13 µm CMOS

8HP

8WL Option 1

8WL Option 2

8WL Option 3

AM

Al

RF/Analog module

EZ Cu

LY

E1

E1 LM

2X 2X 1X 1X 1X 1X

Standard CMOS ASIC Layers

FIGURE 7.5 Cross-sectional sketch of the BEOL metals in 0.13 mm BiCMOS technologies relative to the base CMOS configuration. Analog metal modules are kept thick to improve the inductor performance.

7.3

The SiGe HBT—Key Technology Elements

In this section, we discuss the key process modules that undergo optimization depending on the technology of choice, i.e., 8HP or 8WL. Primarily, we focus on the subcollector, base–emitter regions, and bipolar isolation. In order to attain the lowest collector resistance, high-performance transistors typically employ buried subcollector with an epi growth. In addition, collector epilayer thickness allows one to tune fT as well as

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allow for multiple breakdown voltage devices. This technique is employed in 8HP to achieve 200 GHz fT. For transistors where subcollector resistance is not the performance limiter, one can easily replace with an implanted subcollector, leading to a much simplified processing [10]. The desired subcollector offset, such as that attained by epitaxial layer growth, is set by the implantation depth and reduction to channeling tails. Special process considerations, such as resist profile and postimplant annealing, need to be employed for ensuring manufacturability. By using various layout techniques one can reduce the total collector resistance and improve fT, without compromising on the processing complexity. The best achievable sheet resistances from both these methods differ by at least an order of magnitude, at the expense of complexity or wafer cost. This difference results in an acceptable but modest peak-fT reduction (<15 GHz) that can somewhat be recovered by using specialized collector layouts [11]. Typically, there are multiple variants of SiGe HBTs in any one technology that are attained by optimizing the collector profile. The maximum breakdown voltage SiGe HBT achievable in any technology will be set by the choice of the subcollector. In order to attain high-performance (HP) SiGe HBT one needs to reduce the vertical distance from the subcollector to base profile by adjusting the epi thickness, which limits the achievable breakdown voltage for the high-breakdown (HB) SiGe HBT. In order to increase the breakdown voltage of HB SiGe HBT, particularly used in power amplifiers and storage preamps, one needs to add additional masks to create an independent subcollector. An intermediate or medium performance (MP) SiGe HBT can be achieved by adding an implant mask to form selectively implanted collector (SIC) profile. In the case of SiGe 8WL, this implant is shared with CMOS well implant to obtain a 65 GHz HBT with no added mask cost. The SiGe base profile is engineered with a Ge ramp profile, with Ge peak concentration around 25% to minimize the base transit time. One can engineer the Ge ramp profile to tradeoff between fT (tE / 1/b / 1/Ge-ramp; tB / 1/Ge-ramp), current gain (b), and breakdown voltage (BVCEO / 1/b). For 8HP, the Ge ramp is made steeper than 8WL resulting in b-difference of two times and BVCEO difference of 0.7 V in a HP SiGe HBT. A carbon-doped narrow base boron profile is used in both technologies to minimize the basewidth. The undoped emitter and collector silicon cap thickness are adjusted for both technologies to attain the appropriate emitter–base and collector–base delay times. The extrinsic base link is formed by an in situ doped raised extrinsic base approach that allows one to reduce rbb simultaneously with CCB, and is utilized in both 8HP and 8WL. Polysilicon emitter is yet another module that has seen processing advances in the recent past. As one scales the transistor performance, the increase in emitter resistance (RE) and current gain (b) due to the presence of the emitter poly–Si interfacial oxide becomes unacceptable. Therefore, the advanced state-ofthe-art technologies use in situ doped polysilicon emitters to form a recrystallized mono emitter interface [12]. This method significantly reduces RE, brings b to a useful range, as well as improves fT. Both 8HP and 8WL technologies take advantage of this process element for improved SiGe HBT performance. Bipolar isolation in 8HP is achieved by using both shallow and deep trenches. The shallow-trench process in 8HP and 8WL is similar to the base CMOS process. The deep trench in 8HP is polyfilled and planarized with process commonality maintained to previous generation production SiGe BiCMOS technologies (e.g., 0.18 mm). This deep-trench isolation feature is not only utilized for bipolar collector– substrate capacitance (CCS) reduction, but, also under the passive elements to reduce substrate coupling. The integration of such a deep trench adds more complexity and wafer cost that is not warranted in 8WL. For desired CCS reduction, if one substitutes the deep trench with traditional simple junction isolation the HBT footprint becomes significant. In 8WL, therefore, a custom deep-trench isolation has been employed for HBTs to optimize performance and cost.

7.4

Electrical Performance

The centerpiece of the BiCMOS technology is the SiGe HBT that enables the frequency performance. SiGe HBTs have shown sevenfold improvement in fT performance since its first introduction in the 0.5 mm production technology (see Figure 7.6). Both lateral- and vertical-scaling techniques are

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400 Next generation Cutoff frequency (GHz)

350 300 250 0.13 µm

200

0.18 µm

150 100

0.5 & 0.25 µm

50 0 0.01

0.1

1

10

100

Collector current density (mA/mm2)

FIGURE 7.6

SiGe HBT performance scaling over multiple technologies.

employed to reduce transit times and parasitics to boost fT/fmax performance. One aspect of the vertical scaling is to reduce base push out by increasing collector-doping concentration. This increases the collector current density required at peak-fT. However, by shrinking the emitter dimension proportionately one can obtain significant improvement in fT at the same collector current or reduce the power level required for the same fT. For example, at 1 mA of collector current, one can achieve an fT of 275 GHz using a 0.11 mm device compared to 43 GHz for a 0.42 mm SiGe HBT. Figure 7.7 shows the Gummel characteristics of both HP and HB SiGe HBTs built in 8HP technology. Devices show ideal behavior over several decades of currents, which is clearly reflected in the current gain (see Figure 7.8). As expected, the high-injection Ge-induced barrier effects are clearly visible in MP and HB devices due to the lower collector doping and early onset of the Kirk effect compared to highperformance SiGe HBT. It should be noted that the retrograde Ge profiles are designed to minimize the parasitic barriers and allow maximum fT prior to the Kirk effect. The output characteristics for HP, MP, and HB devices in both 8HP and 8WL technologies are shown in Figure 7.9 and Figure 7.10. High early voltage is attained for all devices over a 1 V voltage swing (VCE). The fT performance of various flavors of SiGe HBTs with minimum emitter width built in 8HP technology is shown in Figure 7.11. The fT and fmax are extracted from jh21j and jUj measured at 20 GHz and extrapolated with an ideal slope of 20 dB/decade, respectively. The HP transistor achieves 200 GHz at 5.0 mA of collector current for a 0.12 3 mm2 emitter transistor. With additional collector adjustment masks for the MP and HB transistors one can achieve 115 and 50 GHz, simultaneously on a wafer. The HP device also shows a reasonable fT performance over a wide temperature range (0 to 1258C) as seen in Figure 7.12. The peak-fT performance increases from 170 GHz at 1258C to 226 GHz at 08C, with very minor change to the peak-fT current density. One can also observe that the operating collector current reduces by two times at a fixed fT of 120 GHz over 1258C temperature range, primarily due to the temperature dependence of the emitter–base charging time as well as the current gain. In contrast to HBT optimization for peak-fT/fmax performance as in 8HP, the focus shifts to the optimization of power, noise-figure, linearity, breakdown voltage, etc., for the 8WL SiGe HBTs. The key transit time and parasitic reduction elements from the 8HP HBT are shared wherever possible and tradeoffs made on process modules that can lead to significant cost benefits for marginal performance improvement. One example of this study with the collector sinker has shown that the extra collector resistance introduced by replacing the collector reachthrough module in 8HP with available standard CMOS n-type implants reduces the peak-fT by only 3 GHz. This result combined with the subcollector

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1 ⫻ 10−1

Collector and base currents (A)

1 ⫻ 10−2 1⫻

10−3

BiCMOS 8HP AE = 0.12 ⫻ 3.0 µm2 VCB = 0.5 V

1 ⫻ 10−4 1 ⫻ 10−5 1 ⫻ 10−6 1 ⫻ 10−7 1 ⫻ 10−8 1 ⫻ 10−9 1 ⫻ 10−10

HP HB

1 ⫻ 10−11 1 ⫻ 10−12 0.4

0.5

0.6

0.7

0.8

0.9

1

Base−emitter voltage (V)

FIGURE 7.7

Gummel characteristics of BiCMOS 8HP high-performance and high-breakdown SiGe HBTs. 650 600

HP MP HB

550 500 Current gain

450 400 350 300 250 200 150 100 50

BiCMOS 8HP AE = 0.12 ⫻ 3.0 µm2 VCB = 0.5 V

0 1⫻10−9 1⫻10−8 1⫻10−7 1⫻10−6 1⫻10−5 1⫻10−4 1⫻10−3 1⫻10−2 1⫻10−1 Collector current (A)

FIGURE 7.8

Current gain for the three flavors of SiGe HBTs built in BiCMOS 8HP.

optimization data indicates the potential to fabricate very high-performance, state-of-the-art NPN devices, in a low-complexity process. Figure 7.13 shows the fT versus IC curves for three different SiGe HBTs fabricated on an 8WL wafer with optimized implanted subcollector process to meet a wide range of breakdown voltage requirements: a HP device with 96 GHz/2.35 V BVCEO, a MP device with 67 GHz/3.1 V BVCEO, and a HB device with 46 GHz/4.7 V BVCEO. These devices have a BVCBO of 10.4, 14, and 18.6 V, respectively. In general, the devices are not operated in the breakdown bias conditions such as BVCBO or BVCEO. However, these conditions represent the extremity of the NPN operation. The general relationship of breakdown voltage and fT for various SiGe HBTs that span several generations of technologies is plotted in Figure 7.14. This

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6⫻10−4 5⫻10−4 Collector current (A)

HP MP HB

BiCMOS 8HP 2 AE = 0.12 ⫻ 3 µm

4⫻10−4 3⫻10−4 2⫻10−4 1⫻10−4

0⫻100 0

FIGURE 7.9

0.5

1

1.5 2 2.5 Collector-emitter voltage (V)

3

3.5

4

Output characteristics of HP, MP, and HB devices built in BiCMOS 8HP technology.

6⫻10−4 BiCMOS 8WL AE = 0.12 ⫻ 4 µm2

Collector current (A)

5⫻10−4

HP MP HB

4⫻10−4 3⫻10−4 2⫻10−4 1⫻10−4

0⫻100

FIGURE 7.10

0

0.5

1

1.5 2 2.5 3 3.5 Collector-emitter voltage (V)

4

4.5

5

Output characteristics of HP, MP, and HB devices built in BiCMOS 8WL technology.

relationship suggests that the operating margin exceeding 5.5 V can be achieved with a 100 GHz SiGe HBT, with the margin dropping only to 7 V for a 350 GHz SiGe HBT. The fMAX behavior for HP and HB devices is shown in Figure 7.15. The rbb and CCB reduction possible with the raised extrinsic base approach leads to superior fMAX performance for all HBTs, with obvious improvement seen for 8HP devices compared to 8WL over all bias ranges. We expect that the improved fMAX performance will lead to improved NFMIN performance, primarily due to the reduction in rbb. The NFMIN for 8WL shows a comparable performance to 8HP over a wide range of frequencies with 0.23 dB at 2.4 GHz and only upto 1.5 dB at 20 GHz (Figure 7.16 and Figure 7.17). These performance numbers for 8WL compare favorably with previous generation wireless technologies at 0.5 mm and 0.18 mm nodes (Figure 7.18).

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Cutoff frequency (GHz)

Fabrication of SiGe HBT BiCMOS Technology

FIGURE 7.11

220 200 180 160 140 120 100 80 60 40 20 0 0.1

BiCMOS 8HP VCB = 0.5 V

High performance 2 AE = 0.12 ⫻ 3.0 µm

Medium performance 2 A E = 0.12 ⫻ 2.5 µm

High breakdown 2 AE = 0.12 ⫻ 2.5 µm

1 10 Collector current density (mA/mm2)

100

fT characteristics of HP, MP, and HB devices built in BiCMOS 8HP technology.

240 Cutoff frequency (GHz)

220 200

T = 0⬚C, 25⬚C, 55⬚C, 85⬚C, 125⬚C

180 160 140 120 100 BiCMOS 8HP A E = 0.12 ⫻ 3 µm2 V CB = 0.5 V

80 60 40 1⫻10−4

FIGURE 7.12

1⫻10−3 Collector current (A)

1⫻10−2

Temperature dependence of fT for the HP SiGe HBT in BiCMOS 8HP technology.

Cutoff frequency (GHz)

120 100

High performance

80 Medium performance

60 40 High breakdown

20 0 0.01

FIGURE 7.13

BiCMOS 8WL AE = 0.12 ⫻ 4 µm2 VCB = 1.0 V

0.1 1 Collector current (mA)

10

fT characteristics of HP, MP, and HB devices built in BiCMOS 8WL technology.

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Industry Examples at the State-of-the-Art: IBM

Peak cutoff frequency (GHz)

400 350 300 250 200 150

BVCBO limited

100

BVCBO limited

50 0 0

10 15 Breakdown voltage (V)

20

25

The general fT and breakdown voltage relationship for various SiGe HBTs. Unilateral maximum power gain frequency (GHz)

FIGURE 7.14

5

350 HP HB VCB = 1.0 V

300 250

BiCMOS 8HP

200 150 100 50

BiCMOS 8WL

0 0.01

0.1

1

10

100

Collector current density (mA/mm2)

FIGURE 7.15

fMAX characteristics of HP and HB devices built in 8HP and 8WL technologies. 2.5 8HP 8WL

NFMIN (dB)

2 20 GHz 1.5 1 10 GHz 0.5 2 GHz 0 0

FIGURE 7.16

2

4 6 8 Collector current (mA)

10

12

NFMIN as a function of collector current for HP devices in 8HP and 8WL technologies.

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Fabrication of SiGe HBT BiCMOS Technology

2.5 8HP 8WL

NFMIN (dB)

2 1.5 1 0.5 0 0

FIGURE 7.17

5

10 15 20 Frequency (GHz)

25

30

NFMIN for HP devices built in 8HP and 8WL over a wide range of frequencies.

Minimum noise figure (dB)

3 10 GHz 2.5

5HP: AE = 0.5 ⫻ 20 ⫻ 2 µm2

2 7WL: AE = 0.24 ⫻ 20 ⫻ 2 µm2

1.5 1 0.5

8WL: AE = 0.12 ⫻ 32 µm2

0 0.1

1 Collector current (mA)

10

FIGURE 7.18 NFMIN characteristics of 8WL HP device compared to the previous generation wireless technologies at 0.18 and 0.50 mm nodes.

Industry-standard foundry-compatible CMOS devices at 1.2 and 2.5 V are offered in both 8HP and 8WL. In addition to these basic FETs, 8WL includes devices tailored for analog- and mixed-signal applications, such as 3.3 V/5.2 nm gate oxide analog transistors with a gate length of 0.4 mm, zero-VT transistors etc. Triple well nFETs with 2.1 and 5.2 nm gate oxide are also supported in the BiCMOS technologies. RF layouts are developed for the FETs to provide accurate substrate resistance values and wiring parasitics. The 1.2 V/1.5 V 2.1 nm gate oxide logic FETs have gate length of 0.92 mm while the 2.5 V/5.2 nm thick oxide I/O driver FETs have a gate length 0.21 mm. Figure 7.19 and Figure 7.20 show the VTsat versus Idsat scatter plots demonstrating equivalence of the CMOS parameters in the BiCMOS and 0.13 mm base CMOS technologies.

7.5

Manufacturability

For a stable manufacturable technology, it is important that the technology demonstrates adequate parametric control as well as yield over large quantities of lots processed over time. In this section, we present some key manufacturability data that provide insight into the state-of-the-art 8HP technology.

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600

I d Saturation (mA)

580 560 540 520 500 480 8SF 8HP 8WL 460 440 270

290

310

330 350 370 V t Saturation (mV)

390

410

FIGURE 7.19 Thin oxide nFET characteristics in 8HP and 8WL compared to the base 0.13 mm foundry CMOS technology showing good agreement on VTIdsat relationship.

−130 −140

I d Saturation (mA)

−150 −160 −170 −180 −190 −200

8SF

8HP

8WL

−210 −220 −450

−400

−350 V t Saturation (mV)

−300

−250

FIGURE 7.20 Thin oxide pFET characteristics in 8HP and 8WL compared to the base 0.13 mm foundry CMOS technology showing good agreement on VTIdsat relationship.

Figure 7.21 shows the parametric distribution of base–emitter voltage (VBE) measured at 10 mA of emitter current for 0.12 2.5 mm2 HP transistor for a large sample size of lots processed during technology qualification. This normal distribution shows a 0.7% one-sigma variability, signifying good process control for the emitter–base junction depth as well as the base profile including LTE Ge ramp. For the collector–base control, we show in Figure 7.22, the histogram of BVCBO measured at 10 mA for a 0.12 2.5 mm2 HP device on a significantly larger sample size of lots. Data indicate that a tight control of the collector–base junction is possible (one-sigma of 1.3%). We expect that the tight control of the CB profile will also improve the avalanche, fT, CCB, and fMAX performance. The AC performance is sampled (five chips per wafer) routinely to understand the stability of peak-fT/ fmax by measuring s-parameters using a 110 GHz HP analyzer. Figure 7.23 shows the fT and fMAX over a

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Fabrication of SiGe HBT BiCMOS Technology

30

25

Percent

20

15

10

5

N Mean Sigma Minimum 1st Ptile 5th Ptile 10th Ptile 25th Ptile Median 75th Ptile 90th Ptile 95th Ptile 99th Ptile Maximum LSL Target USL % Low

677 727.1496 5.297336 705.6565 711.6716 717.5469 720.4985 724.3328 727.4758 730.3022 733.6274 735.5154 739.8247 742.6243 701 726 751 0

% Yield % High Cp Cpk

100 0 1.573118 1.50078 65.81932

Normal X2

0 700.5

709.5

718.5

727.5

736.5

745.5

754.5

Test M1 8211 309 TX6 FVEBS 10UA

FIGURE 7.21 Histogram of VBE measured on 0.12 2.5 mm2 HP transistor in 8HP technology, over a large sample size of chips built on multiple lots.

22.5 20.0 17.5 15.0

Percent

4185

N

12.5 10.0 7.5

Mean

5.87393

Sigma

0.078501

Minimum

5.627674

1st Ptile

5.695866

5th Ptile

5.750379

10th Ptile

5.784013

25th Ptile

5.828348

Median

5.869673

75th Ptile

5.912518

90th Ptile

5.963103

95th Ptile

6.01013

99th Ptile

6.122393

Maximum

6.289583

LSL

5.5

Target

5.9

USL

6.3

% Low

5.0

% Yield % High

1.587784

Cpk Normal X2

0 5.475

5.595

5.715

5.835

5.955

6.075

6.195

0 1.698482

Cp

2.5

0 100

2251.166

6.315

Test M1 8211 313 TX6 BVCBO 10UA

FIGURE 7.22 Histogram of BVCBO measured on 0.12 2.5 mm2 HP transistor in 8HP technology, over a large sample size of chips built on multiple wafer-lots.

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320 fMAX

305

Cutoff frequency (GHz)

290 275 260 245

BiCMOS 8HP

230

AE = 0.12 ⫻ 3 µm2 VCB = 0.5 V

fT

215 200 185 170 0

Peak-f T and peak-fmax (GHz), min-Rbb (ohms)

FIGURE 7.23 wafer-lots.

10

20

30

40 Wafer

50

60

70

80

Frequency performance trend chart for HP transistor in 8HP technology, sampled over multiple

130

fT

120 110 100

fMAX

90 80 70

AE = 0.2 ⫻ 6.4 µm2

60

Vcb = 1.0 V

50

rbb

40 30 20 10 0 0

3

6

9

12

15

18

21 Lots

24

27

30

33

36

39

FIGURE 7.24 Frequency performance trend chart for HP transistor in 0.18 mm/120 GHz technology, sampled over multiple lots during past 2 years.

significant quantity of wafers built over time. Clearly, the fT is well controlled and centered around 200 GHz. The average fMAX shows around 280 GHz with a range from 260 to 310 GHz. It should be noted that some of the fMAX variability is due to the extraction error introduced by the sensitivity of the slope in jUj roll-off. A much larger sample size of AC data has been collected over a period of 2 years from the production 120 GHz 0.18 mm SiGe BiCMOS technology as shown in Figure 7.24. Data from close to 40 lots sampled over this significant period of production timeframe indicate stability in the AC performance with all lots meeting specifications. Such a performance control in both these highperformance BiCMOS technologies is a testament to the SiGe epi base process control and the LTE tooling capability.

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Fabrication of SiGe HBT BiCMOS Technology

The yield is routinely measured on every lot for various active devices, contacts, and the BEOL metallurgy. The NPN yield is measured on an array of 2000 transistors connected in parallel, with the combined leakage measurement for EB, CB, and CE junctions performed. The chain is considered to be a fail if any one junction shows a higher than expected leakage. The chain yield for both HP and HB devices in 8HP is shown in Figure 7.25. As expected, the HP transistor has lower yield compared to the HB device due to additional processing. The development of SiGe HBT exposed unique NPN CB yield sensitivity due to the interaction of various processing factors, namely, CMOS RIE etch on bipolar regions, SIC implant, and the LTE processing. This process interaction leads to somewhat depressed yield for NPNs, with HP transistors showing more sensitivity to this mechanism. Data suggest that the yield for NPNs can be improved to well above the 90% by eliminating such sensitivities as typically practiced under volume manufacturing by improved defect learning. Figure 7.26 represents the CMOS, contact, and BEOL yield for the last 15 lots fabricated in 8HP technology. The CMOS yield is measured as a cumulative effect of shorts measured from gate-to-source– drain and gate-to-gate and gate-to-well. Contact yield is measured by looking at open on a series of 40K contacts. BEOL cumulative yield is measured as metal shorts and via opens for all the levels. Overall, the combined parametric control as well as yields for various elements of the technology indicates the manufacturability of the state-of-the-art SiGe BiCMOS technology.

7.6

Summary

The state-of-the-art production SiGe BiCMOS technologies at the 0.13 mm lithography node have been presented. The flexibility of SiGe HBT integration is utilized for tailoring BiCMOS technologies for applications that range from performance-hungry automotive radar to low-cost wireless and storage markets. BiCMOS 8HP and 8WL technologies feature multiple SiGe HBTs that tradeoff fT and breakdown voltage, by optimizing the collector profile through implant masks. CMOS and passive elements are also easily integrated with a fully foundry-compatible Cu BEOL wiring. In addition, we have shown manufacturability data for the 200 GHz SiGe BiCMOS technology, indicating that viability of such technologies in the semiconductor marketplace.

100.0 90.0

NPN 2K chain yield (%)

80.0 70.0 60.0 BiCMOS 8HP 50.0

2K Array

40.0 30.0 20.0 HP HB

10.0 0.0 0

5

10

15

20

25

30

35

Wafers

FIGURE 7.25

NPN chain yield for HP and HB transistors in 8HP technology, sampled over multiple wafer-lots.

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100 90 80

Yield (%)

70 60 50 40 30 20 10 0 1

2

3

4

5

6 CMOS

FIGURE 7.26

7

8 Lots

9

Contact

10

11

12

13

14

15

BEOL

Chain yield data for CMOS, contacts, and BEOL elements in 8HP technology.

Acknowledgments We thank the technology development team in Essex Junction, Vermont and East Fishkill, New York, for their dedication in providing RF, Analog, and Mixed-signal technology solutions. In particular, we greatly appreciate the contributions of Louis Lanzerotti, Xuefeng Liu, Qizhi Liu, David Sheridan, Doug Coolbaugh, Robert Rassel, Jim Slinkman, Bradley Orner, Steve St. Onge, Natalie Feilchenfeld, and Jeffrey Johnson toward the success of this work. Finally, we thank the IBM senior management for their support—Bernie Meyerson, David Harame, Dean Herman Jr., Wally Stein (now retired), and John DiToro—in helping to bring the SiGe BiCMOS solution to the marketplace.

References 1. S. Zhang, J.D. Cressler, S. Subbanna, R. Groves, G. Niu, T. Isaacs-Smith, J.R. Williams, H. Bakhru, P.W. Marshall, H.S. Kim, R.A. Reed. An Investigation of Proton Energy Effects in SiGe HBT Technology. IEEE Transactions on Nuclear Science 49(6):3208–3212, 2002. 2. D.C. Ahlgren, M. Gilbert, D. Greenberg, J. Jeng, J. Malinowski, D. Nguyen-Ngoc, K. Schonenberg, K. Stein, R. Groves, K. Walter, G. Hueckel, D. Colavito, G. Freeman, D. Sunderland, D.L. Harame, B. Meyerson. Manufacturability demonstration of an integrated SiGe HBT technology for the analog and wireless marketplace. Technical Digest of International Electron Device Meeting 1996, December 1996, pp. 859–862. 3. SiGe Review. http://www.epenet.com/Newsletters%20-%20Features/sigerev.htm. 4. 802.11 PRISM products. http://www.conexant.com/products/entry.jsp?id ¼ 28. 5. D.L. Harame, D.C. Ahlgren, D.D. Coolbaugh, J.S. Dunn, G.G. Freeman, J.D. Gillis, R.A. Groves, G.N. Hendersen, R.A. Johnson, A.J. Joseph, S. Subbanna, A.M. Victor, K.M. Watson, C.S. Webster, P.J. Zampardi. Current status and future trends of SiGe BiCMOS technology. IEEE Transactions on Electron Devices 48:2575–2584, 2001. 6. B. Jagannathan, M. Meghelli, K. Chan, Jae-Sung Rieh, K. Schonenberg, D. Ahlgren, S. Subbanna, G. Freeman, 3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay. IEEE Electron Device Letters 24:645–655, 2003. 7. B.A. Orner, Q.Z. Liu, B. Rainey, A. Stricker, P. Geiss, P. Gray, M. Zierak, M. Gordon, D. Collins, V. Ramachandran, W. Hodge, C. Willets, A. Joseph, J. Dunn, J.-S. Rieh, S.-J. Jeng, E. Eld, G. Freeman,

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8.

9.

10.

11.

12.

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D. Ahlgren. A 0.13 mm BiCMOS technology featuring a 200/280 GHz (fT/fMAX) SiGe HBT. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, September 2003, pp. 203–206. S. Jouan, R. Planche, H. Baudry, P. Ribot, J.A. Chroboczek, D. Dutartre, D. Gloria, M. Laurens, P. Llinares, M. Marty, A. Monroy, C. Morin, R. Pantel, A. Perrotin, J. de Pontcharro, J.L. Regolini, G. Vincent, A. Chantre. A high-speed low 1/f noise SiGe HBT technology using epitaxially-aligned polysilicon emitters. IEEE Transactions on Electron Devices 46:1525–1531, 1999. A. Joseph, P. Geiss, X. Liu, J. Johnson, K. Schonenberg, A. Chakravarti, D. Ahlgren, J. Dunn. Emitter resistance improvement in SiGe HBTs. Proceedings of the First International SiGe Technology and Device Meeting, January 2003, pp. 223–224. N. Feilchenfeld, L. Lanzerotti, D. Sheridan, R. Wuthrich, P. Geiss, D. Coolbaugh, P. Gray, J. He, P. Demag, J. Greco, T. Larsen, V. Patel, M. Zierak, W. Hodge, J. Rascoe, J. Trappasso, B. Orner, A. Norris, D. Hershberger, B. Voegeli, S. Voldman, R. Rassel, V. Ramachandiran, M. Gautsch, E. Eshun, R. Hussain, D. Jordan, S. St Onge, J. Dunn. High performance low complexity 0.18 mm SiGe BiCMOS technology for wireless circuit applications. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, September 2002, pp. 197–200. L. Lanzerotti, N. Feilchenfeld, D. Coolbaugh, J. Slinkman, P. Gray, D. Sheridan, J. Higgins, W. Hodge, M. Gordon, T. Larsen, M. Gautsch, P. Lindgren, R. Murty, J. Rascoe, K. Watson, T. Stamper, E. Eshun, J. He, K. Downes, R. Rassel, J. Greco, B. Labelle, S. Sweeney, K. Stein, R. Bolam, K. Vaed, B. Omer, A. Joseph, S. St Onge, J. Dunn. A cost performance 0.13 mm SiGe BiCMOS technology for wireless and mixed signal applications. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, September 2004, pp. 13–14, 237–240. P. Chevalier, C. Fellous, L. Rubaldo, D. Dutartre, M. Laurens, T. Jagueneau, F. Leverd, S. Bord, C. Richard, D. Lenoble, J. Bonnouvrier, M. Marty, A. Perrotin, D. Gloria, F. Saguin, B. Barbalat, R. Beerkens, N. Zerounian, F. Aniel, A. Chantre. 230 GHz self aligned SiGeC HBT for 90 nm BiCMOS technology. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, October 2004, pp. 13–14, 225–228.

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8 Industry Examples at the State-of-the-Art: Jazz 8.1 8.2

Introduction......................................................................... 8-1 SiGe Bipolar Transistor....................................................... 8-2 Fully Self-Aligned Device Structure . SiGe npn Performance . Vertical Scaling . Lateral Scaling

8.3

SiGe BiCMOS Process Integration .................................... 8-7 Integration Sequence . CMOS Thermal Budget . SiGe npn Manufacturability

8.4

Paul H.G. Kempf Jazz Semiconductor

8.1

Process Customization........................................................ 8-9 Wireless Technology . High Data Rate and High-Frequency Technology

8.5

Summary ............................................................................ 8-11

Introduction

The roots of most commercial silicon germanium (SiGe) BiCMOS processes lie in a tradition of bipolar technology developed relatively slowly over multiple generations. Historical progress of traditional bipolar technology was quickly outpaced by CMOS processes in the 1990s with ever-shrinking linewidths in state-of-the-art CMOS fabs. A step-up to 200 mm wafers for BiCMOS technology created a gap between older generation bipolar technologies, which were optimized at a time when the addition of CMOS compromised bipolar performance, and the new generation of BiCMOS technologies that took full advantage of the tool capabilities in an advanced CMOS fab [1,2]. Improved capabilities included better control of thermal steps due to vertical furnaces, new temperature monitoring schemes for rapid thermal annealing, higher selectivity etches for silicon, oxide and nitride, in-line SEM metrology for monitoring of critical structures, and tighter photomask alignment tolerances. Along with this fundamentally improved equipment capability came the development of sophisticated factory automation that made it possible to run multiple process technologies with an increasing number of photomask layers at consistently high fab yield. In this new environment, the bipolar transistor was able to realize the full benefit of the addition of silicon germanium to the base structure because lateral scaling reduced performance-limiting parasitic capacitance and resistance, while thermal budget control enabled manufacturable ultra-shallow junctions that were needed for vertical scaling in high-speed bipolar transistors. Acceleration of the performance curve for SiGe bipolar transistors has once again placed the bipolar device as the highest speed transistor available on silicon [3]. This background explains the foundation of Jazz Semiconductor’s SiGe BiCMOS technology, which was released to production as a high-performance upgrade to a 0.35-mm silicon BiCMOS process in the year 2000 (named SiGe60), and later advanced to an ultra-high-performance bipolar module, with fT 8-1

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and fmax greater than 155 GHz, integrated with standard 0.18-mm CMOS (named SiGe120). As an example of state-of-the-art production technology, this chapter will focus on the unique optimization of the bipolar structure in a 0.18-mm process, provide a summary of its performance characteristics for different device optimizations up to an fT of 200 GHz, discuss BiCMOS integration challenges for 0.18 and 0.13-mm, and detail some of the customization requirements that are an important aspect of overall technology capability.

8.2

SiGe Bipolar Transistor

The first choice that must be made when considering transistor architecture is the overall performance level that needs to be met, which is largely fixed by the set of addressable applications for the technology. A dilemma arises when the end-market for a technology is evolving as quickly as the technology. For example, the wireless world was recently focused on up to 2 GHz carrier frequencies, but has since opened up 5 to 60 GHz as a range of interest for high-speed data and other applications. Development of a transistor capable of addressing a wide range of high-speed applications leads to a device design that does not trade off key parameters for one another.

Fully Self-Aligned Device Structure Rather than extending the quasi-self-aligned bipolar structure from the first generation of Jazz SiGe BiCMOS technology to smaller geometries, compromising base link resistance, emitter width, overlap capacitances, and other parameters, a choice was made to create a new self-aligned bipolar device with balanced performance characteristics and physical attributes that would be compatible with supporting a large variety of products integrated with 0.18-mm CMOS technology and below (Figure 8.1a). Key attributes include low resistance buried layer and substrate epitaxy for collector formation, deep trench

Self-aligned extrinsic base

Final emitter Collector Base Self-aligned base implant

Direct-patterned Sacrificial emitter Blanket SiGe

Buried layer

Deep trench isolation

Intrinsic Link SiGe base base (a)

(b)

Normalized Rb

3 2.5 2 1.5

SA

1

QSA

0.5 0 0 0.1 0.2 0.3 Effective base link width (microns) (c)

FIGURE 8.1 (a) Schematic cross section of the self-aligned SiGe npn transistor. (b) Sacrificial emitter masks the extrinsic base implant. (c) Simulated base resistance at peak fT for self-aligned (SA) versus quasi-self-aligned (QSA) emitter. Error bars show 3-sigma variation.

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isolation, near-planar SiGe epi to polysilicon transition, selective collector implants, scalable emitter width with self-aligned base link implants, low-resistance in-situ doped emitter, and conventional cobalt silicidation [4,5]. The process flow begins with the formation of the buried layer by a high-dose implant and growth of an epitaxial layer. This approach is chosen over use of a high-energy implant to minimize collector resistance and maintain high fT at the low Vce typically employed in small-signal, high-speed applications. It also allows for a wide range of breakdown voltages (BVceo) on the same wafer, which is achieved with different doping levels of the selectively implanted collector (SIC). An optional deep trench is also used to reduce collector–substrate capacitance (Ccs), an important factor in reducing switching delay. The trench is filled with an oxide liner and a polysilicon plug. An oxide-filled shallow trench is also formed, providing a planar surface on which to build the emitter–base structure of the npn bipolar transistor. A blanket SiGe deposition was chosen to support scalable transistor geometries for a wide range of active device area to total wafer area ratios, which is an important capability for a foundry technology that must achieve predictable device performance for a wide variety of circuit layouts. The temperature uniformity that can be achieved across the wafer is superior in the case of a blanket process where similar film stacks are present everywhere during SiGe epi growth. For the base of the drift-field SiGe bipolar transistor, germanium is ramped from 0% near the base–emitter junction to approximately 30% near the collector–base junction, and a very narrow spike of boron is included in the growth sequence. A sacrificial emitter is patterned and spacers are formed to self-align the extrinsic base implants (Figure 8.1b), which enable independent optimization of extrinsic base resistance while maintaining a planar base structure that minimizes link resistance effects between the intrinsic epitaxial base and the extrinsic polycrystalline base contact. The sacrificial emitter is removed and an in-situ doped emitter is deposited such that the dimensions of the sacrificial emitter exactly define the final emitter dimensions. This is in contrast to inside spacer techniques that show greater emitter width variation due to the reduced photo and etch resolution of a slot versus a bar, and on the spacer width variation determined by film thickness and etch uniformity (Figure 8.1c). Also, this technique results in a self-aligned emitter–base without selective epitaxy, versus the approach used in Ref. [6]. Outside spacers on the emitter poly are necessary for selfalignment of the final extrinsic base used for low base contact resistance and for the prevention of a silicide short between emitter and base polysilicon layers. The subsequent cobalt silicide formation, contact etch, and oxide chemical mechanical polish (CMP) are the same as a standard CMOS process. Achieving extremely low emitter resistance is critical in order to achieve high-speed performance and can be especially limiting for emitter areas that can be as small as 0.2 0.7 mm2 in 0.18-mm technology. Components of the emitter resistance include the emitter to silicon interface, the polysilicon resistivity (dependent on grain structure and dopant activation), the cobalt silicide to polysilicon interface, and the standard contact and metal components. The completed device has a small footprint and a planar intrinsic to extrinsic base transition that enables the high performance of the SiGe npn transistor.

SiGe npn Performance Effective optimization of the SiGe npn transistor results in a device with a wide range of applicability. The scalable architecture is used to build production devices with fT of 38, 78 and 155 GHz with nominal BVceo of 6, 3.5 and 2.2 V, respectively. Changes to the collector doping profile and reduced base width extend the same approach to a technology with fT and fmax greater than 200 GHz [7] while maintaining a BVceo of 2.0 V. As shown in Figure 8.2, the gains in the performance of the higher breakdown voltage bipolar devices in each technology have been tracking the high-speed transistor, demonstrating that improvements in the intrinsic device structure have played a significant role in overall SiGe npn performance. While achieving peak fT at modest current density is important for small-signal highspeed circuits, minimum noise figure and low power performance are critical for many RF applications. Benefits derived from low parasitic resistance and capacitance of the Jazz 0.18-mm SiGe bipolar transistor are evident in Figure 8.3 relative to the Jazz 0.35-mm SiGe BiCMOS technology that uses a

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1000 BC35 SiGe60

f T (GHz)

SiGe90/120 SiGe200

100

10 1

FIGURE 8.2

2

3

4 BVceo (V)

5

6

7

fT versus typical BVceo for four generations of Jazz BiCMOS.

200 175

Vce=1 V

SiGe200

fT (GHz)

150

SiGe120

125 100 SiGe90

75

SiGe60

50 25

BC35

0 0.01

0.1

1

10

IC (mA) for minimum We and Le = 1 µm

FIGURE 8.3 Higher fT performance at low and high current ranges for 0.18-mm SiGe BiCMOS processes (SiGe90/ 120/200) versus 0.35-mm (SiGe60, BC35).

quasi-self-aligned emitter. A large reduction in current required to meet RF circuit specifications, realized over a wide range of frequencies, has been published in various circuit-related studies [8–11]. Performance gains can be attributed to both the vertical and lateral scaling properties of the SiGe bipolar transistor.

Vertical Scaling Vertical scaling has been the traditional advantage of bipolar transistors over n-type MOS transistors due to the better control of vertical profiles versus lateral dimensions. This inherent fT advantage still holds true for advanced npn SiGe bipolar devices versus nanometer gate length CMOS. Optimization of fT is dependent upon a number of factors, as represented by the following analytical model that has proven effective at predicting peak fT of the Jazz bipolar devices:

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Industry Examples at the State-of-the-Art: Jazz

1=(2pf T ) ¼ (R e þ kT =(qIc ))(Cbe þ Cbc ) þ Wb2 =(2D b ) þ Wc =(2Vs ) þ Rc Cbc

(8:1)

where R e is the emitter series resistance, Ic the collector current, Cbe and Cbc the respective junction capacitances, Wb the base width, Db the electron diffusivity in the base, Wc the collector depletion region, Vs the saturated electron velocity, and Rc the collector resistance. Elements from Equation (8.1) can be calculated as a function of process parameters to help analyze trends in the bipolar performance. One method of increasing fT is to increase the collector doping concentration, which moves the Kirk effect to higher collector current density and results in higher peak fT. As shown in Figure 8.4, both experimental results as well as predictions from Equation 8.1 indicate that this technique is effective at lowering collector doping concentrations, but the benefits saturate at higher doping concentrations due to limitations of Re and Cbc at higher collector current. To achieve higher fT, therefore, Re or Wb must be reduced. Further reduction of base width, Wb, for these high-performance transistors has negative implications on the manufacturability and defect levels for the bipolar device, so reduction of emitter resistance is a more attractive optimization for high fT. Figure 8.4 shows that Re does not significantly affect fT at lower collector doping concentrations or lower Ic, and that Re does significantly affect fT at higher collector doping concentrations or higher Ic. Based on this analysis, a strong reduction in emitter resistance, coupled with a small re-optimization in the collector dose, has been used to increase the fT of the SiGe transistor without significantly reducing the base width. A peak fT of 205 GHz is reached for a production device with BVceo of 2.0 V, resulting in an fTBVceo product of 410 GHz-V.

Lateral Scaling For a given vertical scaling of the SiGe bipolar transistor, the fmax, or similarly the unilateral gain, can be improved with lateral scaling that reduces base-to-collector capacitance and the intrinsic base resistance. Reduction of base resistance also results in lower minimum noise figure, which is beneficial for lownoise amplification of RF signals. Lateral scaling of the active transistor area introduces a challenge in process integration of a nonselective SiGe epitaxial module in order to avoid facet growth at the isolation edge. Optimization for high fmax can be accomplished with a focus on reduction of the total base– collector capacitance (Cbc) and also depends on the emitter integration already discussed for fT optimization, as well as minimizing the extrinsic base resistance or base link, which dominates the total of the extrinsic and intrinsic components of base resistance.

225

0.5 ⫻ Re

200

Re

Peak fT (GHz)

175 2.0 ⫻ Re

150 125 100 75 50 25 0 0

FIGURE 8.4

1 2 3 Normalized collector doping

4

Calculated (lines) and measured peak fT as a function of collector doping and emitter resistance.

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For any given emitter integration, a compromise exists between fT and fmax as the collector design becomes more aggressive. The relationship for fmax with dependence on fT can be expressed as the following:

fmax

sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ fT ¼ 8pRb Cbc

(8:2)

The increased collector doping shifts the Kirk effect to higher current and enables higher fT, but also increases Cbc and degrades fmax. The total Cbc is made up of two basic components: the intrinsic is determined by the collector design to achieve target fT; the parasitic extrinsic components, such as the junction from the pþ extrinsic base to the SIC and also to the nþ buried layer, can be reduced by scaling active area to lower Cbc and improve fmax. Scaling of the base–collector area can be represented by the

22

SIC1 SIC2

21 20

SIC1

Cbc (fF)

19 18 17

SIC2 = 0.8 ⫻ SIC1 Average doping level

16 15 14 13 0.15

(a)

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

Emitter active overplot (µm)

35

DR A DR B

Unilateral gain (db)

30

25

20

15

10

5

0 1⫻109

(b)

1⫻1010

1⫻1011

Frequency (Hz)

FIGURE 8.5 (a) Base–collector capacitance Cbc as a function of the active overplot of the emitter opening for two collector-doping levels. (b) Improvement in unilateral gain with reduced emitter active overplot.

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design rule for active overplot of the emitter, as shown in Figure 8.5a for two different collector designs, one more highly doped at the base–collector junction, and the other more moderately doped. With smaller active sizing (i.e., smaller active overplot of emitter), there is a linear reduction of Cbc that is due to a lower coupling of the peripheral extrinsic component to the nþ buried layer. Since the magnitude of the reduction is dependent on the initial doping level, lateral scaling results in more significant Cbc reduction when a more aggressive, highly doped collector profile is used. Since the physical effect of this design rule is to reduce the length of the electrical connection to the intrinsic transistor, the total resistance would be expected to decrease for a given base resistance. This is not the case for the Jazz 0.18-mm SiGe bipolar transistor due to slow SiGe epi growth planes, dominated by a h3 1 1i type, that are less favorable for carrier transport and effectively reduce the active sizing from the original lithographic definition. Small changes to the optimization of the SiGe epi recipe and the integration process module limit facet growth and result in simultaneous Cbc and Rb reduction for the Jazz 200 GHz SiGe process (named SiGe200). The resultant fmax gains are significant, and reach beyond 200 GHz (Figure 8.5b). Intrinsic base resistance is lowered with reduced emitter width, and parasitic collector–base capacitance is lowered through reduction of the active base area. The resulting transistor has fT greater than 200 GHz (magnitude of H21) and fmax greater than 200 GHz (unilateral gain) for an emitter width of 0.15-mm.

8.3

SiGe BiCMOS Process Integration

CMOS and bipolar performance targets within a BiCMOS technology should be considered simultaneously for a range of applications. Maintaining a significant gap between the fT of the n-type MOS transistor and the high-speed npn bipolar, as defined by fT versus line width in Figure 8.6, has broadened the application space for each process generation. Since the bipolar transistor is what defines the unique capability of SiGe BiCMOS, a number of process variants include the same self-aligned npn architecture with 0.25, 0.18, or 0.13-mm MOS transistors.

200 SiGe BiCMOS NPN

fT (GHz)

100 80 60

Si BiCMOS NPN

40 CMOS NFET

20

10 0.5

0.35

0.25

0.18 0.15

0.13

Technology (µm)

FIGURE 8.6 Performance curve as a function of process generation for production CMOS, BiCMOS, and SiGe BiCMOS technologies.

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Integration Sequence After buried layers are formed in bipolar collector regions, an epitaxially grown n-type silicon layer becomes the starting substrate for the n- and p-type MOS transistors. Standard well implant doses have been slightly adjusted versus the bulk CMOS process for the presence of the lightly doped n-type layer. An oxide-filled shallow trench is created and dual-gate oxides are grown in support of both 1.8 and 3.3 V MOS transistors. After gate formation and patterned opening of the bipolar base regions, the bipolar is integrated by first depositing a blanket SiGe layer using a single-wafer rapid thermal chemical vapor deposition (RT-CVD) reactor. A sacrificial emitter is patterned and spacers are formed to self-align the extrinsic base implant. The sacrificial emitter is removed and an in-situ doped emitter is deposited such that the dimension of the sacrificial emitter exactly defines the final emitter dimension. A collector implant differentiates the fT and BVceo of the three available npn transistors. Several dry etch steps are used to pattern the emitter poly and remove bipolar-related layers from the CMOS regions of the wafer. Next, the CMOS devices are completed with formation of side-wall spacers, implantation of source and drain, final implant activation and cobalt silicidation, all of which are shared with the SiGe bipolar device. Back-end options include three to six layers of metal with a 1 to 4 fF/mm2 MIM capacitor, a 25 ohm/sq metal resistor and up to a 5.2-mm-thick top metal layer and a 3-mm thick top dielectric layer to realize high-quality inductors. These results have been achieved with integrated 1.8/3.3 V dual-gate CMOS. Full digital library compatibility is maintained for 0.18-mm CMOS performance with the integration of the bipolar device. Idsat of the 1.8 V transistors is 600 and 255 mA/mm, respectively, and Idsat of the 3.3 V transistors is 600 and 245 mA/mm, respectively. Options for a natural Vt MOS transistor and triple-well isolation are included in this modular technology. Compatibility with 0.13-mm dual-gate 1.2/3.3 V CMOS has also been demonstrated, as shown in the typical output curves in Figure 8.7. Idsat of the 1.2 V transistors is 500 and 215 mA/mm, respectively, and Idsat of the 3.3 V transistors is 600 and 245 mA/mm, respectively.

CMOS Thermal Budget As CMOS is scaled, thermal budget constraints of advanced bipolar devices and CMOS devices diverge, leading to more difficult integration. The CMOS gate, re-oxidation, LDD, and pocket implants are included prior to SiGe epi deposition then the source–drain implants and final anneal are implemented after the SiGe bipolar transistor is completely formed. This limits the exposure of the SiGe transistor to CMOS-related thermal budget from the gate and re-oxidation cycles, which is key for technologies

1⫻10−3

Vd = 1.2 V

1⫻10−4 1⫻10−5

Vd = 0.1 V

Ids (A)

1⫻10−6 1⫻10−7 1⫻10−8

NFET

PFET

1⫻10−9

Lmin = 0.13 µm

1⫻10−10 1⫻10−11 1⫻10−12 1⫻10−13 −1.5

−0.5

0.5

1.5

Vgs (V)

FIGURE 8.7 Subthreshold characteristics of generic 0.13-mm gate length CMOS integrated with a SiGe npn transistor (fT and fmax >200 GHz).

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having a boron-doped silicon or silicon germanium base where the final base width was largely determined by subsequent thermal budget. The situation is different for a carbon-doped SiGe base profile since the use of carbon co-doping to arrest boron diffusion provides a level of independence from any subsequent thermal budget without compromising bipolar performance. However, while the design of the bipolar is less constrained, the CMOS is now limited by the thermal budget bake used to condition the surface prior to SiGe deposition. The optimization of thermal budget must strike a balance between CMOS performance and bipolar yield. Incomplete surface conditioning results in epi defectivity. This process is thermally activated with an activation energy of approximately 1.1 eV. As the footprint of the bipolar is reduced, some reduction in thermal budget will be possible. For example, shrinking the device area by half but keeping defectivity constant could allow nearly a 1008C reduction in bake temperature. Improvements of ex-situ wet processes and in-situ techniques for pre-cleaning and a reduction in active area due to lateral scaling can make it easier to integrate advanced SiGe devices with scaled CMOS.

SiGe npn Manufacturability A key to manufacturability of SiGe technology is the reuse of high-volume CMOS infrastructure. The maturity of process equipment, the high level of factory automation for recipe download and wafer handling, the yield management discipline, and the mechanisms for continuous improvement make it possible to deliver high-quality wafers in complex process technologies. For similar process complexity, as measured by the number of critical photomask layers or the number of process steps, the manufacturing cost and fab yield is comparable regardless of the technology specifics. It is the commitment to establishing process modules that are within the capability of the equipment set that makes it possible to deliver SiGe technology that is as repeatable and cost-effective as mainstream CMOS. RT-CVD has become the most commonly used process for silicon germanium epitaxy due to the commonality of equipment platforms with other production silicon technologies, and the advantages of single-wafer tools for small lot processes in the high mix manufacturing environment typical of many fabs. Single-wafer RT-CVD tools are used for process recipes such as epitaxial silicon growth on silicon substrates, deposition of heavily doped polycrystalline films, and selective silicon-raised source–drain structures. High-quality SiGe epitaxy required the addition of appropriate gas lines, procedures for minimizing oxygen and carbon contamination, and a redesigned wafer susceptor to achieve production worthy results. Focused efforts on both ex-situ and in-situ pre-clean capabilities were necessary to migrate from initial device level results to attainment of low defect density and high yield for typical levels of BiCMOS integration. Though usually limited to approximately 10,000 bipolar transistors and 250,000 CMOS gates for the integration of many analog/RF functions, the 0.18-mm technology must support upwards of 30,000 bipolar transistors and 1.5 million CMOS gates for practical designs. The ability to perform in-line measurement of SiGe epi thickness, germanium content, and boron doping level is required to establish typical production control charts. Spectroscopic ellipsometry can be used on production wafers to monitor SiGe epi thickness, as shown in Figure 8.8a. Demonstrated control of 1.64% 1-sigma variation provides feedback on the epi process. Measurement of poly thickness and in-line sheet resistance closes the loop for day-to-day SiGe manufacturing. Process variation related to the emitter formation, such as emitter pre-clean, in-situ poly doping, and final rapid thermal anneal, adds to the SiGe bipolar variability. Control of all of these parameters translates into resistances and vertical doping profiles that determine the range of bipolar fT, which is shown in Figure 8.8b to be 2.5% 1-sigma for over 40 production lots of a technology with mean fT greater than 155 GHz.

8.4

Process Customization

In a technology landscape where standardization is accepted as the most straightforward route to economies of scale, the modularity of Jazz technology stands as an example of mass customization.

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SiGe Epi thickness (Angstroms)

460

USL

450 440 430 Epi in-line measurement

420 410

LSL

400 0

10

20

(a)

30

40

Sampled lots

240

fT fmax (GHz)

220 220 180 160 140

fT fmax

120 100 0 (b)

10

20

30

40

Sampled lots

FIGURE 8.8 (a) In-line measurement of SiGe epi thickness for a 40 lot sample of 0.18-mm production wafers. (b) Control of process parameters related to bipolar performance is indicated by small fT and fmax variation for a sample of production lots.

This approach requires rethinking all elements of technology delivery: process development, design kits, design libraries, and manufacturing control systems.

Wireless Technology Wireless applications require high-performance bipolar transistors with high-quality passives, and CMOS density suitable for moderate levels of mixed-signal and logic integration. As the integration of multistandard and multifunction devices in analog/RF subsystems is addressed, higher voltage CMOS and bipolar device options are added to enable integration of power management and power amplification functions. This is achieved in a wireless focused version of the Jazz 0.18-mm SiGe BiCMOS (SiGe90) process by adding modules that meet RF subsystem requirements, such as high-Q capacitors, inductors, and varactors that enable improved RF performance and reduced die size. For handset transceivers, 1.8 V CMOS is not generally required as large digital blocks are often placed on a separate base-band chip. Thus, a single-gate 3.3 V MOS transistor option is available in SiGe90 to reduce mask count and cost. Deep-trench isolation can be removed as most RF blocks (outside of possibly the prescaler) make use of larger devices that do not benefit as much from use of deep trench and are not as sensitive to collector–substrate capacitance. Also, a transistor with 155 GHz peak fT is not relevant for 2–5 GHz applications that typically operate at lower current densities. Because of low parasitics, the higher BVceo devices still maintain a high fmax and provide very good noise and low-current performance. Three different top via and thick metal module options are available for usage depending on the cost, integration level, and inductor performance requirements. A module with 3-mm deep top via and

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5.2-mm thick aluminum offers a significant enhancement in inductor performance or reduction in inductor area for the same level of performance. A 1 kOhm/sq p-type poly resistor provides footprint and matching suitable for 2 to 6 GHz RF circuit design. Upgrade of the MIM capacitor to 2.0 fF/-mm2, or 4.0 fF/mm2 in its stacked topology, reduces capacitor area by using a scaled version of a nitride dielectric.

High Data Rate and High-Frequency Technology To enable implementation of circuits with data rates above 10 Gb/sec or frequencies up to 60 GHz, a fully featured version of the Jazz 0.18-mm SiGe BiCMOS process, SiGe120, is offered. The device set includes dual-gate 1.8/3.3 V CMOS and three SiGe npn transistors with fT of 155/78/38 GHz, four layers of standard metalization for dense digital logic and embedded SRAM, low-capacitance thin film metal resistors for high-frequency operation, a linear MIM capacitor with high Q, and two thick layers of aluminum (1.5 and 3.0-mm) for implementation of transmission lines and inductors. The addition of a higher performance SiGe npn transistor module with peak fT over 200 GHz (SiGe200), and higher fT and fmax over a large range of collector current, enables lower power circuits for networking applications, emerging wireless data standards from 20 to 60 GHz, and even collision-avoidance radar above 60 GHz for automobiles.

8.5

Summary

Adding new features that build on established technology has resulted in a family of processes that offer a combination of active devices, passive components, and interconnect schemes specifically optimized for different types of products. In the mobile phone, extending the voltage capability of the transistor to 5 to 8 V to meet the requirements of RF power control, power management, and low drop out regulation enables higher levels of analog and RF product integration. High-density passives to scale down capacitor and inductor area can be more important to the reduction of die size than the scaling of digital blocks. Use of only the necessary process modules reduces overall manufacturing complexity, and ultimately cost of a design for a specific market segment. This specialty roadmap for analog and RF functional scaling will repeat with the maturation of subsequent generations of CMOS technology. There will be less emphasis on linewidth reduction and more effort related to the reuse of advanced CMOS process equipment for new materials and structures that advance the functional scaling of highly integrated mixed-signal, analog, and RF products.

Acknowledgments The author would like to thank the entire Jazz Semiconductor team for their technology development efforts, as well Marco Racanelli and Greg U’Ren for their direct contributions to this manuscript.

References 1. M Racanelli, Z Zhang, J Zheng, A Kar-Roy, P Joshi, A Kalburge, L Nathawad, M Todd, C Ukah, C Hu, C Compton, K Schuegraf, P Ye, R Dowlatshahi, G Jolly, and P Kempf. BC35: a 0.35 mm, 30 GHz, Production RF BiCMOS Technology. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 125–128. 2. A Chantre, M Marty, JL Regolini, M Mouis, J de Pontcharra, D Dutartre, C Morin, D Gloria, S Jouan, R Pantel, M Laurens, and A Monroy. A high performance low complexity SiGe HBT for BiCMOS integration. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1998, pp. 93–100. 3. JS Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, SJ Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freemen, K Stein, and S Subbanna. SiGe HBTs with cut-off frequency of 350 GHz. IEDM Technical Digest International Electron Devices Meeting, San Francisco, 2002, pp. 771–774.

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4. M Racanelli and P Kempf. SiGe BiCMOS technology for communication systems. Extended Abstracts of the International Conference on Solid State Devices and Materials, Nagoya, 2002, pp. 286–287. 5. M Racanelli, K Schuegraf, A Kalburge, A Kar-Roy, B Shen, C Hu, D Chapek, D Howard, D Quon, F Wang, G U’Ren, L Lao, H Tu, J Zheng, J Zhang, K Bell, K Yin, P Joshi, S Akhtar, S Vo, T Lee, W Shi, and P Kempf. Ultra high speed SiGe npn for advanced BiCMOS technology, International Electron Devices Meeting Washington, 2001, pp. 01-337–15.3.4. 6. K Oda, E Ohue, I Suzumura, R Hayami, A Kodama, I Shimamoto, and K Washio. Self-aligned selective-epitaxial-growth Si1xy GexCy HBT technology featuring 170-GHz fmax. International Electron Devices Meeting, Washington, 2001, pp. 2–5. 7. M Racanelli and P Kempf. SiGe BiCMOS technology for communication products, Custom Integrated Circuits Conference, San Jose, 2003, pp. 331–334. 8. M Kamat, P Ye, Y He, B Agarwal, P Good, S Lloyd, and A Loke. High performance low current CDMA receiver front end using 0.18-mm SiGe BiCMOS. IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia, 2003, pp. 23–26. 9. P Ma, M Racanelli, J Zheng, and M Knight. A 1.4 mA and 3 mW, SiGe90, BiFET low noise amplifier for wireless portable applications. IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia, 2003, pp. 237–240. 10. P Ye, B Agarwal, M Reddy, L Li, J Cheng, PC Mudge, E McCarthy, and SL Lloyd. High performance circuits in 0.18-mm SiGe BiCMOS process for wireless applications. IEEE Radio Frequency Integrated Circuits Symposium, Seattle, 2002, pp. 329–332. 11. M Racanelli, P Ma, and P Kempf. SiGe BiCMOS technology for highly integrated wireless transceivers. 25th GaAs IC Symposium, San Diego, 2003, pp. 183–186.

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9 Industry Examples at the State-of-the-Art: Hitachi

Katsuyoshi Washio Hitachi Ltd.

9.1

9.1 9.2 9.3 9.4 9.5

Introduction......................................................................... 9-1 SiGe HBT Technologies ...................................................... 9-2 SiGe BiCMOS Technologies ............................................... 9-6 Interconnection and Passive Elements .............................. 9-9 Summary ............................................................................ 9-11

Introduction

High-speed monolithic integrated circuits (ICs) and large-scale ICs (LSIs) are the key components for multigigabit data communication systems and wide-bandwidth radio communication systems. Such systems include backbone networks, intercity communication networks, local area networks, and Ethernet for data communications, and microwave and millimeter-wave mobile networks, fixed wireless access, and intelligent transport systems for radio communications. To meet the growing demand for such systems, both high-speed digital operation with sophisticated functions and high-frequency analog operation should be implemented. From this point of view, high-speed SiGe HBT and SiGe HBT with CMOS (BiCMOS) technologies are the most promising candidates to meet these requirements. This is because SiGe HBTs with a sub-5-psec ECL-gate delay and cutoff frequency about 200 GHz have been successfully demonstrated and can be fabricated by the well-established Si process, which is fully compatible with the CMOS process. For the widespread application of these devices in high-speed digital and RF analog ICs/LSIs, SiGe HBTs must be fabricated at a high yield. Moreover, high-quality passive elements, including high-precision resistors, a high-Q varactor, an MIM capacitor, and high-Q inductors, should also be available for integration on a chip. Consequently, technologies for fabricating a self-aligned SiGe HBT by selective epitaxial growth (SEG) and SiGe BiCMOS have been developed. This self-aligned SEG concept can be expected to achieve highspeed and low-power performance as a result of small parasitic resistances and capacitances. A selfaligned SEG SiGe HBT that has shallow-trench and dual-deep-trench isolations (DTIs) and Ti–salicide electrodes was fabricated on a 200-mm wafer line. The fabrication process is almost completely compatible with the 0.2-mm BiCMOS technology that is applied in fabricating fast-cache memory chips. To improve cutoff frequency, maximum oscillation frequency, and ECL-gate delay, optimization of the width of the SiGe SEG layer and the thickness of the Si-cap layer, incorporation of C to suppress B out-diffusion, and application of thin and heavily-boron-doped base have been investigated. In the case of SiGe BiCMOS technology, CMOS devices with gate lengths of 0.25 mm to 80 nm were integrated. For both the SiGe HBT and BiCMOS technologies, a four-level or five-level metal layer structure for interconnection was formed by chemical–mechanical polishing (CMP). Concerning the integration 9-1

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of high-quality passive elements, a high-precision poly-Si resistor with a ‘‘quasi-layer-on-layer’’ structure, a high-Q varactor constructed of a SiGe-base and a Si-collector junction, an MIM capacitor formed between the first and second metal layers by plasma SiO2 as an insulator, and a high-Q inductor fabricated by using the fourth metal layer are available for integration on the same chips as active devices.

9.2

SiGe HBT Technologies

A scanning electron microscopy (SEM) cross-sectional view of a 0.2-mm self-aligned SEG SiGe HBT is shown in Figure 9.1, including an enlarged view of the active region, the key part of the SiGe HBT [1]. The 0.6-mm-wide Si-cap/SiGe-base multilayer was selectively grown in self-alignment with the 0.2-mmwide emitter by ultrahigh vacuum/chemical vapor deposition (UHV/CVD) [2]. A poly-Si-assisted selfaligned SEG (PASS) structure was applied to provide a good link between the intrinsic SiGe and extrinsic

Base

Emitter

Collector 1st metal

Ti salicide

W 1 µm

Shallow trench Dual deep trench

IDP 0.2 µm Base poly Si

Si/SiGe SEG Poly-SiGe

Buffer poly-Si

FIGURE 9.1 An SEM cross-sectional view of a 0.2-mm self-aligned SEG SiGe HBT with an enlarged active region, the key part of the SiGe HBT. A 0.6-mm-wide Si-cap/SiGe-base multilayer self-aligned to a 0.2-mm-wide emitter was selectively grown by UHV/CVD. A poly-Si-assisted self-aligned SEG (PASS) structure, shallow-trench and dualdeep-trench isolations, and Ti–salicide electrodes were applied. (From K. Washio, M. Kondo, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, and T. Harada. IEEE Trans. Electron Devices 48:1989–1994, 2001. With permission.)

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poly-Si bases [3,4]. In the PASS structure, a poly-SiGe base contact was grown, at the same time as the intrinsic SiGe base, around the buffer poly-Si and beneath the extrinsic base poly-Si. This self-aligned active-region structure enabled both low collector capacitance and low base resistance. Furthermore, 0.4-mm-deep shallow-trench isolation (STI) and 0.6-mm-wide 3-mm-DTIs were used to reduce the parasitic capacitances of the collector and substrate, respectively. Ti–salicide layers, with a sheet resistance of 3 V/sq. and contact resistance of about 25 V mm2, were formed on all the electrodes to reduce their parasitic resistances. The process steps in the fabrication of the self-aligned SEG SiGe HBT are explained as follows (Figure 9.2). An nþ buried layer (BL) was formed by ion implantation of antimony followed by annealing. A 0.3-mm-thick Si epitaxial layer was then formed. Next, the shallow- and dual-deep-trench grooves for the isolation were formed and filled up with SiO2 by planarization with CMP. Next, the intrinsic region was covered by the three successively deposited films of Si3N4, poly-Si, and SiO2. This multilayer was used to form the PASS structure. An amorphous Si film for the base poly-Si and a thick SiO2 film were then deposited, and a window to the intrinsic region was opened in these films by etching. The first selectively implanted collector (SIC1) region was then formed by phosphorus-ion implantation through the multilayer and into the Si epitaxial layer. After that, the SiO2 film remained on the sidewall of the window after reactive-ion etching (RIE). The Si3N4 film was then deposited, and it remained on the sidewall of the window. At that time, the top film of the multilayer, the Si3N4, was etched. After that, the remaining films of multilayer, poly-Si and SiO2, were selectively etched. The Si3N4 film was then removed from the sidewall, and the window in the Si3N4 film of the multilayer was enlarged by wet side-etching. Next, the Si-cap/SiGe-base multilayer was selectively grown by UHV/CVD using Si2H6, GeH4, and B2H6 source gases at 5508C for the SiGe layer and Si2H6 at 5808C for the Si layer. The SEG layer consisted of a 15-nm-thick Si cap, 20-nm-thick

FIGURE 9.2 Process steps for fabricating the self-aligned SEG SiGe HBT. (From K. Washio, M. Kondo, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, and T. Harada. IEEE Trans. Electron Devices 48:1989–1994, 2001. With permission.)

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Si1xGex , 40-nm-thick Si0.85Ge0.15, and 10-nm-thick Ge-retrograded (from 15% to 0) Si1xGex . A 15-nm-thick 2 1019 cm3 boron-doped Si1xGex layer was formed as the intrinsic base. The poly-SiGe base contact was formed simultaneously with the intrinsic SEG, and this formation was assisted by the middle film of the multilayer, the poly-Si (which was used as a buffer). Next, phosphorus ions were implanted in the lower part of the SEG layer to form the second SIC region (SIC2). Double selective implantations of phosphorous were applied to increase the collector-doping level to about 1 1018 cm3. Thin SiO2 and in situ phosphorus-doped poly-Si (IDP) layers were deposited, and the IDP film remained on the sidewall of the window. After an emitter area had been opened by wet etching of the thin SiO2, a second IDP layer was deposited. A shallow emitter with a junction depth of about 20 nm was formed by diffusion from the IDP layers into the Si-cap layer at 9008C for 30 sec. Next, Ti–salicide layers on all electrodes of the emitter, base, and collector were formed simultaneously in a self-aligned manner. The SiGe HBT was fabricated on a 200-mm wafer line and the process to fabricate the SiGe HBTs is, with the exception of the SEG, almost the same as the 0.2-mm BiCMOS process [5]. The process is thus completely compatible with BiCMOS technology. The designed profile of the SiGe layer after SEG, featuring dual plateaus with an intermediately Ge-graded slope (DPIG), is shown in Figure 9.3. The Ge profile of the SiGe layer was designed as follows: two plateaus with Ge contents of 10% (on the surface side) and 15% (on the substrate side), a 5-nm-thick Ge-graded layer between the plateaus, and two Ge-graded layers at the interfaces with the Si-epitaxial and Si-cap layers. This DPIG Ge profile was designed to enable precise controllability of the collector current against deviation in the position of the emitter–base junction. At the end of the process, the base was about 30-nm wide, so the two plateaus and the intermediate Ge-graded layer were located in the base. Note that this layer provided an internal drift field in the conduction band and enabled a short base transit time and a high Early voltage in a similar way to the conventional graded-Ge profile. The emitter–base junction was located at the 10%-Ge plateau, and the thickness of this plateau was sufficient to suppress changes in the effective base Gummel number caused by deviation in the emitter–junction depth. The SiGe HBT, with an emitter area AE of 0.2 2 mm, exhibited good I–V performance with a high current gain of 1400. The ideality factor of the base current IB was 1.10, and the base-recombination current was below 10 pA. The HBT yield, measured from 4000 parallel-connected transistors, was more than 99.9993%. These DC characteristics show that no defects were created in the strained Si/SiGe multilayer during the thermal cycles for the HBT formation. The slope of the Arrhenius plot of the normalized current gain indicates that the Ge-induced bandgap reduction for the strained SiGe base layer

NB = 2 1019 cm−3 w B = 15 nm

B

Ge content (%)

15

Ge2

10

Ge1 SEG I/F

5

0 0

20

40 60 Depth (nm)

80

100

FIGURE 9.3 A schematic view of the designed profile, featuring dual plateaus with intermediate Ge-graded slope (DPIG) for the SiGe layer after SEG. Ge1 is the Ge content of the lower plateau and Ge2 is that of the upper plateau. At the end of the process the base was about 30 nm wide, so both plateaus and the intermediate Ge-graded layer were located in the base. (From K. Washio. IEEE Trans. Electron Devices 50:656–668, 2003. With permission.)

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was 110 meV, which verifies that there was no relaxation in the SiGe layer. The typical transistor characteristics of a SiGe HBT with an emitter area of 0.2 2 mm are summarized in Table 9.1. Figure 9.4 shows the dependence of the differential ECL gate-delay time on the switching current as measured from 53-stage ring oscillators with a fan-in and a fan-out of 1 at a single-ended voltage swing VL of 250 mV and a supply voltage of 3.5 V. The SiGe HBTs have an emitter area of 0.2 2 mm. A minimum ECL-gate delay time of 5.5 psec was measured at a switching current of 2 mA. Analysis of the delay components that made up this delay time showed that the contributions of load resistance, base resistance, forward transit time, and other factors were 1.48, 2.39, 0.93, and 0.70 psec, respectively. The power-delay product of the ECL circuit composed of a SiGe HBTwith an emitter area of 0.2 0.5 mm was low, i.e., 4.4 f J. The fast- and low-power performance of the ECL gate was attributed to the low collector capacitance and the low substrate capacitance enabled by the shallow-trench and dual-DTIs, high fT and fmax of the fully selfaligned SEG SiGe HBT structure, and the low parasitic resistance of the Ti–salicide electrodes.

TABLE 9.1 Typical SiGe HBT Characteristics with an Emitter Area of 0.2 2 mm 0.2 2 mm2 1400 1.9 V 3.0 V 6.3 V 90 V 3.6 fF 1.8 fF 122 GHz 163 GHz 5.5 ps

Emitter area Current gain BVCEO BVCER BVCBO Base resistance Collector capacitance Substrate capacitance Cutoff frequency Max. oscillation frequency ECL min. gate delay

Source : K. Washio. IEEE Trans. Electron Devices 50:656–668, 2003. With permission.

30 Differential ECL gate AE = 0.2 2 µm

53-stage R. O. 10

50 mV/div.

ECL gate delay time (ps)

20

VL = 250 mV

8 500 ps/div. 6 5.5 ps 4 0.3

3 1 Switching current (mA)

10

FIGURE 9.4 Dependence of the differential ECL gate-delay time on the switching current as measured from ring oscillators. Each SiGe HBT had an emitter area of 0.2 2 mm and ran at a single-ended voltage swing VL of 250 mV and a supply voltage of 3.5 V. The fan-in and fan-out were 1. The output waveform of a 53-stage ECL ring oscillator as measured at a switching current of 2 mA is also shown. A minimum ECL gate-delay time of 5.5 psec was measured. (From K. Washio. IEEE Trans. Electron Devices 50:656–668, 2003. With permission.)

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Optimization of the device structure and the intrinsic impurity profile were investigated [6,7]. They are related to the collector–base and emitter–base junctions of the self-aligned SEG SiGe HBTs by varying the width of the SiGe SEG layer and the thickness of the Si-cap layer, respectively. The incorporation of carbon to suppress boron out-diffusion of the base was performed [8]. This is effective both to improve high-speed performance and to reduce fluctuations in device performance by alleviating the lattice strain. Furthermore, a thin and heavily-boron-doped base toward a thickness of 1 nm is applied [9]. As a result, a cutoff frequency of 174 GHz, a maximum oscillation frequency of 204 GHz, and an ECL-gate delay of 4.8 psec were obtained. For low-power and high-speed operation, a scaled-down SiGe HBT, structurally optimized for an emitter scaled-down towards 100 nm, was also developed [10].

9.3

SiGe BiCMOS Technologies

A cross-sectional SEM image of the 0.2-mm self-aligned SEG SiGe HBT, a CMOS transistor, and a polySi resistor on an SOI (1-mm-thick Si on 0.3-mm-thick insulator) wafer based on an HRS (resistivity of about 1 kV cm) is shown in Figure 9.5 [11]. The SiGe HBT was fabricated in the manner described above. A 4 1019 cm3 boron-doped 10-nm-thick (as SEG) Si0.95Ge0.05 layer was used as the intrinsic base. A 0.5-mm-wide DTI reaches the buried SiO2. The drawn CMOS gate lengths were 0.25 mm (nMOS) and 0.3 mm (pMOS). The gate electrode was constructed of a layer of 50-nm-thick TiSi2 (formed simultaneously with the other electrodes) stacked on 300-nm-thick nþ-doped poly-Si. The process sequence of SiGe BiCMOS is shown in Figure 9.6. The standard steps of the bipolar fabrication process were carried out from the formation of the nþ buried collector layer to the deep trench isolation. A 0.3-mm CMOS process module was then inserted. The thickness of the gate oxide was 6.5 nm. A poly-Si resistor was also formed from nþ-doped gate poly-Si for low sheet resistance (LR). After CMOS formation, the process sequence returns to continue with the bipolar process sequence. During the fabrication of self-aligned SEG SiGe HBTs, the CMOS and poly-Si resistor areas are covered by SiO2. A poly-Si layer was deposited and patterned. Boron and germanium ions were then implanted

M4 (3µm)

M3 MIM-C M2 M1

via TiSi2 poly Si-R

SiO2 (0.3 µm)

SiGe HBT

HRS (1 kΩcm)

nMOS

pMOS

5 µm

FIGURE 9.5 Cross-sectional SEM image of a 0.2-mm self-aligned SEG SiGe HBT, a CMOS transistor (drawn gate lengths were 0.25 mm for nMOS and 0.3 mm for pMOS), and a poly-Si resistor on a 200-mm SOI (1-mm-thick Si on 0.3-mm-thick insulator) wafer based on an HRS (resistivity of about 1 kV cm). A four-level metal (M1–M4) layer structure was used for interconnection. (From K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. IEEE Trans. Electron Devices 49:271–278, 2002. With permission.)

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SiGe HBT n+ buried collector (Sb+) n− epitaxial growth (0.3 µm) Shallow (0.35 µm) trench isolation Collector plug Deep (1µm) trench isolation MR & HR poly-Si (w/ Ge I/I) Base poly-Si (0.2 µm) Emitter window & SIC1 SiGe SEG & SIC2 Emitter poly-Si (in-situ P-doped)

CMOS n & p well I/I Gate poly-Si (LR) PTS I/I & LDD n & p S/D I/I

Ti-salicide Contact & W plug 1st metal & via MIM capacitor 2nd to 4th metal

FIGURE 9.6 Process sequence for 0.2-mm SOI/HRS SEG SiGe HBT/CMOS. A 0.3-mm CMOS process module was inserted after formation of the trench isolations. (From K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. IEEE Trans. Electron Devices 49:271–278, 2002. With permission.)

to form pþ poly-Si resistors for medium (MR) and high (HR) sheet resistances. After the deposition of oxide, a 0.2-mm-thick poly-Si layer was formed for the base electrode. Phosphorous ions were implanted after the emitter window opening to form SIC1 and after the SiGe SEG to form SIC2. This can provide optimized collector profiles for both high-speed and high-voltage HBTs. The formation of the emitter poly-Si electrode is followed by the process sequence of an interconnection process module. Numbers of masks used were ten for the SiGe HBTs, ten for the CMOS transistors, and three for the poly-Si resistors. The effectiveness of the DPIG Ge profile was confirmed by the dependence of the current gain on Ge1, the Ge content of the lower plateau. As a result, even for HBTs with various Ge2 (the Ge content of the upper plateau) in the range from 7.5% to 15%, the collector current was well controlled by Ge1 and was independent of Ge2. This indicates that the collector current is mainly determined by the bandgap narrowing of the lower plateau. Therefore, the lower plateau suppresses the change in the effective base Gummel number, which occurs with the conventional graded-Ge profile because of the fluctuation in the emitter–junction depth. Good I–V performance, with a current gain of about 300, is confirmed in the Gummel plots for single and 104 parallel-connected HBTs with an emitter area AE of 0.2 1 mm. The averaged forward base tunneling current was about 2 pA/HBT. The respective ideality factors of the collector current IC and base current IB were 1.007 and 1.075. The current gain was higher than 100 in the zlow-collector-current region up to 1 nA. The HBT yield, as measured from sets of 104 HBTs connected in parallel, was about 99.9997%, which means the defect density was about 2000 defects/cm2 under the assumption of a relaxed-limited yield. This means that the limit on the number of HBTs that may be integrated is about 105. The reliability under the forward- and reverse-bias stressing was investigated and compared with manufactural Si BJTs with guaranteed 10-year operation as a control. No change in the collector and base current were viable at JC up to 60 mA/mm2 under forward-bias stress, and a similar behavior of the base current to that of a Si BJT under reverse-bias stress up to a VEB of 3.5 V were observed. As a result, high reliability of SiGe HBTs was confirmed. The HBT characteristics, breakdown voltage, and high-frequency performance were controlled by the collector sheet concentration NS through the double selective phosphorus implantations in the 0.3-mmthick Si epitaxial layer and in the undoped SiGe. The breakdown voltage BVCEO was 2.5 V for the HSHBT and 3.9 V for the HV-HBT. The high Early voltage VA of more than 100 V for both HBTs indicates that the collector current was determined by the drift field created by the bandgap grading. The dependence of the cutoff frequency fT and maximum oscillation frequency fmax on the collector current

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for the HS-HBT with an emitter area AE of 0.2 1 mm and the HV-HBT with an AE of 0.2 4 mm are shown in Figure 9.7. The peak fT of the HS-HBT with an emitter area AE of 0.2 1 mm and the HV-HBT with an AE of 0.2 4 mm were 76 and 47 GHz, respectively. The peak fT for the HV-HBT was about 60% of that for the HS-HBT, and the collector current density at the peak fT for the HV-HBT was about one fourth of that for the HS-HBT. The dependence of the peak fT on BVCEO was also investigated, and their product was about 190 GHz V. The peak fmax for the HS-HBT was 180 GHz and even that for the

100 HS-HBT AE = 0.2 1 µm

Cutoff frequency (GHz)

80

60

40

20

0 0.1

HV-HBT AE = 0.2 4 µm

0.3

1

3

Collector current (mA)

(a)

40

150

HS-HBT AE = 0.2 1µm

30

10

10 100 Frequency (GHz)

40

50

0.3

fmax 180 GHz

VCE = 2 V IC = 0.7 mA 1

HV-HBT AE = 0.2 4 µm

U

MSG/ MAG

20

0 100

0 0.1 (b)

MSG/MAG, U (dB)

AE = 0.2 1 µm HS-HBT

1

Collector current (mA)

3

MSG/MAG, U (dB)

Maximum oscillation frequency (GHz)

200

HV-HBT AE = 0.2 4 µm

30

U

20

MSG/ MAG

10

VCE = 2 V IC = 0.7 mA

0 1

fmax 125 GHz

10 100 Frequency (GHz)

FIGURE 9.7 Dependence of the cutoff frequencies (a) and maximum oscillation frequencies (b) on collector current for the HS-HBT with an emitter area AE of 0.2 1 mm and the HV-HBT with an AE of 0.2 4 mm. (From K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. IEEE Trans. Electron Devices 49:271–278, 2002. With permission.)

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Industry Examples at the State-of-the-Art: Hitachi TABLE 9.2 Typical Transistor Parameters for the HS-HBT with an Emitter Area AE of 0.2 1 mm and the HV-HBT with an AE of 0.2 4 mm

WE (mm) LE (mm) hFE n VA (V) BVCEO (V) BVCBO (V) RB (V) RE (V) CJE (fF) CJC (fF) CSUB (fF) fT (GHz) fmax (GHz) min ECL tpd (psec)

HS

HV

0.2 1 300 1.007 >100 2.5 10.0 120 27 9 1.9 1.1 76 180 7.8

0.2 4 300 1.007 >100 3.9 11.5 45 9 13.4 3.4 2.2 47 125 –

Source: K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. IEEE Trans. Electron Devices 49:271–278, 2002. With permission.

HV-HBT was 125 GHz, thanks to both the low collector capacitance, which was a result of the selfaligned SEG structure and optimized collector profile, and the low base resistance. These results indicate that both HBTs are very suitable for high-frequency analog applications. Typical transistor parameters for the HS-HBT with an emitter area AE of 0.2 1 mm and the HV-HBT with an AE of 0.2 4 mm are summarized in Table 9.2. Here, CSUB was reduced to about 60% of that without SOI [12]. This is because CSUB is given by the series connection of the depletion capacitance under the nþ buried collector and the capacitance of the buried oxide. To improve the functionality, scaled CMOS with gate lengths of 0.18 mm [13], 0.13 mm [14], and 80 nm [15] in SiGe BiCMOS technologies have been advanced by optimizing process flow and reducing thermal budgets.

9.4

Interconnection and Passive Elements

A cross-sectional view of the four-level structure of metal layers with an MIM capacitor is also shown in Figure 9.5. The structure of metal layers for use in interconnection was fabricated by applying CMP to planarize the tungsten deposited for the 0.5-mm-wide contact plugs and 0.6 0.6-mm via holes and to planarize the plasma–SiO2 interlayer insulators. All of the metal layers were multilayered structures of Al, Ti, and TiN. A concave MIM capacitor with a capacitance of 0.7 fF/mm2 was formed between the first- and second-level metal layers by using a 50-nm-thick layer of plasma SiO2 as an insulator. The third- and fourth-level (3-mm-thick Al) metal layers made up high-Q spiral inductors. Eleven masks were used for the four-level structure of metal layers for interconnection, including the MIM capacitor. Precise resistors were formed from pþ poly-Si, with a ‘‘quasi-layer-on-layer’’ structure fabricated by Ge implantation, for medium and high sheet resistances (MR, HR) in the SiGe BiCMOS. A cross-sectional TEM image of a precise poly-Si resistor is shown in Figure 9.8. By using high-dose Ge implantation, roughly the upper half of the poly-Si layer with small grains as deposited (deposition temperature TD was higher than 6008C) became amorphous. It then changed to large-grain poly-Si by recrystallization after annealing. The ‘‘quasi-layer-on-layer’’ structure was thus fabricated. The temperature coefficient TC of resistance for large-grain poly-Si is positive, while that for small-grain poly-Si is negative. Therefore, these opposite characteristics act to cancel out the temperature dependence of the resistance. Furthermore, this

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Poly-Si deposition (TD>600C) Small-grain poly-Si

B and Ge I/I (high dose) Amorphous Si Small-grain poly-Si

Annealing (recrystallization)

Positive TC

Large-grain poly-Si Small-grain poly-Si Negative TC

Large grains

Small grains

50 nm FIGURE 9.8 Cross-sectional TEM image of a precise poly-Si resistor formed from pþ poly-Si with a ‘‘quasi-layeron-layer’’ structure fabricated by Ge implantation, for both medium sheet resistance (MR) and high sheet resistance (HR) in the SiGe BiCMOS. (From K. Washio. IEEE Trans. Electron Devices 50:656–668, 2003. With permission.)

‘‘quasi-layer-on-layer’’ structure made the precise control of the sheet resistance possible; the sheet resistance was mainly determined by the thickness of the upper large-grain poly-Si layer with low resistivity, and its thickness could be controlled well by the Ge-implantation energy. The parameters of the passive elements are summarized in Table 9.3. An ordinary nþ poly-Si resistor, LR (low sheet resistance of 65 V/sq.), had a temperature coefficient of 600 ppm/8C. On the other hand, both types of pþ poly-Si resistors with a ‘‘quasi-layer-on-layer’’ structure, MR (medium sheet resistance of 220 V/sq.) and HR (high sheet resistance of 635 V/sq.), had low temperature coefficients of 330 and 180 ppm/8C, respectively. The MIM capacitor with an area of 50 100 mm and a capacitance of 4.2 pF, which is usually used to stabilize the supply voltage, had an adequate Q of 13 at 10 GHz. In 10 parallelconnected varactors, each with a SiGe-base and Si-collector junction area of 2.3 2.3 mm, the ratio of Cmax to Cmin for VCB of 0 to 3 V was 1.8 and Q was 45 at 10 GHz and a VCB of 1.5 V. This high-Q varactor is applicable to oscillators with a high-purity signal spectrum for use in mobile communications. A three-turn square (132 mm on the outer sides) spiral inductor with a cavity at the center and a line width/line-to-line space of 6/3 mm was formed on a standard low-resistivity substrate (LRS) in the SiGe HBT process. It had L value of 1.36 nH and Q of 8.8 at 5.8 GHz, and L of 1.45 nH and Q of 15.1 at 10 GHz. The octagonal spiral inductor on the SOI/HRS was compared with that on an SOI/LRS. The width and spacing were 9 and 3 mm, respectively. The frequency dependence of the inductance was the

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Industry Examples at the State-of-the-Art: Hitachi TABLE 9.3 Resistor

Passive-Element Parameters nþ poly (LR) pþ poly (MR) pþ poly (HR)

Capacitor

MIM

Varactor

MOS SiGe/Si

Inductor

Oct. spiral

65 V/sq. 600 ppm/8C 220 V/sq. 330 ppm/8C 635 V/sq. 180 ppm/8C 0.7 fF/mm2 13 Q(10 GHz) 4.7 fF/mm2 1.8 (Cmax/Cmin) 45 Q(10 GHz) 0.95/19 nH/Q (10 GHz)

Source : K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. IEEE Trans. Electron Devices 49:271–278, 2002. With permission.

same on the HRS and LRS; however, Q of the HRS became higher at frequencies above 5 GHz, and Q at 15 GHz on the HRS was about twice that on the LRS. These results indicate that the high-resistivity substrate is effective in reducing conductive loss through the Si substrate in the microwave band. The octagonal spiral inductor on the HRS, with an L value of 0.95 nH, showed a high-Q of 19 at 10 GHz.

9.5

Summary

Self-aligned SiGe HBT and BiCMOS technologies have been developed. A Si-cap/SiGe-base multilayer fabricated by the SEG method was applied to improve both high-speed and low-power performance of the SiGe HBTs. The process is almost completely compatible with well-established Si BiCMOS technology, and the SiGe HBT and BiCMOS were fabricated on a 200-mm wafer line. To meet the demand for the integration of sophisticated functions, high-quality passive elements, including a high-precision poly-Si resistor, a high-Q varactor, an MIM capacitor, and a high-Q spiral inductor, have also been developed.

Acknowledgments The author would like to express his sincere thanks to Dr. A. Anzai, Dr. Y. Hatta, and H. Hosoe at the Hitachi Device Development Center (HDDC), and Dr. O. Kanehisa, Dr. K. Seki, and K. Kimura at the Hitachi Central Research Laboratory (HCRL) for their encouragement. The author would also like to express his sincere thanks to Dr. T. Onai, E. Ohue, K. Oda, Dr. M. Kondo, H. Shimamoto, M. Tanabe, R. Hayami, Dr. Y. Kiyota, I. Suzumura, Dr. M. Miura, A. Kodama at HCRL, and to T. Harada, K. Mikami, T. Hashimoto, S. Wada, T. Tominari, K. Tokunaga at HDDC for their extensive contributions throughout this work.

References 1. K. Washio, M. Kondo, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, and T. Harada. A 0.2-mm self-aligned selective-epitaxial-growth SiGe HBT featuring 107-GHz fmax and 6.7-ps ECL. IEEE Trans. Electron Devices 48:1989–1994, 2001. 2. K. Oda, E. Ohue, M. Tanabe, H. Shimamoto, T. Onai, and K. Washio. 130-GHz fT SiGe HBT technology. Technical Digest of the IEEE International Electron Devices Meeting, Washington, DC, 1997, pp. 791–794.

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3. K. Washio, E. Ohue, K. Oda, M. Tanabe, H. Shimamoto, T. Onai, and M. Kondo. A selectiveepitaxial-growth SiGe-base HBT with SMI electrodes featuring 9.3-ps ECL-gate delay. IEEE Trans. Electron Devices 46:1411–1416, 1999. 4. K. Washio. SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems. IEEE Trans. Electron Devices 50:656–668, 2003. 5. T. Hashimoto, T. Kikuchi, K. Watanabe, N. Ohashi, T. Saito, H. Yamaguchi, S. Wada, N. Natsuaki, M. Kondo, S. Kondo, Y. Homma, N. Owada, and T. Ikeda. A 0.2-mm bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processors. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1998, pp. 209–212. 6. E. Ohue, R. Hayami, K. Oda, H. Shimamoto, and K. Washio. 5.3-ps ECL and 71-GHz static frequency divider in self-aligned SEG SiGe HBT. Technical Digest of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 26–29. 7. K. Washio, E. Ohue, K. Oda, R. Hayami, M. Tanabe, and H. Shimamoto. Optimization of characteristics related to the emitter-base junction in self-aligned SEG SiGe HBTs and their application in 72-GHz-static/92-GHz-dynamic Frequency Dividers. IEEE Trans. Electron Devices 49:1755–1760, 2002. 8. K. Oda, E. Ohue, I. Suzumura, R. Hayami, K. Kodama, H. Shimamoto, and K. Washio. Highperformance self-aligned SiGeC HBT with selectively grown Si1xyGexCy base by UHV/CVD. IEEE Trans. Electron Devices 50:2213–2220, 2003. 9. T. Tominari, S. Wada, K. Tokunaga, K. Koyu, M. Kubo, T. Udo, M. Seto, K. Ohhata, H. Hosoe, Y. Kiyota, K. Washio, and T. Hashimoto. Study on extremely thin base SiGe:C HBTs featuring sub 5-ps ECL gate delay. Technical Digest of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, France, 2003, pp. 107–110. 10. K. Washio, E. Ohue, R. Hayami, A. Kodama, H. Shimamoto, M. Miura, K. Oda, I. Suzumura, T. Tominari, and T. Hashimoto. High-speed scaled-down self-aligned SEG SiGe HBTs. IEEE Trans. Electron Devices 50:2417–2424, 2003. 11. K. Washio, E. Ohue, H. Shimamoto, K. Oda, R. Hayami, Y. Kiyota, M. Tanabe, M. Kondo, T. Hashimoto, and T. Harada. A 0.2-mm 180-GHz-fmax 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications. IEEE Trans. Electron Devices 49:271–278, 2002. 12. K. Washio, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, T. Harada, and M. Kondo. 82GHz dynamic frequency divider in 5.5ps ECL SiGe HBTs. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference, San Francisco, 2000, pp. 210–211. 13. S. Wada, Y. Nonaka, T. Saito, T. Tomonari, K. Koyu, K. Ikeda, K. Sakai, K. Sasahara, K. Watanabe, H. Fujiwara, F. Murata, E. Ohue, Y. Kiyota, H. Shimamoto, K. Washio, R. Takeyari, H. Hosoe, and T. Hashimoto. A manufacturable 0.18-mm SiGe BiCMOS technology for 40-Gb/s optical communication LSIs. Technical Digest of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 84–87. 14. T. Hashimoto, Y. Nonaka, T. Saito, K. Sasahara, T. Tomonari, K. Sakai, K. Tokunaga, T. Fujiwara, S. Wada, T. Udo, T. Jinbo, K. Washio, and H. Hosoe. Integration of a 0.13-mm CMOS and a high performance self-aligned SiGe HBT featuring low base resistance. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 779–782. 15. T. Hashimoto, Y. Nonaka, T. Tominari, H. Fujiwara, K. Tokunaga, M. Arai, S. Wada, T. Udo, M. Seto, M. Miura, H. Shimamoto, K. Washio, and H. Hosoe. Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm gate CMOS. Technical Digest of the IEEE International Electron Devices Meeting, Washington, DC, 2003, pp. 129–132.

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10 Industry Examples at the State-of-the-Art: Infineon

Thomas F. Meister, H. Scha¨fer, W. Perndl, and J. Bo¨ck Infineon Technologies AG

10.1

10.1 10.2 10.3 10.4 10.5 10.6

Introduction..................................................................... 10-1 Process Concept............................................................... 10-2 Transistor Fabrication Process ....................................... 10-3 Transistor Results ............................................................ 10-5 Additional Devices .......................................................... 10-9 Circuit Performance ...................................................... 10-10

Introduction

Recent advances [1–7] in state-of-the-art SiGe bipolar and BiCMOS technologies enabled impressive transistor parameters like maximum oscillation frequencies of 285 GHz [1], transit frequencies up to 350 GHz [2] and ring-oscillator gate delay times down to 3.5 psec [5,7]. Therefore, even very highfrequency applications like wireless LANs at 60 GHz, optical communications at 80 Gbit/sec and automotive radar systems around 77 GHz, which can now only be achieved by expensive III–V technologies, seem to become feasible in a low-cost silicon-based technology in a highly integrated manner. The progress in the high-speed performance of SiGe HBTs has been achieved by impurity profile engineering in the SiGe base for improving forward transit time and base resistance as well as by the development of self-aligned transistor architectures providing low parasitic capacitances and low extrinsic series resistances. The different self-aligned emitter–base configurations, which are used in present state-of-the-art SiGe HBT technologies, are requiring either nonselective epitaxial growth (NSEG) [1,2,5] or selective epitaxial growth (SEG) [3,4,6,7] for the integration of the SiGe base. As an example of such an advanced SiGe HBT technology, we describe here Infineon’s high-frequency SiGe bipolar technology. The SiGe technology is based on a double-polysilicon self-aligned (DPSA) transistor configuration, in which the shallow and highly boron-doped SiGe base layer is integrated by means of SEG. The first realizations of such transistors have used epitaxial silicon base layers which have been grown without Ge [8–10]. Because of the superior performance of the SiGe base over the epitaxial Si base, within the next couple of years processes for DPSA HBTs with selectively grown SiGe base layers have been developed [11–14]. Even the first of these DPSA HBTs that were fabricated in 1992 [11] exhibited a maximum oscillation frequency of 50 GHz and a ring oscillator gate delay time of 19 psec, which was state-of-the-art performance at that time. Using the DPSA HBT concept Infineon’s first SiGe bipolar technology, which has been taken into production for the wireless marketplace in the year 1999 [15], exhibited transit and maximum oscillation frequencies of about 75 GHz. In the meantime the transistor performance of DPSA HBTs with a selectively grown SiGe base could be improved considerably, resulting in bipolar and BiCMOS processes with transit and maximum 10-1

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oscillation frequencies of 200 GHz or above [3,4,6,7]. These advancements have been achieved for example by improvements in shallow base formation technology, which has resulted in reduced base thickness even for significantly increased base boron doping levels, as well as by minimizing the size of the transistors for commensurate improvements of base resistance, emitter–base capacitance, and base– collector capacitance. In the following we describe the process concept, the fabrication process, and the electrical results of Infineon’s actual high-frequency SiGe bipolar technology. The technology provides a transit frequency of 200 GHz, a maximum oscillation frequency of 275 GHz, and a ring oscillator gate delay time of 3.5 psec [7]. The bipolar technology is presently under investigation for the realization of very demanding high-frequency applications like 77 GHz automotive radar and optical communications up to 80 Gbit/sec.

10.2

Process Concept

A transmission electron microscopy (TEM) cross section of the npn transistor in the SiGe technology is shown in Figure 10.1. The transistor has a deep trench/shallow trench isolation which is commonly used in advanced SiGe HBT technologies. The transistor isolation has a completely planar surface topography which is of great advantage for the realization of small feature sizes and small lithographic alignment tolerances in order to minimize the sizes of the transistors. In addition the deep trenches are useful in enabling the realization of high transistor packing densities in circuits and also allow the realization of small subcollector dimensions for achieving low values of the collector–substrate capacitance. The transistor, which is built onto this transistor isolation, has a DPSA emitter–base structure, which uses highly boron-doped and silicided polysilicon layers for contacting the SiGe base of the active transistor. These pþ-polysilicon base electrodes are separated self-aligned by a thin oxide spacer from the heavily arsenic-doped emitter layer. As compared to transistor concepts realizing the separation of the emitter from the extrinsic base regions by a photolithographic alignment step, the self-alignment of the emitter–base structure is very advantageous for achieving low values of base resistance and base– collector capacitance. In our SiGe technology the SiGe base layer is integrated by SEG, which has also allowed the formation of a self-aligned base–collector structure [9–14]. Similar to the other most advanced high-frequency SiGe HBT technologies [1–7], the SiGe base contains a certain amount of carbon for realizing very thin and highly boron-doped base layers with steep doping profile gradients [16,17]. Another feature of the SiGe technology is the heavily arsenic-doped monocrystalline emitter

FIGURE 10.1

TEM cross section of a fabricated transistor.

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10-3

contact [7,18,19], which, as compared with conventional polysilicon emitters, reduces the emitter resistance of laterally downscaled transistors considerably. Finally, since in high-frequency SiGe bipolar technologies the SiGe HBTs are operating at high current densities, we use a copper metallization system. In comparison with a conventional aluminum metallization, the copper metallization has the advantage of a significantly improved electromigration hardness and lifetime at high current densities. In the copper metallization, consisting of four metallization layers, also a high-precision TaN resistor, and an MIM capacitor have been integrated [20].

10.3

Transistor Fabrication Process

After having described the basic process concept, the transistor fabrication sequence is given in this section. The main emitter–base fabrication steps are outlined in Figure 10.2. After the fabrication of the deep trench/shallow trench transistor isolation a CVD-oxide layer is deposited. Then the pþ-polysilicon base electrodes, a CVD-oxide layer, and a nitride layer are deposited. The stack made of these three layers is patterned by reactive ion etching (RIE) for forming the emitter window (Figure 10.2a). Then a nitride/ oxide stack consisting of a 20-nm thick nitride and a 50-nm thick oxide layer is deposited and spacers— made of the material of the nitride/oxide stack—are formed inside the emitter window by RIE (Figure 10.2b). Outside the emitter window the nitride/oxide stack is protected during this RIE by resist. Now a phosphorus implantation into the emitter window is done for forming the selectively implanted collector. The collector implantation is automatically self-aligned to the active transistor region and therefore advantageous for realizing low base–collector capacitance. Moreover, since the spacers inside the emitter window significantly reduce the implantation area for collector implantation a reduction of base–collector capacitance of about 20% is observed as compared to a collector implantation through the whole emitter window [6]. Since the collector implantation is performed before SiGe base deposition any broadening of the boron impurity profile in the SiGe base layer due to implantation damageinduced point defects is avoided in this transistor concept. This is different from the transistor concepts using NSEG for base integration. In these transistors, a collector implantation, which is self-aligned to the active transistor region, can be only performed after the SiGe base deposition process. After collector implantation the CVD-oxide layer, which is covering the collector region, is removed by a wet etch in the active transistor region. The wet etch is performed until self-aligned adjusted pþ-polysilicon overhangs of about 100 nm over the CVD-oxide layer beneath have been formed (Figure 10.2c). During this wet oxide etch, the nitride layer of the nitride/oxide stack serves to protect the isolation regions. Now the SiGe base layer is integrated by SEG. The deposition is performed in a radiation-heated single wafer reactor using a gas mixture of H2, SiH2Cl2, HCl, GeH4, B2H6, and SiH3CH3. The HCl is used for ensuring the selective growth conditions whereas the SiH3CH3 is added to achieve the incorporation of substitutional carbon in the SiGe base [16,17] during SEG. The growth parameters of the SiGe base deposition process and their optimization for avoiding loading effects and for improving manufacturability are described in detail in Ref. [21]. Under these selective deposition conditions no growth takes place on the transistor and isolation regions which are covered by the nitride layers (Figure 10.2c). Monocrystalline growth of the SiGe base occurs only at the opened collector regions and polysilicon growth only at the overhanging parts of the extrinsic base polysilicon electrodes. During the selective base deposition process the intrinsic SiGe base layer, which is growing bottom up on the collector, is connected with the polycrystalline base link region, which is growing top down from the base electrodes. After base deposition the thin nitride spacers and the sacrificial nitride layers on top of the structure are removed in phosphoric acid (Figure 10.2d). Then the oxide spacers which serve for the self-aligned separation of the heavily doped emitter layer from the heavily borondoped extrinsic base regions are formed inside the emitter window. Now the heavily arsenic-doped emitter layer is deposited by NSEG in a radiation-heated CVD reactor. After the in situ removal of the native oxide layer on the silicon substrate by a bake in H2 atmosphere,

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CVD-Oxide

Nitride

p+-poly (a) n− CVD-Oxide Nitride/oxide stack

(b)

Nitride/oxide spacer

p+-poly n−

n

Nitride

n−

STI

p+-Poly overhang

p+-poly

p+-poly

(c) n−

n

n−

Monocrystalline SiGe base

STI

Polycrystalline base link

p+-poly

p+-poly P

(d) n

SiGe base

−

n

n+-mono

n−

STI

n+-poly

p+-poly

p+-poly

(e)

P n

−

n

n−

STI

FIGURE 10.2 Fabrication steps of emitter–base structure. (a) Formation of emitter window, (b) deposition of nitride/oxide stack, nitride/oxide spacer formation by RIE using a photomask, self-aligned collector implantation, (c) wet oxide etch for self-aligned formation of pþ-polysilicon overhangs, (d) SiGe base deposition by selective epitaxy, removal of nitride spacers, and sacrificial nitride layers by wet etching, and (e) formation of oxide spacers inside the emitter window, fabrication of emitter.

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Industry Examples at the State-of-the-Art: Infineon

this deposition is performed in the CVD reactor at a temperature of 5508C using disilane as silicon source and arsine as dopant source. Under these deposition conditions, the 1021 cm3 arsenic-doped emitter layer grows monocrystalline on the silicon area of the active transistor region and amorphous on the surrounding isolation regions with a high growth rate of about 70 nm/min. After patterning the NSEG grown nþ-emitter layer, a rapid thermal annealing (RTA) step is performed, which diffuses the emitter about 20 nm deep into the underlying silicon cap of the base. During this emitter drivein, the amorphous parts of the nþ-emitter layer become polycrystalline (Figure 10.2e). After the emitter drive-in, processing is completed by salicidation of the base electrodes and by forming the copper metallization.

10.4

Transistor Results

A TEM cross section through the emitter–base configuration of the fabricated transistors is shown in Figure 10.3. The mask width of the emitter window is 0.3 mm and the width of the oxide spacers which are used for the self-aligned separation of the emitter from the pþ-polysilicon base electrodes is 80 nm. The resulting effective emitter width is only 0.14 mm. These small values of emitter width are effective for realizing low values of base resistance and emitter–base capacitance. The thin SiGe base layer is confined within the walls defined by the CVD-oxide layer, which lies under the pþ-polysilicon base electrodes. As already described in the fabrication process (Figure 10.2c) the overlay between the pþpolysilicon and the CVD-oxide layer below has been adjusted self-aligned to about 100 nm. In the final transistors this results in a self-alignment of the base/collector structure, which means that the size of the contact region between the extrinsic base electrodes and the SiGe base layer is adjusted independently on a photolithographic alignment step. This self-alignment is advantageous for realizing low values of base– collector capacitance. As seen from the micrograph in Figure 10.3 the heavily arsenic-doped nþ-emitter layer is monocrystalline in the active transistor region. The monocrystalline emitter has the advantage of the absence of any interfacial oxide layer between the nþ-emitter contact layer and the underlying silicon cap of the base where the active emitter is diffused in. This is different from polysilicon emitter transistors. In such transistors always a thin interfacial oxide layer is located between the nþ-polysilicon and the underlying silicon substrate, which often breaks up during the emitter drive-in [22]. The thickness of such an interfacial oxide layer is difficult to control and significantly affects the emitter resistance and base currents in polysilicon emitter transistors. The replacement of the polysilicon emitter by the monocrystalline emitter contact has therefore improved emitter resistance and manufacturability of our SiGe HBTs considerably. The emitter resistance has been measured on devices with an emitter length of 2.6 mm by using the modified open collector method described in Ref. [23]. Figure 10.4 compares the emitter resistances of transistors with monocrystalline and polycrystalline emitter contacts for various

CVD -oxide

p+-poly n+-mono Si

STI SiGe-base

100 nm

FIGURE 10.3 0.14 mm.

TEM cross section of the emitter–base complex of a transistor with effective emitter width of

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values of effective emitter widths. In the polysilicon emitter HBTs the thickness of the interfacial oxide layer has been kept as thin as possible. Nevertheless, for an effective emitter width of 0.18 mm the transistors with monocrystalline emitter exhibit an emitter resistance of only 2.6 V, which is more than 50% lower than the emitter resistance of the polysilicon emitter control HBTs. As can be also seen from Figure 10.4 this advantage of the transistors with monocrystalline emitter contact increases with decreasing emitter width and becomes most pronounced in devices with very small effective emitter width. Also, since the interfacial oxide in polysilicon emitter HBTs is a dominant 1/f noise source, it has been found in Ref. [18] that a monocrystalline emitter contact is very effective for improving 1/f noise in high-speed SiGe HBTs. The SIMS doping profile of the fabricated transistors is shown in Figure 10.5. By the self-aligned collector implantation which has been described in Section 10.3, a high collector doping level of 1 1018 cm3 has been employed for realizing high current-carrying capability of the transistors. In the SiGe base layer a maximum Ge fraction of 25% has been used. The Ge profile has been steeply graded across the base to achieve an accelerating drift field for the electrons to increase the transit frequency. In the base a boron spike with high concentration of 4 1019 cm3 has been grown to enable the low base sheet resistance of 2.8 kV/sq. At the emitter side the base is lowly doped with a concentration of 1 1018 cm3 in order to obtain a small emitter–base capacitance. For realizing high transit frequency the

Ω

n+-poly Si emitter n+-mono Si emitter

6

LE = 2.6 µm RE

4

2

0 0.1

0.2

0.3

0.4

WE (µm)

FIGURE 10.4

Emitter resistance RE vs. effective emitter width WE. 30 Base

Collector 25

1021 As

Ge 20 15

1019

C

10

B P 1017 0.05

FIGURE 10.5

0.10

0.15 Depth (mm)

SIMS doping profile of the fabricated transistors.

0.2

5 0 0.25

Ge (%)

Concentration (cm-3)

Emitter

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thickness of the boron spike must be kept as thin as possible during the processing steps and annealing cycles following SiGe base deposition for transistor fabrication. Therefore, as the incorporation of carbon on substitutional sites with typical concentrations between 1 1019 and 5 1019 cm3 reduces the diffusion of boron in Si and SiGe layers significantly [16,17], the region around the boron spike has been carbon doped with a chemical concentration of 3 1019 cm3. From this chemical carbon concentration, about 80% was found to be substitutional by x-ray diffraction (XRD). This incorporation of substitutional carbon during SiGe base deposition has effectively reduced the broadening of the base boron dopant profile in the processing steps after SEG. In combination with low-temperature processing therefore steep boron doping profiles have been achieved, resulting in a final metallurgical base width of 27 nm. Despite the highly boron-doped and aggressively vertical-scaled SiGe base profile the transfer characteristics of the fabricated transistors are ideal. Figure 10.6 shows the typical transfer characteristics of transistors with an effective emitter size of 0.14 2.6 mm2. For a base–emitter voltage of 0.8 V the typical current gain is 250. Also shown in Figure 10.6 is the typical transfer characteristic of a transistor array. These transistor arrays are configured with 7000 transistors connected in parallel. The transistor arrays have an emitter area of 7000 0.18 2.6 mm2 and are used for monitoring the transistor yield. As shown in Ref. [7] the typical emitter–base yield of these transistor arrays is near 100% and the collector– emitter yield is about 80%. Figure 10.7 shows the common emitter output characteristics of transistors with an emitter area of 0.14 2.6 mm2. The collector–emitter breakdown voltage BVCE0, which is measured with open base is 1.7 V. The high-frequency performance of the SiGe HBTs has been evaluated using S-parameter measurements up to 30 GHz. The transit frequency fT has been extrapolated from the small signal current gain jh21j2 using transistors with an emitter area of 0.14 2.6 mm2. Figure 10.8 shows the dependency of transit frequency fT on the collector current IC for different base–collector voltages VBC. The transit frequency reaches its maximum of 200 GHz at VBC ¼ 0 and a collector current density of about 8 mA/mm2. The maximum oscillation frequency fmax has been extrapolated from Mason’s unilateral gain U [24] at 25 GHz with 20 dB/dec role-off. Figure 10.9 shows the dependency of the maximum oscillation frequency on collector current. At VBC ¼ 1 V the maximum oscillation frequency peaks at 275 GHz. Figure 10.10 shows the measured frequency dependence of the small signal current gain jh21j2, the maximum stable gain MSG and the unilateral gain U at the bias conditions (VBC ¼ 1 V, IC ¼ 3.5 mA) where the maximum oscillation frequency reaches its optimum. The transition from the maximum stable gain MSG to the maximum available gain occurs at a frequency higher than 30 GHz. The high values of fmax originate from the integration of the thin base layer into a self-aligned transistor

10−2

7000 transistor array

IC,IB (A)

10−4 10−6 10−8

single transistor

10−10 10−12 0

0.2

0.4

0.6 0.8 VBE (V)

1

1.2

FIGURE 10.6 Transfer characteristics of a transistor with AE ¼ 0.14 2.6 mm2 and a transistor array with AE ¼ 7000 0.18 2.6 mm2.

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4

I B = 0, 5, 10, 15, 20, 25 µA

IC (mA)

3

2

1

BVCE0 = 1.7 V 0 0

FIGURE 10.7

0.5

1

1.5 VCE (V)

2

2.5

3

Common emitter output characteristics of transistors with AE ¼ 0.14 2.6 mm2.

250

300

275 GHz

200 GHz

VCB = 1 V fmax (GHz)

f T (GHz)

200 VCB =1 V

150 100 50 0 0.01

200

100 VCB = 0 V VCB = 0 V 0.1 1 10 Collector current (mA)

0 0.01 100

FIGURE 10.8 Cut-off frequency fT vs. collector current for transistors with AE ¼ 0.14 2.6 mm2.

0.1 1 10 Collector current (mA)

100

FIGURE 10.9 Maximum oscillation frequency fmax vs. collector current for transistors with AE ¼ 0.14 2.6 mm2.

architecture, providing low capacitances and extrinsic series resistances. Furthermore the high fmax values could be achieved by careful optimization of the highly boron-doped base for achieving simultaneously high transit frequency and low base sheet resistance. Table 10.1 summarizes the most important transistor parameters. The tradeoffs between these transistor parameters have been optimized for a balanced compromise to enable high-frequency circuit applications. The high values of transit frequency have been combined with a low base resistance RB of 50 V. The open-base collector–emitter breakdown voltage BVCE0 is 1.7 V and the open-emitter collector– base breakdown voltage BVCB0 is 5.8 V. The maximum sustainable operating voltage of a SiGe HBT generally lies between BVCE0 (worst case) and BVCB0 (best case). The values for emitter–base capacitance CEB, base–collector capacitance CBC, and collector–substrate capacitance CCS in Table 10.1 refer to unbiased junctions and include the wiring parasitic capacitances up to the first metallization layer. Taking into account the high base and collector doping levels, which have been employed in the

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40 U

Gain (dB)

30 20

VCB = 1 V IC = 3.5 mA

MSG |h21|2

275 GHz

10 190 GHz

0 1

10 100 Frequency (GHz)

1000

FIGURE 10.10 Frequency dependence of the small signal current gain jh21j2, the maximum stable gain MSG, and the unilateral gain U for transistors with AE ¼ 0.14 2.6 mm2.

TABLE 10.1 Device Parameters of the High-Speed npn Transistor with AE ¼ 0.14 2.6 mm2 AE b RBI BVCE0 BVCB0 CEB CBC CCS RB RE fT fmax Gate delay

0.14 2.6 mm2 250 2.8 kV/sq. 1.7 V 5.8 V 6.3 fF 5.5 fF 3.7 fF 50 V 3.5 V 200 GHz 275 GHz 3.5 psec

technology for achieving high transit frequency, high current-carrying capability and low base resistance, the DPSA emitter–base configuration has provided reasonable low values for emitter–base and base–collector capacitances of 6.3 and 5.5 fF, respectively.

10.5

Additional Devices

To enable high-performance circuit applications several additional devices have been added to the highfrequency npn transistor. Table 10.2 summarizes all devices which are available in the technology. In addition to the high-frequency npn transistors which have been described before, two other types of npn transistors are offered on the wafers. Table 10.3 summarizes the device parameters of the three different npn transistor types. These npn transistors have been optimized for different tradeoffs between transit frequency fT and base–collector breakdown voltage BVCB0. By using additional mask steps in the process flow, the npn transistors differ in the collector implantation doses. As compared to the high-frequency npn1 transistor, the reduction of the collector doping level in the additional npn transistors has resulted in increased base–collector breakdown voltages of 8.3 and 10.5 V, respectively. This is resulting in a transit frequency of 135 GHz for the npn2 transistor and in a transit frequency of 80 GHz for the npn3 transistor. As seen from Table 10.2 also three types of resistors and an MIM capacitor are available. The resistors poly R1 and poly R2 are made of the pþ-polysilicon base electrodes but with less boron doping. The two polysilicon resistors have sheet resistances of 150 and 1000 V/sq., respectively. The high-precision TaN

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Fabrication of SiGe HBT BiCMOS Technology TABLE 10.2

Available Devices fT ¼ 200 GHz, BVCB0 ¼ 5.8 V fT ¼ 135 GHz, BVCB0 ¼ 8.3 V fT ¼ 80 GHz, BVCB0 ¼ 10.5 V 150 Ohm/sq. 1000 Ohm/sq. 20 Ohm/sq. 1.4 fF/mm2

npn1 npn2 npn3 Poly R1 Poly R2 TaN R3 MIM

TABLE 10.3 Device Parameters of the Three Different npn Transistor Types (AE ¼ 0.14 2.6 mm2)

fT (GHz) fmax (GHz) CBC (fF) BVCE0 (V) BVCB0 (V)

npn1

npn2

npn3

200 275 5.5 1.7 5.8

135 285 4.6 2.0 8.3

80 225 3.6 3.1 10.5

metal resistor and the MIM capacitor are described in more detail in Ref. [20]. The TaN metal resistor is placed between the first and the second copper metallization layer and has a sheet resistance of 20 V/sq. The MIM capacitor has a specific capacitance of 1.4 fF/mm2 and is integrated between the second and third metallization layer. The MIM capacitor uses a 50-nm thick Al2O3 dielectric layer, which has been deposited by atomic layer deposition.

10.6

Circuit Performance

In this section we describe the ring oscillator gate delay performance. Additionally we discuss some of the circuit results which have been achieved in our SiGe bipolar technology. The ring oscillator gate delay performance is a very good figure-of-merit for the digital circuit speed of a bipolar technology since it accounts for the effects of all transistor parameters and local wiring parasitic elements on the performance of a gate. The gate delay of our SiGe technology has been evaluated by ring oscillators using the power-saving current-mode logic (CML) circuit principle. The CML ring oscillators operate with 2.2 V supply voltage and a differential voltage swing of 400 mV. The dependency of the gate delay time on switching current is shown in Figure 10.11 for a position in the center of a wafer. A minimum gate

Gate delay (psec)

30

20

10

0 0.1

FIGURE 10.11

td = 3.5 ps

1 Igate (mA)

10

CML ring oscillator gate delay vs. current per gate Igate (AE ¼ 0.14 2.6 mm2).

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delay time of 3.5 psec is achieved at a switching current density of 8 mA/mm2. This state-of-the-art result demonstrates the well-balanced compromise between the important device parameters in Table 10.1. Figure 10.12 shows the distribution of the minimum gate delay time over a wafer. The mean value is 3.63 psec at a standard deviation of only 1.5%. Figure 10.13 shows the trend of the minimum gate delay in the wafer center over a lot of 15 wafers. The minimum and maximum values over the lot are 3.49 and 3.59 psec, respectively. These results demonstrate that the technology has the performance, homogeneity, and reproducibility needed for advanced high-quality circuit fabrication. To give an impression of application fields which seem to become feasible with high-speed SiGe technologies, we now briefly summarize the results of some high-frequency circuits, which have been fabricated in our technology. The frequency divider results are shown in Table 10.4. The dynamic frequency divider uses the principle of regenerative frequency division and has a divide ratio of 2. The circuit operates with a total supply current of 62 mA up to 110 GHz [25]. The static frequency divider has a divide ratio of 32 and operates up to 86 GHz [25]. This divider is based on the E2CL circuit principle and uses no pretracking technique [26] for further enhancement of operating frequency. Such frequency dividers are key circuit elements in a wide variety of application fields as for example in optical communications and measurement equipment.

[psec]

3.67

3.68

3.75

3.67

3.65

3.62

3.66

3.69

3.67

3.65

3.61

3.54

3.60

3.66

3.71

3.69

3.65

3.58

3.50

3.55

3.63

3.67

3.65

3.59

3.54

3.58

3.65

3.68

3.66

3.60

3.60

3.63

3.62

3.58

3.57

FIGURE 10.12 Wafer map of the ring oscillator gate delay at a switching current density jC ¼ 8 mA/mm2 (AE ¼ 0.14 2.6 mm2).

4.0 3.8 Gate 3.6 delay (psec) 3.4 3.2 3.0 0

5

10

15

Wafer

FIGURE 10.13

Minimum gate delay over a lot of 15 wafers (AE ¼ 0.14 2.6 mm2, jC ¼ 8 mA/mm2).

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Fabrication of SiGe HBT BiCMOS Technology TABLE 10.4

Frequency Divider Data

Divide ratio Frequency range Supply voltage Supply current

Static Frequency Divider

Dynamic Frequency Divider

32 86.2 GHz 5.0 V 180 mA

2 35–110 GHz 5.0 V 62 mA

Source : H Knapp et al. International Microwave Symposium, 2003, pp. 1067–1070. With permission.

TABLE 10.5

Data of Lumped-Element Broadband Amplifier

Frequency range Gain Noise Total Output power Supply voltage Supply current

Broadband Amplifiera

VCO with Integrated Bufferb

3 dB-bandwidth: 62 GHz 16 dB — — 5.0 V 155 mA

74–80.5 GHz — Phase noise (1 MHz offset): <–95 dBc/Hz >18 dB m 5.5 V 218 mA

Active Mixerc 72.3–82.5 GHz >24 dB SSB noise figure: <14 dB — 5.0 V 60 mA

a

From W Perndl et al. Proceedings BCTM, 293–296, 2004. From H Li et al. Journal of Solid-State Circuits, 263–266, 2004. c From W Perndl et al. Radio Frequency Integrated Circuits (RFIC) Symposium, 47–50, 2004. With permission. b

The results of a monolithic integrated broadband amplifier [27] are summarized in Table 10.5. The broadband amplifier is based on lumped elements and is designed for differential input and output signals. The amplifier has a differential gain of 16 dB, a 3-dB bandwidth of 62 GHz and consumes 155 mA at a supply voltage of 5 V. The clear output eye diagram at a data rate of 80 Gbit/s [27] demonstrates the feasibility of the circuit for optical communications at 80 Gbit/s. To investigate the suitability of high-speed SiGe technologies for automotive radar applications at 77 GHz, we have also fabricated first key building blocks like VCOs and mixers. The results of these circuits are also summarized in Table 10.5. The 77-GHz VCO [28] including the resonant circuit and the output buffer has been fully integrated on a single chip (1 mm2). The output buffer has two outputs and has been designed for achieving high output power, which is required in 77-GHz automotive radar applications. The VCO is operating in the frequency range between 74 and 80.5 GHz with a phase noise of 95 dBc/Hz at 1 MHz offset. The total signal power of both buffer outputs is as high as 18 dB m and the total power consumption of the circuit is 1.2 W. The active mixer [29] for down-conversion in Table 10.5 consists of a mixer core based on the Gilbert cell and an on-chip balun at the RF input in order to provide a single-ended input. In the frequency range of 72 to 82 GHz the mixer has a gain of more than 24 dB and a single-sideband (SSB) noise less than 14 dB. These results show that demanding application fields like 77-GHz automotive radar which seemed to be reserved for III–V semiconductor technologies in the past, are now feasible in high-speed SiGe bipolar technologies in a highly integrated manner.

References 1. B Jagannathan, M Khater, F Pagette, JS Rieh, D Angell, H Chen, J Florkey, F Golan, DR Greenberg, R Groves, SJ Jeng, J Johnson, E Mengistu, KT Schonenberg, CM Schnabel, P Smith, A Stricker, D Ahlgren, G Freeman, K Stein, S Subbanna, Self-aligned SiGe npn transistors with 285 GHz fmax and 207 GHz fT in a manufacturable technology. IEEE Electronic Device Letters, 24: 324–326, 2003.

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2. JS Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, SJ Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, S Subbanna, SiGe HBTs with cut-off frequency of 350 GHz. IEDM Technical Digest: 121–124, 2002. 3. T Tominari, S Wada, K Tokunaga, K Koyu, M Kubo, T Udo, M Seto, K Ohhata, H Hosoe, Y Kiyota, K Washio, T Hashimoto, Study on extremely thin base SiGe HBTs featuring sub 5 ps ECL gate delay, Proceedings BCTM: 107–110, 2003. 4. T Hashimoto, Y Nonaka, T Tominari, H Fujiwara, K Tokunaga, M Arai, S Wada, T Udo, M Seto, M Miura, H Shimamoto, K Washio, H Tomioka, Direction to improve SiGe BICMOS technology featuring 200 GHz SiGe HBT and 80nm gate CMOS. IEDM Technical Digest: 129–132, 2003. 5. H Ru¨cker, B Heinemann, R Barth, D Bolze, J Drews, U Haak, W Hoppner, D Knoll, K Kopke, S Marschmeyer, HH Richter, P Schley, D Schmidt, R Scholz, B Tillack, W Winkler, HE Wulf, Y Yamamoto, SiGe:C BiCMOS technology with 3.6 ps gate delay. IEDM Technical Digest: 121–124, 2003. 6. TF Meister, H Scha¨fer, K Aufinger, R Stengl, S Boguth, R Schreiter, M Rest, H Knapp, M Wurzer, A Mitchell, T Bo¨ttner, J Bo¨ck, SiGe bipolar technology with 3.9 ps gate delay. Proceedings BCTM: 103–106, 2003. 7. J Bo¨ck, H Scha¨fer, K Aufinger, R Stengl, S Boguth, R Schreiter, M Rest, H Knapp, M Wurzer, W Perndl, T Bottner, TF Meister, SiGe bipolar technology for automotive radar applications. Proceedings BCTM: 84–87, 2004. 8. JN Burghartz, BJ Ginsberg, SR Mader, TC Chen, DL Harame, Selective epitaxy base transistor (SEBT), Electron Device Letters, IEEE, 9: 259–261, 1988. 9. F Sato, H Takemura, T Tashiro, H Hirayama, M Hiroi, K Koyama, M Nakamae, A self-aligned selective MBE technology for high-performance bipolar transistors. IEDM Technical Digest: 607– 610, 1990. 10. TF Meister, R Stengl, HW Meul, R Weyl, P Packan, A Felder, H Klose, R Schreiter, J Popp, HM Rein, L Treitinger, Sub-20 ps silicon bipolar technology using selective epitaxial growth, IEDM Technical Digest: 401–404, 1992. 11. F Sato, T Hashimoto, T Tatsumi, H Kitahata, T Tashiro, Sub-20 ps ECL circuits with 50 GHz fmax self-aligned HBTs. IEDM Technical Digest: 397–400, 1992. 12. TF Meister, H Scha¨fer, M Franosch, W Molzer, K Aufinger, U Scheler, C Walz, H Stolz, S Boguth, J Bo¨ck, SiGe base bipolar technology with 74 GHz fmax and 11 ps gate delay. IEDM Technical Digest: 739–742, 1995. 13. A Pruijmboom, D Terpstra, CE Timmering, WB de Boer, MJJ Theunissen, JW Slotboom, RJE Hueting, JJEW Hageraats, Selective epitaxial base technology with 14 ps ECL gate delay for low power wide-band communication systems. IEDM Technical Digest: 747–750, 1995. 14. K Washio E Ohue, K Oda, M Tanabe, H Shimamoto, T Onai, A selective-epitaxial SiGe HBT with SMI electrodes featuring 9.3 ps ECL-gate delay, IEDM Technical Digest: 795–798, 1997. 15. W Klein, BUH Klepser, 75 GHz Bipolar production technology for the 21st century, Proceedings of the ESSDERC: 88–94, 1999. 16. LD Lanzerotti, JC Sturm, E Stach, R Hull, T Buyuklimanli, C Magee, Suppression of boron outdiffusion in SiGe HBTs by carbon incorporation, Technical Digest IEDM: 249–252, 1996. 17. HJ Osten B Heinemann, D Knoll, G Lippert, H Ru¨cker, Effects of carbon on boron diffusion in SiGe: principles and impact on bipolar devices. Journal of Vacuum Science and Technology B, 16: 1750–1753, 1998. 18. S Jouan, R Planche, H Baudry, P Ribot, JA Chroboczek, D Dutartre, D Gloria, M Laurens, P Llinares, M Marty, A Monroy, C Morin, R Pantel, A Perrotin, J de Pontcharro, JL Regolini, G Vincent, A Chantre, A high-speed low 1/f noise SiGe HBT technology using epitaxially-aligned polysilicon emitters. IEEE Transactions on Electron Devices, 46: 1525–1529, 1999. 19. A Joseph, P Geiss, X Liu, J Johnson, K Schonenberg, A Chakravarti, D Ahlgren, J Dunn, Emitter resistance improvement in high-performance SiGe HBTs. Program of ISTDM, in Nagoya, Japan: 53– 54, 2003.

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20. M Schwerd, M Seck, T Huttner, T Bo¨ttner, S Drexl, B Hasler, A Mitchell, H Helneder, H Ko¨rner, V Kubrak, M Schrenk, R Lachner; A manufacturable 0.35 mm 150 GHz fT SiGe:C bipolar RF technology. Proceedings Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems: 10–13, 2003. 21. H Scha¨fer, J Bo¨ck, R Stengl, H Knapp, K Aufinger, M Wurzer, S Boguth, M Rest, R Schreiter, TF Meister, Selective epitaxial growth of SiGe:C for high-speed HBTs. Applied Surface Science, 224: 18–23, 2004. 22. H Schaber, TF Meister, Technology and physics of polysilicon emitters, Proceedings BCTM: 75–81, 1989. 23. R Gabl; M Reisch, Emitter series resistance from open-collector measurements – influence of the collector region and the parasitic pnp transistor, IEEE Transactions on Electron Devices, 45: 2457– 2465, 1998. 24. JD Cressler and G Niu. Silicon germanium heterojunction bipolar transistors. Artech House, Inc: 162–164, 2003. 25. H Knapp, M Wurzer, TF Meister, K Aufinger, J Bo¨ck, S Boguth, H Scha¨fer, 86 GHz static and 110 GHz dynamic frequency dividers in SiGe bipolar technology. International Microwave Symposium: 1067–1070, 2003. 26. K Washio, R Hayami, E Ohue, K Oda, M Tanabe, H Shimamoto, M Kondo, 67 GHz static frequency divider using 0:2 mm self-aligned SiGe HBTs. IEEE Radio Frequency Integrated Circuits Symposium: 31–34, 2000. 27. W Perndl; W Wilhelm, H Knapp, M Wurzer, K Aufinger, TF Meister, J Bock, W Simburger, AL Scholtz, A 60 GHz broadband amplifier in SiGe bipolar technology. Proceedings BCTM: 293–296, 2004. 28. H Li, HM Rein, T Suttorp, J Bock, Fully integrated SiGe VCOs with powerful output buffer for 77 GHz automotive radar systems and applications around 100 GHz. Journal of Solid-State Circuits, 39(10): 263–266, 2004. 29. W Perndl, H Knapp, M Wurzer, K Aufinger, TF Meister, J Bo¨ck, W Simbu¨rger, AL Scholtz, A lownoise and high-gain double balanced mixer for 77 GHz automotive radar front-end in SiGe bipolar technology. Radio Frequency Integrated Circuits (RFIC) Symposium: 47–50, 2004.

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11 Industry Examples at the State-of-the-Art: IHP 11.1 11.2 11.3

Introduction..................................................................... 11-1 History of IHP’s SiGe and SiGe:C HBT Technologies..................................................................... 11-2 High-Performance SiGe:C BiCMOS Processes ............. 11-3 85 GHz SiGe:C BiCMOS (SGC25A) . 120 GHz SiGe:C BiCMOS (SGC25B) . 200 GHz SiGe:C BiCMOS (SGC25C)

11.4 11.5 11.6

Dieter Knoll

11.1

60 GHz Transceiver Circuits . Automotive Radar

11.7

IHP

High-Speed, Complementary SiGe:C HBTs in a BiCMOS Technology ............................................... 11-9 Low-Cost SiGe:C BiCMOS Process with a One-Mask HBT Module (SGB25V) ......................... 11-12 Circuit Applications of IHP’s SiGe:C Technologies................................................................... 11-14 Summary ........................................................................ 11-19

Introduction

IHP is an R&D institute mainly financed by the German federal and the Brandenburg state governments. The purpose of IHP’s R&D activities is to create innovative solutions for wireless and broadband communication systems by close cooperative work of competent teams working in the fields of material research, process technology, circuit design, and systems. Cooperation in all these fields with partners from industry, universities, or other R&D institutes is also a common practice. The institute currently operates a 1000 m2 class-1 cleanroom, equipped with a tool set capable for 8-inch Si wafer processing and sub-0.25 mm feature size. In this chapter, we will describe IHP’s modular SiGe:C RF BiCMOS technologies which have been developed to enable the realization of integrated mixed-signal systems-on-a-chip (SoC). These BiCMOS technologies provide several types of SiGe:C HBTs with parameters or features tailored to specific applications, combined with a 0.25 mm CMOS core and a variety of passive elements. We will primarily focus on the fabrication and parameters of the SiGe:C HBT modules, but also give an overview of the further BiCMOS devices. In Section 11.2, the history of IHP’s SiGe and SiGe:C HBT technologies is briefly summarized. The following sections (Sections 11.3 to 11.6) provide a detailed description of the SiGe:C BiCMOS processes presently available at IHP. These processes reflect two different approaches of HBT module development. The first one aims at highest HBT performance for applications such as optical fiber communications with transmission speeds of higher than 40 Gb/sec, very high data rate wireless links in the 60 GHz ISM band, or automotive radar at 77 GHz and beyond. The high-performance HBT modules developed for these applications are described in Section 11.3. They offer peak fT and fmax values of up to 200 and 11-1

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245 GHz, respectively, and ring oscillator delay times down to 3.6 ps, the lowest value obtained so far in a BiCMOS process. Section 11.4 deals with a promising process extension, the common integration of high-speed npn and pnp SiGe:C HBTs in a complementary BiCMOS process. The pnp transistors described show cutoff frequencies which are by a factor of 2 higher than ever-published for a Si-based pnp device. The second approach of IHP’s BiCMOS development aims at cost-sensitive applications, which, however, do not need highest HBT performance. A process, which particularly fulfills the lowcost requirement, is described in Section 11.5. In this process, only one mask step is added to the underlying RF CMOS flow to fabricate simultaneously three types of SiGe:C HBTs with BVCEO/fT values ranging from 2.4 V/80 GHz to 7 V/30 GHz. Finally, Section 11.6 deals with fabricated circuits. Both inhouse designers but also many partners and customers from other institutes, companies, or universities made use of industry-standard design kits and took benefit from prototyping and shuttle services offered by IHP for its SiGe:C BiCMOS processes. Here, we focus on some recent results obtained with IHP’s high-performance HBT modules.

11.2

History of IHP’s SiGe and SiGe:C HBT Technologies

IHP’s activities in the field of SiGe-based device technology began more than 10 years ago with the fabrication of simple double-mesa HBTs with SiGe base layers deposited by MBE or APCVD. These transistors were primarily used to study the particular device properties of HBTs and to learn how these properties can be affected. In the following time, the HBT fabrication process has been continuously improved, also including a change in the SiGe layer deposition process from MBE and APCVD to RTCVD [1]. IHP’s most advanced SiGe HBT technology was a 14-mask RF bipolar process offering three levels of Al and a suite of passive elements [2]. The SiGe HBTs fabricated in this process showed, at 2.7 V BVCEO, peak fT and fmax values of 45 and 60 GHz, respectively, i.e., an RF performance similar to that of IBM’s first generation of SiGe BiCMOS devices [3]. This performance, however, was reached with a much simpler HBT technology that did neither use an epitaxially buried subcollector (EBC), nor deep trench isolation (DTI), nor a self-aligned emitter–base structure. Instead, IHP’s SiGe transistors were fabricated as single-polysilicon transistors with collector wells produced by high-energy P implantation following LOCOS formation. The good RF performance of these devices resulted primarily from a special device construction featuring a minimized spacing between collector contact and internal transistor regions (Figure 11.1a). This construction allowed one to reach the low collector resistances necessary for high RF performance, despite the high sheet resistivity of the implanted wells. Moreover, the HBTs took benefit from a progressive SiGe layer structure featuring a half-graded, less than 30-nm

(b)

Salicided collector link

Field oxide Ch. stop

Extr. base implant

SiGe

20

(a)

Polysilicon emitter

Collector well

p-Substrate

[Ge] (%)

Pt silicide

16 12 8 4 0 60 80 100 Depth (nm)

FIGURE 11.1 HBT construction (a) and Ge profile (b) (extracted from x-ray measurement), as used in IHP’s first SiGe HBT technology. (From D Knoll, B Heinemann, R Barth, K Blum, J Drews, A Wolff, P Schley, D Bolze, B Tillack, G Kissinger, W Winkler, and H J Osten. Proceedings of the European Solid-State Device Research Conference, Bordeaux, 1998, pp. 140–143. With permission.)

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11-3

thick Ge profile (Figure 11.1b). The Ge profiles used in newer IHP technologies, including the current, most advanced ones, exhibit only minor differences compared to this profile. The primary reason for choosing a relatively simple HBT technology was the aimed modular HBT integration in a state-of-the-art CMOS platform. That seemed to be, at this time, the best way to bring HBTs in the mainstream because allowing the combination of the high RF performance of HBTs with the VLSI capability of digital CMOS. For such a modular HBT integration, we considered single-polysilicon transistors with implanted, epi-free collectors as the most attractive candidates because they can be simply integrated, without altering the CMOS process or process flow, or disturbing the CMOS device characteristics. In the middle of the 1990s, IHP’s material research group began to investigate the properties of C-doped Si and SiGe layers. After learning that even the incorporation of relative low concentrations of C (typically 51019 to 11020 cm3) can significantly suppress B diffusion in these layers, technology development was focused more and more on HBTs with C-doped SiGe layers, leading to some pioneer results in this field: In 1997, the first SiGe:C transistors with competitive DC and RF parameters were presented [4,5]. These transistors used MBE-grown SiGe:C base layers. After transferring C-doped Si and SiGe epi-layer deposition to an RTCVD tool, it was shown in detail that C incorporation has no negative effect on ‘impurity-sensitive’ device properties such as leakage currents and yield, low-frequency noise, or base recombination [6,7]. In 1999, the first SiGe:C BiCMOS process was also presented by IHP [8]. The new SiGe:C HBTs resembled IHP’s C-free SiGe transistors in many features, such as the implanted wells, the LOCOS-based device isolation, the special collector construction, and the singlepolysilicon structure. Besides the C incorporation, they differed from the C-free HBTs primarily in the much higher base B doping, lowering the internal base sheet resistance (RSBi) by more than a factor of 2. Moreover, the low-doped collector (LDC) and emitter (LDE) regions of the SiGe:C HBTs were selectively doped after depositing the SiGe base and a Si cap layer by implantations directly through the emitter window. The SiGe:C devices in IHP’s first BiCMOS process showed peak fT and fmax values of 55 and 90 GHz, respectively, with 3.3 V BVCEO [8], i.e., both the (BVCEO fT) product and fmax increased by about 50%, in comparison to the C-free transistors presented in Ref. [2]. Clearly, the SiGe:C HBTs took benefit from the C incorporation which effectively suppresses B out-diffusion from a highly doped SiGe layer even under the strong TED impact of the high-dose implant used for doping the external base regions, and the low-dose implants applied for selectively doping the LDE and LDC regions [4,9]. The reduced B diffusivity in Si:C and SiGe:C layers proved also to be advantageous with respect to a modular BiCMOS process integration. In IHP’s first SiGe:C BiCMOS process, the HBT module was inserted in the CMOS process flow before implantation of the PMOS S/D regions. In this way, the base epitaxy, which needs a high temperature H2-prebake, was prevented from influencing the PMOS parameters. However, the underlying CMOS process did not use a separately implanted drain extension for the PMOS, and a strong RTA had to be applied to drive in the PMOS S/D implant. This anneal was about 708C higher than the RTA of the pure SiGe:C bipolar process [6]. Nevertheless, it could be applied in the BiCMOS flow without degrading the HBT DC and RF characteristics.

11.3

High-Performance SiGe:C BiCMOS Processes

85 GHz SiGe:C BiCMOS (SGC25A) In 2000, a 0.25-mm digital CMOS process of an industrial partner was licensed and transferred to IHP’s new cleanroom, which had been completed and equipped some months before. This CMOS process was used as platform for the development of IHP’s second SiGe:C BiCMOS generation. In September 2001, the development was completed with an industry-standard qualification. The new process, called SGC25A, has been running since then as IHP’s BiCMOS ‘work-horse.’ It uses 25 mask steps to fabricate two types of SiGe:C HBTs, in combination with a triple-well, 2.5 V CMOS core. Among the passives are a varactor, polysilicon resistors, and an MIM capacitor. four layers of Al are available, including a 2 mm thick top layer. Table 11.1 summarizes the device menu offered by the SGC25A process. Figure 11.2

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Fabrication of SiGe HBT BiCMOS Technology SGC25A HBT Parameters and MOS and Passives Parameters of the SGC Process Family

Device

Parameter

Value

Unit

Remark

2

SGC25A HBT Parameters (AE ¼ 0.42 0.84 mm ) Current gain BVEBO

150 >3

V

@ VBE ¼ 0.7 V @ IEB ¼ 1 mA

HBT1

Peak fT / fmax BVCEO BVCBO

60 / 90 3.2 >8

GHz V V

@ VCE ¼ 1.5 V Extrapolateda @ ICB ¼ 0.1 mA

HBT2

Peak fT / fmax BVCEO BVCBO

85 / 100 2.5 >5

GHz V V

@ VCE ¼ 1.5 V Extrapolateda @ ICB ¼ 0.1 mA

HBTs 1 and 2

MOS and Passives Parameters of IHP’s SGC Process Family NMOS and Isolated NMOS

Saturation current Off current Threshold voltage Effective channel length

540 0.4 0.60 0.24

mA/mm pA/mm V mm

@ VDS ¼ 2.5 V

PMOS

Saturation current Off current Threshold voltage Effective channel length

230 0.5 0.56 0.245

mA/mm pA/mm V mm

@ VDS ¼ 2.5 V

MOS Varactor

Tuning ratio Q factor (@ low/high C)

1:3.4 120/30

Salicide Resistor

Sheet resistance Temperature coefficient

6.6 2900

Vsq ppm/8C

Silicided gate poly

Poly-Si Resistor

Sheet resistance Temperature coefficient

95 450

Vsq ppm/8C

Gate poly (nþ)

Poly-Si Resistor

Sheet resistance Temperature coefficient

350 50

Vsq ppm/8C

HBT base poly

MIM Capacitor

Unit capacitance Voltage coefficient Voltage coefficient Temperature coefficient Breakdown voltage Max. application voltage

1 14 1.6 <10 >30 10

fF/mm2 ppm/V ppm/V2 ppm/8C V V

Quality factors (examples)

4 16

Predefined Inductors

2.5 V
10 V
a

Extrapolation from the IC/AE ¼ (0.3–0.75)mA/mm2 part of the VCE(IC) characteristics.

shows the flow and essential features of the process. The HBT module is integrated after structuring the MOS gates and forming the gate spacers, i.e., in a similar way as described in Refs. [8,10]. It adds four mask steps (M8–M11) to the underlying RF CMOS baseline and produces a first HBT type featuring 3.2 V BVCEO, and peak fT and fmax values of 60 and 90 GHz, respectively. A fifth additional mask (M4) is used to provide the second HBT type, which combines 2.5 V BVCEO with 85 GHz peak fT and 100 GHz peak fmax. Cross sections of both HBT types are shown in Figure 11.3. Note that the SGC25A-HBTs are also fabricated, as IHP’s former devices, with epi-free, implanted wells, and a nonself-aligned emitter– base structure. However, shallow trench isolation was introduced, and higher implantation energies were available. It allowed us to replace our previously used collector construction (Figure 11.1a) by a more conventional, planar one. Figure 11.4 shows a trend chart of HBT leakage currents demonstrating the high level of SGC25A process maturity.

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Industry Examples at the State-of-the-Art: IHP

SGC25A PROCESS FLOW

Shallow trench etch (M1) and fill (M2) Deep n-well implantation (M3), RTA Opening HBT regions + High dose collector implant (M4) MOS well implantations (M5, M6), RTA Gate oxidation, Gate poly deposition Gate etch (M7), Spacer formation

S/D implantations (M12, M13), RTA Salblock (M14), Co salicide formation LI (15), Contact (M16), Met-1 (M17) Via-1 (M18), MIM (M19), Met-2 (M20) Via-2 (M21), Met-3 (M22) Via-3 (M23), Met-4 (M24) Passivation (M25)

FIGURE 11.2

• • • •

25 mask steps Shallow trench isolation Triple well option (by deep n-well) 5 nm gate oxide

HBT MODULES (M4), (M8) − (M11) Deposition of CMOS protection layers (M8): Opening active collector regions + Medium dose collector implant + RTA Non-selective Si/ SiGe:C/ Si epitaxy (M9): Opening emitter windows + SIC As doped emitter deposition (M10): Structuring polysilicon emitters + External base implant (M11): External base structuring Removing protection layers by wet etch • • • • •

Co salicide Local interconnect (LI) CMP planarization and W plugs 4 Al layers (w/2 µm thick top metal) 2.5 V supply voltage

Flow and features of the SGC25A process.

Poly SiGe:C/Si

STI

Polysilicon emitter

HBT1 (a)

SIC SiGe:C

Coll. Well (M8)

Deep n-well (M3)

CMOS protection layer

n+ S/D n-Well

HBT2 (b)

SIC Extr. base Coll. Well (M8)

n+ S/D

High dose collector implant (M4)

FIGURE 11.3 Schematic cross sections of the SGC25A HBTs. HBT1 shows 3.2 V BVCEO and 60 GHz fT, while HBT2 combines 2.5 V BVCEO with 85 GHz fT.

The processes SGC25B and SGC25C, described below, are derivatives from SGC25A. They offer a strongly improved HBT performance, while RF CMOS baseline including BEOL, and hence CMOS libraries and passive elements are identical to SGC25A.

120 GHz SiGe:C BiCMOS (SGC25B) [11,12] SGC25B uses the same HBT integration scheme (Figure 11.2) and the same basic HBT construction as SGC25A (Figure 11.3b). To get a higher HBT performance than offered by SGC25A, the conditions for the high-dose collector implantation were optimized and the SIC implantation dose was increased.

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Fabrication of SiGe HBT BiCMOS Technology

AE = 4096⫻(0.42⫻0.84)µm2 log (Ic(A))

−4 −6

IC @VBE = 0.1 V; VCB=1 V

−8

Good device: log IC < −11 Total yield: 92.2%

−10 −12 0

FIGURE 11.4

2000

4000 6000 Measuring point

8000

SGC25A trend chart of leakage currents for 4k HBT arrays. 980 wafers from 97 lots were measured.

TABLE 11.2

SGC25B HBT Parameters

Parameter

Value

Unit

Remark

SGC25B HBT Parameters (AE ¼ 0.420.84 mm2) Current gain Peak fT Peak fmax Min. RO delay time BVEBO BVCEO BVCBO Early voltage B–E capacitance B–C capacitance C–S capacitance Emitter resistance Collector resistance Base resistance a

150 120 140 5.9 >2.5 2.3 >4 >40 6.8 4.5 5.6 23 51 150

GHz GHz ps V V V V fF fF fF V V V

@ VBE ¼ 0.7 V @ VCE ¼ 1.5 V CML, 53 stages @ IEB ¼ 1 mA Extrapolateda @ ICB ¼ 0.1 mA IB ¼ const.b @ VBE ¼ 0 V @ VCB ¼ 0 V @ VCS ¼ 0 V

Circle fit of s11 @ VBE ¼ 0.9 V

2

Extrapolated from the IC/AE ¼ (0.3–0.75) mA/mm part of the VCE(IC) characteristics. IB ¼ const. ¼ IB(VBE ¼ 0.7 V; VCB ¼ 0 V); VCE ¼ (0.9 + 0.2) V.

b

Moreover, we reduced some transistor dimensions, such as the active enclosure of the emitter, the overlap of the polysilicon emitter to the emitter window, and the LDE width. Note that the changed SIC conditions are responsible that only one transistor type is available in SGC25B. The parameters of this HBT type are listed in Table 11.2, featuring 120 GHz peak fT, 140 GHz peak fmax, and a CML ring oscillator delay time of 5.9 psec.

200 GHz SiGe:C BiCMOS (SGC25C) [13,14] SGC25C is IHP’s first BiCMOS process which offers bipolar transistors with 200 GHz cutoff frequencies to the design community. Two HBT variants were tested which differ in the emitter–base structure, as shown in Figure 11.5. Figure 11.6 illustrates both the full SGB25C process flow and the detailed flows for the different HBT modules. The standard HBT variant uses the same single-polysilicon construction as applied in SGC25A/B, featuring an implanted extrinsic base layer (Figure 11.5a). This layer is formed on isolator regions during the nonselective epi-process applied to grow the intrinsic SiGe:C base layer and a Si cap. The implantation step for doping the extrinsic base layer is carried out self-aligned to the outer

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Industry Examples at the State-of-the-Art: IHP

(a)

Emitter

Implanted extrinsic base

Collector contact

STI

(b)

Heavily doped collector

STI

Emitter

Elevated extrinsic base

Collector contact

STI

Heavily doped collector

STI

FIGURE 11.5 Schematic cross sections of the SGC25C standard HBT with implanted extrinsic base (a) and an HBT with elevated extrinsic base (b). (From H Ru¨cker, B Heinemann, R Barth, D Bolze, J Drews, U Haak, W Ho¨ppner, D Knoll, K Ko¨pke, S Marschmeyer, H H Richter, P Schley, D Schmidt, R F Scholz, B Tillack, W Winkler, H E Wulf, and Y Yamamoto. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 121–124. With permission.)

SGC25C PROCESS FLOW

Shallow trench etch (M1) and fill (M2) Deep n-well implantation (M3), RTA MOS well implantations (M4, M5), RTA Gate oxidation, Gate poly deposition Gate etch (M6), Spacer formation

S/D implantations (M12, M13), RTA Salblock (M14), Co salicide formation LI (15), Contact (M16), Met-1 (M17) Via-1 (M18), MIM (M19), Met-2 (M20) Via-2 (M21), Met-3 (M22) Via-3 (M23), Met-4 (M24) Passivation (M25)

ELEVATED EXTRINSIC BASE FORMATION

HBT MODULE (M7) - (M11) Deposition of CMOS protection layers (M7): Opening HBT regions + High dose collector implant + RTA Oxide deposition (M8): Opening active collector regions Si / SiGe:C / Si epitaxy (M9): Opening emitter windows + SIC As doped emitter deposition (M10): Structuring polysilicon emitters + External base implant (M11): External base structuring Removing protection layers by wet etch

Selective Si epitaxy followed by non-selective HBT base + LDE epitaxy

Sacrificial layer deposition (M9): Opening emitter windows + SIC Forming inside spacers Forming outside spacers + Wet etch sacrificial layer + Selective growth of the B-doped extrinsic base

As doped emitter deposition (M10): Structuring polysilicon emitters (M11): External base structuring Removing protection layers by wet etch

FIGURE 11.6 Flow of the SGC25C process with standard HBT module (implanted extrinsic base). The process flow for HBTs with elevated extrinsic base is shown below.

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Fabrication of SiGe HBT BiCMOS Technology

edge of the polysilicon emitter, but not self-aligned to the emitter window. In contrast, the second process variant fabricates transistors with a self-alignment between extrinsic base and emitter window to minimize base resistance (Figure 11.5b). This self-alignment is achieved by selectively growing a highly B-doped, elevated extrinsic base layer after structuring the polysilicon emitter. Sacrificial and protection layer depositions as well as spacer processes are applied before, to make possible that this layer growth also occurs in the space between polysilicon emitter and that extrinsic base layer grown already during the nonselective epi-process for base and Si cap formation. Both SGC25C transistor variants reach 200 GHz fT, whereas the HBTs with elevated extrinsic base show fmax values of up to 245 GHz, which is about 50 GHz higher than reached with the implanted version. The strong fT gain, compared to SGC25B, results primarily from a novel collector design, which substantially reduces base–collector charging and transit times. Figure 11.6 shows that the SGC25C process flow differs from the SGC25A/B flow in the collector well fabrication. The HBT high-dose collector implantation is now carried out after the gate module. Moreover, conditions for this implantation step were found providing simultaneously a low sheet resistance and a junction depth, which is low enough that the lateral spreading of the highly doped collector wells is confined by the STI side walls. The key new SGC25C device features are the formation of the whole HBT structure in one active area without STI stripe between emitter and collector contacts, the complete lateral enclosure of the highly doped collector wells in the STI side walls, and the self-alignment of the collector contact region to the base poly edge (Figure 11.5). This allows us to achieve collector resistances, which are even lower than the emitter resistance. In addition, the new design reduces device dimensions and parasitic capacitances. So, the reduced collector area results in a 50% reduction in the collector– substrate capacitance compared to the SGB25B transistors. Furthermore, since the collector well fabrication is implemented after the critical thermal treatments, this device design allows us to produce extremely steep collector doping profiles and achieves better control of the width of the base–collector space charge regions. Finally, the absence of DTI improves the heat dissipation and reduces the thermal resistance. In addition to the introduction of a new collector design we also optimized the base–collector as well as the emitter–base depletion widths by adjusting the buffer and cap thicknesses of the epi-layer stack in order to maximize fT. Figure 11.7 compares the fT vs. IC curves of SGC25B and SGC25C HBTs and illustrates, by a comparison of transit time components, from what the SGC25C performance gain results in detail. Table 11.3 summarizes the parameters of the SGC25C HBTs. The standard devices, with implanted extrinsic base, show 200 GHz fT, about 185 GHz fmax, and a minimum CML ring oscillator delay of 4.3 ps. The devices with elevated extrinsic base reach fmax values in excess of 240 GHz and a ring oscillator delay of 3.6 ps (Figure 11.8), which is, to our knowledge, the lowest value reached so far in a BiCMOS process.

150 100

VCE = 1.5 V SGC25C

SGC25B

50 AE = 2⫻(0.21⫻0.84) µm2 0.01

0.1 1 Collector current (mA)

10

Transit time (psec)

Transit frequency (GHz)

1.4 200

1.2

(CBC+CBE)kT/qIC

1.0

CBC(RE+RC)

0.8 0.6 wBC /2vsat

0.4 0.2

tE+tB

0.0 SGC25B

SGC25C

FIGURE 11.7 Transit frequency vs. collector current for SGC25B and SGC25C HBTs, and comparison of the transit time components of these transistors.

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Industry Examples at the State-of-the-Art: IHP TABLE 11.3

SGC25C HBT Parameters

Parameter Emitter dimensions Current gain Peak fT Peak fmax Min. RO delay time BVEBO BVCEO BVCBO Early voltage B–E capacitance B–C capacitance C–S capacitance Emitter resistance Collector resistance Base resistance

Selectively Grown Elevated Extrinsic Base

Standard: Implanted Extrinsic Base

Value

Value

Value

0.1750.84 300 190 243 3.6 >1.5 1.9 5.1 >40 n.m. 2.4 n.m. 22 21 75

0.210.84 300 200 225 11 >1.5 1.9 5.0 >40 3.8 2.8 3.0 18 16 85

a

Unit

0.210.84 300 202 186 4.3 >1.5 >1.85 4.5 >40 3.8 3.3 3.0 19 16 110

2

mm

GHz GHz ps V V V V fF fF fF V V V

Remark Drawn dimensions @ VBE ¼ 0.7 V @ VCE ¼ 1.5 V CML, 53 stages @ IEB ¼ 1 mA Extrapolateda @ ICB ¼ 0.1 mA IB ¼ const.b @ VEB ¼ 0 V @ VCB ¼ 0 V @ VCS ¼ 0 V

Circle fit of s11 @ VBE ¼ 0.9 V

2

Extrapolated from the IC/AE ¼ (0.3–0.75) mA/mm part of the VCE(IC) characteristics. IB ¼ const. ¼ IB(VBE ¼ 0.7 V; VCB ¼ 0 V); VCE ¼ (0.9 + 0.2)V.

b

7 Gate delay time (ps)

T = 300 K 6

AE = 0.21⫻0.84

5

µm2

∆V = 300 mV VEE = −2.5 V

Impl. extr. base

4 AE = 0.175⫻0.84 µm

2 Elevated extr. base

3 1

10 Current per gate (mA)

FIGURE 11.8 CML ring oscillator gate delay vs. current per gate for oscillators with 53 stages. Devices with elevated extrinsic base and different emitter dimensions are compared with the standard SGC25C HBTs (with implanted extrinsic base). (From H Ru¨cker, B Heinemann, R Barth, D Bolze, J Drews, U Haak, W Ho¨ppner, D Knoll, K Ko¨pke, S Marschmeyer, H H Richter, P Schley, D Schmidt, R F Scholz, B Tillack, W Winkler, H E Wulf, and Y Yamamoto. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 121–124. With permission.)

11.4 High-Speed, Complementary SiGe:C HBTs in a BiCMOS Technology The availability of both npn- and pnp-type bipolar transistors with matched performance in a complementary BiCMOS process (CBiCMOS) is a promising route to applications simultaneously requiring low voltage, low power, and high speed. IHP has developed a high-speed CBiCMOS process with bipolar parameters summarized in Table 11.4 [15]. This process offers pnp SiGe:C HBTs with peak fT/fmax values of 80 GHz/120 GHz (Figure 11.9) at 2.6 V BVCEO and a CML ring oscillator delay of 8.9 psec (Table 11.4). The simultaneously fabricated npn SiGe:C HBTs show fT/fmax values of 180 GHz/185 GHz, i.e., a

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Fabrication of SiGe HBT BiCMOS Technology TABLE 11.4

CBiCMOS HBT Parameters (AE ¼ 0.21 0.84 mm2) npn

pnp

Parameter

Value

Value

Unit

Current gain Peak fT Peak fmax Min. RO delay time BVEBO BVCEO BVCES Early voltage B–E capacitance B–C capacitance C–S capacitance Emitter resistance Collector resistance Base resistance

160 180 185 4.6 >1.5 2.0 5.0 150 4.5 3.6 3.0 19 16 123

180 80 120 8.9 >2.5 2.6 5.5 40 5.3 3.0 4.0 22 50 147

GHz GHz ps V V V V fF fF fF V V V

Remark @ VBE ¼ 0.7 V @ VCE ¼ 1.5 V CML, 53 stages @ IEB ¼ 1 mA @ 10 mA @ 10 mA @ VBE ¼ 0.7 V @ VEB ¼ 0 V @ VCB ¼ 0 V @ VCS ¼ 0 V

Circle fit of s11 @ VBE ¼ 0.9 V

Source: B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R F Scholz, W Winkler, and Y Yamamoto. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120.

fT or fmax (GHz)

200 150

A E = 2⫻ (0.21⫻0.84) µm2

npn

VCE = 1.5 V pnp-only

100

fmax pnp

50 fT 0

10−4

10−3 Collector current (A)

10−2

FIGURE 11.9 Transit frequency (fT) and maximum oscillation frequency (fmax) vs. collector current for pnp and npn HBTs fabricated on the same wafer in the CBiCMOS and for pnp devices from a pnp-only BiCMOS. (From B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R F Scholz, W Winkler, and Y Yamamoto. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117– 120. With permission.)

performance almost as high as that of the SGC25C process, despite a changed emitter construction and the additional thermal budget within the CBiCMOS process. A pnp-only, reference BiCMOS flow even produced peak fT/fmax values for the pnp devices of 115 GHz/115 GHz (Figure 11.9). This pnp RF performance of CBiCMOS and pnp-only BiCMOS surpasses the best reported values of this transistor type substantially. The strong performance gain of the pnp HBTs is mainly due to a highly tuned vertical doping profile, taking full advantage of the reduced P diffusion in the C-doped base [16] combined with the special collector construction of IHP’s 200 GHz npn transistors. This construction allows one to integrate an isolated pnp into a CMOS process easily, while simultaneously minimizing collector resistance and capacitance. CBiCMOS process flow and transistor cross sections are shown in Figure 11.10 and Figure 11.11. The RF CMOS baseline is the same as used for the SGC (npn-only) process family. Up to the npn base layer

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Industry Examples at the State-of-the-Art: IHP

CBiCMOS PROCESS FLOW

Gate etch (M6), Spacer formation BIPOLAR (NPN+PNP) MODULE (M7)-(M16) Deposition of CMOS protection layers (M7): Opening npn regions+ High dose npn collector implant + RTA Oxide deposition (M8): Opening active npn coll. regions npn base epitaxy

NPN

PNP

(M9): Opening pnp regions + High dose pnp collector implant + n-isolation implant + RTA Oxide deposition (M10): Opening active pnp coll. regions pnp base epitaxy (M11): Structuring pnp emitter window etch stop layer + base link implant

(M12): Opening npn em. window + SIC As doped npn emitter deposition (M13): Opening pnp em. window + SIC B doped pnp emitter deposition (M14): Structuring pnp poly emitters (M15): Structuring npn emitter + pnp base poly (M16): Implantation of npn base and pnp collector contacts Removing CMOS protection layers by wet etch S/D implantations (M17, M18) ... Passivation (M30)

FIGURE 11.10

Base

Flow of the complementary BiCMOS process.

Emitter

Collector

Base

Emitter

Collector

npn Emitter Poly pnp Base Poly SIC

n+ S/D

High doped collector

SIC

p+

n+ S/D

High doped collector

n-Isolation

n well

FIGURE 11.11 Schematic cross section of the npn HBT structure (left) and the pnp HBT structure (right) of the complementary BiCMOS process. (From B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R F Scholz, W Winkler, and Y Yamamoto. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. With permission.)

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epitaxy the process flow is identical to SGC25C. Then, the collector regions of the pnp transistors are formed in analogy with the npn flow. In addition to the collector well implant, a high-energy implantation is applied for the vertical isolation of the pnp. The pnp epitaxy stack consists of a Si buffer layer, the P-doped SiGe:C layer (30 nm thick), delivering a pinched sheet resistance of about 10 kV/sq, and a Si cap layer. A total of ten mask steps are used for the complementary bipolar module, five for the pnp and four for the npn, and one common mask step for structuring npn emitter poly and pnp base poly. The demonstrated RF performance, the high early voltages (Table 11.4) and further results, such as the only weak sensitivity of b and peak fT to the collector bias [15], indicate that valence band barrier effects, a serious problem of pnp HBTs, are largely suppressed before onset of the Kirk effect by a careful profile design at the base–collector junction. A major concern with such heavily doped, rapidly annealed devices, as produced in SGC25C and CBiCMOS is the defect density. The Gummel plots of both npn and pnp 4k HBT arrays, shown in Figure 11.12, prove that this problem has been successfully solved for both HBT types.

11.5 Low-Cost SiGe:C BiCMOS Process with a One-Mask HBT Module (SGB25V) The majority of current BiCMOS applications, in particular in the wireless area, have more modest speed requirements, typically below 100 GHz, but are highly cost-sensitive. Therefore, IHP has developed, in addition to the technologies with high-performance HBTs, a very simple, flexible, and hence low-cost SiGe:C BiCMOS process with ample performance for the majority of high-volume applications. The technology, called SGB25V, is a 0.25 mm BiCMOS SiGe:C HBT process with only 19 lithographic steps, offering four levels of Al and a full menu of active and passive devices (Table 11.5). Three different SiGe:C HBTs can be fabricated simultaneously by adding a single lithography level to the underlying RF CMOS process. These devices offer BVCEO/fT values ranging from 2.4 V/80 GHz to 7 V/30 GHz. The further device menu includes 2.5 V VDD MOS transistors for digital applications, an isolated NMOS device, an accumulation type MOS varactor, a junction varactor, three polysilicon resistors with sheet resistances ranging from 6 V/sq. to 2 kV/sq., a 2-mm thick upper Al layer for high-Q inductor fabrication, and a 1 fF/mm2 MIM.

10−1

10−1

10−2 Base, collector current (A)

npn

pnp

10−2

5 arrays AE = 4096⫻ (0.21⫻0.84) µm2

10−3 10−4 10−5

10−3 10−4 10−5

10−6

10−6

10−7

10−7

10−8

VCB = 0 V

10−8

10−9

T = 300 K

10−9

10−10

−0.8

−0.6

−0.4 0.4 0.6 Base−emitter voltage (V)

10−10 0.8

FIGURE 11.12 Gummel plots of pnp and npn HBT arrays fabricated in the CBiCMOS flow. (From B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R F Scholz, W Winkler, and Y Yamamoto. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. With permission.)

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SGB25V HBT, MOS, and Passives Parameters

Device

Parameter

Value

Unit

Remark

2

SGB25V HBT parameters (AE ¼ 0.5 0.9 mm ) Current gain BVEBO

190 >3

V

@ VBE ¼ 0.7 V @ IEB ¼ 1 mA

npn-H

Peak fT/fmax BVCEO BVCES

30 / 70 7 >20

GHz V V

@ VCE ¼ 2 V Extrapolateda @ 0.1 mA

npn-S

Peak fT/fmax BVCEO BVCES

50 / 95 4.0 16

GHz V V

@ VCE ¼ 2 V Extrapolateda @ 0.1 mA

npn-P

Peak fT/fmax BVCEO BVCES

80 / 95 2.4 7.7

GHz V V

@ VCE ¼ 2 V Extrapolateda @ 0.1 mA

npn-H,S,P

SGB25V MOS and Passives Parameters NMOS and Isolated NMOS

Saturation current Off current Threshold voltage Effective channel length

570 3 0.61 0.22

mA/mm pA/mm V mm

@ VDS ¼ 2.5 V

PMOS

Saturation current Off current Threshold voltage Effective channel length

290 3 0.51 0.185

mA/mm pA/mm V mm

@ VDS ¼ 2.5V

MOS Varactor

Identical to SGC processes

pþn Varactor

Tuning ratio Q factors (@ low/high C)

1.7:1 35 / 20

Salicide Resistor

Sheet resistance Temperature coefficient

6.8 2950

V/sq. ppm/K

Silicided gate poly

Poly-Si Resistor

Sheet resistance Temperature coefficient Temperature coefficient

310 105 0.64

V/sq ppm/K ppm/K2

Gate poly (pþ) 408C to 1258C

Poly-Si Resistor

Sheet resistance Temperature coefficient Temperature coefficient

2000 2760 6.1

V/sq ppm/K ppm/K2

Low-doped gate poly

MIM Capacitor Inductors

Identical to SGC processes Identical to SGC processes

@ 5 GHz

408C to 1258C

a

Extrapolated from the IC/AE ¼ (0.3–0.75) mA/mm2 part of the VCE(IC) characteristics.

The CMOS backbone of SGB25V differs from that CMOS baseline used for the SGC25 processes and for a SGB25V pre-production version [17]. The process changes allowed us to release MOS devices with lower leff, and led to a strong yield increase for dense CMOS sections, which use the shorter devices. Moreover, a set of polysilicon resistors is now available, providing a wider range of sheet resistance values compared to the SGC process family. The SGB25V process flow is shown in Figure 11.13. HBT fabrication starts after depositing the MOS gates and a Si3N4 protection layer. The single HBT mask is used to remove by RIE the nitride film and the gate material from the HBT regions, and to carry out a chain of P implants. After wet etching the gate oxide, the SiGe:C base and a Si LDE layer are successively grown. L-shaped inside spacers are formed, a SIC implantation is carried out, and an As-doped emitter Si layer is deposited. Then, emitter and base

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SGB25V PROCESS FLOW

Shallow trench etch (M1) and fill Deep n-well implantation (M2), RTA MOS well implantations (M3, M4), RTA Gate oxidation, Gate poly deposition

Gate etch (M6), Spacer formation S/D implantations (M7, M8), RTA Salblock(M9), Co salicide formation Contact (M10), Met-1 (M11) Via-1 (M12), MIM (M13), Met-2 (M14) Via-2 (M15), Met-3 (M16) Via-3 (M17), Met-4 (M18) Passivation (M19)

FIGURE 11.13

• • • •

19 mask steps Shallow trench isolation Triple well option (by deep n-well) 5 nm gate oxide HBT MODULE (M5)

Nitride layer for CMOS protection (M5): Opening active collector regions + Low dose collector implants Non-selectiveSi/ SiGe:C/ Si epitaxy Forming oxide inside spacers + SIC As doped emitter deposition CMP (Si, SiGe) with stop on nitride Removing nitride layer by wet etch • • • •

Co salicide CMP planarization and W plugs 4 Al layers (w/2 µm thick top metal) 2.5 V supply voltage

Flow and features of the SGB25V process.

material are removed by CMP from the Si3N4 layer surface to isolate the emitter from the extrinsic base. After wet etching the nitride film from the gate stack, CMOS device fabrication is continued. The gate structuring process and the PMOS S/D implants are also used to form and dope the HBT extrinsic base regions, respectively. Note that using gate-poly as material for the HBT extrinsic base is not the only advantage of the special HBT integration scheme applied here. It also minimizes the impact of the HBT thermal steps on the MOS characteristics. However, we would not have been able to take advantage of these without doping the HBTs with C. This prevents B out-diffusion from SiGe, and thus HBT parameter degradation, by CMOS thermal steps such as poly-reoxidation and S/D RTA, which are carried out after HBT integration. Figure 11.14 shows fT vs. collector current curves for the HBTs simultaneously fabricated in SGB25V. The differences in the fT and BVCEO values are produced by varying the layout for the deep P implant for the CMOS triple-well option, and using the PMOS well implants (Figure 11.15). The SGB25V HBT yield (estimated for 4k device arrays) exceeds 90%, matching the numbers obtained with our other BiCMOS processes. VLSI ability of the process is controlled with an 1M SRAM as test vehicle. To study the impact of HBT integration on the yield of this 6-million transistor device, lots were fabricated with and without HBT module. Figure 11.16 demonstrates a typical SRAM yield of around 70% for both cases showing that the HBT integration scheme, used for SGB25V, is modular and has no negative impact on the yield of dense CMOS sections. Moreover, it shows that SGB25V guarantees high yield for VLSI CMOS segments necessary for a cost-effective fabrication of RF-SOCs.

11.6

Circuit Applications of IHP’s SiGe:C Technologies

IHP’s BiCMOS technologies, described in the previous sections, differ in the level of maturity. SGC25A, SGC25B, SGC25C (implanted HBT version), and SGB25V are fully developed and characterized processes which we were able to release for the access of both in-house and external designers. These processes are also offered as EUROPRACTICE platforms. In contrast, the SGC25C version with elevated extrinsic base as well as the CBiCMOS process have pre-production status. Therefore, the access to these processes is presently restricted to in-house designers and a few longtime partners. For IHP’s BiCMOS technologies design kits are available which support a Cadence mixed signal platform. For HBT characterization, the VBIC model is applied [18].

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Transit frequency (GHz)

80 70

npn-P

2.4V

60

VCE = 2 V

BVCEO

50 40

4.2 V

npn-S

30 20

npn-H

AE = 10⫻(0.5⫻0.9) µm2

7V

10 0.000

0.005

0.010

0.015

0.020

Collector current (A)

FIGURE 11.14 Transit frequency vs. collector current for the three HBT types fabricated in the SGB25V process (npn-P, npn-S, npn-H). The different curves for the same HBT type illustrate the typical scattering across a wafer.

Polysilicon emitter

Gate polysilicon npn-H n+ S/D

SIC

STI

n-Well Coll. well (M5) Poly SiGe:C/Si

Deep n-Well (M2)

SiGe:C base npn-S n+ S/D

SIC Coll. Well

n-Well

Deep n-Well Oxide spacer npn-P SIC Coll. Well

n+ S/D n-Well

Deep n-Well

FIGURE 11.15

Schematic cross sections of the three HBT types fabricated in the SGB25V process.

In the following section, we present some recent exemplary circuit results obtained with IHP’s highperformance BiCMOS processes because these technologies enable new product application areas. For demonstration, a series of benchmarking circuits were designed and tested successfully. The main results are summarized in Table 11.6. Intended applications are very high data rate wireless links in the 60 GHz ISM band and automotive radar at 77 GHz and beyond.

60 GHz Transceiver Circuits For demonstration of new wireless transmission systems with data rates >150 Mb/sec, key circuit blocks for a 60 GHz transceiver system were designed and fabricated [20,21]. The proposed transceiver is based

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SRAMs measured on 45 wafer sites

1M SRAM wafer yield (%)

100

BEC = 0 (@2.5 V) 80

60

40

A

B

C

D

E

F G

H

I

J

K

L

BiCMOS lots

CMOS 20

Lot ID (A − L)

FIGURE 11.16 Wafer yield of 1M SRAMs with a bit error count (BEC) of zero, fabricated in the SGB25V process (BiCMOS lots) or a flow without the SGB25V HBT module (CMOS lots).

TABLE 11.6 Measurement Results of Benchmarking Circuits Fabricated in IHP’s High-Performance BiCMOS Processes Circuit

Parameter

Value

Technology

Ref.

Static frequency divider, 1:2

Maximum input frequency

62 GHz

SGC25B

[19]

Dynamic frequency divider, 1:2

Maximum input frequency

72 GHz

SGC25B

[19]

Low power frequency divider, 1:64, 1 V supply

Maximum input frequency Suppply current

2.4 GHz 0.6 mA

SGC25B SGC25B

[19] [19]

60 GHz LNA

Gain @ 61 GHz

9.6 dB

SGC25C

[20]

LC oscillators

Oscillation frequency

24 GHz 60 GHz 76 GHz 97 GHz 117 GHz

SGC25B SGC25B SGC25B SGC25C SGC25C

[21–23]

Ring oscillators

Gate delay

3.6 ps

SGC25C

[14]

on amplitude shift keying (ASK) modulation principle. The reasons for the selection of this modulation technique are its simplicity, the wide bandwidth of the 61 GHz ISM band, and that there is no need for high-performance A/D converters. The transmit path of the transceiver consists of a 61.25 GHz fundamental mode oscillator, a switch, and a power amplifier. Between the modulator and the power amplifier a filter is inserted to reduce spurs. The receiver path consists of a three-stage, lownoise amplifier (LNA), a mixer, a 56 GHz oscillator, a variable gain amplifier, and an ASK demodulator. One task of the LNA design was to get unconditional stability for both on-wafer measurements and for the use of the amplifier in test board modules together with the other receiver components. Especially the use of bond wires for the connection of the ground potential (and the associated inductance) causes serious stability problems if a single-ended configuration is used. That is why all the stages are designed in differential configuration. The input and output are trafo-coupled. The transformer coupling is useful in two ways. First, it acts as a balun for connection to a singleended antenna. Second, the primary and secondary windings of the transformer are tuned to get a band pass characteristic. With this, an additional input filter in the RX path can be omitted and this function is integrated in the LNA. The single stage of the LNA is a differential stage with inductive load and with matching network at the output. The LNA was measured on wafer with a 110 GHz vector network analyzer. The maximum gain is 9.6 dB. The gain-maximum is reached at 61 GHz, which is

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exactly the target frequency of the requested ISM band (Figure 11.17). The LNA has a band pass characteristic, resulting from the tuned transformers at input and output. With this characteristic, no additional band pass filter is required.

Automotive Radar High-frequency oscillators are key components in modern low-cost radar systems for automotive and other sensor applications. Most of today’s automotive radar systems utilize the frequency bands at 24 and 77 GHz. For future developments, also higher frequency bands at 94 and 140 GHz are of interest. Reasons for the use of higher frequency bands are the further miniaturization of the radar systems and the better beam-forming prospects due to the shorter wavelength. Several LC oscillators for the different frequency ranges were designed and tested [21–23]. The circuit diagram of the oscillators is shown in Figure 11.18. The circuit is a common collector Colpitts oscillator in fully differential implementation. With the symmetric circuit, two advantages are reached: first, it gives reduced signal interference via the silicon substrate and, second, the coupling of the highfrequency energy to subsequent building blocks such as integrated amplifiers or mixers is more effective. 0 0 0 The tank is a symmetric circuit of two inductors L1 and L1 and the MIM capacitors C1, C2, C1 , and C2 . In parallel to the capacitor C1 acts the base–emitter capacitor of the bipolar transistor CBE. For explanation, the tank can be divided into two half circuits separated by the symmetry line shown in Figure 11.18. In operation, the oscillator-halves are working in the odd mode, such that the outputs are 1808 out of phase. The nodes of the tank, indicated by the symmetry line, have virtual ground. The oscillation frequency can then be estimated to a first order by the following equation: f ¼ 1=(2p

pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ L1 {2CBC þ [C2 (CBE þ C1 )=(C1 þ C2 þ CBE )]})

where CBC is the base–collector capacitance of the transistors.

Tank circuit Vctrl L1

L⬘1

C1

C⬘1

C2

Out

C2⬘

10 s21

Gain (dB)

0 −10

Symmetry line

−20 −30

s12

VEE

−40 −50 0

20

FIGURE 11.17

40 60 80 Frequency (GHz)

100

120

Gain curves of the 60 GHz LNA.

FIGURE 11.18 Circuit diagram of the high-frequency oscillator. (From W Winkler, J Borngra¨ber, and B Heinemann. Materials Science in Semiconductor Processing, Vol. 8, Numbers 1–3, February/June 2005, pp. 459–461. With permission.)

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The oscillators were characterized using an on-wafer test system with GS probes. For determination of the output spectrum a Rohde & Schwartz spectrum analyzer FSEM30 with a mixer unit FS-Z110 was used. The measurement results of three oscillators are summarized in Table 11.7. The supply voltage of these oscillators is 3 V or 4 V. The output power is from 7 dB m (oscillator 1) to 12 dB m per output channel (oscillator 3). The frequency of oscillation can be tuned by applying a tuning voltage at the Vctrl input. For oscillator 2, intended for 94 GHz, the tuning range is from 97.5 to 95.2 GHz for the control voltage changing from 2.4 V to 0. Because the target frequency was not met in this design, a redesign has 0 to be done. The capacitance of C2 and C2 will be reduced by a modest amount to shift the frequency to 94 GHz. Figure 11.19 shows the measured output spectrum of oscillator 3, which reaches the highest frequency. The tuning range is from 117.2 to 113.7 GHz. The current consumption is within the range of 10 to 28 mA. Of course, the output power will also undergo a change with varying the current flowing through the oscillator. The maximum measured output power is 12 dB m. Within the tunable frequency

TABLE 11.7 Measurement Results of Experimental LC Oscillators Fabricated in IHP’s High-Performance BiCMOS Processes Parameter

Oscillator 1

Oscillator 2

Oscillator 3

Oscillation frequency Supply voltage Supply current Center frequency Tuning range Output power Phase noise at 1 MHz offset Chip size

76 GHz 4.0 V 32 mA 76.1 GHz — 7 dB m 91 dBc/Hz 750400 mm2

97 GHz 3.0 V 15–37 mA 96.15 GHz 2.3 GHz 11.2 dB m 88 dBc/Hz 750400 mm2

117 GHz 3.0 V 10–28 mA 115.1 GHz 3.5 GHz 12 dB m — 750400 mm2

Ref L vl −5 dBm

Marker-12.24 dB m 114.92457381 GHz

−10 −20 −30 −40 −50 −60 −70 −80 Center 114.9312472 GHz

10 MHz/

Span 100MHz

FIGURE 11.19 Spectrum of single-ended output for oscillator 3. The center frequency is 114.3 GHz. (From W Winkler, J Borngra¨ber, and B Heinemann. Materials Science in Semiconductor Processing, Vol. 8, Numbers 1–3, February/June 2005, pp. 459–461. With permission.)

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range, the output power is above 20 dB m. The phase noise of oscillators 1 and 2 was measured by using a spectrum analyzer. The phase noise is 91 dB c/Hz and 88 dB c/Hz at 1 MHz offset, respectively.

11.7

Summary

We have described IHP’s modular SiGe:C RF BiCMOS technologies which provide several types of SiGe:C HBTs, combined with a 0.25 mm CMOS core and state-of-the art passive elements. Highperformance npn HBT modules with up to 200 GHz fT, a complementary HBT module with superior pnp performance, and a low-cost HBT module, providing simultaneously three HBT types, can be fabricated in IHP’s BiCMOS processes. This process menu ideally fulfills the technological requirements for the fabrication of modern fiber and wireless communication systems.

Acknowledgments The author would like to thank all IHP colleagues contributing to the HBT and BiCMOS work through the last years. Special thanks goes to B. Heinemann, K.-E. Ehwald, H. Ru¨cker, B. Tillack, and R. Barth who had the strongest impact in the field of process technology. P. Schley, Ha. Erzgra¨ber, and R. Scholz did great jobs in device measurement and characterization. I am also grateful to F. Fuernhammer and G. Grau (Advico) for the efforts to realize an adequate design environment for IHP’s technologies, and to W. Winkler who strongly supported all technology developments by providing suitable benchmark and verification circuits. Last but not least, the author thanks J. Osten who initiated SiGe:C material research at IHP, and A. Ourmazd for excellent management support and many valuable discussions.

References 1. G Ritter, B Tillack, and D Knoll. Successful preparation of high-frequency HBT by integrated RTCVD processes. MRS Symposium Proceedings, 1995, Vol. 387, Rapid Thermal and Integrated Processing IV, pp. 341–346. 2. D Knoll, B Heinemann, R Barth, K Blum, J Drews, A Wolff, P Schley, D Bolze, B Tillack, G Kissinger, W Winkler, and H J Osten. Low cost, 50 GHz fmax Si/SiGe heterojunction bipolar transistor technology with epi-free collector wells. Proceedings of the European Solid-State Device Research Conference, Bordeaux, 1998, pp. 140–143. 3. D L Harame, E F Crabbe, J D Cressler, J H Comfort, J Y-C Sun, S R Stiffler, E Kobeda, J N Burghartz, M M Gilbert, J C Malinowski, A J Dally, S Ratanaphanyarat, M J Saccamango, W Rausch, J Cotte, C Chu, and J M C Stork. A high performance epitaxial SiGe-base ECL BiCMOS technology. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1992, pp. 19–22. 4. B Heinemann, D Knoll, G Fischer, D Kru¨ger, G Lippert, H J Osten, H Ru¨cker, W Ro¨pke, P Schley, and B Tillack. Control of steep boron profiles in Si/SiGe heterojunction bipolar transistors. Proceedings of the European Solid-State Device Research Conference, Stuttgart, 1997, pp. 544–547. 5. H J Osten, G Lippert, D Knoll, R Barth, B Heinemann, H Ru¨cker, and P Schley. The effect of carbon incorporation on SiGe heterobipolar transistor performance and process margin. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1997, pp. 803–806. 6. D Knoll, B Heinemann, H J Osten, K E Ehwald, B Tillack, P Schley, R Barth, M Matthes, K S Park, Y Kim, and W Winkler. Si/SiGe:C heterojunction bipolar transistors in an epi-free well, singlepolysilicon technology. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1998, pp. 703–706. 7. H J Osten, D Knoll, B Heinemann, H Ru¨cker, and B Tillack. Carbon doped SiGe heterojunction bipolar transistors for high frequency applications. Proceedings of the Bipolar/ BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 109–116. 8. K E Ehwald, D Knoll, B Heinemann, K Chang, J Kirchgessner, R Mauntel, I S Lim, J Steele, P Schley, B Tillack, A Wolff, K Blum, W Winkler, M Pierschel, U Jagdhold, R Barth, T Grabolla, H J Erzgra¨ber,

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9.

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20.

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B Hunger, and H J Osten. Modular integration of high-performance SiGe:C HBTs in a deep submicron, epi-free CMOS process. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1999, pp. 561–564. D Knoll, B Heinemann, K E Ehwald, G G Fischer, and B Hunger. Emitter scaling of singlepolysilicon SiGe:C HBTs with highly doped base layers. Proceedings of the European Solid-State Device Research Conference, Cork, 2000, pp. 560–563. S A St Onge, D L Harame, J S Dunn, S Subbana, D C Ahlgren, G Freeman, B Jagannathan, S J Jeng, K Schonenburg, K Stein, R Groves, D Coolbaugh, N Feilchenfeldt, P Geiss, M Gordon, P Gray, D Hershberger, S Kilpatrick, R Johnson, A Joseph, L Lanzerotti, J Malinowski, B Orner, and M Zierak. A 0.24 mm SiGe BiCMOS mixed-signal RF production technology featuring a 47 GHz fT HBT and 0.18 mm leff CMOS. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 117–120. B Heinemann, D Knoll, R Barth, D Bolze, K Blum, J Drews, K E Ehwald, G G Fischer, K Ko¨pke, D Kru¨ger, R Kurps, H Ru¨cker, P Schley, W Winkler, and H E Wulf. Cost-effective high-performance high-voltage SiGe:C HBTs with 100GHz fT and BVCEO fT products exceeding 220 V GHz. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2001, pp. 348–351. D Knoll, B Heinemann, K E Ehwald, H Ru¨cker, B Tillack, W Winkler, and P Schley. BiCMOS integration of SiGe:C heterojunction bipolar transistors. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 162–166. B Heinemann, H Ru¨cker, R Barth, J Bauer, D Bolze, E Bugiel, J Drews, K E Ehwald, T Grabolla, U Haak, W Ho¨ppner, D Knoll, D Kru¨ger, B Kuck, R Kurps, S Marschmeyer, H H Richter, P Schley, D Schmidt, R F Scholz, B Tillack, W Winkler, D Wolansky, H E Wulf, Y Yamamoto, and P Zaumseil. Novel collector design for high-speed SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 775–778. H Ru¨cker, B Heinemann, R Barth, D Bolze, J Drews, U Haak, W Ho¨ppner, D Knoll, K Ko¨pke, S Marschmeyer, H H Richter, P Schley, D Schmidt, R F Scholz, B Tillack, W Winkler, H E Wulf, and Y Yamamoto. SiGe:C BiCMOS technology with 3.6 ps gate delay. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 121–124. B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R F Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. H Ru¨cker, B Heinemann, D Bolze, D Knoll, D Kru¨ger, R Kurps, H J Osten, P Schley, B Tillack, and P Zaumseil. Dopant diffusion in C-doped Si and SiGe: Physical model and experimental verification. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1999, pp. 345–348. D Knoll, K E Ehwald, B Heinemann, A Fox, K Blum, H Ru¨cker, F Fu¨rnhammer, B Senapati, R Barth, U Haak, W Ho¨ppner, J Drews, R Kurps, S Marschmeyer, H H Richter, T Grabolla, B Kuck, O Fursenko, P Schley, R F Scholz, B Tillack, Y Yamamoto, K Ko¨pke, H E Wulf, D Wolansky, and W Winkler. A flexible, low-cost, high performance SiGe:C BiCMOS process with a one-mask HBT module. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 783–786. B Senapati, R F Scholz, D Knoll, B Heinemann, and A Chakravorti. Application of the VBIC model for SiGe:C heterojunction bipolar transistors. Proceedings of the 11th International Conference Mixed Design of Integrated Circuits and Systems, Szczecin, 2004. W Winkler, J Borngra¨ber, B Heinemann, P Weger, and H Gustat. High-performance and low-voltage divider circuits fabricated in SiGe:C HBT technology. Proceedings of the European Solid-State Circuits Conference, Firenze, 2002, pp. 827–830. W Winkler, J. Borngra¨ber, H Gustat, and F Korndo¨rfer. 60 GHz transceiver circuits in SiGe:C BiCMOS technology. Proceedings of the 30th European Solid-State Circuits Conference, Leuven, 2004, pp. 83–86.

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21. W Winkler, J Borngra¨ber, B Heinemann, and P Weger. 60 GHz and 76 GHz oscillators in 0.25 mm SiGe:C BiCMOS. IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, 2003, pp. 454–455. 22. W Winkler, J Borngra¨ber, and B Heinemann. A 117 GHz LC-oscillator in SiGe:C BiCMOS technology. Materials Science in Semiconductor Processing, Vol. 8, Numbers 1–3, February/June 2005, pp. 459–461. 23. W Winkler and J Borngra¨ber. LC-oscillator for 94 GHz automotive radar system fabricated in SiGe:C BiCMOS technology. Conference Proceedings of the 12th European Gallium Arsenide & other Compound Semiconductors Application Symposium, Amsterdam, 2004, pp. 45–46.

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12 Industry Examples at the State-of-the-Art: ST Alain Chantre, M. Laurens, B. Szelag, H. Baudry, P. Chevalier, J. Mourier, G. Troillard, B. Martinet, M. Marty, and A. Monroy ST Microelectronics

12.1

12.1 12.2 12.3 12.4 12.5 12.6

Introduction..................................................................... 12-1 Device Structures............................................................. 12-2 Doping and Impurity Profiles........................................ 12-5 BiCMOS Integration Issues ............................................ 12-6 High-Frequency Characteristics ..................................... 12-9 Outlook for the Future ................................................. 12-11

Introduction

The history of SiGe BiCMOS technology development in the ‘‘French silicon valley’’ goes back to the early 1990s [1], when a team of materials researchers at France Telecom CNET Laboratories near Grenoble started investigations in the Si/SiGe system using rapid thermal chemical vapor deposition (RTCVD). Application of this work to the development of heterojunction bipolar transistors (HBTs) soon became a major research theme for the local bipolar device group [2–4]. At the same time, the development of a 0.5-mm single-polysilicon BiCMOS technology was going on in the new 200 mm Crolles plant of STMicroelectronics, a few kilometers away. A joint development work was then initiated between the two teams, with the objective to bring SiGe HBTs into manufacturing when the performance potential of silicon-only bipolar transistors would be fully exhausted [5]. This eventually happened with the 25/40 GHz fT/fmax double-polysilicon self-aligned transistor embedded in the 0.35-mm BiCMOS process. When it was internally demonstrated that much better performance, e.g., 50/70 GHz fT/fmax, could be obtained at the same technology node using a low-complexity SiGe HBT architecture [6], SiGe BiCMOS technology development at ST became a reality. Several SiGe BiCMOS processes, covering the 0.35, 0.25, and 0.13 mm technology nodes, and addressing both wireless and broadband communications applications, have been developed since then, and are now in production or at prototyping level at the Crolles plant. Table 12.1 outlines the main technological features of these processes, in terms of device isolation scheme, SiGe epitaxial base process, emitter–base and collector architectures, and emitter material. Main static and dynamic parameters of the high-speed SiGe HBT in these technologies are also summarized. A common feature of all these processes is the use of RTCVD for the growth of the SiGe (or SiGe:C) base. As discussed in Chapter 5 (see SiGe and Si Strained-Layer Epitaxy for Silicon Heterostructure Devices), RTCVD presents many advantages over competing approaches, and is today the dominant technique for conventional Si epitaxy as well as advanced SiGe processes in the semiconductor industry. Likewise, all technologies rely on a conventional collector structure, consisting of a heavily arsenicimplanted layer buried under lightly doped epitaxial silicon. In contrast with these longstanding technological options, Table 12.1 shows that several materials and architecture changes have been brought to the SiGe HBT while moving along the performance path from 45 to 160 GHz fT. The motivations for these structural changes and the accompanying evolutions of transistor doping and 12-1

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TABLE 12.1

ST SiGe BiCMOS Technologies: Main Process Features and Device Parameters

Technology

BiCMOS6G

BiCMOS7

BiCMOS7RF

BiCMOS9

CMOS node Back-end

0.35 mm Al

0.25 mm Al

0.25 mm Al

0.13 mm Cu

Collector Isolation Base E/B architecture Emitter

BL/epitaxy LOCOS SiGe NSEG QSA single-poly As implant Poly

BL/epitaxy STI/DTI SiGe NSEG QSA double-poly As in-situ doping Mono

BL/epitaxy STI/DTI SiGeC NSEG QSA double-poly As in-situ doping Mono

BL/epitaxy STI/DTI SiGeC NSEG QSA double-poly As in-situ doping Mono

WE (mm) RpB (kV/sq) Basewidth (nm)

0.4 10 —

0.25 6.5 50

0.25 1 —

0.17 3.6 25

Current gain BVCEO (V) VAF (V) fT (GHz) fmax (GHz) JC (mA/mm2) NFmin @ 2 GHz

100 3.6 60 45 60 1.0 0.8

120 2.6 >50 70 90 3.8 —

200 3.0 >150 60 120 1.8 <0.4

600 1.7 >150 160 160 7.5 —

Applications Status

RF Production

Broadband Production

RF, PA Prototyping

Broadband Prototyping

Refs.

[8]

[9]

[15,16]

[17]

impurity profiles are discussed in Sections 12.2 and 12.3, respectively. Section 12.4 addresses some of the issues that have been encountered while integrating these HBTs into the corresponding CMOS flows. Main high-frequency characteristics of the SiGe HBT in the various technologies are reviewed in Section 12.5. Finally, Section 12.6 concludes the chapter with early results from the development of next generation transistors, targeting 230 GHz cutoff frequencies for the 90-nm technology node.

12.2

Device Structures

Figure 12.1 displays SEM cross sections through the SiGe and SiGe:C HBTs used in ST SiGe BiCMOS technologies. The geometrical scale can be inferred from the contact size, i.e., 0.4 mm in (a), 0.25 mm in (b and c) and 0.16 mm in (d). A glance at the pictures shows that, in all technologies, the SiGe base is grown using nonselective epitaxy (NSEG). Compared to the alternative selective deposition process (SEG), this approach presents several advantages [7]: simpler chemistry, larger growth rates (or lower growth temperature), reduced macro- and microloading effects, and improved metrology. Unfortunately, these advantages on the manufacturability side come at the expense of a penalty on the performance side. Indeed, there is no simple way to build a SiGe HBT with fully self-aligned (FSA) emitter–base (E–B) regions on a nonselective base. As briefly discussed in Section 12.6, there are only complex solutions to this problem, which (at least partly) outbalance the advantages of NSEG over SEG structures. A pragmatic answer to this manufacturability vs. performance trade-off is provided by the family of quasiself-aligned (QSA) HBT structures implemented in ST SiGe BiCMOS technologies. As shown in Figure 12.1a, a single-polysilicon QSA structure is used in BiCMOS-6G [8], which mainly addresses the RF mobile communications market. In this construction, the poly-SiGe extension of the base formed on the field oxide (here LOCOS) during epitaxy is used as the extrinsic base material. The emitter (width WE ¼ 0.4 mm) is defined by a window opened in a thin deposited nitride/oxide stack. The low topography of the structure enables the use of a conventional arsenic-implanted polysilicon emitter, which is subsequently patterned around the emitter window using a second

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Industry Examples at the State-of-the-Art: ST

(a)

(b)

(c)

(d)

FIGURE 12.1 SEM cross sections through the SiGe and SiGe:C HBTs used in ST SiGe BiCMOS technologies: (a) BiCMOS-6G, (b) and (c) BiCMOS-7 and -7RF, (d) BiCMOS-9. (From M. Laurens, B. Martinet, O. Kermarrec, Y. Campidelli, F. Dele´glise, D. Dutartre, G. Troillard, D. Gloria, J. Bonnouvrier, R. Beerkens, V. Rousset, F. Leverd, A. Chantre, and A. Monroy. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 147–150. With permission.)

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Fabrication of SiGe HBT BiCMOS Technology

lithography level. An extrinsic base implant is then performed self-aligned to the polysilicon emitter block (i.e., not to the emitter), followed by dopant activation and salicidation. This single-polysilicon QSA structure is very simple and ideally meets the performance needs of BiCMOS-6G (45/60 GHz fT/fmax). However, several limitations have been foreseen when considering the significantly higher performances (70/90 GHz fT/fmax) targeted for the second generation technology, BiCMOS-7: (i) narrow emitter windows (below 0.3 mm) are difficult to obtain using this process, which penalizes base resistance-related parameters (e.g., fmax, NFmin) and power consumption; (ii) good silicidation of the poly/mono-SiGe/Si boundary region at the edge of the active area is difficult, which penalizes the base access resistance; (iii) point defects injected at the emitter periphery during extrinsic base implantation cause enhanced boron diffusion and base widening [3], which negatively impacts the forward transit time (fT). The double-polysilicon QSA structure developed for BiCMOS-7 successfully addresses all these limitations* [9]. As shown in Figure 12.1b and c, shallow/deep trench isolation (STI/DTI) is used in this technology, which reduces parasitic capacitances and provides a flat topography after SiGe base epitaxy. A conventional double-polysilicon structure is constructed above the base, resulting in the following advantages regarding items (i) to (iii) above: (i) internal spacers reduce the effective emitter width from the emitter window opening, enabling narrow emitters (WE ¼ 0.25 mm) without specific lithography requirements; (ii) extrinsic base silicidation is greatly improved by the availability of a true polysilicon base layer (on top of the poly-SiGe extension of the base), and by the flat topography of the structure at the edges of the base active area; (iii) the extrinsic-to-intrinsic base contact region is formed by the out-diffusion of boron from the base polysilicon layer, avoiding base widening effects related to high-dose implants through the SiGe layer. In order to prevent overetching into the thin epitaxial base during emitter window opening, a polysilicon/oxide pedestal is patterned on the SiGe base prior to base polysilicon deposition, as visible in Figure 12.1c. As a result, emitter and base regions are not self-aligned in this structure either. However, it has been found that a proper overlay strategy with present-day steppers allows enough process margin for the emitter window enclosure by this etch-stop layer, while easily meeting BiCMOS-7 performance targets. A closer look at Figure 12.1c also reveals a significant difference in the crystalline structure of the emitter, when compared with the first-generation transistor. Indeed, due to the larger topography of the structure at the emitter deposition step, in-situ arsenic-doped polysilicon is used in BiCMOS-7 to avoid emitter perimeter depletion and plug effects. This material is deposited in a commercial singlewafer CVD reactor. Load locks and a very clean ambient eliminate any unwanted oxide layer at the poly-Si–Si interface, resulting in monocrystalline structure on the active transistor region and in polycrystalline structure on the surrounding isolation regions at the end of the process (Figure 12.2). These so-called monoemitters have many advantages over conventional polyemitters [10,11]: (i) very shallow and uniform E/B junction depths are obtained; (ii) manufacturability issues related to the control and reproducibility of the interfacial oxide layer are suppressed; (ii) emitter resistance and low frequency noise are significantly reduced; (iii) base current is increased, which translates into an improved emitter-to-collector breakdown voltage, BVCEO. It should be pointed out that this monocrystalline emitter process was first described in Ref. [12], and is now becoming a standard in the SiGe BiCMOS technology industry. Extension to a SiGe emitter process has also been proposed recently [13]. The range of performances achievable with the double-polysilicon QSA HBT structure has been dramatically extended by introducing SiGe:C base technology [14]. The device used in BiCMOS-7RF, which addresses RF [15] and power amplifier [16] applications, is structurally and geometrically identical to the BiCMOS-7 transistor shown in Figure 12.1b and c. Here, carbon doping of SiGe is * It should be pointed out that the latter two effects (ii) and (iii) are minimized in more recent technologies using shallow trench isolation (STI) instead of LOCOS (this reduces the topography of the structure at the edges of the base active area), and carbon-doping of the SiGe base (which suppresses to a large extent transient enhanced diffusion effects caused by the extrinsic base implant).

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Industry Examples at the State-of-the-Art: ST

Poly

Epi

SiGe base 60 nm

FIGURE 12.2 TEM cross section showing the monocrystalline structure of the emitter in ST BiCMOS-7 technology (similar emitter structure is used in BiCMOS-7RF and -9).

leveraged to improve high-frequency noise figures by enabling much larger integrated base doping concentration. In contrast, the SiGe:C process developed for BiCMOS-9 aims at producing devices with ultrathin bases, in order to comply with the very high cutoff frequencies (160 GHz fT and fmax) required for broadband communications applications [17]. As shown in Figure 12.1d, the transistor structure has been scaled vertically and laterally while moving to 0.13 mm technology node. Vertical scaling was imposed by CMOS compatibility constraints, as discussed in Section 12.4. Horizontal scaling, with final emitter widths of 0.17 mm, minimizes the intrinsic component of the base resistance, as well as parasitic elements such as collector resistance and collector/base (C/B) capacitance, which is needed to reach frequency performance targets. Moreover, a reduced emitter stripe width is mandatory to accommodate the increased current density at peak fT in this technology (see Figure 12.9).

12.3

Doping and Impurity Profiles

Transistor doping and impurity profiles have also greatly evolved throughout these developments. The main features of these profiles and the motivations for these evolutions are discussed in this section, with the help of the schematic drawings shown in Figure 12.3. BiCMOS-6G and -7, which use a pure SiGe base (i.e., without carbon doping), rely on a ‘‘conventional’’ E/B dopant distribution, where the arsenic profile intercepts the boron profile close to its maximum value (Figure 12.3a). The doping level there is typically limited to 5 1018 cm3 to avoid tunneling currents and excessive E/B junction capacitance. A two-step germanium profile is used in the base, with larger concentration on the collector side than on the emitter side. This profile serves several purposes and is designed as follows: (i) the Ge content of the lower step sets (to a large extent) the current gain of the transistor; (ii) the flat Ge profile at the E/B junction stabilizes the current gain against fluctuations in the junction depth and improves the reverse Early voltage (as compared to a graded Ge profile); (iii) the larger Ge concentration on the collector side reduces boron diffusion and base widening during processing; (iv) the Ge step in the base creates a pseudoelectric field, which reduces base transit time and improves fT; and (v) the difference in the Ge content between C/B and E/B

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Fabrication of SiGe HBT BiCMOS Technology

SiGe HBT

Ge B

SiGe:C HBT Ge

As

Concentration

Concentration

As

B

P

P

(a)

Depth

(b)

Depth

FIGURE 12.3 Schematic evolution of transistor doping and impurity profiles through ST SiGe BiCMOS technologies: (a) BiCMOS-6G and -7, (b) BiCMOS-7RF (dashed lines), and BiCMOS-9 (solid lines).

junctions increases the forward Early voltage of the transistor. It shoud be pointed out that the whole profile has been scaled down while moving from BiCMOS-6G to -7, in order to comply with the frequency performance increase (final basewidth WB is 50 nm in the latter process). This has been highly facilitated by the introduction of the monoemitter process discussed above. The collector doping, set by a masked implantation prior to SiGe base deposition, has also been adjusted (i.e., increased). No change has been brought to the collector epitaxy thickness. Doping and Ge profiles used in BiCMOS-9 and 7RF SiGe:C technologies are significantly different from the above discussed profiles (Figure 12.3b). Their main features can be summarized as follows: (i) a bell-shaped boron distribution with peak doping concentration significantly above 1019 cm3 is used in the base, which is made possible by the strong reduction of boron diffusion in SiGe:C [14]; (ii) there is no overlap between arsenic and boron profiles, which keeps E/B junction capacitance low despite the heavy base doping level; (iii) the Ge content is graded across the base on the emitter side, in order to compensate the retarding electric field associated with the retrograde boron profile; (iv) a flat Ge profile is used on the collector side, where an accelerating field is created by the boron distribution itself. Such trapezoidal Ge profile has been found optimum to avoid layer stability issues and high injection induced barrier effects in high-voltage transistors, which can been encountered with triangular Ge profiles. As shown in Figure 12.3b, different optimizations of this generic SiGe:C HBT profile are used in BiCMOS-9 and -7RF. BiCMOS-9 favors a short forward transit time to reach the high fT target. This is obtained using a very thin base (WB 25 nm), a high collector doping, and a thin collector epitaxy. Despite the narrow base, pinched base resistance remains low (RpB 3.6kV/sq.) thanks to the heavy boron doping, enabling simultaneously high fT and fmax in this technology. In contrast, noise figure and analog characteristics are given prior attention in BiCMOS-7RF. To this end, the boron spike width (and the whole SiGe:C stack) has been enlarged, leading to very low base resistance (RpB 1 kV/sq). Also, larger spacing is used between arsenic and boron profiles (through the thickness of the silicon-capping layer), which reduces E/B junction capacitance and improves low current characteristics. The collector structure in this technology is similar to BiCMOS-7. As detailed in Refs. [15,17], the carbon concentration in both SiGe:C technologies has been carefully optimized to effectively suppress boron diffusion during processing, while avoiding E/B and neutral base recombination effects observed at excessively large carbon contents.

12.4

BiCMOS Integration Issues

One major challenge of BiCMOS integration engineers is to design a process flow in such a way that bipolar transistors can be added without disturbing CMOS devices, in order to retain full compatibility

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with existing logic libraries. This has become increasingly difficult, with the downscaling of CMOS gate lengths and the upscaling of bipolar cutoff frequencies. BiCMOS integration issues are briefly reviewed in this section, with special emphasis on ST’s most challenging technology in this respect, i.e., BiCMOS-9. Generally speaking, the integration of a high-speed HBT within an advanced CMOS technology raises several types of concerns: (i) Thermal cycle issues. The process flow must be designed to avoid substantial CMOS dopant motion due to the addition of the HBT fabrication steps. The hydrogen pre-bake used in RTCVD to clean the base active area prior to SiGe epitaxy is particularly critical in this regard. Symmetrically, high-temperature CMOS processing must be placed prior to the HBT formation to minimize base broadening. It should be pointed out that the use of SiGe:C is very helpful, due to the blocking effect of carbon on the diffusion of boron. Arsenic emitter doping (as opposed to phosphorous) is also favorable, since it is compatible with the final activation anneal of the CMOS process, that the HBT is usually exposed to. (ii) Structural integration issues. The fabrication of the HBT in the presence of CMOS gate topography requires careful choice of integration sequence. Numerous films are deposited during the HBT formation, as illustrated on Figure 12.4 which shows the accumulation of some of these films over closely spaced 0.13-mm gates in BiCMOS-9. Subsequent etch steps must isotropically remove these films without leaving unwanted spacers. Another difficulty encountered in the development of BiCMOS-9 is related to the thin photoresists used for critical lithography steps, such as gate patterning. The topography of the adjacent bipolar areas must then be low enough to ensure that sufficient resist be left there to avoid damaging the HBTs while processing CMOS gates. (iii) Back-end compatibility issues. Thin premetal dielectric layers are used in advanced CMOS technologies to reduce the contact hole aspect ratio. This raises concerns in a BiCMOS process, where bipolar transistors are usually higher than CMOS devices, and justifies the significant vertical scaling applied to the double-polysilicon QSA HBT structure while moving to 0.13-mm technology node (see Figure 12.1c and d). Electromigration issues must also be paid attention in high-speed SiGe BiCMOS technologies, where large current densities (JC) can be attained at peak fT. In BiCMOS-9 where JC 7.5 mA/mm2, full compatibility with the back-end rules of the core CMOS process has been maintained by developing a specific transistor layout, with two rows of contacts (and vias) on emitter and collector regions (see Figure 12.1d). A generic process flow for ST SiGe BiCMOS technologies is shown in Figure 12.5. In all processes, the fabrication starts with buried layer formation on a p-substrate, followed by collector epitaxy. The DTI module is then inserted (except in BiCMOS-6G). Next, the shallow trench module (or LOCOS for BiCMOS-6G) of the CMOS core process is implemented, and the collector reachthrough is formed. At

FIGURE 12.4 SEM cross section showing closely spaced 0.13-mm CMOS gates covered by SiGe:C HBT films in ST BiCMOS-9 technology.

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Fabrication of SiGe HBT BiCMOS Technology

CMOS backbone

Bipolar steps

Shallow trench isolation

Buried layer and collector epitaxy Deep trench isolation Collector reachthrough

Well implants Gate oxide process Poly gate

Extension & S/D implants Activation anneal Salicidation and contacts Metal interconnect

SIC implant Base epitaxy Emitter−base structure

FIGURE 12.5 Schematic integration flow for ST SiGe BiCMOS technologies, showing insertion of bipolar modules into the CMOS core process.

FIGURE 12.6 Saturation current vs. threshold voltage for 1.2 V low leakage nMOS and pMOS transistors in 0.13 mm pure CMOS and BiCMOS-9 technologies. (From M. Laurens, B. Martinet, O. Kermarrec, Y. Campidelli, F. Dele´glise, D. Dutartre, G. Troillard, D. Gloria, J. Bonnouvrier, R. Beerkens, V. Rousset, F. Leverd, A. Chantre, and A. Monroy. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 147–150. With permission.)

this stage, the CMOS flow resumes with the formation of wells, gate oxides, and polysilicon gates. Deviations then exist regarding the fabrication of the emitter–base structure of the HBT. In BiCMOS6G, 7, and 7RF, where the main concern was the integrity of the pMOS transistor, the whole E/B module is inserted between extension and source/drain implants, in order to avoid boron penetration through the gate oxide. The situation is more complex in the case of BiCMOS-9, where both CMOS and bipolar devices have become very touchy. A novel integration scheme has been developed for this technology [17], in which E/B fabrication steps are split into two parts, in such a way that all integration issues discussed in concerns (i) and (ii) are solved. Finally, all fabrication sequences are completed by the activation anneal of dopants, salicidation, contact formation, and metallization. Figure 12.6 compares 0.13-mm pure CMOS and BiCMOS-9 technologies regarding the saturation current and the threshold voltage of nMOS and pMOS transistors. The results demonstrate the successful integration of the high-speed SiGe:C HBT with the newly developed BiCMOS integration scheme.

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12.5

High-Frequency Characteristics

Figure 12.7 and Figure 12.8 summarize high-frequency figures-of-merit fT vs. BVCEO and fmax vs. fT for the low-voltage SiGe HBT in the various technologies discussed above, and for a high-voltage device obtained in BiCMOS-7RF and -9 by altering the collector doping profile. Shown values of fT and fmax are

200

BC6G BC7 150

BC7RF

fT (GHz)

BC9 180

270

BC7RF-HV

100

BC9-HV

50 f T ⫻ BVCEO (GHz-V) 0 0

2

8

6

4 B V CEO (V)

FIGURE 12.7 fT vs. BVCEO data for high-speed and high-voltage SiGe HBTs in ST SiGe BiCMOS technologies. Solid lines represent process design contours with constant fTBVCEO product.

200 fmax > fT 150

fmax (GHz)

fmax < fT BC6G

100

BC7 BC7RF 50

BC9 BC7RF-HV BC9-HV

0 0

50

100

150

200

f T(GHz)

FIGURE 12.8

fmax vs. fT data for high-speed and high-voltage SiGe HBTs in ST SiGe BiCMOS technologies.

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200 BC9 BC6G

150 f T (GHz)

BC7 BC7RF 100

50

0 0.01

0.1

1 JC

10

100

(mA/µm2)

FIGURE 12.9 Comparison of fT vs. JC characteristics for SiGe and SiGe:C HBTs in ST SiGe BiCMOS technologies (high-speed devices only).

derived from s-parameter measurements up to 110 GHz. Details on the procedure used to extract fmax from unilateral power gain data may be found in Ref. [17]. The fT vs. BVCEO plot in Figure 12.7 shows the classical trade-off between operation speed and breakdown voltage, with fT BVCEO products close to 180 GHz-V for most devices, except in BiCMOS-9 where this product rises up 270 GHz-V for the high-speed SiGe:C HBT. Figure 12.8 shows that fmax/fT ratios larger than unity have been maintained throughout the roadmap, which indicates that process enhancements used to increase fT have not been detrimental to fmax. This holds true for the high-speed HBT in BiCMOS-9, where fTfmax 160 GHz. This remarkable (and somewhat unexpected) result demonstrates that the combination of the robust double-polysilicon QSA HBT structure with a thin and heavily doped SiGe:C base can provide outstanding frequency performances. The various SiGe technology generations are further compared in Figure 12.9 and Figure 12.10, which plot the dependencies of fT and fmax on collector current density JC. Here again, a classical trend of increasing current density with peak fT value is observed: from 45 to 160 GHz, approximately eightfold increase in JC at peak fT is obtained. This reflects the delayed onset of Kirk effect at increasing collectordoping concentrations. The benefits of SiGe:C base technology and geometrical scaling for RF and broadband applications are highlighted by the following observations: (i) RF applications. Comparing BiCMOS-7RF and -7 characteristics in Figure 12.7 to Figure 12.10, one notices a large increase in fmax (from 90 to 120 GHz), despite a 10-GHz decrease in fT linked to a small BVCEO adjust. This results from the drastic reduction of base resistance (pinched base resistance decreases from 6.5 to 1kV/sq) achieved with heavy SiGe:C base doping. As shown in Figure 12.11, this translates into excellent HF noise characteristics: NFmin at 2 GHz is lower than 0.4 dB in BiCMOS-7RF, which is twice smaller than in the first RF SiGe process, BiCMOS-6G. Comparing further BiCMOS-6G and -7RF performances in Figure 12.10, it is found that fmax has been increased by a factor of 2 for similar current per unit transistor length (i.e., similar JC WE). This large performance improvement is explained by the combination of the heavily doped SiGe:C base and the reduced emitter width in BiCMOS7RF. As discussed in Ref. [16], the high-voltage SiGe:C HBT also benefits from these features, enabling the integration of power amplifiers with RF functions using this technology. (ii) Broadband applications. Similarly, the introduction of carbon-doped SiGe and the downscaling of emitter widths from 0.25 to 0.17 mm account for the large fmax performance jump (þ60 GHz) between BiCMOS-7 and -9 HBTs (Figure 12.10). In this case, the process has

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1.2

NF min(dB)

1.0

200 BC9 BC6 G

f max (GHz)

150

BC7 BC7RF

AE = 6⫻(0.25⫻9.85) µm2 f = 2 GHz VBC = 0 V VBC = −1 V

0.8 0.6 0.4 0.2

100

0 0

50

0.005

0.01

0.015

0.02

IC (A)

0 0.01

0.1

1

10

100

JC (mA/µm2)

FIGURE 12.10 Comparison of fmax vs. JC characteristics for SiGe and SiGe:C HBTs in ST SiGe BiCMOS technologies (high-speed devices only).

FIGURE 12.11 Noise figure vs. collector current at 2 GHz for BiCMOS-7RF SiGe:C HBT. (From H. Baudry, B. Szelag, F. Dele´glise, M. Laurens, J. Mourier, F. Saguin, G. Troillard, A. Chantre, and A. Monroy. IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 207–210. With permission.)

been designed to provide similar fT enhancement simultaneously. As shown in Figure 12.9, the SiGe:C HBT in BiCMOS-9 has about twice the fT of the BiCMOS-7 device at its peak current density of 4 mA/mm2. Alternatively, this approximately twofold higher frequency can be traded for an approximately fivefold reduction in power consumption at the same frequency for applications not requiring the ultimate performance. It should be pointed out that, in addition to these remarkable frequency performances, excellent yield results and process reproducibility have been demonstrated for this technology, as detailed in Ref. [17].

12.6

Outlook for the Future

In this chapter, the main features of ST 0.35, 0.25, and 0.13 mm SiGe BiCMOS technologies have been reviewed, with emphasis on SiGe HBT structures, profiles, and high frequency characteristics. Further details on these processes, including other available active and passive components, may be found in the literature [8,15–17]. Circuit applications of these technologies for the mobile communications market are described in Chapter 16 (see Circuits and Applications Using Silicon Heterostructure Devices) of this book. As far as optical communications applications are concerned, available circuit results indicate that the 160 GHz fT/fmax BiCMOS-9 device is able to address the 40 Gb/s market [18,19]. For more demanding applications, such as 77 GHz automotive radar, higher frequency performances will be required, e.g., >230 GHz fT/fmax. From the past experience in BiCMOS-9 technology optimization, we estimate that the doublepolysilicon QSA HBT architecture can be extended over 200 GHz fT, but that aggressive design rules would be needed to reach 230 GHz fmax. Consequently, decision has been made to investigate a FSA HBT structure for 90-nm SiGe BiCMOS generation. As mentioned already, FSA HBT structures using nonselective base epitaxy are not straightforward. They require specific process modules, such as CMP or countermask lithography, which are not easy to implement and to integrate into a BiCMOS flow. For this and other reasons discussed in Refs. [20,21], the approach used at ST is based on the selective epitaxial base (FSA-SEG) concept, which has the other advantage to be mask-compatible with the QSA-NSEG approach.

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FIGURE 12.12

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SEM cross section through a FSA-selective SiGe:C base HBT fabricated using BiCMOS-9 reticles.

400

55 K

f max fT, fmax (GHz)

300

fT 300 K

200

100

0 0.1

AE = 0.17⫻3.6 µm2 VC B = 0.5 V 1

10

100

JC (mA/µm2)

FIGURE 12.13 High-frequency characteristics at 300 and 55 K of a FSA-selective SiGe:C base HBT fabricated using BiCMOS-9 reticles.

Figure 12.12 shows an SEM cross section through a FSA-SEG SiGe:C HBT fabricated using BiCMOS-9 reticles. The main difficulty with the selective epitaxy of SiGe:C is the higher growth temperature compared to nonselective epitaxy, which is detrimental to the carbon incorporation on substitutional sites. However, by proper optimization of the carbon and Ge profiles, this difficulty can be solved, and good process manufacturability and world class device performances (230 and 350 GHz fT/fmax at room and cryogenic temperatures, respectively) have been demonstrated, such as shown in Figure 12.13. It should be pointed out that these performances have been obtained for a device using an arsenic-doped monoemitter and sustaining a high thermal budget, which will facilitate its later integration with 90-nm CMOS.

Acknowledgments The authors are indebted to the many people at ST Microelectronics Crolles involved in the various aspects of this work. In particular, they wish to thank the members of the epitaxy teams of D. Dutartre (C. Fellous, F. Dele´glise, and L. Rubaldo) and D. Bensahel (Y. Campidelli and O. Kermarrec), and of the former CVD group of J.L. Regolini at France Telecom CNET Laboratories, for their contributions to making SiGe BiCMOS technology at ST a success story. The continuous support of B. Sautreuil and M. Roche is also gratefully acknowledged.

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12-13

References 1. D. Dutartre, G. Bre´mond, A. Souifi, and T. Benyattou. Excitonic photoluminescence from Si-capped strained Si1–xGex layers. Phys. Rev. B 44:11525–11527, 1991. 2. H. Boussetta, G. Giroult-Matlakowski, B. Le Tron, D. Dutartre, P. Warren, M.J. Bouzid, and A. Chantre. Identification of peripheral base currents in Si or SiGe epitaxial-base single-polysilicon self-aligned bipolar transistors. Proceedings 24th European Solid-State Device Research Conference, Edinburgh, 1994, pp. 63–66. 3. S. Denorme, H. Boussetta, A. Chantre, G. Vincent, and M. Mouis. Demonstration of enhanced base diffusion due to extrinsic base implantations in submicron, polysilicon-emitter, epitaxial base bipolar transistors. Proceedings 25th European Solid-State Device Research Conference, The Hague, 1995, pp. 513–516. 4. B. Le Tron, M.D.R. Hashim, P. Ashburn, M. Mouis, A. Chantre, and G. Vincent. Determination of bandgap narrowing and parasitic energy barriers in SiGe HBTs integrated in a bipolar technology. IEEE Trans. Electron Devices 44:715–722, 1997. 5. E. de Berranger, S. Bodnar, A. Chantre, J. Kirtsch, A. Monroy, M. Laurens, A. Granier, J.L. Regolini, and M. Mouis. Performance improvement in a 200 mm BiCMOS technology by Si/SiGe heterojunction bipolar transistor integration. Proceedings 26th European Solid-State Device Research Conference, Bologna, 1996, pp. 433–436. 6. A. Chantre, M. Marty, J.L. Regolini, M. Mouis, J. de Pontcharra, D. Dutartre, C. Morin, D. Gloria, S. Jouan, R. Pantel, M. Laurens, and A. Monroy. A high performance low complexity SiGe HBT for BiCMOS integration. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1998, pp. 93–96. 7. D. Dutartre. Silicon epitaxy: new applications. In Semiconductors and Semimetals, vol. 72. Academic Press, New York, 2001, pp. 397–457. 8. A. Monroy, M. Laurens, M. Marty, D. Dutartre, D. Gloria, J.L. Carbonero, A. Perrotin, M. Roche, and A. Chantre. BiCMOS6G: a high performance 0.35 mm SiGe BiCMOS technology for wireless applications. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 121–124. 9. H. Baudry, B. Martinet, C. Fellous, O. Kermarrec, Y. Campidelli, M. Laurens, M. Marty, J. Mourier, G. Troillard, A. Monroy, D. Dutartre, D. Bensahel, G. Vincent, and A. Chantre. High performance 0.25 mm SiGe and SiGe:C HBTs using non selective epitaxy. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 52–55. 10. S. Jouan, R. Planche, M. Marty, D. Dutartre, J.A. Chroboczek, P. Llinares, H. Baudry, J. de Pontcharra, J.L. Regolini, G. Vincent, and A. Chantre. In-situ arsenic doped single-crystal emitters for low 1/f noise SiGe HBTs. Proceedings of the 29th European Solid-State Device Research Conference, Leuven, 1999, pp. 336–339. 11. S. Jouan, R. Planche, H. Baudry, P. Ribot, J.A. Chroboczek, D. Dutartre, D. Gloria, M. Laurens, P. Llinare`s, M. Marty, A. Monroy, C. Morin, R. Pantel, A. Perrotin, J. de Pontcharra, J.L. Regolini, G. Vincent, and A. Chantre. A high speed low 1/f noise SiGe HBT technology using epitaxially aligned polysilicon emitters. IEEE Trans. Electron Devices 46:1525–1531, 1999. 12. S. Niel, O. Rozeau, L. Ailloud, C. Hernandez, P. Llinare`s, M. Guillermet, J. Kirtsch, A. Monroy, J. de Pontcharra, G. Auvert, B. Blanchard, M. Mouis, G. Vincent, and A. Chantre. A 54 GHz fmax implanted base 0.35 mm single-polysilicon bipolar technology. Technical Digest IEEE International Electron Devices Meeting, Washington DC, 1997, pp. 807–810. 13. B. Martinet, F. Romagna, O. Kermarrec, Y. Campidelli, F. Saguin, H. Baudry, M. Marty, D. Dutartre, and A. Chantre. An investigation of the static and dynamic characteristics of high speed SiGe:C HBTs using a poly-SiGe emitter. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2002, pp. 147–150. 14. B. Martinet, H. Baudry, O. Kermarrec, Y. Campidelli, M. Laurens, M. Marty, T. Schwartzmann, A. Monroy, D. Bensahel, and A. Chantre. 100 GHz SiGe:C HBTs using non selective base

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15.

16.

17.

18. 19.

20.

21.

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epitaxy. Proceedings 31st European Solid-State Device Research Conference, Nuremberg, 2001, pp. 97–100. H. Baudry, B. Szelag, F. Dele´glise, M. Laurens, J. Mourier, F. Saguin, G. Troillard, A. Chantre, and A. Monroy. BiCMOS7RF: a highly manufacturable 0.25 mm BiCMOS RF-applications-dedicated technology using nonselective SiGe:C epitaxy. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 207–210. D. Muller, A. Giry, C. Arnaud, C. Arricastres, R. Sommet, B. Szelag, A. Monroy, and D. Pache. LDMOSFET and SiGe:C HBT integrated in a 0.25 mm BiCMOS technology for RF-PA applications. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 168–171. M. Laurens, B. Martinet, O. Kermarrec, Y. Campidelli, F. Dele´glise, D. Dutartre, G. Troillard, D. Gloria, J. Bonnouvrier, R. Beerkens, V. Rousset, F. Leverd, A. Chantre, and A. Monroy. A 150 GHz fT/fmax 0.13 mm SiGe:C BiCMOS technology. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 147–150. T.O. Dickson, R. Beerkens, and S.P. Voinigescu. A 2.5-V, 40-Gb/s decision circuit using SiGe BiCMOS logic. Proceedings Symposium on VLSI Circuits, Honolulu, 2004, pp. 206–209. S.P.Voinigescu, T.O. Dickson, R. Beerkens, and P. Westergaard. A comparison of Si CMOS, SiGe BiCMOS, and InP HBTs technologies for high-speed and millimeter-wave ICs. Proceedings Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, 2004, pp. 111–114. P. Chevalier, C. Fellous, B. Martinet, F. Leverd, F. Saguin, D. Dutartre, and A. Chantre. 180 GHz fT and fmax self-aligned SiGeC HBT using selective epitaxial growth of the base. Proceedings European Solid-State Device Research Conference, Estoril, 2003, pp. 299–302. P. Chevalier, C. Fellous, L. Rubaldo, D. Dutartre, M. Laurens, T. Jagueneau, F. Leverd, S. Bord, C. Richard, D. Lenoble, J. Bonnouvrier, M. Marty, A. Perrotin, D. Gloria, F. Saguin, B. Barbalat, N. Ze´rounian, F. Aniel, and A. Chantre. 230 GHz self-aligned SiGeC HBT for 90 nm BiCMOS technology. Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 225–228.

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13 Industry Examples at the State-of-the-Art: Texas Instruments Integration of a Complementary-SiGe BiCMOS Process for High-Speed Precision Analog Applications 13.1 13.2

Badih El-Kareh, Scott Balster, P. Steinmann, and Hiroshi Yasuda Texas Instruments

13.1

Introduction..................................................................... 13-1 Process Integration.......................................................... 13-2 Starting Material . Buried Layers, Collector Epitaxy . Lateral Isolation . Collector Sinkers, CMOS Wells . Base Modules . Emitter Modules . CMOS Module . Capacitors . Resistors

13.3

Components and their Characteristics.......................... 13-6 Bipolars . CMOS . Capacitors . Resistors Thermal Resistance

13.4 13.5

.

Circuit Application........................................................ 13-10 Summary ........................................................................ 13-10

Introduction

Extensive work has been published on RF SiGe [1–15] and SiGe:C [16–18,22] npn transistors with impressive cutoff frequencies in the range 40–350 GHz. There are, however, very little data available on SiGe and SiGe:C pnp transistors [19–21]. The design of complementary npn and pnp transistors of high and comparable performance is important to linear analog circuits with symmetrical architectures. In addition, there is a tradeoff between gain (b), transistor breakdown (BVCEO), early voltage (VA), cutoff frequency (fT), and noise that must be met for every application. Finally, there are limitations to the thermal budget that must be considered when integrating SiGe-bipolar, CMOS, and passive components. These considerations were taken into account during the development of a novel, full dielectrically isolated modular complementary-SiGe BiCMOS process that is now in manufacturing for ultrahighspeed precision analog circuits [23]. The availability of SiGe and a controlled emitter interface oxide (IFO) provide added flexibility during the tradeoff. This chapter describes the integration of bipolar, 13-1

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CMOS, and passive process modules; their interactions; and integration issues. Active and passive components and their key parameters are then discussed. The chapter concludes with a summary of results obtained on a typical voltage feedback operational amplifier.

13.2

Process Integration

This section describes the integration of bipolar, CMOS, and passive process modules and their interactions. Table 13.1 summarizes key processing steps. A schematic cross-section of the completed bipolar transistors is shown in Figure 13.1 for illustration.

Starting Material The starting material is commercially available silicon on insulator (SOI) wafers with 1.25-mm top silicon and 0.1 to 0.4-mm buried-oxide (BOX) on high-resistivity p-type support wafers. The choice of buried oxide (BOX) thickness is a tradeoff between thermal resistance, maximum applied voltage, parasitic capacitance between collector and support wafer, and cost. For high-voltage applications, the BOX thickness is typically 0.4 mm. It is thinned down to 0.1–0.2 mm wherever applicable to reduce thermal resistance and self-heating, particularly during operation at maximum power. Reducing the BOX thickness, however, increases parasitic capacitance. For a typical p-type support wafer, this increase is particularly significant in pnp structures because of the accumulating applied voltage and workfunction difference between collector and support wafer. Increasing its resistivity to >100 Ohm-cm reduces the impact of thinner BOX on parasitic capacitance and also improves the quality factor of passive components. The latter is especially important in RF applications.

Buried Layers, Collector Epitaxy The n- and p-buried layers (NBL and PBL) are patterned, implanted, and diffused into the top silicon film. The implant and anneal conditions are critical to maintaining low collector resistances while minimizing defect density, surface roughness, and autodoping during epitaxy. An epitaxial film is then deposited. Its minimum thickness is primarily limited by the buried-layer updiffusion, the selectively implanted collector (SIC) and base profiles, and their impact on transistor breakdown. Tighter control of the epitaxial film allows reduction of its nominal thickness, improving fT (mainly the npn fT) while maintaining the minimum transistor breakdown of 5.5 V. For some

TABLE 13.1

Key Process Modules

Starting material, SOI wafer Buried layer implants and anneal Collector epitaxy Isolation. Deep- and shallow-trench patterning and fill Collector sinker implants CMOS well implants npn base module pnp base module Precision polysilicon resistor patterning and implant npn emitter module pnp emitter module Patterning of CMOS gate, base, polysilicon resistors, polysilicon capacitor plates Source/drain implant and anneal MIM capacitor module Metal-1 and Metal-2 modules Thin-film resistor module Metal-3 and Metal-4 modules

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17 16

14

5

9

13

3

11 2

4

12

15

5

7

5 4

8

10

3 1

5

6

5 4

Buried oxide PNP

NPN Support wafer

FIGURE 13.1 Schematic cross-section of npn and pnp transistors. 1: n-buried layer; 2: p-buried layer; 3: collector epitaxy; 4: deep trench; 5: STI; 6: npn sinker; 7: pnp sinker; 8: npn base; 9: pnp base; 10: npn SIC; 11: pnp SIC; 12: NEMIT POLY; 13: PEMIT POLY; 14: CoSi2; 15: BPSG; 16: contact; 17: first metal (second to fourth metal not shown).

applications, boron is implanted in an intermediate region under the base of the pnp. This allows tailoring the collector profile independently of epitaxial thickness, reducing the collector resistance and improving fT while maintaining low-impact ionization at the collector–base junction.

Lateral Isolation Oxide-filled, deep, and shallow trenches fully encapsulate components. This isolation technique minimizes parasitic capacitances, eliminates latch-up, increases packing density, and allows for separate CMOS body-bias and extensions to high-voltage applications. Deep trenches are first patterned and etched into silicon through a triple oxide–nitride-oxide (ONO) stack of suitable film thickness. After partially filling deep trenches, shallow trenches are patterned, straddling deep trenches, and etched into silicon. A thin oxide liner is grown in both trenches followed by conventional oxide-fill and chemical– mechanical polishing (CMP). The process is optimized to minimize stress [24], and provide a quasiplanar surface for subsequent processing steps.

Collector Sinkers, CMOS Wells Collector sinkers are patterned and implanted to reduce collector resistance. Several factors are considered when defining the sinker dose and energy: the collector resistance, the limited thermal budget, and the sinker surface concentration. The latter is an important factor when constructing a ‘‘highdensity’’ capacitor over an n-type sinker with polysilicon as the second plate and the gate-oxide film as the dielectric. As the surface concentration increases, the oxidation rate increases, reducing the capacitance per unit area. An increase in surface concentration also degrades the dielectric integrity. An advantage of full dielectric isolation over junction isolation is the capability of independently isolating the bottom plate of the polysilicon–oxide–silicon capacitor. After growing 11.5-nm CMOS gate oxide, an intrinsic polysilicon film is deposited that constitutes the first part of the CMOS polysilicon gate. The second part is deposited during the npn base formation.

Base Modules The bipolar base modules begin after the deposition of the CMOS intrinsic gate-polysilicon. The npn base is first patterned by removing the gate-polysilicon and gate oxide from the base region. The SiGe

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npn base is grown epitaxially in the patterned windows and as a polysilicon film over the first intrinsic polysilicon-gate. The film can be in-situ doped or implanted. The base-polysilicon and first gatepolysilicon form the final CMOS gate, capacitor plates, and one of the polysilicon precision resistors. While low in concentration, the presence of Ge in the CMOS gate slightly modifies its bandgap, and hence workfunction [25]. For a specified threshold voltage, a minor re-adjustment in channel profile may become necessary when the npn base Ge concentration is modified. Patterning the pnp base is critical. The npn base polysilicon/epitaxy is first covered with a thin film that will serve as an etch stop in a subsequent step. The pnp base region is patterned through the stack, and a SiGe pnp base epitaxy/polysilicon deposited. Similarly to the npn, the film can be in-situ doped or implanted. A tight control of emitter patterning and film undercut allows the reduction of base dose and energy, and hence of base width, increasing fT without impacting emitter–base leakage. The Ge profile is tailored to maximize VA. The positions of the SiGe/Si transitions strongly impact bipolar parameters. In this process, the pnp early voltage (VA) is dominated by the ratio of Ge concentration at the collector– base junction to that at the emitter–base junction [26,27]. This limits the flexibility of increasing the Ge concentration at the emitter–base junction to increase gain without seriously impacting VA.

Emitter Modules The key feature of the emitter modules is the npn and pnp interface oxide (IFO) formed at the base surface immediately below the emitter polysilicon. The emitter modules start with a stack of grown/ deposited insulators into which emitter windows are patterned over the base. The thickness and composition of the stack is a tradeoff between patterning control and emitter–base overlap capacitance. The npn emitter openings are first patterned, leaving only a thin oxide film that serves as a screen oxide during the selectively implanted collector (SIC) with the photoresist in place. The SIC profile is tailored to maximize fT while satisfying requirements on impact ionization. A similar process is repeated for pnp emitters and SIC. The most critical step is the emitter surface preparation and interface oxide formation. After removing the thin screen oxide, a controlled IFO is grown over emitters. The interface oxide considerably reduces tunneling of carriers injected from the base into the emitter, resulting in a larger increase in gain and reduction in transistor breakdown voltage. An increase in interface oxide also increases flicker noise. Optimizing the interface oxide thickness offers the flexibility of increasing the gain without degrading the early voltage while minimizing the impact on noise, breakdown, and fT. After depositing a 200-nm polysilicon film over the entire surface, the npn emitters are implanted with arsenic, followed by an anneal step, and the pnp emitters with boron or BF2. The emitter polysilicon is patterned over both transistors.

CMOS Module The CMOS gate-polysilicon, npn base, pnp base, zero-TCR polysilicon resistor, and capacitor plates are patterned simultaneously with focus on controlling the CMOS polysilicon gate-length (LPOLY). A lightly doped drain (LDD) is implanted in NMOS, primarily to ensure adequate channel hot-electron reliability. A nitride film is then deposited, patterned, and directionally etched to form polysilicon-gate sidewall spacers, and also to block silicidation when patterned over selected regions, such as polysilicon resistors. This is followed by conventional masking and implant steps to dope source, drain, gate, and well contacts. The source/drain implants are also introduced into the bipolar base contact regions. Controlling the proximity of base contacts to the corresponding emitters is a critical tradeoff between extrinsic base resistance, VA and transistor breakdown. At close proximity, interactions between dopants can seriously impact the emitter and base profiles in the active region, as also predicted by simulations [28]. The structures are then subjected to a final high-temperature rapid-thermal anneal (RTA). This final anneal is the only high-temperature cycle that the pnp emitter is subjected to.

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Industry Examples at the State-of-the-Art: Texas Instruments

Capacitors Precision, MIM A schematic cross-section of the metal–insulator–metal (MIM) capacitor is shown in Figure 13.2. The capacitor dielectric is oxide (0.7 fF/mm2) or nitride (2 fF/mm2), depending on application. The dielectric is deposited on silicided polysilicon that acts as the bottom capacitor plate, and then covered by a titanium nitride film that, after patterning, serves as the top capacitor plate. Both plates exhibit metallic behavior. The deposition conditions of oxide dielectric and its interfaces with TiN and CoSi2 are optimized to reduce the trap density within the dielectric and its interfaces, reducing transient shifts in capacitance, an effect that is also known as ‘‘dielectric absorption’’ [29]. Stacked Capacitor A high-density capacitor is formed by stacking the MIM capacitor described in the previous section on a capacitor formed between polysilicon and sinker, whereby the gate oxide acts as the dielectric (Figure 13.3). While the voltage coefficient of such a stack is very high compared to that of the MIM capacitor, the capacitance density is increased to near 4.5 fF/mm2 without adding process complexity. Another advantage of the structure is the full isolation of the bottom plate (sinker, well, and buried layer), reducing the parasitic capacitance. When optimizing the sinker profile, it is important to consider the enhanced oxidation rate and oxide integrity as the sinker surface concentration is increased. With this

Capacitor dielectric

TiN, top capacitor plate

Cobalt silicide

Polysilicon

STI

BOX

Support wafer

FIGURE 13.2

Illustration of a precision TiN–oxide–polycide capacitor.

Metal

Contact

Gate oxide

Deposited oxide or nitride

TiN (plate 1)

CMOS gate poly (common plate)

STI

STI

N- or P-sinker (plate 2)

DT

DT NBL or PBL Box

Support wafer

FIGURE 13.3

STI

Schematic cross-section of the stacked capacitor.

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Oxide

Contacting pad Metal 2 NiCrAl thin flim

VIAI

Metal 1 Silicide

BPSG

Contact

FIGURE 13.4

Illustration of thin-film resistor placement. The TFR can also be placed on a planarized surface.

respect, a p-type sinker typically exhibits less enhanced oxidation rate than an n-type sinker, however, at the cost of increased series resistance.

Resistors Three types of precision resistors with sheet resistance ranging from 50 to 320 Ohm/square are available: Polysilicon resistors that are defined during emitter polysilicon patterning, a ‘‘medium-sheet’’ polysilicon resistor tailored to near-zero TCR, and a trimmable thin-film resistor (TFR). Polysilicon Resistors Precision resistors are formed by selectively blocking silicidation of polysilicon. The CMOS polysilicon gate is tailored by selective implantation to 100 Ohm/square and near-zero TCR. The npn and pnp emitter polysilicon films are also utilized to define resistors of near 300 Ohm/square sheet resistance. Silicidation is blocked by patterning the ‘‘sidewall nitride,’’ leaving a patterned nitride film over resistor areas after the directional sidewall etch. Thin-Film Resistor A precision thin-film resistor (TFR) of near 50 Ohm/square is integrated during metallization. The metal modules are standard back-end of the line processes. A laser-trimmable TFR is formed in two masking steps by first depositing an interlevel oxide film, depositing and patterning a thin NiCrAl film, and then patterning contacting pads to the TFR, as shown in Figure 13.4.

13.3

Components and their Characteristics

The components are optimized for 5 V applications. Their key characteristics are summarized in this section.

Bipolars Bipolar transistors are optimized for 5 V, low base resistance, and high b*VA products while maximizing fT. Key bipolar parameters are given in Table 13.2. npn and pnp fT plots are shown in Figure 13.5 and Figure 13.6. The main contributor to the increase in fT is the reduced base width. Decreasing the IFO thickness considerably suppresses noise, as shown in Figure 13.7 where a reduction in flicker noise by approximately one order of magnitude can be seen [30,31].

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Industry Examples at the State-of-the-Art: Texas Instruments TABLE 13.2

Nominal npn and pnp Characteristics, AE ¼ 0.4 0.8 mm2 (258C)

Parameter

Unit

npn

pnp

b VA fTmax (VCE ¼ 5 V) fmax (VCE ¼ 3 V) NFmin BVCEO BVCBO BVEBO

V GHz GHz dB V V V

200 95 27 90 0.7 6.0 13 3.5

140 200 27 60 0.9 6.0 13 3.0

30 25

npn 2

fT (GHz)

20

4

3

Vce = 5 V

1

15 10 5 0 100 JC

FIGURE 13.5 process.

10,000

1000 (µA/µm2)

npn fT for Vce ¼ 1 to 5 V. AE ¼ 0.4 0.8 mm2. Dotted lines: Ref. [23]; solid lines: optimized

30 pnp

Vce = 5 V

25

3

4

2 fT (GHz)

20

1

15 10 5 0 100

1000

10,000

Jc (µA/µm2)

FIGURE 13.6 process.

pnp fT for Vce ¼ 1 to 5 V. AE ¼ 0.4 0.8 mm2. Dotted lines: Ref. [23]; solid lines: optimized

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CMOS Table 13.3 summarizes the CMOS parameters. The values are shown for 5 and 3.3 V with reduced channel length. The CMOS performance meets or exceeds stand-alone 5 V CMOS processes, indicating that performance was not significantly sacrificed during integration into a BiCMOS flow.

Capacitors The MIM capacitor is formed between TiN and polysilicon-silicide, both exhibiting metallic characteristics. Key capacitor parameters are given in Table 13.4. One important property of precision capacitors is the transient drift caused by traps within the dielectric and at its interfaces. This effect manifests itself as a partial recovery of voltage across the capacitor when the terminals are instantaneously shortened. This drift causes errors in analog applications that are based on charging and discharging capacitors, such as sample-and-hold circuits [29]. Silicon dioxide exhibits lower VCC and dielectric absorption (voltage recovery <50 ppm) than silicon nitride, indicating a lower trap density in SiO2. The stack capacitor is partially formed over an n-sinker surface and hence exhibits higher VCC than the MIM capacitor.

Resistors Three types of precision resistors are available: a thin NiCrAl resistor (TFR), polysilicon resistors that are defined during emitter polysilicon patterning, and a medium-sheet resistor tailored to near-zero TCR. Some properties of the thin-film and polysilicon resistors are given in Table 13.5.

TABLE 13.3

Nominal CMOS Characteristics (258C)

Parameter

Unit

Drawn L Linear VT IDSAT Max Isub BVDSS Off current

mm V mA/mm mA/mm V pA/mm

TABLE 13.4

NMOS, 5 V

NMOS, 3.3 V

PMOS, 5 V

PMOS, 3.3 V

0.6 0.75 520 2.0 12 <1

0.5 0.75 590 0.05 12 <1

0.5 0.80 290 0.08 9 <10

0.45 0.80 300 0.0004 12 <10

Capacitor Characteristics (258C)

Type Dielectric thickness Capacitance per unit area Capacitance to support wafer Linear VCC, 1 MHz Quadratic VCC, 1 MHz Linear TCC Quadratic TCC Dielectric BV at 0.1 nA/mm2 Dielectric absorption, k

TABLE 13.5 Type Sheet resistance Linear TCC Quadratic TCC

MIM, SiO2

MIM, Si3N4

Stack SiO2/Si3N4

50 0.70 0.04 4 0.6 10 0.03 >40 <50

30 2.0 0.04 90 50 60 25 >40 1400

30/14 4.5 0.04 3500 500 — — >10 —

Unit nm fF/mm2 fF/mm2 ppm/V ppm/V2 ppm/8C ppm/8C2 V ppm

Resistor Characteristics (258C) TFR

PPOLY

NPOLY

48 25 0

320 40 0.8

100 100 0.6

Unit Ohm/square ppm/8C ppm/8C2

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10−19

S IB (A2/Hz)

10−20 NPN, ref. 23

10−21

NPN, optimized 10−22 10−23 ~1/f

10−24 10−25 100

FIGURE 13.7 noise.

101

103 102 Frequency (Hz)

104

105

Flicker noise comparison of two IFO thicknesses. Decreasing the IFO thickness considerably reduces

Hot spot

Emitter

Deep trench

Top silicon

Buried layer

Box

Heat-flow path

FIGURE 13.8

Simplified model to estimate thermal resistance.

Thermal Resistance Figure 13.8 is a schematic of the bipolar structure illustrating the major heat dissipation paths. Because the thermal conductance is considerably lower in silicon dioxide than in single-crystal silicon (0.014 W/ cm-K in SiO2 versus 1.47 W/cm-K in Si), the effective thermal resistance is strongly affected by the BOX thickness. The insulator film compositions above the structure limit the heat dissipation upward and toward bond-pads. Lateral heat dissipation is limited by the effective deep trench thickness and sidewall area, and balanced by heat transfer from adjacent structures. A simplified analytical spreading resistance model is developed to approximate the effective thermal resistance for DC conditions. The assumption is made that most of the heat dissipation occurs toward the support wafer of infinite dimensions compared to the size of the structure. The model predicts a reduction in thermal resistance by approximately 50% as the BOX thickness is decreased from 0.4 to 0.145 mm. More accurate 2D thermal simulations are in progress. The impact of reduced BOX thickness on self-heating is experimentally observed by tracing the base– emitter forward voltage as a function of collector reverse voltage for a fixed base current (Figure 13.9).

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0.88 0.87

Bulk

0.86 Box: 0.145 µm

Vbe (V)

0.85 0.84

Box: 0.4 µm

0.83 0.82 0.81 0.80 0.79 0.78 0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Vce (V)

FIGURE 13.9 Measurement of Vbe versus Vce at constant collector current showing the impact of BOX thickness on self-heating.

The drop of Vbe with increased power dissipation is a measure of self-heating. An appreciable reduction in self-heating is found when the BOX thickness is reduced from 0.4 to 0.145 mm. Thermal resistance and self-heating are also important considerations for CMOS, passive components, and temperature increase in adjacent structures.

13.4

Circuit Application

The process has been used to fabricate a prototype voltage feedback amplifier with characteristics summarized in Table 13.6 [32]. A simplified amplifier schematic is shown in Figure 13.10. This is a class AB-folded cascode input stage to achieve higher slew rate (lower distortion at higher frequencies) and class AB diamond driver output stage. The improved pnp and npn cutoff frequencies and reduced base resistance and parasitic capacitances increase the frequency of the nondominant poles, allowing a higher small-signal bandwidth (2500 MHz versus 1000 MHz for JI process). The complementary SiGe bipolar technology allows symmetrical architectures with very low distortion. A third-order intermodulation distortion (IMD3) of better than 100 dBc at 60 MHz, 90 dBc at 100 MHz, and 72 dBc at 300 MHz is achieved. These results stem from the complementary SiGe bipolar and the reduction in parasitic capacitances, especially at the high-impedance node of the circuit. Furthermore, the smaller base resistance of the fully dielectrically isolated transistors results in a lower equivalent input noise voltage. Another voltage feedback amplifier implemented on this technology is designed for low noise and included a class AB biased input stage. We p achieved 0.1 dB gain flatness of 500 MHz with an input referred noise of only 1 nV/ Hz in a gain of two. With this process, a unity gain stable general purpose amplifier with 2.6 GHz of bandwidth is achieved for the first time. Such general purpose amplifiers can be used for RF/IF applications with much less power consumption (due to class AB operation) and more flexible external gain setting than currently used class-A RF amplifiers.

13.5

Summary

A fully oxide-isolated 5 V complementary-SiGe BiCMOS technology with MIM capacitors and thin-film resistors has been developed for ultrahigh-speed analog applications. The technology provides high

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Industry Examples at the State-of-the-Art: Texas Instruments TABLE 13.6

Voltage Feedback Amplifier Characteristics

Parameter

Measured

Small-signal bandwidth Gain setting Noise IMD3* at 100 MHz IMD3 at 300MHz

2300 MHz Gain of 5 p 1.9 nV/ Hz 90dBc 72dBc

*IMD3: Third order intermodulation distortion.

VBIAS INP

OUT INN

Class AB Input stage

FIGURE 13.10

Folded cascode

Class AB output stage

Voltage feedback amplifier topology.

b*VA and fT*BVCEO npn and pnp transistors with well-matched characteristics. Passive components of very low voltage and temperature coefficients are realized. This process has been used to build an extremely fast voltage feedback amplifier and is now in production for high-speed analog circuits. It is modularly extendable to higher performance or higher voltage applications. By optimizing the npn and pnp emitter interfaces and base profiles in a complementary 5 V SiGe BiCMOS process, a nominal fT of 27 GHz is achieved for both transistors, and the npn noise is reduced by one order of magnitude. In addition, thinning down the SOI BOX thickness reduces the thermal resistance and self-heating, further improving bipolar parameters. Finally, the reduction in dielectric trap density and hence dielectric absorption in precision capacitors extends the applicability of the process.

Acknowledgments We thank the Freising manufacturing, engineering, characterization, and management teams and the Dallas characterization and modeling teams for their relentless support in completing this project.

References 1. JMC Stork, GL Patton, DL Harame, BS Meyerson, SS IYER, E Ganin, and EF Crabbe. SiGe heterojunction bipolar transistors. Symposium on VLSI Technology, Kyoto 1989, pp. 1–4.

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2. TC Chen, E Ganin, H Stork, B Meyerson, JD Cressler, J Warnock, DL Harame, G Patton, GP Li, CT Chuang, and TH Ning. Submicrometer Si and Si–Ge epitaxial-base double-poly self-aligned bipolar transistors. IEEE Trans. Elect. Dev. 38: 941–943, 1991. 3. E Crabbe, BS Meyerson, JMC Stork, and DL Harame. Vertical profile optimization of very high frequency epitaxial Si- and SiGe-base bipolar transistors. Digest of the IEEE International Electron Devices Meeting, Washington, 1993, pp. 83–86. 4. E Kasper, A Gruhle, and H Kibbel. High speed SiGe-HBT with very low base sheet resistivity. Digest of the IEEE International Electron Devices Meeting, Washington, 1993, pp. 79–81. 5. DL Harame, JH Comfort, JD Cressler, EF Crabbe, JYC Sun, BS Meyerson, and T Tice. Si/SiGe epitaxial-base transistors—Part I: materials, physics and circuits. IEEE Trans. Elect. Dev. 42: 455– 468, 1995. 6. JN Burghartz, JH Comfort, GL Patton, JD Cressler, BS Meyerson, JMC Stork, JYC Sun, G Scilla, J Warnock, BJ Ginsberg, K Jenkins, KY Toh, DL Harame, and SR Mader. Sub-30ps ECL circuits using high-fT Si and SiGe epitaxial base SEEW transistors. Digest of the IEEE International Electron Devices Meeting, San Francisco, 1990, pp. 297–300. 7. TF Meister, H Schaefer, M Franosch, W Molzer, K Aufinger, U Scheler, C Walz, M Stolz, S Boguth, and J Boeck. SiGe base bipolar technology with 74 GHz fmax and 11 ps gate delay. Digest of the IEEE International Electron Devices Meeting, Washington, 1995, pp. 739–742. 8. A Schueppen, U Erben, A Gruhle, H Kibbel, H Schumacher, and U Koening. Enhanced SiGe heterojunction bipolar transistors with 160 GHz–fmax. Digest of the IEEE International Electron Devices Meeting, Washington, 1995, pp. 743–746. 9. JD Cressler. SiGe HBT technology: a new contender for Si-based RF and microwave circuit applications. IEEE Trans. Microwave Theory Tech. 46: 572–589, 1998. 10. M Kondo, K Oda, E Ohue, H Shimamoto, M Tanabe, T Onai, and K Washio. Ultra-low-power and high-speed SiGe base bipolar transistors for wireless telecommunication systems. IEEE Trans. Elect. Dev. 45: 1287–1294, 1998. 11. FS Johnson, J Ai, S Dunn, B El-Kareh, J Erdeljac, S John, K Benaissa, A Bellaour, B Benna, L Hodgson, G Hoffleisch, L Hutter, M Jaumann, R Jumpertz, M mercer, M Nair, J Seitchik, C Shen, M Schiekofer, T Scharnagl, K Schimpf, U Schulz, B Staufer, L Stroth, D Tatman, M Thompson, B Williams, and K Violette. A highly manufacturable 0.25 mm RF technology utilizing a unique SiGe integration. Proceedings of the 1997 IEEE Bipolar/BiCMOS Circuits and Technology, pp. 56–60. 12. J Boeck, H Schaefer, H Knapp, D Zoeschg, K Aufinger, M Wurzer, S Boguth, M Rest, R Schreiter, R Stengl, and TF Meister. Sub 5 ps SiGe bipolar technology. Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 763–766. 13. JS Rieh, B Jaganathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, SJ Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 771–774. 14. M Racanelli, P Ma, and P Kempf. SiGe BiCMOS technology for highly integrated wireless transceivers. Technical Digest of the IEEE GaAs, 2003, pp. 183–186. 15. BA Orner, QZ Liu, B Rainey, A Stricker, P Geis, P gray, M Zierak, M Gordon, D Collins, V Ramachandran, W Hodge, C Willets, A Joseph, J Dunn, JS Rieh, SJ Jeng, E Eld, G Freeman, and D Ahlgren. A 0.13 mm BiCMOS technology featuring a 200/280 GHz (fT/fmax) SiGe HBT. Proceedings of the 2003 IEEE Bipolar/BiCMOS Circuits and Technology, pp. 203–206. 16. LD Lanzerotti, A St Amour, CW Liu, and JC Sturm. Si/Si1–x–y/Gex/Cy heterojunction bipolar transistors. Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 930–932. 17. HJ Osten, D Knoll, B Heinemann, H Ruecker, and B Tillack. Carbon doped SiGe heterojunction bipolar transistors for high frequency applications. Proceedings of the 1999 IEEE Bipolar/BiCMOS Circuits and Technology, pp. 109–116.

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18. D Knoll, B Heinemann, HJ Osten, KE Ehwald, B Tillak, P Schley, R Barth, M Matthes, KS Park, Y Kim, and W Winkler. Si/SiGe:C heterojunction bipolar transistors in an epi-free well, singlepolysilicon technology. Digest of the IEEE International Electron Devices Meeting, San Francisco, 1998, pp. 703–706. 19. DL Harame, JMC Stork, GL Patton, SS Iyer, BS Meyerson, GJ Scilla, EF Crabbe, and E Ganin. High performance Si and SiGe-base PNP transistors. Digest of the IEEE International Electron Devices Meeting, San Francisco, 1988, pp. 889–891. 20. J Warnock, PF Lu, JD Cressler, KA Jenkins, and JYC Sun. 35 GHz/35 PSEC ECL PNP technology. Digest of the IEEE International Electron Devices Meeting, San Francisco, 1990, pp. 301–304. 21. D Nguyen-Ngoc, DL Harame, JN Burghartz, RC McIntosh, EF Crabbe, JD Warnock, CL Stanis, BS Meyerson, JM Cotte, and JH Comfort. Ion-implanted base SiGe PNP self-aligned SEEW transistors. Proceedings of the 1991 IEEE Bipolar/BiCMOS Circuits and Technology, pp. 75–78. 22. B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Grego, U Haak, W Hoeppner, D Knoll, R Kurps, S Marshmeyer, S Orlowski, H Ruecker, P Schley, D Schmidt, R Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. 23. B El-Kareh, S Balster, W Leitz, P Steinmann, H Yasuda, M Corsi, K Dawoodi, C Dirnecker, P Foglietti, A Haeusler, P Menz, M Ramin, T Scharnagl, M Schiekofer, M Schober, U Schulz, L Swanson, D Tatman, M Waitschull, JW Weijtmans, and C Willis. Proceeding of the BCTM, Toulouse, 2003, pp. 211–214. 24. R Jerome, I Post, K Huffstatter, G Wodek, P Travnicek, and D Williams. The effect of trench processing conditions on complementary analog devices with SOI/trench isolation. Technical Digest of the IEEE Bipolar Circuits and Technology Meeting, 1993, pp. 41–44. 25. T-J King, JR Pfiester, and KC Saraswat. A variable-work-function polycrystalline–Si1–xGex gate material for submicron CMOS technologies. IEEE Electron Dev. Lett., EDL-12: 533, 1991. 26. EJ Prinz and JC Sturm. Analytical Modeling of current-gain—Early voltage products in Si/Si1–x /Gex/ Si heterojunction bipolar transistors. Digest of the IEEE International Electron Devices Meeting, Washington, 1991, pp. 853–856. 27. JW Slotboom, G Streutker, A Pruijmboom, and D Gravensteijn. Parasitic energy barriers in SiGe HBT’s. IEEE Trans. Elect. Dev. 12: 486–488, 1991. 28. S Denorme, D Mathiot, P Dollfus, and M Mouis. Two-dimensional modeling of the enhanced diffusion in thin base n-p-n bipolar transistors after lateral ion implantation. IEEE Trans. Elect. Dev. 42: 523–527, 1995. 29. C Iorga, Compartmental analysis of dielectric absorption in capacitors. IEEE Trans. Dielectric Electrical Insulation, 7: 187–192, 2000. 30. JD Cressler, E. Zhao, Georgia Institute of Technology, joint project with Texas Instruments. To be published. 31. F Hou, Texas Instruments, Dallas. Private communication. 32. K Hayat-Dawoodi, Texas Instruments, Dallas. Private Communication.

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14 Industry Examples at the State-of-the-Art: Philips 14.1 14.2

Introduction..................................................................... 14-1 Historical Background .................................................... 14-1 SiGe Pioneering Phase . QUBiC1 through QUBiC4

14.3

SiGe in Manufacturing—QUBiC4G.............................. 14-3 Process Integration . Electrical Results . HBT Models . Circuit Results

Roy Colclaser and Peter Deixler Philips Semiconductors

14.1

14.4

Upgrade to SiGe:C and Monocrystalline Emitters—QUBiC4X....................................................... 14-8

14.5

Summary ........................................................................ 14-14

Process Integration . Electrical Results

Introduction

Significant increases in the operating frequency range of silicon semiconductor devices over the past decade have made low-cost electronic equipment available to the consumers at spectacular performance levels. The development of techniques to make silicon-based heterojunction bipolar transistors (HBTs) using SiGe and, later, SiGe:C, was responsible for great strides forward in bipolar transistor performance. An important way to use HBTs is to combine them with high-performance CMOS and well-characterized passive components in monolithic integrated circuit processes designated BiCMOS. Philips has manufactured RF BiCMOS products in the QUBiC family since 1989. SiGe HBTs were added to the process in 2002 and SiGe:C HBTs were added in 2004.

14.2

Historical Background

Philips Electronics is one of the very few manufacturing companies that made the transition from the vacuum tube era to the semiconductor integrated circuits era in the 1960s. Philips Research Laboratories in Eindhoven, the Netherlands, and, more recently, Leuven, Belgium, have made major contributions to the fundamental understanding of semiconductor materials and device physics. Philips Semiconductors manufactures a variety of integrated circuits using bipolar, MOS, and BiCMOS processes. Radio frequency integrated circuits are a major interest at Philips, and SiGe has become an important area for development.

SiGe Pioneering Phase Within Philips, the task of exploring new and exciting fabrication processes and device structures was assigned to Philips Research Laboratories. From 1988 to 2000, process modules were developed using 14-1

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low-temperature atmospheric and reduced pressure single-wafer epitaxial reactors for both selective and nonselective (differential) epitaxy of SiGe [1–4]. Selective epitaxy deposits as monocrystalline over exposed areas of single-crystal substrates and does not deposit over dielectric regions. Differential epitaxy is monocrystalline over exposed areas of single-crystal substrates and polycrystalline over dielectrics and polycrystalline regions. A team of device architects and process integration specialists worked with device physics experts to develop early versions of HBTs based on molecular beam epitaxy, and both selective and nonselective epitaxial growth [5–10]. Outstanding performance in SiGe HBTs was presented at IEDM in 1995 [7]. In parallel, the model development group extended the MEXTRAM bipolar model to include the parameters necessary to describe SiGe HBTs [11–13].

QUBiC1 through QUBiC4 During the same time span, project teams within Philips Semiconductors developed the QUBiC family of processes for the manufacture of silicon BiCMOS integrated circuits [14–17]. This process family is bipolar based with buried n-type and buried p-type layers, vertical npn and lateral pnp transistors, a selection of monocrystalline and polycrystalline silicon resistors, a variety of capacitor types (including metal–insulator–metal, [MIM], in QUBiC4), varicaps, inductors, and compatibility with a corresponding standard family of CMOS from the Philips roadmap. Key characteristics of the basic silicon QUBiC family are summarized in Table 14.1. The QUBiC4 [17] process evolved from the previous generations. QUBiC1 [14] utilizes fully recessed LOCOS, a single poly bipolar transistor, and three layers of metal. QUBiC2 [15] uses a modified LOCOS, a single poly bipolar transistor, and three layers of metal. The architecture of QUBiC3 [16] is a major change, using conventional LOCOS, separating CMOS and bipolar processing, adding a thick, fourth layer of metal for inductors, and introducing a double poly bipolar transistor with L-shaped oxide or nitride spacers to define the width of the emitter. The base in this device is implanted before the spacers are formed, and the emitter is diffused from polycrystalline silicon that is implanted with arsenic. The major changes for QUBiC4 are associated with isolation. The 0.25 mm CMOS process uses shallowtrench isolation (STI), and this is combined with deep-trench isolation (DTI) to reduce the parasitic capacitances and improve the RF isolation. The npn transistor is modified to use in situ arsenic-doped polycrystalline silicon. A 3 mm thick fifth layer of metal is added to the process to improve the inductors and provide more flexibility for interconnect. The features of this process include a variety of polycrystalline and monocrystalline silicon resistors with sheet resistances ranging from 25 to 2000 ohms/sq., poly–mono capacitors, poly–poly capacitors, and metal–insulator–metal capacitors, lateral pnp bipolar transistors, and varactors using either junctions or MOS capacitors.

TABLE 14.1

The QUBiC Family of Silicon BiCMOS Manufacturing Technologies

Technology

QUBiC1

QUBiC2

QUBiC3

QUBiC4

Lithography (mm) npn fT (GHz) npn fmax (GHz) Substrate isolation CMOS Leff (mm) Metal layers

1.0 13

0.7 20

Fully recessed LOCOS 0.78 3

Partly recessed LOCOS 0.70 3

0.5 30 60 LOCOS 0.42 4

0.25 37 90 STI/DTI 0.14 5/6

Source : P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. With permission.

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14.3

14-3

SiGe in Manufacturing—QUBiC4G

The development of QUBiC4 was well under way when it was decided to introduce a silicon–germanium heterojunction bipolar npn transistor (SiGeHBT) with QUBiC4 as a starting platform. A crossfunctional team was assembled from the research laboratories, product groups, and the manufacturing facilities to implement this development. We were able to reuse much of the work that had already been completed for QUBiC4 in the new project, which was designated QUBiC4G [18]. Many of the process modules could be transferred in total from QUBiC4, a few of the modules required small modifications, and some modules had to be developed specifically for the new process. We selected an architecture that enabled the use of the same set of design rules and layouts for essentially all the important devices, which meant that the databases for mask generation for the large arrays of test structures did not have to be altered. We were able to use algorithms to generate the mask layers in QUBiC4G that were different from those used for QUBiC4 without having to redesign the test structures. In fact, we are able to use the same physical masks for many of the layers, allowing us to mix QUBiC4 and QUBiC4G designs on the same multiproject tape-outs. This is a very cost-effective way to evaluate new test structures at the same time as new product designs. All the outstanding passive components that had been developed for QUBiC4 were easily transferred to QUBiC4G. The only major difference in design rules was due to a request from the design community to increase the thickness of the fourth metal layer from 1 to 2 mm so that lowresistivity orthogonal transmission lines could be implemented in the process.

Process Integration After formation of both n- and p-type buried layers beneath the thin collector epitaxial layer, we apply STI and DTI to significantly reduce the parasitic capacitance. We then complete the standard CMOS integration. The windows defining the active bipolar areas are etched, followed by the implanting of the subcollector doping profile. The high breakdown voltage device is obtained by selectively masking some of the collector implants. Extensive process and device simulations were used to guide the collector and base profile optimization and reduce the number of development cycles. The subcollector implants in QUBiC4 are self-aligned to the emitter opening. In QUBiC4G, we chose to do the subcollector implants before deposition of the base SiGe layer due to the possibility of implant damage to the base layer. At this point, in the process, the base layer of the HBT is deposited using reduced-pressure lowtemperature nonselective epitaxial growth in an ASM CVD reactor. The highly doped boron layer is embedded in a stepped germanium profile without intentional grading [10]. The base layer is monocrystalline over the exposed single-crystal silicon and polycrystalline over the regions that were covered with various dielectric materials. In QUBiC4, the boron-doped base region is implanted into the collector epitaxial layer through an opening in the base polycrystalline silicon and is self-aligned to the opening for the formation of the emitter. In QUBiC4G, the boron-doped portion of the base layer extends across the entire extent of the base, allowing for the formation of low resistance contacts to the extrinsic base region. The emitter in QUBiC4G is formed using a different procedure from QUBiC4 as well. A dielectric layer is deposited over the base layer and patterned, using deep-ultraviolet lithography and an advanced overlay feedback system. This layer serves as an etch stop during the reactive ion etching for the emitter opening to prevent etch damage to the base layer. At this point in the process, we form a similar type of double poly structure with L-shaped inside spacers as in QUBiC4 [16,17]. The technology features in situ arsenic-doped polycrystalline silicon emitters. The mesa-like topography of the HBT structure (Figure 14.1) ensures that the silicide of the base poly and the intrinsic SiGe base are laterally at the same level. Combined with tight alignment, this guarantees that the etch-stop layer does not block the shortest current path from the active base via the highly boron-doped SiGe layer to the silicide of the base electrode. This results in a low base-link resistance and, therefore, low noise figure and high fmax.

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Fabrication of SiGe HBT BiCMOS Technology

FIGURE 14.1 The SiGe-HBT combines robust nonselective epitaxial growth with a double-poly structure and deep- and shallow-trench isolation for high performance in a process based on 0.25 mm lithography. (From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.)

The PMOS source–drain extensions are implanted just before the emitter drive-in anneal. This avoids PMOS degradation during the hydrogen bake cycle before the SiGe layer deposition. The NMOS characteristics are not affected by the limited bipolar thermal cycles due to the SiGe layer deposition and the in situ doped emitter polycrystalline silicon. A tungsten liner is used under each of the first three aluminum–copper layers to enhance the electromigration performance of the interconnect structures. This liner is necessary because of the higher current densities associated with peak fT for the HBT as compared to the npn device in the QUBiC4 process. The top two aluminum–copper metal layers are 2- and 3-mm thick, respectively. These low-resistance interconnect layers facilitate the fabrication of high quality-factor inductors and orthogonal transmission lines. A high-density metal–insulator–metal capacitor is located between the top two metal layers. The back-end structures are planarized using chemical–mechanical polishing and highdensity plasma dielectric layers.

Electrical Results Defining optimum performance parameters for a BiCMOS process is not a straightforward task. The art of device design is an exercise in compromise. A particular parameter may be dominant in one circuit application and superfluous in another. We worked closely with our product design teams to tailor the HBT performance to satisfy the needs for their applications. For instance, there are different requirements for HBTs that are optimized for current mode logic as compared to those optimized for analog RF power amplifiers.

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1⫻100

250

1⫻10−2

200

hFE

IC,IB (A)

150

1⫻10−6 100

1⫻10−8

50

1⫻10−10

Aem = 0.3⫻20.1 µm2

1⫻10−12

0 0.4

0.6 0.8 VBE (V)

1.0

IC,IB (A)

1⫻10−1

1⫻10−4

(a)

1⫻101

1⫻10−3 1⫻10−5 Aem = 1000⫻0.3⫻0.9 µm2

1⫻10−7 0.4 (b)

0.6 0.8 VBE (V)

FIGURE 14.2 (a) Gummel plot of a standard HBT with Aem ¼ 0.3 20.1 mm2 (symbols are measured data and solid lines are simulated using a Mextram model) and (b) Gummel plot of an array of 1000 standard HBTs with Aem ¼ 0.3 0.9 mm2. Both the individual device and the array have near-ideal slopes for the base and collector currents. (From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.)

The Gummel plots in Figure 14.2 show a comparison of a 0.3 20.1 mm2 standard HBT to a typical multiemitter array with 1000 0.3 0.9 mm2 transistors in parallel. Both the collector currents and base currents are near-ideal down to low base–emitter biases. The output characteristics shown in Figure 14.3 exhibit very high Early voltages (>200 V). The standard HBT has a BVCEO of 2.7 V when measured at VBE ¼ 0.65 V, well within the ideal base current regime and before the onset of high injection effects. BVCEO is maintained above the 2.5 V supply voltage set by the digital CMOS logic. The resulting unconditional circuit stability enables circuit design without concerns about breakdown phenomena during power supply transients. The technology also offers HV npn HBTs with a 3.9 V BVCEO for circuit applications where an increased power supply voltage is required. This device type has excellent RF characteristics with fT of 50 GHz and fmax of 110 GHz and complements the standard device with fT of 70 GHz and fmax of 100 GHz. The RF results are shown in Figure 14.4 and Figure 14.5. The measured RF characteristics have near-ideal slopes and high power gains. The fmax values are derived by extrapolation from the measured slopes, which, due to the low CCS and high Rsub, are observed to be always near 20 dB/decade. The minimum-sized HBT (Aem ¼ 0.25 mm2) draws less than 0.6 mA collector current at peak fT ¼ 70 GHz (as shown in Figure 14.4). On this small device, the deep-trench substrate isolation scheme with the low doping level in the substrate reduces the collector–substrate capacitance to less than 2 fF. As seen from Figure 14.3, even the deep-trench isolated HBTs biased near peak fT do not show significant selfheating effects. Basing the process integration on the proven QUBiC4 integration scheme allowed us to preserve characteristics of the 0.25 mm CMOS in QUBiC4G. With only minor implant adjustments, all the QUBiC4G CMOS parameters are closely matched to the parent CMOS technology. This ensures full compatibility with the standard CMOS library. The full suite of passive elements was also carried over from QUBiC4 [17]. The MIM capacitor from this process has a 5 fF/mm2 density based on a Ta2O5 dielectric layer. Only one masking step is added for this component. Two polycrystalline silicon capacitors types are also available. Five resistor types are included in the component list. Other features include varactor diodes, a lateral pnp transistor, and RFCMOS. Spiral inductors with quality factors above 20 at 20 GHz can be fabricated in the 3-mm thick top metal layer. Multilayer inductors using the top two metal layers can also be designed.

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60 50

∆IB = 40 nA

IC (µA)

40 30 20 10 IB = 40 nA 0 (a)

0

0.5

1

1.5

2

2.5

VCE (V) 30

IC (µA)

20 ∆IB = ⫻2

10

IB = 25 µA

0 (b)

0

0.5

1

1.5

2

2.5

VCE (V)

FIGURE 14.3 Output characteristics for the standard HBT (Aem ¼ 0.3 20.1 mm2) at T ¼ 258C biased at low power (a) and near peak fT (b). BVCEO is 2.7 V and VA exceeds 200 V. The solid lines are from Mextram 504 model simulations. (From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.)

Independent high-performance transmission lines can be realized using the two thick top metal layers. This enables the formation of transmission line grids such as those required for the cross-point switch matrix in one of our first products [18,20].

HBT Models By the time the actual development of the QUBiC4G technology was started, there was already a product group ready to start designing. We provided the initial models for the project by doing a process

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80 70

f T [GHz]

60

Std-HBT, BVceo = 2.7 V HV-HBT, BVceo = 3.9 V

50 40 30 20 10 0 0.01

Aem = 0.3⫻20 µm2 VCB = 1 V 0.1

1

10

Jc (mA/µm2)

FIGURE 14.4 Transition frequency as a function of collector current density for the standard and high-voltage HBTs (effective emitter width is 0.3 mm). (From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.)

simulation using TSUPREM4 with the USIT applications module and a device simulation using MEDICI with the HBT module [19]. The first set of Mextram [13] models was made available by placing the QUBiC4G intrinsic transistor in a framework based on measurements of the extrinsic parameters of QUBiC4 transistors. These models were sufficient for the designers to get started, and the first models based on measurements of QUBiC4G material were available before the design was taped out for mask making. The first models were used for circuit prototyping, providing valuable input for the HBT development. In Figure 14.2 and Figure 14.3, the excellent agreement between electrical measurements and the silicon-based scalable Mextram 504 simulations is demonstrated.

Circuit Results 12.5 Gb/sec Asynchronous Cross-Point Switch The first product designed in QUBiC4G is a 20 20 cross-point switch [20] operating at 12.5 Gb/ sec with a peak-to-peak input swing of 100 mV and peak-to-peak output swing of 600 mV. This product has unicast, multicast, and broadcast switching capabilities used for routing data in optical networks. It utilizes the high-speed and low-noise performance of the inherently matched QUBiC4G technology to maintain highly symmetrical rise and fall times and to reduce jitter to less than 2 psec per switching operation. These switches can be cascaded without the need to insert clock–data recovery and retiming logic. The product operates from a 2.5 V supply and consumes less than 4 W. The die area is 36 mm2. LC-VCOs Fully integrated voltage-controlled oscillators based on varactors and spiral inductors have been fabricated in the QUBiC4G process. The measured output spectrum of a 20 GHz LC-VCO [21] is shown in Figure 14.6. The center frequency of this circuit is tunable from 19.8 to 22.7 GHz within a 3 V control range. A measured phase noise of 103 dB c/Hz at 2 MHz from the carrier frequency is achieved. A 35.2 to 37.6 GHz LC-VCO [22] has also been demonstrated.

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60 U (dB) Gmax (dB) h21 (dB)

U, Gmax, h21(dB)

50 40 30 20 10

Std-HBT Aem = 0.3⫻20.1

0 1⫻108

1⫻109

1⫻1010

1⫻1011

f (Hz)

(a)

60 U (dB) Gmax (dB) h21 (dB)

U, Gmax, h21(dB)

50 40 30 20 10

HV-HBT Aem = 0.3⫻20.1

0 1⫻108 (b)

1⫻109

1⫻1010

1⫻1011

f (Hz)

FIGURE 14.5 Measured AC-gains at VCB ¼ 1 V, biased at peak fT, as a function of frequency for (a) the standard HBT and (b) the high-voltage HBT. The fmax values of 100 GHz for the standard device and 110 GHz for the highvoltage device are derived by extrapolation with the measured slope. (From P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.)

14.4 Upgrade to SiGe:C and Monocrystalline Emitters—QUBiC4X The consumer-oriented microwave applications in the 8 to 30 GHz regime require even more RF capabilities than those provided by the QUBiC4G technology. Using the same basic QUBiC4 BiCMOS platform, we are able to substantially improve the RF performance by incorporating a vertically scaled, carbon-enhanced SiGe base, deposited with nonselective epitaxy. We have also replaced the polycrystalline silicon emitter by an epitaxially grown monocrystalline silicon emitter, with significantly lower emitter access resistance. The new process is called QUBiC4X [23]. This technology offers, on the same chip, npns optimized for either ultrahigh speed or high-voltage robustness. Both devices show near-ideal device characteristics combined with excellent RF and low power performance. We also offer a process derivative for power and analog application, featuring dedicated very-high breakdown SiGe:C power transistors.

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Industry Examples at the State-of-the-Art: Philips

10: 33: 14 JUL 17, 2002 hp REF −10 . 0 dB m

MKR 19.832233 GHz −19.30 dB m

# AT 0 dB

PEAK LOG 10 dB/

Center 19.832228 GHz

WA SB SC FS CORR

Center 19.832228 GHz #RES BW 30 KHz

#VBW 300 Hz

Span 2. 000 MHz SWP 667 msec

FIGURE 14.6 Measured output spectrum of a 20 GHz voltage-controlled oscillator at Vtune ¼ 0.5 V implemented in QUBiC4G. (From H Veenstra and E van der Heijden. Proceedings of Conference on European Solid-State Circuits, Lisbon, 2003, pp. 349–352. Figure used by permission of IEEE.)

We elected to stay with the same CMOS for this process development because it satisfies the needs of our product portfolio. The CMOS part of the process flow is relatively independent of the bipolar part, so it would be possible to migrate to more advanced CMOS in the future. We have added the capability to make depletion-mode MOS devices and isolated NMOS transistors to this process flow. RF-CMOS models have been added to the library. The on-chip passive components have also been enhanced for QUBiC4X and characterized over the anticipated frequency range. A SiCr thin-film resistor has been added in the back-end part of the flow and there are now seven silicon resistor styles. The titanium silicide has been replaced by cobalt silicide. New models have also been developed for the inductors [24].

Process Integration The QUBiC4X process is based on the established QUBiC4G technology described in the previous section. The significant process changes are associated with the npn HBT. Carbon has been added to the base layer. The carefully tailored carbon profile enables a thinner base with both a significantly higher boron and germanium content, while maintaining ideal base currents. Base resistance is minimized while ensuring sufficient current gain and good high-frequency noise. The extrinsic base is diffused from the boron-doped base polycrystalline silicon into the SiGe film. This procedure preserves HBT doping profile integrity and minimizes the extrinsic collector junction depth. The parasitic collector–base capacitance and the base-access resistance are both low as a result of this approach. The emitter structure, as in QUBiC4G, is based on L-shaped spacers. The upward expanding emitter electrode width [25] minimizes the emitter resistance on the smallest allowed geometries. This enables us to aggressively scale emitter sizes without any degradation in transition frequency. We have moved

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Fabrication of SiGe HBT BiCMOS Technology

beyond emitters with amorphous silicon and epitaxially aligned polycrystalline silicon to a defect-free epitaxially grown arsenic-doped monocrystalline silicon emitter. This structure is shown in Figure 14.7. Optimized silane-based deposition chemistry, pressure, and temperature in the ASM Epsilon CVD reactor enable growth rates approaching the typical throughput of in situ arsenic-doped polycrystalline silicon emitters. By using an optimized clean in combination with a vacuum load lock, high-temperature hydrogen prebakes are not necessary. We use 0.18-mm lithography for the bipolar and CMOS steps that require tight overlay and line width manufacturing control. We decrease the minimum effective emitter stripe width and place dual rows of contacts at the collector and emitter to ensure reliable npn operation near peak transition frequency. The bipolar modules are combined with the CMOS steps in the same manner as QUBiC4G. The gate patterning and cobalt silicide modules from a 0.18 mm CMOS technology have been introduced. This results in a significant enhancement of the RF CMOS performance and tighter process control. The final rapid thermal anneal has been adjusted to a high-temperature spike to mitigate the traditional thermal budget mismatch between SiGe-HBTs and CMOS. We simultaneously achieve good MOS gate–source–drain activation, MOS transistor matching, minimized npn total base-resistance, and shallow or steep emitter diffusion, aided by the limited diffusivity of the arsenic in the monocrystalline silicon emitter.

FIGURE 14.7 The QUBiC4X HBT combines a nonselective epitaxial SiGe:C base, an epitaxially grown monocrystalline silicon emitter and a double-polycrystalline silicon structure for minimized parasitics and high performance. (From P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE.)

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The back-end integration is tailored to the specific needs of mixed-signal and radio frequency designs. It is based on the QUBiC4G technology, with three layers of thin aluminum–copper with tungsten under-liners and two layers of thick aluminum–copper. We have added a silicon–chromium thin-film resistor with low parasitic capacitance and excellent temperature stability.

Electrical Results The diverse portfolio of highly integrated RF and mixed-signal products demands considerable flexibility of BiCMOS technologies over a wide range of frequencies and voltages. We developed a balanced set of high-speed or high-voltage active devices and well-characterized passive components that will enable the designers to explore the considerable potential of SiGe:C BiCMOS technologies for monolithic microwave applications. A Gummel plot and output characteristics of a 0.15 20.1 mm2 standard SiGe:C npn HBT are shown in Figure 14.8. Both IC and IB are nearly ideal over several orders of magnitude of current while the Early voltage exceeds 50 V. The standard HBT has a collector–emitter breakdown voltage

1⫻100

IC,I B (A)

1⫻10−2 1⫻10−4 1⫻10−6 1⫻10−8 Aem = 0.15⫻20.1µm2

1⫻10−10 0.4

0.8

0.6

1.0

VBE (V)

(a)

IC, (mA)

1.0

0.5

∆/B =230nA

0.0 0 (b)

0.5

1 VCE (V)

1.5

2

FIGURE 14.8 The Gummel plot (a) and output characteristics (b) of a standard HBT with Aem ¼ 0.15 20.1 mm2, showing near-ideal device characteristics. (From P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE.)

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Fabrication of SiGe HBT BiCMOS Technology

1

gm/(q.Ic/kT )

0.8

0.6

0.4 2 Monoemitter: RE = 2.5 Ω µm Polyemitter: RE = 20 Ω µm2

0.2

Identical collector architecture and grown SiGe:C base 0 1⫻10−4

1⫻10−3

1⫻10−2

Jc (A/µm2)

FIGURE 14.9 The epitaxially grown monocrystalline silicon emitter and optimized HBT doping profiles boost the transconductance to increase drive capability, especially near peak fT. (From P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. Proceedings of the Bipolar/ BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE.)

of 2.0 V, measured at VBE ¼ 0.65 V, which is well within the ideal base-current regime and before the onset of high injection effects. The epitaxially grown monocrystalline silicon emitter has an emitter resistivity of 2.5 ohm mm2. This provides a significant boost in the available transconductance per unit current (as shown in Figure 14.9). The transition frequency for the standard HBT is 131 GHz at a relatively low collector current density of 4.4 mA/mm2 (Figure 14.10). The maximum frequency of oscillation for this transistor exceeds 140 GHz. The RF minimum noise figure and associated gain are shown in Figure 14.11. These properties are useful for low-noise amplifiers operating at high frequencies. The output power specifications for many microwave applications require voltage swings in excess of 5 V, demanding devices with high breakdown voltages. Our technology offers a high-voltage HBT with BVCBO ¼ 13 V. The transition frequency for this device is 60 GHz at 1.1 mA/mm2 with BVCEO exceeding 3.2 V and fmax of 120 GHz. The combination of high-performance standard HBTs and high-voltage HBTs will enable the monolithic integration of high-speed circuitry and powerful antenna driver blocks. To successfully address some new applications [26] it is necessary to develop SiGe:C HBTs with even higher breakdown characteristics. We have demonstrated a customized very-high-breakdown version of QUBiC4X targeted for power amplifiers with 5 V power supplies and BiCMOS protection circuitry. The SiGe:C PA transistors have been optimized for high-temperature stability of transition frequency, minimized emitter–base capacitance for increased transition frequency at low currents and high collector–base breakdown voltages. The fT BVCEO and fT BVCBO products are outstanding and exceed 245 and 842 GHz V, respectively. We achieve 88% power-added efficiency with a 20 dB power gain at 1.8 GHz with 3.3 V supply voltage [27]. This combination of high-voltage ruggedness, device speed, and power performance, integrated in BiCMOS, illustrates the potential of silicon-based high-end power amplifiers. The characteristics of the SiGe:C HBT styles available in the QUBiC4X technologies are compared to those in QUBiC4 and QUBiC4G in Table 14.2.

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160 Vbc = −0.5 V

140

Vbc = 0.0 V Vbc = 0.2 V

120

fT (GHz)

100

80

60

40

20

fT and fmax are derived by extrapolation from 50 GHz Aem = 0.15⫻20.3 µm2

0 0.0001

0.001 Jc (A/µm2)

0.01

2.5

2.5

2.0

2.0

1.5

1.5

1.0

1.0 NFMIN (dB) 0.5

0.5 0.0

Gass (dB)

Fmin (dB)

FIGURE 14.10 The transition frequency as a function of collector current density for the QUBiC4X standard HBT. Only VBE ¼ 0.81 V and IC ¼ 4 mA/mm2 are required to reach 130 GHz fT. (From P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. Proceedings of the Bipolar/ BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE.)

Aem = 0.15⫻20.3 0

µm2

Gass (dB)

5 10 15 Frequency (GHz)

0.0 20

FIGURE 14.11 The NFMIN and associated gain for the QUBiC4X standard HBT is 0.4 dB at 2 GHz and 1.1 dB at 10 GHz. This is a result of the minimized parasitic capacitances and access resistances. (From P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE.)

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Fabrication of SiGe HBT BiCMOS Technology

TABLE 14.2 Electrical Results Obtained for the Standard HBT, the High-Voltage HBT and the Power Amp HBT (at Room Temperature for Aem ¼ 0.15 20.1 mm2) from the QUBiC4X Process Options [23] as Compared to the Standard and High-Voltage Devices from QUBiC4 [17] and QUBiC4G Parameters

QUBiC4 [17]

fT at VCB ¼ 0.5 fmax IC at peak fT hfe BVCEO BVCBO VA Rpinch REAE CCB/AE CCS/PCollector NFMIN at 2 GHz NFMIN at 10 GHz

QUBiC4G [18]

QUBiC4X [23]

Units

Std BT

HV BT

Std HBT

HV HBT

Std HBT

HV HBT

PA HBT

37 90 0.75 150 3.8 16 27 12 22 2.7 1.5

28 70 0.5 140 5.9 18 50 12 22 2.1 1.5

67 90 1.65 300 2.5 10.0 150 4 22 4.0 2.1

50 90 0.83 300 3.6 14.0 220 4 22 3.3 2.1

131 138 4.4 600 2.0 9.0 50 2.8 2.5 7.0 0.22 0.4 1.1

60 120 1.1 600 3.1 13.0 80 2.8 2.5 3.2 0.22

51 115 0.8 160 4.8 16.5 >250 3.2 20 3.0 0.22

GHz GHz mA/mm2 — V V V kohm/sq. ohm mm2 fF/mm2 fF/mm dB dB

Source : P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE.

14.5

Summary

Philips has a long history in bipolar-based BiCMOS for RF applications. The QUBiC family has evolved through the years with a suite of well-characterized passive components that provide the designers with all they need to make fully integrated products for the consumer market. When a SiGe HBT replaced the silicon bipolar npn in QUBiC4G, a new frequency range was added to the process capabilities. The enhancement of this HBT by the addition of carbon to the HBT in QUBiC4X opens another set of applications to the silicon-based BiCMOS product arena. The remarkable improvements in SiGe:C HBTs make it possible to manufacture products at low cost that previously could only be made using III–V compound semiconductors. Modeling of both active and passive components had to keep pace with these developments in the technology, making it possible to supply the designers with the tools that are needed to make leading edge designs when the technologies are available.

Acknowledgments The authors acknowledge the teamwork within the Philips organization that made it possible for the development of the QUBiC family of process technologies and the incorporation of SiGe and SiGe:C HBTs in production. We thank the teams at Philips Research in Eindhoven and Leuven, Philips Semiconductors Technology Development in Sunnyvale, Albuquerque, Fishkill, San Jose, Nijmegen, Caen and Crolles, and Philips Semiconductors Product Design in Caen, Nijmegen, and San Jose, for all their efforts on these projects.

References 1. WB de Boer and DJ Meyer. Low-temperature chemical vapor deposition of epitaxial Si and SiGe layers at atmospheric pressure. Applied Physics Letters 58:1286–1288, 1991. 2. WB de Boer, D Terpstra, and JGM van Berkum. Selective versus non-selective growth of Si and SiGe. Materials Science and Engineering B 67:46–52, 1999.

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Industry Examples at the State-of-the-Art: Philips

14-15

3. WB de Boer and D Terpstra. Emissivity effects in low-temperature epitaxial growth of Si and SiGe. Proceedings ECS Spring Meeting, Seattle, 1999, pp. 309–318(99–10). 4. E Aksen, WB de Boer, and D Terpstra. Emissivity effects in differential epitaxial growth (DEG). Proceedings ECS Spring Meeting, Washington, 2001, Abstract No. 558(2001–1). 5. A Pruijmboom, JW Slotboom, DJ Gravesteijn, CW Fredriksz, AA van Gorkum, RA van de Heuvel, JML van Rooij-Mulder, G. Streutker, and GFA van de Walle. Heterojunction bipolar transistors with SiGe base grown by molecular beam epitaxy. Electron Device Letters 12:357–359, 1991. 6. JW Slotboom, GFA Streutker, and A Pruijmboom. Parasitic energy barriers in SiGe HBTs. Electron Device Letters 12:486–488, 1991. 7. A Pruijmboom, D Terpstra, CE Timmering. WB de Boer, MJJ Theunissen, JW Slotboom, RJE Hueting, and JJEW Hageraats. Selective-epitaxial base technology with 14 ps ECL-gate delay, for low power wide-band communication systems. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1995, pp. 747–750. 8. RJE Hueting, JW Slotboom, A Pruijmboom, WB de Boer, CE Timmering, and NEB Cowern. On the optimization of SiGe-base bipolar transistors. IEEE Transactions on Electron Devices 43:1518–1524, 1996. 9. MS Peter, JW Slotboom, and D Terpstra. Impact ionization and neutral base recombination in SiGe HBTs. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2000, pp. 126–129. 10. P Deixler, HGA Huizing, JJTM Donkers, JH Klootwijk, D Hartskeerl, WB de Boer, RJ Havens, R van der Toorn, JCJ Paasschens, WJ Kloosterman, JGM van Berkum, D Terpstra, and JW Slotboom. Explorations for high performance SiGe-heterojunction bipolar transistor integration. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 30–33. 11. JCJ Paasschens, WJ Kloosterman, and RJ Havens. Modeling two SiGe HBT specific features for circuit simulation. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 38–41. 12. JCJ Paasschens, WJ Kloosterman, RJ Havens, and HC de Graaff. Improved compact modeling of output conductance and cutoff frequency of bipolar transistors. IEEE Journal of Solid-State Circuits 36:1390–1398, 2001. 13. Mextram Models, Level 504. www.semiconductors.philips.com/Philips_Models/bipolar/mextram/ index.html. 14. JL de Jong, R Lane, B van Schravendijk, and G Conner. Single polycrystalline silicon layer advanced super high-speed BiCMOS technology. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1989, pp. 182–185. 15. B van Schravendijk, JL de Jong, P van Wijnen, and G Conner. QUBiC2: BiCMOS technology for 17 GHz bipolar and 0.5 mm CMOS. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1990, pp. 158–161. 16. A Pruijmboom, D Szmyd, R Brock, R Wall, N Morris, K Fong, and F Jovenin. QUBiC3: A 0.5 mm BiCMOS production technology, with fT ¼ 30 GHz, fmax ¼ 60 GHz and high-quality passive components for wireless telecommunication applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1998, pp. 120–123. 17. D Szmyd, R Brock, N Bell, S Harker, G Patrizi, J Fraser, and R Dondero. QUBiC4: a silicon RFBiCMOS technology for wireless communication ICs. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 60–63. 18. P Deixler, R Colclaser, D Bower, N Bell, W de Boer, D Szmyd, S Bardy, W Wilbanks, P Barre, M van Houdt, JCJ Paasschens, H Veenstra, Eric van der Heijden, JJTM Donkers, and JW Slotboom. QUBiC4G: a fT/fmax ¼ 70/100 GHz 0.25 mm low power SiGe-BiCMOS production technology with high quality passives for 12.5 Gb/s optical networking and emerging wireless applications up to 20 GHz. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Monterey, 2002, pp. 126–129. Figures used by permission of IEEE. 19. Synopsis markets TSUPREM4 and MEDICI. www.synopsis.com.

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Fabrication of SiGe HBT BiCMOS Technology

20. H Veenstra, P Barre, E van der Heijden, D van Goor, N Lecacheur, B Fahs, G Gloaguen, S Clamagirand, and O Burg. A 20-input 20-output 12.5 Gb/s SiGe cross-point switch with less than 2 ps RMS jitter. Digest of the Technical Papers, IEEE International Solid State Circuits Conference, San Francisco, 2003, pp. 174–176. 21. H Veenstra and E van der Heijden. A 19–23 GHz integrated LC-VCO in a production 70 GHz fT SiGe technology. Proceedings of Conference on European Solid-State Circuits, Lisbon, 2003, pp. 349–352. Figure used by permission of IEEE. 22. H Veenstra and E van der Heijden. A 35.2–37.6 GHz LC VCO in a 70/100 GHz fT/fmax SiGe Technology. Digest of the Technical Papers, IEEE International Solid State Circuits Conference, San Francisco, 2004. 23. P Deixler, A Rodriguez, H Sun, R Colclaser, W de Boer, D Bower, N Bell, A Yao, R Brock, Y Bouttement, GAM Hurkx, LF Tiemeijer, HGA Huizing, JCJ Paasschens, D Haartskerl, P Agarwal, PHC Magnee, E Aksen, and JW Slotboom. QUBiC4X: a fT/fmax ¼ 130/140 GHz SiGe:C-BiCMOS manufacturing technology with elite passives for emerging microwave applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 233–236. Figures used by permission of IEEE. 24. LF Tiemeijer, RJ Havens, R de Kort, Y Bouttement, P Deixler, and M Ryczek. Predictive spiral inductor compact model for frequency and time domain. Technical Digest of the International Electron Devices Meeting, Washington, 2003, pp. 875–878. 25. K Washio, E Ohue, R Hayami, A Kodama, H Shimamoto, M Miura, K Oda, I Suzumara, T Tominari, and T Hashimoto. High-speed scaled-down self-aligned SEG SiGe HBTs. IEEE Transactions on Electron Devices 50:2417–2424, 2003. 26. K Nellis and P Zampardi. A comparison of bipolar technologies for linear handset power amplifier applications. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 3–6. 27. DMH Hartskeerl, HGA Huizing, P Deixler, W van Noort, and PHC Magnee. High performance SiGeC HBT integrated into a 0.25 mm BiCMOS technology featuring record 88% power-added efficiency. International Microwave Symposium, Fort Worth, 2004.

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A.1 Properties of Silicon and Germanium

John D. Cressler Georgia Institute of Technology

The energy band structures of Si and Ge are depicted in Figure A.1.1, together with (1) their carrier effective mass parameters (Table A.1.1) and (2) their bulk structural, mechanical, optical, and electrical properties (Table A.1.2) [1–3].

Si

2

Ec

2

3

3

Ge

Eg

−1

Energy (eV) 0 1

1 0

Eg

−1

Energy (eV)

Ec

−2

Ev

L

[111]

Γ

[100]

X

−3

−3

−2

Ev

L

[111]

Γ

[100]

X

FIGURE A.1.1 Energy band structure, showing the principal conduction and valence bands of Si and Ge as a function of k-space direction. (From M Shur. Physics of Semiconductor Devices. Englewood Cliffs, NJ: Prentice-Hall, 1990. With permission.)

A.1-1

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A.1-2

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Fabrication of SiGe HBT BiCMOS Technology

TABLE A.1.1

Carrier Effective Mass Parameters for Si and Ge

Parameter

Units

Effective electron mass (m n*) Longitudinal (4.2 K) Transverse (4.2 K) Density-of-states (4.2 K) Density-of-states (300 K)

(m o)

Effective hole mass (m p*) Heavy hole (4.2 K) Light hole (4.2 K) Density-of-states (4.2 K) Density-of-states (300 K)

(m o)

TABLE A.1.2

Silicon

Germanium

0.9163 0.1905 1.062 1.090

1.58 0.082 — —

0.537 0.153 0.59 1.15

0.28 0.044 — —

Properties of Bulk Si and Ge

Parameter

Units

Silicon

Germanium

Atomic number Atomic density Atomic weight Density Electronic orbital configuration Crystal structure Lattice constant (298 K) Dielectric constant Breakdown strength Electron affinity Specific heat Melting point Intrinsic Debye length (300 K) Index of refraction Transparency region Thermal conductivity (300 K) Thermal expansion coefficient (300 K) Young’s modulus Energy bandgap (low doping)

— (atoms/cm3) (g/mole) (g/cm3) — — (A˚) — (V/cm) (V) (J/g-8C) (8C) (mm) — (mm) (W/cm-8C) (8C 1) (dyne/cm2) (eV)

Equivalent conduction band minima Effective electron mass (300 K) Effective hole mass (300 K) Intrinsic carrier density (300 K) Effective conduction band DoS (300 K) Effective valence band DoS (300 K) Electron mobility (300 K) Hole mobility (300 K) Electron diffusivity (300 K) Hole diffusivity (300 K) Optical phonon energy Phonon mean free path length Intrinsic resistivity (300 K)

— (mo) (mo) (cm 3) (cm 3) (cm 3) (cm2/V-sec) (cm2/V-sec) (cm2/sec) (cm2/sec) (meV) A˚

14 5.021022 28.09 2.329 (Ne) 3s23p2 Diamond 5.43107 11.7 3105 4.05 0.7 1412 24 3.42 1.1–6.5 1.31 2.610 6 1.91012 1.12 (300 K) 1.17 (77 K) 6 1.18 0.81 1.021010 2.81019 1.041019 1450 500 37.5 13 63 76 3.16105

32 4.421022 72.6 5.323 (Ar) 3d104s24p2 Diamond 5.65791 16.2 1105 4.00 0.31 1240 0.68 3.98 1.8–15 0.60 5.910 6 — 0.664 (291 K) 0.741 (4.2 K) 8 — — 2.331013 1.041019 6.001018 3900 1900 100 49 37 105 47.62

(V cm)

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Properties of Silicon and Germanium

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A.1-3

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 2. M Shur. Physics of Semiconductor Devices. Englewood Cliffs, NJ: Prentice-Hall, 1990. 3. R Hull, editor. Properties of Crystalline Silicon. London: EMIS Datareviews Series, Number 20, INPSEC, 1999.

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Cressler/Fabrication of SiGe HBT BiCMOS Technology

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16.10.2007 6:43pm Compositor Name: VBalamugundan

A.2 The Generalized Moll–Ross Relations

John D. Cressler Georgia Institute of Technology

The classical solution for the collector current density in a Si BJT, derived by Shockley, necessarily assumes a constant base doping profile. In this case, for low-injection conditions, the drift component of the minority carrier transport equation can be neglected, and the minority carrier diffusion equation solved under the Shockley boundary conditions. The resultant equation, under the assumptions of negligible neutral base recombination and forward-active bias, is the well-known expression JC ¼

qDnb 2 DEgbapp =kT qVBE =kT n e e 1 : io W Nab b

(A:2:1)

2 Here, Dnb is the minority electron diffusivity, Nab is the ionized base doping level, nio is the low-doping intrinsic carrier density, given by,

n2io ¼ NC NV eEgo =kT ,

(A:2:2)

and DEgbapp is the heavy-doping induced bandgap narrowing. The path to the generalization of this result to the ‘‘real-world’’ case of a nonconstant base doping profile (Figure A.2.1) is nonobvious, and even a cursory glance at the problem is enough to convince one that it cannot follow the original path in Shockley’s approach. The complexity of this problem results from the addition of the field-driven transport, which is now no longer negligible due to the dopinggradient-induced field. The clever solution to this problem was first presented in the classic paper by Moll and Ross in 1956, the so-called ‘‘Moll–Ross relation’’ [1]. Unfortunately, that solution made two undesirable assumptions: (1) that the minority electron mobility (hence, diffusivity) is constant across the quasineutral base and (2) that the intrinsic carrier density is constant across the quasineutral base. The latter assumption, in particular, fails in the presence of a heavily doped base (i.e., real life), since the apparent bandgap narrowing is inherently position dependent across the base, and hence the effective bandgap in the base is also position dependent.* In essence, then, the problem becomes one of solving for the collector current density in the presence of both nonconstant base doping and nonconstant base bandgap, and is particularly relevant to the graded-base SiGe HBT. This problem remained unsolved for *In fairness, Moll and Ross cannot be blamed for the second assumption since doping-induced bandgap narrowing had not yet been discovered.

A.2-1

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A.2-2

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Fabrication of SiGe HBT BiCMOS Technology

Nab−(x)

Space charge n+

n−

p Wb

0 E

x C

B

FIGURE A.2.1 Schematic nonconstant base doping profile used in the derivations.

almost 30 years until the seminal paper by Kroemer in 1985 [2]. Since Kroemer’s ‘‘generalized Moll–Ross relations’’ are the starting point for both the dc and ac analysis of the graded-base SiGe HBT (Chapter 4, see Silicon Heterostructure Devices), we present that elegant derivation here (showing all of the mathematical steps that Kroemer neglected to include in his paper). The assumptions in Kroemer’s solution include: (1) 1-D transport, (2) transport by both drift and (x) for all x across the base), (4) negligible diffusion, (3) low-injection conditions (i.e., nb(x) Nab neutral base recombination, and (5) forward-active bias. Importantly, however, there are no assumptions on the position dependence of the base doping profile or the base bandgap.* We begin from the generalized drift–diffusion minority electron transport equation, as expressed in terms of the minority electron quasi-Fermi potential Jn ¼ qmn nrfn ,

(A:2:3)

which for our 1-D Si BJT problem reduces to JC ¼ qmnb (x)nb (x)

dfn (x) : dx

(A:2:4)

In the quasineutral base, the majority carrier (hole) quasi-Fermi potential (fp) in low-injection is constant, such that JC ¼ qmnb (x)nb (x)

d fn (x) fp , dx

(A:2:5)

and from the generalized Shockley boundary condition nb (x)pb (x) ¼ n2ib (x)eq(fn (x)fp )=kT ,

(A:2:6)

kT nb (x)pb (x) ln ¼ fn (x) fp : q n2ib (x)

(A:2:7)

which can be rewritten as

*Interestingly, additional generalizations to Kroemer’s result have been recently offered [3]. Let it never be said that the final word in device physics is ever in.

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The Generalized Moll–Ross Relations

A.2-3

Taking the derivative of both sides we have kT q

n2ib (x) d nb (x)pb (x) d ¼ f (x) f p : nb (x)pb (x) dx n2ib (x) dx n

(A:2:8)

Substituting this result back into Equation A.2.5, we obtain kT n2ib (x) d nb (x)pb (x) JC ¼ qmnb (x)nb (x) q nb (x)pb (x) dx n2ib (x)

(A:2:9)

We now integrate this expression from some arbitrary point in the base profile to the neutral base boundary (Wb) to obtain ð Wb x

JC pb (x 0 ) 0 nb (x 0 )pb (x 0 )Wb dx ¼ n2ib (x 0 ) x qDnb (x 0 ) n2ib (x 0 )

(A:2:10)

Under the assumptions of negligible neutral base recombination (i.e., JC is a constant to the integration), and using the fact that in forward-active bias, pb (Wb )nb (Wb ) ’ n2ib (Wb )

(A:2:11)

pb (x 0 )dx 0 nb (x)pb (x) ¼1 n2ib (x) Dnb (x 0 )n2ib (x 0 )

(A:2:12)

we find JC q

ð Wb x

At the emitter–base boundary (x ¼ 0), we know from the generalized Shockley boundary condition that nb (0)pb (0) ¼ n2ib (0)eq(fn (0)fp (0) )=kT ,

(A:2:13)

fn (0) fp (0) ¼ VBE ,

(A:2:14)

pb (x)dx ¼ 1 e qVBE =kT , Dnb (x)n2ib (x)

(A:2:15)

and

so that we obtain JC q

ð Wb 0

and thus finally, q(e qVBE =kT 1) , JC ¼ W Ð b pb (x)dx 2 0 Dnb (x)nib (x)

(A:2:16)

This is the ‘‘generalized Moll–Ross relation’’* for the collector current density in a bipolar transistor with nonconstant base doping and arbitrary position-dependence of the base bandgap. Observe that if *I personally would have no problem calling this elegant result the ‘‘Kroemer relation.’’

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A.2-4

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Fabrication of SiGe HBT BiCMOS Technology

we allow pb (x) ¼ Nab (x) ¼ Nab ¼ constant, then we obtain Equation A.2.1, as expected (the extra negative sign simply accounts for the fact that the electron flow is in the opposite direction of the positive current flow). As detailed in Chapter 4 (see Silicon Heterostructure Devices), this fundamental result is the starting point of the derivations for collector current density, the current gain, and the output conductance in a graded-base SiGe HBT. In this case, in addition to the bandgap-narrowing-induced position dependence in the base bandgap, we have an additional contribution from the Ge-strained layer (Figure A.2.2). This 2 in Equation A.2.16. For more Ge contribution easily enters the generalized Moll–Ross relation via nib detail on the resultant derivations and the assumptions and approximations involved, the reader is referred to Ref. [4]. An additional desirable feature of Kroemer’s approach is that we can also easily obtain an analytical expression for the base transit time in a device with nonconstant base doping and bandgap. Under a quasistatic assumption we can generally define the base transit time as

q tb ¼ JC

W ðb

nb (x)dx:

(A:2:17)

0

From Equation A.2.12 and neglecting the unity factor, we can solve for nb (x) as

nb (x) ¼

JC n2ib (x) q pb (x)

W ðb x

pb (x 0 )dx 0 Dnb (x 0 )n2ib (x 0 )

(A:2:18)

Substituting this result into Equation A.2.17, we finally obtain

tb ¼

ð Wb 0

8W 9 ðb n2ib (x) < pb (y)dy = dx pb (x) : Dnb (y)n2ib (y);

(A:2:19)

x

Again, observe that if we allow pb(x) ¼ Nab (x) ¼ Nab ¼ constant, we obtain the classical result for a BJT with constant base doping

tb ¼

Wb2 , 2Dnb

(A:2:20)

Ge

Space charge

_ n+

Wb

0 E

n−

p B

x C

FIGURE A.2.2 Schematic drawing of a position-dependent, graded Ge base profile in a SiGe HBT.

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The Generalized Moll–Ross Relations

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A.2-5

as expected. This second generalized Moll–Ross relation is the starting point for the derivation of base transit in a graded-base SiGe HBT (Figure A.2.2), as detailed in Chapter 4 (see Silicon Heterostructure Devices) and Ref. [4].

References 1. J Moll and I Ross. The dependence of transistor parameters on the distribution of base layer resistivity. Proceedings of the Institute of Radio Engineers 44:72, 1956. 2. H Kroemer. Two integral relations pertaining to electron transport through a bipolar transistor with a nonuniform energy gap in the base region. Solid-State Electronics 28:1101–1103, 1985. 3. SN Mohammad. Generalization of the Moll–Ross relations for heterojunction bipolar transistors. Solid-State Electronics 46:589–591, 2002. 4. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003.

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Cressler/Fabrication of SiGe HBT BiCMOS Technology

66870_A003 Final Proof

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5.11.2007 12:04pm Compositor Name: JGanesan

A.3 Integral ChargeControl Relations A.3.1 A.3.2 A.3.3 A.3.4

Introduction ................................................................. Derivation of a General Relationship ........................ Homojunction Transistors .......................................... Heterojunction Transistors .........................................

A.3-1 A.3-2 A.3-6 A.3-9

Box Ge Profile in the (Metallurgical) Base Region . Trapezoidal Profile in the (Metallurgical) Base Region

Michael Schro¨ter University of California at San Diego

A.3.1

A.3.5 A.3.6

Further Extensions..................................................... A.3-12 Summary .................................................................... A.3-13

Introduction

One of the most important requirements for compact models is an accurate description of the devices’ main current. In an npn bipolar transistor, this is the (generally time dependent) collector current iC which is given by the transport of electrons from emitter to collector. For time (and frequency) dependent quasistatic (q.s.) operation, which is the case in the vast majority of practical applications, the current flowing at the collector terminal can be partitioned into a q.s. transfer current iT and a charging current supplying all charge storage elements connected to the collector terminal. Since the latter elements are described and represented separately in a model, a formulation of iT, which equals IC under d.c. conditions, is of major interest. Before a general relation for iT is derived, a brief historical perspective of the respective theory is given below. The obvious starting point for such an equation is the transport and continuity equation. Since the time derivative term in the latter is taken into account separately by the charge storage elements, and the impact of recombination on iT in modern bipolar transistors is negligibly small, a spatially constant electron current density jnx results (and is observed in device simulation) throughout the structure of a one-dimensional (1D) transistor. This fact can be used to solve the transport equation first for the carrier density and associated charge at a given transfer current, and then reformulate the result to obtain the transfer current at a given charge. The first solution of this kind was published by Moll and Ross in 1956 [1, Equation (13)], exp (V 0 0 =VT ) iT ¼ qmnB n2iB VT R x u B E x l h(x)p(x)dx

(A:3:1)

with p(x) ¼ NB(x), h(x) ¼ 1, VB0 E0 as internal base–emitter voltage, and [xl, xu] as base region. The relation provided a great deal of insight into the dependence of iT (and also the transit time) on doping profile and material parameters in the base region. An improved and more complete expression was later used for one of the first TCAD papers by Ghosh et al. in 1967 [2]. Here, the 2 ) / (mnni2) was included for the first time, but the integral material dependent function h(x) ¼ (mnBniB A.3-1

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A.3-2

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Fabrication of SiGe HBT BiCMOS Technology

was evaluated numerically, thus not providing a formulation suitable for compact modeling. Only shortly thereafter, in 1970 Gummel published his well-known paper about the integral charge-control relation (ICCR) [3]. For the first time, a compact formulation for iT was derived, that contained in a consistent relation between iT and stored charge and with all bias-dependent nonideal effects that were relevant for transistors at that time. In one way or the other, the ICCR has been used until today in any reasonably physics-based compact model. Note that the Scharfetter–Gummel discretization, which was first published and applied to a bipolar transistor, also assumes a constant current density between discrete points, which is the main reason for its numerical stability and wide use for device simulation. An extension of the Moll–Ross relation with special emphasis on a spatially variable bandgap in the base layer was derived by Kroemer in 1985 [4]. Here also the doping density was replaced by the biasdependent hole density as in Equation A.3.1, but no equation suitable for compact modeling was given. In 1993, for both the latter equation and the ICCR a generalization was presented in Ref. [5], with application to compact modeling. The respective generalized ICCR (GICCR) will be discussed in more detail in subsequent sections. During its derivation, the various results mentioned above will be obtained and be referred to again. Since the theories above all apply only to a 1D transistor structure with reasonably smooth material and bandgap changes, and to quasistatic operation, extensions for practical cases are of interest, which will be briefly discussed in A.3.5. The considerations in this chapter apply to Si and SiGe technologies. In the latter, two fundamentally different types of doping profiles can be distinguished which are presently being manufactured and illustrated schematically in Figure A.3.1. The conventional emitter doping (CED) type has a similar profile shape as BJTs, but contains in addition a Ge distribution that increases from the BE junction to the BC junction. In contrast, the low-emitter concentration (LEC) type contains a box Ge profile (or at least a sufficiently high step at the BE junction) that allows to significantly increase the base doping and to lower the emitter doping.

A.3.2

Derivation of a General Relationship

Although the GICCR can be derived for the 3D case, the considerations here will be restricted to the 1D case in order to demonstrate the concept. The assumptions required for the derivation are summarized below: (a) A one-dimensional transistor structure (cf. Figure A.3.1) is considered, with the emitter contact (x ¼ 0) at the mono-silicon surface and the collector contact (x ¼ xC) at the transition from the lightly-doped collector region to the buried layer. This 1D structure does not include the emitter and external collector series resistance. (b) Volume recombination within the above 1D transistor region is negligible. (c) The time derivative is negligible, which corresponds to quasistatic operation. (d) Effects such as thermionic emission and tunneling across the junctions are neglected. They can be accounted for though by separate terms and can be combined with the GICCR solution. Assumptions (a), (b), and (c) together with the electron continuity equation lead to a spatially independent electron current density, Jn ¼ const(x) ¼ JT ¼

IT , AE

(A:3:2)

which can be expressed by the transfer current and area (emitter) AE of the 1D-transistor. The derivation starts with the electron transport equation,

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A.3-3

Integral Charge-Control Relations

0 xe0

N

NE

N

xc0 Wbm

x⬘

mx mGe

NB

NB mGe mp NC

0

xjC

xjE

NC

NE

xC x

xjC

xjE

0

(a)

xC

x

(b)

FIGURE A.3.1 Sketch of doping and Ge profiles for (a) CED transistors and (b) LEC transistors.

Jn ¼ qmn n

dwn dx

(A:3:3)

where mn, n and wn are the electron mobility, density, and quasifermi potential. Inserting n ¼ ni exp[(c wn) / VT] into (A.3.3) gives c wn dfn exp : Jn ¼ qmn ni exp VT VT dx

(A:3:4)

Note that the effective intrinsic carrier density ni accounts for bandgap differences caused by highdoping effects and bandgap-engineering. This topic will be discussed later. Using the transformation d exp (wn =VT ) 1 w dwn ¼ exp n dx VT VT dx

(A:3:5)

c d exp (wn =VT ) Jn ¼ qVT mn ni exp : VT dx

(A:3:6)

leads to

Separation of the differential variables and rearranging terms gives Jn c w exp dx ¼ d exp n : VT qVT mn ni VT

(A:3:7)

Extension of the l.h.s. by the product ni exp(wp/VT) allows to replace the inconvenient term exp(c/VT) by the hole density, yielding Jn p wn dx ¼ d exp : qVT mn n2i exp (wp =VT ) VT Integration of the above equation over the general spatial interval [xl, xu] gives

(A:3:8)

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A.3-4

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Fabrication of SiGe HBT BiCMOS Technology

xðu xl

Jn exp (wp =VT ) p dx ¼ qVT mn n2i

exp (wnð (xu )=VT )

w d exp n : VT

(A:3:9)

exp (wn (xl )=VT )

The result for the r.h.s. is exp (wnð (xu )=VT )

w w (xu ) w (xl ) ¼ exp n exp n : d exp n VT VT VT

(A:3:10)

exp (wn (xl )=VT )

The exact value of wn on the r.h.s. depends on the choice of the integration limits and will be discussed later. First though, the left-hand-side of (A.3.9) is integrated, xðu xl

Jn exp (wp =VT ) JT exp (VB0 E0 =VT ) p dx ¼ 2 qVT mnr n2ir qVT mn ni

xðu

h(x)p(x)dx,

(A:3:11)

xl

with h ¼ hghihw as the normalized weighting function of the hole density, and its components hg ¼

mnr n2ir , mn (x)n2i (x)

hi ¼

Jn (x) , JT

VB0 E0 wp (x) : hw ¼ exp VT

(A:3:12)

mnr and nir are the mobility and intrinsic carrier density, respectively, of a reference material. Equating (A.3.10) with (A.3.11), and solving for the desired transfer current yields the ‘‘master’’ equation h i exp VVB0TE0 exp wnV(xT l ) exp wnV(xT u ) Ð xu JT ¼ qVT2 mnr n2ir , x l hg hi hw pdx

(A:3:13)

from which different analytical formulations can be derived. The choice of the reference material (or transistor region) and its associated values for mnr n2ir is arbitrary and will be discussed later. The integration interval is undefined yet, and so is the impact of the various weighting functions on the integral. An attractive choice for the integration limits is [0, xC], which corresponds to the entire 1D transistor region. As a result of this choice, the electron quasifermi potentials in the numerator assume their known internal terminal values (e.g., for common-emitter configuration), wn (xl ) ¼ wn (0) ¼ 0 and

wn (xu ) ¼ wn (xC ) ¼ VC0 E0 ,

(A:3:14)

with VC0 E0 as (internal) collector–emitter voltage. The denominator integral is more difficult to oversee. Thus, Figure A.3.2 shows the spatial dependence of the weighting functions with the hole density superimposed. Since the hole quasifermi potential equals VB0 E0 over the entire base and adjacent space–charge regions, hw equals 1 where p(x) is significant. Similarly, the electron current density is constant and equals JT even in a larger interval, except in a small region close to the emitter contact, where it increases slightly due to the back injection of holes and the corresponding recombination; the maximum deviation can be 1/Bf. Therefore, without introducing a significant error, it is possible for both BJT and HBT to assume an average value for the functions hi and hw that is very close to 1. According to Figure A.3.2, the main spatial dependence of the weighting function h is caused by hg via the bandgap variation of ni. A smaller contribution to the spatial dependence comes from the doping and field dependence of the mobility.

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A.3-5

Integral Charge-Control Relations

1.2 hi h, p (normal.), hp (normal.)

1

p

hϕ, hi

0.8 hg 0.6 hg*p

0.4

0.2

0 0 xje

0.05 xjc

(a)

0.1 x (µm)

0.15

0.2

1.2 hi h, p (normal.), hp (normal.)

1 hϕ, hi 0.8 p hg

0.6

hg*p 0.4

0.2

0 (b)

0

xje

0.05

xjc

0.1 x (µm)

0.15

0.2

FIGURE A.3.2 Spatial dependence of the weighting functions for a CED transistor with the same doping profile: (a) 70 GHz BJT without Ge; (b) 120 GHz HBT with Ge. Bias point (JC ¼ JT,VB0 C0 ) ¼ (0.1 mA/mm2, 0 V). The hole density p, weighting function hg, and their product hgp have been normalized to the respective maximum value. xje and xjc denote the emitter and base junction depth.

Inserting (A.3.14) and hg from (A.3.12) into (A.3.13), extension by q as well as using average values hi and hw yields the basic formulation m n2 exp (VB0 E0 =VT ) exp (VB0 C0 =VT ) Ðx JT ¼ q2 VT nr ir : q 0 C hg pdx hi hw

(A:3:15)

from which practically relevant equations can be derived as shown later. The denominator is not yet suitable for (compact) modeling, but at this point can be prepared for further evaluation by partitioning it into a bias-independent and a bias-dependent portion

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A.3-6

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Fabrication of SiGe HBT BiCMOS Technology

ð xC q

hg pdx ¼ q

ð xC

0

hg p0 dx þ q

0

ð xC hg Dpdx,

(A:3:16)

0

where p0 is the hole density in equilibrium and Dp is the hole density change in the transistor with respect to equilibrium. Dp consists of depletion and minority components. While the latter density is distributed over the whole base region, the former densities are located around the junctions and related to the (ionized) base doping.

A.3.3

Homojunction Transistors

In homojunction transistors, the variation of hg is only caused by high-doping effects. Thus, hg is fairly constant in the region around the peak hole density (cf. Figure A.3.2a), which contributes most to the integral. Defining an average value 2

m n hg ¼ nr 2ir , mn ni

(A:3:17)

the denominator of (A.3.15) becomes ð xC q xE

mnr n2ir p p(x)dx ¼ hg Q mn n2i

(A:3:18)

with the hole charge per area stored in the 1D transistor structure, p ¼ q Q

ð xC p(x)dx:

(A:3:19)

0

Inserting (A.3.18) and (A.3.19) into (A.3.15) yields JT ¼ c

exp (VB0 E0 =VT ) exp (VB0 C0 =VT ) p Q

(A:3:20)

which has the same form as Gummel’s ICCR in Ref. [3], but a different definition of the integration region and, thus, of the charge and controlling voltages. The factor m n2ir c ¼ q2 VT nr ﬃ q2 VT mn n2i hi hw hg

(A:3:21)

is assumed to be constant over bias. Usually, the most right term is used only, which is obtained by setting hi ¼ hw ¼ 1 and is an excellent assumption for the 1D case. Since the hole density is concentrated mostly in the base, the value for hg and mn n2i is close to that for the base material. The charge in (A.3.19) can be divided into a bias-independent and a bias-dependent component, Q p ¼ Q p0 þ DQ p. The bias-independent charge Q p0 is defined at VB0 E0 ¼ VB0 C0 ¼ 0 and consists of holes stored mostly in the neutral base region 0 x 0 wB0 at equilibrium: p0 ¼ q Q

ð xC 0

p0 (x)dx ﬃ q

ð wB0 0

p0 (x 0 )dx 0 q

ð wB0

NB (x 0 )dx 0 :

(A:3:22)

0

(Note the use of a different coordinate x 0 in the neutral base region, cf. Figure A.3.1b.) The biasdependent charge component represents all holes, Dp, that for a nonequilibrium bias condition enter the

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Integral Charge-Control Relations

A.3-7

base region (i) to charge the depletion regions, (ii) to compensate the electrons injected into the (neutral) base, and (iii) for the injection into emitter and collector, p ¼ q DQ

ð xC

pE þ Q jE þ Q nB þ Q jC þ Q pC Dp(x)dx ¼ Q

(A:3:23)

0

Here, Q jE and QjC are the BE and BC depletion charge (per unit area), respectively, and the other components are the minority charges (per unit area) stored in E, B, and C. As a consequence of the choice of the chosen integration limits, DQp can actually be measured via the terminals. From a physicsbased point of view, the biggest advantage of the extended ICCR (A.3.20) is its firm link between the quasistatic transfer current and the total hole charge, which resembles the charge-controlled operation principle of a bipolar transistor in a very compact form. Examples for the accuracy of various solutions are shown in Figure A.3.3 for a typical Gummel plot. In all cases, the denominator integral (e.g. Q p in (A.3.20)) has been taken directly from device simulation. As expected, the basic Equation A.3.15 follows exactly the simulated behavior of JT (crosses). For the older generation profile (‘‘25 GHz transistor’’ in Figure A.3.3a), the practically interesting approximation (A.3.20) is very accurate at low and medium current densities, and shows only slight deviations at high current densities, which are tolerable though and typical for homo-junction bipolar processes (e.g. [6,7]). The reason for these small deviations is caused by the assumption of a biasindependent value for hg. However, if the minority charge contributions of emitter and collector, QpE and Q pC, are neglected in (A.3.20), the model current becomes far too large. Thus, including only the base charge is not a feasible approach. For the profile of a modern generation Si(Ge) transistor (‘‘70 GHz BJT’’ in Figure A.3.3b), Equation A.3.20 starts to deviate already at medium current densities, affecting the accuracy of the transconductance modeling. This is caused by the increased difference in doping and associated variation of hg across the base region, which requires a different weighting factor for Qp0 and QjE along the same lines as discussed in the next section on HBTs, applying the corresponding Equation A.3.28 gives again a much higher accuracy. The assumption of a bias-independent value for hg deserves some consideration. High-doping effects cause both ni and mn (which is also field dependent) to depend on x within the base region, with the change of ni partially being compensated by the change of mn. Obviously though, as long as the spatial distributions of p and mn n2i do not change with bias, hg remains bias independent. This holds quite well for low and medium current densities where p is concentrated in the base region, and the mobility depends only very slightly on bias. Toward high current densities, however, p spreads out into the collector and partially also into the emitter region. In the collector, for instance, high-doping effects can be neglected but the field (and thus bias) dependence of mn is significant, leading to a different weighting of the hole density in this region. As a consequence, the average value hg defined at low current densities is not quite correct anymore at high current densities and causes the observed small deviation from the exact current. Note though that the field dependence of the mobility around the BC junction decreases at high current densities. At this point, the choice of the integration limits shall be briefly discussed. Fundamentally, there is an infinite number of possible integration intervals. Besides the one selected above (i.e., entire 1D transistor), the other most important choice in literature (e.g., Refs. [3,4]) is the base region, i.e., x 2 [xjE,xjC]. In this case, hg is only a very weak function of bias, but there are serious disadvantages of this choice: (i) the unknown values for the electron quasi-fermi potentials at the base region boundaries, i.e., wn(xjE) and wn(xjC) in the numerator of (A.3.13), are not easily accessible by measurements; (ii) a separate determination (i.e., measurement) of the base hole charge, in particular the base minority charge, is difficult at medium to high current densities. The original and most famous expression of the ICCR as given by Gummel in Ref. [3], which has the same form as (A.3.20), is in fact based on considering only the base region for the integration and assuming contributions from outside that region to be negligible. Although this was a reasonable assumption at that time for the charge, it was not for the voltage drop toward the contacts.

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A.3-8

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Fabrication of SiGe HBT BiCMOS Technology

102

(a)

101

JC (mA/µm2)

100 10−1 X XX X X X X

10−2

XX X X X XX X 10−4 X XX XX 10−5 0.6 0.65 0.7 0.75

XXX XXX X X X XX XXXX XX X X X X X X XXXX XXXX X X X X X X X

10−3

0.8 0.85 VBE (V)

0.9

0.95

1

102

(b)

101

X

X X X

JC (mA/µm2)

100 10−1 10−2 10−3 10−4 10−5 0.6

0.65

0.7

0.75

0.8 0.85 VBE (V)

0.9

0.95

1

FIGURE A.3.3 Transfer current density for (a) 25 GHz BJT and (b) 70 GHz BJT: comparison between device simulation (symbols) and analytical calculations from Equation A.3.15 (solid line), Equation A.3.24 (dotted line), Equation A.3.20 (dashed line), as well as Equation A.3.20 without QpE þ QpC as dash-dotted line in (a) and Equation A.3.28 as dash-dotted line in (b). The arrow indicates the current density at which the fT peak occurs.

An often found further simplification is to replace the hole density in (A.3.19) by the base doping density NB. As a consequence, the hole charge equals the expression on the most r.h.s. of (A.3.22) and does not contain any bias-dependent ‘‘nonideal’’ effects anymore. Neglecting the voltage drops toward the contacts, Moll and Ross [1] first derived the corresponding expression for the transfer current JT ¼ qVT mnB n2iB

exp (VB0 E =VT ) exp (VB0 C0 =VT ) Ð WB 0 0 NB dx

(A:3:24)

This is a more general relation compared to the classical transistor theory along the lines of Ebers and Moll [9], and aided the understanding that the transfer current is linked to the integral of the base

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A.3-9

Integral Charge-Control Relations

doping and not to some spot value. As shown in Figure A.3.2, Equation A.3.24 produces an almost ideal characteristic due to the missing bias-dependent charge components.

A.3.4

Heterojunction Transistors

A comparison for the weighting function hg between a SiGe and a Si transistor with the same doping profile was already shown in Figure A.3.2. While the spatial dependence of the hole QFP and electron current density and, thus, of hw and hi is still similar to BJTs, the intentional bandgap differences in HBTs lead to additional variations of ni2 within the integration interval [0,xC]. As a consequence, it is impossible to define a single average value hg over this whole interval. Thus, the denominator integral in (A.3.15) now has to be formulated in terms of charge components in separate transistor regions that are multiplied with an average value of the weighting function hg taken over the respective region. In HBTs the transition from one bandgap value to another usually takes place close to the junctions. Therefore, Ðxc partitioning of the respective integral q hg pdx into neutral and space–charge regions is one reasonable 0

choice in order to obtain separate expressions, in which the weighting function is sufficiently independent on location and bias. This leads generally to ð xC q

p0 þ hg,E Q pE þ hg,jE Q jE þ hg,B Q nB þ hg,jC Q jC þ hg,C Q pC hg pdx ¼ hg,B0 Q

(A:3:25)

0 2

with

m n hg,v ¼ n0r ir mnv n2iv

and

v ¼ {B0, E, jE, B, jC, C}:

(A:3:26)

Choosing the base region as reference and assuming hg,B ¼ hg,B0, all weighting factors can be divided by hg,B giving for the normalized remaining weighting factors hg,v m n2 hv ¼ ¼ nB iB hg,B mnv n2iv

with

v ¼ {E, jE, jC, C},

(A:3:27)

which are considered to be model parameters. Inserting the above expression and charge components into (A.3.15), and making again the valid assumption hi ¼ hw ¼ 1 yields the GICCR as the final expression for 1D-HBTs [5] JT ¼ q2 VT mnB n2iB

exp (VB0 E0 =VT ) exp (VB0 C0 =VT ) p,T Q

(A:3:28)

with the modified (‘‘transfer current related’’) charge density p,T ¼ Q pE þ hjE Q jE þ Q jC þ hC Q pC , p0 þ DQ p,T ¼ Q p0 þ hE Q nB þ hjC Q Q

(A:3:29)

in which—as for BJTs—still a bias-independent hole charge, Qp0, and a bias-dependent portion can be distinguished. According to Refs. [5,8], and also as Figure A.3.4 shows, (A.3.28) with (A.3.29) using bias-independent values for hn leads to a significant improvement over the conventional ICCR (A.3.20). Thus, the GICCR results in an accurate description of the transfer current characteristics and the respective derivatives over the entire bias range of interest (up to high current densities). Again, as in Figure A.3.3, the charges and weighting factors have been calculated directly from device simulation results to avoid any errors introduced by analytical approximations. For ‘‘ideal’’ doping profiles like in Figure A.3.1, the weighting factors hn in (A.3.2) can be calculated analytically using (A.3.15). This aids the physical understanding of the impact of the Ge profile on device characteristics and shall be demonstrated below for two Ge profile examples. However, the calculation can be extended to other profiles but just becomes more elaborate.

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A.3-10

Fabrication of SiGe HBT BiCMOS Technology

101

JC (mA/µm2)

100

10−1

10−2

10−3 X X 0.6

X

X

X

X

X

0.65

X

X

X

X

X

0.7

X

X

X

X

X

X

XXXXXXXXXX XX XX XX XX

0.75 VBE (V)

0.8

0.85

FIGURE A.3.4 Transfer current density for the 120 GHz HBT: comparison between device simulation (symbols) and analytical calculations from Equation A.3.15 (solid line), Equation A.3.28 (dashed line), Equation A.3.24 (dotted line), and Equation A.3.28 without QpE þ QpC (dash-dotted line).

Box Ge Profile in the (Metallurgical) Base Region In this case, mn n2i is constant over the base region and the portion of the space–charge regions that are associated with the base. For the sake of simplicity, low injection is assumed first. Setting mnr n2ir ¼ mnB n2iB yields hg ¼ 1 already in the integral over the base region and, thus, hjE ¼ hjC ¼ 1. In the emitter and collector region, hE ¼ mnB n2iB =mnE n2iE >> 1 and hC ¼ mnB n2iB =mnC n2iC >> 1, respectively, due to the much larger bandgap in those regions. As a consequence of this bandgap, the hole charges Q pE and Q pC are very small and do not significantly impact the dynamic transistor behavior, regardless of the respective doping profile. However, according to (A.3.28) these charges can have a significant impact on the transfer current due to the large weighting factors hE and hC. The respective terms hE QpE and hC QpC in (A.3.28) actually cause the ‘‘saturation’’ of the IC(VBE) characteristics at high injection observed in Figure A.3.2b. In HBTs with a box Ge profile, Equation A.3.28 can be simplified to [5] exp (VB0 E0 =VT ) exp (VB0 C0 =VT ) JT ¼ q2 VT mnB n2iB pE þ (hC 1)Q pC , Qp þ (hE 1)Q

(A:3:30)

which contains the total hole charge as a lumped variable and correction factors in the denominator. In pC is described directly by a compact expression rather than separately by Ref. [8], the product (hC 1)Q the weighting factor and charge component.

Trapezoidal Profile in the (Metallurgical) Base Region Consider the Ge profile in Figure A.3.1b. For the sake of simplicity it is assumed that the Ge mole fraction mGe and the respective bandgap voltage increase over the width of the neutral base (x0 2 [xe0,xc0]) only, but stay constant across the space–charge regions. Choosing the Si-base without Ge contents as reference material, the bandgap voltage differences DVGp ¼ DVG(x0 ¼ xe0) and DVGx ¼ DVG(x0 ¼ xc0), respectively, can be defined. Hence, the intrinsic carrier density within the neutral base with the width wB0 ¼ xc0 xe0 can be written as

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A.3-11

Integral Charge-Control Relations

DVGp þ aG (x 0 xe0 ) n2i ¼ n2iB,Si exp VT

(A:3:31)

with the slope factor aG ¼ (DVGx DVGp)/wB0. Neglecting the (much smaller) dependence of the mobility on field and Ge contents, and applying the above relation to (A.3.16) with p0 ¼ NB yields for the bias-independent term xðC

q 0

mnr n2ir p0 dx 0 ﬃ q mn n2i

xðc0 xe0

DVGp þ aG (x 0 xe0 ) NB dx 0 exp VT

(A:3:32)

which gives after evaluating the r.h.s. integral xðC

q 0

mnr n2ir mn n2i

p0 dx 0 ﬃ

VT aG

h i DV Gx exp VTGp exp DV VT wB0

p0 ¼ hg,B0 Q p0 Q

(A:3:33)

p0 ¼ qNB wB0 . As can be seen, the average weighting factor depends exponentially on the bandgap with Q voltages at the beginning and the end of the neutral base. For the bias-dependent portion in (A.3.16), one can write at low current densities xðC

q

2 6 hg Dpdx ﬃ q4

xðe0 xe

0

exp

N B dx 0 þ DVGp VT

xðc xc0

xðjC

3

N n B dx 0 þ dx 0 7 5 ~xe0 ) DVGp þaG (x 0 n DVGx ~ exp n exp VT VT x

(A:3:34)

jE

The first two terms represent the depletion components that are only to be evaluated between the SCR boundary (i.e., xe, xc) at the given bias point and the respective equilibrium SCR boundaries (i.e., xe0, xc0); it also has been assumed that the bandgap (i.e., Ge mole) change within (xe0xe) and (xc0xc) is still jC ¼ qNB (xc xc0 ). For the case jE ¼ qNB (xe0 xe ) and Q negligible. The resulting depletion charges are Q that the electric field in the base due to Ge grading causes the electrons to travel with saturation drift velocity vs , i.e. n ¼ JT/(qvs) does not depend on x0 , the resulting base minority charge is then Q nB ¼ JT wB/vs. With these charge expressions, one obtains after evaluating all terms on the r.h.s. of (A.3.34) xðC

q 0

DVGp DVGx nB , QjE þ exp QjC þ hg,B0 Q hg Dpdx ﬃ exp VT VT

(A:3:35)

where the last term follows the same evaluation as (A.3.32). The final step is to insert the components in (A.3.33) and (A.3.35) back into (A.3.15) and to normalize the denominator to the base weighting factor, hgB0 given by Equation A.3.33. The resulting expression then reads mnB,Si n2iB,Si exp (VB0 E0 =VT ) exp (VB0 C0 =VT ) JT ¼ q2 VT jE þ hjC Q jC þ Q nB : p0 þ hjE Q hi hw hg ,B0 Q |ﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ{zﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄﬄ} c10

(A:3:36)

which has the same form as (A.3.28), but for low current densities and with known analytical expressions of the weighting factors from the above analysis: DV exp VTGp v exp (v) , hjE ¼ ¼ exp (v) 1 hg,B0

Gx exp DV VT v hjC ¼ : ¼ exp (v) 1 hg,B0

(A:3:37)

Cressler/Fabrication of SiGe HBT BiCMOS Technology

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A.3-12

Fabrication of SiGe HBT BiCMOS Technology

with v ¼ [DVGX DVGP]/VT as normalized bandgap difference between beginning and end of the base region (cf. Figure A.3.1b). The dependence of the weighting factors as a function of v is shown in Figure A.3.5 for a practically relevant range. From the above results, the forward Early voltage at low injection, can be calculated: VEf ¼

p p0 exp (v) 1 Q Q : v hjC CjCi CjCi

(A:3:38)

According to (A.3.37), a 20% difference in Ge across the base region corresponds to an about 40 times increase in Early voltage, which is a significant enhancement factor over a Si-BJT or a SiGe HBT with a Ge box profile (v ¼ 0). In addition to the strong variation in ni, the mobility varies within the transistor as a function of both doping and bias (via the electric field). The variation caused by the latter is most pronounced in the BC junction and collector region. In general, mn and ni possess an opposite dependence on doping, leading to a partial compensation within hg. However, the influence of ni still remains much stronger than that of mn. As a consequence, the weighting function hg always deviates strongly from 1 and has to be considered for all processes.

A.3.5

Further Extensions

All of the considerations so far apply to a 1D transistor structure and quasistatic operation. Extensions in both directions have been investigated and proposed. A solution of the time-dependent continuity equation led to the transient ICCR (TICC) [10], in which the ‘‘in-phase’’ component gives the same expression as the ICCR for the for q.s. transfer current, while the ‘‘out-of-phase’’ solution yields a physical definition of the charging currents flowing through the E and C contact. Hence, the out-ofphase solution defines a physics-based capacitance matrix associated with the E and C terminals, that includes the case of non-quasistatic operation. Extensions of the TICC towards including recombination and non-1D effects were presented in, for example, Ref. [11]. The application of the TICC results in a compact model, however, is quite challenging due to the bias-dependent weighting functions in the integrals defining the charging components.

6 5

hjE, hjC

4 hjE 3 2 1 hjC 0

0

1

2

3 v

4

5

6

FIGURE A.3.5 Weighting factors of the depletion charges according to Equation A.3.37 as a function of the normalized bandgap difference v ¼ (DVGx DVGp)/VT .

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A.3-13

Integral Charge-Control Relations

As shown in Ref. [7], it is possible to extend the GICCR to two- and three-dimensional transistor structures. The respective derivation is beyond the scope of this chapter, but the result shall be briefly discussed. For instance, the resulting 2D-GICCR reads h i Bcon ) exp (VB0 E0 =VT ) exp (VB0 C0 =VT 2(yBconbþb þ 2bbBcon E E , (A:3:39) IT ¼ c10 Qp0,T þ DQp,T where the constant c10 depends on an enlarged (effective) emitter width bE ¼ bE0 þ 2

ð yBcon bE0 =2

wn (x ¼ 0,y) dy: exp VT

(A:3:40)

bE0 is the emitter window width, yBcon is the edge of the base contact or polysilicon next to the emitter, and bBcon is the base contact or polysilicon width on mon-silicon. DQp,T is defined as in (A.3.29), but now includes, among others, the impact of electron current crowding. This also applies to Qp0,T, which introduces a bias-dependent geometry dependence at higher current densities. In practice, Qp0,T can be approximated by a constant value to first order.

A.3.6

Summary

A set of integral charge-control relations has been derived and put in perspective to the (classical) literature. It was shown that a ‘‘master’’ equation exists, from which integral charge-control relations of different complexity and accuracy can be derived. The most general form, that is suitable for accurately describing the transfer current in a compact model for HBTs and BJTs, is the GICCR, which includes bandgap differences in the various device regions and also contains the weakest assumptions among the known theories for the transfer current. The GICCR is a powerful tool to analytically derive the relationship between transfer current, stored charges, and physical as well as structural parameters of a transistor. The GICCR can be very accurate, provided that the respective weigthing factors as a function of device structure and the hole charge as a function of bias are accurately modeled. Notice that the latter is a prerequisite for the description of high-speed applications in any way. Also, since the hole charge has to be continuously differentiable with respect to bias, the transfer current is also automatically continuously differentiable over all bias regions and, hence, is modeled via a single-piece formulation. This is a very desirable feature of the (G)ICCR for compact models. Applying the ‘‘master’’ equation to compact modeling requires partitioning of the hole charge and analytical approximations for its various components. These measures as well as the determination of charge model parameters and appropriate weighting factor values introduce additional inaccuracies with respect to the results shown here, which are unavoidable though for any compact model equation.

Acknowledgment The author would like to thank H. Tran for performing simulations and model calculations.

References 1. J.L. Moll and J.M. Ross, The dependence of transistor parameters on the distribution of base layer resistivity, Proc. IRE, 44, 1956, S72–S78. 2. H.N. Ghosh, F.H. De La Moneda, and N.R. Dono, Computer-aided transistor design, characterization, and optimization, Proc. IEEE, 55, 1967, 1897–1912. 3. H.K. Gummel, A charge-control relation for bipolar transistors’’, Bell System Technical J., 49, 1970, S115–S120.

Cressler/Fabrication of SiGe HBT BiCMOS Technology

A.3-14

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Fabrication of SiGe HBT BiCMOS Technology

4. H. Kroemer, Two-Integral equations pertaining to the electron transport through a bipolar transistor with nonuniform energy gap in the base region, Solid-State Electron., 28, 1985, 1101–1103. 5. M. Schroter, M. Friedrich, and H.-M. Rein, A generalized integral charge-control relation and its application to compact models for silicon based HBTs, IEEE Trans. Electron Dev., 40, 1993, 2036– 2046. 6. H.-M. Rein, H. Stu¨bing, and M. Schroter, Verification of the integral charge-control relation for high-speed bipolar transistors at high current densities, IEEE Trans. Electron Dev., 32, 1985, 1070– 1076. 7. M. Schroter, A compact physical large-signal model for high-speed bipolar transistors with special regard to high current densities and two-dimensional effects, PhD thesis (in German), RuhrUniversity Bochum, Bochum, Germany, 1988. 8. M. Friedrich and H.-M. Rein, Analytical current–voltage relations for compact SiGe HBT models, IEEE Trans. Electron Dev., Vol. ED-46, 2001, 1384–1401. 9. J.J. Ebers and J.L. Moll, Large-signal behavior of junction transistors, Proc. IRE, 42, 1761–1772, 1954. 10. H. Klose and A. Wieder, The transient integral charge–control relation—a novel formulation of the currents in a bipolar transistor, IEEE Trans. Electron Dev., ED-34, 1090–1099, 1987. 11. J.S. Hamel and C.R. Selvakumar, The general transient charge–control relation: a new charge– control relation for semiconductor devices, IEEE Trans. Electron Dev., ED-38, 1467–1476, 1991.

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A.4 Sample SiGe HBT Compact Model Parameters

Ramana M. Malladi IBM Microelectronics

This appendix contains a sample set of compact model parameters for a representative 0.3216.8 mm2 first-generation npn SiGe HBT with a peak fT of 50 GHz, for each of the three dominant higher-order SiGe compact models available in the public domain and in leading circuit simulators: HICUM, MEXTRAM, and VBIC. Each model was carefully calibrated to a comprehensive set of measured dc and ac data.

A.4-1

Name c10 qp0 ich hjei hjci mcf hfe hfc ibeis mbei ibeps mbep ireis mrei ireps mrep ibcis mbci ibcxs mbcx ibets abet favl qavl rbi0 rbx fdqr0 fgeo fqi fcrbi re rcx iscs

Group

Transfer current

Base–emitter currents

Base–collector currents

Base–emitter tunnelling current

Base–collector avalanche current

Series resistances — base, emitter, and collector

Emitter

Collector

Substrate transistor

TABLE A.4.1 HICUM (v 2.1) SiGe HBT Model Parameters

CS diode saturation current

Extrinsic collector series resistance

Emitter series resistance

Internal base resistance at zero bias Extrinsic base resistance Correction factor for modulation by BE and BC SCR Geometry factor for current crowding Ratio of internal to total minority charge Ratio of shunt capacitance (parallel to Rbi) to total internal capacitance

Avalanche current factor Exponent for avalanche current

41021 A

23 V

3V

20 V 6V 0.2 0.67 1.0 0

19.3 V1 1501015 C

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11021 A 36

66870_A004 Final Proof

BE tunneling saturation current BE tunneling factor

A

A

A

A

1.51018 A 1.02 21019 A 2

71020 1.005 71022 1 11017 2 11020 2

8.51031 A2 S 1.41013 C 10 A 2 0.1 1 1 0.2

Value

A.4-2

Internal BC saturation current Internal BC saturation current ideality factor External BC saturation current External BC saturation current ideality factor

Internal BE sauration current Internal BE non-ideality factor Peripheral BE saturation current Peripheral BE non-ideality factor Internal BE saturation current (recombination) Internal BE non-ideality factor (recombination) Peripheral BE saturation current (recombination) Peripheral BE non-ideality factor (recombination)

Constant for ICCR (= Is.qp0) Zero-bias hole charge in the base High-current correction to account for 2D and 3D effects BE depletion charge weighting factor for HBTs BC depletion charge weighting factor for HBTs Forward nonideality factor for transfer current for HBTs Emitter minority charge weighting factor for HBTs Collector minority charge weighting factor for HBTs

Parameter Description

Cressler/Fabrication of SiGe HBT BiCMOS Technology 16.10.2007 7:06pm Compositor Name: JGanesan

Fabrication of SiGe HBT BiCMOS Technology

rsu csu rth cth cjei0 vdei zei aljei cjep0 vdep zep aljep ceox cjci0 vdci zci vptci cjcx0 vdcx zcx vptcx ccox fbc cjs0 vds zs vpts t0 dt0h tbvl tef0 gtfe

Substrate network

Self-heating

Base–emitter junction capacitance

Base–collector junction capacitance

Collector–substrate junction capacitance

Diffusion capacitances/transit times—low currents

High currents

msc itss msf msr tsf

(Continued)

401015 sec 1.0

Sample SiGe HBT Compact Model Parameters

Neutral emitter storage time Exponent for current dependence of neutral emitter storage time

2.61012 sec 0.91012 sec 0.71012 sec Low current forward transit time at Vcb ¼ 0 V Time constant for base and BC space charge layer width modulation Time constant for modeling carrier jam at low Vce

page 3

401015 F 0.6 V 0.3 11010 V

71015 F 0.7 V 0.3 2.5 V 301015 F 0.73 V 0.4 100 V 2.51015 F 0.8

351015 F 1.0 V 0.32 2.0 51015 F 1.0 V 0.32 2.2 181015 F

700 K/W 350 pJ/K

50 V (layout dependent) 31018 F

1 2.51019 A 1 1 21012 sec

66870_A004 Final Proof

Zero-bias CS depletion capacitance CS built-in voltage CS grading coefficient Punch-through voltage of CS junction

Internal zero-bias BC depletion capacitance Internal BC built-in voltage Internal BC grading coefficient Punch-through voltage of internal BC junction External zero-bias BC depletion capacitance External BC built-in voltage External BC grading coefficient Punch-through voltage of external BC junction BC overlap capacitance Partitioning factor for cjcx and ccox over rbx

Internal zero-bias BE depletion capacitance Internal BE built-in voltage Internal BE grading coefficient Maximum internal depletion capacitance divided by cjei0 Peripheral zero-bias BE depletion capacitance Peripheral BE built-in voltage Peripheral BE grading coefficient Maximum peripheral depletion capacitance divided by cjep0 Emitter oxide (overlap) capacitance

Thermal resistance Thermal capacitance

Substrate resistance Substrate capacitance

CS diode non-ideality factor Transfer saturation current of substrate transistor Forward non-ideality factor of substrate transfer current Reverse non-ideality factor of substrate transfer current Transit time (forward operation)—substrate

Cressler/Fabrication of SiGe HBT BiCMOS Technology 16.10.2007 7:06pm Compositor Name: JGanesan

A.4-3

Flicker noise factor Flicker noise exponent factor Noise factor for internal base resistance Measurement temperature Bandgap voltage Temperature coefficient of current gain Temperature coefficient of favl Temperature coefficient of qavl Temperature coefficient for mobility in epi-collector (i.e., for collector resitance) Relative temperature coefficient of saturation drift velocity Relative temperature coefficient of vces Temperature coefficient for mobility in internal base (i.e., for internal base resistance) Temperature coefficient for mobility in extrinsic base (i.e., for extrinsic base resistance) Temperature coefficient for mobility in extrinsic collector (i.e., for extrinsic collector resistance) Temperature coefficient for emitter resistance First-order temperature coefficient of t0 Second-order temperature coefficient of t0

kf af krbi tnom vgb alb alfav alqav zetaci alvs alces zetarbi zetarbx zetarcx zetare alt0 kt0

Noise parameters

Temperature effect parameters

Factor for additional delay time of minority charge Factor for additional delay time of transfer current

Saturation time constant at high current densities Smoothing factor for current dependence of base and collector transit time Factor for partitioning this into base and collector portion Internal C-E saturation voltage Internal collector resistance at low electric field Voltage separating ohmic (low field) and saturation velocity (high field) regime Collector punch-through voltage Storage time for inverse operation

thcs alhc fthc vces rci0 vlim vpt tr alqf alit

Parameter Description

Name

Non-quasistatic effects

Group

TABLE A.4.1 HICUM (v 2.1) SiGe HBT Model Parameters (Continued)

25 C 1.17 V 6103 5105 K1 2104 K1 1.6 1103 K1 0.4103 K1 0.6 0.2 0.2 0 1103 K1 1105 K2

22106 2.5 1

0.125 0.45

251012 sec 0.53 0.6 0.1 V 20 V 0.7 V 15 V 201012 sec

Value

Cressler/Fabrication of SiGe HBT BiCMOS Technology 66870_A004 Final Proof

A.4-4

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Fabrication of SiGe HBT BiCMOS Technology

Name is ik bf ibf mlf xibi bri ibr vlr xext ver vef wavl vavl sfh re rbc rbv rcc rcv scrcv ihc axi cje vde pe xcje cbeo cjc vdc pc xp

Group

Forward and reverse currents

Early voltage

Weak avalanche

Resistances and quasisaturation

Base–emitter junction capacitance

Base–collector junction capacitance

TABLE A.4.2 MEXTRAM 504 SiGe HBT Model Parameters

Zero–bias collector–base depletion capacitance Collector–base diffusion voltage Colector–base grading coefficient Constant part of cjc

Sample SiGe HBT Compact Model Parameters (Continued)

71015 F 0.75 V 0.28 1103

page 5

421015 F 0.9 V 0.23 0 181015 F

3.0 V 6V 20 V 17 V 52 V 54 V 3.56103 A 0.21

2.44107 M 0.63 V 1.7

4.8 V 65 V

51018 A 4.5102 A 95 21017 A 1.545 0 3.77 1.71015 A 1102 V 0.19

Value

66870_A004 Final Proof

Zero-bias emitter–base depletion capacitance Emitter–base diffusion voltage Emitter–base grading coefficient Fraction of the emitter–base depletion capacitance that belongs to the side-wall Emitter–base overlap capacitance

Emitter resistance Constant part of the base resistance Zer-bias value of the bias-dependent base resistance Constant part of the collector resistance Resistance of the un-modulated epilayer Space charge resistance of the epilayer Critical current for velocity saturation in the epilayer Smoothness parameter for the onset of quasi-saturation

Epilayer thickness used in weak-avalanche model Voltage determining curvature of avalanche current Current spreading factor of avalanche model (when exavl ¼ 1)

Reverse Early voltage Forward Early voltage

Transistor main saturation current Knee current for high-injection effects in the base Ideal forward current gain Saturation-current of the non-ideal forward base current Non-ideality factor of the non-ideal forward base current Sidewall component of ideal base current Ideal reverse current gain Saturation current of the non-ideal reverse base current Cross-over voltage of the non-ideal reverse base current Partitioning factor for the extrinsic region

Parameter Description

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A.4-5

Bandgap difference over the base Pre-factor of the recombination part of ideal base current Temperature coefficient of the zero-bias base charge Temperature coefficient of the resistivity of the emitter Temperature coefficient of the resistivity of the base Temperature coefficient of the resistivity of the epilayer Temperature coefficient of the resistivity of the extrinsic base Temperature coefficient of the resistivity of the buried layer Temperature coefficient for Iss and Iks (for a closed buried layer, as¼ac and for an open buried layer, as¼aepi) Bandgap voltage difference for forward current gain Bandgap voltage difference for reverse current gain Bandgap voltage of the base Bandgap voltage of the collector Bandgap voltage: recombination of the emitter–base junction Bandgap voltage difference of emitter stored charge Exponent of the flicker noise Flicker-noise coefficient of the ideal base current Flicker noise coefficient of the non-ideal base current Base-substrate saturation current Base-substrate high-injection knee current Thermal resistance Thermal capacitance

deg xrec aqbo ae ab aepi aex ac as dvgbf dvgbr vgb vgc vgj dvgte af kf kfn iss iks rth cth

HBT parameters

Temperature coeffcients

1/f Noise

Substrate transistor

Self-heating network

Diffusion capacitances/transit times

Zero-bias collector–substrate depletion capacitance Collector–substrate diffusion voltage Collector–substrate grading coefficient Bandgap voltage of the substrate Non-ideality factor for the emitter stored charge Minimum transit time of stored emitter charge Transit time of stored base charge Transit time of stored epilayer charge Transit time of reverse extrinsic stored base charge

Coefficient for the current modulation of the collector–base depletion capacitance Fraction of the collector–base depletion capacitance under the emitter Collector–base overlap capacitance

mc xcjc cbco cjs vds ps vgs mtau taue taub tepi taur

Parameter Description

Name

Collector–substrate junction capacitance

Group

TABLE A.4.2 MEXTRAM 504 SiGe HBT Model Parameters (Continued)

700 K/W 350 pJ/K

A.4-6

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2.51019 A 50 A

66870_A004 Final Proof

2.5 22106 201012

0.34 0 1.22 1.88 8.7107 1 0.76 3.75102 V 4.38102 V 1.15 V 1.18 V 1.15V 0.236 V

0.03 eV 0

451015 F 0.6 V 0.3 1.17 V 0.388 521015 sec 1.441012 sec 14.41012 sec 201012 sec

0.5 8.7102 2.51015 F

Value

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Fabrication of SiGe HBT BiCMOS Technology

Name is ibei iben ibci ibcn isp ibcip ibcnp ibeip ibenp nf nei nen nr nci ncn nfp ncip ncnp ikf ikr ikp avc1 avc2 rbi rbx rbp re rcx rs rth cth

Group

Saturation currents and ideality factors

Knee currents

Avalanche breakdown

Series resistances

Self-heating

TABLE A.4.3 VBIC SiGe HBT Model Parameters

Thermal resistance Thermal capacitance

Intrinsic base resistance Extrinsic base resistance Parasitic base resistance Emitter resistance Extrinsic collector resistance Substrate resistance

Sample SiGe HBT Compact Model Parameters (Continued)

700 K/W 350 pJ/W

20 V 6V 1V 3V 23 V 50 V

19.2 23.6 V

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Base–collector weak avalanche parameter 1 Base–collector weak avalanche parameter 2

4.5102 A 4.8103 A 10 A

11040 A 2.521018 A 11028 A 1.0003 1.026 2.5 1 1.02 1.00 1.00 1.00 2

4.851018 A 71020 A 11015 A 1.51018 A 11034 A 31019 A

Value

66870_A004 Final Proof

Forward knee current Reverse knee current Parasitic knee current

Transport saturation current (collector) Ideal base–emitter saturation current Nonideal base–emitter saturation current Ideal base–collector saturation current Nonideal base–collector saturation current Parasitic transport saturation current Ideal parasitic base–collector saturation current Nonideal parasitic base–collector saturation current Ideal parasitic base–emitter saturation current Nonideal parasitic base–emitter saturation current Forward emission coefficient Ideal base–emitter emission coefficient Nonideal base–emitter emission coefficient Reverse emission coefficient Ideal base–collector emission coefficient Nonideal base–collector emission coefficient Parasitic forwad emission coefficent Ideal parasitic base–collector emission coefficient Nonideal parasitic base–collector emission coefficient

Parameter Description

Cressler/Fabrication of SiGe HBT BiCMOS Technology 16.10.2007 7:06pm Compositor Name: JGanesan

A.4-7

Name rci vo gamm hrcf qco vef ver cje me pe cbeo fc aje cjc mc pc cbco cjep ajc cjcp ms ps ccso ajs tf itf vtf qtf td ea eaie eaic eais eanc

Group

Quasi-saturation parameters

Early effect parameters

Base–emitter junction capacitance

Base–collector junction capacitance

Collector–substrate junction capacitance

Transit times and their bias dependence

Temperature effect parameters

TABLE A.4.3 VBIC SiGe HBT Model Parameters (Continued)

Activation energy Activation energy Activation energy Activation energy Activation energy

for is for ibei for ibci and ibeip for ibcip for ibcn/ibenp

1.17 V 1.17 V 1.17 V 1.17 V 1.17 V

21012 sec 0.32 23.7 0 0.71012 sec

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Forward transit time Coefficient of tf dependence of ic Coefficient of tf dependence of Vbc Variation of tf with base-width modulation Forward excess-phase delay time

A.4-8

401015 F 0.3 0.6 V 3e18 F 0.9

71015 F 0.3 0.7 V 2.51015 F 301015 F 0.1

42 fF 1.0 0.3 V 181015 F 0.93 0.1

65 V 5.5 V

40 V 11010 V 51013 V 11013 1.41015

Value

66870_A004 Final Proof

Substrate–collector zero bias capacitance Substrate–collector grading coefficient Substrate–collector built-in potential Fixed collector–substrate capacitance Substrate–collector capacitance switching parameter

Base–collector intrinsic zero-bias capacitance Base–collector grading coefficient Base–collector built-in potential Extrinsic base–collector overlap capacitance Base–collector extrinsic zero bias capacitance Base–collector capacitance switching parameter

Base–emitter zero-bias capacitance Base–emitter grading coefficient Base–emitter built-in potential Extrinsic base–emitter overlap capacitance Forward bias depletion capacitance limit Base–emitter capacitance switching parameter

Forward Early voltage Reverse Early voltage

Intrinsic collector resistance Epi drift saturation voltage Epi doping parameter High-current RC factor Epi-charge parameter

Parameter Description

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Fabrication of SiGe HBT BiCMOS Technology

eane eans xii xin xis xre xrb xrc xrs xvo tavc Activation energy for iben Activation energy for ibcnp Temperature coefficient for ibei, ibci, ibeip, and ibcip Temperature coefficient for iben, ibcn, ibenp, and ibcnp Temperature coefficient for is Temperature coefficient for re Temperature coefficient for rbi Temperature coefficient for rc Temperature coefficient for rs Temperature coefficient for vo Temperature coefficient for avc2 1.17 V 1.17 V 2.0 2.0 1.9 0 0 0 0 0 250106 V

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Sample SiGe HBT Compact Model Parameters

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A.4-9

Cressler/Fabrication of SiGe HBT BiCMOS Technology

A.4-10

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Fabrication of SiGe HBT BiCMOS Technology

References 1. HICUM bipolar transistor model: http://www.iee.et.tu-dresden.de/iee/eb/comp_mod.html. 2. Mextram bipolar transistor model: http://www.semiconductors.phillips.com/acrobat/other/phillipsmodels/NLUR2000811_7.pdf. 3. VBIC bipolar transistor model: http://www.designers-guide.org/VBIC/references.html.

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Index A Active mixer, 10-12 Advanced CMOS process, lithography node integration of HBTs, 4-11 Advanced HBT structures and scaling limits, 4-11–4-14 Arsenic-doped monocrystalline emitters contact in, 10-2–10-3 epitaxially grown, 14-10–14-11 Asynchronous cross-point switch, 14-7 Automotive radar, high-frequency oscillators, 11-17–11-18 Avalanche multiplication factor (M-1), collector–base junction, 5-10

B Bandgap engineering, 1-3–1-4, 2-2–2-4, 4-1, 5-9, 5-36 Base-after-gate method (BAG), 7-1–7-2 Base-collector breakdown voltage, npn transistors, 10-9 Base-collector capacitance(CCB), 4-4, 4-8, 4-12, 5-6 Base-collector voltage, and transit frequency, 10-7 Base-emitter voltage parametric distribution, 7-13 Base sheet resistance, boron-doped base, 10-8 Base transit time, A.2-4 BEOL cumulative yield, 7-16 BiCMOS-6G E/B module insertion, 12-8 SiGe base, E/B dopant distribution in, 12-5–12-6 single-polysilicon QSA structure in, 12-2, 12-4 BiCMOS-7 boron spike width and base resistance, 12-6 high-frequency figures-of-merit and collector doping profile, 12-9–12-10 noise figure vs. collector current for, 12-11 RF applications of, 12-10 SiGe, carbon doping of, 12-4–12-5 SiGe:C process for, aim of, 12-5 single-polysilicon and double polysilicon QSA structure for, 12-4 transistor doping and impurity profiles for, 12-6

BiCMOS-9 monocrystalline structure of emitter in, 12-5 SiGe:C process for, 12-5 transistor doping and impurity profiles for, 12-6 BiCMOS process integration, 4-5–4-7 base-after-gate (BAG) method, 7-1–7-2 bipolar module, 7-2–7-3 CMOS protect layer, 7-3 emitter-base junction, 7-3 flows, base-before gate (BbG), 4-8, 4-9 intergration sequence in SiGe, 8-3 issues pMOS transistor integrity, 12-8 thermal cycle and structural integration issues, 12-6 metallization, 7-4 process flows, 8HP and 8WL, 7-2–7-4 VTsat vs. Idsat scatter plots, 7-12–7-13 BiCMOS-7RF base resistance reduction, 12-10 carbon doping of SiGe in, 12-4–12-5 high-frequency figures-of-merit of, 12-9 noise figure vs. collector current for, 12-11 transistor doping and impurity profiles in, 12-6 BiCMOS SiGe:C HBT process with lithographic steps, 11-12 Bipolar complementary metal oxide semiconductor (BiCMOS) technology, 1-2, 4-1 HBT parameters, 11-10 SiGe:C HBTs, 11-1 transit frequency (fT) and maximum oscillation frequency (fmax), 11-10 Bipolar fabrication process, 9-6–9-7 Bipolar structure non-self-aligned epitaxial base transistor epitaxial base bipolar structure, 4-4, 4-5–4-9 SEM of, 4-5 process, 4-2 self-aligned epitaxial base transistor, 4-4, 4-7–4-9 Bipolar transistors characteristics, 13-6 integration process, 6-2, 13-2 Boron spike, 10-7 BOX thickness, 13-2, 13-9, 13-10, 13-11 Breakdown voltage (BVCEO), 5-6, 5-11, 5-13

I-1

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66870_C015 Final Proof

I-2 Broadband amplifier, 10-12 Buried oxide, 5-2–5-4, 5-6, 5-11, 5-12 Buried sub-collector, 4-3

C Capacitors, integration, 6-3 CBiCMOS process flow, 10-11 C-doped Si properties, 11-3 Charging current (IC), 4-12 Chemical-mechanical polishing (CMP), 9-1 Chip area and transistor fabrication process, 6-1–6-2 CML ring oscillators gate delay, 10-10 gate delay vs. current for, 10-10–10-11 wafer map, 10-11 CMOS characteristics of, 13-8 compatible manufacturing process, 5-2 compatible SOI, 5-9–5-12 latch-up, 4-3 module, 13-4 processing steps, 7-2 protect layer, 7-3 technology, 4-1, 4-11 yield, 7-16 Code division multiple access (CDMA), 1-6 Collector–base junction capacitance (CCB), 5-2, 5-8, 5-11 Collector capacitance(CSC), 4-3 Collector current for pnp and npn HBTs, 10-10 Collector doping concentration, 8-5 Collector etching, 5-8 Collector resistance (RC), 4-3, 13-3 Collector sheet concentration, 9-7 Collector sinker, 7-7 Common emitter output characteristics, of npn transistors, 10-8 Complementary BiCMOS process flow, 10-11 Complementary bipolar module, ten mask steps, 11-12 Complementary-SiGe BiCMOS process, 13-1 Contact yield, 7-16 Conventional emitter doping (CED) transistors, A.3-3 Coplanar waveguides (CPW), inductors and capacitors, 6-2 Cost performance (CP), 4-2 Current-mode logic ring oscillators, see CML ring oscillators

D Deep-trench isolations (DTIs), 9-3 Depletion region, collector, 5-10, 5-11 Dielectric absorption, 13-5, 13-8 Dielectric layer, 4-5, 4-10 Differential epitaxy, 14-2

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Fabrication of SiGe HBT BiCMOS Technology Diodes, see p-i-n diodes Doped polysilicon sheet resistance, 6-3 Double-polysilicon with epitaxial base, 4-7 QSA structure, 12-4 self-aligned (DPSA) transistor, 4-7, 10-1, 10-2 DPSA HBTs, fabrication of, 10-1 DPSA structure with Pad oxide, 4-8 Drain junction capacitance, 5-1 Dual plateaus with an intermediately Ge-graded slope (DPIG), 9-4, 9-7 Dynamic frequency divider, 10-11–10-12

E E2CL circuit principle, 10-11 ECL-gate delay and self-aligned SEG SiGe HBTs, 9-6 switching current and, 9-5 Eddy currents, 6-7 Emitter-base structure fabrication steps emitter window formation, 10-3 nitride/oxide spacer formation, 10-4–10-5 SiGe base deposition process, 10-3 Emitter current (IE), 5-10 Emitter polysilicon, 13-4 Emitter resistance, 8-3, 8-5 polysilicon emitter transistors, 10-5 transistors with monocrystalline emitter, 10-6 Emitter window formation of, 10-3–10-4 mask width of, 10-5 epi growth, 4-4, 5-13 Epitaxial base layer development, 4-4 Epitaxial film, 13-2 ESD specifications, 4-3 Extrinsic base implants, self-aligning of, 8-3, 8-8

F Fabrication process layout optimization, 6-3 Ferromagnetic thin films, 6-11 FET mobility, 4-11 Flicker noise comparison, IFO thickness, 13-9

G Gate oxide logic FETs, 7-12 Ge effective mass parameters, A.1-2 energy band structure, A.1-1 properties of, A.1-2 Generalized ICCR (GICCR), A.3-2–A.3-6, A.3-13 Gilbert cell, 10-12 Global positioning systems (GPS), 1-6 Global system for mobile communications (GSM), 1-6 Graded SiGe base HBTs, 4-12

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I-3

Index Ground shield effect, 6-9 Gummel plot, 5-9 standard HBT, 14-5

collector current and cutoff frequencies, 9-7–9-8 transistor parameters of, 9-9 HV npn HBTs, RF characteristics of, 14-5

H

I

HBT fabricated in SGB25V process cross sections, 11-15 HBT fabrication process, SiGe layer deposition, 11-2 HBT models, Mextram 504 simulations, 14-6–14-7 HBT process, 4-4 HBT structures, SiGe self-aligned and non-self-aligned structures, 4-1 HBT types fabricated in SGB25V process transit frequency vs. collector current, 11-15 Heterojunction transistors, charge control relation, A.3-9–A.3-12 HICUM (v 2.1) SiGe HBT model parameters, A.4-2–A.4-4 High-density MIM capacitors, 7-3 High electron mobility transistors (HEMTs), 1-8 High-frequency characteristics for high-speed and high-voltage SiGe HBTs, 12-9–12-10 operation speed and breakdown voltage, 12-10 High-frequency npn transistor collector doping level, 10-9 High-frequency oscillator, circuit diagram, 11-17 High-frequency SiGe bipolar technologies, 10-1 arsenic-doped monocrystalline emitter contact, 10-2–10-3 boron-doped base layers, 10-2 High-performance benchmarking circuits, 11-16 High-performance BiCMOS process, LC oscillators fabricated in, 11-18 High-performance transmission lines, 14-6 High-quality passive elements, integration of, 7-3 High-resistivity silicon (HRS), substrate conductive loss reduction, 9-11 loss supression, 6-10 maximum quality factor, 6-8, 9-11 High-speed HBT integration issues CMOS dopant motion and etch steps, 12-7 dielectric layers, 12-7 pMOS transistor integrity, 12-8 High-speed monolithic integrated circuits (ICs), 9-1 Homojunction transistors, charge control relation, A.3-6–A.3-9 HP transistor AC performance of, 7-13 base–emitter voltage and emitter current for, 7-13 chain yield and senstivity of, 7-16 collector current, 7-7 frequency performance trend chart for, 7-15 HSHBT and HV-HBT breakdown voltage of, 9-7 collector capacitance, 9-9

Implanted and diffused resistors, RF circuit design, 6-3 Inductors coil design and interturn capacitance, 6-4–6-5, 6-7 eddy currents, 6-7 ground shield, effects of, 6-8 inductor mode and resonator mode, 6-7 optimization of, 6-8–6-9 planar substrate contact effect, 6-5 quality factor of, 6-4, 6-6 spiral inductor design, 6-4 substrate resistivity, 6-7–6-8 In-situ doped emitter, deposition of, 8-3, 8-8 In situ doped polysilicon emitters, 7-6 Integral charge-control relation (ICCR), A.3-2 for hetereojunction transistors, A.3-9–A.3-12 for homojunction transistors, A.3-6–A.3-9 Integrated inductor compact model of, 6-6 inductance and quality factor of, 6-6 maximum quality factor, inductance and resonant frequency of, 6-7 Integration process Buried layers, collector epitaxy, 13-2 collector sinkers, CMOS wells, 13-3 emitter modules, 13-4 lateral isolation, 13-3 metal-insulator-metal (MIM) capacitor, 13-5 starting material, 13-2–13-6 Intellectual property (IP), 4-1 Interconnection, of metal layers, 9-9 Interconnects, parasitic inductances, 6-1 Interdigitated capacitor, 6-3 Internal base sheet resistance (RSBi), 11-3 Intrinsic device structure, 8-3 Ion implantation boron, 9-6–9-7 germanium ions, 9-6–9-7, 9-9–9-10 phosphorus and antimony, 9-3, 9-7 ISM band, 11-16–11-17

J Junction transistor bipolar transistors on SOI substrate, 5-3 SiGe HBT and Si BJT, 4-11

K Kirk effect, 4-12, 4-14, 8-5–8-6 Kroemer’s approach, A.2-4

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Fabrication of SiGe HBT BiCMOS Technology

L

nMOS transistors, saturation current vs. threshold voltage for, 12-8 Nonselective epitaxial growth (NSEG), 10-1, 12-2 npn and pnp transistors characteristics, 13-7 Cross-section of, 13-3 solid lines, 13-7 npn HBT and pnp HBT cross section structure, 10-11 npn Transistors additional devices for, 10-10 base-collector breakdown voltage, 10-9 base resistance and emitter–base capacitance, 10-5 deep trench/shallow trench isolation, 10-2 fabrication sequence of, 10-3–10-5 SIMS doping profile of, 10-6 NPN yield, 7-16 nþ polysilicon emitter, 5-8 nþ reachthrough, 5-2, 5-3, 5-5, 5-7, 5-11, 5-12, 5-13 self-alignment of the LTE window, 5-13

Large-scale ICs (LSIs), 9-1 Lateral heat dissipation, 13-9 Lateral isolation, 13-3 Lateral scaling factor, 5-13 LC-VCOs center frequency of, 14-7 output spectrum of, 14-7 Lightly doped drain (LDD), 13-4 LOCOS effect, 4-10 Low-emitter concentration (LEC) transistors, A.3-3 Low-resistivity substrate (LRS), 9-11 Low-temperature epitaxy (LTE) process, 5-8 Lumped-element broadband amplifier data, 10-12

M Maximum electric field (EMAX), 5-6 MESFET switch, insertion loss and isolation of, 6-11 Metal–insulator–metal (MIM) capacitor, characteristics of, 11-3, 13-5, 13-8 Metal layers masks for, 9-9 multilayered structures, 9-9 Metallization, 8HP and 8WL, 7-4 Metal-oxide-silicon capacitors,capacitance/area of, 6-3 MEXTRAM 504 model parameters, A.4-5–A.4-6 Micromachining, 6-11 Microstrip lines, 4-2 MIM capacitor capacitance of, 6-4 dielectric MIM capacitor, 7-3–7-4 lumped-element model of, 6-3–6-4 metal layers, structure of, 9-9 optimization of, 7-3 quality factor of, 6-4, 9-10 specific capacitance of, 10-10 Moll–Ross collector current density relation, A.2-3 Moll-Ross relation assumptions for, A.2-1 generalized, A.2-2 Monocrystalline silicon emitter, emitter resistivity of, 14-12 Monolithic integrated broadband amplifier, 10-12 III-V monolithic microwave integrated circuit (MMIC) technology, 6-3 Moore’s law, 1-8 MOS capacitor, 5-3–5-5 MOS integration process, 13-2 MOS, passive parameter, 11-13 Mutual coupling, transformer, 6-9

N n- and p-buried layers (NBL and PBL), 13-2 Neutral base width, 4-14

O Ohmic losses of inductor coil, 6-5 On-chip antenna, 6-12 On-chip inductors inductance and capacitance values, 6-1 Oscillator spectrum single-ended, 11-18 Overlap capacitance (CCBOL), 4-12, 4-13

P Parasitic capacitance, 13-2, 13-10 Passive components capacitors, 6-3–6-4 chip integration concerns of, 6-1 diodes and switches, 6-10–6-11 inductors on silicon substrates, 6-4–6-9 integration of, 6-2 micromachining and MEMS, 6-11 on-chip antenna, 6-12 parameters of, 9-10–9-11 resistors, 6-3–6-4 transformers, 6-9–6-10 transmission lines, 6-10 Pattern density-loading effect, 4-8 p-i-n diodes as bias-controlled resistor, 6-11 integration of, 6-11 varactors, 6-10 pMOS transistors, saturation current vs. threshold voltage for, 12-8 pnp and npn HBT arrays, Gummel plots of, 11-12 pnp devices from a pnp-only BiCMOS, 10-10 pnp HBTs, 10-10, 10-12 Poly-buffered-LOCOS (PBL), 4-9 Poly-Si-assisted selfaligned SEG structure

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Q Quality factor, of RF capacitor, 6-3 Quasi-layer-on-layer fabrication of, 9-9 sheet resistance, 9-10 Quasiself-aligned HBT structure extrinsic base material, 12-2 single-polysilicon and double-polysilicon, 12-4 Quasi-TEM propagation modes, 4-2, 4-3 QUBiC4G process cross-point switch, jitter reduction, 12-7 process integration for HBT base layer deposition, 12-3 interconnect layers, 12-4 PMOS source–drain extensions, 12-4 subcollector implants, 12-3 QUBiC1 process, components of, 14-2 QUBiC process family, silicon BiCMOS integrated circuits characteristics of, 14-2 QUBiC4X process emitter structure in, 14-9 on-chip passive components for, 14-9 RF performance, 14-8 QUBiC4X standard HBT, 14-12–14-13

R Rapid-thermal anneal (RTA), 13-4 Rapid thermal chemical vapor deposition (RT-CVD, 8-9 RC time constants, 4-12 Reactive ion etching (RIE), 10-3 Resistors, integration of, 6-3 RF capacitor, figure-of-merit of, 6-3 RF circuit design inductance values, 6-8 junction isolation, 6-2, 6-3 parasitic effects suppression, 6-12 RF CMOS baseline, 11-10–11-11 RF switches, 6-11 Ring oscillator gate delay performance of CML ring oscillators, 10-10 wafer map of, 10-11

23.10.2007 12:26pm Compositor Name: JGanesan

I-5

Index poly-SiGe base contact growth, 9-3 Polysilicon emitter, 7-6 transistors interfacial oxide layer and, 10-5 Polysilicon gate, 13-3 Polysilicon growth, 5-7–5-8 Polysilicon resistors, 11-3, 13-4, 13-5 sheet resistance of, 10-9 shunt capacitance of, 6-3 Potential distributions, 5-3, 5-4, 5-11 pþ polysilicon layer, 5-6, 5-8 Precision resistors, characteristics of, 13-8

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S Sacrificial emitter extrinsic base implants, self-aligning of, 8-3, 8-8 Scaling techniques, lateral and vertical, 7-6–7-7 Scanning electron microscopy (SEM), 9-2 Selective epitaxial growth (SEG), 9-1 Selectively implanted collector breakdown voltages, 8-3 pþ extrinsic base and nþ buried layer, 8-6 Selectively implanted collector region, 9-3–9-4, 9-7 Self-aligned bipolar device, buried layer, 8-3 Self-aligned SEG SiGe HBT base multilayer, selective growth of, 9-2 collector sheet concentration, 9-7 DC characteristics of, 9-4 device structure and intrinsic impurity profile, optimization of, 9-6 fabrication of buried layer (BL), 9-3 CMOS and poly-Si resistor areas, 9-6–9-7 SEG layer, 9-4 I-V performance of, 9-7 SiGe SEG layer width optimization, 9-6 ultrahigh vacuum/chemical vapor deposition (UHV/CVD), 9-2–9-3 Self-aligned SiGe epitaxial base bipolar structure, 4-9 Self-alignment, base and emitter window base resistance, 11-7 Self-resonance, 6-3 SEM micrograph, SiGe HBT on silicon film SOI, 4-5, 4-10, 5-7 SGB25V HBT, passives parameters, 11-13 SGB25V process, flow and feature, 11-14 SGC25A-HBTs fabrication, 11-4 SGC25A process flow and features of, 11-5 HBT leakage currents, 11-4, 11-6 HBT parameters, 11-6 passives parameters of, 11-3, 11-4 SGC25B HBTs transit frequency vs. collector current for, 11-8 time components of, 11-8 SGC25C and CBiCMOS, density defect in, 10-12 SGC25C process with standard HBT module, flow, 11-7 SGC25C standard HBT emitter-base structure, 11-6 parameters of, 11-9 schematic cross sections of, 11-7 transit frequency vs. collector current for, 11-8 transit time components of, 11-8 Shallow-trench isolation (STI), 9-3 Sheet resistance of doped polysilicon, 6-3 in-line sheet resistance, 8-9 Shockley boundary condition, generelized, A.2-2, A.2-3

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Fabrication of SiGe HBT BiCMOS Technology

Si

Gummel characteristics of, 7-7 high-frequency performance of, 10-7 high-speed performance of, 10-1, 12-11 I–V performance of, 9-4 maximum oscillation frequency vs. collector current for, 10-7–10-8 nonselective epitaxy (NSEG), 12-2 output characteristics, 7-7, 7-9 process modules optimization, 7-5–7-6 technology generations, performance of, 1-9–1-10 transistor characteristics of, 9-5 transit time and parasitic reduction elements, 7-7 yield, 4-4 SiGe heterojunction bipolar transistors, structural processing features, 4-2 SiGe ICs applications, 1-7–1-8 SiGe layer components of, 9-3–9-4 Ge profile of, 9-4 SiGe npn transistor common emitter output characteristics of, 10-7–10-8 cut-off frequency vs. collector current for, 10-8 emitter resistance vs. effective emitter width, 10-6 high-volume CMOS infrastructure, reuse of, 8-9 intrinsic device structure, 8-3 lateral scaling of base-collector capacitance, 8-4–8-5 intrinsic base resistance, 8-7 unilateral gain, 8-5 maximum oscillation frequency vs. collector current for, 10-7–10-8 parasitic resistance and capacitance of, 8-3 performance of, 8-3–8-4 planar intrinsic to extrinsic base transition, 8-3 self-aligned, 8-2 transfer characteristics of, 10-7 transistor parameters of, 10-8–10-9 vertical scaling properties of, 8-4–8-5 SiGe SEG layer width optimization, 9-6 SiGe technologies, 11-1, 11-2 SiGe wireless transceiver, 1-8 Silicon-germanium base layer, epitaxial growth of, 5-2 Silicon-on-insulator (SOI) technology, 4-11, 5-1 Silicon RF integration and BiCMOS processes, 6-2 Silicon substrate eddy currents, effect of, 6-5 high-resistivity silicon (HRS), 6-8 of spiral inductor, 6-4 Silicon wafer, 4-2, 4-3 SIMS doping profile, 10-6 Single-polysilicon QSA structure, 12-4 Single-polysilicon transistors, 11-3 Si-strained layer epitaxy, 1-4 Skin effect, 1-2, 6-6 SOI BiCMOS integration circuit, 5-1, 5-5, 5-6 SOI bipolar transistor, verticle

effective mass parameters, A.1-2 energy band structure, A.1-1 properties of, A.1-2 Si-based high electron mobility transistors (HEMTs), 1-10 light emitters, 1-10 optoelectronic superchip, 1-10 transistor (s), 1-2, 1-9 SIC, see Selectively implanted collector SiGe alloys, 1-4, 2-1, 5-9, 8-8, 10-2, 12-3 SiGe-based device technology, 11-2 SiGe base deposition process, 10-3, 10-7 SiGe BiCMOS 8HP, 7-1 SiGe BiCMOS process integration sequence of, 8-8, 9-6–9-9 SiGe120, 8-11 technological features of, 12-1–12-2 SiGe BiCMOS (SiGe90) process current densities and parasitics, 8-10 inductor performance, 8-11 SiGe BiCMOS technologies, 7-1 performance curve of, 8-7 SiGe BiCMOS technology, AC performance, 7-15 SiGe buffer layers, 4-11 SiGe:C BiCMOS process, 11-12–11-14 SiGe:C HBTs in BiCMOS Technology high-speed and complementary, 10-9–10-12 peak fT/fmax values, 10-9–10-12 Transit frequency (fT) and maximum oscillation frequency (fmax), 10-9–10-12 SiGe:C HBT technologies, RF performance, 11-1, 11-2, 11-3 SiGe:C npn HBT, Gummel plot and output characteristics of, 14-11 SiGe:C technologies, circuit applications, 11-14 SiGe:C transistors, DC and RF parameters, 11-3 SiGe deposition, blanket scalable transistor geometries, 8-3 SiGe epitaxy process growth, 4-8, 4-14, 5-2 MBE, UHV/CVD and APCVD or RPCVD, 4-4 SiGe epi thickness, in-line measurement of, 8-9–8-10 SiGe fabrication facilities, 1-6 SiGe fabrication process, passive component and device structures, 6-2 SiGe HBT BiCMOS technology generations, 1-5, 1-9–1-10 SiGe HBT-CMOS technology, 5-2 SiGe HBTs breakdown voltage and transit frequency, relationship of, 7-8, 7-11 on CMOS-compatible SOI substrate, 5-6–5-8 collector current density of, 7-7 ECL gate-delay time, 9-5 frequency performance of, 7-6–7-12 fT versus IC curves for, 7-8, 7-10 graded Ge base profile, A.2-4

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I-7

Index collector characteristic of, 5-5, 5-12 lithographical and SOI thickness scaling, 5-13 SOI SiGe HBTs, 5-13 characteristics of, 5-8–5-12 DC characteristics of, 5-9 Source junction capacitance, 5-1 Spiral inductor design, 6-4 metal losses in, 6-6 modeling of, 6-8 width and spacing of, 9-10 SRAMs with a bit error count (BEC), wafer yield, 11-16 Stacked capacitor cross-section, 13-5 Stacked coils, 6-9–6-10 Standard HBT, see Standard heterojunction bipolar transistor Standard heterojunction bipolar transistor Collector-emitter breakdown voltage of, 14-11–14-12 Gummel plot of, 14-5 output characteristics for, 14-5–14-6 transition frequency for, 14-12–14-13 Static frequency divider, 10-11–10-12 Strained Si CMOS, 1-2, 1-6, 1-8–1-10, 2-11 Strained Si fabrication facilities, 1-6 ST SiGe BiCMOS technologies broadband applications of, 12-10–12-11 RF applications of, 12-10 SiGe and SiGe:C HBTs in, 12-2–12-3 Substrate resistivity, 4-2 Synchronous optical network (SONET), 1-6

T TaN metal resistor, 10-10 TaN resistor, 10-3 Thermal budget constraints, CMOS devices epi deposition, 8-8 optimization of, 8-9 Thermal resistance estimation, 13-9 Thin epitaxial base overetching prevention, 12-4 Thin-film resistor(TFR), 13-6 Thin NiCrAl resistor (TFR), 13-8 Thin oxide nFET characteristics and thin oxide pFET characteristics, 7-13 THz performance, 4-13–4-14 TiN-oxide-polycide capacitor, 13-5 Ti-salicide layers formation, 9-3–9-4 Transceiver circuits, amplitude shift keying (ASK) modulation, 11-15–11-17 Transformers, integrated spiral coils, 6-9 stacked, bifilar, and nested coil type of, 6-9–6-10 Transient ICCR (TICC), A.3-2 Transistor array, transfer characteristic of, 10-7

Transistor biasing, 5-8–5-9 Transistor fabrication process chip area and, 6-1–6-2 emitter-base fabrication steps, 10-3–10-4 Transistor fabrication, using Infineon’s SiGe technology common emitter output characteristics, 10-8 emitter-base configuration, 10-3–10-5 emitter resistance, 10-5–10-6 fabrication steps, 10-3–10-5 mask width, 10-5 monocrystalline emitter in, 10-6 oxide layer thickness, 10-5 parameters, 10-9 process concept, 10-2 SIMS doping profile, 10-6 TEM cross section, 10-2 transfer characteristics, 10-7 Transistor isolation, 10-2–10-3 Transistor parameters, 10-8–10-9 Transit frequency boron-doped base, 10-8 boron spike thickness, 10-7 and Ge profile of transistor, 10-6 of npn2 and npn3 transistor, 10-9 Transmission electron microscopy (TEM), 10-2 Transmission lines, 6-10 Triple well nFETs, 7-12

U UHV/CVD, see Ultrahigh vacuum/chemical vapor deposition Ultrahigh vacuum/chemical vapor deposition, 9-2–9-3

V Varactors collector base voltage and quality factor of, 9-10–9-11 optimization of, 7-3 VBIC SiGe HBT model parameters, A.4-7–A.4-9 Vertical bipolar transistors, on thin SOI, 5-2, 5-8 Voltage-controlled oscillators Voltage-controlled oscillators, output spectrum of, 14-9 Voltage feedback amplifier, characteristics of, 13-10, 13-11 Voltage pinning, of collector, 5-3, 5-5

W Wafers, minimum gate delay of, 10-11 Wet oxide etch, 10-3–10-4

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23.10.2007 12:26pm Compositor Name: JGanesan